1 /* 2 ****************************************************************************** 3 * @file lps28dfw_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lps28dfw_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2024 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LPS28DFW_REGS_H 23 #define LPS28DFW_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LPS28DFW 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LPS28DFW_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0xB9 if SA0=1 -> 0xBB **/ 172 #define LPS28DFW_I2C_ADD_L 0xB9U 173 #define LPS28DFW_I2C_ADD_H 0xBBU 174 175 /** Device Identification (Who am I) **/ 176 #define LPS28DFW_ID 0xB4U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LPS28DFW_INTERRUPT_CFG 0x0BU 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t phe : 1; 188 uint8_t ple : 1; 189 uint8_t lir : 1; 190 uint8_t not_used_01 : 1; 191 uint8_t reset_az : 1; 192 uint8_t autozero : 1; 193 uint8_t reset_arp : 1; 194 uint8_t autorefp : 1; 195 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 196 uint8_t autorefp : 1; 197 uint8_t reset_arp : 1; 198 uint8_t autozero : 1; 199 uint8_t reset_az : 1; 200 uint8_t not_used_01 : 1; 201 uint8_t lir : 1; 202 uint8_t ple : 1; 203 uint8_t phe : 1; 204 #endif /* DRV_BYTE_ORDER */ 205 } lps28dfw_interrupt_cfg_t; 206 207 #define LPS28DFW_THS_P_L 0x0CU 208 typedef struct 209 { 210 uint8_t ths : 8; 211 } lps28dfw_ths_p_l_t; 212 213 #define LPS28DFW_THS_P_H 0x0DU 214 typedef struct 215 { 216 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 217 uint8_t ths : 7; 218 uint8_t not_used_01 : 1; 219 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 220 uint8_t not_used_01 : 1; 221 uint8_t ths : 7; 222 #endif /* DRV_BYTE_ORDER */ 223 } lps28dfw_ths_p_h_t; 224 225 #define LPS28DFW_IF_CTRL 0x0EU 226 typedef struct 227 { 228 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 229 uint8_t not_used_01 : 2; 230 uint8_t int_pd_dis : 1; 231 uint8_t not_used_02 : 1; 232 uint8_t sda_pu_en : 1; 233 uint8_t not_used_03 : 2; 234 uint8_t int_en_i3c : 1; 235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 236 uint8_t int_en_i3c : 1; 237 uint8_t not_used_03 : 2; 238 uint8_t sda_pu_en : 1; 239 uint8_t not_used_02 : 1; 240 uint8_t int_pd_dis : 1; 241 uint8_t not_used_01 : 2; 242 #endif /* DRV_BYTE_ORDER */ 243 } lps28dfw_if_ctrl_t; 244 245 #define LPS28DFW_WHO_AM_I 0x0FU 246 #define LPS28DFW_CTRL_REG1 0x10U 247 typedef struct 248 { 249 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 250 uint8_t avg : 3; 251 uint8_t odr : 4; 252 uint8_t not_used_01 : 1; 253 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 254 uint8_t not_used_01 : 1; 255 uint8_t odr : 4; 256 uint8_t avg : 3; 257 #endif /* DRV_BYTE_ORDER */ 258 } lps28dfw_ctrl_reg1_t; 259 260 #define LPS28DFW_CTRL_REG2 0x11U 261 typedef struct 262 { 263 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 264 uint8_t oneshot : 1; 265 uint8_t not_used_01 : 1; 266 uint8_t swreset : 1; 267 uint8_t bdu : 1; 268 uint8_t en_lpfp : 1; 269 uint8_t lfpf_cfg : 1; 270 uint8_t fs_mode : 1; 271 uint8_t boot : 1; 272 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 273 uint8_t boot : 1; 274 uint8_t fs_mode : 1; 275 uint8_t lfpf_cfg : 1; 276 uint8_t en_lpfp : 1; 277 uint8_t bdu : 1; 278 uint8_t swreset : 1; 279 uint8_t not_used_01 : 1; 280 uint8_t oneshot : 1; 281 #endif /* DRV_BYTE_ORDER */ 282 } lps28dfw_ctrl_reg2_t; 283 284 #define LPS28DFW_CTRL_REG3 0x12U 285 typedef struct 286 { 287 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 288 uint8_t if_add_inc : 1; 289 uint8_t pp_od : 1; 290 uint8_t not_used_02 : 1; 291 uint8_t int_h_l : 1; 292 uint8_t not_used_01 : 4; 293 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 294 uint8_t not_used_01 : 4; 295 uint8_t int_h_l : 1; 296 uint8_t not_used_02 : 1; 297 uint8_t pp_od : 1; 298 uint8_t if_add_inc : 1; 299 #endif /* DRV_BYTE_ORDER */ 300 } lps28dfw_ctrl_reg3_t; 301 302 #define LPS28DFW_CTRL_REG4 0x13U 303 typedef struct 304 { 305 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 306 uint8_t int_f_ovr : 1; 307 uint8_t int_f_wtm : 1; 308 uint8_t int_f_full : 1; 309 uint8_t not_used_02 : 1; 310 uint8_t int_en : 1; 311 uint8_t drdy : 1; 312 uint8_t drdy_pls : 1; 313 uint8_t not_used_01 : 1; 314 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 315 uint8_t not_used_01 : 1; 316 uint8_t drdy_pls : 1; 317 uint8_t drdy : 1; 318 uint8_t int_en : 1; 319 uint8_t not_used_02 : 1; 320 uint8_t int_f_full : 1; 321 uint8_t int_f_wtm : 1; 322 uint8_t int_f_ovr : 1; 323 #endif /* DRV_BYTE_ORDER */ 324 } lps28dfw_ctrl_reg4_t; 325 326 #define LPS28DFW_FIFO_CTRL 0x14U 327 typedef struct 328 { 329 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 330 uint8_t f_mode : 2; 331 uint8_t trig_modes : 1; 332 uint8_t stop_on_wtm : 1; 333 uint8_t not_used_01 : 4; 334 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 335 uint8_t not_used_01 : 4; 336 uint8_t stop_on_wtm : 1; 337 uint8_t trig_modes : 1; 338 uint8_t f_mode : 2; 339 #endif /* DRV_BYTE_ORDER */ 340 } lps28dfw_fifo_ctrl_t; 341 342 #define LPS28DFW_FIFO_WTM 0x15U 343 typedef struct 344 { 345 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 346 uint8_t wtm : 7; 347 uint8_t not_used_01 : 1; 348 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 349 uint8_t not_used_01 : 1; 350 uint8_t wtm : 7; 351 #endif /* DRV_BYTE_ORDER */ 352 } lps28dfw_fifo_wtm_t; 353 354 #define LPS28DFW_REF_P_L 0x16U 355 typedef struct 356 { 357 uint8_t refp : 8; 358 } lps28dfw_ref_p_l_t; 359 360 #define LPS28DFW_REF_P_H 0x17U 361 typedef struct 362 { 363 uint8_t refp : 8; 364 } lps28dfw_ref_p_h_t; 365 366 #define LPS28DFW_I3C_IF_CTRL 0x19U 367 typedef struct 368 { 369 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 370 uint8_t I3C_Bus_Avb_Sel : 2; 371 uint8_t not_used_02 : 3; 372 uint8_t asf_on : 1; 373 uint8_t not_used_01 : 2; 374 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 375 uint8_t not_used_01 : 2; 376 uint8_t asf_on : 1; 377 uint8_t not_used_02 : 3; 378 uint8_t I3C_Bus_Avb_Sel : 2; 379 #endif /* DRV_BYTE_ORDER */ 380 } lps28dfw_i3c_if_ctrl_t; 381 382 #define LPS28DFW_RPDS_L 0x1AU 383 #define LPS28DFW_RPDS_H 0x1BU 384 #define LPS28DFW_INT_SOURCE 0x24U 385 typedef struct 386 { 387 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 388 uint8_t ph : 1; 389 uint8_t pl : 1; 390 uint8_t ia : 1; 391 uint8_t not_used_01 : 4; 392 uint8_t boot_on : 1; 393 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 394 uint8_t boot_on : 1; 395 uint8_t not_used_01 : 4; 396 uint8_t ia : 1; 397 uint8_t pl : 1; 398 uint8_t ph : 1; 399 #endif /* DRV_BYTE_ORDER */ 400 } lps28dfw_int_source_t; 401 402 #define LPS28DFW_FIFO_STATUS1 0x25U 403 typedef struct 404 { 405 uint8_t fss : 8; 406 } lps28dfw_fifo_status1_t; 407 408 #define LPS28DFW_FIFO_STATUS2 0x26U 409 typedef struct 410 { 411 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 412 uint8_t not_used_01 : 5; 413 uint8_t fifo_full_ia : 1; 414 uint8_t fifo_ovr_ia : 1; 415 uint8_t fifo_wtm_ia : 1; 416 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 417 uint8_t fifo_wtm_ia : 1; 418 uint8_t fifo_ovr_ia : 1; 419 uint8_t fifo_full_ia : 1; 420 uint8_t not_used_01 : 5; 421 #endif /* DRV_BYTE_ORDER */ 422 } lps28dfw_fifo_status2_t; 423 424 #define LPS28DFW_STATUS 0x27U 425 typedef struct 426 { 427 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 428 uint8_t p_da : 1; 429 uint8_t t_da : 1; 430 uint8_t not_used_01 : 2; 431 uint8_t p_or : 1; 432 uint8_t t_or : 1; 433 uint8_t not_used_02 : 2; 434 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 435 uint8_t not_used_02 : 2; 436 uint8_t t_or : 1; 437 uint8_t p_or : 1; 438 uint8_t not_used_01 : 2; 439 uint8_t t_da : 1; 440 uint8_t p_da : 1; 441 #endif /* DRV_BYTE_ORDER */ 442 } lps28dfw_status_t; 443 444 #define LPS28DFW_PRESS_OUT_XL 0x28U 445 #define LPS28DFW_PRESS_OUT_L 0x29U 446 #define LPS28DFW_PRESS_OUT_H 0x2AU 447 #define LPS28DFW_TEMP_OUT_L 0x2BU 448 #define LPS28DFW_TEMP_OUT_H 0x2CU 449 450 #define LPS28DFW_FIFO_DATA_OUT_PRESS_XL 0x78U 451 #define LPS28DFW_FIFO_DATA_OUT_PRESS_L 0x79U 452 #define LPS28DFW_FIFO_DATA_OUT_PRESS_H 0x7AU 453 454 /** 455 * @defgroup LPS28DFW_Register_Union 456 * @brief This union group all the registers that has a bitfield 457 * description. 458 * This union is useful but not need by the driver. 459 * 460 * REMOVING this union you are compliant with: 461 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 462 * 463 * @{ 464 * 465 */ 466 467 typedef union 468 { 469 lps28dfw_interrupt_cfg_t interrupt_cfg; 470 lps28dfw_ths_p_l_t ths_p_l; 471 lps28dfw_ths_p_h_t ths_p_h; 472 lps28dfw_if_ctrl_t if_ctrl; 473 lps28dfw_ctrl_reg1_t ctrl_reg1; 474 lps28dfw_ctrl_reg2_t ctrl_reg2; 475 lps28dfw_ctrl_reg3_t ctrl_reg3; 476 lps28dfw_ctrl_reg4_t ctrl_reg4; 477 lps28dfw_fifo_ctrl_t fifo_ctrl; 478 lps28dfw_fifo_wtm_t fifo_wtm; 479 lps28dfw_ref_p_l_t ref_p_l; 480 lps28dfw_ref_p_h_t ref_p_h; 481 lps28dfw_i3c_if_ctrl_t i3c_if_ctrl; 482 lps28dfw_int_source_t int_source; 483 lps28dfw_fifo_status1_t fifo_status1; 484 lps28dfw_fifo_status2_t fifo_status2; 485 lps28dfw_status_t status; 486 bitwise_t bitwise; 487 uint8_t byte; 488 } lps28dfw_reg_t; 489 490 #ifndef __weak 491 #define __weak __attribute__((weak)) 492 #endif /* __weak */ 493 494 /* 495 * These are the basic platform dependent I/O routines to read 496 * and write device registers connected on a standard bus. 497 * The driver keeps offering a default implementation based on function 498 * pointers to read/write routines for backward compatibility. 499 * The __weak directive allows the final application to overwrite 500 * them with a custom implementation. 501 */ 502 503 int32_t lps28dfw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 504 uint8_t *data, uint16_t len); 505 int32_t lps28dfw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 506 uint8_t *data, uint16_t len); 507 508 extern float_t lps28dfw_from_fs1260_to_hPa(int32_t lsb); 509 extern float_t lps28dfw_from_fs4060_to_hPa(int32_t lsb); 510 511 extern float_t lps28dfw_from_lsb_to_celsius(int16_t lsb); 512 513 typedef struct 514 { 515 uint8_t whoami; 516 } lps28dfw_id_t; 517 int32_t lps28dfw_id_get(const stmdev_ctx_t *ctx, lps28dfw_id_t *val); 518 519 typedef enum 520 { 521 LPS28DFW_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 522 LPS28DFW_INT_PIN_ON_I3C = 0x04, /* INT pin polarized as OUT with I3C */ 523 } lps28dfw_interface_t; 524 525 typedef enum 526 { 527 LPS28DFW_AUTO = 0x00, /* anti-spike filters managed by protocol */ 528 LPS28DFW_ALWAYS_ON = 0x01, /* anti-spike filters always on */ 529 } lps28dfw_filter_t; 530 531 typedef enum 532 { 533 LPS28DFW_BUS_AVB_TIME_50us = 0x00, /* bus available time equal to 50 us */ 534 LPS28DFW_BUS_AVB_TIME_2us = 0x01, /* bus available time equal to 2 us */ 535 LPS28DFW_BUS_AVB_TIME_1ms = 0x02, /* bus available time equal to 1 ms */ 536 LPS28DFW_BUS_AVB_TIME_25ms = 0x03, /* bus available time equal to 25 ms */ 537 } lps28dfw_bus_avb_time_t; 538 539 typedef struct 540 { 541 lps28dfw_interface_t interface; 542 lps28dfw_filter_t filter; 543 lps28dfw_bus_avb_time_t bus_avb_time; 544 } lps28dfw_bus_mode_t; 545 int32_t lps28dfw_bus_mode_set(const stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val); 546 int32_t lps28dfw_bus_mode_get(const stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val); 547 548 typedef enum 549 { 550 LPS28DFW_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 551 LPS28DFW_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 552 LPS28DFW_RESET = 0x02, /* Reset configuration registers */ 553 } lps28dfw_init_t; 554 int32_t lps28dfw_init_set(const stmdev_ctx_t *ctx, lps28dfw_init_t val); 555 556 typedef struct 557 { 558 uint8_t sw_reset : 1; /* Restoring configuration registers. */ 559 uint8_t boot : 1; /* Restoring calibration parameters. */ 560 uint8_t drdy_pres : 1; /* Pressure data ready. */ 561 uint8_t drdy_temp : 1; /* Temperature data ready. */ 562 uint8_t ovr_pres : 1; /* Pressure data overrun. */ 563 uint8_t ovr_temp : 1; /* Temperature data overrun. */ 564 uint8_t end_meas : 1; /* Single measurement is finished. */ 565 uint8_t ref_done : 1; /* Auto-Zero value is set. */ 566 } lps28dfw_stat_t; 567 int32_t lps28dfw_status_get(const stmdev_ctx_t *ctx, lps28dfw_stat_t *val); 568 569 typedef struct 570 { 571 uint8_t int_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 572 uint8_t int_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ 573 uint8_t sda_pull_up : 1; /* 1 = pull-up always disabled */ 574 } lps28dfw_pin_conf_t; 575 int32_t lps28dfw_pin_conf_set(const stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val); 576 int32_t lps28dfw_pin_conf_get(const stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val); 577 578 typedef struct 579 { 580 uint8_t drdy_pres : 1; /* Pressure data ready */ 581 uint8_t drdy_temp : 1; /* Temperature data ready */ 582 uint8_t over_pres : 1; /* Over pressure event */ 583 uint8_t under_pres : 1; /* Under pressure event */ 584 uint8_t thrsld_pres : 1; /* Over/Under pressure event */ 585 uint8_t fifo_full : 1; /* FIFO full */ 586 uint8_t fifo_ovr : 1; /* FIFO overrun */ 587 uint8_t fifo_th : 1; /* FIFO threshold reached */ 588 } lps28dfw_all_sources_t; 589 int32_t lps28dfw_all_sources_get(const stmdev_ctx_t *ctx, 590 lps28dfw_all_sources_t *val); 591 592 typedef enum 593 { 594 LPS28DFW_1260hPa = 0x00, 595 LPS28DFW_4060hPa = 0x01, 596 } lps28dfw_fs_t; 597 598 typedef enum 599 { 600 LPS28DFW_ONE_SHOT = 0x00, /* Device in power down till software trigger */ 601 LPS28DFW_1Hz = 0x01, 602 LPS28DFW_4Hz = 0x02, 603 LPS28DFW_10Hz = 0x03, 604 LPS28DFW_25Hz = 0x04, 605 LPS28DFW_50Hz = 0x05, 606 LPS28DFW_75Hz = 0x06, 607 LPS28DFW_100Hz = 0x07, 608 LPS28DFW_200Hz = 0x08, 609 } lps28dfw_odr_t; 610 611 typedef enum 612 { 613 LPS28DFW_4_AVG = 0, 614 LPS28DFW_8_AVG = 1, 615 LPS28DFW_16_AVG = 2, 616 LPS28DFW_32_AVG = 3, 617 LPS28DFW_64_AVG = 4, 618 LPS28DFW_128_AVG = 5, 619 LPS28DFW_256_AVG = 6, 620 LPS28DFW_512_AVG = 7, 621 } lps28dfw_avg_t; 622 623 typedef enum 624 { 625 LPS28DFW_LPF_DISABLE = 0, 626 LPS28DFW_LPF_ODR_DIV_4 = 1, 627 LPS28DFW_LPF_ODR_DIV_9 = 3, 628 } lps28dfw_lpf_t; 629 630 typedef struct 631 { 632 lps28dfw_fs_t fs; 633 lps28dfw_odr_t odr; 634 lps28dfw_avg_t avg; 635 lps28dfw_lpf_t lpf; 636 } lps28dfw_md_t; 637 int32_t lps28dfw_mode_set(const stmdev_ctx_t *ctx, lps28dfw_md_t *val); 638 int32_t lps28dfw_mode_get(const stmdev_ctx_t *ctx, lps28dfw_md_t *val); 639 640 int32_t lps28dfw_trigger_sw(const stmdev_ctx_t *ctx, lps28dfw_md_t *md); 641 642 typedef struct 643 { 644 struct 645 { 646 float_t hpa; 647 int32_t raw; /* 32 bit signed-left algned format left */ 648 } pressure; 649 struct 650 { 651 float_t deg_c; 652 int16_t raw; 653 } heat; 654 } lps28dfw_data_t; 655 int32_t lps28dfw_data_get(const stmdev_ctx_t *ctx, lps28dfw_md_t *md, 656 lps28dfw_data_t *data); 657 658 int32_t lps28dfw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); 659 int32_t lps28dfw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); 660 661 typedef enum 662 { 663 LPS28DFW_BYPASS = 0, 664 LPS28DFW_FIFO = 1, 665 LPS28DFW_STREAM = 2, 666 LPS28DFW_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ 667 LPS28DFW_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ 668 LPS28DFW_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ 669 } lps28dfw_operation_t; 670 671 typedef struct 672 { 673 lps28dfw_operation_t operation; 674 uint8_t watermark : 7; /* (0 disable) max 128.*/ 675 } lps28dfw_fifo_md_t; 676 int32_t lps28dfw_fifo_mode_set(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val); 677 int32_t lps28dfw_fifo_mode_get(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val); 678 679 int32_t lps28dfw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 680 681 typedef struct 682 { 683 float_t hpa; 684 int32_t raw; 685 } lps28dfw_fifo_data_t; 686 int32_t lps28dfw_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, 687 lps28dfw_md_t *md, lps28dfw_fifo_data_t *data); 688 689 typedef struct 690 { 691 uint8_t int_latched : 1; /* int events are: int on threshold, FIFO */ 692 uint8_t active_low : 1; /* 1 = active low / 0 = active high */ 693 uint8_t drdy_latched : 1; /* pulsed ~5 μs with enabled drdy_pres " */ 694 } lps28dfw_int_mode_t; 695 int32_t lps28dfw_interrupt_mode_set(const stmdev_ctx_t *ctx, 696 lps28dfw_int_mode_t *val); 697 int32_t lps28dfw_interrupt_mode_get(const stmdev_ctx_t *ctx, 698 lps28dfw_int_mode_t *val); 699 700 typedef struct 701 { 702 uint8_t drdy_pres : 1; /* Pressure data ready */ 703 uint8_t fifo_th : 1; /* FIFO threshold reached */ 704 uint8_t fifo_ovr : 1; /* FIFO overrun */ 705 uint8_t fifo_full : 1; /* FIFO full */ 706 } lps28dfw_pin_int_route_t; 707 int32_t lps28dfw_pin_int_route_set(const stmdev_ctx_t *ctx, 708 lps28dfw_pin_int_route_t *val); 709 int32_t lps28dfw_pin_int_route_get(const stmdev_ctx_t *ctx, 710 lps28dfw_pin_int_route_t *val); 711 712 typedef struct 713 { 714 uint16_t threshold; /* Threshold in hPa * 16 (@1260hPa) 715 * Threshold in hPa * 8 (@4060hPa) 716 */ 717 uint8_t over_th : 1; /* Pressure data over threshold event */ 718 uint8_t under_th : 1; /* Pressure data under threshold event */ 719 } lps28dfw_int_th_md_t; 720 int32_t lps28dfw_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, 721 lps28dfw_int_th_md_t *val); 722 int32_t lps28dfw_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, 723 lps28dfw_int_th_md_t *val); 724 725 typedef enum 726 { 727 LPS28DFW_OUT_AND_INTERRUPT = 0, 728 LPS28DFW_ONLY_INTERRUPT = 1, 729 LPS28DFW_RST_REFS = 2, 730 } lps28dfw_apply_ref_t; 731 732 typedef struct 733 { 734 lps28dfw_apply_ref_t apply_ref; 735 uint8_t get_ref : 1; /* Use current pressure value as reference */ 736 } lps28dfw_ref_md_t; 737 int32_t lps28dfw_reference_mode_set(const stmdev_ctx_t *ctx, 738 lps28dfw_ref_md_t *val); 739 int32_t lps28dfw_reference_mode_get(const stmdev_ctx_t *ctx, 740 lps28dfw_ref_md_t *val); 741 742 int32_t lps28dfw_refp_get(const stmdev_ctx_t *ctx, int16_t *val); 743 744 int32_t lps28dfw_opc_set(const stmdev_ctx_t *ctx, int16_t val); 745 int32_t lps28dfw_opc_get(const stmdev_ctx_t *ctx, int16_t *val); 746 747 /** 748 *@} 749 * 750 */ 751 752 #ifdef __cplusplus 753 } 754 #endif 755 756 #endif /* LPS28DFW_REGS_H */ 757 758 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 759
