1 /** 2 ****************************************************************************** 3 * @file lps27hhtw_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lps27hhtw_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LPS27HHTW_DRIVER_H 23 #define LPS27HHTW_DRIVER_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LPS27HHTW 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LPS27HHTW_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> B9 if SA0=1 -> BB **/ 172 #define LPS27HHTW_I2C_ADD_H 0xBBU 173 #define LPS27HHTW_I2C_ADD_L 0xB9U 174 175 /** Device Identification (Who am I) **/ 176 #define LPS27HHTW_ID 0xB3U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LPS27HHTW_INTERRUPT_CFG 0x0BU 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t pe : 2; /* ple + phe */ 188 uint8_t lir : 1; 189 uint8_t diff_en : 1; 190 uint8_t reset_az : 1; 191 uint8_t autozero : 1; 192 uint8_t reset_arp : 1; 193 uint8_t autorefp : 1; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t autorefp : 1; 196 uint8_t reset_arp : 1; 197 uint8_t autozero : 1; 198 uint8_t reset_az : 1; 199 uint8_t diff_en : 1; 200 uint8_t lir : 1; 201 uint8_t pe : 2; /* ple + phe */ 202 #endif /* DRV_BYTE_ORDER */ 203 } lps27hhtw_interrupt_cfg_t; 204 205 #define LPS27HHTW_THS_P_L 0x0CU 206 typedef struct 207 { 208 uint8_t ths : 8; 209 } lps27hhtw_ths_p_l_t; 210 211 #define LPS27HHTW_THS_P_H 0x0DU 212 typedef struct 213 { 214 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 215 uint8_t ths : 7; 216 uint8_t not_used_01 : 1; 217 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 218 uint8_t not_used_01 : 1; 219 uint8_t ths : 7; 220 #endif /* DRV_BYTE_ORDER */ 221 } lps27hhtw_ths_p_h_t; 222 223 #define LPS27HHTW_IF_CTRL 0x0EU 224 typedef struct 225 { 226 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 227 uint8_t i2c_disable : 1; 228 uint8_t i3c_disable : 1; 229 uint8_t pd_dis_int1 : 1; 230 uint8_t sdo_pu_en : 1; 231 uint8_t sda_pu_en : 1; 232 uint8_t not_used_01 : 2; 233 uint8_t int_en_i3c : 1; 234 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 235 uint8_t int_en_i3c : 1; 236 uint8_t not_used_01 : 2; 237 uint8_t sda_pu_en : 1; 238 uint8_t sdo_pu_en : 1; 239 uint8_t pd_dis_int1 : 1; 240 uint8_t i3c_disable : 1; 241 uint8_t i2c_disable : 1; 242 #endif /* DRV_BYTE_ORDER */ 243 } lps27hhtw_if_ctrl_t; 244 245 #define LPS27HHTW_WHO_AM_I 0x0FU 246 #define LPS27HHTW_CTRL_REG1 0x10U 247 typedef struct 248 { 249 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 250 uint8_t sim : 1; 251 uint8_t bdu : 1; 252 uint8_t lpfp_cfg : 2; /* en_lpfp + lpfp_cfg */ 253 uint8_t odr : 3; 254 uint8_t not_used_01 : 1; 255 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 256 uint8_t not_used_01 : 1; 257 uint8_t odr : 3; 258 uint8_t lpfp_cfg : 2; /* en_lpfp + lpfp_cfg */ 259 uint8_t bdu : 1; 260 uint8_t sim : 1; 261 #endif /* DRV_BYTE_ORDER */ 262 263 } lps27hhtw_ctrl_reg1_t; 264 265 #define LPS27HHTW_CTRL_REG2 0x11U 266 typedef struct 267 { 268 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 269 uint8_t one_shot : 1; 270 uint8_t low_noise_en : 1; 271 uint8_t swreset : 1; 272 uint8_t not_used_01 : 1; 273 uint8_t if_add_inc : 1; 274 uint8_t pp_od : 1; 275 uint8_t int_h_l : 1; 276 uint8_t boot : 1; 277 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 278 uint8_t boot : 1; 279 uint8_t int_h_l : 1; 280 uint8_t pp_od : 1; 281 uint8_t if_add_inc : 1; 282 uint8_t not_used_01 : 1; 283 uint8_t swreset : 1; 284 uint8_t low_noise_en : 1; 285 uint8_t one_shot : 1; 286 #endif /* DRV_BYTE_ORDER */ 287 288 } lps27hhtw_ctrl_reg2_t; 289 290 #define LPS27HHTW_CTRL_REG3 0x12U 291 typedef struct 292 { 293 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 294 uint8_t int_s : 2; 295 uint8_t drdy : 1; 296 uint8_t int_f_ovr : 1; 297 uint8_t int_f_wtm : 1; 298 uint8_t int_f_full : 1; 299 uint8_t not_used_01 : 2; 300 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 301 uint8_t not_used_01 : 2; 302 uint8_t int_f_full : 1; 303 uint8_t int_f_wtm : 1; 304 uint8_t int_f_ovr : 1; 305 uint8_t drdy : 1; 306 uint8_t int_s : 2; 307 #endif /* DRV_BYTE_ORDER */ 308 } lps27hhtw_ctrl_reg3_t; 309 310 #define LPS27HHTW_FIFO_CTRL 0x13U 311 typedef struct 312 { 313 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 314 uint8_t f_mode : 3; /* f_mode + trig_modes */ 315 uint8_t stop_on_wtm : 1; 316 uint8_t not_used_01 : 4; 317 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 318 uint8_t not_used_01 : 4; 319 uint8_t stop_on_wtm : 1; 320 uint8_t f_mode : 3; /* f_mode + trig_modes */ 321 #endif /* DRV_BYTE_ORDER */ 322 } lps27hhtw_fifo_ctrl_t; 323 324 #define LPS27HHTW_FIFO_WTM 0x14U 325 typedef struct 326 { 327 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 328 uint8_t wtm : 7; 329 uint8_t not_used_01 : 1; 330 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 331 uint8_t not_used_01 : 1; 332 uint8_t wtm : 7; 333 #endif /* DRV_BYTE_ORDER */ 334 } lps27hhtw_fifo_wtm_t; 335 336 #define LPS27HHTW_REF_P_L 0x15U 337 #define LPS27HHTW_REF_P_H 0x16U 338 #define LPS27HHTW_RPDS_L 0x18U 339 #define LPS27HHTW_RPDS_H 0x19U 340 #define LPS27HHTW_INT_SOURCE 0x24U 341 typedef struct 342 { 343 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 344 uint8_t ph : 1; 345 uint8_t pl : 1; 346 uint8_t ia : 1; 347 uint8_t not_used_01 : 4; 348 uint8_t boot_on : 1; 349 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 350 uint8_t boot_on : 1; 351 uint8_t not_used_01 : 4; 352 uint8_t ia : 1; 353 uint8_t pl : 1; 354 uint8_t ph : 1; 355 #endif /* DRV_BYTE_ORDER */ 356 } lps27hhtw_int_source_t; 357 358 #define LPS27HHTW_FIFO_STATUS1 0x25U 359 #define LPS27HHTW_FIFO_STATUS2 0x26U 360 typedef struct 361 { 362 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 363 uint8_t not_used_01 : 5; 364 uint8_t fifo_full_ia : 1; 365 uint8_t fifo_ovr_ia : 1; 366 uint8_t fifo_wtm_ia : 1; 367 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 368 uint8_t fifo_wtm_ia : 1; 369 uint8_t fifo_ovr_ia : 1; 370 uint8_t fifo_full_ia : 1; 371 uint8_t not_used_01 : 5; 372 #endif /* DRV_BYTE_ORDER */ 373 } lps27hhtw_fifo_status2_t; 374 375 #define LPS27HHTW_STATUS 0x27U 376 typedef struct 377 { 378 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 379 uint8_t p_da : 1; 380 uint8_t t_da : 1; 381 uint8_t not_used_01 : 2; 382 uint8_t p_or : 1; 383 uint8_t t_or : 1; 384 uint8_t not_used_02 : 2; 385 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 386 uint8_t not_used_02 : 2; 387 uint8_t t_or : 1; 388 uint8_t p_or : 1; 389 uint8_t not_used_01 : 2; 390 uint8_t t_da : 1; 391 uint8_t p_da : 1; 392 #endif /* DRV_BYTE_ORDER */ 393 } lps27hhtw_status_t; 394 395 #define LPS27HHTW_PRESS_OUT_XL 0x28U 396 #define LPS27HHTW_PRESS_OUT_L 0x29U 397 #define LPS27HHTW_PRESS_OUT_H 0x2AU 398 #define LPS27HHTW_TEMP_OUT_L 0x2BU 399 #define LPS27HHTW_TEMP_OUT_H 0x2CU 400 #define LPS27HHTW_FIFO_DATA_OUT_PRESS_XL 0x78U 401 #define LPS27HHTW_FIFO_DATA_OUT_PRESS_L 0x79U 402 #define LPS27HHTW_FIFO_DATA_OUT_PRESS_H 0x7AU 403 #define LPS27HHTW_FIFO_DATA_OUT_TEMP_L 0x7BU 404 #define LPS27HHTW_FIFO_DATA_OUT_TEMP_H 0x7CU 405 406 /** 407 * @defgroup LPS27HHTW_Register_Union 408 * @brief This union group all the registers having a bit-field 409 * description. 410 * This union is useful but it's not needed by the driver. 411 * 412 * REMOVING this union you are compliant with: 413 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 414 * 415 * @{ 416 * 417 */ 418 typedef union 419 { 420 lps27hhtw_interrupt_cfg_t interrupt_cfg; 421 lps27hhtw_if_ctrl_t if_ctrl; 422 lps27hhtw_ctrl_reg1_t ctrl_reg1; 423 lps27hhtw_ctrl_reg2_t ctrl_reg2; 424 lps27hhtw_ctrl_reg3_t ctrl_reg3; 425 lps27hhtw_fifo_ctrl_t fifo_ctrl; 426 lps27hhtw_fifo_wtm_t fifo_wtm; 427 lps27hhtw_int_source_t int_source; 428 lps27hhtw_fifo_status2_t fifo_status2; 429 lps27hhtw_status_t status; 430 bitwise_t bitwise; 431 uint8_t byte; 432 } lps27hhtw_reg_t; 433 434 /** 435 * @} 436 * 437 */ 438 439 #ifndef __weak 440 #define __weak __attribute__((weak)) 441 #endif /* __weak */ 442 443 /* 444 * These are the basic platform dependent I/O routines to read 445 * and write device registers connected on a standard bus. 446 * The driver keeps offering a default implementation based on function 447 * pointers to read/write routines for backward compatibility. 448 * The __weak directive allows the final application to overwrite 449 * them with a custom implementation. 450 */ 451 452 int32_t lps27hhtw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 453 uint8_t *data, 454 uint16_t len); 455 int32_t lps27hhtw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 456 uint8_t *data, 457 uint16_t len); 458 459 float_t lps27hhtw_from_lsb_to_hpa(int32_t lsb); 460 461 float_t lps27hhtw_from_lsb_to_celsius(int16_t lsb); 462 463 int32_t lps27hhtw_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val); 464 int32_t lps27hhtw_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); 465 466 int32_t lps27hhtw_autozero_set(const stmdev_ctx_t *ctx, uint8_t val); 467 int32_t lps27hhtw_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val); 468 469 int32_t lps27hhtw_pressure_snap_rst_set(const stmdev_ctx_t *ctx, 470 uint8_t val); 471 int32_t lps27hhtw_pressure_snap_rst_get(const stmdev_ctx_t *ctx, 472 uint8_t *val); 473 474 int32_t lps27hhtw_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val); 475 int32_t lps27hhtw_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val); 476 477 int32_t lps27hhtw_block_data_update_set(const stmdev_ctx_t *ctx, 478 uint8_t val); 479 int32_t lps27hhtw_block_data_update_get(const stmdev_ctx_t *ctx, 480 uint8_t *val); 481 482 typedef enum 483 { 484 LPS27HHTW_POWER_DOWN = 0x00, 485 LPS27HHTW_ONE_SHOOT = 0x08, 486 LPS27HHTW_1_Hz = 0x01, 487 LPS27HHTW_10_Hz = 0x02, 488 LPS27HHTW_25_Hz = 0x03, 489 LPS27HHTW_50_Hz = 0x04, 490 LPS27HHTW_75_Hz = 0x05, 491 LPS27HHTW_1_Hz_LOW_NOISE = 0x11, 492 LPS27HHTW_10_Hz_LOW_NOISE = 0x12, 493 LPS27HHTW_25_Hz_LOW_NOISE = 0x13, 494 LPS27HHTW_50_Hz_LOW_NOISE = 0x14, 495 LPS27HHTW_75_Hz_LOW_NOISE = 0x15, 496 LPS27HHTW_100_Hz = 0x06, 497 LPS27HHTW_200_Hz = 0x07, 498 } lps27hhtw_odr_t; 499 int32_t lps27hhtw_data_rate_set(const stmdev_ctx_t *ctx, 500 lps27hhtw_odr_t val); 501 int32_t lps27hhtw_data_rate_get(const stmdev_ctx_t *ctx, 502 lps27hhtw_odr_t *val); 503 504 int32_t lps27hhtw_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val); 505 int32_t lps27hhtw_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val); 506 507 int32_t lps27hhtw_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val); 508 int32_t lps27hhtw_pressure_offset_get(const stmdev_ctx_t *ctx, 509 int16_t *val); 510 511 typedef struct 512 { 513 lps27hhtw_int_source_t int_source; 514 lps27hhtw_fifo_status2_t fifo_status2; 515 lps27hhtw_status_t status; 516 } lps27hhtw_all_sources_t; 517 int32_t lps27hhtw_all_sources_get(const stmdev_ctx_t *ctx, 518 lps27hhtw_all_sources_t *val); 519 520 int32_t lps27hhtw_status_reg_get(const stmdev_ctx_t *ctx, 521 lps27hhtw_status_t *val); 522 523 int32_t lps27hhtw_press_flag_data_ready_get(const stmdev_ctx_t *ctx, 524 uint8_t *val); 525 526 int32_t lps27hhtw_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 527 uint8_t *val); 528 529 int32_t lps27hhtw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); 530 531 int32_t lps27hhtw_temperature_raw_get(const stmdev_ctx_t *ctx, 532 int16_t *buff); 533 534 int32_t lps27hhtw_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, 535 uint32_t *buff); 536 537 int32_t lps27hhtw_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, 538 int16_t *buff); 539 540 int32_t lps27hhtw_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 541 542 int32_t lps27hhtw_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 543 int32_t lps27hhtw_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 544 545 int32_t lps27hhtw_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 546 int32_t lps27hhtw_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 547 548 int32_t lps27hhtw_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 549 int32_t lps27hhtw_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 550 551 typedef enum 552 { 553 LPS27HHTW_LPF_ODR_DIV_2 = 0, 554 LPS27HHTW_LPF_ODR_DIV_9 = 2, 555 LPS27HHTW_LPF_ODR_DIV_20 = 3, 556 } lps27hhtw_lpfp_cfg_t; 557 int32_t lps27hhtw_lp_bandwidth_set(const stmdev_ctx_t *ctx, 558 lps27hhtw_lpfp_cfg_t val); 559 int32_t lps27hhtw_lp_bandwidth_get(const stmdev_ctx_t *ctx, 560 lps27hhtw_lpfp_cfg_t *val); 561 562 typedef enum 563 { 564 LPS27HHTW_I2C_ENABLE = 0, 565 LPS27HHTW_I2C_DISABLE = 1, 566 } lps27hhtw_i2c_disable_t; 567 int32_t lps27hhtw_i2c_interface_set(const stmdev_ctx_t *ctx, 568 lps27hhtw_i2c_disable_t val); 569 int32_t lps27hhtw_i2c_interface_get(const stmdev_ctx_t *ctx, 570 lps27hhtw_i2c_disable_t *val); 571 572 typedef enum 573 { 574 LPS27HHTW_I3C_ENABLE = 0x00, 575 LPS27HHTW_I3C_ENABLE_INT_PIN_ENABLE = 0x10, 576 LPS27HHTW_I3C_DISABLE = 0x11, 577 } lps27hhtw_i3c_disable_t; 578 int32_t lps27hhtw_i3c_interface_set(const stmdev_ctx_t *ctx, 579 lps27hhtw_i3c_disable_t val); 580 int32_t lps27hhtw_i3c_interface_get(const stmdev_ctx_t *ctx, 581 lps27hhtw_i3c_disable_t *val); 582 583 typedef enum 584 { 585 LPS27HHTW_PULL_UP_DISCONNECT = 0, 586 LPS27HHTW_PULL_UP_CONNECT = 1, 587 } lps27hhtw_pu_en_t; 588 int32_t lps27hhtw_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 589 lps27hhtw_pu_en_t val); 590 int32_t lps27hhtw_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 591 lps27hhtw_pu_en_t *val); 592 int32_t lps27hhtw_sda_mode_set(const stmdev_ctx_t *ctx, 593 lps27hhtw_pu_en_t val); 594 int32_t lps27hhtw_sda_mode_get(const stmdev_ctx_t *ctx, 595 lps27hhtw_pu_en_t *val); 596 597 typedef enum 598 { 599 LPS27HHTW_SPI_4_WIRE = 0, 600 LPS27HHTW_SPI_3_WIRE = 1, 601 } lps27hhtw_sim_t; 602 int32_t lps27hhtw_spi_mode_set(const stmdev_ctx_t *ctx, 603 lps27hhtw_sim_t val); 604 int32_t lps27hhtw_spi_mode_get(const stmdev_ctx_t *ctx, 605 lps27hhtw_sim_t *val); 606 607 typedef enum 608 { 609 LPS27HHTW_INT_PULSED = 0, 610 LPS27HHTW_INT_LATCHED = 1, 611 } lps27hhtw_lir_t; 612 int32_t lps27hhtw_int_notification_set(const stmdev_ctx_t *ctx, 613 lps27hhtw_lir_t val); 614 int32_t lps27hhtw_int_notification_get(const stmdev_ctx_t *ctx, 615 lps27hhtw_lir_t *val); 616 617 typedef enum 618 { 619 LPS27HHTW_PUSH_PULL = 0, 620 LPS27HHTW_OPEN_DRAIN = 1, 621 } lps27hhtw_pp_od_t; 622 int32_t lps27hhtw_pin_mode_set(const stmdev_ctx_t *ctx, 623 lps27hhtw_pp_od_t val); 624 int32_t lps27hhtw_pin_mode_get(const stmdev_ctx_t *ctx, 625 lps27hhtw_pp_od_t *val); 626 627 typedef enum 628 { 629 LPS27HHTW_ACTIVE_HIGH = 0, 630 LPS27HHTW_ACTIVE_LOW = 1, 631 } lps27hhtw_int_h_l_t; 632 int32_t lps27hhtw_pin_polarity_set(const stmdev_ctx_t *ctx, 633 lps27hhtw_int_h_l_t val); 634 int32_t lps27hhtw_pin_polarity_get(const stmdev_ctx_t *ctx, 635 lps27hhtw_int_h_l_t *val); 636 637 int32_t lps27hhtw_pin_int_route_set(const stmdev_ctx_t *ctx, 638 lps27hhtw_ctrl_reg3_t *val); 639 int32_t lps27hhtw_pin_int_route_get(const stmdev_ctx_t *ctx, 640 lps27hhtw_ctrl_reg3_t *val); 641 642 typedef enum 643 { 644 LPS27HHTW_NO_THRESHOLD = 0, 645 LPS27HHTW_POSITIVE = 1, 646 LPS27HHTW_NEGATIVE = 2, 647 LPS27HHTW_BOTH = 3, 648 } lps27hhtw_pe_t; 649 int32_t lps27hhtw_int_on_threshold_set(const stmdev_ctx_t *ctx, 650 lps27hhtw_pe_t val); 651 int32_t lps27hhtw_int_on_threshold_get(const stmdev_ctx_t *ctx, 652 lps27hhtw_pe_t *val); 653 654 int32_t lps27hhtw_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff); 655 int32_t lps27hhtw_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff); 656 657 typedef enum 658 { 659 LPS27HHTW_BYPASS_MODE = 0, 660 LPS27HHTW_FIFO_MODE = 1, 661 LPS27HHTW_STREAM_MODE = 2, 662 LPS27HHTW_DYNAMIC_STREAM_MODE = 3, 663 LPS27HHTW_BYPASS_TO_FIFO_MODE = 5, 664 LPS27HHTW_BYPASS_TO_STREAM_MODE = 6, 665 LPS27HHTW_STREAM_TO_FIFO_MODE = 7, 666 } lps27hhtw_f_mode_t; 667 int32_t lps27hhtw_fifo_mode_set(const stmdev_ctx_t *ctx, 668 lps27hhtw_f_mode_t val); 669 int32_t lps27hhtw_fifo_mode_get(const stmdev_ctx_t *ctx, 670 lps27hhtw_f_mode_t *val); 671 672 int32_t lps27hhtw_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, 673 uint8_t val); 674 int32_t lps27hhtw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, 675 uint8_t *val); 676 677 int32_t lps27hhtw_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 678 int32_t lps27hhtw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 679 680 int32_t lps27hhtw_fifo_data_level_get(const stmdev_ctx_t *ctx, 681 uint8_t *buff); 682 683 int32_t lps27hhtw_fifo_src_get(const stmdev_ctx_t *ctx, 684 lps27hhtw_fifo_status2_t *val); 685 686 int32_t lps27hhtw_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 687 688 int32_t lps27hhtw_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 689 690 int32_t lps27hhtw_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 691 692 int32_t lps27hhtw_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); 693 int32_t lps27hhtw_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, 694 uint8_t *val); 695 696 int32_t lps27hhtw_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, 697 uint8_t val); 698 int32_t lps27hhtw_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, 699 uint8_t *val); 700 701 int32_t lps27hhtw_fifo_full_on_int_set(const stmdev_ctx_t *ctx, 702 uint8_t val); 703 int32_t lps27hhtw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, 704 uint8_t *val); 705 706 /** 707 * @} 708 * 709 */ 710 711 #ifdef __cplusplus 712 } 713 #endif 714 715 #endif /*LPS27HHTW_REGS_H */ 716 717 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 718
