1 /** 2 ****************************************************************************** 3 * @file lps25hb_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lps25hb_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LPS25HB_REGS_H 23 #define LPS25HB_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LPS25HB 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 71 /** @defgroup STMicroelectronics sensors common types 72 * @{ 73 * 74 */ 75 76 #ifndef MEMS_SHARED_TYPES 77 #define MEMS_SHARED_TYPES 78 79 typedef struct 80 { 81 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 82 uint8_t bit0 : 1; 83 uint8_t bit1 : 1; 84 uint8_t bit2 : 1; 85 uint8_t bit3 : 1; 86 uint8_t bit4 : 1; 87 uint8_t bit5 : 1; 88 uint8_t bit6 : 1; 89 uint8_t bit7 : 1; 90 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 91 uint8_t bit7 : 1; 92 uint8_t bit6 : 1; 93 uint8_t bit5 : 1; 94 uint8_t bit4 : 1; 95 uint8_t bit3 : 1; 96 uint8_t bit2 : 1; 97 uint8_t bit1 : 1; 98 uint8_t bit0 : 1; 99 #endif /* DRV_BYTE_ORDER */ 100 } bitwise_t; 101 102 #define PROPERTY_DISABLE (0U) 103 #define PROPERTY_ENABLE (1U) 104 105 /** @addtogroup Interfaces_Functions 106 * @brief This section provide a set of functions used to read and 107 * write a generic register of the device. 108 * MANDATORY: return 0 -> no Error. 109 * @{ 110 * 111 */ 112 113 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 114 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 115 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 116 117 typedef struct 118 { 119 /** Component mandatory fields **/ 120 stmdev_write_ptr write_reg; 121 stmdev_read_ptr read_reg; 122 /** Component optional fields **/ 123 stmdev_mdelay_ptr mdelay; 124 /** Customizable optional pointer **/ 125 void *handle; 126 } stmdev_ctx_t; 127 128 /** 129 * @} 130 * 131 */ 132 133 #endif /* MEMS_SHARED_TYPES */ 134 135 #ifndef MEMS_UCF_SHARED_TYPES 136 #define MEMS_UCF_SHARED_TYPES 137 138 /** @defgroup Generic address-data structure definition 139 * @brief This structure is useful to load a predefined configuration 140 * of a sensor. 141 * You can create a sensor configuration by your own or using 142 * Unico / Unicleo tools available on STMicroelectronics 143 * web site. 144 * 145 * @{ 146 * 147 */ 148 149 typedef struct 150 { 151 uint8_t address; 152 uint8_t data; 153 } ucf_line_t; 154 155 /** 156 * @} 157 * 158 */ 159 160 #endif /* MEMS_UCF_SHARED_TYPES */ 161 162 /** 163 * @} 164 * 165 */ 166 167 /** @defgroup LPS25HB_Infos 168 * @{ 169 * 170 */ 171 172 /** I2C Device Address 8 bit format if SA0=0 -> B9 if SA0=1 -> BB **/ 173 #define LPS25HB_I2C_ADD_L 0xB9U 174 #define LPS25HB_I2C_ADD_H 0xBBU 175 176 /** Device Identification (Who am I) **/ 177 #define LPS25HB_ID 0xBDU 178 179 /** 180 * @} 181 * 182 */ 183 184 #define LPS25HB_REF_P_XL 0x08U 185 #define LPS25HB_REF_P_L 0x09U 186 #define LPS25HB_REF_P_H 0x0AU 187 #define LPS25HB_WHO_AM_I 0x0FU 188 #define LPS25HB_RES_CONF 0x10U 189 typedef struct 190 { 191 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 192 uint8_t avgp : 2; 193 uint8_t avgt : 2; 194 uint8_t not_used_01 : 4; 195 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 196 uint8_t not_used_01 : 4; 197 uint8_t avgt : 2; 198 uint8_t avgp : 2; 199 #endif /* DRV_BYTE_ORDER */ 200 } lps25hb_res_conf_t; 201 202 #define LPS25HB_CTRL_REG1 0x20U 203 typedef struct 204 { 205 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 206 uint8_t sim : 1; 207 uint8_t reset_az : 1; 208 uint8_t bdu : 1; 209 uint8_t diff_en : 1; 210 uint8_t odr : 4; /* pd + odr -> odr */ 211 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 212 uint8_t odr : 4; /* pd + odr -> odr */ 213 uint8_t diff_en : 1; 214 uint8_t bdu : 1; 215 uint8_t reset_az : 1; 216 uint8_t sim : 1; 217 #endif /* DRV_BYTE_ORDER */ 218 } lps25hb_ctrl_reg1_t; 219 220 #define LPS25HB_CTRL_REG2 0x21U 221 typedef struct 222 { 223 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 224 uint8_t one_shot : 1; 225 uint8_t autozero : 1; 226 uint8_t swreset : 1; 227 uint8_t i2c_dis : 1; 228 uint8_t fifo_mean_dec : 1; 229 uint8_t stop_on_fth : 1; 230 uint8_t fifo_en : 1; 231 uint8_t boot : 1; 232 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 233 uint8_t boot : 1; 234 uint8_t fifo_en : 1; 235 uint8_t stop_on_fth : 1; 236 uint8_t fifo_mean_dec : 1; 237 uint8_t i2c_dis : 1; 238 uint8_t swreset : 1; 239 uint8_t autozero : 1; 240 uint8_t one_shot : 1; 241 #endif /* DRV_BYTE_ORDER */ 242 } lps25hb_ctrl_reg2_t; 243 244 #define LPS25HB_CTRL_REG3 0x22U 245 typedef struct 246 { 247 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 248 uint8_t int_s : 2; 249 uint8_t not_used_01 : 4; 250 uint8_t pp_od : 1; 251 uint8_t int_h_l : 1; 252 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 253 uint8_t int_h_l : 1; 254 uint8_t pp_od : 1; 255 uint8_t not_used_01 : 4; 256 uint8_t int_s : 2; 257 #endif /* DRV_BYTE_ORDER */ 258 } lps25hb_ctrl_reg3_t; 259 260 #define LPS25HB_CTRL_REG4 0x23U 261 typedef struct 262 { 263 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 264 uint8_t drdy : 1; 265 uint8_t f_ovr : 1; 266 uint8_t f_fth : 1; 267 uint8_t f_empty : 1; 268 uint8_t not_used_01 : 4; 269 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 270 uint8_t not_used_01 : 4; 271 uint8_t f_empty : 1; 272 uint8_t f_fth : 1; 273 uint8_t f_ovr : 1; 274 uint8_t drdy : 1; 275 #endif /* DRV_BYTE_ORDER */ 276 } lps25hb_ctrl_reg4_t; 277 278 #define LPS25HB_INTERRUPT_CFG 0x24U 279 typedef struct 280 { 281 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 282 uint8_t pe : 2; /* pl_e + ph_e -> pe */ 283 uint8_t lir : 1; 284 uint8_t not_used_01 : 5; 285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 286 uint8_t not_used_01 : 5; 287 uint8_t lir : 1; 288 uint8_t pe : 2; /* pl_e + ph_e -> pe */ 289 #endif /* DRV_BYTE_ORDER */ 290 } lps25hb_interrupt_cfg_t; 291 292 #define LPS25HB_INT_SOURCE 0x25U 293 typedef struct 294 { 295 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 296 uint8_t ph : 1; 297 uint8_t pl : 1; 298 uint8_t ia : 1; 299 uint8_t not_used_01 : 5; 300 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 301 uint8_t not_used_01 : 5; 302 uint8_t ia : 1; 303 uint8_t pl : 1; 304 uint8_t ph : 1; 305 #endif /* DRV_BYTE_ORDER */ 306 } lps25hb_int_source_t; 307 308 #define LPS25HB_STATUS_REG 0x27U 309 typedef struct 310 { 311 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 312 uint8_t t_da : 1; 313 uint8_t p_da : 1; 314 uint8_t not_used_01 : 2; 315 uint8_t t_or : 1; 316 uint8_t p_or : 1; 317 uint8_t not_used_02 : 2; 318 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 319 uint8_t not_used_02 : 2; 320 uint8_t p_or : 1; 321 uint8_t t_or : 1; 322 uint8_t not_used_01 : 2; 323 uint8_t p_da : 1; 324 uint8_t t_da : 1; 325 #endif /* DRV_BYTE_ORDER */ 326 } lps25hb_status_reg_t; 327 328 #define LPS25HB_PRESS_OUT_XL 0x28U 329 #define LPS25HB_PRESS_OUT_L 0x29U 330 #define LPS25HB_PRESS_OUT_H 0x2AU 331 #define LPS25HB_TEMP_OUT_L 0x2BU 332 #define LPS25HB_TEMP_OUT_H 0x2CU 333 #define LPS25HB_FIFO_CTRL 0x2EU 334 typedef struct 335 { 336 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 337 uint8_t wtm_point : 5; 338 uint8_t f_mode : 3; 339 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 340 uint8_t f_mode : 3; 341 uint8_t wtm_point : 5; 342 #endif /* DRV_BYTE_ORDER */ 343 } lps25hb_fifo_ctrl_t; 344 345 #define LPS25HB_FIFO_STATUS 0x2FU 346 typedef struct 347 { 348 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 349 uint8_t fss : 5; 350 uint8_t empty_fifo : 1; 351 uint8_t ovr : 1; 352 uint8_t fth_fifo : 1; 353 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 354 uint8_t fth_fifo : 1; 355 uint8_t ovr : 1; 356 uint8_t empty_fifo : 1; 357 uint8_t fss : 5; 358 #endif /* DRV_BYTE_ORDER */ 359 } lps25hb_fifo_status_t; 360 361 #define LPS25HB_THS_P_L 0x30U 362 #define LPS25HB_THS_P_H 0x31U 363 #define LPS25HB_RPDS_L 0x39U 364 #define LPS25HB_RPDS_H 0x3AU 365 366 /** 367 * @defgroup LPS25HB_Register_Union 368 * @brief This union group all the registers having a bit-field 369 * description. 370 * This union is useful but it's not needed by the driver. 371 * 372 * REMOVING this union you are compliant with: 373 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 374 * 375 * @{ 376 * 377 */ 378 typedef union 379 { 380 lps25hb_res_conf_t res_conf; 381 lps25hb_ctrl_reg1_t ctrl_reg1; 382 lps25hb_ctrl_reg2_t ctrl_reg2; 383 lps25hb_ctrl_reg3_t ctrl_reg3; 384 lps25hb_ctrl_reg4_t ctrl_reg4; 385 lps25hb_interrupt_cfg_t interrupt_cfg; 386 lps25hb_int_source_t int_source; 387 lps25hb_status_reg_t status_reg; 388 lps25hb_fifo_ctrl_t fifo_ctrl; 389 lps25hb_fifo_status_t fifo_status; 390 bitwise_t bitwise; 391 uint8_t byte; 392 } lps25hb_reg_t; 393 394 /** 395 * @} 396 * 397 */ 398 399 #ifndef __weak 400 #define __weak __attribute__((weak)) 401 #endif /* __weak */ 402 403 /* 404 * These are the basic platform dependent I/O routines to read 405 * and write device registers connected on a standard bus. 406 * The driver keeps offering a default implementation based on function 407 * pointers to read/write routines for backward compatibility. 408 * The __weak directive allows the final application to overwrite 409 * them with a custom implementation. 410 */ 411 412 int32_t lps25hb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 413 uint8_t *data, 414 uint16_t len); 415 int32_t lps25hb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 416 uint8_t *data, 417 uint16_t len); 418 419 float_t lps25hb_from_lsb_to_hpa(uint32_t lsb); 420 421 float_t lps25hb_from_lsb_to_degc(int16_t lsb); 422 423 int32_t lps25hb_pressure_ref_set(const stmdev_ctx_t *ctx, int32_t val); 424 int32_t lps25hb_pressure_ref_get(const stmdev_ctx_t *ctx, int32_t *val); 425 426 typedef enum 427 { 428 LPS25HB_P_AVG_8 = 0, 429 LPS25HB_P_AVG_16 = 1, 430 LPS25HB_P_AVG_32 = 2, 431 LPS25HB_P_AVG_64 = 3, 432 } lps25hb_avgp_t; 433 int32_t lps25hb_pressure_avg_set(const stmdev_ctx_t *ctx, 434 lps25hb_avgp_t val); 435 int32_t lps25hb_pressure_avg_get(const stmdev_ctx_t *ctx, 436 lps25hb_avgp_t *val); 437 438 typedef enum 439 { 440 LPS25HB_T_AVG_8 = 0, 441 LPS25HB_T_AVG_16 = 1, 442 LPS25HB_T_AVG_32 = 2, 443 LPS25HB_T_AVG_64 = 3, 444 } lps25hb_avgt_t; 445 int32_t lps25hb_temperature_avg_set(const stmdev_ctx_t *ctx, 446 lps25hb_avgt_t val); 447 int32_t lps25hb_temperature_avg_get(const stmdev_ctx_t *ctx, 448 lps25hb_avgt_t *val); 449 450 int32_t lps25hb_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val); 451 int32_t lps25hb_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); 452 453 int32_t lps25hb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 454 int32_t lps25hb_block_data_update_get(const stmdev_ctx_t *ctx, 455 uint8_t *val); 456 457 typedef enum 458 { 459 LPS25HB_POWER_DOWN = 0, 460 LPS25HB_ODR_1Hz = 9, 461 LPS25HB_ODR_7Hz = 10, 462 LPS25HB_ODR_12Hz5 = 11, 463 LPS25HB_ODR_25Hz = 12, 464 LPS25HB_ONE_SHOT = 8, 465 } lps25hb_odr_t; 466 int32_t lps25hb_data_rate_set(const stmdev_ctx_t *ctx, lps25hb_odr_t val); 467 int32_t lps25hb_data_rate_get(const stmdev_ctx_t *ctx, lps25hb_odr_t *val); 468 469 int32_t lps25hb_one_shoot_trigger_set(const stmdev_ctx_t *ctx, uint8_t val); 470 int32_t lps25hb_one_shoot_trigger_get(const stmdev_ctx_t *ctx, 471 uint8_t *val); 472 473 int32_t lps25hb_autozero_set(const stmdev_ctx_t *ctx, uint8_t val); 474 int32_t lps25hb_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val); 475 476 int32_t lps25hb_fifo_mean_decimator_set(const stmdev_ctx_t *ctx, 477 uint8_t val); 478 int32_t lps25hb_fifo_mean_decimator_get(const stmdev_ctx_t *ctx, 479 uint8_t *val); 480 481 int32_t lps25hb_press_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 482 483 int32_t lps25hb_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 484 485 int32_t lps25hb_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 486 487 int32_t lps25hb_press_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 488 489 int32_t lps25hb_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); 490 491 int32_t lps25hb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); 492 493 int32_t lps25hb_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val); 494 int32_t lps25hb_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 495 496 int32_t lps25hb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 497 498 int32_t lps25hb_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 499 int32_t lps25hb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 500 501 int32_t lps25hb_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 502 int32_t lps25hb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 503 504 int32_t lps25hb_status_get(const stmdev_ctx_t *ctx, 505 lps25hb_status_reg_t *val); 506 507 int32_t lps25hb_int_generation_set(const stmdev_ctx_t *ctx, uint8_t val); 508 int32_t lps25hb_int_generation_get(const stmdev_ctx_t *ctx, uint8_t *val); 509 510 typedef enum 511 { 512 LPS25HB_DRDY_OR_FIFO_FLAGS = 0, 513 LPS25HB_HIGH_PRES_INT = 1, 514 LPS25HB_LOW_PRES_INT = 2, 515 LPS25HB_EVERY_PRES_INT = 3, 516 } lps25hb_int_s_t; 517 int32_t lps25hb_int_pin_mode_set(const stmdev_ctx_t *ctx, 518 lps25hb_int_s_t val); 519 int32_t lps25hb_int_pin_mode_get(const stmdev_ctx_t *ctx, 520 lps25hb_int_s_t *val); 521 522 typedef enum 523 { 524 LPS25HB_PUSH_PULL = 0, 525 LPS25HB_OPEN_DRAIN = 1, 526 } lps25hb_pp_od_t; 527 int32_t lps25hb_pin_mode_set(const stmdev_ctx_t *ctx, lps25hb_pp_od_t val); 528 int32_t lps25hb_pin_mode_get(const stmdev_ctx_t *ctx, lps25hb_pp_od_t *val); 529 530 typedef enum 531 { 532 LPS25HB_ACTIVE_HIGH = 0, 533 LPS25HB_ACTIVE_LOW = 1, 534 } lps25hb_int_h_l_t; 535 int32_t lps25hb_int_polarity_set(const stmdev_ctx_t *ctx, 536 lps25hb_int_h_l_t val); 537 int32_t lps25hb_int_polarity_get(const stmdev_ctx_t *ctx, 538 lps25hb_int_h_l_t *val); 539 540 int32_t lps25hb_drdy_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); 541 int32_t lps25hb_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); 542 543 int32_t lps25hb_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); 544 int32_t lps25hb_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); 545 546 int32_t lps25hb_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, 547 uint8_t val); 548 int32_t lps25hb_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, 549 uint8_t *val); 550 551 int32_t lps25hb_fifo_empty_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); 552 int32_t lps25hb_fifo_empty_on_int_get(const stmdev_ctx_t *ctx, 553 uint8_t *val); 554 555 typedef enum 556 { 557 LPS25HB_NO_THRESHOLD = 0, 558 LPS25HB_POSITIVE = 1, 559 LPS25HB_NEGATIVE = 2, 560 LPS25HB_BOTH = 3, 561 } lps25hb_pe_t; 562 int32_t lps25hb_sign_of_int_threshold_set(const stmdev_ctx_t *ctx, 563 lps25hb_pe_t val); 564 int32_t lps25hb_sign_of_int_threshold_get(const stmdev_ctx_t *ctx, 565 lps25hb_pe_t *val); 566 567 typedef enum 568 { 569 LPS25HB_INT_PULSED = 0, 570 LPS25HB_INT_LATCHED = 1, 571 } lps25hb_lir_t; 572 int32_t lps25hb_int_notification_mode_set(const stmdev_ctx_t *ctx, 573 lps25hb_lir_t val); 574 int32_t lps25hb_int_notification_mode_get(const stmdev_ctx_t *ctx, 575 lps25hb_lir_t *val); 576 577 int32_t lps25hb_int_source_get(const stmdev_ctx_t *ctx, 578 lps25hb_int_source_t *val); 579 580 int32_t lps25hb_int_on_press_high_get(const stmdev_ctx_t *ctx, 581 uint8_t *val); 582 583 int32_t lps25hb_int_on_press_low_get(const stmdev_ctx_t *ctx, uint8_t *val); 584 585 int32_t lps25hb_interrupt_event_get(const stmdev_ctx_t *ctx, uint8_t *val); 586 587 int32_t lps25hb_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); 588 int32_t lps25hb_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); 589 590 int32_t lps25hb_stop_on_fifo_threshold_set(const stmdev_ctx_t *ctx, 591 uint8_t val); 592 int32_t lps25hb_stop_on_fifo_threshold_get(const stmdev_ctx_t *ctx, 593 uint8_t *val); 594 595 int32_t lps25hb_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); 596 int32_t lps25hb_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); 597 598 int32_t lps25hb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 599 int32_t lps25hb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 600 601 typedef enum 602 { 603 LPS25HB_BYPASS_MODE = 0, 604 LPS25HB_FIFO_MODE = 1, 605 LPS25HB_STREAM_MODE = 2, 606 LPS25HB_Stream_to_FIFO_mode = 3, 607 LPS25HB_BYPASS_TO_STREAM_MODE = 4, 608 LPS25HB_MEAN_MODE = 6, 609 LPS25HB_BYPASS_TO_FIFO_MODE = 7, 610 } lps25hb_f_mode_t; 611 int32_t lps25hb_fifo_mode_set(const stmdev_ctx_t *ctx, 612 lps25hb_f_mode_t val); 613 int32_t lps25hb_fifo_mode_get(const stmdev_ctx_t *ctx, 614 lps25hb_f_mode_t *val); 615 616 int32_t lps25hb_fifo_status_get(const stmdev_ctx_t *ctx, 617 lps25hb_fifo_status_t *val); 618 619 int32_t lps25hb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 620 621 int32_t lps25hb_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 622 623 int32_t lps25hb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 624 625 int32_t lps25hb_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 626 627 typedef enum 628 { 629 LPS25HB_SPI_4_WIRE = 0, 630 LPS25HB_SPI_3_WIRE = 1, 631 } lps25hb_sim_t; 632 int32_t lps25hb_spi_mode_set(const stmdev_ctx_t *ctx, lps25hb_sim_t val); 633 int32_t lps25hb_spi_mode_get(const stmdev_ctx_t *ctx, lps25hb_sim_t *val); 634 635 typedef enum 636 { 637 LPS25HB_I2C_ENABLE = 0, 638 LPS25HB_I2C_DISABLE = 1, 639 } lps25hb_i2c_dis_t; 640 int32_t lps25hb_i2c_interface_set(const stmdev_ctx_t *ctx, 641 lps25hb_i2c_dis_t val); 642 int32_t lps25hb_i2c_interface_get(const stmdev_ctx_t *ctx, 643 lps25hb_i2c_dis_t *val); 644 645 /** 646 *@} 647 * 648 */ 649 650 #ifdef __cplusplus 651 } 652 #endif 653 654 #endif /* LPS25HB_REGS_H */ 655 656 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 657
