1 /** 2 ****************************************************************************** 3 * @file lps22ch_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lps22ch_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LPS22CH_REGS_H 23 #define LPS22CH_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LPS22CH 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LPS22CH_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> B9 if SA0=1 -> BB **/ 172 #define LPS22CH_I2C_ADD_H 0xBBU 173 #define LPS22CH_I2C_ADD_L 0xB9U 174 175 /** Device Identification (Who am I) **/ 176 #define LPS22CH_ID 0xB3U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LPS22CH_INTERRUPT_CFG 0x0BU 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t pe : 2; /* ple + phe */ 188 uint8_t lir : 1; 189 uint8_t diff_en : 1; 190 uint8_t reset_az : 1; 191 uint8_t autozero : 1; 192 uint8_t reset_arp : 1; 193 uint8_t autorefp : 1; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t autorefp : 1; 196 uint8_t reset_arp : 1; 197 uint8_t autozero : 1; 198 uint8_t reset_az : 1; 199 uint8_t diff_en : 1; 200 uint8_t lir : 1; 201 uint8_t pe : 2; /* ple + phe */ 202 #endif /* DRV_BYTE_ORDER */ 203 } lps22ch_interrupt_cfg_t; 204 205 #define LPS22CH_THS_P_L 0x0CU 206 typedef struct 207 { 208 uint8_t ths : 8; 209 } lps22ch_ths_p_l_t; 210 211 #define LPS22CH_THS_P_H 0x0DU 212 typedef struct 213 { 214 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 215 uint8_t ths : 7; 216 uint8_t not_used_01 : 1; 217 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 218 uint8_t not_used_01 : 1; 219 uint8_t ths : 7; 220 #endif /* DRV_BYTE_ORDER */ 221 } lps22ch_ths_p_h_t; 222 223 #define LPS22CH_IF_CTRL 0x0EU 224 typedef struct 225 { 226 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 227 uint8_t i2c_disable : 1; 228 uint8_t i3c_disable : 1; 229 uint8_t pd_dis_int1 : 1; 230 uint8_t sdo_pu_en : 1; 231 uint8_t sda_pu_en : 1; 232 uint8_t not_used : 2; 233 uint8_t int_en_i3c : 1; 234 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 235 uint8_t int_en_i3c : 1; 236 uint8_t not_used : 2; 237 uint8_t sda_pu_en : 1; 238 uint8_t sdo_pu_en : 1; 239 uint8_t pd_dis_int1 : 1; 240 uint8_t i3c_disable : 1; 241 uint8_t i2c_disable : 1; 242 #endif /* DRV_BYTE_ORDER */ 243 } lps22ch_if_ctrl_t; 244 245 #define LPS22CH_WHO_AM_I 0x0FU 246 #define LPS22CH_CTRL_REG1 0x10U 247 typedef struct 248 { 249 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 250 uint8_t sim : 1; 251 uint8_t bdu : 1; 252 uint8_t lpfp_cfg : 2; /* en_lpfp + lpfp_cfg */ 253 uint8_t odr : 3; 254 uint8_t not_used_01 : 1; 255 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 256 uint8_t not_used_01 : 1; 257 uint8_t odr : 3; 258 uint8_t lpfp_cfg : 2; /* en_lpfp + lpfp_cfg */ 259 uint8_t bdu : 1; 260 uint8_t sim : 1; 261 #endif /* DRV_BYTE_ORDER */ 262 } lps22ch_ctrl_reg1_t; 263 264 #define LPS22CH_CTRL_REG2 0x11U 265 typedef struct 266 { 267 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 268 uint8_t one_shot : 1; 269 uint8_t low_noise_en : 1; 270 uint8_t swreset : 1; 271 uint8_t not_used_01 : 1; 272 uint8_t if_add_inc : 1; 273 uint8_t pp_od : 1; 274 uint8_t int_h_l : 1; 275 uint8_t boot : 1; 276 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 277 uint8_t boot : 1; 278 uint8_t int_h_l : 1; 279 uint8_t pp_od : 1; 280 uint8_t if_add_inc : 1; 281 uint8_t not_used_01 : 1; 282 uint8_t swreset : 1; 283 uint8_t low_noise_en : 1; 284 uint8_t one_shot : 1; 285 #endif /* DRV_BYTE_ORDER */ 286 } lps22ch_ctrl_reg2_t; 287 288 #define LPS22CH_CTRL_REG3 0x12U 289 typedef struct 290 { 291 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 292 uint8_t int_s : 2; 293 uint8_t drdy : 1; 294 uint8_t int_f_ovr : 1; 295 uint8_t int_f_wtm : 1; 296 uint8_t int_f_full : 1; 297 uint8_t not_used_01 : 2; 298 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 299 uint8_t not_used_01 : 2; 300 uint8_t int_f_full : 1; 301 uint8_t int_f_wtm : 1; 302 uint8_t int_f_ovr : 1; 303 uint8_t drdy : 1; 304 uint8_t int_s : 2; 305 #endif /* DRV_BYTE_ORDER */ 306 } lps22ch_ctrl_reg3_t; 307 308 #define LPS22CH_FIFO_CTRL 0x13U 309 typedef struct 310 { 311 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 312 uint8_t f_mode : 3; /* f_mode + trig_modes */ 313 uint8_t stop_on_wtm : 1; 314 uint8_t not_used_01 : 4; 315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 316 uint8_t not_used_01 : 4; 317 uint8_t stop_on_wtm : 1; 318 uint8_t f_mode : 3; /* f_mode + trig_modes */ 319 #endif /* DRV_BYTE_ORDER */ 320 } lps22ch_fifo_ctrl_t; 321 322 #define LPS22CH_FIFO_WTM 0x14U 323 typedef struct 324 { 325 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 326 uint8_t wtm : 7; 327 uint8_t not_used_01 : 1; 328 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 329 uint8_t not_used_01 : 1; 330 uint8_t wtm : 7; 331 #endif /* DRV_BYTE_ORDER */ 332 } lps22ch_fifo_wtm_t; 333 334 #define LPS22CH_REF_P_L 0x15U 335 #define LPS22CH_REF_P_H 0x16U 336 #define LPS22CH_RPDS_L 0x18U 337 #define LPS22CH_RPDS_H 0x19U 338 #define LPS22CH_INT_SOURCE 0x24U 339 typedef struct 340 { 341 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 342 uint8_t ph : 1; 343 uint8_t pl : 1; 344 uint8_t ia : 1; 345 uint8_t not_used_01 : 4; 346 uint8_t boot_on : 1; 347 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 348 uint8_t boot_on : 1; 349 uint8_t not_used_01 : 4; 350 uint8_t ia : 1; 351 uint8_t pl : 1; 352 uint8_t ph : 1; 353 #endif /* DRV_BYTE_ORDER */ 354 } lps22ch_int_source_t; 355 356 #define LPS22CH_FIFO_STATUS1 0x25U 357 #define LPS22CH_FIFO_STATUS2 0x26U 358 typedef struct 359 { 360 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 361 uint8_t not_used_01 : 5; 362 uint8_t fifo_full_ia : 1; 363 uint8_t fifo_ovr_ia : 1; 364 uint8_t fifo_wtm_ia : 1; 365 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 366 uint8_t fifo_wtm_ia : 1; 367 uint8_t fifo_ovr_ia : 1; 368 uint8_t fifo_full_ia : 1; 369 uint8_t not_used_01 : 5; 370 #endif /* DRV_BYTE_ORDER */ 371 } lps22ch_fifo_status2_t; 372 373 #define LPS22CH_STATUS 0x27U 374 typedef struct 375 { 376 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 377 uint8_t p_da : 1; 378 uint8_t t_da : 1; 379 uint8_t not_used_01 : 2; 380 uint8_t p_or : 1; 381 uint8_t t_or : 1; 382 uint8_t not_used_02 : 2; 383 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 384 uint8_t not_used_02 : 2; 385 uint8_t t_or : 1; 386 uint8_t p_or : 1; 387 uint8_t not_used_01 : 2; 388 uint8_t t_da : 1; 389 uint8_t p_da : 1; 390 #endif /* DRV_BYTE_ORDER */ 391 } lps22ch_status_t; 392 393 #define LPS22CH_PRESS_OUT_XL 0x28U 394 #define LPS22CH_PRESS_OUT_L 0x29U 395 #define LPS22CH_PRESS_OUT_H 0x2AU 396 #define LPS22CH_TEMP_OUT_L 0x2BU 397 #define LPS22CH_TEMP_OUT_H 0x2CU 398 #define LPS22CH_FIFO_DATA_OUT_PRESS_XL 0x78U 399 #define LPS22CH_FIFO_DATA_OUT_PRESS_L 0x79U 400 #define LPS22CH_FIFO_DATA_OUT_PRESS_H 0x7AU 401 #define LPS22CH_FIFO_DATA_OUT_TEMP_L 0x7BU 402 #define LPS22CH_FIFO_DATA_OUT_TEMP_H 0x7CU 403 404 /** 405 * @defgroup LPS22CH_Register_Union 406 * @brief This union group all the registers having a bit-field 407 * description. 408 * This union is useful but it's not needed by the driver. 409 * 410 * REMOVING this union you are compliant with: 411 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 412 * 413 * @{ 414 * 415 */ 416 typedef union 417 { 418 lps22ch_interrupt_cfg_t interrupt_cfg; 419 lps22ch_if_ctrl_t if_ctrl; 420 lps22ch_ctrl_reg1_t ctrl_reg1; 421 lps22ch_ctrl_reg2_t ctrl_reg2; 422 lps22ch_ctrl_reg3_t ctrl_reg3; 423 lps22ch_fifo_ctrl_t fifo_ctrl; 424 lps22ch_fifo_wtm_t fifo_wtm; 425 lps22ch_int_source_t int_source; 426 lps22ch_fifo_status2_t fifo_status2; 427 lps22ch_status_t status; 428 bitwise_t bitwise; 429 uint8_t byte; 430 } lps22ch_reg_t; 431 432 /** 433 * @} 434 * 435 */ 436 437 #ifndef __weak 438 #define __weak __attribute__((weak)) 439 #endif /* __weak */ 440 441 /* 442 * These are the basic platform dependent I/O routines to read 443 * and write device registers connected on a standard bus. 444 * The driver keeps offering a default implementation based on function 445 * pointers to read/write routines for backward compatibility. 446 * The __weak directive allows the final application to overwrite 447 * them with a custom implementation. 448 */ 449 450 int32_t lps22ch_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 451 uint8_t *data, 452 uint16_t len); 453 int32_t lps22ch_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 454 uint8_t *data, 455 uint16_t len); 456 457 float_t lps22ch_from_lsb_to_hpa(uint32_t lsb); 458 459 float_t lps22ch_from_lsb_to_celsius(int16_t lsb); 460 461 int32_t lps22ch_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val); 462 int32_t lps22ch_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); 463 464 int32_t lps22ch_autozero_set(const stmdev_ctx_t *ctx, uint8_t val); 465 int32_t lps22ch_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val); 466 467 int32_t lps22ch_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val); 468 int32_t lps22ch_pressure_snap_rst_get(const stmdev_ctx_t *ctx, 469 uint8_t *val); 470 471 int32_t lps22ch_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val); 472 int32_t lps22ch_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val); 473 474 int32_t lps22ch_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 475 int32_t lps22ch_block_data_update_get(const stmdev_ctx_t *ctx, 476 uint8_t *val); 477 478 typedef enum 479 { 480 LPS22CH_POWER_DOWN = 0x00, 481 LPS22CH_ONE_SHOOT = 0x08, 482 LPS22CH_1_Hz = 0x01, 483 LPS22CH_10_Hz = 0x02, 484 LPS22CH_25_Hz = 0x03, 485 LPS22CH_50_Hz = 0x04, 486 LPS22CH_75_Hz = 0x05, 487 LPS22CH_1_Hz_LOW_NOISE = 0x11, 488 LPS22CH_10_Hz_LOW_NOISE = 0x12, 489 LPS22CH_25_Hz_LOW_NOISE = 0x13, 490 LPS22CH_50_Hz_LOW_NOISE = 0x14, 491 LPS22CH_75_Hz_LOW_NOISE = 0x15, 492 LPS22CH_100_Hz = 0x06, 493 LPS22CH_200_Hz = 0x07, 494 } lps22ch_odr_t; 495 int32_t lps22ch_data_rate_set(const stmdev_ctx_t *ctx, lps22ch_odr_t val); 496 int32_t lps22ch_data_rate_get(const stmdev_ctx_t *ctx, lps22ch_odr_t *val); 497 498 int32_t lps22ch_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val); 499 int32_t lps22ch_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val); 500 501 int32_t lps22ch_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val); 502 int32_t lps22ch_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 503 504 typedef struct 505 { 506 lps22ch_int_source_t int_source; 507 lps22ch_fifo_status2_t fifo_status2; 508 lps22ch_status_t status; 509 } lps22ch_all_sources_t; 510 int32_t lps22ch_all_sources_get(const stmdev_ctx_t *ctx, 511 lps22ch_all_sources_t *val); 512 513 int32_t lps22ch_status_reg_get(const stmdev_ctx_t *ctx, 514 lps22ch_status_t *val); 515 516 int32_t lps22ch_press_flag_data_ready_get(const stmdev_ctx_t *ctx, 517 uint8_t *val); 518 519 int32_t lps22ch_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 520 uint8_t *val); 521 522 int32_t lps22ch_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); 523 524 int32_t lps22ch_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); 525 526 int32_t lps22ch_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, 527 uint32_t *buff); 528 529 int32_t lps22ch_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, 530 int16_t *buff); 531 532 int32_t lps22ch_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 533 534 int32_t lps22ch_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 535 int32_t lps22ch_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 536 537 int32_t lps22ch_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 538 int32_t lps22ch_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 539 540 int32_t lps22ch_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 541 int32_t lps22ch_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 542 543 typedef enum 544 { 545 LPS22CH_LPF_ODR_DIV_2 = 0, 546 LPS22CH_LPF_ODR_DIV_9 = 2, 547 LPS22CH_LPF_ODR_DIV_20 = 3, 548 } lps22ch_lpfp_cfg_t; 549 int32_t lps22ch_lp_bandwidth_set(const stmdev_ctx_t *ctx, 550 lps22ch_lpfp_cfg_t val); 551 int32_t lps22ch_lp_bandwidth_get(const stmdev_ctx_t *ctx, 552 lps22ch_lpfp_cfg_t *val); 553 554 typedef enum 555 { 556 LPS22CH_I2C_ENABLE = 0, 557 LPS22CH_I2C_DISABLE = 1, 558 } lps22ch_i2c_disable_t; 559 int32_t lps22ch_i2c_interface_set(const stmdev_ctx_t *ctx, 560 lps22ch_i2c_disable_t val); 561 int32_t lps22ch_i2c_interface_get(const stmdev_ctx_t *ctx, 562 lps22ch_i2c_disable_t *val); 563 564 typedef enum 565 { 566 LPS22CH_I3C_ENABLE = 0, 567 LPS22CH_I3C_DISABLE = 1, 568 } lps22ch_i3c_disable_t; 569 int32_t lps22ch_i3c_interface_set(const stmdev_ctx_t *ctx, 570 lps22ch_i3c_disable_t val); 571 int32_t lps22ch_i3c_interface_get(const stmdev_ctx_t *ctx, 572 lps22ch_i3c_disable_t *val); 573 574 typedef enum 575 { 576 LPS22CH_PULL_UP_DISCONNECT = 0, 577 LPS22CH_PULL_UP_CONNECT = 1, 578 } lps22ch_pu_en_t; 579 int32_t lps22ch_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 580 lps22ch_pu_en_t val); 581 int32_t lps22ch_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 582 lps22ch_pu_en_t *val); 583 int32_t lps22ch_sda_mode_set(const stmdev_ctx_t *ctx, lps22ch_pu_en_t val); 584 int32_t lps22ch_sda_mode_get(const stmdev_ctx_t *ctx, lps22ch_pu_en_t *val); 585 586 typedef enum 587 { 588 LPS22CH_SPI_4_WIRE = 0, 589 LPS22CH_SPI_3_WIRE = 1, 590 } lps22ch_sim_t; 591 int32_t lps22ch_spi_mode_set(const stmdev_ctx_t *ctx, lps22ch_sim_t val); 592 int32_t lps22ch_spi_mode_get(const stmdev_ctx_t *ctx, lps22ch_sim_t *val); 593 594 typedef enum 595 { 596 LPS22CH_INT_PULSED = 0, 597 LPS22CH_INT_LATCHED = 1, 598 } lps22ch_lir_t; 599 int32_t lps22ch_int_notification_set(const stmdev_ctx_t *ctx, 600 lps22ch_lir_t val); 601 int32_t lps22ch_int_notification_get(const stmdev_ctx_t *ctx, 602 lps22ch_lir_t *val); 603 604 typedef enum 605 { 606 LPS22CH_PUSH_PULL = 0, 607 LPS22CH_OPEN_DRAIN = 1, 608 } lps22ch_pp_od_t; 609 int32_t lps22ch_pin_mode_set(const stmdev_ctx_t *ctx, lps22ch_pp_od_t val); 610 int32_t lps22ch_pin_mode_get(const stmdev_ctx_t *ctx, lps22ch_pp_od_t *val); 611 612 typedef enum 613 { 614 LPS22CH_ACTIVE_HIGH = 0, 615 LPS22CH_ACTIVE_LOW = 1, 616 } lps22ch_int_h_l_t; 617 int32_t lps22ch_pin_polarity_set(const stmdev_ctx_t *ctx, 618 lps22ch_int_h_l_t val); 619 int32_t lps22ch_pin_polarity_get(const stmdev_ctx_t *ctx, 620 lps22ch_int_h_l_t *val); 621 622 int32_t lps22ch_pin_int_route_set(const stmdev_ctx_t *ctx, 623 lps22ch_ctrl_reg3_t *val); 624 int32_t lps22ch_pin_int_route_get(const stmdev_ctx_t *ctx, 625 lps22ch_ctrl_reg3_t *val); 626 627 typedef enum 628 { 629 LPS22CH_NO_THRESHOLD = 0, 630 LPS22CH_POSITIVE = 1, 631 LPS22CH_NEGATIVE = 2, 632 LPS22CH_BOTH = 3, 633 } lps22ch_pe_t; 634 int32_t lps22ch_int_on_threshold_set(const stmdev_ctx_t *ctx, 635 lps22ch_pe_t val); 636 int32_t lps22ch_int_on_threshold_get(const stmdev_ctx_t *ctx, 637 lps22ch_pe_t *val); 638 639 int32_t lps22ch_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff); 640 int32_t lps22ch_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff); 641 642 typedef enum 643 { 644 LPS22CH_BYPASS_MODE = 0, 645 LPS22CH_FIFO_MODE = 1, 646 LPS22CH_STREAM_MODE = 2, 647 LPS22CH_DYNAMIC_STREAM_MODE = 3, 648 LPS22CH_BYPASS_TO_FIFO_MODE = 5, 649 LPS22CH_BYPASS_TO_STREAM_MODE = 6, 650 LPS22CH_STREAM_TO_FIFO_MODE = 7, 651 } lps22ch_f_mode_t; 652 int32_t lps22ch_fifo_mode_set(const stmdev_ctx_t *ctx, 653 lps22ch_f_mode_t val); 654 int32_t lps22ch_fifo_mode_get(const stmdev_ctx_t *ctx, 655 lps22ch_f_mode_t *val); 656 657 int32_t lps22ch_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 658 int32_t lps22ch_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); 659 660 int32_t lps22ch_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 661 int32_t lps22ch_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 662 663 int32_t lps22ch_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *buff); 664 665 int32_t lps22ch_fifo_src_get(const stmdev_ctx_t *ctx, 666 lps22ch_fifo_status2_t *val); 667 668 int32_t lps22ch_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 669 670 int32_t lps22ch_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 671 672 int32_t lps22ch_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 673 674 int32_t lps22ch_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); 675 int32_t lps22ch_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); 676 677 int32_t lps22ch_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, 678 uint8_t val); 679 int32_t lps22ch_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, 680 uint8_t *val); 681 682 int32_t lps22ch_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); 683 int32_t lps22ch_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); 684 685 /** 686 * @} 687 * 688 */ 689 690 #ifdef __cplusplus 691 } 692 #endif 693 694 #endif /*LPS22CH_REGS_H */ 695 696 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 697
