1 /**************************************************************************//** 2 * @file lppdma_reg.h 3 * @version V1.00 4 * @brief LPPDMA register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __LPPDMA_REG_H__ 10 #define __LPPDMA_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** @addtogroup REGISTER Control Register 17 18 @{ 19 20 */ 21 22 23 /*---------------------- Low Power Peripheral Direct Memory Access Controller -------------------------*/ 24 /** 25 @addtogroup LPPDMA Low Power Peripheral Direct Memory Access Controller (LPPDMA) 26 Memory Mapped Structure for LPPDMA Controller 27 @{ */ 28 29 typedef struct 30 { 31 32 33 /** 34 * @var LPDSCT_T::CTL 35 * Offset: 0x00 Descriptor Table Control Register of LPPDMA Channel n 36 * --------------------------------------------------------------------------------------------------- 37 * |Bits |Field |Descriptions 38 * | :----: | :----: | :---- | 39 * |[1:0] |OPMODE |LPPDMA Operation Mode Selection 40 * | | |00 = Idle state: Channel is stopped or this table is complete, when LPPDMA finish channel table task, OPMODE will be cleared to idle state automatically. 41 * | | |01 = Basic mode: The descriptor table only has one task 42 * | | |When this task is finished, LPPDMA_INTSTS[1] will be asserted. 43 * | | |10 = Scatter-gather mode: When operating in this mode, user must give the next descriptor table address in LPPDMA_DSCTn_NEXT register; LPPDMA will ignore this task, then load the next task to execute. 44 * | | |11 = Reserved. 45 * | | |Note: Before filling new transfer task in the Descriptor Table, user must check LPPDMA_INTSTS[1] to make sure the current task is complete. 46 * |[2] |TXTYPE |Transfer Type 47 * | | |0 = Burst transfer type. 48 * | | |1 = Single transfer type. 49 * |[6:4] |BURSIZE |Burst Size 50 * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. 51 * | | |000 = 128 Transfers. 52 * | | |001 = 64 Transfers. 53 * | | |010 = 32 Transfers. 54 * | | |011 = 16 Transfers. 55 * | | |100 = 8 Transfers. 56 * | | |101 = 4 Transfers. 57 * | | |110 = 2 Transfers. 58 * | | |111 = 1 Transfers. 59 * | | |Note: This field is only useful in burst transfer type. 60 * |[7] |TBINTDIS |Table Interrupt Disable Bit 61 * | | |This field can be used to decide whether to enable table interrupt or not 62 * | | |If the TBINTDIS bit is 1 it will not generates TDIFn(LPPDMA_TDSTS[3:0]) when LPPDMA finishes transfer task. 63 * | | |0 = Table interrupt Enabled. 64 * | | |1 = Table interrupt Disabled. 65 * | | |Note: This function only for Scatter-gather mode. 66 * |[9:8] |SAINC |Source Address Increment 67 * | | |This field is used to set the source address increment size. 68 * | | |11 = No increment (fixed address). 69 * | | |Others = Increment and size is depended on TXWIDTH selection. 70 * | | |Note: The fixed address function does not support in memory to memory transfer type. 71 * |[11:10] |DAINC |Destination Address Increment 72 * | | |This field is used to set the destination address increment size. 73 * | | |11 = No increment (fixed address). 74 * | | |Others = Increment and size is depended on TXWIDTH selection. 75 * | | |Note: The fixed address function does not support in memory to memory transfer type. 76 * |[13:12] |TXWIDTH |Transfer Width Selection 77 * | | |This field is used for transfer width. 78 * | | |00 = One byte (8 bit) is transferred for every operation. 79 * | | |01= One half-word (16 bit) is transferred for every operation. 80 * | | |10 = One word (32-bit) is transferred for every operation. 81 * | | |11 = Reserved. 82 * | | |Note: LPPDMA transfer source address (LPPDMA_DSCTn_SA) and LPPDMA transfer destination address (LPPDMA_DSCTn_DA) should be alignment under the TXWIDTH selection 83 * |[31:16] |TXCNT |Transfer Count 84 * | | |The TXCNT represents the required number of LPPDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 65536, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. 85 * | | |Note: When LPPDMA finishes each transfer data, this field will be decreased immediately. 86 * @var LPDSCT_T::SA 87 * Offset: 0x04 Source Address Register of LPPDMA Channel n 88 * --------------------------------------------------------------------------------------------------- 89 * |Bits |Field |Descriptions 90 * | :----: | :----: | :---- | 91 * |[31:0] |SA |LPPDMA Transfer Source Address 92 * | | |This field indicates a 32-bit source address of LPPDMA. 93 * @var LPDSCT_T::DA 94 * Offset: 0x08 Destination Address Register of LPPDMA Channel n 95 * --------------------------------------------------------------------------------------------------- 96 * |Bits |Field |Descriptions 97 * | :----: | :----: | :---- | 98 * |[31:0] |DA |LPPDMA Transfer Destination Address 99 * | | |This field indicates a 32-bit destination address of LPPDMA. 100 * @var LPDSCT_T::NEXT 101 * Offset: 0x0C Next Scatter-gather Descriptor Table Offset Address of LPPDMA Channel n 102 * --------------------------------------------------------------------------------------------------- 103 * |Bits |Field |Descriptions 104 * | :----: | :----: | :---- | 105 * |[15:0] |NEXT |LPPDMA Next Descriptor Table Offset 106 * | | |This field indicates the offset of the next descriptor table address in system memory. 107 * | | |Write Operation: 108 * | | |If the system memory based address is 0x2800_0000 (LPPDMA_SCATBA), and the next descriptor table is start from 0x2800_0100, then this field must fill in 0x0100. 109 * | | |Read Operation: 110 * | | |When operating in Scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. 111 * | | |Note 1: The descriptor table address must be word boundary. 112 * | | |Note 2: Before filling transfer task in the descriptor table, user must check if the descriptor table is complete. 113 * |[31:16] |EXENEXT |LPPDMA Execution Next Descriptor Table Offset 114 * | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. 115 * | | |Note: Write operation is useless in this field. 116 */ 117 __IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of LPPDMA Channel n */ 118 __IO uint32_t SA; /*!< [0x0004] Source Address Register of LPPDMA Channel n */ 119 __IO uint32_t DA; /*!< [0x0008] Destination Address Register of LPPDMA Channel n */ 120 __IO uint32_t NEXT; /*!< [0x000c] Next Scatter-gather Descriptor Table Offset Address of LPPDMA Channel n */ 121 } LPDSCT_T; 122 123 typedef struct 124 { 125 126 127 /** 128 * @var LPPDMA_T::CURSCAT 129 * Offset: 0x40 Current Scatter-gather Descriptor Table Address of LPPDMA Channel n 130 * --------------------------------------------------------------------------------------------------- 131 * |Bits |Field |Descriptions 132 * | :----: | :----: | :---- | 133 * |[31:0] |CURADDR |LPPDMA Current Description Address (Read Only) 134 * | | |This field indicates a 32-bit current external description address of LPPDMA. 135 * | | |Note: This field is read only and used for Scatter-gather mode only to indicate the current external description address. 136 * @var LPPDMA_T::CHCTL 137 * Offset: 0x400 LPPDMA Channel Control Register 138 * --------------------------------------------------------------------------------------------------- 139 * |Bits |Field |Descriptions 140 * | :----: | :----: | :---- | 141 * |[3:0] |CHENn |LPPDMA Channel Enable Bits 142 * | | |Set this bit to 1 to enable LPPDMAn operation. Channel cannot be active if it is not set as enabled. 143 * | | |0 = LPPDMA channel [n] Disabled. 144 * | | |1 = LPPDMA channel [n] Enabled. 145 * | | |Note: Setting the corresponding bit of LPPDMA_PAUSE or LPPDMA_CHRST register will also clear this bit. 146 * @var LPPDMA_T::PAUSE 147 * Offset: 0x404 LPPDMA Transfer Pause Control Register 148 * --------------------------------------------------------------------------------------------------- 149 * |Bits |Field |Descriptions 150 * | :----: | :----: | :---- | 151 * |[3:0] |PAUSEn |LPPDMA Channel n Transfer Pause Control (Write Only) 152 * | | |User can set PAUSEn bit field to pause LPPDMA transfer 153 * | | |When user sets PAUSEn bit, LPPDMA will pause the on-going transfer, then clear the channel enable bit CHENn(LPPDMA_CHCTL [n], n=0,1..3) and clear request active flag(LPPDMA_TRGSTS[n:0], n=0,1..3) 154 * | | |If the paused channel is re-enabled again, the remaining transfers will be processed. 155 * | | |0 = No effect. 156 * | | |1 = Pause LPPDMA channel n transfer. 157 * @var LPPDMA_T::SWREQ 158 * Offset: 0x408 LPPDMA Software Request Register 159 * --------------------------------------------------------------------------------------------------- 160 * |Bits |Field |Descriptions 161 * | :----: | :----: | :---- | 162 * |[3:0] |SWREQn |LPPDMA Software Request (Write Only) 163 * | | |Set this bit to 1 to generate a software request to LPPDMA [n]. 164 * | | |0 = No effect. 165 * | | |1 = Generate a software request. 166 * | | |Note 1: User can read LPPDMA_TRGSTS register to know which channel is on active 167 * | | |Active flag may be triggered by software request or peripheral request. 168 * | | |Note 2: If user does not enable corresponding LPPDMA channel, the software request will be ignored. 169 * @var LPPDMA_T::TRGSTS 170 * Offset: 0x40C LPPDMA Channel Request Status Register 171 * --------------------------------------------------------------------------------------------------- 172 * |Bits |Field |Descriptions 173 * | :----: | :----: | :---- | 174 * |[3:0] |REQSTSn |LPPDMA Channel Request Status (Read Only) 175 * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral 176 * | | |When LPPDMA finishes channel transfer, this bit will be cleared automatically. 177 * | | |0 = LPPDMA Channel n has no request. 178 * | | |1 = LPPDMA Channel n has a request. 179 * | | |Note: If user pauses or resets each LPPDMA transfer by setting LPPDMA_PAUSE or LPPDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. 180 * @var LPPDMA_T::PRISET 181 * Offset: 0x410 LPPDMA Fixed Priority Setting Register 182 * --------------------------------------------------------------------------------------------------- 183 * |Bits |Field |Descriptions 184 * | :----: | :----: | :---- | 185 * |[3:0] |FPRISETn |LPPDMA Fixed Priority Setting 186 * | | |Set this bit to 1 to enable fixed priority level. 187 * | | |Write Operation: 188 * | | |0 = No effect. 189 * | | |1 = Set LPPDMA channel [n] to fixed priority channel. 190 * | | |Read Operation: 191 * | | |0 = Corresponding LPPDMA channel is round-robin priority. 192 * | | |1 = Corresponding LPPDMA channel is fixed priority. 193 * | | |Note: This field is only set to fixed priority. To clear fixed priority, use LPPDMA_PRICLR register. 194 * @var LPPDMA_T::PRICLR 195 * Offset: 0x414 LPPDMA Fixed Priority Clear Register 196 * --------------------------------------------------------------------------------------------------- 197 * |Bits |Field |Descriptions 198 * | :----: | :----: | :---- | 199 * |[3:0] |FPRICLRn |LPPDMA Fixed Priority Clear Bits (Write Only) 200 * | | |Set this bit to 1 to clear fixed priority level. 201 * | | |0 = No effect. 202 * | | |1 = Clear LPPDMA channel [n] fixed priority setting. 203 * | | |Note: User can read LPPDMA_PRISET register to know the channel priority. 204 * @var LPPDMA_T::INTEN 205 * Offset: 0x418 LPPDMA Interrupt Enable Register 206 * --------------------------------------------------------------------------------------------------- 207 * |Bits |Field |Descriptions 208 * | :----: | :----: | :---- | 209 * |[3:0] |INTENn |LPPDMA Interrupt Enable Bits 210 * | | |This field is used to enable LPPDMA channel[n] interrupt. 211 * | | |0 = LPPDMA channel n interrupt Disabled. 212 * | | |1 = LPPDMA channel n interrupt Enabled. 213 * | | |Note: The interrupt flag is abort, transfer done and align. 214 * @var LPPDMA_T::INTSTS 215 * Offset: 0x41C LPPDMA Interrupt Status Register 216 * --------------------------------------------------------------------------------------------------- 217 * |Bits |Field |Descriptions 218 * | :----: | :----: | :---- | 219 * |[0] |ABTIF |LPPDMA Read/Write Target Abort Interrupt Flag (Read Only) 220 * | | |This bit indicates that LPPDMA has target abort error; Software can read LPPDMA_ABTSTS register to find which channel has target abort error. 221 * | | |0 = No AHB bus ERROR response received. 222 * | | |1 = AHB bus ERROR response received. 223 * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) 224 * | | |This bit indicates that LPPDMA controller has finished transmission; User can read LPPDMA_TDSTS register to indicate which channel finished transfer. 225 * | | |0 = Not finished yet. 226 * | | |1 = LPPDMA channel has finished transmission. 227 * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) 228 * | | |0 = LPPDMA channel source address and destination address both follow transfer width setting. 229 * | | |1 = LPPDMA channel source address or destination address is not follow transfer width setting. 230 * |[3] |WKF |Wake Up Flag 231 * | | |0 = LPPDMA no wake up event. 232 * | | |1 = LPPDMA wake up event happened. 233 * @var LPPDMA_T::ABTSTS 234 * Offset: 0x420 LPPDMA Channel Read/Write Target Abort Flag Register 235 * --------------------------------------------------------------------------------------------------- 236 * |Bits |Field |Descriptions 237 * | :----: | :----: | :---- | 238 * |[3:0] |ABTIFn |LPPDMA Read/Write Target Abort Interrupt Status Flag 239 * | | |This bit indicates which LPPDMA controller has target abort error. 240 * | | |0 = No AHB bus ERROR response received when channel n transfer. 241 * | | |1 = AHB bus ERROR response received when channel n transfer. 242 * | | |Note 1: If channel n target abort, REQSRCn should set0 to disable peripheral request. 243 * | | |Note 2: User can write 1 to clear this bit. 244 * @var LPPDMA_T::TDSTS 245 * Offset: 0x424 LPPDMA Channel Transfer Done Flag Register 246 * --------------------------------------------------------------------------------------------------- 247 * |Bits |Field |Descriptions 248 * | :----: | :----: | :---- | 249 * |[3:0] |TDIFn |Transfer Done Flag 250 * | | |This bit indicates whether LPPDMA controller channel transfer has been finished or not. 251 * | | |0 = LPPDMA channel transfer has not finished. 252 * | | |1 = LPPDMA channel has finished transmission. 253 * | | |Note: User can write 1 to clear these bits. 254 * @var LPPDMA_T::ALIGN 255 * Offset: 0x428 LPPDMA Transfer Alignment Status Register 256 * --------------------------------------------------------------------------------------------------- 257 * |Bits |Field |Descriptions 258 * | :----: | :----: | :---- | 259 * |[3:0] |ALIGNn |Transfer Alignment Flag 260 * | | |This bit indicates whether source and destination address both follow transfer width setting. 261 * | | |0 = LPPDMA channel source address and destination address both follow transfer width setting. 262 * | | |1 = LPPDMA channel source address or destination address is not follow transfer width setting. 263 * | | |Note: User can write 1 to clear these bits. 264 * @var LPPDMA_T::TACTSTS 265 * Offset: 0x42C LPPDMA Transfer Active Flag Register 266 * --------------------------------------------------------------------------------------------------- 267 * |Bits |Field |Descriptions 268 * | :----: | :----: | :---- | 269 * |[3:0] |TXACTFn |Transfer on Active Flag (Read Only) 270 * | | |This bit indicates which LPPDMA channel is in active. 271 * | | |0 = LPPDMA channel is finished. 272 * | | |1 = LPPDMA channel is active. 273 * @var LPPDMA_T::SCATBA 274 * Offset: 0x43C LPPDMA Scatter-gather Descriptor Table Base Address Register 275 * --------------------------------------------------------------------------------------------------- 276 * |Bits |Field |Descriptions 277 * | :----: | :----: | :---- | 278 * |[31:16] |SCATBA |LPPDMA Scatter-gather Descriptor Table Address 279 * | | |In Scatter-gather mode, this is the base address for calculating the next link - list address 280 * | | |The next link address equation is 281 * | | |Next Link Address = LPPDMA_SCATBA + LPPDMA_DSCTn_NEXT. 282 * | | |Note: Only useful in Scatter-gather mode. 283 * @var LPPDMA_T::CHRST 284 * Offset: 0x460 LPPDMA Channel Reset Register 285 * --------------------------------------------------------------------------------------------------- 286 * |Bits |Field |Descriptions 287 * | :----: | :----: | :---- | 288 * |[3:0] |CHnRST |Channel n Reset 289 * | | |0 = Corresponding channel n is not reset. 290 * | | |1 = Corresponding channel n is reset. 291 * @var LPPDMA_T::REQSEL0_3 292 * Offset: 0x480 LPPDMA Request Source Select Register 0 293 * --------------------------------------------------------------------------------------------------- 294 * |Bits |Field |Descriptions 295 * | :----: | :----: | :---- | 296 * |[6:0] |REQSRC0 |Channel 0 Request Source Selection 297 * | | |This filed defines which peripheral is connected to LPPDMA channel 0 298 * | | |User can configure the peripheral by setting REQSRC0. 299 * | | |0 = Disable LPPDMA peripheral request. 300 * | | |1 = Channel connects to LPUART0_TX. 301 * | | |2 = Channel connects to LPUART0_RX . 302 * | | |3 = Channel connects to LPSPI0_TX. 303 * | | |4 = Channel connects to LPSPI0_RX. 304 * | | |5 = Channel connects to LPI2C0_TX. 305 * | | |6 = Channel connects to LPI2C0_RX. 306 * | | |7 = Channel connects to LPTIMER0. 307 * | | |8 = Channel connects to LPTIMER1. 308 * | | |9 = Channel connects to TTIMER0. 309 * | | |10=Channel connects to TTIMER1. 310 * | | |11 = Channel connects to LPADC0_RX. 311 * | | |12 = Reserved. 312 * | | |13 = Reserved . 313 * | | |14 = Channel connects to ACMP0. 314 * | | |15 = Channel connects to ACMP1. 315 * | | |16 = Channel connects to ACMP2. 316 * | | |Others = Reserved. 317 * | | |Note 1: A peripheral cannot be assigned to two channels at the same time. 318 * | | |Note 2: This field is useless when transfer between memory and memory. 319 * |[14:8] |REQSRC1 |Channel 1 Request Source Selection 320 * | | |This filed defines which peripheral is connected to LPPDMA channel 1 321 * | | |User can configure the peripheral setting by REQSRC1. 322 * | | |Note: The channel configuration is the same as REQSRC0 field 323 * | | |Please refer to the explanation of REQSRC0. 324 * |[22:16] |REQSRC2 |Channel 2 Request Source Selection 325 * | | |This filed defines which peripheral is connected to LPPDMA channel 2 326 * | | |User can configure the peripheral setting by REQSRC2. 327 * | | |Note: The channel configuration is the same as REQSRC0 field 328 * | | |Please refer to the explanation of REQSRC0. 329 * |[30:24] |REQSRC3 |Channel 3 Request Source Selection 330 * | | |This filed defines which peripheral is connected to LPPDMA channel 3 331 * | | |User can configure the peripheral setting by REQSRC3. 332 * | | |Note: The channel configuration is the same as REQSRC0 field 333 * | | |Please refer to the explanation of REQSRC0. 334 */ 335 LPDSCT_T LPDSCT[4]; /*!< [0x0000 ~ 0x003C] Control Register of LPPDMA Channel 0 ~ 3 */ 336 __I uint32_t CURSCAT[4]; /*!< [0x0040 ~ 0x004C] Current Scatter-gather Descriptor Table Address of LPPDMA Channel n */ 337 __I uint32_t RESERVE0[236]; 338 __IO uint32_t CHCTL; /*!< [0x0400] LPPDMA Channel Control Register */ 339 __O uint32_t PAUSE; /*!< [0x0404] LPPDMA Transfer Pause Control Register */ 340 __O uint32_t SWREQ; /*!< [0x0408] LPPDMA Software Request Register */ 341 __I uint32_t TRGSTS; /*!< [0x040c] LPPDMA Channel Request Status Register */ 342 __IO uint32_t PRISET; /*!< [0x0410] LPPDMA Fixed Priority Setting Register */ 343 __O uint32_t PRICLR; /*!< [0x0414] LPPDMA Fixed Priority Clear Register */ 344 __IO uint32_t INTEN; /*!< [0x0418] LPPDMA Interrupt Enable Register */ 345 __IO uint32_t INTSTS; /*!< [0x041c] LPPDMA Interrupt Status Register */ 346 __IO uint32_t ABTSTS; /*!< [0x0420] LPPDMA Channel Read/Write Target Abort Flag Register */ 347 __IO uint32_t TDSTS; /*!< [0x0424] LPPDMA Channel Transfer Done Flag Register */ 348 __IO uint32_t ALIGN; /*!< [0x0428] LPPDMA Transfer Alignment Status Register */ 349 __I uint32_t TACTSTS; /*!< [0x042c] LPPDMA Transfer Active Flag Register */ 350 __I uint32_t RESERVE1[3]; 351 __IO uint32_t SCATBA; /*!< [0x043c] LPPDMA Scatter-gather Descriptor Table Base Address Register */ 352 __I uint32_t RESERVE2[8]; 353 __IO uint32_t CHRST; /*!< [0x0460] LPPDMA Channel Reset Register */ 354 __I uint32_t RESERVE3[7]; 355 __IO uint32_t REQSEL0_3; /*!< [0x0480] LPPDMA Request Source Select Register 0 */ 356 357 } LPPDMA_T; 358 359 /** 360 @addtogroup LPPDMA_CONST LPPDMA Bit Field Definition 361 Constant Definitions for LPPDMA Controller 362 @{ */ 363 364 #define LPPDMA_DSCT_CTL_OPMODE_Pos (0) /*!< LPDSCT_T::CTL: OPMODE Position */ 365 #define LPPDMA_DSCT_CTL_OPMODE_Msk (0x3ul << LPPDMA_DSCT_CTL_OPMODE_Pos) /*!< LPDSCT_T::CTL: OPMODE Mask */ 366 367 #define LPPDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< LPDSCT_T::CTL: TXTYPE Position */ 368 #define LPPDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << LPPDMA_DSCT_CTL_TXTYPE_Pos) /*!< LPDSCT_T::CTL: TXTYPE Mask */ 369 370 #define LPPDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< LPDSCT_T::CTL: BURSIZE Position */ 371 #define LPPDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << LPPDMA_DSCT_CTL_BURSIZE_Pos) /*!< LPDSCT_T::CTL: BURSIZE Mask */ 372 373 #define LPPDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< LPDSCT_T::CTL: TBINTDIS Position */ 374 #define LPPDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << LPPDMA_DSCT_CTL_TBINTDIS_Pos) /*!< LPDSCT_T::CTL: TBINTDIS Mask */ 375 376 #define LPPDMA_DSCT_CTL_SAINC_Pos (8) /*!< LPDSCT_T::CTL: SAINC Position */ 377 #define LPPDMA_DSCT_CTL_SAINC_Msk (0x3ul << LPPDMA_DSCT_CTL_SAINC_Pos) /*!< LPDSCT_T::CTL: SAINC Mask */ 378 379 #define LPPDMA_DSCT_CTL_DAINC_Pos (10) /*!< LPDSCT_T::CTL: DAINC Position */ 380 #define LPPDMA_DSCT_CTL_DAINC_Msk (0x3ul << LPPDMA_DSCT_CTL_DAINC_Pos) /*!< LPDSCT_T::CTL: DAINC Mask */ 381 382 #define LPPDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< LPDSCT_T::CTL: TXWIDTH Position */ 383 #define LPPDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << LPPDMA_DSCT_CTL_TXWIDTH_Pos) /*!< LPDSCT_T::CTL: TXWIDTH Mask */ 384 385 #define LPPDMA_DSCT_CTL_TXCNT_Pos (16) /*!< LPDSCT_T::CTL: TXCNT Position */ 386 #define LPPDMA_DSCT_CTL_TXCNT_Msk (0xfffful << LPPDMA_DSCT_CTL_TXCNT_Pos) /*!< LPDSCT_T::CTL: TXCNT Mask */ 387 388 #define LPPDMA_DSCT_SA_SA_Pos (0) /*!< LPDSCT_T::SA: SA Position */ 389 #define LPPDMA_DSCT_SA_SA_Msk (0xfffffffful << LPPDMA_DSCT_SA_SA_Pos) /*!< LPDSCT_T::SA: SA Mask */ 390 391 #define LPPDMA_DSCT_DA_DA_Pos (0) /*!< LPDSCT_T::DA: DA Position */ 392 #define LPPDMA_DSCT_DA_DA_Msk (0xfffffffful << LPPDMA_DSCT_DA_DA_Pos) /*!< LPDSCT_T::DA: DA Mask */ 393 394 #define LPPDMA_DSCT_NEXT_NEXT_Pos (0) /*!< LPDSCT_T::NEXT: NEXT Position */ 395 #define LPPDMA_DSCT_NEXT_NEXT_Msk (0xfffful << LPPDMA_DSCT_NEXT_NEXT_Pos) /*!< LPDSCT_T::NEXT: NEXT Mask */ 396 397 #define LPPDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< LPDSCT_T::NEXT: EXENEXT Position */ 398 #define LPPDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << LPPDMA_DSCT_NEXT_EXENEXT_Pos) /*!< LPDSCT_T::NEXT: EXENEXT Mask */ 399 400 #define LPPDMA_CURSCAT_CURADDR_Pos (0) /*!< LPPDMA_T::CURSCAT: CURADDR Position */ 401 #define LPPDMA_CURSCAT_CURADDR_Msk (0xfffffffful << LPPDMA_CURSCAT_CURADDR_Pos) /*!< LPPDMA_T::CURSCAT: CURADDR Mask */ 402 403 #define LPPDMA_CHCTL_CHENn_Pos (0) /*!< LPPDMA_T::CHCTL: CHENn Position */ 404 #define LPPDMA_CHCTL_CHENn_Msk (0xful << LPPDMA_CHCTL_CHENn_Pos) /*!< LPPDMA_T::CHCTL: CHENn Mask */ 405 406 #define LPPDMA_PAUSE_PAUSEn_Pos (0) /*!< LPPDMA_T::PAUSE: PAUSEn Position */ 407 #define LPPDMA_PAUSE_PAUSEn_Msk (0xful << LPPDMA_PAUSE_PAUSEn_Pos) /*!< LPPDMA_T::PAUSE: PAUSEn Mask */ 408 409 #define LPPDMA_SWREQ_SWREQn_Pos (0) /*!< LPPDMA_T::SWREQ: SWREQn Position */ 410 #define LPPDMA_SWREQ_SWREQn_Msk (0xful << LPPDMA_SWREQ_SWREQn_Pos) /*!< LPPDMA_T::SWREQ: SWREQn Mask */ 411 412 #define LPPDMA_TRGSTS_REQSTSn_Pos (0) /*!< LPPDMA_T::TRGSTS: REQSTSn Position */ 413 #define LPPDMA_TRGSTS_REQSTSn_Msk (0xful << LPPDMA_TRGSTS_REQSTSn_Pos) /*!< LPPDMA_T::TRGSTS: REQSTSn Mask */ 414 415 #define LPPDMA_PRISET_FPRISETn_Pos (0) /*!< LPPDMA_T::PRISET: FPRISETn Position */ 416 #define LPPDMA_PRISET_FPRISETn_Msk (0xful << LPPDMA_PRISET_FPRISETn_Pos) /*!< LPPDMA_T::PRISET: FPRISETn Mask */ 417 418 #define LPPDMA_PRICLR_FPRICLRn_Pos (0) /*!< LPPDMA_T::PRICLR: FPRICLRn Position */ 419 #define LPPDMA_PRICLR_FPRICLRn_Msk (0xful << LPPDMA_PRICLR_FPRICLRn_Pos) /*!< LPPDMA_T::PRICLR: FPRICLRn Mask */ 420 421 #define LPPDMA_INTEN_INTENn_Pos (0) /*!< LPPDMA_T::INTEN: INTENn Position */ 422 #define LPPDMA_INTEN_INTENn_Msk (0xful << LPPDMA_INTEN_INTENn_Pos) /*!< LPPDMA_T::INTEN: INTENn Mask */ 423 424 #define LPPDMA_INTSTS_ABTIF_Pos (0) /*!< LPPDMA_T::INTSTS: ABTIF Position */ 425 #define LPPDMA_INTSTS_ABTIF_Msk (0x1ul << LPPDMA_INTSTS_ABTIF_Pos) /*!< LPPDMA_T::INTSTS: ABTIF Mask */ 426 427 #define LPPDMA_INTSTS_TDIF_Pos (1) /*!< LPPDMA_T::INTSTS: TDIF Position */ 428 #define LPPDMA_INTSTS_TDIF_Msk (0x1ul << LPPDMA_INTSTS_TDIF_Pos) /*!< LPPDMA_T::INTSTS: TDIF Mask */ 429 430 #define LPPDMA_INTSTS_ALIGNF_Pos (2) /*!< LPPDMA_T::INTSTS: ALIGNF Position */ 431 #define LPPDMA_INTSTS_ALIGNF_Msk (0x1ul << LPPDMA_INTSTS_ALIGNF_Pos) /*!< LPPDMA_T::INTSTS: ALIGNF Mask */ 432 433 #define LPPDMA_INTSTS_WKF_Pos (3) /*!< LPPDMA_T::INTSTS: WKF Position */ 434 #define LPPDMA_INTSTS_WKF_Msk (0x1ul << LPPDMA_INTSTS_WKF_Pos) /*!< LPPDMA_T::INTSTS: WKF Mask */ 435 436 #define LPPDMA_ABTSTS_ABTIF0_Pos (0) /*!< LPPDMA_T::ABTSTS: ABTIF0 Position */ 437 #define LPPDMA_ABTSTS_ABTIF0_Msk (0x1ul << LPPDMA_ABTSTS_ABTIF0_Pos) /*!< LPPDMA_T::ABTSTS: ABTIF0 Mask */ 438 439 #define LPPDMA_ABTSTS_ABTIF1_Pos (1) /*!< LPPDMA_T::ABTSTS: ABTIF1 Position */ 440 #define LPPDMA_ABTSTS_ABTIF1_Msk (0x1ul << LPPDMA_ABTSTS_ABTIF1_Pos) /*!< LPPDMA_T::ABTSTS: ABTIF1 Mask */ 441 442 #define LPPDMA_ABTSTS_ABTIF2_Pos (2) /*!< LPPDMA_T::ABTSTS: ABTIF2 Position */ 443 #define LPPDMA_ABTSTS_ABTIF2_Msk (0x1ul << LPPDMA_ABTSTS_ABTIF2_Pos) /*!< LPPDMA_T::ABTSTS: ABTIF2 Mask */ 444 445 #define LPPDMA_ABTSTS_ABTIF3_Pos (3) /*!< LPPDMA_T::ABTSTS: ABTIF3 Position */ 446 #define LPPDMA_ABTSTS_ABTIF3_Msk (0x1ul << LPPDMA_ABTSTS_ABTIF3_Pos) /*!< LPPDMA_T::ABTSTS: ABTIF3 Mask */ 447 448 #define LPPDMA_TDSTS_TDIF0_Pos (0) /*!< LPPDMA_T::TDSTS: TDIF0 Position */ 449 #define LPPDMA_TDSTS_TDIF0_Msk (0x1ul << LPPDMA_TDSTS_TDIF0_Pos) /*!< LPPDMA_T::TDSTS: TDIF0 Mask */ 450 451 #define LPPDMA_TDSTS_TDIF1_Pos (1) /*!< LPPDMA_T::TDSTS: TDIF1 Position */ 452 #define LPPDMA_TDSTS_TDIF1_Msk (0x1ul << LPPDMA_TDSTS_TDIF1_Pos) /*!< LPPDMA_T::TDSTS: TDIF1 Mask */ 453 454 #define LPPDMA_TDSTS_TDIF2_Pos (2) /*!< LPPDMA_T::TDSTS: TDIF2 Position */ 455 #define LPPDMA_TDSTS_TDIF2_Msk (0x1ul << LPPDMA_TDSTS_TDIF2_Pos) /*!< LPPDMA_T::TDSTS: TDIF2 Mask */ 456 457 #define LPPDMA_TDSTS_TDIF3_Pos (3) /*!< LPPDMA_T::TDSTS: TDIF3 Position */ 458 #define LPPDMA_TDSTS_TDIF3_Msk (0x1ul << LPPDMA_TDSTS_TDIF3_Pos) /*!< LPPDMA_T::TDSTS: TDIF3 Mask */ 459 460 #define LPPDMA_ALIGN_ALIGNn_Pos (0) /*!< LPPDMA_T::ALIGN: ALIGNn Position */ 461 #define LPPDMA_ALIGN_ALIGNn_Msk (0xful << LPPDMA_ALIGN_ALIGNn_Pos) /*!< LPPDMA_T::ALIGN: ALIGNn Mask */ 462 463 #define LPPDMA_TACTSTS_TXACTFn_Pos (0) /*!< LPPDMA_T::TACTSTS: TXACTFn Position */ 464 #define LPPDMA_TACTSTS_TXACTFn_Msk (0xful << LPPDMA_TACTSTS_TXACTFn_Pos) /*!< LPPDMA_T::TACTSTS: TXACTFn Mask */ 465 466 #define LPPDMA_SCATBA_SCATBA_Pos (16) /*!< LPPDMA_T::SCATBA: SCATBA Position */ 467 #define LPPDMA_SCATBA_SCATBA_Msk (0xfffful << LPPDMA_SCATBA_SCATBA_Pos) /*!< LPPDMA_T::SCATBA: SCATBA Mask */ 468 469 #define LPPDMA_CHRST_CHnRST_Pos (0) /*!< LPPDMA_T::CHRST: CHnRST Position */ 470 #define LPPDMA_CHRST_CHnRST_Msk (0xful << LPPDMA_CHRST_CHnRST_Pos) /*!< LPPDMA_T::CHRST: CHnRST Mask */ 471 472 #define LPPDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< LPPDMA_T::REQSEL0_3: REQSRC0 Position */ 473 #define LPPDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << LPPDMA_REQSEL0_3_REQSRC0_Pos) /*!< LPPDMA_T::REQSEL0_3: REQSRC0 Mask */ 474 475 #define LPPDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< LPPDMA_T::REQSEL0_3: REQSRC1 Position */ 476 #define LPPDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << LPPDMA_REQSEL0_3_REQSRC1_Pos) /*!< LPPDMA_T::REQSEL0_3: REQSRC1 Mask */ 477 478 #define LPPDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< LPPDMA_T::REQSEL0_3: REQSRC2 Position */ 479 #define LPPDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << LPPDMA_REQSEL0_3_REQSRC2_Pos) /*!< LPPDMA_T::REQSEL0_3: REQSRC2 Mask */ 480 481 #define LPPDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< LPPDMA_T::REQSEL0_3: REQSRC3 Position */ 482 #define LPPDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << LPPDMA_REQSEL0_3_REQSRC3_Pos) /*!< LPPDMA_T::REQSEL0_3: REQSRC3 Mask */ 483 484 /**@}*/ /* LPPDMA_CONST */ 485 /**@}*/ /* end of LPPDMA register group */ 486 /**@}*/ /* end of REGISTER group */ 487 488 #if defined ( __CC_ARM ) 489 #pragma no_anon_unions 490 #endif 491 492 #endif /* __LPPDMA_REG_H__ */
