1 /**************************************************************************//** 2 * @file lpi2c_reg.h 3 * @version V1.00 4 * @brief LPI2C register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __LPI2C_REG_H__ 10 #define __LPI2C_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** @addtogroup REGISTER Control Register 17 18 @{ 19 20 */ 21 22 23 /*---------------------- Low Power Inter-IC Bus Controller -------------------------*/ 24 /** 25 @addtogroup LPI2C Low Power Inter-IC Bus Controller(LPI2C) 26 Memory Mapped Structure for LPI2C Controller 27 @{ */ 28 29 typedef struct 30 { 31 32 33 /** 34 * @var LPI2C_T::CTL0 35 * Offset: 0x00 LPI2C Control Register 0 36 * --------------------------------------------------------------------------------------------------- 37 * |Bits |Field |Descriptions 38 * | :----: | :----: | :---- | 39 * |[2] |AA |Assert Acknowledge Control 40 * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter 41 * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line 42 * |[3] |SI |LPI2C Interrupt Flag 43 * | | |When a new LPI2C state is present in the LPI2C_STATUS0 register, the SI flag is set by hardware 44 * | | |If bit INTEN (LPI2C_CTL0 [7]) is set, the LPI2C interrupt is requested 45 * | | |SI must be cleared by software 46 * | | |Clear SI by writing 1 to this bit. 47 * |[4] |STO |LPI2C STOP Control 48 * | | |In Master mode, setting STO to transmit a STOP condition to bus then LPI2C will check the bus condition if a STOP condition is detected 49 * | | |This bit will be cleared by hardware automatically. 50 * |[5] |STA |LPI2C START Control 51 * | | |Setting STA to logic 1 to enter Master mode, the LPI2C hardware sends a START or repeat START condition to bus when the bus is free. 52 * |[6] |LPI2CEN |LPI2C Controller Enable Bit 53 * | | |Set to enable LPI2C serial function controller 54 * | | |When LPI2CEN=1 the LPI2C serial function enable 55 * | | |The multi-function pin function must set to SDA, and SCL of LPI2C function first. 56 * | | |0 = LPI2C controller Disabled. 57 * | | |1 = LPI2C controller Enabled. 58 * |[7] |INTEN |Enable Interrupt 59 * | | |0 = LPI2C interrupt Disabled. 60 * | | |1 = LPI2C interrupt Enabled. 61 * @var LPI2C_T::ADDR0 62 * Offset: 0x04 LPI2C Slave Address Register0 63 * --------------------------------------------------------------------------------------------------- 64 * |Bits |Field |Descriptions 65 * | :----: | :----: | :---- | 66 * |[0] |GC |General Call Function 67 * | | |0 = General Call function Disabled. 68 * | | |1 = General Call function Enabled. 69 * |[7:1] |ADDR |LPI2C Address 70 * | | |The content of this register is irrelevant when LPI2C is in Master mode 71 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 72 * | | |The LPI2C hardware will react if either of the address is matched. 73 * | | |Note: When software set 7'h000, the address cannot be used. 74 * @var LPI2C_T::DAT 75 * Offset: 0x08 LPI2C Data Register 76 * --------------------------------------------------------------------------------------------------- 77 * |Bits |Field |Descriptions 78 * | :----: | :----: | :---- | 79 * |[7:0] |DAT |LPI2C Data 80 * | | |Bit [7:0] is located with the 8-bit transferred/received data of LPI2C serial port. 81 * @var LPI2C_T::STATUS0 82 * Offset: 0x0C LPI2C Status Register 0 83 * --------------------------------------------------------------------------------------------------- 84 * |Bits |Field |Descriptions 85 * | :----: | :----: | :---- | 86 * |[7:0] |STATUS |LPI2C Status 87 * | | |The three least significant bits are always 0 88 * | | |The five most significant bits contain the status code 89 * | | |There are 28 possible status codes 90 * | | |When the content of LPI2C_STATUS0 is F8H, no serial interrupt is requested 91 * | | |Others LPI2C_STATUS0 values correspond to defined LPI2C states 92 * | | |When each of these states is entered, a status interrupt is requested (SI = 1) 93 * | | |A valid status code is present in LPI2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software 94 * | | |In addition, states 00H stands for a Bus Error 95 * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame 96 * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. 97 * @var LPI2C_T::CLKDIV 98 * Offset: 0x10 LPI2C Clock Divided Register 99 * --------------------------------------------------------------------------------------------------- 100 * |Bits |Field |Descriptions 101 * | :----: | :----: | :---- | 102 * |[9:0] |DIVIDER |LPI2C Clock Divider 103 * | | |Indicates the LPI2C clock rate: Data Baud Rate of LPI2C = (system clock) / (4x (DIVDER+1)). 104 * | | |Note: The minimum value of DIVIDER is 4. 105 * |[15:12] |NFCNT |Noise Filter Count 106 * | | |The register bits control the input filter width. 107 * | | |If the pulse width is narrower than the setting((3+N)*PCLK), it will be ignored. 108 * | | |0 = Filter width 3*PCLK 109 * | | |1 = Filter width 4*PCLK 110 * | | |N = Filter width (3+N)*PCKL 111 * | | |Note: Filter width Min :3*PCLK, Max : 18*PCLK 112 * @var LPI2C_T::TOCTL 113 * Offset: 0x14 LPI2C Time-out Control Register 114 * --------------------------------------------------------------------------------------------------- 115 * |Bits |Field |Descriptions 116 * | :----: | :----: | :---- | 117 * |[0] |TOIF |Time-out Flag 118 * | | |This bit is set by hardware when LPI2C time-out happened and it can interrupt CPU if LPI2C interrupt enable bit (INTEN) is set to 1. 119 * | | |Note: Software can write 1 to clear this bit. 120 * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4 121 * | | |When enabled, the time-out period is extended 4 times. 122 * | | |0 = Time-out period is extend 4 times Disabled. 123 * | | |1 = Time-out period is extend 4 times Enabled. 124 * |[2] |TOCEN |Time-out Counter Enable Bit 125 * | | |When enabled, the 14-bit time-out counter will start counting when SI is cleared 126 * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 127 * | | |0 = Time-out counter Disabled. 128 * | | |1 = Time-out counter Enabled. 129 * @var LPI2C_T::ADDR1 130 * Offset: 0x18 LPI2C Slave Address Register1 131 * --------------------------------------------------------------------------------------------------- 132 * |Bits |Field |Descriptions 133 * | :----: | :----: | :---- | 134 * |[0] |GC |General Call Function 135 * | | |0 = General Call function Disabled. 136 * | | |1 = General Call function Enabled. 137 * |[7:1] |ADDR |LPI2C Address 138 * | | |The content of this register is irrelevant when LPI2C is in Master mode 139 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 140 * | | |The LPI2C hardware will react if either of the address is matched. 141 * | | |Note: When software set 7'h000, the address cannot be used. 142 * @var LPI2C_T::ADDR2 143 * Offset: 0x1C LPI2C Slave Address Register2 144 * --------------------------------------------------------------------------------------------------- 145 * |Bits |Field |Descriptions 146 * | :----: | :----: | :---- | 147 * |[0] |GC |General Call Function 148 * | | |0 = General Call function Disabled. 149 * | | |1 = General Call function Enabled. 150 * |[7:1] |ADDR |LPI2C Address 151 * | | |The content of this register is irrelevant when LPI2C is in Master mode 152 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 153 * | | |The LPI2C hardware will react if either of the address is matched. 154 * | | |Note: When software set 7'h000, the address cannot be used. 155 * @var LPI2C_T::ADDR3 156 * Offset: 0x20 LPI2C Slave Address Register3 157 * --------------------------------------------------------------------------------------------------- 158 * |Bits |Field |Descriptions 159 * | :----: | :----: | :---- | 160 * |[0] |GC |General Call Function 161 * | | |0 = General Call function Disabled. 162 * | | |1 = General Call function Enabled. 163 * |[7:1] |ADDR |LPI2C Address 164 * | | |The content of this register is irrelevant when LPI2C is in Master mode 165 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 166 * | | |The LPI2C hardware will react if either of the address is matched. 167 * | | |Note: When software set 7'h000, the address cannot be used. 168 * @var LPI2C_T::ADDRMSK0 169 * Offset: 0x24 LPI2C Slave Address Mask Register0 170 * --------------------------------------------------------------------------------------------------- 171 * |Bits |Field |Descriptions 172 * | :----: | :----: | :---- | 173 * |[7:1] |ADDRMSK |LPI2C Address Mask 174 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 175 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 176 * | | |LPI2C bus controllers support multiple address recognition with four address mask register 177 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 178 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 179 * @var LPI2C_T::ADDRMSK1 180 * Offset: 0x28 LPI2C Slave Address Mask Register1 181 * --------------------------------------------------------------------------------------------------- 182 * |Bits |Field |Descriptions 183 * | :----: | :----: | :---- | 184 * |[7:1] |ADDRMSK |LPI2C Address Mask 185 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 186 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 187 * | | |LPI2C bus controllers support multiple address recognition with four address mask register 188 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 189 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 190 * @var LPI2C_T::ADDRMSK2 191 * Offset: 0x2C LPI2C Slave Address Mask Register2 192 * --------------------------------------------------------------------------------------------------- 193 * |Bits |Field |Descriptions 194 * | :----: | :----: | :---- | 195 * |[7:1] |ADDRMSK |LPI2C Address Mask 196 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 197 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 198 * | | |LPI2C bus controllers support multiple address recognition with four address mask register 199 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 200 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 201 * @var LPI2C_T::ADDRMSK3 202 * Offset: 0x30 LPI2C Slave Address Mask Register3 203 * --------------------------------------------------------------------------------------------------- 204 * |Bits |Field |Descriptions 205 * | :----: | :----: | :---- | 206 * |[7:1] |ADDRMSK |LPI2C Address Mask 207 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 208 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 209 * | | |LPI2C bus controllers support multiple address recognition with four address mask register 210 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 211 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 212 * @var LPI2C_T::WKCTL 213 * Offset: 0x3C LPI2C Wake-up Control Register 214 * --------------------------------------------------------------------------------------------------- 215 * |Bits |Field |Descriptions 216 * | :----: | :----: | :---- | 217 * |[0] |WKEN |LPI2C Wake-up Enable Bit 218 * | | |0 = LPI2C wake-up function Disabled. 219 * | | |1 = LPI2C wake-up function Enabled. 220 * | | |Note: This is for slave address match wakeup. 221 * |[7] |NHDBUSEN |LPI2C No Hold BUS Enable Bit 222 * | | |0 = LPI2C hold bus after wake-up. 223 * | | |1= LPI2C don't hold bus after wake-up. 224 * | | |Note: LPI2C could respond when WKIF event is not clear, it may cause error data transmitted or received 225 * | | |If data transmitted or received when WKIF event is not clear, user must reset LPI2C controller and execute the original operation again. 226 * @var LPI2C_T::WKSTS 227 * Offset: 0x40 LPI2C Wake-up Status Register 228 * --------------------------------------------------------------------------------------------------- 229 * |Bits |Field |Descriptions 230 * | :----: | :----: | :---- | 231 * |[0] |WKIF |LPI2C Wake-up Flag 232 * | | |When chip is woken up from Power-down mode by LPI2C, this bit is set to 1 233 * | | |Software can write 1 to clear this bit. 234 * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done 235 * | | |0 = The ACK bit cycle of address match frame isn't done. 236 * | | |1 = The ACK bit cycle of address match frame is done in power-down. 237 * | | |Note: This bit cannot release WKIF. Software can write 1 to clear this bit. 238 * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame 239 * | | |0 = Write command be record on the address match wakeup frame. 240 * | | |1 = Read command be record on the address match wakeup frame. 241 * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit. 242 * @var LPI2C_T::CTL1 243 * Offset: 0x44 LPI2C Control Register 1 244 * --------------------------------------------------------------------------------------------------- 245 * |Bits |Field |Descriptions 246 * | :----: | :----: | :---- | 247 * |[0] |TXPDMAEN |LPPDMA Transmit Channel Available 248 * | | |0 = Transmit LPPDMA function Disabled. 249 * | | |1 = Transmit LPPDMA function Enabled. 250 * |[1] |RXPDMAEN |LPPDMA Receive Channel Available 251 * | | |0 = Receive LPPDMA function Disabled. 252 * | | |1 = Receive LPPDMA function Enabled. 253 * |[2] |PDMARST |LPPDMA Reset 254 * | | |0 = No effect. 255 * | | |1 = Reset the LPI2C request to LPPDMA. 256 * |[8] |PDMASTR |LPPDMA Stretch Bit 257 * | | |0 = LPI2C send STOP automatically after LPPDMA transfer done. (only master TX) 258 * | | |1 = LPI2C SCL bus is stretched by hardware after LPPDMA transfer done if the SI is not cleared 259 * | | |(only master TX) 260 * |[10] |SWITCHEN |SCL And SDA Pin Switch Enable Bit 261 * | | |0 = LPI²C use original pin configuration. 262 * | | |1 = LPI²C switch SCL and SDA pin configuration. 263 * | | |Note: Original pin configuration table is shown in Basic Configuration chapter. 264 * @var LPI2C_T::STATUS1 265 * Offset: 0x48 LPI2C Status Register 1 266 * --------------------------------------------------------------------------------------------------- 267 * |Bits |Field |Descriptions 268 * | :----: | :----: | :---- | 269 * |[0] |ADMAT0 |LPI2C Address 0 Match Status 270 * | | |When address 0 is matched, hardware will inform which address used 271 * | | |This bit will set to 1, and software can write 1 to clear this bit. 272 * |[1] |ADMAT1 |LPI2C Address 1 Match Status 273 * | | |When address 1 is matched, hardware will inform which address used 274 * | | |This bit will set to 1, and software can write 1 to clear this bit. 275 * |[2] |ADMAT2 |LPI2C Address 2 Match Status 276 * | | |When address 2 is matched, hardware will inform which address used 277 * | | |This bit will set to 1, and software can write 1 to clear this bit. 278 * |[3] |ADMAT3 |LPI2C Address 3 Match Status 279 * | | |When address 3 is matched, hardware will inform which address used 280 * | | |This bit will set to 1, and software can write 1 to clear this bit. 281 * |[8] |ONBUSY |On Bus Busy (Read Only) 282 * | | |Indicates that a communication is in progress on the bus 283 * | | |It is set by hardware when a START condition is detected 284 * | | |It is cleared by hardware when a STOP condition is detected. 285 * | | |0 = The bus is IDLE (both SCL and SDA High). 286 * | | |1 = The bus is busy. 287 * @var LPI2C_T::TMCTL 288 * Offset: 0x4C LPI2C Timing Configure Control Register 289 * --------------------------------------------------------------------------------------------------- 290 * |Bits |Field |Descriptions 291 * | :----: | :----: | :---- | 292 * |[8:0] |STCTL |Setup Time Configure Control 293 * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. 294 * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK. 295 * | | |Note: Setup time setting should not make SCL output less than three PCLKs. 296 * |[24:16] |HTCTL |Hold Time Configure Control 297 * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. 298 * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK. 299 * @var LPI2C_T::AUTOCTL 300 * Offset: 0x70 LPI2C Automatic Operation Control Register 301 * --------------------------------------------------------------------------------------------------- 302 * |Bits |Field |Descriptions 303 * | :----: | :----: | :---- | 304 * |[3:0] |TGSRCSEL |Low Power Auto-operation Trigger Source Select 305 * | | |0000 = Low Power Auto-operation Trigger Source from LPTMR0. 306 * | | |0001 = Low Power Auto-operation Trigger Source from LPTMR1. 307 * | | |0010 = Low Power Auto-operation Trigger Source from TTMR0. 308 * | | |0011 = Low Power Auto-operation Trigger Source from TTMR1. 309 * | | |0100 = Low Power Auto-operation Trigger Source from WKIOA0(GPA0). 310 * | | |0101 = Low Power Auto-operation Trigger Source from WKIOB0(GPB0). 311 * | | |0110 = Low Power Auto-operation Trigger Source from WKIOC0(GPC0). 312 * | | |0111 = Low Power Auto-operation Trigger Source from WKIOD0(GPD0). 313 * | | |1000 = Low Power Auto-operation Trigger Source from Software setting SWTRG(LPI2C_AUTOCTL[31]) to 1. 314 * | | |1001~1111 = Reserved. 315 * |[4] |TRGEN |Trigger Source Enable bit 316 * | | |0 = LPI2C trigger source disable. 317 * | | |1 = LPI2C trigger source enable. 318 * |[5] |TXWKEN |TX Transfer Count Match Wakeup Enable bit 319 * | | |0 = Power off after TX transfer count matches TXCNT. 320 * | | |1 = Wakeup after TX transfer count matches TXCNT. 321 * |[6] |RXWKEN |RX Transfer Count Match Wakeup Enable bit 322 * | | |0 = Power off after RX transfer count matches RXCNT. 323 * | | |1 = Wakeup after RX transfer count matches RXCNT. 324 * |[7] |NACKWKEN |Receive Slave NACK Wakeup Enable bit 325 * | | |0 = Stop after receiving NACK. 326 * | | |1 = Wakeup after receiving NACK. 327 * |[10:8] |AUTOMODE |Auto-operation Mode Select 328 * | | |000 = No auto-operation. 329 * | | |001 = Auto TXPDMA transfer mode. 330 * | | |010 = Auto RXPDMA transfer mode. 331 * | | |011 = Random Read mode, repeat start between TX/RX. 332 * | | |100 = Random Read mode, stop and start between TX/RX. 333 * | | |Others = Reserved. 334 * |[31] |SWTRG |Auto-operation Mode Software Trigger Bit 335 * | | |0 = No operation. 336 * | | |1 = Software trigger auto-operattion. 337 * | | |Note: TGSRCSEL(LPI2C_AUTOCTL[3:0]) need to be set to 0x8 first 338 * @var LPI2C_T::AUTOSTS 339 * Offset: 0x74 LPI2C Automatic Operation Status Register 340 * --------------------------------------------------------------------------------------------------- 341 * |Bits |Field |Descriptions 342 * | :----: | :----: | :---- | 343 * |[0] |TXWKF |TX Transfer Count Match Wakeup Flag 344 * | | |When chip is woken up from Power-down mode by LPI2C TX transfer count match, this bit is set to 1 345 * | | |Software can write 1 to clear this bit. 346 * |[1] |RXWKF |RX Transfer Count Match Wakeup Flag 347 * | | |When chip is woken up from Power-down mode by LPI2C RX transfer count match, this bit is set to 1 348 * | | |Software can write 1 to clear this bit. 349 * |[2] |ERRORWKF |Error Condition Wakeup Flag 350 * | | |When chip is woken up from Power-down mode by LPI2C receiving NACK from slave, running into bus error or arbitration lost, this bit is set to 1 351 * | | |Software can write 1 to clear this bit. 352 * |[8] |TXFINISH |Automatic Operation TX Finish Flag 353 * | | |AOFINISH is set when finishing one round of auto operation(Automode = 1), but it will not issue interrupt 354 * | | |Software can write 1 to clear this bit. 355 * |[9] |RXFINISH |Automatic Operation RX Finish Flag 356 * | | |RXFINISH is set when finishing one round of auto operation(Automode = 2/3/4), but it will not issue interrupt 357 * | | |Software can write 1 to clear this bit. 358 * |[10] |ERRORIF |ERROR Interrupt Flag 359 * | | |When LPI2C receiving NACK from slave, running into bus error or arbitration lost, this bit is set to 1 360 * | | |Software can write 1 to clear this bit. 361 * |[24] |AOFINISH |Automatic Operation Finish Flag 362 * | | |AOFINISH is set when finishing one round of auto operation, but it will not issue interrupt 363 * | | |Software can write 1 to clear this bit. 364 * |[31] |BUSY |Busy Flag 365 * | | |When chip is woken up and this bit is set to 1, it means that there are one or more requests from trigger source during transfer 366 * | | |Software can write 1 to clear this bit. 367 * @var LPI2C_T::AUTOCNT 368 * Offset: 0x78 LPI2C Automatic Operation Transfer Count Register 369 * --------------------------------------------------------------------------------------------------- 370 * |Bits |Field |Descriptions 371 * | :----: | :----: | :---- | 372 * |[7:0] |TXCNT |TX Transfer Count 373 * | | |Bit [7:0] is set for TXPDMA and Random Read transfer mode 374 * | | |TXCNT represents the required number of the transfer, the real transfer count is TXCNT + 1 375 * | | |The maximum transfer count is 255 + 1. 376 * |[23:16] |RXCNT |RX Transfer Count 377 * | | |Bit [23:16] is set for RXPDMA and Random Read transfer mode 378 * | | |RXCNT represents the required number of the transfer, the real transfer count is RXCNT + 1 379 * | | |The maximum transfer count is 255 + 1. 380 */ 381 __IO uint32_t CTL0; /*!< [0x0000] LPI2C Control Register 0 */ 382 __IO uint32_t ADDR0; /*!< [0x0004] LPI2C Slave Address Register0 */ 383 __IO uint32_t DAT; /*!< [0x0008] LPI2C Data Register */ 384 __I uint32_t STATUS0; /*!< [0x000c] LPI2C Status Register 0 */ 385 __IO uint32_t CLKDIV; /*!< [0x0010] LPI2C Clock Divided Register */ 386 __IO uint32_t TOCTL; /*!< [0x0014] LPI2C Time-out Control Register */ 387 __IO uint32_t ADDR1; /*!< [0x0018] LPI2C Slave Address Register1 */ 388 __IO uint32_t ADDR2; /*!< [0x001c] LPI2C Slave Address Register2 */ 389 __IO uint32_t ADDR3; /*!< [0x0020] LPI2C Slave Address Register3 */ 390 __IO uint32_t ADDRMSK0; /*!< [0x0024] LPI2C Slave Address Mask Register0 */ 391 __IO uint32_t ADDRMSK1; /*!< [0x0028] LPI2C Slave Address Mask Register1 */ 392 __IO uint32_t ADDRMSK2; /*!< [0x002c] LPI2C Slave Address Mask Register2 */ 393 __IO uint32_t ADDRMSK3; /*!< [0x0030] LPI2C Slave Address Mask Register3 */ 394 __I uint32_t RESERVE0[2]; 395 __IO uint32_t WKCTL; /*!< [0x003c] LPI2C Wake-up Control Register */ 396 __IO uint32_t WKSTS; /*!< [0x0040] LPI2C Wake-up Status Register */ 397 __IO uint32_t CTL1; /*!< [0x0044] LPI2C Control Register 1 */ 398 __IO uint32_t STATUS1; /*!< [0x0048] LPI2C Status Register 1 */ 399 __IO uint32_t TMCTL; /*!< [0x004c] LPI2C Timing Configure Control Register */ 400 __I uint32_t RESERVE1[8]; 401 __IO uint32_t AUTOCTL; /*!< [0x0070] LPI2C Automatic Operation Control Register */ 402 __IO uint32_t AUTOSTS; /*!< [0x0074] LPI2C Automatic Operation Status Register */ 403 __IO uint32_t AUTOCNT; /*!< [0x0078] LPI2C Automatic Operation Transfer Count Register */ 404 405 } LPI2C_T; 406 407 /** 408 @addtogroup LPI2C_CONST LPI2C Bit Field Definition 409 Constant Definitions for LPI2C Controller 410 @{ */ 411 412 #define LPI2C_CTL0_AA_Pos (2) /*!< LPI2C_T::CTL0: AA Position */ 413 #define LPI2C_CTL0_AA_Msk (0x1ul << LPI2C_CTL0_AA_Pos) /*!< LPI2C_T::CTL0: AA Mask */ 414 415 #define LPI2C_CTL0_SI_Pos (3) /*!< LPI2C_T::CTL0: SI Position */ 416 #define LPI2C_CTL0_SI_Msk (0x1ul << LPI2C_CTL0_SI_Pos) /*!< LPI2C_T::CTL0: SI Mask */ 417 418 #define LPI2C_CTL0_STO_Pos (4) /*!< LPI2C_T::CTL0: STO Position */ 419 #define LPI2C_CTL0_STO_Msk (0x1ul << LPI2C_CTL0_STO_Pos) /*!< LPI2C_T::CTL0: STO Mask */ 420 421 #define LPI2C_CTL0_STA_Pos (5) /*!< LPI2C_T::CTL0: STA Position */ 422 #define LPI2C_CTL0_STA_Msk (0x1ul << LPI2C_CTL0_STA_Pos) /*!< LPI2C_T::CTL0: STA Mask */ 423 424 #define LPI2C_CTL0_LPI2CEN_Pos (6) /*!< LPI2C_T::CTL0: LPI2CEN Position */ 425 #define LPI2C_CTL0_LPI2CEN_Msk (0x1ul << LPI2C_CTL0_LPI2CEN_Pos) /*!< LPI2C_T::CTL0: LPI2CEN Mask */ 426 427 #define LPI2C_CTL0_INTEN_Pos (7) /*!< LPI2C_T::CTL0: INTEN Position */ 428 #define LPI2C_CTL0_INTEN_Msk (0x1ul << LPI2C_CTL0_INTEN_Pos) /*!< LPI2C_T::CTL0: INTEN Mask */ 429 430 #define LPI2C_ADDR0_GC_Pos (0) /*!< LPI2C_T::ADDR0: GC Position */ 431 #define LPI2C_ADDR0_GC_Msk (0x1ul << LPI2C_ADDR0_GC_Pos) /*!< LPI2C_T::ADDR0: GC Mask */ 432 433 #define LPI2C_ADDR0_ADDR_Pos (1) /*!< LPI2C_T::ADDR0: ADDR Position */ 434 #define LPI2C_ADDR0_ADDR_Msk (0x7ful << LPI2C_ADDR0_ADDR_Pos) /*!< LPI2C_T::ADDR0: ADDR Mask */ 435 436 #define LPI2C_DAT_DAT_Pos (0) /*!< LPI2C_T::DAT: DAT Position */ 437 #define LPI2C_DAT_DAT_Msk (0xfful << LPI2C_DAT_DAT_Pos) /*!< LPI2C_T::DAT: DAT Mask */ 438 439 #define LPI2C_STATUS0_STATUS_Pos (0) /*!< LPI2C_T::STATUS0: STATUS Position */ 440 #define LPI2C_STATUS0_STATUS_Msk (0xfful << LPI2C_STATUS0_STATUS_Pos) /*!< LPI2C_T::STATUS0: STATUS Mask */ 441 442 #define LPI2C_CLKDIV_DIVIDER_Pos (0) /*!< LPI2C_T::CLKDIV: DIVIDER Position */ 443 #define LPI2C_CLKDIV_DIVIDER_Msk (0x3fful << LPI2C_CLKDIV_DIVIDER_Pos) /*!< LPI2C_T::CLKDIV: DIVIDER Mask */ 444 445 #define LPI2C_CLKDIV_NFCNT_Pos (12) /*!< LPI2C_T::CLKDIV: NFCNT Position */ 446 #define LPI2C_CLKDIV_NFCNT_Msk (0xful << LPI2C_CLKDIV_NFCNT_Pos) /*!< LPI2C_T::CLKDIV: NFCNT Mask */ 447 448 #define LPI2C_TOCTL_TOIF_Pos (0) /*!< LPI2C_T::TOCTL: TOIF Position */ 449 #define LPI2C_TOCTL_TOIF_Msk (0x1ul << LPI2C_TOCTL_TOIF_Pos) /*!< LPI2C_T::TOCTL: TOIF Mask */ 450 451 #define LPI2C_TOCTL_TOCDIV4_Pos (1) /*!< LPI2C_T::TOCTL: TOCDIV4 Position */ 452 #define LPI2C_TOCTL_TOCDIV4_Msk (0x1ul << LPI2C_TOCTL_TOCDIV4_Pos) /*!< LPI2C_T::TOCTL: TOCDIV4 Mask */ 453 454 #define LPI2C_TOCTL_TOCEN_Pos (2) /*!< LPI2C_T::TOCTL: TOCEN Position */ 455 #define LPI2C_TOCTL_TOCEN_Msk (0x1ul << LPI2C_TOCTL_TOCEN_Pos) /*!< LPI2C_T::TOCTL: TOCEN Mask */ 456 457 #define LPI2C_ADDR1_GC_Pos (0) /*!< LPI2C_T::ADDR1: GC Position */ 458 #define LPI2C_ADDR1_GC_Msk (0x1ul << LPI2C_ADDR1_GC_Pos) /*!< LPI2C_T::ADDR1: GC Mask */ 459 460 #define LPI2C_ADDR1_ADDR_Pos (1) /*!< LPI2C_T::ADDR1: ADDR Position */ 461 #define LPI2C_ADDR1_ADDR_Msk (0x7ful << LPI2C_ADDR1_ADDR_Pos) /*!< LPI2C_T::ADDR1: ADDR Mask */ 462 463 #define LPI2C_ADDR2_GC_Pos (0) /*!< LPI2C_T::ADDR2: GC Position */ 464 #define LPI2C_ADDR2_GC_Msk (0x1ul << LPI2C_ADDR2_GC_Pos) /*!< LPI2C_T::ADDR2: GC Mask */ 465 466 #define LPI2C_ADDR2_ADDR_Pos (1) /*!< LPI2C_T::ADDR2: ADDR Position */ 467 #define LPI2C_ADDR2_ADDR_Msk (0x7ful << LPI2C_ADDR2_ADDR_Pos) /*!< LPI2C_T::ADDR2: ADDR Mask */ 468 469 #define LPI2C_ADDR3_GC_Pos (0) /*!< LPI2C_T::ADDR3: GC Position */ 470 #define LPI2C_ADDR3_GC_Msk (0x1ul << LPI2C_ADDR3_GC_Pos) /*!< LPI2C_T::ADDR3: GC Mask */ 471 472 #define LPI2C_ADDR3_ADDR_Pos (1) /*!< LPI2C_T::ADDR3: ADDR Position */ 473 #define LPI2C_ADDR3_ADDR_Msk (0x7ful << LPI2C_ADDR3_ADDR_Pos) /*!< LPI2C_T::ADDR3: ADDR Mask */ 474 475 #define LPI2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< LPI2C_T::ADDRMSK0: ADDRMSK Position */ 476 #define LPI2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << LPI2C_ADDRMSK0_ADDRMSK_Pos) /*!< LPI2C_T::ADDRMSK0: ADDRMSK Mask */ 477 478 #define LPI2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< LPI2C_T::ADDRMSK1: ADDRMSK Position */ 479 #define LPI2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << LPI2C_ADDRMSK1_ADDRMSK_Pos) /*!< LPI2C_T::ADDRMSK1: ADDRMSK Mask */ 480 481 #define LPI2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< LPI2C_T::ADDRMSK2: ADDRMSK Position */ 482 #define LPI2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << LPI2C_ADDRMSK2_ADDRMSK_Pos) /*!< LPI2C_T::ADDRMSK2: ADDRMSK Mask */ 483 484 #define LPI2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< LPI2C_T::ADDRMSK3: ADDRMSK Position */ 485 #define LPI2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << LPI2C_ADDRMSK3_ADDRMSK_Pos) /*!< LPI2C_T::ADDRMSK3: ADDRMSK Mask */ 486 487 #define LPI2C_WKCTL_WKEN_Pos (0) /*!< LPI2C_T::WKCTL: WKEN Position */ 488 #define LPI2C_WKCTL_WKEN_Msk (0x1ul << LPI2C_WKCTL_WKEN_Pos) /*!< LPI2C_T::WKCTL: WKEN Mask */ 489 490 #define LPI2C_WKCTL_NHDBUSEN_Pos (7) /*!< LPI2C_T::WKCTL: NHDBUSEN Position */ 491 #define LPI2C_WKCTL_NHDBUSEN_Msk (0x1ul << LPI2C_WKCTL_NHDBUSEN_Pos) /*!< LPI2C_T::WKCTL: NHDBUSEN Mask */ 492 493 #define LPI2C_WKSTS_WKIF_Pos (0) /*!< LPI2C_T::WKSTS: WKIF Position */ 494 #define LPI2C_WKSTS_WKIF_Msk (0x1ul << LPI2C_WKSTS_WKIF_Pos) /*!< LPI2C_T::WKSTS: WKIF Mask */ 495 496 #define LPI2C_WKSTS_WKAKDONE_Pos (1) /*!< LPI2C_T::WKSTS: WKAKDONE Position */ 497 #define LPI2C_WKSTS_WKAKDONE_Msk (0x1ul << LPI2C_WKSTS_WKAKDONE_Pos) /*!< LPI2C_T::WKSTS: WKAKDONE Mask */ 498 499 #define LPI2C_WKSTS_WRSTSWK_Pos (2) /*!< LPI2C_T::WKSTS: WRSTSWK Position */ 500 #define LPI2C_WKSTS_WRSTSWK_Msk (0x1ul << LPI2C_WKSTS_WRSTSWK_Pos) /*!< LPI2C_T::WKSTS: WRSTSWK Mask */ 501 502 #define LPI2C_CTL1_TXPDMAEN_Pos (0) /*!< LPI2C_T::CTL1: TXPDMAEN Position */ 503 #define LPI2C_CTL1_TXPDMAEN_Msk (0x1ul << LPI2C_CTL1_TXPDMAEN_Pos) /*!< LPI2C_T::CTL1: TXPDMAEN Mask */ 504 505 #define LPI2C_CTL1_RXPDMAEN_Pos (1) /*!< LPI2C_T::CTL1: RXPDMAEN Position */ 506 #define LPI2C_CTL1_RXPDMAEN_Msk (0x1ul << LPI2C_CTL1_RXPDMAEN_Pos) /*!< LPI2C_T::CTL1: RXPDMAEN Mask */ 507 508 #define LPI2C_CTL1_PDMARST_Pos (2) /*!< LPI2C_T::CTL1: PDMARST Position */ 509 #define LPI2C_CTL1_PDMARST_Msk (0x1ul << LPI2C_CTL1_PDMARST_Pos) /*!< LPI2C_T::CTL1: PDMARST Mask */ 510 511 #define LPI2C_CTL1_PDMASTR_Pos (8) /*!< LPI2C_T::CTL1: PDMASTR Position */ 512 #define LPI2C_CTL1_PDMASTR_Msk (0x1ul << LPI2C_CTL1_PDMASTR_Pos) /*!< LPI2C_T::CTL1: PDMASTR Mask */ 513 514 #define LPI2C_CTL1_SWITCHEN_Pos (10) /*!< LPI2C_T::CTL1: SWITCHEN Position */ 515 #define LPI2C_CTL1_SWITCHEN_Msk (0x1ul << LPI2C_CTL1_SWITCHEN_Pos) /*!< LPI2C_T::CTL1: SWITCHEN Mask */ 516 517 #define LPI2C_STATUS1_ADMAT0_Pos (0) /*!< LPI2C_T::STATUS1: ADMAT0 Position */ 518 #define LPI2C_STATUS1_ADMAT0_Msk (0x1ul << LPI2C_STATUS1_ADMAT0_Pos) /*!< LPI2C_T::STATUS1: ADMAT0 Mask */ 519 520 #define LPI2C_STATUS1_ADMAT1_Pos (1) /*!< LPI2C_T::STATUS1: ADMAT1 Position */ 521 #define LPI2C_STATUS1_ADMAT1_Msk (0x1ul << LPI2C_STATUS1_ADMAT1_Pos) /*!< LPI2C_T::STATUS1: ADMAT1 Mask */ 522 523 #define LPI2C_STATUS1_ADMAT2_Pos (2) /*!< LPI2C_T::STATUS1: ADMAT2 Position */ 524 #define LPI2C_STATUS1_ADMAT2_Msk (0x1ul << LPI2C_STATUS1_ADMAT2_Pos) /*!< LPI2C_T::STATUS1: ADMAT2 Mask */ 525 526 #define LPI2C_STATUS1_ADMAT3_Pos (3) /*!< LPI2C_T::STATUS1: ADMAT3 Position */ 527 #define LPI2C_STATUS1_ADMAT3_Msk (0x1ul << LPI2C_STATUS1_ADMAT3_Pos) /*!< LPI2C_T::STATUS1: ADMAT3 Mask */ 528 529 #define LPI2C_STATUS1_ONBUSY_Pos (8) /*!< LPI2C_T::STATUS1: ONBUSY Position */ 530 #define LPI2C_STATUS1_ONBUSY_Msk (0x1ul << LPI2C_STATUS1_ONBUSY_Pos) /*!< LPI2C_T::STATUS1: ONBUSY Mask */ 531 532 #define LPI2C_TMCTL_STCTL_Pos (0) /*!< LPI2C_T::TMCTL: STCTL Position */ 533 #define LPI2C_TMCTL_STCTL_Msk (0x1fful << LPI2C_TMCTL_STCTL_Pos) /*!< LPI2C_T::TMCTL: STCTL Mask */ 534 535 #define LPI2C_TMCTL_HTCTL_Pos (16) /*!< LPI2C_T::TMCTL: HTCTL Position */ 536 #define LPI2C_TMCTL_HTCTL_Msk (0x1fful << LPI2C_TMCTL_HTCTL_Pos) /*!< LPI2C_T::TMCTL: HTCTL Mask */ 537 538 #define LPI2C_AUTOCTL_TGSRCSEL_Pos (0) /*!< LPI2C_T::AUTOCTL: TGSRCSEL Position */ 539 #define LPI2C_AUTOCTL_TGSRCSEL_Msk (0xful << LPI2C_AUTOCTL_TGSRCSEL_Pos) /*!< LPI2C_T::AUTOCTL: TGSRCSEL Mask */ 540 541 #define LPI2C_AUTOCTL_TRGEN_Pos (4) /*!< LPI2C_T::AUTOCTL: TRGEN Position */ 542 #define LPI2C_AUTOCTL_TRGEN_Msk (0x1ul << LPI2C_AUTOCTL_TRGEN_Pos) /*!< LPI2C_T::AUTOCTL: TRGEN Mask */ 543 544 #define LPI2C_AUTOCTL_TXWKEN_Pos (5) /*!< LPI2C_T::AUTOCTL: TXWKEN Position */ 545 #define LPI2C_AUTOCTL_TXWKEN_Msk (0x1ul << LPI2C_AUTOCTL_TXWKEN_Pos) /*!< LPI2C_T::AUTOCTL: TXWKEN Mask */ 546 547 #define LPI2C_AUTOCTL_RXWKEN_Pos (6) /*!< LPI2C_T::AUTOCTL: RXWKEN Position */ 548 #define LPI2C_AUTOCTL_RXWKEN_Msk (0x1ul << LPI2C_AUTOCTL_RXWKEN_Pos) /*!< LPI2C_T::AUTOCTL: RXWKEN Mask */ 549 550 #define LPI2C_AUTOCTL_NACKWKEN_Pos (7) /*!< LPI2C_T::AUTOCTL: NACKWKEN Position */ 551 #define LPI2C_AUTOCTL_NACKWKEN_Msk (0x1ul << LPI2C_AUTOCTL_NACKWKEN_Pos) /*!< LPI2C_T::AUTOCTL: NACKWKEN Mask */ 552 553 #define LPI2C_AUTOCTL_AUTOMODE_Pos (8) /*!< LPI2C_T::AUTOCTL: AUTOMODE Position */ 554 #define LPI2C_AUTOCTL_AUTOMODE_Msk (0x7ul << LPI2C_AUTOCTL_AUTOMODE_Pos) /*!< LPI2C_T::AUTOCTL: AUTOMODE Mask */ 555 556 #define LPI2C_AUTOCTL_SWTRG_Pos (31) /*!< LPI2C_T::AUTOCTL: SWTRG Position */ 557 #define LPI2C_AUTOCTL_SWTRG_Msk (0x1ul << LPI2C_AUTOCTL_SWTRG_Pos) /*!< LPI2C_T::AUTOCTL: SWTRG Mask */ 558 559 #define LPI2C_AUTOSTS_TXWKF_Pos (0) /*!< LPI2C_T::AUTOSTS: TXWKF Position */ 560 #define LPI2C_AUTOSTS_TXWKF_Msk (0x1ul << LPI2C_AUTOSTS_TXWKF_Pos) /*!< LPI2C_T::AUTOSTS: TXWKF Mask */ 561 562 #define LPI2C_AUTOSTS_RXWKF_Pos (1) /*!< LPI2C_T::AUTOSTS: RXWKF Position */ 563 #define LPI2C_AUTOSTS_RXWKF_Msk (0x1ul << LPI2C_AUTOSTS_RXWKF_Pos) /*!< LPI2C_T::AUTOSTS: RXWKF Mask */ 564 565 #define LPI2C_AUTOSTS_ERRORWKF_Pos (2) /*!< LPI2C_T::AUTOSTS: ERRORWKF Position */ 566 #define LPI2C_AUTOSTS_ERRORWKF_Msk (0x1ul << LPI2C_AUTOSTS_ERRORWKF_Pos) /*!< LPI2C_T::AUTOSTS: ERRORWKF Mask */ 567 568 #define LPI2C_AUTOSTS_TXFINISH_Pos (8) /*!< LPI2C_T::AUTOSTS: TXFINISH Position */ 569 #define LPI2C_AUTOSTS_TXFINISH_Msk (0x1ul << LPI2C_AUTOSTS_TXFINISH_Pos) /*!< LPI2C_T::AUTOSTS: TXFINISH Mask */ 570 571 #define LPI2C_AUTOSTS_RXFINISH_Pos (9) /*!< LPI2C_T::AUTOSTS: RXFINISH Position */ 572 #define LPI2C_AUTOSTS_RXFINISH_Msk (0x1ul << LPI2C_AUTOSTS_RXFINISH_Pos) /*!< LPI2C_T::AUTOSTS: RXFINISH Mask */ 573 574 #define LPI2C_AUTOSTS_ERRORIF_Pos (10) /*!< LPI2C_T::AUTOSTS: ERRORIF Position */ 575 #define LPI2C_AUTOSTS_ERRORIF_Msk (0x1ul << LPI2C_AUTOSTS_ERRORIF_Pos) /*!< LPI2C_T::AUTOSTS: ERRORIF Mask */ 576 577 #define LPI2C_AUTOSTS_AOFINISH_Pos (24) /*!< LPI2C_T::AUTOSTS: AOFINISH Position */ 578 #define LPI2C_AUTOSTS_AOFINISH_Msk (0x1ul << LPI2C_AUTOSTS_AOFINISH_Pos) /*!< LPI2C_T::AUTOSTS: AOFINISH Mask */ 579 580 #define LPI2C_AUTOSTS_BUSY_Pos (31) /*!< LPI2C_T::AUTOSTS: BUSY Position */ 581 #define LPI2C_AUTOSTS_BUSY_Msk (0x1ul << LPI2C_AUTOSTS_BUSY_Pos) /*!< LPI2C_T::AUTOSTS: BUSY Mask */ 582 583 #define LPI2C_AUTOCNT_TXCNT_Pos (0) /*!< LPI2C_T::AUTOCNT: TXCNT Position */ 584 #define LPI2C_AUTOCNT_TXCNT_Msk (0xfful << LPI2C_AUTOCNT_TXCNT_Pos) /*!< LPI2C_T::AUTOCNT: TXCNT Mask */ 585 586 #define LPI2C_AUTOCNT_RXCNT_Pos (16) /*!< LPI2C_T::AUTOCNT: RXCNT Position */ 587 #define LPI2C_AUTOCNT_RXCNT_Msk (0xfful << LPI2C_AUTOCNT_RXCNT_Pos) /*!< LPI2C_T::AUTOCNT: RXCNT Mask */ 588 589 /**@}*/ /* LPI2C_CONST */ 590 /**@}*/ /* end of LPI2C register group */ 591 /**@}*/ /* end of REGISTER group */ 592 593 #if defined ( __CC_ARM ) 594 #pragma no_anon_unions 595 #endif 596 597 #endif /* __LPI2C_REG_H__ */
