1 /**************************************************************************//** 2 * @file lpgpio_reg.h 3 * @version V1.00 4 * @brief LPGPIO register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __LPGPIO_REG_H__ 10 #define __LPGPIO_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup LPGPIO Low Power General Purpose Input/Output Controller (LPGPIO) 23 Memory Mapped Structure for LPGPIO Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var LPGPIO_T::MODE 32 * Offset: 0x00 LPIOn Mode Control 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |MODE0 |LPIOn I/O Pin Mode Control 37 * | | |Determine each I/O mode of LPIOn pins. 38 * | | |0 = LPIOn is in Input mode. 39 * | | |1 = LPIOn is in Push-pull Output mode. 40 * |[1] |MODE1 |LPIOn I/O Pin Mode Control 41 * | | |Determine each I/O mode of LPIOn pins. 42 * | | |0 = LPIOn is in Input mode. 43 * | | |1 = LPIOn is in Push-pull Output mode. 44 * |[2] |MODE2 |LPIOn I/O Pin Mode Control 45 * | | |Determine each I/O mode of LPIOn pins. 46 * | | |0 = LPIOn is in Input mode. 47 * | | |1 = LPIOn is in Push-pull Output mode. 48 * |[3] |MODE3 |LPIOn I/O Pin Mode Control 49 * | | |Determine each I/O mode of LPIOn pins. 50 * | | |0 = LPIOn is in Input mode. 51 * | | |1 = LPIOn is in Push-pull Output mode. 52 * |[4] |MODE4 |LPIOn I/O Pin Mode Control 53 * | | |Determine each I/O mode of LPIOn pins. 54 * | | |0 = LPIOn is in Input mode. 55 * | | |1 = LPIOn is in Push-pull Output mode. 56 * |[5] |MODE5 |LPIOn I/O Pin Mode Control 57 * | | |Determine each I/O mode of LPIOn pins. 58 * | | |0 = LPIOn is in Input mode. 59 * | | |1 = LPIOn is in Push-pull Output mode. 60 * |[6] |MODE6 |LPIOn I/O Pin Mode Control 61 * | | |Determine each I/O mode of LPIOn pins. 62 * | | |0 = LPIOn is in Input mode. 63 * | | |1 = LPIOn is in Push-pull Output mode. 64 * |[7] |MODE7 |LPIOn I/O Pin Mode Control 65 * | | |Determine each I/O mode of LPIOn pins. 66 * | | |0 = LPIOn is in Input mode. 67 * | | |1 = LPIOn is in Push-pull Output mode. 68 * |[31] |LPPDMA_EN |LPPDMA Enable Bit 69 * | | |This bit is used to enable LPPDMA to access LPGPIO when chip is in NPD0/1/2/3/4. 70 * | | |0 = LPPDMA cannot access LPGPIO when chip is in NPD0/1/2/3/4. 71 * | | |1 = LPPDMA can access LPGPIO when chip is in NPD0/1/2/3/4. 72 * @var LPGPIO_T::DOUT 73 * Offset: 0x04 LPIOn Data Output Value 74 * --------------------------------------------------------------------------------------------------- 75 * |Bits |Field |Descriptions 76 * | :----: | :----: | :---- | 77 * |[0] |DOUT0 |LPIOn Output Value 78 * | | |Each of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode. 79 * | | |0 = LPIOn will drive Low if the LPIOn pin is configured as Push-pull output mode. 80 * | | |1 = LPIOn will drive High if the LPIOn pin is configured as Push-pull output mode. 81 * |[1] |DOUT1 |LPIOn Output Value 82 * | | |Each of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode. 83 * | | |0 = LPIOn will drive Low if the LPIOn pin is configured as Push-pull output mode. 84 * | | |1 = LPIOn will drive High if the LPIOn pin is configured as Push-pull output mode. 85 * |[2] |DOUT2 |LPIOn Output Value 86 * | | |Each of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode. 87 * | | |0 = LPIOn will drive Low if the LPIOn pin is configured as Push-pull output mode. 88 * | | |1 = LPIOn will drive High if the LPIOn pin is configured as Push-pull output mode. 89 * |[3] |DOUT3 |LPIOn Output Value 90 * | | |Each of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode. 91 * | | |0 = LPIOn will drive Low if the LPIOn pin is configured as Push-pull output mode. 92 * | | |1 = LPIOn will drive High if the LPIOn pin is configured as Push-pull output mode. 93 * |[4] |DOUT4 |LPIOn Output Value 94 * | | |Each of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode. 95 * | | |0 = LPIOn will drive Low if the LPIOn pin is configured as Push-pull output mode. 96 * | | |1 = LPIOn will drive High if the LPIOn pin is configured as Push-pull output mode. 97 * |[5] |DOUT5 |LPIOn Output Value 98 * | | |Each of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode. 99 * | | |0 = LPIOn will drive Low if the LPIOn pin is configured as Push-pull output mode. 100 * | | |1 = LPIOn will drive High if the LPIOn pin is configured as Push-pull output mode. 101 * |[6] |DOUT6 |LPIOn Output Value 102 * | | |Each of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode. 103 * | | |0 = LPIOn will drive Low if the LPIOn pin is configured as Push-pull output mode. 104 * | | |1 = LPIOn will drive High if the LPIOn pin is configured as Push-pull output mode. 105 * |[7] |DOUT7 |LPIOn Output Value 106 * | | |Each of these bits controls the status of a LPIOn pin when the LPIOn is configured as Push-pull output mode. 107 * | | |0 = LPIOn will drive Low if the LPIOn pin is configured as Push-pull output mode. 108 * | | |1 = LPIOn will drive High if the LPIOn pin is configured as Push-pull output mode. 109 * @var LPGPIO_T::PIN 110 * Offset: 0x08 LPIOn Pin Value 111 * --------------------------------------------------------------------------------------------------- 112 * |Bits |Field |Descriptions 113 * | :----: | :----: | :---- | 114 * |[0] |PIN0 |LPIOn Pin Value 115 * | | |Each bit of the register reflects the actual status of the respective Pn pin 116 * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 117 * |[1] |PIN1 |LPIOn Pin Value 118 * | | |Each bit of the register reflects the actual status of the respective Pn pin 119 * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 120 * |[2] |PIN2 |LPIOn Pin Value 121 * | | |Each bit of the register reflects the actual status of the respective Pn pin 122 * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 123 * |[3] |PIN3 |LPIOn Pin Value 124 * | | |Each bit of the register reflects the actual status of the respective Pn pin 125 * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 126 * |[4] |PIN4 |LPIOn Pin Value 127 * | | |Each bit of the register reflects the actual status of the respective Pn pin 128 * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 129 * |[5] |PIN5 |LPIOn Pin Value 130 * | | |Each bit of the register reflects the actual status of the respective Pn pin 131 * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 132 * |[6] |PIN6 |LPIOn Pin Value 133 * | | |Each bit of the register reflects the actual status of the respective Pn pin 134 * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 135 * |[7] |PIN7 |LPIOn Pin Value 136 * | | |Each bit of the register reflects the actual status of the respective Pn pin 137 * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 138 * @var LPGPIO_T::DSRST 139 * Offset: 0x0C LPIOn Data Output Set and Reset Control 140 * --------------------------------------------------------------------------------------------------- 141 * |Bits |Field |Descriptions 142 * | :----: | :----: | :---- | 143 * |[0] |DSET0 |LPIOn Data Ouput Set Control (Write Only) 144 * | | |Writing 1 to each bit can set LPIOn pin output data to 1. 145 * | | |0 = No action. 146 * | | |1 = Reset LPIOn to 1. 147 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 148 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 149 * | | |Note 3 : Writing 1 to DSET[n] will make DOUT[n] reflect the set value. 150 * |[1] |DSET1 |LPIOn Data Ouput Set Control (Write Only) 151 * | | |Writing 1 to each bit can set LPIOn pin output data to 1. 152 * | | |0 = No action. 153 * | | |1 = Reset LPIOn to 1. 154 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 155 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 156 * | | |Note 3 : Writing 1 to DSET[n] will make DOUT[n] reflect the set value. 157 * |[2] |DSET2 |LPIOn Data Ouput Set Control (Write Only) 158 * | | |Writing 1 to each bit can set LPIOn pin output data to 1. 159 * | | |0 = No action. 160 * | | |1 = Reset LPIOn to 1. 161 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 162 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 163 * | | |Note 3 : Writing 1 to DSET[n] will make DOUT[n] reflect the set value. 164 * |[3] |DSET3 |LPIOn Data Ouput Set Control (Write Only) 165 * | | |Writing 1 to each bit can set LPIOn pin output data to 1. 166 * | | |0 = No action. 167 * | | |1 = Reset LPIOn to 1. 168 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 169 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 170 * | | |Note 3 : Writing 1 to DSET[n] will make DOUT[n] reflect the set value. 171 * |[4] |DSET4 |LPIOn Data Ouput Set Control (Write Only) 172 * | | |Writing 1 to each bit can set LPIOn pin output data to 1. 173 * | | |0 = No action. 174 * | | |1 = Reset LPIOn to 1. 175 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 176 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 177 * | | |Note 3 : Writing 1 to DSET[n] will make DOUT[n] reflect the set value. 178 * |[5] |DSET5 |LPIOn Data Ouput Set Control (Write Only) 179 * | | |Writing 1 to each bit can set LPIOn pin output data to 1. 180 * | | |0 = No action. 181 * | | |1 = Reset LPIOn to 1. 182 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 183 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 184 * | | |Note 3 : Writing 1 to DSET[n] will make DOUT[n] reflect the set value. 185 * |[6] |DSET6 |LPIOn Data Ouput Set Control (Write Only) 186 * | | |Writing 1 to each bit can set LPIOn pin output data to 1. 187 * | | |0 = No action. 188 * | | |1 = Reset LPIOn to 1. 189 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 190 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 191 * | | |Note 3 : Writing 1 to DSET[n] will make DOUT[n] reflect the set value. 192 * |[7] |DSET7 |LPIOn Data Ouput Set Control (Write Only) 193 * | | |Writing 1 to each bit can set LPIOn pin output data to 1. 194 * | | |0 = No action. 195 * | | |1 = Reset LPIOn to 1. 196 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 197 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 198 * | | |Note 3 : Writing 1 to DSET[n] will make DOUT[n] reflect the set value. 199 * |[16] |DRESET0 |LPIOn Data Ouput Reset Control (Write Only) 200 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 201 * | | |0 = No action. 202 * | | |1 = Reset LPIOn to 0. 203 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 204 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 205 * | | |Note 3 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 206 * |[17] |DRESET1 |LPIOn Data Ouput Reset Control (Write Only) 207 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 208 * | | |0 = No action. 209 * | | |1 = Reset LPIOn to 0. 210 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 211 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 212 * | | |Note 3 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 213 * |[18] |DRESET2 |LPIOn Data Ouput Reset Control (Write Only) 214 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 215 * | | |0 = No action. 216 * | | |1 = Reset LPIOn to 0. 217 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 218 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 219 * | | |Note 3 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 220 * |[19] |DRESET3 |LPIOn Data Ouput Reset Control (Write Only) 221 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 222 * | | |0 = No action. 223 * | | |1 = Reset LPIOn to 0. 224 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 225 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 226 * | | |Note 3 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 227 * |[20] |DRESET4 |LPIOn Data Ouput Reset Control (Write Only) 228 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 229 * | | |0 = No action. 230 * | | |1 = Reset LPIOn to 0. 231 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 232 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 233 * | | |Note 3 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 234 * |[21] |DRESET5 |LPIOn Data Ouput Reset Control (Write Only) 235 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 236 * | | |0 = No action. 237 * | | |1 = Reset LPIOn to 0. 238 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 239 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 240 * | | |Note 3 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 241 * |[22] |DRESET6 |LPIOn Data Ouput Reset Control (Write Only) 242 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 243 * | | |0 = No action. 244 * | | |1 = Reset LPIOn to 0. 245 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 246 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 247 * | | |Note 3 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 248 * |[23] |DRESET7 |LPIOn Data Ouput Reset Control (Write Only) 249 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 250 * | | |0 = No action. 251 * | | |1 = Reset LPIOn to 0. 252 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 253 * | | |Note 2 : If DRESET[n] and DSET[n] are both set, DSET[n] has higher pirority. 254 * | | |Note 3 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 255 * @var LPGPIO_T::DRST 256 * Offset: 0x10 LPIOn Data Output Reset Control 257 * --------------------------------------------------------------------------------------------------- 258 * |Bits |Field |Descriptions 259 * | :----: | :----: | :---- | 260 * |[0] |DRESET0 |LPIOn Data Ouput Reset Control (Write Only) 261 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 262 * | | |0 = No action. 263 * | | |1 = Reset LPIOn to 0. 264 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 265 * | | |Note 2 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 266 * |[1] |DRESET1 |LPIOn Data Ouput Reset Control (Write Only) 267 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 268 * | | |0 = No action. 269 * | | |1 = Reset LPIOn to 0. 270 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 271 * | | |Note 2 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 272 * |[2] |DRESET2 |LPIOn Data Ouput Reset Control (Write Only) 273 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 274 * | | |0 = No action. 275 * | | |1 = Reset LPIOn to 0. 276 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 277 * | | |Note 2 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 278 * |[3] |DRESET3 |LPIOn Data Ouput Reset Control (Write Only) 279 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 280 * | | |0 = No action. 281 * | | |1 = Reset LPIOn to 0. 282 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 283 * | | |Note 2 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 284 * |[4] |DRESET4 |LPIOn Data Ouput Reset Control (Write Only) 285 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 286 * | | |0 = No action. 287 * | | |1 = Reset LPIOn to 0. 288 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 289 * | | |Note 2 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 290 * |[5] |DRESET5 |LPIOn Data Ouput Reset Control (Write Only) 291 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 292 * | | |0 = No action. 293 * | | |1 = Reset LPIOn to 0. 294 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 295 * | | |Note 2 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 296 * |[6] |DRESET6 |LPIOn Data Ouput Reset Control (Write Only) 297 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 298 * | | |0 = No action. 299 * | | |1 = Reset LPIOn to 0. 300 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 301 * | | |Note 2 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 302 * |[7] |DRESET7 |LPIOn Data Ouput Reset Control (Write Only) 303 * | | |Writing 1 to each bit can reset LPIOn pin output data to 0. 304 * | | |0 = No action. 305 * | | |1 = Reset LPIOn to 0. 306 * | | |Note 1 : This bit field is write only, and reading this field will respond with 0. 307 * | | |Note 2 : Writing 1 to DRESET[n] will make DOUT[n] reflect the reset value. 308 */ 309 __IO uint32_t MODE; /*!< [0x0000] LPIOn Mode Control */ 310 __IO uint32_t DOUT; /*!< [0x0004] LPIOn Data Output Value */ 311 __I uint32_t PIN; /*!< [0x0008] LPIOn Pin Value */ 312 __O uint32_t DSRST; /*!< [0x000c] LPIOn Data Output Set and Reset Control */ 313 __O uint32_t DRST; /*!< [0x0010] LPIOn Data Output Reset Control */ 314 315 } LPGPIO_T; 316 317 /** 318 @addtogroup LPGPIO_CONST LPGPIO Bit Field Definition 319 Constant Definitions for LPGPIO Controller 320 @{ */ 321 322 #define LPGPIO_MODE_MODE0_Pos (0) /*!< LPGPIO_T::MODE: MODE0 Position */ 323 #define LPGPIO_MODE_MODE0_Msk (0x1ul << LPGPIO_MODE_MODE0_Pos) /*!< LPGPIO_T::MODE: MODE0 Mask */ 324 325 #define LPGPIO_MODE_MODE1_Pos (1) /*!< LPGPIO_T::MODE: MODE1 Position */ 326 #define LPGPIO_MODE_MODE1_Msk (0x1ul << LPGPIO_MODE_MODE1_Pos) /*!< LPGPIO_T::MODE: MODE1 Mask */ 327 328 #define LPGPIO_MODE_MODE2_Pos (2) /*!< LPGPIO_T::MODE: MODE2 Position */ 329 #define LPGPIO_MODE_MODE2_Msk (0x1ul << LPGPIO_MODE_MODE2_Pos) /*!< LPGPIO_T::MODE: MODE2 Mask */ 330 331 #define LPGPIO_MODE_MODE3_Pos (3) /*!< LPGPIO_T::MODE: MODE3 Position */ 332 #define LPGPIO_MODE_MODE3_Msk (0x1ul << LPGPIO_MODE_MODE3_Pos) /*!< LPGPIO_T::MODE: MODE3 Mask */ 333 334 #define LPGPIO_MODE_MODE4_Pos (4) /*!< LPGPIO_T::MODE: MODE4 Position */ 335 #define LPGPIO_MODE_MODE4_Msk (0x1ul << LPGPIO_MODE_MODE4_Pos) /*!< LPGPIO_T::MODE: MODE4 Mask */ 336 337 #define LPGPIO_MODE_MODE5_Pos (5) /*!< LPGPIO_T::MODE: MODE5 Position */ 338 #define LPGPIO_MODE_MODE5_Msk (0x1ul << LPGPIO_MODE_MODE5_Pos) /*!< LPGPIO_T::MODE: MODE5 Mask */ 339 340 #define LPGPIO_MODE_MODE6_Pos (6) /*!< LPGPIO_T::MODE: MODE6 Position */ 341 #define LPGPIO_MODE_MODE6_Msk (0x1ul << LPGPIO_MODE_MODE6_Pos) /*!< LPGPIO_T::MODE: MODE6 Mask */ 342 343 #define LPGPIO_MODE_MODE7_Pos (7) /*!< LPGPIO_T::MODE: MODE7 Position */ 344 #define LPGPIO_MODE_MODE7_Msk (0x1ul << LPGPIO_MODE_MODE7_Pos) /*!< LPGPIO_T::MODE: MODE7 Mask */ 345 346 #define LPGPIO_MODE_LPPDMA_EN_Pos (31) /*!< LPGPIO_T::MODE: LPPDMA_EN Position */ 347 #define LPGPIO_MODE_LPPDMA_EN_Msk (0x1ul << LPGPIO_MODE_LPPDMA_EN_Pos) /*!< LPGPIO_T::MODE: LPPDMA_EN Mask */ 348 349 #define LPGPIO_DOUT_DOUT0_Pos (0) /*!< LPGPIO_T::DOUT: DOUT0 Position */ 350 #define LPGPIO_DOUT_DOUT0_Msk (0x1ul << LPGPIO_DOUT_DOUT0_Pos) /*!< LPGPIO_T::DOUT: DOUT0 Mask */ 351 352 #define LPGPIO_DOUT_DOUT1_Pos (1) /*!< LPGPIO_T::DOUT: DOUT1 Position */ 353 #define LPGPIO_DOUT_DOUT1_Msk (0x1ul << LPGPIO_DOUT_DOUT1_Pos) /*!< LPGPIO_T::DOUT: DOUT1 Mask */ 354 355 #define LPGPIO_DOUT_DOUT2_Pos (2) /*!< LPGPIO_T::DOUT: DOUT2 Position */ 356 #define LPGPIO_DOUT_DOUT2_Msk (0x1ul << LPGPIO_DOUT_DOUT2_Pos) /*!< LPGPIO_T::DOUT: DOUT2 Mask */ 357 358 #define LPGPIO_DOUT_DOUT3_Pos (3) /*!< LPGPIO_T::DOUT: DOUT3 Position */ 359 #define LPGPIO_DOUT_DOUT3_Msk (0x1ul << LPGPIO_DOUT_DOUT3_Pos) /*!< LPGPIO_T::DOUT: DOUT3 Mask */ 360 361 #define LPGPIO_DOUT_DOUT4_Pos (4) /*!< LPGPIO_T::DOUT: DOUT4 Position */ 362 #define LPGPIO_DOUT_DOUT4_Msk (0x1ul << LPGPIO_DOUT_DOUT4_Pos) /*!< LPGPIO_T::DOUT: DOUT4 Mask */ 363 364 #define LPGPIO_DOUT_DOUT5_Pos (5) /*!< LPGPIO_T::DOUT: DOUT5 Position */ 365 #define LPGPIO_DOUT_DOUT5_Msk (0x1ul << LPGPIO_DOUT_DOUT5_Pos) /*!< LPGPIO_T::DOUT: DOUT5 Mask */ 366 367 #define LPGPIO_DOUT_DOUT6_Pos (6) /*!< LPGPIO_T::DOUT: DOUT6 Position */ 368 #define LPGPIO_DOUT_DOUT6_Msk (0x1ul << LPGPIO_DOUT_DOUT6_Pos) /*!< LPGPIO_T::DOUT: DOUT6 Mask */ 369 370 #define LPGPIO_DOUT_DOUT7_Pos (7) /*!< LPGPIO_T::DOUT: DOUT7 Position */ 371 #define LPGPIO_DOUT_DOUT7_Msk (0x1ul << LPGPIO_DOUT_DOUT7_Pos) /*!< LPGPIO_T::DOUT: DOUT7 Mask */ 372 373 #define LPGPIO_PIN_PIN0_Pos (0) /*!< LPGPIO_T::PIN: PIN0 Position */ 374 #define LPGPIO_PIN_PIN0_Msk (0x1ul << LPGPIO_PIN_PIN0_Pos) /*!< LPGPIO_T::PIN: PIN0 Mask */ 375 376 #define LPGPIO_PIN_PIN1_Pos (1) /*!< LPGPIO_T::PIN: PIN1 Position */ 377 #define LPGPIO_PIN_PIN1_Msk (0x1ul << LPGPIO_PIN_PIN1_Pos) /*!< LPGPIO_T::PIN: PIN1 Mask */ 378 379 #define LPGPIO_PIN_PIN2_Pos (2) /*!< LPGPIO_T::PIN: PIN2 Position */ 380 #define LPGPIO_PIN_PIN2_Msk (0x1ul << LPGPIO_PIN_PIN2_Pos) /*!< LPGPIO_T::PIN: PIN2 Mask */ 381 382 #define LPGPIO_PIN_PIN3_Pos (3) /*!< LPGPIO_T::PIN: PIN3 Position */ 383 #define LPGPIO_PIN_PIN3_Msk (0x1ul << LPGPIO_PIN_PIN3_Pos) /*!< LPGPIO_T::PIN: PIN3 Mask */ 384 385 #define LPGPIO_PIN_PIN4_Pos (4) /*!< LPGPIO_T::PIN: PIN4 Position */ 386 #define LPGPIO_PIN_PIN4_Msk (0x1ul << LPGPIO_PIN_PIN4_Pos) /*!< LPGPIO_T::PIN: PIN4 Mask */ 387 388 #define LPGPIO_PIN_PIN5_Pos (5) /*!< LPGPIO_T::PIN: PIN5 Position */ 389 #define LPGPIO_PIN_PIN5_Msk (0x1ul << LPGPIO_PIN_PIN5_Pos) /*!< LPGPIO_T::PIN: PIN5 Mask */ 390 391 #define LPGPIO_PIN_PIN6_Pos (6) /*!< LPGPIO_T::PIN: PIN6 Position */ 392 #define LPGPIO_PIN_PIN6_Msk (0x1ul << LPGPIO_PIN_PIN6_Pos) /*!< LPGPIO_T::PIN: PIN6 Mask */ 393 394 #define LPGPIO_PIN_PIN7_Pos (7) /*!< LPGPIO_T::PIN: PIN7 Position */ 395 #define LPGPIO_PIN_PIN7_Msk (0x1ul << LPGPIO_PIN_PIN7_Pos) /*!< LPGPIO_T::PIN: PIN7 Mask */ 396 397 #define LPGPIO_DSRST_DSET0_Pos (0) /*!< LPGPIO_T::DSRST: DSET0 Position */ 398 #define LPGPIO_DSRST_DSET0_Msk (0x1ul << LPGPIO_DSRST_DSET0_Pos) /*!< LPGPIO_T::DSRST: DSET0 Mask */ 399 400 #define LPGPIO_DSRST_DSET1_Pos (1) /*!< LPGPIO_T::DSRST: DSET1 Position */ 401 #define LPGPIO_DSRST_DSET1_Msk (0x1ul << LPGPIO_DSRST_DSET1_Pos) /*!< LPGPIO_T::DSRST: DSET1 Mask */ 402 403 #define LPGPIO_DSRST_DSET2_Pos (2) /*!< LPGPIO_T::DSRST: DSET2 Position */ 404 #define LPGPIO_DSRST_DSET2_Msk (0x1ul << LPGPIO_DSRST_DSET2_Pos) /*!< LPGPIO_T::DSRST: DSET2 Mask */ 405 406 #define LPGPIO_DSRST_DSET3_Pos (3) /*!< LPGPIO_T::DSRST: DSET3 Position */ 407 #define LPGPIO_DSRST_DSET3_Msk (0x1ul << LPGPIO_DSRST_DSET3_Pos) /*!< LPGPIO_T::DSRST: DSET3 Mask */ 408 409 #define LPGPIO_DSRST_DSET4_Pos (4) /*!< LPGPIO_T::DSRST: DSET4 Position */ 410 #define LPGPIO_DSRST_DSET4_Msk (0x1ul << LPGPIO_DSRST_DSET4_Pos) /*!< LPGPIO_T::DSRST: DSET4 Mask */ 411 412 #define LPGPIO_DSRST_DSET5_Pos (5) /*!< LPGPIO_T::DSRST: DSET5 Position */ 413 #define LPGPIO_DSRST_DSET5_Msk (0x1ul << LPGPIO_DSRST_DSET5_Pos) /*!< LPGPIO_T::DSRST: DSET5 Mask */ 414 415 #define LPGPIO_DSRST_DSET6_Pos (6) /*!< LPGPIO_T::DSRST: DSET6 Position */ 416 #define LPGPIO_DSRST_DSET6_Msk (0x1ul << LPGPIO_DSRST_DSET6_Pos) /*!< LPGPIO_T::DSRST: DSET6 Mask */ 417 418 #define LPGPIO_DSRST_DSET7_Pos (7) /*!< LPGPIO_T::DSRST: DSET7 Position */ 419 #define LPGPIO_DSRST_DSET7_Msk (0x1ul << LPGPIO_DSRST_DSET7_Pos) /*!< LPGPIO_T::DSRST: DSET7 Mask */ 420 421 #define LPGPIO_DSRST_DRESET0_Pos (16) /*!< LPGPIO_T::DSRST: DRESET0 Position */ 422 #define LPGPIO_DSRST_DRESET0_Msk (0x1ul << LPGPIO_DSRST_DRESET0_Pos) /*!< LPGPIO_T::DSRST: DRESET0 Mask */ 423 424 #define LPGPIO_DSRST_DRESET1_Pos (17) /*!< LPGPIO_T::DSRST: DRESET1 Position */ 425 #define LPGPIO_DSRST_DRESET1_Msk (0x1ul << LPGPIO_DSRST_DRESET1_Pos) /*!< LPGPIO_T::DSRST: DRESET1 Mask */ 426 427 #define LPGPIO_DSRST_DRESET2_Pos (18) /*!< LPGPIO_T::DSRST: DRESET2 Position */ 428 #define LPGPIO_DSRST_DRESET2_Msk (0x1ul << LPGPIO_DSRST_DRESET2_Pos) /*!< LPGPIO_T::DSRST: DRESET2 Mask */ 429 430 #define LPGPIO_DSRST_DRESET3_Pos (19) /*!< LPGPIO_T::DSRST: DRESET3 Position */ 431 #define LPGPIO_DSRST_DRESET3_Msk (0x1ul << LPGPIO_DSRST_DRESET3_Pos) /*!< LPGPIO_T::DSRST: DRESET3 Mask */ 432 433 #define LPGPIO_DSRST_DRESET4_Pos (20) /*!< LPGPIO_T::DSRST: DRESET4 Position */ 434 #define LPGPIO_DSRST_DRESET4_Msk (0x1ul << LPGPIO_DSRST_DRESET4_Pos) /*!< LPGPIO_T::DSRST: DRESET4 Mask */ 435 436 #define LPGPIO_DSRST_DRESET5_Pos (21) /*!< LPGPIO_T::DSRST: DRESET5 Position */ 437 #define LPGPIO_DSRST_DRESET5_Msk (0x1ul << LPGPIO_DSRST_DRESET5_Pos) /*!< LPGPIO_T::DSRST: DRESET5 Mask */ 438 439 #define LPGPIO_DSRST_DRESET6_Pos (22) /*!< LPGPIO_T::DSRST: DRESET6 Position */ 440 #define LPGPIO_DSRST_DRESET6_Msk (0x1ul << LPGPIO_DSRST_DRESET6_Pos) /*!< LPGPIO_T::DSRST: DRESET6 Mask */ 441 442 #define LPGPIO_DSRST_DRESET7_Pos (23) /*!< LPGPIO_T::DSRST: DRESET7 Position */ 443 #define LPGPIO_DSRST_DRESET7_Msk (0x1ul << LPGPIO_DSRST_DRESET7_Pos) /*!< LPGPIO_T::DSRST: DRESET7 Mask */ 444 445 #define LPGPIO_DRST_DRESET0_Pos (0) /*!< LPGPIO_T::DRST: DRESET0 Position */ 446 #define LPGPIO_DRST_DRESET0_Msk (0x1ul << LPGPIO_DRST_DRESET0_Pos) /*!< LPGPIO_T::DRST: DRESET0 Mask */ 447 448 #define LPGPIO_DRST_DRESET1_Pos (1) /*!< LPGPIO_T::DRST: DRESET1 Position */ 449 #define LPGPIO_DRST_DRESET1_Msk (0x1ul << LPGPIO_DRST_DRESET1_Pos) /*!< LPGPIO_T::DRST: DRESET1 Mask */ 450 451 #define LPGPIO_DRST_DRESET2_Pos (2) /*!< LPGPIO_T::DRST: DRESET2 Position */ 452 #define LPGPIO_DRST_DRESET2_Msk (0x1ul << LPGPIO_DRST_DRESET2_Pos) /*!< LPGPIO_T::DRST: DRESET2 Mask */ 453 454 #define LPGPIO_DRST_DRESET3_Pos (3) /*!< LPGPIO_T::DRST: DRESET3 Position */ 455 #define LPGPIO_DRST_DRESET3_Msk (0x1ul << LPGPIO_DRST_DRESET3_Pos) /*!< LPGPIO_T::DRST: DRESET3 Mask */ 456 457 #define LPGPIO_DRST_DRESET4_Pos (4) /*!< LPGPIO_T::DRST: DRESET4 Position */ 458 #define LPGPIO_DRST_DRESET4_Msk (0x1ul << LPGPIO_DRST_DRESET4_Pos) /*!< LPGPIO_T::DRST: DRESET4 Mask */ 459 460 #define LPGPIO_DRST_DRESET5_Pos (5) /*!< LPGPIO_T::DRST: DRESET5 Position */ 461 #define LPGPIO_DRST_DRESET5_Msk (0x1ul << LPGPIO_DRST_DRESET5_Pos) /*!< LPGPIO_T::DRST: DRESET5 Mask */ 462 463 #define LPGPIO_DRST_DRESET6_Pos (6) /*!< LPGPIO_T::DRST: DRESET6 Position */ 464 #define LPGPIO_DRST_DRESET6_Msk (0x1ul << LPGPIO_DRST_DRESET6_Pos) /*!< LPGPIO_T::DRST: DRESET6 Mask */ 465 466 #define LPGPIO_DRST_DRESET7_Pos (7) /*!< LPGPIO_T::DRST: DRESET7 Position */ 467 #define LPGPIO_DRST_DRESET7_Msk (0x1ul << LPGPIO_DRST_DRESET7_Pos) /*!< LPGPIO_T::DRST: DRESET7 Mask */ 468 469 /**@}*/ /* LPGPIO_CONST */ 470 /**@}*/ /* end of LPGPIO register group */ 471 /**@}*/ /* end of REGISTER group */ 472 473 #if defined ( __CC_ARM ) 474 #pragma no_anon_unions 475 #endif 476 477 #endif /* __LPGPIO_REG_H__ */ 478
