1 /***************************************************************************//** 2 * \file cyip_lpcomp.h 3 * 4 * \brief 5 * LPCOMP IP definitions 6 * 7 * \note 8 * Generator version: 1.6.0.409 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _CYIP_LPCOMP_H_ 29 #define _CYIP_LPCOMP_H_ 30 31 #include "cyip_headers.h" 32 33 /******************************************************************************* 34 * LPCOMP 35 *******************************************************************************/ 36 37 #define LPCOMP_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Low Power Comparators (LPCOMP) 41 */ 42 typedef struct { 43 __IOM uint32_t CONFIG; /*!< 0x00000000 LPCOMP Configuration Register */ 44 __IM uint32_t STATUS; /*!< 0x00000004 LPCOMP Status Register */ 45 __IM uint32_t RESERVED[2]; 46 __IOM uint32_t INTR; /*!< 0x00000010 LPCOMP Interrupt request register */ 47 __IOM uint32_t INTR_SET; /*!< 0x00000014 LPCOMP Interrupt set register */ 48 __IOM uint32_t INTR_MASK; /*!< 0x00000018 LPCOMP Interrupt request mask */ 49 __IM uint32_t INTR_MASKED; /*!< 0x0000001C LPCOMP Interrupt request masked */ 50 __IM uint32_t RESERVED1[8]; 51 __IOM uint32_t CMP0_CTRL; /*!< 0x00000040 Comparator 0 control Register */ 52 __IM uint32_t RESERVED2[3]; 53 __IOM uint32_t CMP0_SW; /*!< 0x00000050 Comparator 0 switch control */ 54 __IOM uint32_t CMP0_SW_CLEAR; /*!< 0x00000054 Comparator 0 switch control clear */ 55 __IM uint32_t RESERVED3[10]; 56 __IOM uint32_t CMP1_CTRL; /*!< 0x00000080 Comparator 1 control Register */ 57 __IM uint32_t RESERVED4[3]; 58 __IOM uint32_t CMP1_SW; /*!< 0x00000090 Comparator 1 switch control */ 59 __IOM uint32_t CMP1_SW_CLEAR; /*!< 0x00000094 Comparator 1 switch control clear */ 60 } LPCOMP_V1_Type; /*!< Size = 152 (0x98) */ 61 62 63 /* LPCOMP.CONFIG */ 64 #define LPCOMP_CONFIG_LPREF_EN_Pos 30UL 65 #define LPCOMP_CONFIG_LPREF_EN_Msk 0x40000000UL 66 #define LPCOMP_CONFIG_ENABLED_Pos 31UL 67 #define LPCOMP_CONFIG_ENABLED_Msk 0x80000000UL 68 /* LPCOMP.STATUS */ 69 #define LPCOMP_STATUS_OUT0_Pos 0UL 70 #define LPCOMP_STATUS_OUT0_Msk 0x1UL 71 #define LPCOMP_STATUS_OUT1_Pos 16UL 72 #define LPCOMP_STATUS_OUT1_Msk 0x10000UL 73 /* LPCOMP.INTR */ 74 #define LPCOMP_INTR_COMP0_Pos 0UL 75 #define LPCOMP_INTR_COMP0_Msk 0x1UL 76 #define LPCOMP_INTR_COMP1_Pos 1UL 77 #define LPCOMP_INTR_COMP1_Msk 0x2UL 78 /* LPCOMP.INTR_SET */ 79 #define LPCOMP_INTR_SET_COMP0_Pos 0UL 80 #define LPCOMP_INTR_SET_COMP0_Msk 0x1UL 81 #define LPCOMP_INTR_SET_COMP1_Pos 1UL 82 #define LPCOMP_INTR_SET_COMP1_Msk 0x2UL 83 /* LPCOMP.INTR_MASK */ 84 #define LPCOMP_INTR_MASK_COMP0_MASK_Pos 0UL 85 #define LPCOMP_INTR_MASK_COMP0_MASK_Msk 0x1UL 86 #define LPCOMP_INTR_MASK_COMP1_MASK_Pos 1UL 87 #define LPCOMP_INTR_MASK_COMP1_MASK_Msk 0x2UL 88 /* LPCOMP.INTR_MASKED */ 89 #define LPCOMP_INTR_MASKED_COMP0_MASKED_Pos 0UL 90 #define LPCOMP_INTR_MASKED_COMP0_MASKED_Msk 0x1UL 91 #define LPCOMP_INTR_MASKED_COMP1_MASKED_Pos 1UL 92 #define LPCOMP_INTR_MASKED_COMP1_MASKED_Msk 0x2UL 93 /* LPCOMP.CMP0_CTRL */ 94 #define LPCOMP_CMP0_CTRL_MODE0_Pos 0UL 95 #define LPCOMP_CMP0_CTRL_MODE0_Msk 0x3UL 96 #define LPCOMP_CMP0_CTRL_HYST0_Pos 5UL 97 #define LPCOMP_CMP0_CTRL_HYST0_Msk 0x20UL 98 #define LPCOMP_CMP0_CTRL_INTTYPE0_Pos 6UL 99 #define LPCOMP_CMP0_CTRL_INTTYPE0_Msk 0xC0UL 100 #define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos 10UL 101 #define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk 0x400UL 102 #define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Pos 11UL 103 #define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk 0x800UL 104 /* LPCOMP.CMP0_SW */ 105 #define LPCOMP_CMP0_SW_CMP0_IP0_Pos 0UL 106 #define LPCOMP_CMP0_SW_CMP0_IP0_Msk 0x1UL 107 #define LPCOMP_CMP0_SW_CMP0_AP0_Pos 1UL 108 #define LPCOMP_CMP0_SW_CMP0_AP0_Msk 0x2UL 109 #define LPCOMP_CMP0_SW_CMP0_BP0_Pos 2UL 110 #define LPCOMP_CMP0_SW_CMP0_BP0_Msk 0x4UL 111 #define LPCOMP_CMP0_SW_CMP0_IN0_Pos 4UL 112 #define LPCOMP_CMP0_SW_CMP0_IN0_Msk 0x10UL 113 #define LPCOMP_CMP0_SW_CMP0_AN0_Pos 5UL 114 #define LPCOMP_CMP0_SW_CMP0_AN0_Msk 0x20UL 115 #define LPCOMP_CMP0_SW_CMP0_BN0_Pos 6UL 116 #define LPCOMP_CMP0_SW_CMP0_BN0_Msk 0x40UL 117 #define LPCOMP_CMP0_SW_CMP0_VN0_Pos 7UL 118 #define LPCOMP_CMP0_SW_CMP0_VN0_Msk 0x80UL 119 /* LPCOMP.CMP0_SW_CLEAR */ 120 #define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Pos 0UL 121 #define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Msk 0x1UL 122 #define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Pos 1UL 123 #define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Msk 0x2UL 124 #define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Pos 2UL 125 #define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Msk 0x4UL 126 #define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Pos 4UL 127 #define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Msk 0x10UL 128 #define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Pos 5UL 129 #define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Msk 0x20UL 130 #define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Pos 6UL 131 #define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Msk 0x40UL 132 #define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Pos 7UL 133 #define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Msk 0x80UL 134 /* LPCOMP.CMP1_CTRL */ 135 #define LPCOMP_CMP1_CTRL_MODE1_Pos 0UL 136 #define LPCOMP_CMP1_CTRL_MODE1_Msk 0x3UL 137 #define LPCOMP_CMP1_CTRL_HYST1_Pos 5UL 138 #define LPCOMP_CMP1_CTRL_HYST1_Msk 0x20UL 139 #define LPCOMP_CMP1_CTRL_INTTYPE1_Pos 6UL 140 #define LPCOMP_CMP1_CTRL_INTTYPE1_Msk 0xC0UL 141 #define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos 10UL 142 #define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk 0x400UL 143 #define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Pos 11UL 144 #define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk 0x800UL 145 /* LPCOMP.CMP1_SW */ 146 #define LPCOMP_CMP1_SW_CMP1_IP1_Pos 0UL 147 #define LPCOMP_CMP1_SW_CMP1_IP1_Msk 0x1UL 148 #define LPCOMP_CMP1_SW_CMP1_AP1_Pos 1UL 149 #define LPCOMP_CMP1_SW_CMP1_AP1_Msk 0x2UL 150 #define LPCOMP_CMP1_SW_CMP1_BP1_Pos 2UL 151 #define LPCOMP_CMP1_SW_CMP1_BP1_Msk 0x4UL 152 #define LPCOMP_CMP1_SW_CMP1_IN1_Pos 4UL 153 #define LPCOMP_CMP1_SW_CMP1_IN1_Msk 0x10UL 154 #define LPCOMP_CMP1_SW_CMP1_AN1_Pos 5UL 155 #define LPCOMP_CMP1_SW_CMP1_AN1_Msk 0x20UL 156 #define LPCOMP_CMP1_SW_CMP1_BN1_Pos 6UL 157 #define LPCOMP_CMP1_SW_CMP1_BN1_Msk 0x40UL 158 #define LPCOMP_CMP1_SW_CMP1_VN1_Pos 7UL 159 #define LPCOMP_CMP1_SW_CMP1_VN1_Msk 0x80UL 160 /* LPCOMP.CMP1_SW_CLEAR */ 161 #define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Pos 0UL 162 #define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Msk 0x1UL 163 #define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Pos 1UL 164 #define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Msk 0x2UL 165 #define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Pos 2UL 166 #define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Msk 0x4UL 167 #define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Pos 4UL 168 #define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Msk 0x10UL 169 #define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Pos 5UL 170 #define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Msk 0x20UL 171 #define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Pos 6UL 172 #define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Msk 0x40UL 173 #define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Pos 7UL 174 #define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Msk 0x80UL 175 176 177 #endif /* _CYIP_LPCOMP_H_ */ 178 179 180 /* [] END OF FILE */ 181
