1 /**************************************************************************//** 2 * @file lpadc_reg.h 3 * @version V1.00 4 * @brief LPADC register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __LPADC_REG_H__ 10 #define __LPADC_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup LPADC Low Power Analog to Digital Converter (LPADC) 23 Memory Mapped Structure for LPADC Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var LPADC_T::ADDR[32] 32 * Offset: 0x00/0x04/0x08/0x0C/0x10/0x14/0x18/0x1C/0x20/0x24/0x28/0x2C/0x30/0x34/0x38/0x3C/0x40/0x44/0x48/0x4C/0x50/0x54/0x58/0x5C/0x60/0x64/0x68/0x6C/0x70/0x74/0x78/0x7C ADC Data Register 0~31 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[15:0] |RSLT |A/D Conversion Result (Read Only) 37 * | | |This field contains conversion result of ADC. 38 * |[16] |OVERRUN |Overrun Flag (Read Only) 39 * | | |If converted data in RSLT bits has not been read before new conversion result is loaded to this register, OVERRUN bit is set to 1 40 * | | |It is cleared by hardware after ADDR register is read. 41 * | | |0 = Data in RSLT bits is not overwritten. 42 * | | |1 = Data in RSLT bits is overwritten. 43 * |[17] |VALID |Valid Flag (Read Only) 44 * | | |This bit will be set to 1 when the conversion of the corresponding channel is completed 45 * | | |This bit will be cleared to 0 by hardware after ADDR register is read. 46 * | | |0 = Data in RSLT bits is not valid. 47 * | | |1 = Data in RSLT bits is valid. 48 * @var LPADC_T::ADCR 49 * Offset: 0x80 ADC Control Register 50 * --------------------------------------------------------------------------------------------------- 51 * |Bits |Field |Descriptions 52 * | :----: | :----: | :---- | 53 * |[0] |ADEN |A/D Converter Enable Bit 54 * | | |0 = A/D converter Disabled. 55 * | | |1 = A/D converter Enabled. 56 * | | |Note: Before starting A/D conversion function, this bit should be set to 1 57 * | | |Clear it to 0 to disable A/D converter analog circuit to save power consumption. 58 * |[1] |ADIE |A/D Interrupt Enable Bit 59 * | | |A/D conversion end interrupt request is generated if ADIE bit is set to 1. 60 * | | |0 = A/D conversion end interrupt function Disabled. 61 * | | |1 = A/D conversion end interrupt function Enabled. 62 * |[3:2] |ADMD |A/D Converter Operation Mode Control 63 * | | |00 = Single conversion. 64 * | | |01 = Burst conversion. 65 * | | |10 = Single-cycle Scan. 66 * | | |11 = Continuous Scan. 67 * | | |Note 1: When changing the operation mode, software should clear ADST bit first. 68 * | | |Note 2: In Burst mode, the A/D conversion result data is always at ADC Data Register 0. 69 * |[7:6] |TRGCOND |External Trigger Condition 70 * | | |These two bits decide external pin LPADC0_ST trigger event is level or edge 71 * | | |The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger. 72 * | | |00 = Low level. 73 * | | |01 = High level. 74 * | | |10 = Falling edge. 75 * | | |11 = Rising edge. 76 * |[8] |TRGEN |External Trigger Enable Bit 77 * | | |Enable or disable triggering of A/D conversion by external LPADC0_ST pin, EPWM trigger, PWM trigger, ACMP interrupt event and Timer trigger 78 * | | |If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source. 79 * | | |0 = External trigger Disabled. 80 * | | |1 = External trigger Enabled. 81 * | | |Note: The ADC external trigger function is only supported in Single-cycle Scan mode. 82 * |[9] |PTEN |LPPDMA Transfer Enable Bit 83 * | | |When A/D conversion is completed, the converted data is loaded into ADDR0~26 and ADDR28~ADDR31 84 * | | |Software can enable this bit to generate a LPPDMA data transfer request. 85 * | | |0 = LPPDMA data transfer Disabled. 86 * | | |1 = LPPDMA data transfer in ADDR0~26 and ADDR28~ADDR31 Enabled. 87 * | | |Note: When PTEN=1, software must set ADIE=0 to disable interrupt. 88 * |[10] |DIFFEN |Differential Input Mode Control 89 * | | |Differential input voltage (Vdiff) = Vplus - Vminus. 90 * | | |The relation between Vplus and Vminus is Vplus + Vminus = Vref. 91 * | | |The Vplus of differential input paired channel x is from LPADC0_CHy pin; Vminus is from LPADC0_CHz pin, x=0,1..11, y=2*x, z=y+1. 92 * | | |0 = Single-end analog input mode. 93 * | | |1 = Differential analog input mode. 94 * | | |Note: In Differential Input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER register 95 * | | |The conversion result will be placed to the corresponding data register of the enabled channel. 96 * |[11] |ADST |A/D Conversion Start or Calibration Start 97 * | | |ADST bit can be set to 1 from four sources: software, external pin LPADC0_ST, PWM trigger and Timer trigger 98 * | | |ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode, Single-cycle Scan mode and Calibration mode 99 * | | |In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset. 100 * | | |0 = Conversion stops and A/D converter enters idle state. 101 * | | |1 = Conversion starts or Calibration Start. 102 * | | |Note 1: When ADST becomes from 1 to 0, ADC macro will reset to initial state 103 * | | |After macro reset to initial state, user should wait at most 2 ADC clock and set this bit to start next conversion. 104 * | | |Note 2: Calibration Start only if CALEN (LPADC_ADCAL[0]) = 1. 105 * |[12] |RESET |ADC RESET (Write Protect) 106 * | | |If user writes this bit, the ADC analog macro will reset 107 * | | |Calibration data in macro will be deleted, but registers LPADC will keep. 108 * | | |Note: This bit is cleared by hardware. 109 * |[19:16] |TRGS |Hardware Trigger Source 110 * | | |0000 = A/D conversion is started by external LPADC0_ST pin. 111 * | | |0001 = Timer0 ~ Timer3 overflow pulse trigger. 112 * | | |0011 = A/D conversion is started by PWM trigger. 113 * | | |0100 = A/D conversion is started by EPWM trigger. 114 * | | |1000 = ACMP0_O edge event. 115 * | | |1001 = ACMP1_O edge event. 116 * | | |1010 = ACMP2_O edge event. 117 * | | |Others = Reserved. 118 * | | |Note 1: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits. 119 * | | |Note 2: These trigger sources are only abaliable when chip is in run and idle mode. 120 * |[21:20] |ACMPTES |ACMP Trigger Event Selection 121 * | | |00 = ACMP0/1/2 both edge event as trigger source. 122 * | | |01 = ACMP0/1/2 rising edge event as trigger source. 123 * | | |10 = ACMP0/1/2 falling edge event as trigger source. 124 * | | |11 = Reserved. 125 * |[29:28] |RESSEL |Resolution Select Bits 126 * | | |00 = ADC resolution 12 bits. 127 * | | |01 = ADC resolution 10 bits. 128 * | | |10 = ADC resolution 8 bits. 129 * | | |11 = Reserved. 130 * |[31] |DMOF |Differential Input Mode Output Format 131 * | | |If user enables differential input mode, the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format). 132 * | | |0 = A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format (straight binary format). 133 * | | |1 = A/D Conversion result will be filled in RSLT at ADDRx registers with 2's complement format. 134 * @var LPADC_T::ADCHER 135 * Offset: 0x84 ADC Channel Enable Register 136 * --------------------------------------------------------------------------------------------------- 137 * |Bits |Field |Descriptions 138 * | :----: | :----: | :---- | 139 * |[31:0] |CHEN |Analog Input Channel Enable Control 140 * | | |Set ADCHER[23:0] bits to enable the corresponding analog external input channel 23 ~ 0 141 * | | |If DIFFEN bit is set to 1, only the even number channel needs to be enabled. 142 * | | |Besides, setting the ADCHER[26:24] bits will enable internal OPA0/1/2 output voltage, setting the ADCHER[28] bit will enable internal channel for AVDD divided by four, setting the ADCHER[29] bit will enable internal channel for band-gap voltage, setting the ADCHER[30] bit will enable internal channel for temperature sensor output voltage, setting the ADCHER[31] bit will enable internal channel for VBAT divided by four 143 * | | |Other bits are reserved. 144 * | | |0 = Channel Disabled. 145 * | | |1 = Channel Enabled. 146 * | | |Note: If the internal channel for AVDD divide by four (CHEN[28]), band-gap voltage (CHEN[29]), temperature sensor output voltage (CHEN[30]) or VBAT divided by four (CHEN[31]) is active, the maximum sampling rate will be 300k SPS. 147 * @var LPADC_T::ADCMPR[2] 148 * Offset: 0x88/0x8C ADC Compare Register 0~1 149 * --------------------------------------------------------------------------------------------------- 150 * |Bits |Field |Descriptions 151 * | :----: | :----: | :---- | 152 * |[0] |CMPEN |Compare Enable Bit 153 * | | |Set this bit to 1 to enable LPADC to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register. 154 * | | |0 = Compare function Disabled. 155 * | | |1 = Compare function Enabled. 156 * |[1] |CMPIE |Compare Interrupt Enable Bit 157 * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE bit is set to 1, a compare interrupt request is generated. 158 * | | |0 = Compare function interrupt Disabled. 159 * | | |1 = Compare function interrupt Enabled. 160 * |[2] |CMPCOND |Compare Condition 161 * | | |0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD bits, the internal match counter will increase one. 162 * | | |1 = Set the compare condition as that when a 12-bit A/D conversion result is greater than or equal to the 12-bit CMPD bits, the internal match counter will increase one. 163 * | | |Note: When the internal counter reaches to (CMPMCNT +1), the CMPFx bit will be set. 164 * |[7:3] |CMPCH |Compare Channel Selection 165 * | | |00000 = Channel 0 conversion result is selected to be compared. 166 * | | |00001 = Channel 1 conversion result is selected to be compared. 167 * | | |00010 = Channel 2 conversion result is selected to be compared. 168 * | | |00011 = Channel 3 conversion result is selected to be compared. 169 * | | |00100 = Channel 4 conversion result is selected to be compared. 170 * | | |00101 = Channel 5 conversion result is selected to be compared. 171 * | | |00110 = Channel 6 conversion result is selected to be compared. 172 * | | |00111 = Channel 7 conversion result is selected to be compared. 173 * | | |01000 = Channel 8 conversion result is selected to be compared. 174 * | | |01001 = Channel 9 conversion result is selected to be compared. 175 * | | |01010 = Channel 10 conversion result is selected to be compared. 176 * | | |01011 = Channel 11 conversion result is selected to be compared. 177 * | | |01100 = Channel 12 conversion result is selected to be compared. 178 * | | |01101 = Channel 13 conversion result is selected to be compared. 179 * | | |01110 = Channel 14 conversion result is selected to be compared. 180 * | | |01111 = Channel 15 conversion result is selected to be compared. 181 * | | |10000 = Channel 16 conversion result is selected to be compared. 182 * | | |10001 = Channel 17 conversion result is selected to be compared. 183 * | | |10010 = Channel 18 conversion result is selected to be compared. 184 * | | |10011 = Channel 19 conversion result is selected to be compared. 185 * | | |10100 = Channel 20 conversion result is selected to be compared. 186 * | | |10101 = Channel 21 conversion result is selected to be compared. 187 * | | |10110 = Channel 22 conversion result is selected to be compared. 188 * | | |10111 = Channel 23 conversion result is selected to be compared. 189 * | | |11000 = OPA0 internal output voltage conversion result is selected to be compared. 190 * | | |11001 = OPA1 internal output voltage conversion result is selected to be compared. 191 * | | |11010 = OPA2 internal output voltage conversion result is selected to be compared. 192 * | | |11100 = AVDD/4 channel conversion result is selected to be compared. 193 * | | |11101 = Band-gap voltage conversion result is selected to be compared. 194 * | | |11110 = Temperature sensor voltage conversion result is selected to be compared. 195 * | | |11111 = VBAT/4 channel conversion result is selected to be compared. 196 * | | |Others = Reserved. 197 * |[11:8] |CMPMCNT |Compare Match Count 198 * | | |When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit, the internal match counter will increase 1 199 * | | |When the internal counter reaches the value to (CMPMCNT +1), the CMPFx bit will be set. 200 * |[15] |CMPWEN |Compare Window Mode Enable Bit 201 * | | |0 = Compare Window Mode Disabled. 202 * | | |1 = Compare Window Mode Enabled. 203 * | | |Note: This bit is only presented in ADCMPR0 register. 204 * |[27:16] |CMPD |Comparison Data 205 * | | |The 12-bit data is used to compare with conversion result of specified channel. 206 * | | |Note: CMPD bits should be filled in unsigned format (straight binary format). 207 * @var LPADC_T::ADSR0 208 * Offset: 0x90 ADC Status Register0 209 * --------------------------------------------------------------------------------------------------- 210 * |Bits |Field |Descriptions 211 * | :----: | :----: | :---- | 212 * |[0] |ADF |A/D Conversion End Flag 213 * | | |A status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit. 214 * | | |The ADF bit is set to 1 at the following three conditions: 215 * | | |1. When A/D conversion ends in Single mode. 216 * | | |2 217 * | | |When A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode. 218 * | | |3. When more than or equal to 8 samples in FIFO in Burst mode. 219 * |[1] |CMPF0 |Compare Flag 0 220 * | | |When the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1 221 * | | |This bit is cleared by writing 1 to it. 222 * | | |0 = Conversion result in ADDR does not meet ADCMPR0 setting. 223 * | | |1 = Conversion result in ADDR meets ADCMPR0 setting. 224 * |[2] |CMPF1 |Compare Flag 1 225 * | | |When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register, this bit is set to 1; it is cleared by writing 1 to it 226 * | | |0 = Conversion result in ADDR does not meet ADCMPR1 setting. 227 * | | |1 = Conversion result in ADDR meets ADCMPR1 setting. 228 * |[7] |BUSY |BUSY/IDLE (Read Only) 229 * | | |This bit is a mirror of ADST bit in ADCR register. 230 * | | |0 = A/D converter is in idle state. 231 * | | |1 = A/D converter is busy at conversion. 232 * |[8] |VALIDF |Data Valid Flag (Read Only) 233 * | | |If any one of VALID (ADDRx[17]) is set, this flag will be set to 1. 234 * | | |Note: When ADC is in burst mode and any conversion result is valid, this flag will be set to 1. 235 * |[16] |OVERRUNF |Overrun Flag (Read Only) 236 * | | |If any one of OVERRUN (ADDRx[16]) is set, this flag will be set to 1. 237 * | | |Note: When ADC is in burst mode and the FIFO is overrun, this flag will be set to 1. 238 * |[24] |ADPRDY |ADC Power On Ready (Read Only) 239 * | | |After set ADEN (LPADC_ADCR[0]) to 1, the ADPRDY will set to 1 within one PCLK2 clock period. 240 * | | |Then ADC macro can start convet. 241 * | | |The chip also support ALDO when chip want to do A/D conversion under chip power level is PL2 and PL3. 242 * | | |When ALDOEN (LPADC_ALDOCTL[8]) set to 1 to enable ALDO, the ALDO need a power stable time. 243 * | | |The ADPRDY will keep low until ALDO power stable. 244 * | | |The ALDO power ready time depends on STBSEL (LPADC_ALDOCTL[18:16]). 245 * | | |Note: LPADC can start converting after ADPRDY is 1. 246 * |[31:27] |CHANNEL |Current Conversion Channel (Read Only) 247 * | | |When BUSY=1, this filed reflects current conversion channel 248 * | | |When BUSY=0, it shows the number of the next converted channel. 249 * @var LPADC_T::ADSR1 250 * Offset: 0x94 ADC Status Register1 251 * --------------------------------------------------------------------------------------------------- 252 * |Bits |Field |Descriptions 253 * | :----: | :----: | :---- | 254 * |[31:0] |VALID |Data Valid Flag (Read Only) 255 * | | |VALID[31, 30, 29, 28, 26, 25, 24, 23:0] are the mirror of the VALID bits in ADDR31[17], ADDR30[17], ADDR29[17], ADDR28[17], ADDR26[17], ADDR25[17], ADDR24[17], ADDR23[17]~ ADDR0[17] 256 * | | |The other bits are reserved. 257 * | | |Note: When ADC is in burst mode and any conversion result is valid, VALID[31, 30, 29, 28, 26, 25, 24, 23:0] will be set to 1. 258 * @var LPADC_T::ADSR2 259 * Offset: 0x98 ADC Status Register2 260 * --------------------------------------------------------------------------------------------------- 261 * |Bits |Field |Descriptions 262 * | :----: | :----: | :---- | 263 * |[31:0] |OVERRUN |Overrun Flag (Read Only) 264 * | | |OVERRUN[31, 30, 29, 28, 26, 25, 24, 23:0] are the mirror of the OVERRUN bit in ADDR31[16], ADDR30[16], ADDR29[16], ADDR28[16], ADDR26[16], ADDR25[16], ADDR24[16], ADDR23[16] ~ ADDR0[16] 265 * | | |The other bits are reserved. 266 * | | |Note: When ADC is in burst mode and the FIFO is overrun, OVERRUN[31, 30, 29, 28, 26, 25, 24, 23:0] will be set to 1. 267 * @var LPADC_T::ESMPCTL 268 * Offset: 0xA0 ADC Extend Sample Time Control Register 269 * --------------------------------------------------------------------------------------------------- 270 * |Bits |Field |Descriptions 271 * | :----: | :----: | :---- | 272 * |[13:0] |EXTSMPT |ADC Sampling Time Extend 273 * | | |When A/D conversion at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time. 274 * | | |The range of start delay time is from 0~16383 ADC clock. 275 * @var LPADC_T::CFDCTL 276 * Offset: 0xA4 ADC Channel Floating Detect Control Register 277 * --------------------------------------------------------------------------------------------------- 278 * |Bits |Field |Descriptions 279 * | :----: | :----: | :---- | 280 * |[0] |PRECHEN |Precharge Enable Bit 281 * | | |0 = Channel precharge Disabled. 282 * | | |1 = Channel precharge Enabled. 283 * | | |Note: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enabled. 284 * |[1] |DISCHEN |Discharge Enable Bit 285 * | | |0 = Channel discharge Disabled. 286 * | | |1 = Channel discharge Enabled. 287 * | | |Note: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enabled. 288 * |[8] |FDETCHEN |Floating Detect Channel Enable Bit 289 * | | |0 = Floating Detect Channel Disabled. 290 * | | |1 = Floating Detect Channel Enabled. 291 * @var LPADC_T::ADPDMA 292 * Offset: 0x100 ADC LPPDMA Current Transfer Data Register 293 * --------------------------------------------------------------------------------------------------- 294 * |Bits |Field |Descriptions 295 * | :----: | :----: | :---- | 296 * |[17:0] |CURDAT |ADC LPPDMA Current Transfer Data Register (Read Only) 297 * | | |When LPPDMA transfers data, reading the register can monitor the current LPPDMA transfer data. 298 * | | |Current LPPDMA transfer data could be the content of ADDR0 ~ ADDR23, ADDR24, ADDR25, ADDR26, ADDR28, ADDR29, ADDC30 and ADDR31 registers. 299 * @var LPADC_T::ADCAL 300 * Offset: 0x180 ADC Calibration Mode Register 301 * --------------------------------------------------------------------------------------------------- 302 * |Bits |Field |Descriptions 303 * | :----: | :----: | :---- | 304 * |[0] |CALEN |Calibration Function Enable Bit 305 * | | |0 = Calibration function Disabled. 306 * | | |1.= Calibration function Enabled. 307 * | | |Note: If chip is powered off, calibration function should be executed again. 308 * |[1] |CALIE |Calibration Interrupt Enable Bit 309 * | | |If calibration function is enabled and the calibration is finished, CALIF bit will be asserted, in the meanwhile, if CALIE bit is set to 1, a calibration interrupt request is generated. 310 * | | |0 = Calibration function Interrupt Disabled. 311 * | | |1 = Calibration function Interrupt Enabled. 312 * @var LPADC_T::ADCALSTS 313 * Offset: 0x184 ADC Calibration Status Register 314 * --------------------------------------------------------------------------------------------------- 315 * |Bits |Field |Descriptions 316 * | :----: | :----: | :---- | 317 * |[0] |CALIF |Calibration Finish Interrupt Flag 318 * | | |If calibration is finished, this flag will be set to 1. It is cleared by writing 1 to it. 319 * @var LPADC_T::AUTOCTL 320 * Offset: 0x800 ADC Auto Operation Control Register 321 * --------------------------------------------------------------------------------------------------- 322 * |Bits |Field |Descriptions 323 * | :----: | :----: | :---- | 324 * |[3:0] |TRIGSEL |Automatic Operation Trigger Source Select 325 * | | |0000 = Auto-operation Trigger Source from LPTMR0. 326 * | | |0001 = Auto-operation Trigger Source from LPTMR1. 327 * | | |0010 = Auto-operation Trigger Source from TTMR0. 328 * | | |0011 = Auto-operation Trigger Source from TTMR1. 329 * | | |0100 = Auto-operation Trigger Source from WKIOA0. 330 * | | |0101 = Auto-operation Trigger Source from WKIOB0. 331 * | | |0110 = Auto-operation Trigger Source from WKIOC0. 332 * | | |0111 = Auto-operation Trigger Source from WKIOD0. 333 * | | |1000 = Auto-operation Trigger Source from ACMP0 analog output event. 334 * | | |1001 = Auto-operation Trigger Source from ACMP1 analog output event. 335 * | | |1010 = Auto-operation Trigger Source from ACMP2 analog output event. 336 * | | |Others = Reserved. 337 * | | |Note: TRIGSEL cannot be changed when TRIGEN is 1. 338 * |[4] |TRIGEN |Automatic Operation Trigger Enable Bit 339 * | | |When automatic operation mode is enabled, the LPADC will start working if LPADC is triggered by a event sent from the trigger source selected by TRIGSEL[3:0] after this bit is set to 1. 340 * | | |0 = LPADC Automatic Operation Trigger Disabled. 341 * | | |1 = LPADC Automatic Operation Trigger Enabled. 342 * |[8] |ADWKEN |Automatic Operation Mode Conversion End Wake-up Enable Bit 343 * | | |0 = LPADC automatic operation conversion end wake-up Disabled. 344 * | | |1 = LPADC automatic operation conversion end wake-up Enabled. 345 * |[9] |CMP0WKEN |Automatic Operation Mode Comparator 0 Wake-up Enable Bit 346 * | | |0 = LPADC automatic operation comparator 0 wake-up Disabled. 347 * | | |1 = LPADC automatic operation comparator 0 wake-up Enabled. 348 * |[10] |CMP1WKEN |Automatic Operation Mode Comparator 1 Wake-up Enable Bit 349 * | | |0 = LPADC automatic operation comparator 1 wake-up Disabled. 350 * | | |1 = LPADC automatic operation comparator 1 wake-up Enabled. 351 * |[31] |AUTOEN |Automatic Operation Mode Enable Bit 352 * | | |0 = LPADC automatic operation Disabled. 353 * | | |1 = LPADC automatic operation Enabled. 354 * @var LPADC_T::AUTOSTRG 355 * Offset: 0x804 ADC Auto Operation Software Trigger Register 356 * --------------------------------------------------------------------------------------------------- 357 * |Bits |Field |Descriptions 358 * | :----: | :----: | :---- | 359 * |[0] |SWTRIG |Automatic Operation Software Trigger Bit 360 * | | |Write 1 to this bit will trigger LPADC start automatic operation. 361 * | | |Note: This bit will be auto cleared by hardware. 362 * @var LPADC_T::AUTOSTS 363 * Offset: 0x810 ADC Auto Operation Status Register 364 * --------------------------------------------------------------------------------------------------- 365 * |Bits |Field |Descriptions 366 * | :----: | :----: | :---- | 367 * |[0] |ADWKF |Automatic Operation Conversion End Wake-up Flag Bit 368 * | | |When automatic operation mode is enabled, and the conversion is finished, this flag will be set 369 * | | |If WKEN is also set to 1, the chip will be woken up. 370 * | | |Note: Software can write 1 to clear this bit. 371 * |[1] |CMP0WKF |Automatic Operation Compare 0 Wake-up Flag Bit 372 * | | |When automatic operation mode is enabled, and the conversion result monitor comparator 1 matches setting criteria, this flag will be set 373 * | | |If CMP1WKEN is also set to 1, the chip will be woken up. 374 * | | |Note: Software can write1 to clear this bit. 375 * |[2] |CMP1WKF |Automatic Operation Compare 1 Wake-up Flag Bit 376 * | | |When automatic operation mode is enabled, and the conversion result monitor comparator 0 is match setting criteria, this flag will be set 377 * | | |If CMP0WKEN is also set to 1, the chip will be woken up. 378 * | | |Note: Software can write 1 to clear this bit. 379 * @var LPADC_T::ALDOCTL 380 * Offset: 0xFEC ADC ALDO Control Register 381 * --------------------------------------------------------------------------------------------------- 382 * |Bits |Field |Descriptions 383 * | :----: | :----: | :---- | 384 * |[8] |ALDOEN |ALDO Enable Bit 385 * | | |0 = ALDO Disabled. 386 * | | |1 = ALDO Enabled. 387 * | | |Note 1: After ADEN (LPADC_ADCR[0]) is enabled, the ALDOEN cannot be changed. 388 * | | |Note 2: ALDO can be enabled only when the chip runs at power level 3 (PL3) or NPD2/4 or NPD0/1/3 with power level 3 389 * | | |When the chip runs at power level 1 (PL1) or power level 2 (PL2), ALDO should be disabled. 390 * |[18:16] |STBSEL |ALDO Stable Count Select Bits 391 * | | |If IGENEN (ALDOCTL[23]) is 0, the ALDO stable count is as follows. 392 * | | |010 = ALDO stable count is 408 PCLK2 (When PCLK is 12 MHz). 393 * | | |011 = ALDO stable count is 272 PCLK2 (When PCLK is 8 MHz). 394 * | | |100 = ALDO stable count is 136 PCLK2 (When PCLK is 4 MHz). 395 * | | |Others = Reserved. 396 * | | |If IGENEN (ALDOCTL[23]) is 1, the ALDO stable count is as follows. 397 * | | |010 = ALDO stable count is 48 PCLK2 (When PCLK is 12 MHz). 398 * | | |011 = ALDO stable count is 32 PCLK2 (When PCLK is 8 MHz). 399 * | | |100 = ALDO stable count is 16 PCLK2 (When PCLK is 4 MHz). 400 * | | |Others = Reserved. 401 * |[23] |IGENEN |ALDO Enable under IGEN Enable Bit 402 * | | |0 = ALDO enable under IGEN Disabled. 403 * | | |1 = ALDO enable under IGEN Enabled. 404 * | | |Note: When ALDO enable under IGEN enable, the ALDO stable time is shorter. 405 */ 406 __I uint32_t ADDR[32]; /*!< [0x0000-0x007c] ADC Data Register 0~31 */ 407 __IO uint32_t ADCR; /*!< [0x0080] ADC Control Register */ 408 __IO uint32_t ADCHER; /*!< [0x0084] ADC Channel Enable Register */ 409 __IO uint32_t ADCMPR[2]; /*!< [0x0088-0x008c] ADC Compare Register 0~1 */ 410 __IO uint32_t ADSR0; /*!< [0x0090] ADC Status Register0 */ 411 __I uint32_t ADSR1; /*!< [0x0094] ADC Status Register1 */ 412 __I uint32_t ADSR2; /*!< [0x0098] ADC Status Register2 */ 413 __I uint32_t RESERVE1[1]; 414 __IO uint32_t ESMPCTL; /*!< [0x00a0] ADC Extend Sample Time Control Register */ 415 __IO uint32_t CFDCTL; /*!< [0x00a4] ADC Channel Floating Detect Control Register */ 416 __I uint32_t RESERVE2[22]; 417 __I uint32_t ADPDMA; /*!< [0x0100] ADC LPPDMA Current Transfer Data Register */ 418 __I uint32_t RESERVE3[31]; 419 __IO uint32_t ADCAL; /*!< [0x0180] ADC Calibration Mode Register */ 420 __IO uint32_t ADCALSTS; /*!< [0x0184] ADC Calibration Status Register */ 421 __I uint32_t RESERVE4[414]; 422 __IO uint32_t AUTOCTL; /*!< [0x0800] ADC Auto Operation Control Register */ 423 __O uint32_t AUTOSTRG; /*!< [0x0804] ADC Auto Operation Software Trigger Register */ 424 __I uint32_t RESERVE5[2]; 425 __IO uint32_t AUTOSTS; /*!< [0x0810] ADC Auto Operation Status Register */ 426 __I uint32_t RESERVE6[502]; 427 __IO uint32_t ALDOCTL; /*!< [0x0fec] ADC ALDO Control Register */ 428 429 } LPADC_T; 430 431 /** 432 @addtogroup LPADC_CONST LPADC Bit Field Definition 433 Constant Definitions for LPADC Controller 434 @{ */ 435 436 #define LPADC_ADDR0_RSLT_Pos (0) /*!< LPADC_T::ADDR0: RSLT Position */ 437 #define LPADC_ADDR0_RSLT_Msk (0xfffful << LPADC_ADDR0_RSLT_Pos) /*!< LPADC_T::ADDR0: RSLT Mask */ 438 439 #define LPADC_ADDR0_OVERRUN_Pos (16) /*!< LPADC_T::ADDR0: OVERRUN Position */ 440 #define LPADC_ADDR0_OVERRUN_Msk (0x1ul << LPADC_ADDR0_OVERRUN_Pos) /*!< LPADC_T::ADDR0: OVERRUN Mask */ 441 442 #define LPADC_ADDR0_VALID_Pos (17) /*!< LPADC_T::ADDR0: VALID Position */ 443 #define LPADC_ADDR0_VALID_Msk (0x1ul << LPADC_ADDR0_VALID_Pos) /*!< LPADC_T::ADDR0: VALID Mask */ 444 445 #define LPADC_ADDR1_RSLT_Pos (0) /*!< LPADC_T::ADDR1: RSLT Position */ 446 #define LPADC_ADDR1_RSLT_Msk (0xfffful << LPADC_ADDR1_RSLT_Pos) /*!< LPADC_T::ADDR1: RSLT Mask */ 447 448 #define LPADC_ADDR1_OVERRUN_Pos (16) /*!< LPADC_T::ADDR1: OVERRUN Position */ 449 #define LPADC_ADDR1_OVERRUN_Msk (0x1ul << LPADC_ADDR1_OVERRUN_Pos) /*!< LPADC_T::ADDR1: OVERRUN Mask */ 450 451 #define LPADC_ADDR1_VALID_Pos (17) /*!< LPADC_T::ADDR1: VALID Position */ 452 #define LPADC_ADDR1_VALID_Msk (0x1ul << LPADC_ADDR1_VALID_Pos) /*!< LPADC_T::ADDR1: VALID Mask */ 453 454 #define LPADC_ADDR2_RSLT_Pos (0) /*!< LPADC_T::ADDR2: RSLT Position */ 455 #define LPADC_ADDR2_RSLT_Msk (0xfffful << LPADC_ADDR2_RSLT_Pos) /*!< LPADC_T::ADDR2: RSLT Mask */ 456 457 #define LPADC_ADDR2_OVERRUN_Pos (16) /*!< LPADC_T::ADDR2: OVERRUN Position */ 458 #define LPADC_ADDR2_OVERRUN_Msk (0x1ul << LPADC_ADDR2_OVERRUN_Pos) /*!< LPADC_T::ADDR2: OVERRUN Mask */ 459 460 #define LPADC_ADDR2_VALID_Pos (17) /*!< LPADC_T::ADDR2: VALID Position */ 461 #define LPADC_ADDR2_VALID_Msk (0x1ul << LPADC_ADDR2_VALID_Pos) /*!< LPADC_T::ADDR2: VALID Mask */ 462 463 #define LPADC_ADDR3_RSLT_Pos (0) /*!< LPADC_T::ADDR3: RSLT Position */ 464 #define LPADC_ADDR3_RSLT_Msk (0xfffful << LPADC_ADDR3_RSLT_Pos) /*!< LPADC_T::ADDR3: RSLT Mask */ 465 466 #define LPADC_ADDR3_OVERRUN_Pos (16) /*!< LPADC_T::ADDR3: OVERRUN Position */ 467 #define LPADC_ADDR3_OVERRUN_Msk (0x1ul << LPADC_ADDR3_OVERRUN_Pos) /*!< LPADC_T::ADDR3: OVERRUN Mask */ 468 469 #define LPADC_ADDR3_VALID_Pos (17) /*!< LPADC_T::ADDR3: VALID Position */ 470 #define LPADC_ADDR3_VALID_Msk (0x1ul << LPADC_ADDR3_VALID_Pos) /*!< LPADC_T::ADDR3: VALID Mask */ 471 472 #define LPADC_ADDR4_RSLT_Pos (0) /*!< LPADC_T::ADDR4: RSLT Position */ 473 #define LPADC_ADDR4_RSLT_Msk (0xfffful << LPADC_ADDR4_RSLT_Pos) /*!< LPADC_T::ADDR4: RSLT Mask */ 474 475 #define LPADC_ADDR4_OVERRUN_Pos (16) /*!< LPADC_T::ADDR4: OVERRUN Position */ 476 #define LPADC_ADDR4_OVERRUN_Msk (0x1ul << LPADC_ADDR4_OVERRUN_Pos) /*!< LPADC_T::ADDR4: OVERRUN Mask */ 477 478 #define LPADC_ADDR4_VALID_Pos (17) /*!< LPADC_T::ADDR4: VALID Position */ 479 #define LPADC_ADDR4_VALID_Msk (0x1ul << LPADC_ADDR4_VALID_Pos) /*!< LPADC_T::ADDR4: VALID Mask */ 480 481 #define LPADC_ADDR5_RSLT_Pos (0) /*!< LPADC_T::ADDR5: RSLT Position */ 482 #define LPADC_ADDR5_RSLT_Msk (0xfffful << LPADC_ADDR5_RSLT_Pos) /*!< LPADC_T::ADDR5: RSLT Mask */ 483 484 #define LPADC_ADDR5_OVERRUN_Pos (16) /*!< LPADC_T::ADDR5: OVERRUN Position */ 485 #define LPADC_ADDR5_OVERRUN_Msk (0x1ul << LPADC_ADDR5_OVERRUN_Pos) /*!< LPADC_T::ADDR5: OVERRUN Mask */ 486 487 #define LPADC_ADDR5_VALID_Pos (17) /*!< LPADC_T::ADDR5: VALID Position */ 488 #define LPADC_ADDR5_VALID_Msk (0x1ul << LPADC_ADDR5_VALID_Pos) /*!< LPADC_T::ADDR5: VALID Mask */ 489 490 #define LPADC_ADDR6_RSLT_Pos (0) /*!< LPADC_T::ADDR6: RSLT Position */ 491 #define LPADC_ADDR6_RSLT_Msk (0xfffful << LPADC_ADDR6_RSLT_Pos) /*!< LPADC_T::ADDR6: RSLT Mask */ 492 493 #define LPADC_ADDR6_OVERRUN_Pos (16) /*!< LPADC_T::ADDR6: OVERRUN Position */ 494 #define LPADC_ADDR6_OVERRUN_Msk (0x1ul << LPADC_ADDR6_OVERRUN_Pos) /*!< LPADC_T::ADDR6: OVERRUN Mask */ 495 496 #define LPADC_ADDR6_VALID_Pos (17) /*!< LPADC_T::ADDR6: VALID Position */ 497 #define LPADC_ADDR6_VALID_Msk (0x1ul << LPADC_ADDR6_VALID_Pos) /*!< LPADC_T::ADDR6: VALID Mask */ 498 499 #define LPADC_ADDR7_RSLT_Pos (0) /*!< LPADC_T::ADDR7: RSLT Position */ 500 #define LPADC_ADDR7_RSLT_Msk (0xfffful << LPADC_ADDR7_RSLT_Pos) /*!< LPADC_T::ADDR7: RSLT Mask */ 501 502 #define LPADC_ADDR7_OVERRUN_Pos (16) /*!< LPADC_T::ADDR7: OVERRUN Position */ 503 #define LPADC_ADDR7_OVERRUN_Msk (0x1ul << LPADC_ADDR7_OVERRUN_Pos) /*!< LPADC_T::ADDR7: OVERRUN Mask */ 504 505 #define LPADC_ADDR7_VALID_Pos (17) /*!< LPADC_T::ADDR7: VALID Position */ 506 #define LPADC_ADDR7_VALID_Msk (0x1ul << LPADC_ADDR7_VALID_Pos) /*!< LPADC_T::ADDR7: VALID Mask */ 507 508 #define LPADC_ADDR8_RSLT_Pos (0) /*!< LPADC_T::ADDR8: RSLT Position */ 509 #define LPADC_ADDR8_RSLT_Msk (0xfffful << LPADC_ADDR8_RSLT_Pos) /*!< LPADC_T::ADDR8: RSLT Mask */ 510 511 #define LPADC_ADDR8_OVERRUN_Pos (16) /*!< LPADC_T::ADDR8: OVERRUN Position */ 512 #define LPADC_ADDR8_OVERRUN_Msk (0x1ul << LPADC_ADDR8_OVERRUN_Pos) /*!< LPADC_T::ADDR8: OVERRUN Mask */ 513 514 #define LPADC_ADDR8_VALID_Pos (17) /*!< LPADC_T::ADDR8: VALID Position */ 515 #define LPADC_ADDR8_VALID_Msk (0x1ul << LPADC_ADDR8_VALID_Pos) /*!< LPADC_T::ADDR8: VALID Mask */ 516 517 #define LPADC_ADDR9_RSLT_Pos (0) /*!< LPADC_T::ADDR9: RSLT Position */ 518 #define LPADC_ADDR9_RSLT_Msk (0xfffful << LPADC_ADDR9_RSLT_Pos) /*!< LPADC_T::ADDR9: RSLT Mask */ 519 520 #define LPADC_ADDR9_OVERRUN_Pos (16) /*!< LPADC_T::ADDR9: OVERRUN Position */ 521 #define LPADC_ADDR9_OVERRUN_Msk (0x1ul << LPADC_ADDR9_OVERRUN_Pos) /*!< LPADC_T::ADDR9: OVERRUN Mask */ 522 523 #define LPADC_ADDR9_VALID_Pos (17) /*!< LPADC_T::ADDR9: VALID Position */ 524 #define LPADC_ADDR9_VALID_Msk (0x1ul << LPADC_ADDR9_VALID_Pos) /*!< LPADC_T::ADDR9: VALID Mask */ 525 526 #define LPADC_ADDR10_RSLT_Pos (0) /*!< LPADC_T::ADDR10: RSLT Position */ 527 #define LPADC_ADDR10_RSLT_Msk (0xfffful << LPADC_ADDR10_RSLT_Pos) /*!< LPADC_T::ADDR10: RSLT Mask */ 528 529 #define LPADC_ADDR10_OVERRUN_Pos (16) /*!< LPADC_T::ADDR10: OVERRUN Position */ 530 #define LPADC_ADDR10_OVERRUN_Msk (0x1ul << LPADC_ADDR10_OVERRUN_Pos) /*!< LPADC_T::ADDR10: OVERRUN Mask */ 531 532 #define LPADC_ADDR10_VALID_Pos (17) /*!< LPADC_T::ADDR10: VALID Position */ 533 #define LPADC_ADDR10_VALID_Msk (0x1ul << LPADC_ADDR10_VALID_Pos) /*!< LPADC_T::ADDR10: VALID Mask */ 534 535 #define LPADC_ADDR11_RSLT_Pos (0) /*!< LPADC_T::ADDR11: RSLT Position */ 536 #define LPADC_ADDR11_RSLT_Msk (0xfffful << LPADC_ADDR11_RSLT_Pos) /*!< LPADC_T::ADDR11: RSLT Mask */ 537 538 #define LPADC_ADDR11_OVERRUN_Pos (16) /*!< LPADC_T::ADDR11: OVERRUN Position */ 539 #define LPADC_ADDR11_OVERRUN_Msk (0x1ul << LPADC_ADDR11_OVERRUN_Pos) /*!< LPADC_T::ADDR11: OVERRUN Mask */ 540 541 #define LPADC_ADDR11_VALID_Pos (17) /*!< LPADC_T::ADDR11: VALID Position */ 542 #define LPADC_ADDR11_VALID_Msk (0x1ul << LPADC_ADDR11_VALID_Pos) /*!< LPADC_T::ADDR11: VALID Mask */ 543 544 #define LPADC_ADDR12_RSLT_Pos (0) /*!< LPADC_T::ADDR12: RSLT Position */ 545 #define LPADC_ADDR12_RSLT_Msk (0xfffful << LPADC_ADDR12_RSLT_Pos) /*!< LPADC_T::ADDR12: RSLT Mask */ 546 547 #define LPADC_ADDR12_OVERRUN_Pos (16) /*!< LPADC_T::ADDR12: OVERRUN Position */ 548 #define LPADC_ADDR12_OVERRUN_Msk (0x1ul << LPADC_ADDR12_OVERRUN_Pos) /*!< LPADC_T::ADDR12: OVERRUN Mask */ 549 550 #define LPADC_ADDR12_VALID_Pos (17) /*!< LPADC_T::ADDR12: VALID Position */ 551 #define LPADC_ADDR12_VALID_Msk (0x1ul << LPADC_ADDR12_VALID_Pos) /*!< LPADC_T::ADDR12: VALID Mask */ 552 553 #define LPADC_ADDR13_RSLT_Pos (0) /*!< LPADC_T::ADDR13: RSLT Position */ 554 #define LPADC_ADDR13_RSLT_Msk (0xfffful << LPADC_ADDR13_RSLT_Pos) /*!< LPADC_T::ADDR13: RSLT Mask */ 555 556 #define LPADC_ADDR13_OVERRUN_Pos (16) /*!< LPADC_T::ADDR13: OVERRUN Position */ 557 #define LPADC_ADDR13_OVERRUN_Msk (0x1ul << LPADC_ADDR13_OVERRUN_Pos) /*!< LPADC_T::ADDR13: OVERRUN Mask */ 558 559 #define LPADC_ADDR13_VALID_Pos (17) /*!< LPADC_T::ADDR13: VALID Position */ 560 #define LPADC_ADDR13_VALID_Msk (0x1ul << LPADC_ADDR13_VALID_Pos) /*!< LPADC_T::ADDR13: VALID Mask */ 561 562 #define LPADC_ADDR14_RSLT_Pos (0) /*!< LPADC_T::ADDR14: RSLT Position */ 563 #define LPADC_ADDR14_RSLT_Msk (0xfffful << LPADC_ADDR14_RSLT_Pos) /*!< LPADC_T::ADDR14: RSLT Mask */ 564 565 #define LPADC_ADDR14_OVERRUN_Pos (16) /*!< LPADC_T::ADDR14: OVERRUN Position */ 566 #define LPADC_ADDR14_OVERRUN_Msk (0x1ul << LPADC_ADDR14_OVERRUN_Pos) /*!< LPADC_T::ADDR14: OVERRUN Mask */ 567 568 #define LPADC_ADDR14_VALID_Pos (17) /*!< LPADC_T::ADDR14: VALID Position */ 569 #define LPADC_ADDR14_VALID_Msk (0x1ul << LPADC_ADDR14_VALID_Pos) /*!< LPADC_T::ADDR14: VALID Mask */ 570 571 #define LPADC_ADDR15_RSLT_Pos (0) /*!< LPADC_T::ADDR15: RSLT Position */ 572 #define LPADC_ADDR15_RSLT_Msk (0xfffful << LPADC_ADDR15_RSLT_Pos) /*!< LPADC_T::ADDR15: RSLT Mask */ 573 574 #define LPADC_ADDR15_OVERRUN_Pos (16) /*!< LPADC_T::ADDR15: OVERRUN Position */ 575 #define LPADC_ADDR15_OVERRUN_Msk (0x1ul << LPADC_ADDR15_OVERRUN_Pos) /*!< LPADC_T::ADDR15: OVERRUN Mask */ 576 577 #define LPADC_ADDR15_VALID_Pos (17) /*!< LPADC_T::ADDR15: VALID Position */ 578 #define LPADC_ADDR15_VALID_Msk (0x1ul << LPADC_ADDR15_VALID_Pos) /*!< LPADC_T::ADDR15: VALID Mask */ 579 580 #define LPADC_ADDR16_RSLT_Pos (0) /*!< LPADC_T::ADDR16: RSLT Position */ 581 #define LPADC_ADDR16_RSLT_Msk (0xfffful << LPADC_ADDR16_RSLT_Pos) /*!< LPADC_T::ADDR16: RSLT Mask */ 582 583 #define LPADC_ADDR16_OVERRUN_Pos (16) /*!< LPADC_T::ADDR16: OVERRUN Position */ 584 #define LPADC_ADDR16_OVERRUN_Msk (0x1ul << LPADC_ADDR16_OVERRUN_Pos) /*!< LPADC_T::ADDR16: OVERRUN Mask */ 585 586 #define LPADC_ADDR16_VALID_Pos (17) /*!< LPADC_T::ADDR16: VALID Position */ 587 #define LPADC_ADDR16_VALID_Msk (0x1ul << LPADC_ADDR16_VALID_Pos) /*!< LPADC_T::ADDR16: VALID Mask */ 588 589 #define LPADC_ADDR17_RSLT_Pos (0) /*!< LPADC_T::ADDR17: RSLT Position */ 590 #define LPADC_ADDR17_RSLT_Msk (0xfffful << LPADC_ADDR17_RSLT_Pos) /*!< LPADC_T::ADDR17: RSLT Mask */ 591 592 #define LPADC_ADDR17_OVERRUN_Pos (16) /*!< LPADC_T::ADDR17: OVERRUN Position */ 593 #define LPADC_ADDR17_OVERRUN_Msk (0x1ul << LPADC_ADDR17_OVERRUN_Pos) /*!< LPADC_T::ADDR17: OVERRUN Mask */ 594 595 #define LPADC_ADDR17_VALID_Pos (17) /*!< LPADC_T::ADDR17: VALID Position */ 596 #define LPADC_ADDR17_VALID_Msk (0x1ul << LPADC_ADDR17_VALID_Pos) /*!< LPADC_T::ADDR17: VALID Mask */ 597 598 #define LPADC_ADDR18_RSLT_Pos (0) /*!< LPADC_T::ADDR18: RSLT Position */ 599 #define LPADC_ADDR18_RSLT_Msk (0xfffful << LPADC_ADDR18_RSLT_Pos) /*!< LPADC_T::ADDR18: RSLT Mask */ 600 601 #define LPADC_ADDR18_OVERRUN_Pos (16) /*!< LPADC_T::ADDR18: OVERRUN Position */ 602 #define LPADC_ADDR18_OVERRUN_Msk (0x1ul << LPADC_ADDR18_OVERRUN_Pos) /*!< LPADC_T::ADDR18: OVERRUN Mask */ 603 604 #define LPADC_ADDR18_VALID_Pos (17) /*!< LPADC_T::ADDR18: VALID Position */ 605 #define LPADC_ADDR18_VALID_Msk (0x1ul << LPADC_ADDR18_VALID_Pos) /*!< LPADC_T::ADDR18: VALID Mask */ 606 607 #define LPADC_ADDR19_RSLT_Pos (0) /*!< LPADC_T::ADDR19: RSLT Position */ 608 #define LPADC_ADDR19_RSLT_Msk (0xfffful << LPADC_ADDR19_RSLT_Pos) /*!< LPADC_T::ADDR19: RSLT Mask */ 609 610 #define LPADC_ADDR19_OVERRUN_Pos (16) /*!< LPADC_T::ADDR19: OVERRUN Position */ 611 #define LPADC_ADDR19_OVERRUN_Msk (0x1ul << LPADC_ADDR19_OVERRUN_Pos) /*!< LPADC_T::ADDR19: OVERRUN Mask */ 612 613 #define LPADC_ADDR19_VALID_Pos (17) /*!< LPADC_T::ADDR19: VALID Position */ 614 #define LPADC_ADDR19_VALID_Msk (0x1ul << LPADC_ADDR19_VALID_Pos) /*!< LPADC_T::ADDR19: VALID Mask */ 615 616 #define LPADC_ADDR20_RSLT_Pos (0) /*!< LPADC_T::ADDR20: RSLT Position */ 617 #define LPADC_ADDR20_RSLT_Msk (0xfffful << LPADC_ADDR20_RSLT_Pos) /*!< LPADC_T::ADDR20: RSLT Mask */ 618 619 #define LPADC_ADDR20_OVERRUN_Pos (16) /*!< LPADC_T::ADDR20: OVERRUN Position */ 620 #define LPADC_ADDR20_OVERRUN_Msk (0x1ul << LPADC_ADDR20_OVERRUN_Pos) /*!< LPADC_T::ADDR20: OVERRUN Mask */ 621 622 #define LPADC_ADDR20_VALID_Pos (17) /*!< LPADC_T::ADDR20: VALID Position */ 623 #define LPADC_ADDR20_VALID_Msk (0x1ul << LPADC_ADDR20_VALID_Pos) /*!< LPADC_T::ADDR20: VALID Mask */ 624 625 #define LPADC_ADDR21_RSLT_Pos (0) /*!< LPADC_T::ADDR21: RSLT Position */ 626 #define LPADC_ADDR21_RSLT_Msk (0xfffful << LPADC_ADDR21_RSLT_Pos) /*!< LPADC_T::ADDR21: RSLT Mask */ 627 628 #define LPADC_ADDR21_OVERRUN_Pos (16) /*!< LPADC_T::ADDR21: OVERRUN Position */ 629 #define LPADC_ADDR21_OVERRUN_Msk (0x1ul << LPADC_ADDR21_OVERRUN_Pos) /*!< LPADC_T::ADDR21: OVERRUN Mask */ 630 631 #define LPADC_ADDR21_VALID_Pos (17) /*!< LPADC_T::ADDR21: VALID Position */ 632 #define LPADC_ADDR21_VALID_Msk (0x1ul << LPADC_ADDR21_VALID_Pos) /*!< LPADC_T::ADDR21: VALID Mask */ 633 634 #define LPADC_ADDR22_RSLT_Pos (0) /*!< LPADC_T::ADDR22: RSLT Position */ 635 #define LPADC_ADDR22_RSLT_Msk (0xfffful << LPADC_ADDR22_RSLT_Pos) /*!< LPADC_T::ADDR22: RSLT Mask */ 636 637 #define LPADC_ADDR22_OVERRUN_Pos (16) /*!< LPADC_T::ADDR22: OVERRUN Position */ 638 #define LPADC_ADDR22_OVERRUN_Msk (0x1ul << LPADC_ADDR22_OVERRUN_Pos) /*!< LPADC_T::ADDR22: OVERRUN Mask */ 639 640 #define LPADC_ADDR22_VALID_Pos (17) /*!< LPADC_T::ADDR22: VALID Position */ 641 #define LPADC_ADDR22_VALID_Msk (0x1ul << LPADC_ADDR22_VALID_Pos) /*!< LPADC_T::ADDR22: VALID Mask */ 642 643 #define LPADC_ADDR23_RSLT_Pos (0) /*!< LPADC_T::ADDR23: RSLT Position */ 644 #define LPADC_ADDR23_RSLT_Msk (0xfffful << LPADC_ADDR23_RSLT_Pos) /*!< LPADC_T::ADDR23: RSLT Mask */ 645 646 #define LPADC_ADDR23_OVERRUN_Pos (16) /*!< LPADC_T::ADDR23: OVERRUN Position */ 647 #define LPADC_ADDR23_OVERRUN_Msk (0x1ul << LPADC_ADDR23_OVERRUN_Pos) /*!< LPADC_T::ADDR23: OVERRUN Mask */ 648 649 #define LPADC_ADDR23_VALID_Pos (17) /*!< LPADC_T::ADDR23: VALID Position */ 650 #define LPADC_ADDR23_VALID_Msk (0x1ul << LPADC_ADDR23_VALID_Pos) /*!< LPADC_T::ADDR23: VALID Mask */ 651 652 #define LPADC_ADDR24_RSLT_Pos (0) /*!< LPADC_T::ADDR24: RSLT Position */ 653 #define LPADC_ADDR24_RSLT_Msk (0xfffful << LPADC_ADDR24_RSLT_Pos) /*!< LPADC_T::ADDR24: RSLT Mask */ 654 655 #define LPADC_ADDR24_OVERRUN_Pos (16) /*!< LPADC_T::ADDR24: OVERRUN Position */ 656 #define LPADC_ADDR24_OVERRUN_Msk (0x1ul << LPADC_ADDR24_OVERRUN_Pos) /*!< LPADC_T::ADDR24: OVERRUN Mask */ 657 658 #define LPADC_ADDR24_VALID_Pos (17) /*!< LPADC_T::ADDR24: VALID Position */ 659 #define LPADC_ADDR24_VALID_Msk (0x1ul << LPADC_ADDR24_VALID_Pos) /*!< LPADC_T::ADDR24: VALID Mask */ 660 661 #define LPADC_ADDR25_RSLT_Pos (0) /*!< LPADC_T::ADDR25: RSLT Position */ 662 #define LPADC_ADDR25_RSLT_Msk (0xfffful << LPADC_ADDR25_RSLT_Pos) /*!< LPADC_T::ADDR25: RSLT Mask */ 663 664 #define LPADC_ADDR25_OVERRUN_Pos (16) /*!< LPADC_T::ADDR25: OVERRUN Position */ 665 #define LPADC_ADDR25_OVERRUN_Msk (0x1ul << LPADC_ADDR25_OVERRUN_Pos) /*!< LPADC_T::ADDR25: OVERRUN Mask */ 666 667 #define LPADC_ADDR25_VALID_Pos (17) /*!< LPADC_T::ADDR25: VALID Position */ 668 #define LPADC_ADDR25_VALID_Msk (0x1ul << LPADC_ADDR25_VALID_Pos) /*!< LPADC_T::ADDR25: VALID Mask */ 669 670 #define LPADC_ADDR26_RSLT_Pos (0) /*!< LPADC_T::ADDR26: RSLT Position */ 671 #define LPADC_ADDR26_RSLT_Msk (0xfffful << LPADC_ADDR26_RSLT_Pos) /*!< LPADC_T::ADDR26: RSLT Mask */ 672 673 #define LPADC_ADDR26_OVERRUN_Pos (16) /*!< LPADC_T::ADDR26: OVERRUN Position */ 674 #define LPADC_ADDR26_OVERRUN_Msk (0x1ul << LPADC_ADDR26_OVERRUN_Pos) /*!< LPADC_T::ADDR26: OVERRUN Mask */ 675 676 #define LPADC_ADDR26_VALID_Pos (17) /*!< LPADC_T::ADDR26: VALID Position */ 677 #define LPADC_ADDR26_VALID_Msk (0x1ul << LPADC_ADDR26_VALID_Pos) /*!< LPADC_T::ADDR26: VALID Mask */ 678 679 #define LPADC_ADDR28_RSLT_Pos (0) /*!< LPADC_T::ADDR28: RSLT Position */ 680 #define LPADC_ADDR28_RSLT_Msk (0xfffful << LPADC_ADDR28_RSLT_Pos) /*!< LPADC_T::ADDR28: RSLT Mask */ 681 682 #define LPADC_ADDR28_OVERRUN_Pos (16) /*!< LPADC_T::ADDR28: OVERRUN Position */ 683 #define LPADC_ADDR28_OVERRUN_Msk (0x1ul << LPADC_ADDR28_OVERRUN_Pos) /*!< LPADC_T::ADDR28: OVERRUN Mask */ 684 685 #define LPADC_ADDR28_VALID_Pos (17) /*!< LPADC_T::ADDR28: VALID Position */ 686 #define LPADC_ADDR28_VALID_Msk (0x1ul << LPADC_ADDR28_VALID_Pos) /*!< LPADC_T::ADDR28: VALID Mask */ 687 688 #define LPADC_ADDR29_RSLT_Pos (0) /*!< LPADC_T::ADDR29: RSLT Position */ 689 #define LPADC_ADDR29_RSLT_Msk (0xfffful << LPADC_ADDR29_RSLT_Pos) /*!< LPADC_T::ADDR29: RSLT Mask */ 690 691 #define LPADC_ADDR29_OVERRUN_Pos (16) /*!< LPADC_T::ADDR29: OVERRUN Position */ 692 #define LPADC_ADDR29_OVERRUN_Msk (0x1ul << LPADC_ADDR29_OVERRUN_Pos) /*!< LPADC_T::ADDR29: OVERRUN Mask */ 693 694 #define LPADC_ADDR29_VALID_Pos (17) /*!< LPADC_T::ADDR29: VALID Position */ 695 #define LPADC_ADDR29_VALID_Msk (0x1ul << LPADC_ADDR29_VALID_Pos) /*!< LPADC_T::ADDR29: VALID Mask */ 696 697 #define LPADC_ADDR30_RSLT_Pos (0) /*!< LPADC_T::ADDR30: RSLT Position */ 698 #define LPADC_ADDR30_RSLT_Msk (0xfffful << LPADC_ADDR30_RSLT_Pos) /*!< LPADC_T::ADDR30: RSLT Mask */ 699 700 #define LPADC_ADDR30_OVERRUN_Pos (16) /*!< LPADC_T::ADDR30: OVERRUN Position */ 701 #define LPADC_ADDR30_OVERRUN_Msk (0x1ul << LPADC_ADDR30_OVERRUN_Pos) /*!< LPADC_T::ADDR30: OVERRUN Mask */ 702 703 #define LPADC_ADDR30_VALID_Pos (17) /*!< LPADC_T::ADDR30: VALID Position */ 704 #define LPADC_ADDR30_VALID_Msk (0x1ul << LPADC_ADDR30_VALID_Pos) /*!< LPADC_T::ADDR30: VALID Mask */ 705 706 #define LPADC_ADDR31_RSLT_Pos (0) /*!< LPADC_T::ADDR31: RSLT Position */ 707 #define LPADC_ADDR31_RSLT_Msk (0xfffful << LPADC_ADDR31_RSLT_Pos) /*!< LPADC_T::ADDR31: RSLT Mask */ 708 709 #define LPADC_ADDR31_OVERRUN_Pos (16) /*!< LPADC_T::ADDR31: OVERRUN Position */ 710 #define LPADC_ADDR31_OVERRUN_Msk (0x1ul << LPADC_ADDR31_OVERRUN_Pos) /*!< LPADC_T::ADDR31: OVERRUN Mask */ 711 712 #define LPADC_ADDR31_VALID_Pos (17) /*!< LPADC_T::ADDR31: VALID Position */ 713 #define LPADC_ADDR31_VALID_Msk (0x1ul << LPADC_ADDR31_VALID_Pos) /*!< LPADC_T::ADDR31: VALID Mask */ 714 715 #define LPADC_ADCR_ADEN_Pos (0) /*!< LPADC_T::ADCR: ADEN Position */ 716 #define LPADC_ADCR_ADEN_Msk (0x1ul << LPADC_ADCR_ADEN_Pos) /*!< LPADC_T::ADCR: ADEN Mask */ 717 718 #define LPADC_ADCR_ADIE_Pos (1) /*!< LPADC_T::ADCR: ADIE Position */ 719 #define LPADC_ADCR_ADIE_Msk (0x1ul << LPADC_ADCR_ADIE_Pos) /*!< LPADC_T::ADCR: ADIE Mask */ 720 721 #define LPADC_ADCR_ADMD_Pos (2) /*!< LPADC_T::ADCR: ADMD Position */ 722 #define LPADC_ADCR_ADMD_Msk (0x3ul << LPADC_ADCR_ADMD_Pos) /*!< LPADC_T::ADCR: ADMD Mask */ 723 724 #define LPADC_ADCR_TRGCOND_Pos (6) /*!< LPADC_T::ADCR: TRGCOND Position */ 725 #define LPADC_ADCR_TRGCOND_Msk (0x3ul << LPADC_ADCR_TRGCOND_Pos) /*!< LPADC_T::ADCR: TRGCOND Mask */ 726 727 #define LPADC_ADCR_TRGEN_Pos (8) /*!< LPADC_T::ADCR: TRGEN Position */ 728 #define LPADC_ADCR_TRGEN_Msk (0x1ul << LPADC_ADCR_TRGEN_Pos) /*!< LPADC_T::ADCR: TRGEN Mask */ 729 730 #define LPADC_ADCR_PTEN_Pos (9) /*!< LPADC_T::ADCR: PTEN Position */ 731 #define LPADC_ADCR_PTEN_Msk (0x1ul << LPADC_ADCR_PTEN_Pos) /*!< LPADC_T::ADCR: PTEN Mask */ 732 733 #define LPADC_ADCR_DIFFEN_Pos (10) /*!< LPADC_T::ADCR: DIFFEN Position */ 734 #define LPADC_ADCR_DIFFEN_Msk (0x1ul << LPADC_ADCR_DIFFEN_Pos) /*!< LPADC_T::ADCR: DIFFEN Mask */ 735 736 #define LPADC_ADCR_ADST_Pos (11) /*!< LPADC_T::ADCR: ADST Position */ 737 #define LPADC_ADCR_ADST_Msk (0x1ul << LPADC_ADCR_ADST_Pos) /*!< LPADC_T::ADCR: ADST Mask */ 738 739 #define LPADC_ADCR_RESET_Pos (12) /*!< LPADC_T::ADCR: RESET Position */ 740 #define LPADC_ADCR_RESET_Msk (0x1ul << LPADC_ADCR_RESET_Pos) /*!< LPADC_T::ADCR: RESET Mask */ 741 742 #define LPADC_ADCR_TRGS_Pos (16) /*!< LPADC_T::ADCR: TRGS Position */ 743 #define LPADC_ADCR_TRGS_Msk (0xful << LPADC_ADCR_TRGS_Pos) /*!< LPADC_T::ADCR: TRGS Mask */ 744 745 #define LPADC_ADCR_ACMPTES_Pos (20) /*!< LPADC_T::ADCR: ACMPTES Position */ 746 #define LPADC_ADCR_ACMPTES_Msk (0x3ul << LPADC_ADCR_ACMPTES_Pos) /*!< LPADC_T::ADCR: ACMPTES Mask */ 747 748 #define LPADC_ADCR_RESSEL_Pos (28) /*!< LPADC_T::ADCR: RESSEL Position */ 749 #define LPADC_ADCR_RESSEL_Msk (0x3ul << LPADC_ADCR_RESSEL_Pos) /*!< LPADC_T::ADCR: RESSEL Mask */ 750 751 #define LPADC_ADCR_DMOF_Pos (31) /*!< LPADC_T::ADCR: DMOF Position */ 752 #define LPADC_ADCR_DMOF_Msk (0x1ul << LPADC_ADCR_DMOF_Pos) /*!< LPADC_T::ADCR: DMOF Mask */ 753 754 #define LPADC_ADCHER_CHEN_Pos (0) /*!< LPADC_T::ADCHER: CHEN Position */ 755 #define LPADC_ADCHER_CHEN_Msk (0xfffffffful << LPADC_ADCHER_CHEN_Pos) /*!< LPADC_T::ADCHER: CHEN Mask */ 756 757 #define LPADC_ADCMPR_CMPEN_Pos (0) /*!< LPADC_T::ADCMPR: CMPEN Position */ 758 #define LPADC_ADCMPR_CMPEN_Msk (0x1ul << LPADC_ADCMPR_CMPEN_Pos) /*!< LPADC_T::ADCMPR: CMPEN Mask */ 759 760 #define LPADC_ADCMPR_CMPIE_Pos (1) /*!< LPADC_T::ADCMPR: CMPIE Position */ 761 #define LPADC_ADCMPR_CMPIE_Msk (0x1ul << LPADC_ADCMPR_CMPIE_Pos) /*!< LPADC_T::ADCMPR: CMPIE Mask */ 762 763 #define LPADC_ADCMPR_CMPCOND_Pos (2) /*!< LPADC_T::ADCMPR: CMPCOND Position */ 764 #define LPADC_ADCMPR_CMPCOND_Msk (0x1ul << LPADC_ADCMPR_CMPCOND_Pos) /*!< LPADC_T::ADCMPR: CMPCOND Mask */ 765 766 #define LPADC_ADCMPR_CMPCH_Pos (3) /*!< LPADC_T::ADCMPR: CMPCH Position */ 767 #define LPADC_ADCMPR_CMPCH_Msk (0x1ful << LPADC_ADCMPR_CMPCH_Pos) /*!< LPADC_T::ADCMPR: CMPCH Mask */ 768 769 #define LPADC_ADCMPR_CMPMCNT_Pos (8) /*!< LPADC_T::ADCMPR: CMPMCNT Position */ 770 #define LPADC_ADCMPR_CMPMCNT_Msk (0xful << LPADC_ADCMPR_CMPMCNT_Pos) /*!< LPADC_T::ADCMPR: CMPMCNT Mask */ 771 772 #define LPADC_ADCMPR_CMPWEN_Pos (15) /*!< LPADC_T::ADCMPR: CMPWEN Position */ 773 #define LPADC_ADCMPR_CMPWEN_Msk (0x1ul << LPADC_ADCMPR_CMPWEN_Pos) /*!< LPADC_T::ADCMPR: CMPWEN Mask */ 774 775 #define LPADC_ADCMPR_CMPD_Pos (16) /*!< LPADC_T::ADCMPR: CMPD Position */ 776 #define LPADC_ADCMPR_CMPD_Msk (0xffful << LPADC_ADCMPR_CMPD_Pos) /*!< LPADC_T::ADCMPR: CMPD Mask */ 777 778 #define LPADC_ADCMPR0_CMPEN_Pos (0) /*!< LPADC_T::ADCMPR0: CMPEN Position */ 779 #define LPADC_ADCMPR0_CMPEN_Msk (0x1ul << LPADC_ADCMPR0_CMPEN_Pos) /*!< LPADC_T::ADCMPR0: CMPEN Mask */ 780 781 #define LPADC_ADCMPR0_CMPIE_Pos (1) /*!< LPADC_T::ADCMPR0: CMPIE Position */ 782 #define LPADC_ADCMPR0_CMPIE_Msk (0x1ul << LPADC_ADCMPR0_CMPIE_Pos) /*!< LPADC_T::ADCMPR0: CMPIE Mask */ 783 784 #define LPADC_ADCMPR0_CMPCOND_Pos (2) /*!< LPADC_T::ADCMPR0: CMPCOND Position */ 785 #define LPADC_ADCMPR0_CMPCOND_Msk (0x1ul << LPADC_ADCMPR0_CMPCOND_Pos) /*!< LPADC_T::ADCMPR0: CMPCOND Mask */ 786 787 #define LPADC_ADCMPR0_CMPCH_Pos (3) /*!< LPADC_T::ADCMPR0: CMPCH Position */ 788 #define LPADC_ADCMPR0_CMPCH_Msk (0x1ful << LPADC_ADCMPR0_CMPCH_Pos) /*!< LPADC_T::ADCMPR0: CMPCH Mask */ 789 790 #define LPADC_ADCMPR0_CMPMCNT_Pos (8) /*!< LPADC_T::ADCMPR0: CMPMCNT Position */ 791 #define LPADC_ADCMPR0_CMPMCNT_Msk (0xful << LPADC_ADCMPR0_CMPMCNT_Pos) /*!< LPADC_T::ADCMPR0: CMPMCNT Mask */ 792 793 #define LPADC_ADCMPR0_CMPWEN_Pos (15) /*!< LPADC_T::ADCMPR0: CMPWEN Position */ 794 #define LPADC_ADCMPR0_CMPWEN_Msk (0x1ul << LPADC_ADCMPR0_CMPWEN_Pos) /*!< LPADC_T::ADCMPR0: CMPWEN Mask */ 795 796 #define LPADC_ADCMPR0_CMPD_Pos (16) /*!< LPADC_T::ADCMPR0: CMPD Position */ 797 #define LPADC_ADCMPR0_CMPD_Msk (0xffful << LPADC_ADCMPR0_CMPD_Pos) /*!< LPADC_T::ADCMPR0: CMPD Mask */ 798 799 #define LPADC_ADCMPR1_CMPEN_Pos (0) /*!< LPADC_T::ADCMPR1: CMPEN Position */ 800 #define LPADC_ADCMPR1_CMPEN_Msk (0x1ul << LPADC_ADCMPR1_CMPEN_Pos) /*!< LPADC_T::ADCMPR1: CMPEN Mask */ 801 802 #define LPADC_ADCMPR1_CMPIE_Pos (1) /*!< LPADC_T::ADCMPR1: CMPIE Position */ 803 #define LPADC_ADCMPR1_CMPIE_Msk (0x1ul << LPADC_ADCMPR1_CMPIE_Pos) /*!< LPADC_T::ADCMPR1: CMPIE Mask */ 804 805 #define LPADC_ADCMPR1_CMPCOND_Pos (2) /*!< LPADC_T::ADCMPR1: CMPCOND Position */ 806 #define LPADC_ADCMPR1_CMPCOND_Msk (0x1ul << LPADC_ADCMPR1_CMPCOND_Pos) /*!< LPADC_T::ADCMPR1: CMPCOND Mask */ 807 808 #define LPADC_ADCMPR1_CMPCH_Pos (3) /*!< LPADC_T::ADCMPR1: CMPCH Position */ 809 #define LPADC_ADCMPR1_CMPCH_Msk (0x1ful << LPADC_ADCMPR1_CMPCH_Pos) /*!< LPADC_T::ADCMPR1: CMPCH Mask */ 810 811 #define LPADC_ADCMPR1_CMPMCNT_Pos (8) /*!< LPADC_T::ADCMPR1: CMPMCNT Position */ 812 #define LPADC_ADCMPR1_CMPMCNT_Msk (0xful << LPADC_ADCMPR1_CMPMCNT_Pos) /*!< LPADC_T::ADCMPR1: CMPMCNT Mask */ 813 814 #define LPADC_ADCMPR1_CMPWEN_Pos (15) /*!< LPADC_T::ADCMPR1: CMPWEN Position */ 815 #define LPADC_ADCMPR1_CMPWEN_Msk (0x1ul << LPADC_ADCMPR1_CMPWEN_Pos) /*!< LPADC_T::ADCMPR1: CMPWEN Mask */ 816 817 #define LPADC_ADCMPR1_CMPD_Pos (16) /*!< LPADC_T::ADCMPR1: CMPD Position */ 818 #define LPADC_ADCMPR1_CMPD_Msk (0xffful << LPADC_ADCMPR1_CMPD_Pos) /*!< LPADC_T::ADCMPR1: CMPD Mask */ 819 820 #define LPADC_ADSR0_ADF_Pos (0) /*!< LPADC_T::ADSR0: ADF Position */ 821 #define LPADC_ADSR0_ADF_Msk (0x1ul << LPADC_ADSR0_ADF_Pos) /*!< LPADC_T::ADSR0: ADF Mask */ 822 823 #define LPADC_ADSR0_CMPF0_Pos (1) /*!< LPADC_T::ADSR0: CMPF0 Position */ 824 #define LPADC_ADSR0_CMPF0_Msk (0x1ul << LPADC_ADSR0_CMPF0_Pos) /*!< LPADC_T::ADSR0: CMPF0 Mask */ 825 826 #define LPADC_ADSR0_CMPF1_Pos (2) /*!< LPADC_T::ADSR0: CMPF1 Position */ 827 #define LPADC_ADSR0_CMPF1_Msk (0x1ul << LPADC_ADSR0_CMPF1_Pos) /*!< LPADC_T::ADSR0: CMPF1 Mask */ 828 829 #define LPADC_ADSR0_BUSY_Pos (7) /*!< LPADC_T::ADSR0: BUSY Position */ 830 #define LPADC_ADSR0_BUSY_Msk (0x1ul << LPADC_ADSR0_BUSY_Pos) /*!< LPADC_T::ADSR0: BUSY Mask */ 831 832 #define LPADC_ADSR0_VALIDF_Pos (8) /*!< LPADC_T::ADSR0: VALIDF Position */ 833 #define LPADC_ADSR0_VALIDF_Msk (0x1ul << LPADC_ADSR0_VALIDF_Pos) /*!< LPADC_T::ADSR0: VALIDF Mask */ 834 835 #define LPADC_ADSR0_OVERRUNF_Pos (16) /*!< LPADC_T::ADSR0: OVERRUNF Position */ 836 #define LPADC_ADSR0_OVERRUNF_Msk (0x1ul << LPADC_ADSR0_OVERRUNF_Pos) /*!< LPADC_T::ADSR0: OVERRUNF Mask */ 837 838 #define LPADC_ADSR0_ADPRDY_Pos (24) /*!< LPADC_T::ADSR0: ADPRDY Position */ 839 #define LPADC_ADSR0_ADPRDY_Msk (0x1ul << LPADC_ADSR0_ADPRDY_Pos) /*!< LPADC_T::ADSR0: ADPRDY Mask */ 840 841 #define LPADC_ADSR0_CHANNEL_Pos (27) /*!< LPADC_T::ADSR0: CHANNEL Position */ 842 #define LPADC_ADSR0_CHANNEL_Msk (0x1ful << LPADC_ADSR0_CHANNEL_Pos) /*!< LPADC_T::ADSR0: CHANNEL Mask */ 843 844 #define LPADC_ADSR1_VALID_Pos (0) /*!< LPADC_T::ADSR1: VALID Position */ 845 #define LPADC_ADSR1_VALID_Msk (0xfffffffful << LPADC_ADSR1_VALID_Pos) /*!< LPADC_T::ADSR1: VALID Mask */ 846 847 #define LPADC_ADSR2_OVERRUN_Pos (0) /*!< LPADC_T::ADSR2: OVERRUN Position */ 848 #define LPADC_ADSR2_OVERRUN_Msk (0xfffffffful << LPADC_ADSR2_OVERRUN_Pos) /*!< LPADC_T::ADSR2: OVERRUN Mask */ 849 850 #define LPADC_ESMPCTL_EXTSMPT_Pos (0) /*!< LPADC_T::ESMPCTL: EXTSMPT Position */ 851 #define LPADC_ESMPCTL_EXTSMPT_Msk (0x3ffful << LPADC_ESMPCTL_EXTSMPT_Pos) /*!< LPADC_T::ESMPCTL: EXTSMPT Mask */ 852 853 #define LPADC_CFDCTL_PRECHEN_Pos (0) /*!< LPADC_T::CFDCTL: PRECHEN Position */ 854 #define LPADC_CFDCTL_PRECHEN_Msk (0x1ul << LPADC_CFDCTL_PRECHEN_Pos) /*!< LPADC_T::CFDCTL: PRECHEN Mask */ 855 856 #define LPADC_CFDCTL_DISCHEN_Pos (1) /*!< LPADC_T::CFDCTL: DISCHEN Position */ 857 #define LPADC_CFDCTL_DISCHEN_Msk (0x1ul << LPADC_CFDCTL_DISCHEN_Pos) /*!< LPADC_T::CFDCTL: DISCHEN Mask */ 858 859 #define LPADC_CFDCTL_FDETCHEN_Pos (8) /*!< LPADC_T::CFDCTL: FDETCHEN Position */ 860 #define LPADC_CFDCTL_FDETCHEN_Msk (0x1ul << LPADC_CFDCTL_FDETCHEN_Pos) /*!< LPADC_T::CFDCTL: FDETCHEN Mask */ 861 862 #define LPADC_ADPDMA_CURDAT_Pos (0) /*!< LPADC_T::ADPDMA: CURDAT Position */ 863 #define LPADC_ADPDMA_CURDAT_Msk (0x3fffful << LPADC_ADPDMA_CURDAT_Pos) /*!< LPADC_T::ADPDMA: CURDAT Mask */ 864 865 #define LPADC_ADCAL_CALEN_Pos (0) /*!< LPADC_T::ADCAL: CALEN Position */ 866 #define LPADC_ADCAL_CALEN_Msk (0x1ul << LPADC_ADCAL_CALEN_Pos) /*!< LPADC_T::ADCAL: CALEN Mask */ 867 868 #define LPADC_ADCAL_CALIE_Pos (1) /*!< LPADC_T::ADCAL: CALIE Position */ 869 #define LPADC_ADCAL_CALIE_Msk (0x1ul << LPADC_ADCAL_CALIE_Pos) /*!< LPADC_T::ADCAL: CALIE Mask */ 870 871 #define LPADC_ADCALSTS_CALIF_Pos (0) /*!< LPADC_T::ADCALSTS: CALIF Position */ 872 #define LPADC_ADCALSTS_CALIF_Msk (0x1ul << LPADC_ADCALSTS_CALIF_Pos) /*!< LPADC_T::ADCALSTS: CALIF Mask */ 873 874 #define LPADC_AUTOCTL_TRIGSEL_Pos (0) /*!< LPADC_T::AUTOCTL: TRIGSEL Position */ 875 #define LPADC_AUTOCTL_TRIGSEL_Msk (0xful << LPADC_AUTOCTL_TRIGSEL_Pos) /*!< LPADC_T::AUTOCTL: TRIGSEL Mask */ 876 877 #define LPADC_AUTOCTL_TRIGEN_Pos (4) /*!< LPADC_T::AUTOCTL: TRIGEN Position */ 878 #define LPADC_AUTOCTL_TRIGEN_Msk (0x1ul << LPADC_AUTOCTL_TRIGEN_Pos) /*!< LPADC_T::AUTOCTL: TRIGEN Mask */ 879 880 #define LPADC_AUTOCTL_ADWKEN_Pos (8) /*!< LPADC_T::AUTOCTL: ADWKEN Position */ 881 #define LPADC_AUTOCTL_ADWKEN_Msk (0x1ul << LPADC_AUTOCTL_ADWKEN_Pos) /*!< LPADC_T::AUTOCTL: ADWKEN Mask */ 882 883 #define LPADC_AUTOCTL_CMP0WKEN_Pos (9) /*!< LPADC_T::AUTOCTL: CMP0WKEN Position */ 884 #define LPADC_AUTOCTL_CMP0WKEN_Msk (0x1ul << LPADC_AUTOCTL_CMP0WKEN_Pos) /*!< LPADC_T::AUTOCTL: CMP0WKEN Mask */ 885 886 #define LPADC_AUTOCTL_CMP1WKEN_Pos (10) /*!< LPADC_T::AUTOCTL: CMP1WKEN Position */ 887 #define LPADC_AUTOCTL_CMP1WKEN_Msk (0x1ul << LPADC_AUTOCTL_CMP1WKEN_Pos) /*!< LPADC_T::AUTOCTL: CMP1WKEN Mask */ 888 889 #define LPADC_AUTOCTL_AUTOEN_Pos (31) /*!< LPADC_T::AUTOCTL: AUTOEN Position */ 890 #define LPADC_AUTOCTL_AUTOEN_Msk (0x1ul << LPADC_AUTOCTL_AUTOEN_Pos) /*!< LPADC_T::AUTOCTL: AUTOEN Mask */ 891 892 #define LPADC_AUTOSTRG_SWTRIG_Pos (0) /*!< LPADC_T::AUTOSTRG: SWTRIG Position */ 893 #define LPADC_AUTOSTRG_SWTRIG_Msk (0x1ul << LPADC_AUTOSTRG_SWTRIG_Pos) /*!< LPADC_T::AUTOSTRG: SWTRIG Mask */ 894 895 #define LPADC_AUTOSTS_ADWKF_Pos (0) /*!< LPADC_T::AUTOSTS: ADWKF Position */ 896 #define LPADC_AUTOSTS_ADWKF_Msk (0x1ul << LPADC_AUTOSTS_ADWKF_Pos) /*!< LPADC_T::AUTOSTS: ADWKF Mask */ 897 898 #define LPADC_AUTOSTS_CMP0WKF_Pos (1) /*!< LPADC_T::AUTOSTS: CMP0WKF Position */ 899 #define LPADC_AUTOSTS_CMP0WKF_Msk (0x1ul << LPADC_AUTOSTS_CMP0WKF_Pos) /*!< LPADC_T::AUTOSTS: CMP0WKF Mask */ 900 901 #define LPADC_AUTOSTS_CMP1WKF_Pos (2) /*!< LPADC_T::AUTOSTS: CMP1WKF Position */ 902 #define LPADC_AUTOSTS_CMP1WKF_Msk (0x1ul << LPADC_AUTOSTS_CMP1WKF_Pos) /*!< LPADC_T::AUTOSTS: CMP1WKF Mask */ 903 904 #define LPADC_ALDOCTL_ALDOEN_Pos (8) /*!< LPADC_T::ALDOCTL: ALDOEN Position */ 905 #define LPADC_ALDOCTL_ALDOEN_Msk (0x1ul << LPADC_ALDOCTL_ALDOEN_Pos) /*!< LPADC_T::ALDOCTL: ALDOEN Mask */ 906 907 #define LPADC_ALDOCTL_STBSEL_Pos (16) /*!< LPADC_T::ALDOCTL: STBSEL Position */ 908 #define LPADC_ALDOCTL_STBSEL_Msk (0x7ul << LPADC_ALDOCTL_STBSEL_Pos) /*!< LPADC_T::ALDOCTL: STBSEL Mask */ 909 910 #define LPADC_ALDOCTL_IGENEN_Pos (23) /*!< LPADC_T::ALDOCTL: IGENEN Position */ 911 #define LPADC_ALDOCTL_IGENEN_Msk (0x1ul << LPADC_ALDOCTL_IGENEN_Pos) /*!< LPADC_T::ALDOCTL: IGENEN Mask */ 912 913 /**@}*/ /* LPADC_CONST */ 914 /**@}*/ /* end of LPADC register group */ 915 /**@}*/ /* end of REGISTER group */ 916 917 #if defined ( __CC_ARM ) 918 #pragma no_anon_unions 919 #endif 920 921 #endif /* __LPADC_REG_H__ */ 922
