1 /* 2 * Copyright (c) 2017-2022 ARM Limited 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __REGION_DEFS_H__ 18 #define __REGION_DEFS_H__ 19 #include "flash_layout.h" 20 21 #define BL2_HEAP_SIZE 0x0001000 22 #define BL2_MSP_STACK_SIZE 0x0002000 23 24 #define LOADER_NS_MSP_STACK_SIZE 0x0000400 25 #define LOADER_NS_HEAP_SIZE 0x0000200 26 #define LOADER_NS_PSP_STACK_SIZE 0x0000400 27 28 #define LOADER_S_MSP_STACK_SIZE 0x0000400 29 #define LOADER_S_HEAP_SIZE 0x0000200 30 #define LOADER_S_PSP_STACK_SIZE 0x0000400 31 32 33 #ifdef ENABLE_HEAP 34 #define S_HEAP_SIZE (0x0000200) 35 #else 36 #define S_HEAP_SIZE (0x0000000) 37 #endif 38 39 #define S_MSP_STACK_SIZE 0x0000800 40 #define S_PSP_STACK_SIZE 0x0000800 41 42 #define NS_HEAP_SIZE 0x0001000 43 #define NS_STACK_SIZE 0x0001800 44 45 /* GTZC specific Alignment */ 46 #define GTZC_RAM_ALIGN 512 47 #define GTZC_FLASH_ALIGN 8192 48 49 /* FIX ME : include stm32u5xx.h instead */ 50 #define _SRAM2_TOP (0x40000) /* 256Kbytes */ 51 #define _SRAM1_SIZE_MAX (0x30000) /*!< SRAM1=192k*/ 52 #define _SRAM2_SIZE_MAX (0x10000 - BOOT_TFM_SHARED_DATA_SIZE) /*!< SRAM2=64k -0x400 */ 53 #define _SRAM3_SIZE_MAX (0x80000) /* 512Kbytes */ 54 #define _SRAM4_SIZE_MAX (0x04000) /* 16Kbytes */ 55 56 /* Flash and internal SRAMs base addresses - Non secure aliased */ 57 #define _FLASH_BASE_NS (0x08000000) /*!< FLASH(up to 512 KB) base address */ 58 #define _SRAM1_BASE_NS (0x20000000) /*!< SRAM1(up to 192 KB) base address */ 59 #define _SRAM2_BASE_NS (0x20030000) /*!< SRAM2(64 KB) base address */ 60 #define _SRAM3_BASE_NS (0x20040000) /*!< SRAM3(512 KB) base address */ 61 #define _SRAM4_BASE_NS (0x28000000) /*!< SRAM4(16 KB) base address */ 62 /* Flash and internal SRAMs base addresses - Secure aliased */ 63 #define _FLASH_BASE_S (0x0C000000) /*!< FLASH(up to 512 KB) base address */ 64 #define _SRAM1_BASE_S (0x30000000) /*!< SRAM1(up to 192 KB) base address */ 65 #define _SRAM2_BASE_S (0x30030000) /*!< SRAM2(64 KB) base address */ 66 #define _SRAM3_BASE_S (0x30040000) /*!< SRAM3(512 KB) base address */ 67 #define _SRAM4_BASE_S (0x38000000) /*!< SRAM4(16 KB) base address */ 68 69 #define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE 70 #define TOTAL_RAM_SIZE (_SRAM1_SIZE_MAX +_SRAM2_SIZE_MAX) 71 /* 192 + 64 Kbytes - BOOT info */ 72 /* boot info are placed and locked at top of SRAM2 */ 73 74 #define S_TOTAL_RAM2_SIZE (_SRAM2_SIZE_MAX) /*! size require for Secure part */ 75 #define S_TOTAL_RAM1_SIZE (0x10000) 76 #define S_TOTAL_RAM_SIZE (S_TOTAL_RAM2_SIZE + S_TOTAL_RAM1_SIZE) 77 #define NS_TOTAL_RAM_SIZE (TOTAL_RAM_SIZE - S_TOTAL_RAM_SIZE) 78 79 /* 80 * Boot partition structure if MCUBoot is used: 81 * 0x0_0000 Bootloader header 82 * 0x0_0400 Image area 83 * 0x7_0000 Trailer 84 */ 85 /* IMAGE_CODE_SIZE is the space available for the software binary image. 86 * It is less than the FLASH_PARTITION_SIZE because we reserve space 87 * for the image header and trailer introduced by the bootloader. 88 */ 89 90 #ifdef BL2 91 #define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) 92 #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) 93 #define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET + FLASH_S_PARTITION_SIZE) 94 #define NS_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET + FLASH_S_PARTITION_SIZE) 95 #else 96 #error "Config without BL2 not supported" 97 #endif /* BL2 */ 98 99 100 #define IMAGE_S_CODE_SIZE \ 101 (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) 102 #define IMAGE_NS_CODE_SIZE \ 103 (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) 104 105 /* FIXME: veneer region size is increased temporarily while both legacy veneers 106 * and their iovec-based equivalents co-exist for secure partitions. To be 107 * adjusted as legacy veneers are eliminated 108 */ 109 #define CMSE_VENEER_REGION_SIZE (0x00000380) 110 111 /* Use SRAM1 memory to store Code data */ 112 #define S_ROM_ALIAS_BASE (_FLASH_BASE_S) 113 #define NS_ROM_ALIAS_BASE (_FLASH_BASE_NS) 114 115 116 #define S_RAM_ALIAS_BASE (_SRAM1_BASE_S) 117 #define NS_RAM_ALIAS_BASE (_SRAM1_BASE_NS) 118 119 /* Alias definitions for secure and non-secure areas*/ 120 #define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) 121 #define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) 122 123 #define LOADER_NS_ROM_ALIAS(x) (_FLASH_BASE_NS + (x)) 124 #define LOADER_S_ROM_ALIAS(x) (_FLASH_BASE_S + (x)) 125 126 #define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) 127 #define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) 128 129 130 #define S_IMAGE_PRIMARY_AREA_OFFSET (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) 131 #define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) 132 #define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE) 133 #define S_CODE_LIMIT ((S_CODE_START + S_CODE_SIZE) -1) 134 #define S_DATA_START (S_RAM_ALIAS(NS_TOTAL_RAM_SIZE)) 135 #define S_DATA_SIZE (S_TOTAL_RAM_SIZE) 136 #define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) 137 138 /* CMSE Veneers region */ 139 #define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1) 140 /* Non-secure regions */ 141 142 /* Secure regions , the end of secure regions must be aligned on page size for dual bank 0x800*/ 143 /* Offset and size definition in flash area, used by assemble.py 144 * 0x11400+0x33c00= 13000+34000 = 45000*/ 145 146 #define NS_IMAGE_PRIMARY_AREA_OFFSET (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) 147 #define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) 148 #define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) 149 #define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) 150 #define NS_DATA_START (NS_RAM_ALIAS(0)) 151 #define NS_NO_INIT_DATA_SIZE (0x100) 152 #define NS_DATA_SIZE (NS_TOTAL_RAM_SIZE) 153 #define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) 154 155 /* NS partition information is used for MPC and SAU configuration */ 156 #define NS_PARTITION_START (NS_CODE_START) 157 #define NS_PARTITION_SIZE (NS_CODE_SIZE) 158 159 /* Secondary partition for new images/ in case of firmware upgrade */ 160 #define SECONDARY_PARTITION_START (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET)) 161 #define SECONDARY_PARTITION_SIZE (FLASH_AREA_2_SIZE) 162 163 #ifdef BL2 164 /* Personalized region */ 165 #define PERSO_START (S_ROM_ALIAS(FLASH_AREA_PERSO_OFFSET)) 166 #define PERSO_SIZE (FLASH_AREA_PERSO_SIZE) 167 #define PERSO_LIMIT (PERSO_START + PERSO_SIZE - 1) 168 169 /* Bootloader region protected by hdp */ 170 #define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)) 171 #define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) 172 #define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) 173 174 /* Bootloader region not protected by hdp */ 175 #define BL2_NOHDP_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_NOHDP_OFFSET)) 176 #define BL2_NOHDP_CODE_SIZE (FLASH_AREA_BL2_NOHDP_SIZE) 177 #define BL2_NOHDP_CODE_LIMIT (BL2_NOHDP_CODE_START + BL2_NOHDP_CODE_SIZE - 1) 178 179 /* Bootloader boot address */ 180 #define BL2_BOOT_VTOR_ADDR (BL2_CODE_START) 181 182 /* keep 256 bytes unused to place while(1) for non secure to enable */ 183 /* regression from local tool with non secure attachment 184 * This avoid blocking board in case of hardening error */ 185 #define BL2_DATA_START (S_RAM_ALIAS(_SRAM1_SIZE_MAX)) 186 #define BL2_DATA_SIZE (BOOT_TFM_SHARED_DATA_BASE - BL2_DATA_START) 187 #define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) 188 189 /* Define BL2 MPU SRAM protection to remove execution capability */ 190 /* Area is covering the complete SRAM memory space non secure alias and secure alias */ 191 #define BL2_SRAM_AREA_BASE (_SRAM1_BASE_NS) 192 #define BL2_SRAM_AREA_END (_SRAM4_BASE_S + _SRAM4_SIZE_MAX -1) 193 194 /* Define Area provision by BL2 */ 195 #define BL2_OTP_AREA_BASE S_ROM_ALIAS(TFM_OTP_NV_COUNTERS_AREA_ADDR) 196 #define BL2_OTP_AREA_SIZE (TFM_OTP_NV_COUNTERS_AREA_SIZE) 197 /* Define Area for Initializing NVM counter */ 198 /* backup sector is initialised */ 199 #define BL2_NVM_AREA_BASE S_ROM_ALIAS(TFM_NV_COUNTERS_AREA_ADDR+FLASH_AREA_IMAGE_SECTOR_SIZE) 200 #define BL2_NVM_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) 201 /* Define Area for initializing BL2_NVCNT */ 202 /* backup sector is initialised */ 203 #define BL2_NVMCNT_AREA_BASE S_ROM_ALIAS(FLASH_BL2_NVCNT_AREA_OFFSET+FLASH_AREA_IMAGE_SECTOR_SIZE) 204 #define BL2_NVMCNT_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) 205 #endif /* BL2 */ 206 207 208 #define LOADER_NS_CODE_SIZE (0x6000) /* 24 Kbytes */ 209 210 #if defined(MCUBOOT_PRIMARY_ONLY) 211 /* Secure Loader Image */ 212 #define FLASH_AREA_LOADER_BANK_OFFSET (FLASH_B_SIZE-LOADER_IMAGE_S_CODE_SIZE-LOADER_NS_CODE_SIZE) 213 #define FLASH_AREA_LOADER_OFFSET (FLASH_TOTAL_SIZE-LOADER_IMAGE_S_CODE_SIZE-LOADER_NS_CODE_SIZE) 214 /* Control Secure Loader Image */ 215 #if (FLASH_AREA_LOADER_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 216 #error "FLASH_AREA_LOADER_OFFSET not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" 217 #endif /* (FLASH_AREA_LOADER_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ 218 219 /* Non-Secure Loader Image */ 220 #define LOADER_NS_CODE_START (LOADER_NS_ROM_ALIAS(FLASH_AREA_LOADER_OFFSET + LOADER_IMAGE_S_CODE_SIZE)) 221 /* Control Non-Secure Loader Image */ 222 #if (LOADER_NS_CODE_START % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 223 #error "LOADER_NS_CODE_START not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" 224 #endif /* (LOADER_NS_CODE_START % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ 225 226 /* define used for checking possible overlap */ 227 #define LOADER_CODE_SIZE (LOADER_NS_CODE_SIZE+LOADER_IMAGE_S_CODE_SIZE) 228 #else 229 /* Loader Image */ 230 #define FLASH_AREA_LOADER_BANK_OFFSET (FLASH_B_SIZE-LOADER_NS_CODE_SIZE) 231 #define FLASH_AREA_LOADER_OFFSET (FLASH_TOTAL_SIZE-LOADER_NS_CODE_SIZE) 232 /* Control Loader Image */ 233 #if (FLASH_AREA_LOADER_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 234 #error "FLASH_AREA_LOADER_OFFSET not aligned on FLASH_AREA_IMAGE_SECTOR_SIZE" 235 #endif /* (FLASH_AREA_LOADER_OFFSET % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0 */ 236 237 #define LOADER_NS_CODE_START (LOADER_NS_ROM_ALIAS(FLASH_AREA_LOADER_OFFSET)) 238 /* define used for checking possible overlap */ 239 #define LOADER_CODE_SIZE (LOADER_NS_CODE_SIZE) 240 #endif /* MCUBOOT_PRIMARY_ONLY */ 241 242 #define LOADER_IMAGE_S_CODE_SIZE (0x4000) /* 16 Kbytes */ 243 #define LOADER_CMSE_VENEER_REGION_SIZE (0x100) 244 #define LOADER_S_CODE_START (LOADER_S_ROM_ALIAS(FLASH_AREA_LOADER_OFFSET)) 245 #define LOADER_S_CODE_SIZE (LOADER_IMAGE_S_CODE_SIZE - LOADER_CMSE_VENEER_REGION_SIZE) 246 #define LOADER_S_CODE_LIMIT (LOADER_S_CODE_START + LOADER_S_CODE_SIZE -1) 247 #define LOADER_S_DATA_START (S_RAM_ALIAS(_SRAM1_SIZE_MAX)) 248 #define LOADER_S_DATA_SIZE (_SRAM2_SIZE_MAX) 249 #define LOADER_S_DATA_LIMIT (LOADER_S_DATA_START + LOADER_S_DATA_SIZE - 1) 250 #define LOADER_CMSE_VENEER_REGION_START (LOADER_S_CODE_LIMIT + 1) 251 #define LOADER_CMSE_VENEER_REGION_LIMIT (LOADER_S_ROM_ALIAS(FLASH_AREA_LOADER_OFFSET+LOADER_IMAGE_S_CODE_SIZE - 1)) 252 253 #define LOADER_NS_CODE_LIMIT (LOADER_NS_CODE_START+LOADER_NS_CODE_SIZE - 1) 254 #define LOADER_NS_DATA_START (NS_RAM_ALIAS(0x0)) 255 #define LOADER_NS_DATA_SIZE (_SRAM1_SIZE_MAX) 256 #define LOADER_NS_DATA_LIMIT (LOADER_NS_DATA_START + LOADER_NS_DATA_SIZE - 1) 257 258 #ifdef MCUBOOT_PRIMARY_ONLY 259 #define LOADER_MAX_CODE_SIZE (FLASH_TOTAL_SIZE - FLASH_AREA_1_OFFSET - FLASH_AREA_1_SIZE) 260 #else 261 #define LOADER_MAX_CODE_SIZE (FLASH_TOTAL_SIZE - FLASH_AREA_3_OFFSET - FLASH_AREA_3_SIZE) 262 #endif /* MCUBOOT_PRIMARY_ONLY */ 263 264 #if LOADER_CODE_SIZE > LOADER_MAX_CODE_SIZE 265 #error "Loader mapping overlapping slot %LOADER_CODE_SIZE %LOADER_MAX_CODE_SIZE" 266 #endif /* LOADER_CODE_SIZE > LOADER_MAX_CODE_SIZE */ 267 268 /* TFM non volatile data (NVCNT/PS/ITS) region */ 269 #define TFM_NV_DATA_START (S_ROM_ALIAS(FLASH_AREA_OTP_OFFSET)) 270 #define TFM_NV_DATA_SIZE (FLASH_AREA_OTP_SIZE + FLASH_NV_COUNTERS_AREA_SIZE \ 271 + FLASH_PS_AREA_SIZE + FLASH_ITS_AREA_SIZE) 272 #define TFM_NV_DATA_LIMIT (TFM_NV_DATA_START + TFM_NV_DATA_SIZE - 1) 273 /* Additional Check to detect flash download slot overlap or overflow */ 274 #if defined(MCUBOOT_EXT_LOADER) 275 #define FLASH_AREA_END_OFFSET_MAX FLASH_AREA_LOADER_OFFSET 276 #else 277 #define FLASH_AREA_END_OFFSET_MAX (FLASH_TOTAL_SIZE) 278 #endif /* defined(MCUBOOT_EXT_LOADER) */ 279 280 #if FLASH_AREA_END_OFFSET > FLASH_AREA_END_OFFSET_MAX 281 #error "Flash memory overflow" 282 #endif /* FLASH_AREA_END_OFFSET > FLASH_AREA_END_OFFSET_MAX */ 283 284 #endif /* __REGION_DEFS_H__ */ 285
