1 /***************************************************************************//** 2 * \file cyip_crypto_v2.h 3 * 4 * \brief 5 * CRYPTO IP definitions 6 * 7 * \note 8 * Generator version: 1.6.0.409 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _CYIP_CRYPTO_V2_H_ 29 #define _CYIP_CRYPTO_V2_H_ 30 31 #include "cyip_headers.h" 32 33 /******************************************************************************* 34 * CRYPTO 35 *******************************************************************************/ 36 37 #define CRYPTO_V2_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Cryptography component (CRYPTO) 41 */ 42 typedef struct { 43 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 44 __IM uint32_t RESERVED; 45 __IOM uint32_t RAM_PWR_CTL; /*!< 0x00000008 SRAM power control */ 46 __IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x0000000C SRAM power delay control */ 47 __IOM uint32_t ECC_CTL; /*!< 0x00000010 ECC control */ 48 __IM uint32_t RESERVED1[3]; 49 __IM uint32_t ERROR_STATUS0; /*!< 0x00000020 Error status 0 */ 50 __IOM uint32_t ERROR_STATUS1; /*!< 0x00000024 Error status 1 */ 51 __IM uint32_t RESERVED2[54]; 52 __IOM uint32_t INTR; /*!< 0x00000100 Interrupt register */ 53 __IOM uint32_t INTR_SET; /*!< 0x00000104 Interrupt set register */ 54 __IOM uint32_t INTR_MASK; /*!< 0x00000108 Interrupt mask register */ 55 __IM uint32_t INTR_MASKED; /*!< 0x0000010C Interrupt masked register */ 56 __IM uint32_t RESERVED3[60]; 57 __IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */ 58 __IOM uint32_t PR_LFSR_CTL1; /*!< 0x00000204 Pseudo random LFSR control 1 */ 59 __IOM uint32_t PR_LFSR_CTL2; /*!< 0x00000208 Pseudo random LFSR control 2 */ 60 __IOM uint32_t PR_MAX_CTL; /*!< 0x0000020C Pseudo random maximum control */ 61 __IOM uint32_t PR_CMD; /*!< 0x00000210 Pseudo random command */ 62 __IM uint32_t RESERVED4; 63 __IOM uint32_t PR_RESULT; /*!< 0x00000218 Pseudo random result */ 64 __IM uint32_t RESERVED5[25]; 65 __IOM uint32_t TR_CTL0; /*!< 0x00000280 True random control 0 */ 66 __IOM uint32_t TR_CTL1; /*!< 0x00000284 True random control 1 */ 67 __IOM uint32_t TR_CTL2; /*!< 0x00000288 True random control 2 */ 68 __IM uint32_t TR_STATUS; /*!< 0x0000028C True random status */ 69 __IOM uint32_t TR_CMD; /*!< 0x00000290 True random command */ 70 __IM uint32_t RESERVED6; 71 __IOM uint32_t TR_RESULT; /*!< 0x00000298 True random result */ 72 __IM uint32_t RESERVED7; 73 __IOM uint32_t TR_GARO_CTL; /*!< 0x000002A0 True random GARO control */ 74 __IOM uint32_t TR_FIRO_CTL; /*!< 0x000002A4 True random FIRO control */ 75 __IM uint32_t RESERVED8[6]; 76 __IOM uint32_t TR_MON_CTL; /*!< 0x000002C0 True random monitor control */ 77 __IM uint32_t RESERVED9; 78 __IOM uint32_t TR_MON_CMD; /*!< 0x000002C8 True random monitor command */ 79 __IM uint32_t RESERVED10; 80 __IOM uint32_t TR_MON_RC_CTL; /*!< 0x000002D0 True random monitor RC control */ 81 __IM uint32_t RESERVED11; 82 __IM uint32_t TR_MON_RC_STATUS0; /*!< 0x000002D8 True random monitor RC status 0 */ 83 __IM uint32_t TR_MON_RC_STATUS1; /*!< 0x000002DC True random monitor RC status 1 */ 84 __IOM uint32_t TR_MON_AP_CTL; /*!< 0x000002E0 True random monitor AP control */ 85 __IM uint32_t RESERVED12; 86 __IM uint32_t TR_MON_AP_STATUS0; /*!< 0x000002E8 True random monitor AP status 0 */ 87 __IM uint32_t TR_MON_AP_STATUS1; /*!< 0x000002EC True random monitor AP status 1 */ 88 __IM uint32_t RESERVED13[837]; 89 __IM uint32_t STATUS; /*!< 0x00001004 Status */ 90 __IM uint32_t RESERVED14[14]; 91 __IOM uint32_t INSTR_FF_CTL; /*!< 0x00001040 Instruction FIFO control */ 92 __IM uint32_t INSTR_FF_STATUS; /*!< 0x00001044 Instruction FIFO status */ 93 __OM uint32_t INSTR_FF_WR; /*!< 0x00001048 Instruction FIFO write */ 94 __IM uint32_t RESERVED15[29]; 95 __IM uint32_t LOAD0_FF_STATUS; /*!< 0x000010C0 Load 0 FIFO status */ 96 __IM uint32_t RESERVED16[3]; 97 __IM uint32_t LOAD1_FF_STATUS; /*!< 0x000010D0 Load 1 FIFO status */ 98 __IM uint32_t RESERVED17[7]; 99 __IM uint32_t STORE_FF_STATUS; /*!< 0x000010F0 Store FIFO status */ 100 __IM uint32_t RESERVED18[3]; 101 __IOM uint32_t AES_CTL; /*!< 0x00001100 AES control */ 102 __IM uint32_t RESERVED19[31]; 103 __IOM uint32_t RESULT; /*!< 0x00001180 Result */ 104 __IM uint32_t RESERVED20[159]; 105 __IOM uint32_t CRC_CTL; /*!< 0x00001400 CRC control */ 106 __IM uint32_t RESERVED21[3]; 107 __IOM uint32_t CRC_DATA_CTL; /*!< 0x00001410 CRC data control */ 108 __IM uint32_t RESERVED22[3]; 109 __IOM uint32_t CRC_POL_CTL; /*!< 0x00001420 CRC polynomial control */ 110 __IM uint32_t RESERVED23[7]; 111 __IOM uint32_t CRC_REM_CTL; /*!< 0x00001440 CRC remainder control */ 112 __IM uint32_t RESERVED24; 113 __IM uint32_t CRC_REM_RESULT; /*!< 0x00001448 CRC remainder result */ 114 __IM uint32_t RESERVED25[13]; 115 __IOM uint32_t VU_CTL0; /*!< 0x00001480 Vector unit control 0 */ 116 __IOM uint32_t VU_CTL1; /*!< 0x00001484 Vector unit control 1 */ 117 __IOM uint32_t VU_CTL2; /*!< 0x00001488 Vector unit control 2 */ 118 __IM uint32_t RESERVED26; 119 __IM uint32_t VU_STATUS; /*!< 0x00001490 Vector unit status */ 120 __IM uint32_t RESERVED27[11]; 121 __IM uint32_t VU_RF_DATA[16]; /*!< 0x000014C0 Vector unit register-file */ 122 __IM uint32_t RESERVED28[704]; 123 __IOM uint32_t DEV_KEY_ADDR0_CTL; /*!< 0x00002000 Device key address 0 control */ 124 __IOM uint32_t DEV_KEY_ADDR0; /*!< 0x00002004 Device key address 0 */ 125 __IM uint32_t RESERVED29[6]; 126 __IOM uint32_t DEV_KEY_ADDR1_CTL; /*!< 0x00002020 Device key address 1 control */ 127 __IOM uint32_t DEV_KEY_ADDR1; /*!< 0x00002024 Device key address 1 control */ 128 __IM uint32_t RESERVED30[22]; 129 __IM uint32_t DEV_KEY_STATUS; /*!< 0x00002080 Device key status */ 130 __IM uint32_t RESERVED31[31]; 131 __IOM uint32_t DEV_KEY_CTL0; /*!< 0x00002100 Device key control 0 */ 132 __IM uint32_t RESERVED32[7]; 133 __IOM uint32_t DEV_KEY_CTL1; /*!< 0x00002120 Device key control 1 */ 134 __IM uint32_t RESERVED33[6071]; 135 __IOM uint32_t MEM_BUFF[8192]; /*!< 0x00008000 Memory buffer */ 136 } CRYPTO_V2_Type; /*!< Size = 65536 (0x10000) */ 137 138 139 /* CRYPTO.CTL */ 140 #define CRYPTO_V2_CTL_P_Pos 0UL 141 #define CRYPTO_V2_CTL_P_Msk 0x1UL 142 #define CRYPTO_V2_CTL_NS_Pos 1UL 143 #define CRYPTO_V2_CTL_NS_Msk 0x2UL 144 #define CRYPTO_V2_CTL_PC_Pos 4UL 145 #define CRYPTO_V2_CTL_PC_Msk 0xF0UL 146 #define CRYPTO_V2_CTL_ECC_EN_Pos 16UL 147 #define CRYPTO_V2_CTL_ECC_EN_Msk 0x10000UL 148 #define CRYPTO_V2_CTL_ECC_INJ_EN_Pos 17UL 149 #define CRYPTO_V2_CTL_ECC_INJ_EN_Msk 0x20000UL 150 #define CRYPTO_V2_CTL_ENABLED_Pos 31UL 151 #define CRYPTO_V2_CTL_ENABLED_Msk 0x80000000UL 152 /* CRYPTO.RAM_PWR_CTL */ 153 #define CRYPTO_V2_RAM_PWR_CTL_PWR_MODE_Pos 0UL 154 #define CRYPTO_V2_RAM_PWR_CTL_PWR_MODE_Msk 0x3UL 155 /* CRYPTO.RAM_PWR_DELAY_CTL */ 156 #define CRYPTO_V2_RAM_PWR_DELAY_CTL_UP_Pos 0UL 157 #define CRYPTO_V2_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL 158 /* CRYPTO.ECC_CTL */ 159 #define CRYPTO_V2_ECC_CTL_WORD_ADDR_Pos 0UL 160 #define CRYPTO_V2_ECC_CTL_WORD_ADDR_Msk 0x1FFFUL 161 #define CRYPTO_V2_ECC_CTL_PARITY_Pos 25UL 162 #define CRYPTO_V2_ECC_CTL_PARITY_Msk 0xFE000000UL 163 /* CRYPTO.ERROR_STATUS0 */ 164 #define CRYPTO_V2_ERROR_STATUS0_DATA32_Pos 0UL 165 #define CRYPTO_V2_ERROR_STATUS0_DATA32_Msk 0xFFFFFFFFUL 166 /* CRYPTO.ERROR_STATUS1 */ 167 #define CRYPTO_V2_ERROR_STATUS1_DATA24_Pos 0UL 168 #define CRYPTO_V2_ERROR_STATUS1_DATA24_Msk 0xFFFFFFUL 169 #define CRYPTO_V2_ERROR_STATUS1_IDX_Pos 24UL 170 #define CRYPTO_V2_ERROR_STATUS1_IDX_Msk 0x7000000UL 171 #define CRYPTO_V2_ERROR_STATUS1_VALID_Pos 31UL 172 #define CRYPTO_V2_ERROR_STATUS1_VALID_Msk 0x80000000UL 173 /* CRYPTO.INTR */ 174 #define CRYPTO_V2_INTR_INSTR_FF_LEVEL_Pos 0UL 175 #define CRYPTO_V2_INTR_INSTR_FF_LEVEL_Msk 0x1UL 176 #define CRYPTO_V2_INTR_INSTR_FF_OVERFLOW_Pos 1UL 177 #define CRYPTO_V2_INTR_INSTR_FF_OVERFLOW_Msk 0x2UL 178 #define CRYPTO_V2_INTR_TR_INITIALIZED_Pos 2UL 179 #define CRYPTO_V2_INTR_TR_INITIALIZED_Msk 0x4UL 180 #define CRYPTO_V2_INTR_TR_DATA_AVAILABLE_Pos 3UL 181 #define CRYPTO_V2_INTR_TR_DATA_AVAILABLE_Msk 0x8UL 182 #define CRYPTO_V2_INTR_PR_DATA_AVAILABLE_Pos 4UL 183 #define CRYPTO_V2_INTR_PR_DATA_AVAILABLE_Msk 0x10UL 184 #define CRYPTO_V2_INTR_INSTR_OPC_ERROR_Pos 16UL 185 #define CRYPTO_V2_INTR_INSTR_OPC_ERROR_Msk 0x10000UL 186 #define CRYPTO_V2_INTR_INSTR_CC_ERROR_Pos 17UL 187 #define CRYPTO_V2_INTR_INSTR_CC_ERROR_Msk 0x20000UL 188 #define CRYPTO_V2_INTR_BUS_ERROR_Pos 18UL 189 #define CRYPTO_V2_INTR_BUS_ERROR_Msk 0x40000UL 190 #define CRYPTO_V2_INTR_TR_AP_DETECT_ERROR_Pos 19UL 191 #define CRYPTO_V2_INTR_TR_AP_DETECT_ERROR_Msk 0x80000UL 192 #define CRYPTO_V2_INTR_TR_RC_DETECT_ERROR_Pos 20UL 193 #define CRYPTO_V2_INTR_TR_RC_DETECT_ERROR_Msk 0x100000UL 194 #define CRYPTO_V2_INTR_INSTR_DEV_KEY_ERROR_Pos 21UL 195 #define CRYPTO_V2_INTR_INSTR_DEV_KEY_ERROR_Msk 0x200000UL 196 /* CRYPTO.INTR_SET */ 197 #define CRYPTO_V2_INTR_SET_INSTR_FF_LEVEL_Pos 0UL 198 #define CRYPTO_V2_INTR_SET_INSTR_FF_LEVEL_Msk 0x1UL 199 #define CRYPTO_V2_INTR_SET_INSTR_FF_OVERFLOW_Pos 1UL 200 #define CRYPTO_V2_INTR_SET_INSTR_FF_OVERFLOW_Msk 0x2UL 201 #define CRYPTO_V2_INTR_SET_TR_INITIALIZED_Pos 2UL 202 #define CRYPTO_V2_INTR_SET_TR_INITIALIZED_Msk 0x4UL 203 #define CRYPTO_V2_INTR_SET_TR_DATA_AVAILABLE_Pos 3UL 204 #define CRYPTO_V2_INTR_SET_TR_DATA_AVAILABLE_Msk 0x8UL 205 #define CRYPTO_V2_INTR_SET_PR_DATA_AVAILABLE_Pos 4UL 206 #define CRYPTO_V2_INTR_SET_PR_DATA_AVAILABLE_Msk 0x10UL 207 #define CRYPTO_V2_INTR_SET_INSTR_OPC_ERROR_Pos 16UL 208 #define CRYPTO_V2_INTR_SET_INSTR_OPC_ERROR_Msk 0x10000UL 209 #define CRYPTO_V2_INTR_SET_INSTR_CC_ERROR_Pos 17UL 210 #define CRYPTO_V2_INTR_SET_INSTR_CC_ERROR_Msk 0x20000UL 211 #define CRYPTO_V2_INTR_SET_BUS_ERROR_Pos 18UL 212 #define CRYPTO_V2_INTR_SET_BUS_ERROR_Msk 0x40000UL 213 #define CRYPTO_V2_INTR_SET_TR_AP_DETECT_ERROR_Pos 19UL 214 #define CRYPTO_V2_INTR_SET_TR_AP_DETECT_ERROR_Msk 0x80000UL 215 #define CRYPTO_V2_INTR_SET_TR_RC_DETECT_ERROR_Pos 20UL 216 #define CRYPTO_V2_INTR_SET_TR_RC_DETECT_ERROR_Msk 0x100000UL 217 #define CRYPTO_V2_INTR_SET_INSTR_DEV_KEY_ERROR_Pos 21UL 218 #define CRYPTO_V2_INTR_SET_INSTR_DEV_KEY_ERROR_Msk 0x200000UL 219 /* CRYPTO.INTR_MASK */ 220 #define CRYPTO_V2_INTR_MASK_INSTR_FF_LEVEL_Pos 0UL 221 #define CRYPTO_V2_INTR_MASK_INSTR_FF_LEVEL_Msk 0x1UL 222 #define CRYPTO_V2_INTR_MASK_INSTR_FF_OVERFLOW_Pos 1UL 223 #define CRYPTO_V2_INTR_MASK_INSTR_FF_OVERFLOW_Msk 0x2UL 224 #define CRYPTO_V2_INTR_MASK_TR_INITIALIZED_Pos 2UL 225 #define CRYPTO_V2_INTR_MASK_TR_INITIALIZED_Msk 0x4UL 226 #define CRYPTO_V2_INTR_MASK_TR_DATA_AVAILABLE_Pos 3UL 227 #define CRYPTO_V2_INTR_MASK_TR_DATA_AVAILABLE_Msk 0x8UL 228 #define CRYPTO_V2_INTR_MASK_PR_DATA_AVAILABLE_Pos 4UL 229 #define CRYPTO_V2_INTR_MASK_PR_DATA_AVAILABLE_Msk 0x10UL 230 #define CRYPTO_V2_INTR_MASK_INSTR_OPC_ERROR_Pos 16UL 231 #define CRYPTO_V2_INTR_MASK_INSTR_OPC_ERROR_Msk 0x10000UL 232 #define CRYPTO_V2_INTR_MASK_INSTR_CC_ERROR_Pos 17UL 233 #define CRYPTO_V2_INTR_MASK_INSTR_CC_ERROR_Msk 0x20000UL 234 #define CRYPTO_V2_INTR_MASK_BUS_ERROR_Pos 18UL 235 #define CRYPTO_V2_INTR_MASK_BUS_ERROR_Msk 0x40000UL 236 #define CRYPTO_V2_INTR_MASK_TR_AP_DETECT_ERROR_Pos 19UL 237 #define CRYPTO_V2_INTR_MASK_TR_AP_DETECT_ERROR_Msk 0x80000UL 238 #define CRYPTO_V2_INTR_MASK_TR_RC_DETECT_ERROR_Pos 20UL 239 #define CRYPTO_V2_INTR_MASK_TR_RC_DETECT_ERROR_Msk 0x100000UL 240 #define CRYPTO_V2_INTR_MASK_INSTR_DEV_KEY_ERROR_Pos 21UL 241 #define CRYPTO_V2_INTR_MASK_INSTR_DEV_KEY_ERROR_Msk 0x200000UL 242 /* CRYPTO.INTR_MASKED */ 243 #define CRYPTO_V2_INTR_MASKED_INSTR_FF_LEVEL_Pos 0UL 244 #define CRYPTO_V2_INTR_MASKED_INSTR_FF_LEVEL_Msk 0x1UL 245 #define CRYPTO_V2_INTR_MASKED_INSTR_FF_OVERFLOW_Pos 1UL 246 #define CRYPTO_V2_INTR_MASKED_INSTR_FF_OVERFLOW_Msk 0x2UL 247 #define CRYPTO_V2_INTR_MASKED_TR_INITIALIZED_Pos 2UL 248 #define CRYPTO_V2_INTR_MASKED_TR_INITIALIZED_Msk 0x4UL 249 #define CRYPTO_V2_INTR_MASKED_TR_DATA_AVAILABLE_Pos 3UL 250 #define CRYPTO_V2_INTR_MASKED_TR_DATA_AVAILABLE_Msk 0x8UL 251 #define CRYPTO_V2_INTR_MASKED_PR_DATA_AVAILABLE_Pos 4UL 252 #define CRYPTO_V2_INTR_MASKED_PR_DATA_AVAILABLE_Msk 0x10UL 253 #define CRYPTO_V2_INTR_MASKED_INSTR_OPC_ERROR_Pos 16UL 254 #define CRYPTO_V2_INTR_MASKED_INSTR_OPC_ERROR_Msk 0x10000UL 255 #define CRYPTO_V2_INTR_MASKED_INSTR_CC_ERROR_Pos 17UL 256 #define CRYPTO_V2_INTR_MASKED_INSTR_CC_ERROR_Msk 0x20000UL 257 #define CRYPTO_V2_INTR_MASKED_BUS_ERROR_Pos 18UL 258 #define CRYPTO_V2_INTR_MASKED_BUS_ERROR_Msk 0x40000UL 259 #define CRYPTO_V2_INTR_MASKED_TR_AP_DETECT_ERROR_Pos 19UL 260 #define CRYPTO_V2_INTR_MASKED_TR_AP_DETECT_ERROR_Msk 0x80000UL 261 #define CRYPTO_V2_INTR_MASKED_TR_RC_DETECT_ERROR_Pos 20UL 262 #define CRYPTO_V2_INTR_MASKED_TR_RC_DETECT_ERROR_Msk 0x100000UL 263 #define CRYPTO_V2_INTR_MASKED_INSTR_DEV_KEY_ERROR_Pos 21UL 264 #define CRYPTO_V2_INTR_MASKED_INSTR_DEV_KEY_ERROR_Msk 0x200000UL 265 /* CRYPTO.PR_LFSR_CTL0 */ 266 #define CRYPTO_V2_PR_LFSR_CTL0_LFSR32_Pos 0UL 267 #define CRYPTO_V2_PR_LFSR_CTL0_LFSR32_Msk 0xFFFFFFFFUL 268 /* CRYPTO.PR_LFSR_CTL1 */ 269 #define CRYPTO_V2_PR_LFSR_CTL1_LFSR31_Pos 0UL 270 #define CRYPTO_V2_PR_LFSR_CTL1_LFSR31_Msk 0x7FFFFFFFUL 271 /* CRYPTO.PR_LFSR_CTL2 */ 272 #define CRYPTO_V2_PR_LFSR_CTL2_LFSR29_Pos 0UL 273 #define CRYPTO_V2_PR_LFSR_CTL2_LFSR29_Msk 0x1FFFFFFFUL 274 /* CRYPTO.PR_MAX_CTL */ 275 #define CRYPTO_V2_PR_MAX_CTL_DATA32_Pos 0UL 276 #define CRYPTO_V2_PR_MAX_CTL_DATA32_Msk 0xFFFFFFFFUL 277 /* CRYPTO.PR_CMD */ 278 #define CRYPTO_V2_PR_CMD_START_Pos 0UL 279 #define CRYPTO_V2_PR_CMD_START_Msk 0x1UL 280 /* CRYPTO.PR_RESULT */ 281 #define CRYPTO_V2_PR_RESULT_DATA32_Pos 0UL 282 #define CRYPTO_V2_PR_RESULT_DATA32_Msk 0xFFFFFFFFUL 283 /* CRYPTO.TR_CTL0 */ 284 #define CRYPTO_V2_TR_CTL0_SAMPLE_CLOCK_DIV_Pos 0UL 285 #define CRYPTO_V2_TR_CTL0_SAMPLE_CLOCK_DIV_Msk 0xFFUL 286 #define CRYPTO_V2_TR_CTL0_RED_CLOCK_DIV_Pos 8UL 287 #define CRYPTO_V2_TR_CTL0_RED_CLOCK_DIV_Msk 0xFF00UL 288 #define CRYPTO_V2_TR_CTL0_INIT_DELAY_Pos 16UL 289 #define CRYPTO_V2_TR_CTL0_INIT_DELAY_Msk 0xFF0000UL 290 #define CRYPTO_V2_TR_CTL0_VON_NEUMANN_CORR_Pos 24UL 291 #define CRYPTO_V2_TR_CTL0_VON_NEUMANN_CORR_Msk 0x1000000UL 292 #define CRYPTO_V2_TR_CTL0_STOP_ON_AP_DETECT_Pos 28UL 293 #define CRYPTO_V2_TR_CTL0_STOP_ON_AP_DETECT_Msk 0x10000000UL 294 #define CRYPTO_V2_TR_CTL0_STOP_ON_RC_DETECT_Pos 29UL 295 #define CRYPTO_V2_TR_CTL0_STOP_ON_RC_DETECT_Msk 0x20000000UL 296 /* CRYPTO.TR_CTL1 */ 297 #define CRYPTO_V2_TR_CTL1_RO11_EN_Pos 0UL 298 #define CRYPTO_V2_TR_CTL1_RO11_EN_Msk 0x1UL 299 #define CRYPTO_V2_TR_CTL1_RO15_EN_Pos 1UL 300 #define CRYPTO_V2_TR_CTL1_RO15_EN_Msk 0x2UL 301 #define CRYPTO_V2_TR_CTL1_GARO15_EN_Pos 2UL 302 #define CRYPTO_V2_TR_CTL1_GARO15_EN_Msk 0x4UL 303 #define CRYPTO_V2_TR_CTL1_GARO31_EN_Pos 3UL 304 #define CRYPTO_V2_TR_CTL1_GARO31_EN_Msk 0x8UL 305 #define CRYPTO_V2_TR_CTL1_FIRO15_EN_Pos 4UL 306 #define CRYPTO_V2_TR_CTL1_FIRO15_EN_Msk 0x10UL 307 #define CRYPTO_V2_TR_CTL1_FIRO31_EN_Pos 5UL 308 #define CRYPTO_V2_TR_CTL1_FIRO31_EN_Msk 0x20UL 309 /* CRYPTO.TR_CTL2 */ 310 #define CRYPTO_V2_TR_CTL2_SIZE_Pos 0UL 311 #define CRYPTO_V2_TR_CTL2_SIZE_Msk 0x3FUL 312 /* CRYPTO.TR_STATUS */ 313 #define CRYPTO_V2_TR_STATUS_INITIALIZED_Pos 0UL 314 #define CRYPTO_V2_TR_STATUS_INITIALIZED_Msk 0x1UL 315 /* CRYPTO.TR_CMD */ 316 #define CRYPTO_V2_TR_CMD_START_Pos 0UL 317 #define CRYPTO_V2_TR_CMD_START_Msk 0x1UL 318 /* CRYPTO.TR_RESULT */ 319 #define CRYPTO_V2_TR_RESULT_DATA32_Pos 0UL 320 #define CRYPTO_V2_TR_RESULT_DATA32_Msk 0xFFFFFFFFUL 321 /* CRYPTO.TR_GARO_CTL */ 322 #define CRYPTO_V2_TR_GARO_CTL_POLYNOMIAL31_Pos 0UL 323 #define CRYPTO_V2_TR_GARO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL 324 /* CRYPTO.TR_FIRO_CTL */ 325 #define CRYPTO_V2_TR_FIRO_CTL_POLYNOMIAL31_Pos 0UL 326 #define CRYPTO_V2_TR_FIRO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL 327 /* CRYPTO.TR_MON_CTL */ 328 #define CRYPTO_V2_TR_MON_CTL_BITSTREAM_SEL_Pos 0UL 329 #define CRYPTO_V2_TR_MON_CTL_BITSTREAM_SEL_Msk 0x3UL 330 /* CRYPTO.TR_MON_CMD */ 331 #define CRYPTO_V2_TR_MON_CMD_START_AP_Pos 0UL 332 #define CRYPTO_V2_TR_MON_CMD_START_AP_Msk 0x1UL 333 #define CRYPTO_V2_TR_MON_CMD_START_RC_Pos 1UL 334 #define CRYPTO_V2_TR_MON_CMD_START_RC_Msk 0x2UL 335 /* CRYPTO.TR_MON_RC_CTL */ 336 #define CRYPTO_V2_TR_MON_RC_CTL_CUTOFF_COUNT8_Pos 0UL 337 #define CRYPTO_V2_TR_MON_RC_CTL_CUTOFF_COUNT8_Msk 0xFFUL 338 /* CRYPTO.TR_MON_RC_STATUS0 */ 339 #define CRYPTO_V2_TR_MON_RC_STATUS0_BIT_Pos 0UL 340 #define CRYPTO_V2_TR_MON_RC_STATUS0_BIT_Msk 0x1UL 341 /* CRYPTO.TR_MON_RC_STATUS1 */ 342 #define CRYPTO_V2_TR_MON_RC_STATUS1_REP_COUNT_Pos 0UL 343 #define CRYPTO_V2_TR_MON_RC_STATUS1_REP_COUNT_Msk 0xFFUL 344 /* CRYPTO.TR_MON_AP_CTL */ 345 #define CRYPTO_V2_TR_MON_AP_CTL_CUTOFF_COUNT16_Pos 0UL 346 #define CRYPTO_V2_TR_MON_AP_CTL_CUTOFF_COUNT16_Msk 0xFFFFUL 347 #define CRYPTO_V2_TR_MON_AP_CTL_WINDOW_SIZE_Pos 16UL 348 #define CRYPTO_V2_TR_MON_AP_CTL_WINDOW_SIZE_Msk 0xFFFF0000UL 349 /* CRYPTO.TR_MON_AP_STATUS0 */ 350 #define CRYPTO_V2_TR_MON_AP_STATUS0_BIT_Pos 0UL 351 #define CRYPTO_V2_TR_MON_AP_STATUS0_BIT_Msk 0x1UL 352 /* CRYPTO.TR_MON_AP_STATUS1 */ 353 #define CRYPTO_V2_TR_MON_AP_STATUS1_OCC_COUNT_Pos 0UL 354 #define CRYPTO_V2_TR_MON_AP_STATUS1_OCC_COUNT_Msk 0xFFFFUL 355 #define CRYPTO_V2_TR_MON_AP_STATUS1_WINDOW_INDEX_Pos 16UL 356 #define CRYPTO_V2_TR_MON_AP_STATUS1_WINDOW_INDEX_Msk 0xFFFF0000UL 357 /* CRYPTO.STATUS */ 358 #define CRYPTO_V2_STATUS_BUSY_Pos 31UL 359 #define CRYPTO_V2_STATUS_BUSY_Msk 0x80000000UL 360 /* CRYPTO.INSTR_FF_CTL */ 361 #define CRYPTO_V2_INSTR_FF_CTL_EVENT_LEVEL_Pos 0UL 362 #define CRYPTO_V2_INSTR_FF_CTL_EVENT_LEVEL_Msk 0x7UL 363 #define CRYPTO_V2_INSTR_FF_CTL_CLEAR_Pos 16UL 364 #define CRYPTO_V2_INSTR_FF_CTL_CLEAR_Msk 0x10000UL 365 #define CRYPTO_V2_INSTR_FF_CTL_BLOCK_Pos 17UL 366 #define CRYPTO_V2_INSTR_FF_CTL_BLOCK_Msk 0x20000UL 367 /* CRYPTO.INSTR_FF_STATUS */ 368 #define CRYPTO_V2_INSTR_FF_STATUS_USED_Pos 0UL 369 #define CRYPTO_V2_INSTR_FF_STATUS_USED_Msk 0xFUL 370 #define CRYPTO_V2_INSTR_FF_STATUS_EVENT_Pos 16UL 371 #define CRYPTO_V2_INSTR_FF_STATUS_EVENT_Msk 0x10000UL 372 /* CRYPTO.INSTR_FF_WR */ 373 #define CRYPTO_V2_INSTR_FF_WR_DATA32_Pos 0UL 374 #define CRYPTO_V2_INSTR_FF_WR_DATA32_Msk 0xFFFFFFFFUL 375 /* CRYPTO.LOAD0_FF_STATUS */ 376 #define CRYPTO_V2_LOAD0_FF_STATUS_USED5_Pos 0UL 377 #define CRYPTO_V2_LOAD0_FF_STATUS_USED5_Msk 0x1FUL 378 #define CRYPTO_V2_LOAD0_FF_STATUS_BUSY_Pos 31UL 379 #define CRYPTO_V2_LOAD0_FF_STATUS_BUSY_Msk 0x80000000UL 380 /* CRYPTO.LOAD1_FF_STATUS */ 381 #define CRYPTO_V2_LOAD1_FF_STATUS_USED5_Pos 0UL 382 #define CRYPTO_V2_LOAD1_FF_STATUS_USED5_Msk 0x1FUL 383 #define CRYPTO_V2_LOAD1_FF_STATUS_BUSY_Pos 31UL 384 #define CRYPTO_V2_LOAD1_FF_STATUS_BUSY_Msk 0x80000000UL 385 /* CRYPTO.STORE_FF_STATUS */ 386 #define CRYPTO_V2_STORE_FF_STATUS_USED5_Pos 0UL 387 #define CRYPTO_V2_STORE_FF_STATUS_USED5_Msk 0x1FUL 388 #define CRYPTO_V2_STORE_FF_STATUS_BUSY_Pos 31UL 389 #define CRYPTO_V2_STORE_FF_STATUS_BUSY_Msk 0x80000000UL 390 /* CRYPTO.AES_CTL */ 391 #define CRYPTO_V2_AES_CTL_KEY_SIZE_Pos 0UL 392 #define CRYPTO_V2_AES_CTL_KEY_SIZE_Msk 0x3UL 393 /* CRYPTO.RESULT */ 394 #define CRYPTO_V2_RESULT_DATA_Pos 0UL 395 #define CRYPTO_V2_RESULT_DATA_Msk 0xFFFFFFFFUL 396 /* CRYPTO.CRC_CTL */ 397 #define CRYPTO_V2_CRC_CTL_DATA_REVERSE_Pos 0UL 398 #define CRYPTO_V2_CRC_CTL_DATA_REVERSE_Msk 0x1UL 399 #define CRYPTO_V2_CRC_CTL_REM_REVERSE_Pos 8UL 400 #define CRYPTO_V2_CRC_CTL_REM_REVERSE_Msk 0x100UL 401 /* CRYPTO.CRC_DATA_CTL */ 402 #define CRYPTO_V2_CRC_DATA_CTL_DATA_XOR_Pos 0UL 403 #define CRYPTO_V2_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL 404 /* CRYPTO.CRC_POL_CTL */ 405 #define CRYPTO_V2_CRC_POL_CTL_POLYNOMIAL_Pos 0UL 406 #define CRYPTO_V2_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL 407 /* CRYPTO.CRC_REM_CTL */ 408 #define CRYPTO_V2_CRC_REM_CTL_REM_XOR_Pos 0UL 409 #define CRYPTO_V2_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL 410 /* CRYPTO.CRC_REM_RESULT */ 411 #define CRYPTO_V2_CRC_REM_RESULT_REM_Pos 0UL 412 #define CRYPTO_V2_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL 413 /* CRYPTO.VU_CTL0 */ 414 #define CRYPTO_V2_VU_CTL0_ALWAYS_EXECUTE_Pos 0UL 415 #define CRYPTO_V2_VU_CTL0_ALWAYS_EXECUTE_Msk 0x1UL 416 /* CRYPTO.VU_CTL1 */ 417 #define CRYPTO_V2_VU_CTL1_ADDR24_Pos 8UL 418 #define CRYPTO_V2_VU_CTL1_ADDR24_Msk 0xFFFFFF00UL 419 /* CRYPTO.VU_CTL2 */ 420 #define CRYPTO_V2_VU_CTL2_MASK_Pos 8UL 421 #define CRYPTO_V2_VU_CTL2_MASK_Msk 0x7F00UL 422 /* CRYPTO.VU_STATUS */ 423 #define CRYPTO_V2_VU_STATUS_CARRY_Pos 0UL 424 #define CRYPTO_V2_VU_STATUS_CARRY_Msk 0x1UL 425 #define CRYPTO_V2_VU_STATUS_EVEN_Pos 1UL 426 #define CRYPTO_V2_VU_STATUS_EVEN_Msk 0x2UL 427 #define CRYPTO_V2_VU_STATUS_ZERO_Pos 2UL 428 #define CRYPTO_V2_VU_STATUS_ZERO_Msk 0x4UL 429 #define CRYPTO_V2_VU_STATUS_ONE_Pos 3UL 430 #define CRYPTO_V2_VU_STATUS_ONE_Msk 0x8UL 431 /* CRYPTO.VU_RF_DATA */ 432 #define CRYPTO_V2_VU_RF_DATA_DATA32_Pos 0UL 433 #define CRYPTO_V2_VU_RF_DATA_DATA32_Msk 0xFFFFFFFFUL 434 /* CRYPTO.DEV_KEY_ADDR0_CTL */ 435 #define CRYPTO_V2_DEV_KEY_ADDR0_CTL_VALID_Pos 31UL 436 #define CRYPTO_V2_DEV_KEY_ADDR0_CTL_VALID_Msk 0x80000000UL 437 /* CRYPTO.DEV_KEY_ADDR0 */ 438 #define CRYPTO_V2_DEV_KEY_ADDR0_ADDR32_Pos 0UL 439 #define CRYPTO_V2_DEV_KEY_ADDR0_ADDR32_Msk 0xFFFFFFFFUL 440 /* CRYPTO.DEV_KEY_ADDR1_CTL */ 441 #define CRYPTO_V2_DEV_KEY_ADDR1_CTL_VALID_Pos 31UL 442 #define CRYPTO_V2_DEV_KEY_ADDR1_CTL_VALID_Msk 0x80000000UL 443 /* CRYPTO.DEV_KEY_ADDR1 */ 444 #define CRYPTO_V2_DEV_KEY_ADDR1_ADDR32_Pos 0UL 445 #define CRYPTO_V2_DEV_KEY_ADDR1_ADDR32_Msk 0xFFFFFFFFUL 446 /* CRYPTO.DEV_KEY_STATUS */ 447 #define CRYPTO_V2_DEV_KEY_STATUS_LOADED_Pos 0UL 448 #define CRYPTO_V2_DEV_KEY_STATUS_LOADED_Msk 0x1UL 449 /* CRYPTO.DEV_KEY_CTL0 */ 450 #define CRYPTO_V2_DEV_KEY_CTL0_ALLOWED_Pos 0UL 451 #define CRYPTO_V2_DEV_KEY_CTL0_ALLOWED_Msk 0x1UL 452 /* CRYPTO.DEV_KEY_CTL1 */ 453 #define CRYPTO_V2_DEV_KEY_CTL1_ALLOWED_Pos 0UL 454 #define CRYPTO_V2_DEV_KEY_CTL1_ALLOWED_Msk 0x1UL 455 /* CRYPTO.MEM_BUFF */ 456 #define CRYPTO_V2_MEM_BUFF_DATA32_Pos 0UL 457 #define CRYPTO_V2_MEM_BUFF_DATA32_Msk 0xFFFFFFFFUL 458 459 460 #endif /* _CYIP_CRYPTO_V2_H_ */ 461 462 463 /* [] END OF FILE */ 464
