1 /**************************************************************************//** 2 * @file epwm_reg.h 3 * @version V1.00 4 * @brief EPWM register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EPWM_REG_H__ 10 #define __EPWM_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup EPWM Pulse Width Modulation Controller(EPWM) 23 Memory Mapped Structure for EPWM Controller 24 @{ */ 25 26 typedef struct 27 { 28 /** 29 * @var ECAPDAT_T::RCAPDAT 30 * Offset: 0x20C EPWM Rising Capture Data Register 0~5 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only) 35 * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. 36 * @var ECAPDAT_T::FCAPDAT 37 * Offset: 0x210 EPWM Falling Capture Data Register 0~5 38 * --------------------------------------------------------------------------------------------------- 39 * |Bits |Field |Descriptions 40 * | :----: | :----: | :---- | 41 * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only) 42 * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. 43 */ 44 __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */ 45 __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */ 46 } ECAPDAT_T; 47 48 typedef struct 49 { 50 51 52 /** 53 * @var EPWM_T::CTL0 54 * Offset: 0x00 EPWM Control Register 0 55 * --------------------------------------------------------------------------------------------------- 56 * |Bits |Field |Descriptions 57 * | :----: | :----: | :---- | 58 * |[0] |CTRLD0 |Center Re-load 59 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 60 * | | |CMPDAT will load to CMPBUF at the center point of a period 61 * |[1] |CTRLD1 |Center Re-load 62 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 63 * | | |CMPDAT will load to CMPBUF at the center point of a period 64 * |[2] |CTRLD2 |Center Re-load 65 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 66 * | | |CMPDAT will load to CMPBUF at the center point of a period 67 * |[3] |CTRLD3 |Center Re-load 68 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 69 * | | |CMPDAT will load to CMPBUF at the center point of a period 70 * |[4] |CTRLD4 |Center Re-load 71 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 72 * | | |CMPDAT will load to CMPBUF at the center point of a period 73 * |[5] |CTRLD5 |Center Re-load 74 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 75 * | | |CMPDAT will load to CMPBUF at the center point of a period 76 * |[8] |WINLDEN0 |Window Load Enable Bits 77 * | | |0 = PERIOD will load to PBUF at the end point of each period 78 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 79 * | | |1 = PERIOD will load to PBUF at the end point of each period 80 * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set 81 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 82 * |[9] |WINLDEN1 |Window Load Enable Bits 83 * | | |0 = PERIOD will load to PBUF at the end point of each period 84 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 85 * | | |1 = PERIOD will load to PBUF at the end point of each period 86 * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set 87 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 88 * |[10] |WINLDEN2 |Window Load Enable Bits 89 * | | |0 = PERIOD will load to PBUF at the end point of each period 90 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 91 * | | |1 = PERIOD will load to PBUF at the end point of each period 92 * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set 93 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 94 * |[11] |WINLDEN3 |Window Load Enable Bits 95 * | | |0 = PERIOD will load to PBUF at the end point of each period 96 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 97 * | | |1 = PERIOD will load to PBUF at the end point of each period 98 * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set 99 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 100 * |[12] |WINLDEN4 |Window Load Enable Bits 101 * | | |0 = PERIOD will load to PBUF at the end point of each period 102 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 103 * | | |1 = PERIOD will load to PBUF at the end point of each period 104 * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set 105 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 106 * |[13] |WINLDEN5 |Window Load Enable Bits 107 * | | |0 = PERIOD will load to PBUF at the end point of each period 108 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 109 * | | |1 = PERIOD will load to PBUF at the end point of each period 110 * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set 111 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 112 * |[16] |IMMLDEN0 |Immediately Load Enable Bits 113 * | | |0 = PERIOD will load to PBUF at the end point of each period 114 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 115 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 116 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 117 * |[17] |IMMLDEN1 |Immediately Load Enable Bits 118 * | | |0 = PERIOD will load to PBUF at the end point of each period 119 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 120 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 121 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 122 * |[18] |IMMLDEN2 |Immediately Load Enable Bits 123 * | | |0 = PERIOD will load to PBUF at the end point of each period 124 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 125 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 126 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 127 * |[19] |IMMLDEN3 |Immediately Load Enable Bits 128 * | | |0 = PERIOD will load to PBUF at the end point of each period 129 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 130 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 131 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 132 * |[20] |IMMLDEN4 |Immediately Load Enable Bits 133 * | | |0 = PERIOD will load to PBUF at the end point of each period 134 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 135 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 136 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 137 * |[21] |IMMLDEN5 |Immediately Load Enable Bits 138 * | | |0 = PERIOD will load to PBUF at the end point of each period 139 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 140 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 141 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 142 * |[24] |GROUPEN |Group Function Enable Bit(S) 143 * | | |0 = The output waveform of each EPWM channel are independent. 144 * | | |1 = Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1. 145 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) 146 * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. 147 * | | |0 = ICE debug mode counter halt disable. 148 * | | |1 = ICE debug mode counter halt enable. 149 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 150 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) 151 * | | |0 = ICE debug mode acknowledgement effects EPWM output. 152 * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged. 153 * | | |1 = ICE debug mode acknowledgement disabled. 154 * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not. 155 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 156 * @var EPWM_T::CTL1 157 * Offset: 0x04 EPWM Control Register 1 158 * --------------------------------------------------------------------------------------------------- 159 * |Bits |Field |Descriptions 160 * | :----: | :----: | :---- | 161 * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type 162 * | | |00 = Up counter type (supports in capture mode). 163 * | | |01 = Down count type (supports in capture mode). 164 * | | |10 = Up-down counter type. 165 * | | |11 = Reserved. 166 * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type 167 * | | |00 = Up counter type (supports in capture mode). 168 * | | |01 = Down count type (supports in capture mode). 169 * | | |10 = Up-down counter type. 170 * | | |11 = Reserved. 171 * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type 172 * | | |00 = Up counter type (supports in capture mode). 173 * | | |01 = Down count type (supports in capture mode). 174 * | | |10 = Up-down counter type. 175 * | | |11 = Reserved. 176 * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type 177 * | | |00 = Up counter type (supports in capture mode). 178 * | | |01 = Down count type (supports in capture mode). 179 * | | |10 = Up-down counter type. 180 * | | |11 = Reserved. 181 * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type 182 * | | |00 = Up counter type (supports in capture mode). 183 * | | |01 = Down count type (supports in capture mode). 184 * | | |10 = Up-down counter type. 185 * | | |11 = Reserved. 186 * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type 187 * | | |00 = Up counter type (supports in capture mode). 188 * | | |01 = Down count type (supports in capture mode). 189 * | | |10 = Up-down counter type. 190 * | | |11 = Reserved. 191 * |[16] |CNTMODE0 |EPWM Counter Mode 192 * | | |0 = Auto-reload mode. 193 * | | |1 = One-shot mode. 194 * |[17] |CNTMODE1 |EPWM Counter Mode 195 * | | |0 = Auto-reload mode. 196 * | | |1 = One-shot mode. 197 * |[18] |CNTMODE2 |EPWM Counter Mode 198 * | | |0 = Auto-reload mode. 199 * | | |1 = One-shot mode. 200 * |[19] |CNTMODE3 |EPWM Counter Mode 201 * | | |0 = Auto-reload mode. 202 * | | |1 = One-shot mode. 203 * |[20] |CNTMODE4 |EPWM Counter Mode 204 * | | |0 = Auto-reload mode. 205 * | | |1 = One-shot mode. 206 * |[21] |CNTMODE5 |EPWM Counter Mode 207 * | | |0 = Auto-reload mode. 208 * | | |1 = One-shot mode. 209 * |[24] |OUTMODE0 |EPWM Output Mode 210 * | | |Each bit n controls the output mode of corresponding EPWM channel n. 211 * | | |0 = EPWM independent mode. 212 * | | |1 = EPWM complementary mode. 213 * | | |Note: When operating in group function, these bits must all set to the same mode. 214 * |[25] |OUTMODE2 |EPWM Output Mode 215 * | | |Each bit n controls the output mode of corresponding EPWM channel n. 216 * | | |0 = EPWM independent mode. 217 * | | |1 = EPWM complementary mode. 218 * | | |Note: When operating in group function, these bits must all set to the same mode. 219 * |[26] |OUTMODE4 |EPWM Output Mode 220 * | | |Each bit n controls the output mode of corresponding EPWM channel n. 221 * | | |0 = EPWM independent mode. 222 * | | |1 = EPWM complementary mode. 223 * | | |Note: When operating in group function, these bits must all set to the same mode. 224 * @var EPWM_T::SYNC 225 * Offset: 0x08 EPWM Synchronization Register 226 * --------------------------------------------------------------------------------------------------- 227 * |Bits |Field |Descriptions 228 * | :----: | :----: | :---- | 229 * |[0] |PHSEN0 |SYNC Phase Enable Bits 230 * | | |0 = EPWM counter disable to load PHS value. 231 * | | |1 = EPWM counter enable to load PHS value. 232 * |[1] |PHSEN2 |SYNC Phase Enable Bits 233 * | | |0 = EPWM counter disable to load PHS value. 234 * | | |1 = EPWM counter enable to load PHS value. 235 * |[2] |PHSEN4 |SYNC Phase Enable Bits 236 * | | |0 = EPWM counter disable to load PHS value. 237 * | | |1 = EPWM counter enable to load PHS value. 238 * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection 239 * | | |00 = Synchronize source from SYNC_IN or SWSYNC. 240 * | | |01 = Counter equal to 0. 241 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. 242 * | | |11 = SYNC_OUT will not be generated. 243 * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection 244 * | | |00 = Synchronize source from SYNC_IN or SWSYNC. 245 * | | |01 = Counter equal to 0. 246 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. 247 * | | |11 = SYNC_OUT will not be generated. 248 * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection 249 * | | |00 = Synchronize source from SYNC_IN or SWSYNC. 250 * | | |01 = Counter equal to 0. 251 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. 252 * | | |11 = SYNC_OUT will not be generated. 253 * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits 254 * | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled. 255 * | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled. 256 * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection 257 * | | |000 = Filter clock = HCLK. 258 * | | |001 = Filter clock = HCLK/2. 259 * | | |010 = Filter clock = HCLK/4. 260 * | | |011 = Filter clock = HCLK/8. 261 * | | |100 = Filter clock = HCLK/16. 262 * | | |101 = Filter clock = HCLK/32. 263 * | | |110 = Filter clock = HCLK/64. 264 * | | |111 = Filter clock = HCLK/128. 265 * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count 266 * | | |The register bits control the counter number of edge detector. 267 * |[23] |SINPINV |SYNC Input Pin Inverse 268 * | | |0 = The state of pin SYNC is passed to the negative edge detector. 269 * | | |1 = The inversed state of pin SYNC is passed to the negative edge detector. 270 * |[24] |PHSDIR0 |EPWM Phase Direction Control 271 * | | |0 = Control EPWM counter count decrement after synchronizing. 272 * | | |1 = Control EPWM counter count increment after synchronizing. 273 * |[25] |PHSDIR2 |EPWM Phase Direction Control 274 * | | |0 = Control EPWM counter count decrement after synchronizing. 275 * | | |1 = Control EPWM counter count increment after synchronizing. 276 * |[26] |PHSDIR4 |EPWM Phase Direction Control 277 * | | |0 = Control EPWM counter count decrement after synchronizing. 278 * | | |1 = Control EPWM counter count increment after synchronizing. 279 * @var EPWM_T::SWSYNC 280 * Offset: 0x0C EPWM Software Control Synchronization Register 281 * --------------------------------------------------------------------------------------------------- 282 * |Bits |Field |Descriptions 283 * | :----: | :----: | :---- | 284 * |[0] |SWSYNC0 |Software SYNC Function 285 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 286 * |[1] |SWSYNC2 |Software SYNC Function 287 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 288 * |[2] |SWSYNC4 |Software SYNC Function 289 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 290 * @var EPWM_T::CLKSRC 291 * Offset: 0x10 EPWM Clock Source Register 292 * --------------------------------------------------------------------------------------------------- 293 * |Bits |Field |Descriptions 294 * | :----: | :----: | :---- | 295 * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select 296 * | | |000 = EPWMx_CLK, x denotes 0 or 1. 297 * | | |001 = TIMER0 overflow. 298 * | | |010 = TIMER1 overflow. 299 * | | |011 = TIMER2 overflow. 300 * | | |100 = TIMER3 overflow. 301 * | | |Others = Reserved. 302 * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select 303 * | | |000 = EPWMx_CLK, x denotes 0 or 1. 304 * | | |001 = TIMER0 overflow. 305 * | | |010 = TIMER1 overflow. 306 * | | |011 = TIMER2 overflow. 307 * | | |100 = TIMER3 overflow. 308 * | | |Others = Reserved. 309 * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select 310 * | | |000 = EPWMx_CLK, x denotes 0 or 1. 311 * | | |001 = TIMER0 overflow. 312 * | | |010 = TIMER1 overflow. 313 * | | |011 = TIMER2 overflow. 314 * | | |100 = TIMER3 overflow. 315 * | | |Others = Reserved. 316 * @var EPWM_T::CLKPSC[3] 317 * Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5 318 * --------------------------------------------------------------------------------------------------- 319 * |Bits |Field |Descriptions 320 * | :----: | :----: | :---- | 321 * |[11:0] |CLKPSC |EPWM Counter Clock Prescale 322 * | | |The clock of EPWM counter is decided by clock prescaler 323 * | | |Each EPWM pair share one EPWM counter clock prescaler 324 * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) 325 * @var EPWM_T::CNTEN 326 * Offset: 0x20 EPWM Counter Enable Register 327 * --------------------------------------------------------------------------------------------------- 328 * |Bits |Field |Descriptions 329 * | :----: | :----: | :---- | 330 * |[0] |CNTEN0 |EPWM Counter Enable Bits 331 * | | |0 = EPWM Counter and clock prescaler Stop Running. 332 * | | |1 = EPWM Counter and clock prescaler Start Running. 333 * |[1] |CNTEN1 |EPWM Counter Enable Bits 334 * | | |0 = EPWM Counter and clock prescaler Stop Running. 335 * | | |1 = EPWM Counter and clock prescaler Start Running. 336 * |[2] |CNTEN2 |EPWM Counter Enable Bits 337 * | | |0 = EPWM Counter and clock prescaler Stop Running. 338 * | | |1 = EPWM Counter and clock prescaler Start Running. 339 * |[3] |CNTEN3 |EPWM Counter Enable Bits 340 * | | |0 = EPWM Counter and clock prescaler Stop Running. 341 * | | |1 = EPWM Counter and clock prescaler Start Running. 342 * |[4] |CNTEN4 |EPWM Counter Enable Bits 343 * | | |0 = EPWM Counter and clock prescaler Stop Running. 344 * | | |1 = EPWM Counter and clock prescaler Start Running. 345 * |[5] |CNTEN5 |EPWM Counter Enable Bits 346 * | | |0 = EPWM Counter and clock prescaler Stop Running. 347 * | | |1 = EPWM Counter and clock prescaler Start Running. 348 * @var EPWM_T::CNTCLR 349 * Offset: 0x24 EPWM Clear Counter Register 350 * --------------------------------------------------------------------------------------------------- 351 * |Bits |Field |Descriptions 352 * | :----: | :----: | :---- | 353 * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit 354 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 355 * | | |0 = No effect. 356 * | | |1 = Clear 16-bit EPWM counter to 0000H. 357 * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit 358 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 359 * | | |0 = No effect. 360 * | | |1 = Clear 16-bit EPWM counter to 0000H. 361 * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit 362 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 363 * | | |0 = No effect. 364 * | | |1 = Clear 16-bit EPWM counter to 0000H. 365 * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit 366 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 367 * | | |0 = No effect. 368 * | | |1 = Clear 16-bit EPWM counter to 0000H. 369 * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit 370 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 371 * | | |0 = No effect. 372 * | | |1 = Clear 16-bit EPWM counter to 0000H. 373 * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit 374 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 375 * | | |0 = No effect. 376 * | | |1 = Clear 16-bit EPWM counter to 0000H. 377 * @var EPWM_T::LOAD 378 * Offset: 0x28 EPWM Load Register 379 * --------------------------------------------------------------------------------------------------- 380 * |Bits |Field |Descriptions 381 * | :----: | :----: | :---- | 382 * |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 383 * | | |This bit is software write, hardware clear when current EPWM period end. 384 * | | |Write Operation: 385 * | | |0 = No effect. 386 * | | |1 = Set load window of window loading mode. 387 * | | |Read Operation: 388 * | | |0 = No load window is set. 389 * | | |1 = Load window is set. 390 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 391 * |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 392 * | | |This bit is software write, hardware clear when current EPWM period end. 393 * | | |Write Operation: 394 * | | |0 = No effect. 395 * | | |1 = Set load window of window loading mode. 396 * | | |Read Operation: 397 * | | |0 = No load window is set. 398 * | | |1 = Load window is set. 399 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 400 * |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 401 * | | |This bit is software write, hardware clear when current EPWM period end. 402 * | | |Write Operation: 403 * | | |0 = No effect. 404 * | | |1 = Set load window of window loading mode. 405 * | | |Read Operation: 406 * | | |0 = No load window is set. 407 * | | |1 = Load window is set. 408 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 409 * |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 410 * | | |This bit is software write, hardware clear when current EPWM period end. 411 * | | |Write Operation: 412 * | | |0 = No effect. 413 * | | |1 = Set load window of window loading mode. 414 * | | |Read Operation: 415 * | | |0 = No load window is set. 416 * | | |1 = Load window is set. 417 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 418 * |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 419 * | | |This bit is software write, hardware clear when current EPWM period end. 420 * | | |Write Operation: 421 * | | |0 = No effect. 422 * | | |1 = Set load window of window loading mode. 423 * | | |Read Operation: 424 * | | |0 = No load window is set. 425 * | | |1 = Load window is set. 426 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 427 * |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 428 * | | |This bit is software write, hardware clear when current EPWM period end. 429 * | | |Write Operation: 430 * | | |0 = No effect. 431 * | | |1 = Set load window of window loading mode. 432 * | | |Read Operation: 433 * | | |0 = No load window is set. 434 * | | |1 = Load window is set. 435 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 436 * @var EPWM_T::PERIOD[6] 437 * Offset: 0x30 EPWM Period Register 0~5 438 * --------------------------------------------------------------------------------------------------- 439 * |Bits |Field |Descriptions 440 * | :----: | :----: | :---- | 441 * |[15:0] |PERIOD |EPWM Period Register 442 * | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. 443 * | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. 444 * | | |EPWM period time = (PERIOD+1) * EPWM_CLK period. 445 * | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. 446 * | | |EPWM period time = 2 * PERIOD * EPWM_CLK period. 447 * @var EPWM_T::CMPDAT[6] 448 * Offset: 0x50 EPWM Comparator Register 0 449 * --------------------------------------------------------------------------------------------------- 450 * |Bits |Field |Descriptions 451 * | :----: | :----: | :---- | 452 * |[15:0] |CMP |EPWM Comparator Register 453 * | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC. 454 * | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point. 455 * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. 456 * @var EPWM_T::DTCTL[3] 457 * Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5 458 * --------------------------------------------------------------------------------------------------- 459 * |Bits |Field |Descriptions 460 * | :----: | :----: | :---- | 461 * |[11:0] |DTCNT |Dead-time Counter (Write Protect) 462 * | | |The dead-time can be calculated from the following formula: 463 * | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period. 464 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 465 * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect) 466 * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled 467 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 468 * | | |0 = Dead-time insertion Disabled on the pin pair. 469 * | | |1 = Dead-time insertion Enabled on the pin pair. 470 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 471 * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) 472 * | | |0 = Dead-time clock source from EPWM_CLK. 473 * | | |1 = Dead-time clock source from prescaler output. 474 * | | |Note: This register is write protected. Refer toREGWRPROT register. 475 * @var EPWM_T::PHS[3] 476 * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5 477 * --------------------------------------------------------------------------------------------------- 478 * |Bits |Field |Descriptions 479 * | :----: | :----: | :---- | 480 * |[15:0] |PHS |EPWM Synchronous Start Phase Bits 481 * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. 482 * @var EPWM_T::CNT[6] 483 * Offset: 0x90 EPWM Counter Register 0~5 484 * --------------------------------------------------------------------------------------------------- 485 * |Bits |Field |Descriptions 486 * | :----: | :----: | :---- | 487 * |[15:0] |CNT |EPWM Data Register (Read Only) 488 * | | |User can monitor CNTR to know the current value in 16-bit period counter. 489 * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) 490 * | | |0 = Counter is Down count. 491 * | | |1 = Counter is UP count. 492 * @var EPWM_T::WGCTL0 493 * Offset: 0xB0 EPWM Generation Register 0 494 * --------------------------------------------------------------------------------------------------- 495 * |Bits |Field |Descriptions 496 * | :----: | :----: | :---- | 497 * |[1:0] |ZPCTL0 |EPWM Zero Point Control 498 * | | |00 = Do nothing. 499 * | | |01 = EPWM zero point output Low. 500 * | | |10 = EPWM zero point output High. 501 * | | |11 = EPWM zero point output Toggle. 502 * | | |EPWM can control output level when EPWM counter count to zero. 503 * |[3:2] |ZPCTL1 |EPWM Zero Point Control 504 * | | |00 = Do nothing. 505 * | | |01 = EPWM zero point output Low. 506 * | | |10 = EPWM zero point output High. 507 * | | |11 = EPWM zero point output Toggle. 508 * | | |EPWM can control output level when EPWM counter count to zero. 509 * |[5:4] |ZPCTL2 |EPWM Zero Point Control 510 * | | |00 = Do nothing. 511 * | | |01 = EPWM zero point output Low. 512 * | | |10 = EPWM zero point output High. 513 * | | |11 = EPWM zero point output Toggle. 514 * | | |EPWM can control output level when EPWM counter count to zero. 515 * |[7:6] |ZPCTL3 |EPWM Zero Point Control 516 * | | |00 = Do nothing. 517 * | | |01 = EPWM zero point output Low. 518 * | | |10 = EPWM zero point output High. 519 * | | |11 = EPWM zero point output Toggle. 520 * | | |EPWM can control output level when EPWM counter count to zero. 521 * |[9:8] |ZPCTL4 |EPWM Zero Point Control 522 * | | |00 = Do nothing. 523 * | | |01 = EPWM zero point output Low. 524 * | | |10 = EPWM zero point output High. 525 * | | |11 = EPWM zero point output Toggle. 526 * | | |EPWM can control output level when EPWM counter count to zero. 527 * |[11:10] |ZPCTL5 |EPWM Zero Point Control 528 * | | |00 = Do nothing. 529 * | | |01 = EPWM zero point output Low. 530 * | | |10 = EPWM zero point output High. 531 * | | |11 = EPWM zero point output Toggle. 532 * | | |EPWM can control output level when EPWM counter count to zero. 533 * |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control 534 * | | |00 = Do nothing. 535 * | | |01 = EPWM period (center) point output Low. 536 * | | |10 = EPWM period (center) point output High. 537 * | | |11 = EPWM period (center) point output Toggle. 538 * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). 539 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 540 * |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control 541 * | | |00 = Do nothing. 542 * | | |01 = EPWM period (center) point output Low. 543 * | | |10 = EPWM period (center) point output High. 544 * | | |11 = EPWM period (center) point output Toggle. 545 * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). 546 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 547 * |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control 548 * | | |00 = Do nothing. 549 * | | |01 = EPWM period (center) point output Low. 550 * | | |10 = EPWM period (center) point output High. 551 * | | |11 = EPWM period (center) point output Toggle. 552 * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). 553 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 554 * |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control 555 * | | |00 = Do nothing. 556 * | | |01 = EPWM period (center) point output Low. 557 * | | |10 = EPWM period (center) point output High. 558 * | | |11 = EPWM period (center) point output Toggle. 559 * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). 560 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 561 * |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control 562 * | | |00 = Do nothing. 563 * | | |01 = EPWM period (center) point output Low. 564 * | | |10 = EPWM period (center) point output High. 565 * | | |11 = EPWM period (center) point output Toggle. 566 * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). 567 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 568 * |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control 569 * | | |00 = Do nothing. 570 * | | |01 = EPWM period (center) point output Low. 571 * | | |10 = EPWM period (center) point output High. 572 * | | |11 = EPWM period (center) point output Toggle. 573 * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). 574 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 575 * @var EPWM_T::WGCTL1 576 * Offset: 0xB4 EPWM Generation Register 1 577 * --------------------------------------------------------------------------------------------------- 578 * |Bits |Field |Descriptions 579 * | :----: | :----: | :---- | 580 * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control 581 * | | |00 = Do nothing. 582 * | | |01 = EPWM compare up point output Low. 583 * | | |10 = EPWM compare up point output High. 584 * | | |11 = EPWM compare up point output Toggle. 585 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 586 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 587 * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control 588 * | | |00 = Do nothing. 589 * | | |01 = EPWM compare up point output Low. 590 * | | |10 = EPWM compare up point output High. 591 * | | |11 = EPWM compare up point output Toggle. 592 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 593 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 594 * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control 595 * | | |00 = Do nothing. 596 * | | |01 = EPWM compare up point output Low. 597 * | | |10 = EPWM compare up point output High. 598 * | | |11 = EPWM compare up point output Toggle. 599 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 600 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 601 * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control 602 * | | |00 = Do nothing. 603 * | | |01 = EPWM compare up point output Low. 604 * | | |10 = EPWM compare up point output High. 605 * | | |11 = EPWM compare up point output Toggle. 606 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 607 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 608 * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control 609 * | | |00 = Do nothing. 610 * | | |01 = EPWM compare up point output Low. 611 * | | |10 = EPWM compare up point output High. 612 * | | |11 = EPWM compare up point output Toggle. 613 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 614 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 615 * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control 616 * | | |00 = Do nothing. 617 * | | |01 = EPWM compare up point output Low. 618 * | | |10 = EPWM compare up point output High. 619 * | | |11 = EPWM compare up point output Toggle. 620 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 621 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 622 * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control 623 * | | |00 = Do nothing. 624 * | | |01 = EPWM compare down point output Low. 625 * | | |10 = EPWM compare down point output High. 626 * | | |11 = EPWM compare down point output Toggle. 627 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 628 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 629 * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control 630 * | | |00 = Do nothing. 631 * | | |01 = EPWM compare down point output Low. 632 * | | |10 = EPWM compare down point output High. 633 * | | |11 = EPWM compare down point output Toggle. 634 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 635 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 636 * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control 637 * | | |00 = Do nothing. 638 * | | |01 = EPWM compare down point output Low. 639 * | | |10 = EPWM compare down point output High. 640 * | | |11 = EPWM compare down point output Toggle. 641 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 642 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 643 * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control 644 * | | |00 = Do nothing. 645 * | | |01 = EPWM compare down point output Low. 646 * | | |10 = EPWM compare down point output High. 647 * | | |11 = EPWM compare down point output Toggle. 648 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 649 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 650 * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control 651 * | | |00 = Do nothing. 652 * | | |01 = EPWM compare down point output Low. 653 * | | |10 = EPWM compare down point output High. 654 * | | |11 = EPWM compare down point output Toggle. 655 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 656 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 657 * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control 658 * | | |00 = Do nothing. 659 * | | |01 = EPWM compare down point output Low. 660 * | | |10 = EPWM compare down point output High. 661 * | | |11 = EPWM compare down point output Toggle. 662 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 663 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 664 * @var EPWM_T::MSKEN 665 * Offset: 0xB8 EPWM Mask Enable Register 666 * --------------------------------------------------------------------------------------------------- 667 * |Bits |Field |Descriptions 668 * | :----: | :----: | :---- | 669 * |[0] |MSKEN0 |EPWM Mask Enable Bits 670 * | | |The EPWM output signal will be masked when this bit is enabled 671 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 672 * | | |0 = EPWM output signal is non-masked. 673 * | | |1 = EPWM output signal is masked and output MSKDATn data. 674 * |[1] |MSKEN1 |EPWM Mask Enable Bits 675 * | | |The EPWM output signal will be masked when this bit is enabled 676 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 677 * | | |0 = EPWM output signal is non-masked. 678 * | | |1 = EPWM output signal is masked and output MSKDATn data. 679 * |[2] |MSKEN2 |EPWM Mask Enable Bits 680 * | | |The EPWM output signal will be masked when this bit is enabled 681 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 682 * | | |0 = EPWM output signal is non-masked. 683 * | | |1 = EPWM output signal is masked and output MSKDATn data. 684 * |[3] |MSKEN3 |EPWM Mask Enable Bits 685 * | | |The EPWM output signal will be masked when this bit is enabled 686 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 687 * | | |0 = EPWM output signal is non-masked. 688 * | | |1 = EPWM output signal is masked and output MSKDATn data. 689 * |[4] |MSKEN4 |EPWM Mask Enable Bits 690 * | | |The EPWM output signal will be masked when this bit is enabled 691 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 692 * | | |0 = EPWM output signal is non-masked. 693 * | | |1 = EPWM output signal is masked and output MSKDATn data. 694 * |[5] |MSKEN5 |EPWM Mask Enable Bits 695 * | | |The EPWM output signal will be masked when this bit is enabled 696 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 697 * | | |0 = EPWM output signal is non-masked. 698 * | | |1 = EPWM output signal is masked and output MSKDATn data. 699 * @var EPWM_T::MSK 700 * Offset: 0xBC EPWM Mask Data Register 701 * --------------------------------------------------------------------------------------------------- 702 * |Bits |Field |Descriptions 703 * | :----: | :----: | :---- | 704 * |[0] |MSKDAT0 |EPWM Mask Data Bit 705 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 706 * | | |0 = Output logic low to EPWM channel n. 707 * | | |1 = Output logic high to EPWM channel n. 708 * |[1] |MSKDAT1 |EPWM Mask Data Bit 709 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 710 * | | |0 = Output logic low to EPWM channel n. 711 * | | |1 = Output logic high to EPWM channel n. 712 * |[2] |MSKDAT2 |EPWM Mask Data Bit 713 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 714 * | | |0 = Output logic low to EPWM channel n. 715 * | | |1 = Output logic high to EPWM channel n. 716 * |[3] |MSKDAT3 |EPWM Mask Data Bit 717 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 718 * | | |0 = Output logic low to EPWM channel n. 719 * | | |1 = Output logic high to EPWM channel n. 720 * |[4] |MSKDAT4 |EPWM Mask Data Bit 721 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 722 * | | |0 = Output logic low to EPWM channel n. 723 * | | |1 = Output logic high to EPWM channel n. 724 * |[5] |MSKDAT5 |EPWM Mask Data Bit 725 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 726 * | | |0 = Output logic low to EPWM channel n. 727 * | | |1 = Output logic high to EPWM channel n. 728 * @var EPWM_T::BNF 729 * Offset: 0xC0 EPWM Brake Noise Filter Register 730 * --------------------------------------------------------------------------------------------------- 731 * |Bits |Field |Descriptions 732 * | :----: | :----: | :---- | 733 * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit 734 * | | |0 = Noise filter of EPWM Brake 0 Disabled. 735 * | | |1 = Noise filter of EPWM Brake 0 Enabled. 736 * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection 737 * | | |000 = Filter clock = HCLK. 738 * | | |001 = Filter clock = HCLK/2. 739 * | | |010 = Filter clock = HCLK/4. 740 * | | |011 = Filter clock = HCLK/8. 741 * | | |100 = Filter clock = HCLK/16. 742 * | | |101 = Filter clock = HCLK/32. 743 * | | |110 = Filter clock = HCLK/64. 744 * | | |111 = Filter clock = HCLK/128. 745 * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count 746 * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 747 * |[7] |BRK0PINV |Brake 0 Pin Inverse 748 * | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector. 749 * | | |1 = The inversed state of pin EPWMx_BRAKE10 is passed to the negative edge detector. 750 * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit 751 * | | |0 = Noise filter of EPWM Brake 1 Disabled. 752 * | | |1 = Noise filter of EPWM Brake 1 Enabled. 753 * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection 754 * | | |000 = Filter clock = HCLK. 755 * | | |001 = Filter clock = HCLK/2. 756 * | | |010 = Filter clock = HCLK/4. 757 * | | |011 = Filter clock = HCLK/8. 758 * | | |100 = Filter clock = HCLK/16. 759 * | | |101 = Filter clock = HCLK/32. 760 * | | |110 = Filter clock = HCLK/64. 761 * | | |111 = Filter clock = HCLK/128. 762 * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count 763 * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 764 * |[15] |BRK1PINV |Brake 1 Pin Inverse 765 * | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector. 766 * | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector. 767 * |[16] |BK0SRC |Brake 0 Pin Source Select 768 * | | |For EPWM0 setting: 769 * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0. 770 * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0. 771 * | | |For EPWM1 setting: 772 * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0. 773 * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. 774 * |[24] |BK1SRC |Brake 1 Pin Source Select 775 * | | |For EPWM0 setting: 776 * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1. 777 * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1. 778 * | | |For EPWM1 setting: 779 * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1. 780 * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. 781 * @var EPWM_T::FAILBRK 782 * Offset: 0xC4 EPWM System Fail Brake Control Register 783 * --------------------------------------------------------------------------------------------------- 784 * |Bits |Field |Descriptions 785 * | :----: | :----: | :---- | 786 * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit 787 * | | |0 = Brake Function triggered by CSS detection Disabled. 788 * | | |1 = Brake Function triggered by CSS detection Enabled. 789 * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit 790 * | | |0 = Brake Function triggered by BOD Disabled. 791 * | | |1 = Brake Function triggered by BOD Enabled. 792 * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit 793 * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. 794 * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. 795 * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit 796 * | | |0 = Brake Function triggered by Core lockup detection Disabled. 797 * | | |1 = Brake Function triggered by Core lockup detection Enabled. 798 * @var EPWM_T::BRKCTL[3] 799 * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 800 * --------------------------------------------------------------------------------------------------- 801 * |Bits |Field |Descriptions 802 * | :----: | :----: | :---- | 803 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) 804 * | | |0 = ACMP0_O as edge-detect brake source Disabled. 805 * | | |1 = ACMP0_O as edge-detect brake source Enabled. 806 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 807 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) 808 * | | |0 = ACMP1_O as edge-detect brake source Disabled. 809 * | | |1 = ACMP1_O as edge-detect brake source Enabled. 810 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 811 * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) 812 * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. 813 * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. 814 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 815 * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) 816 * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. 817 * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. 818 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 819 * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) 820 * | | |0 = System Fail condition as edge-detect brake source Disabled. 821 * | | |1 = System Fail condition as edge-detect brake source Enabled. 822 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 823 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) 824 * | | |0 = ACMP0_O as level-detect brake source Disabled. 825 * | | |1 = ACMP0_O as level-detect brake source Enabled. 826 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 827 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) 828 * | | |0 = ACMP1_O as level-detect brake source Disabled. 829 * | | |1 = ACMP1_O as level-detect brake source Enabled. 830 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 831 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) 832 * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. 833 * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. 834 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 835 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) 836 * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. 837 * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. 838 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 839 * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) 840 * | | |0 = System Fail condition as level-detect brake source Disabled. 841 * | | |1 = System Fail condition as level-detect brake source Enabled. 842 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 843 * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) 844 * | | |00 = EPWMx brake event will not affect even channels output. 845 * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. 846 * | | |10 = EPWM even channel output low level when EPWMx brake event happened. 847 * | | |11 = EPWM even channel output high level when EPWMx brake event happened. 848 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 849 * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) 850 * | | |00 = EPWMx brake event will not affect odd channels output. 851 * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. 852 * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. 853 * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. 854 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 855 * |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect) 856 * | | |0 = EADCRM as edge-detect brake source Disabled. 857 * | | |1 = EADCRM as edge-detect brake source Enabled. 858 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 859 * |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect) 860 * | | |0 = EADCRM as level-detect brake source Disabled. 861 * | | |1 = EADCRM as level-detect brake source Enabled. 862 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 863 * @var EPWM_T::POLCTL 864 * Offset: 0xD4 EPWM Pin Polar Inverse Register 865 * --------------------------------------------------------------------------------------------------- 866 * |Bits |Field |Descriptions 867 * | :----: | :----: | :---- | 868 * |[0] |PINV0 |EPWM PIN Polar Inverse Control 869 * | | |The register controls polarity state of EPWM output. 870 * | | |0 = EPWM output polar inverse Disabled. 871 * | | |1 = EPWM output polar inverse Enabled. 872 * |[1] |PINV1 |EPWM PIN Polar Inverse Control 873 * | | |The register controls polarity state of EPWM output. 874 * | | |0 = EPWM output polar inverse Disabled. 875 * | | |1 = EPWM output polar inverse Enabled. 876 * |[2] |PINV2 |EPWM PIN Polar Inverse Control 877 * | | |The register controls polarity state of EPWM output. 878 * | | |0 = EPWM output polar inverse Disabled. 879 * | | |1 = EPWM output polar inverse Enabled. 880 * |[3] |PINV3 |EPWM PIN Polar Inverse Control 881 * | | |The register controls polarity state of EPWM output. 882 * | | |0 = EPWM output polar inverse Disabled. 883 * | | |1 = EPWM output polar inverse Enabled. 884 * |[4] |PINV4 |EPWM PIN Polar Inverse Control 885 * | | |The register controls polarity state of EPWM output. 886 * | | |0 = EPWM output polar inverse Disabled. 887 * | | |1 = EPWM output polar inverse Enabled. 888 * |[5] |PINV5 |EPWM PIN Polar Inverse Control 889 * | | |The register controls polarity state of EPWM output. 890 * | | |0 = EPWM output polar inverse Disabled. 891 * | | |1 = EPWM output polar inverse Enabled. 892 * @var EPWM_T::POEN 893 * Offset: 0xD8 EPWM Output Enable Register 894 * --------------------------------------------------------------------------------------------------- 895 * |Bits |Field |Descriptions 896 * | :----: | :----: | :---- | 897 * |[0] |POEN0 |EPWM Pin Output Enable Bits 898 * | | |0 = EPWM pin at tri-state. 899 * | | |1 = EPWM pin in output mode. 900 * |[1] |POEN1 |EPWM Pin Output Enable Bits 901 * | | |0 = EPWM pin at tri-state. 902 * | | |1 = EPWM pin in output mode. 903 * |[2] |POEN2 |EPWM Pin Output Enable Bits 904 * | | |0 = EPWM pin at tri-state. 905 * | | |1 = EPWM pin in output mode. 906 * |[3] |POEN3 |EPWM Pin Output Enable Bits 907 * | | |0 = EPWM pin at tri-state. 908 * | | |1 = EPWM pin in output mode. 909 * |[4] |POEN4 |EPWM Pin Output Enable Bits 910 * | | |0 = EPWM pin at tri-state. 911 * | | |1 = EPWM pin in output mode. 912 * |[5] |POEN5 |EPWM Pin Output Enable Bits 913 * | | |0 = EPWM pin at tri-state. 914 * | | |1 = EPWM pin in output mode. 915 * @var EPWM_T::SWBRK 916 * Offset: 0xDC EPWM Software Brake Control Register 917 * --------------------------------------------------------------------------------------------------- 918 * |Bits |Field |Descriptions 919 * | :----: | :----: | :---- | 920 * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) 921 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. 922 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 923 * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) 924 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. 925 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 926 * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) 927 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. 928 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 929 * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) 930 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. 931 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 932 * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) 933 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. 934 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 935 * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) 936 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. 937 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 938 * @var EPWM_T::INTEN0 939 * Offset: 0xE0 EPWM Interrupt Enable Register 0 940 * --------------------------------------------------------------------------------------------------- 941 * |Bits |Field |Descriptions 942 * | :----: | :----: | :---- | 943 * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits 944 * | | |0 = Zero point interrupt Disabled. 945 * | | |1 = Zero point interrupt Enabled. 946 * | | |Note: Odd channels will read always 0 at complementary mode. 947 * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits 948 * | | |0 = Zero point interrupt Disabled. 949 * | | |1 = Zero point interrupt Enabled. 950 * | | |Note: Odd channels will read always 0 at complementary mode. 951 * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits 952 * | | |0 = Zero point interrupt Disabled. 953 * | | |1 = Zero point interrupt Enabled. 954 * | | |Note: Odd channels will read always 0 at complementary mode. 955 * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits 956 * | | |0 = Zero point interrupt Disabled. 957 * | | |1 = Zero point interrupt Enabled. 958 * | | |Note: Odd channels will read always 0 at complementary mode. 959 * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits 960 * | | |0 = Zero point interrupt Disabled. 961 * | | |1 = Zero point interrupt Enabled. 962 * | | |Note: Odd channels will read always 0 at complementary mode. 963 * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits 964 * | | |0 = Zero point interrupt Disabled. 965 * | | |1 = Zero point interrupt Enabled. 966 * | | |Note: Odd channels will read always 0 at complementary mode. 967 * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits 968 * | | |0 = Period point interrupt Disabled. 969 * | | |1 = Period point interrupt Enabled. 970 * | | |Note1: When up-down counter type period point means center point. 971 * | | |Note2: Odd channels will read always 0 at complementary mode. 972 * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits 973 * | | |0 = Period point interrupt Disabled. 974 * | | |1 = Period point interrupt Enabled. 975 * | | |Note1: When up-down counter type period point means center point. 976 * | | |Note2: Odd channels will read always 0 at complementary mode. 977 * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits 978 * | | |0 = Period point interrupt Disabled. 979 * | | |1 = Period point interrupt Enabled. 980 * | | |Note1: When up-down counter type period point means center point. 981 * | | |Note2: Odd channels will read always 0 at complementary mode. 982 * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits 983 * | | |0 = Period point interrupt Disabled. 984 * | | |1 = Period point interrupt Enabled. 985 * | | |Note1: When up-down counter type period point means center point. 986 * | | |Note2: Odd channels will read always 0 at complementary mode. 987 * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits 988 * | | |0 = Period point interrupt Disabled. 989 * | | |1 = Period point interrupt Enabled. 990 * | | |Note1: When up-down counter type period point means center point. 991 * | | |Note2: Odd channels will read always 0 at complementary mode. 992 * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits 993 * | | |0 = Period point interrupt Disabled. 994 * | | |1 = Period point interrupt Enabled. 995 * | | |Note1: When up-down counter type period point means center point. 996 * | | |Note2: Odd channels will read always 0 at complementary mode. 997 * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits 998 * | | |0 = Compare up count interrupt Disabled. 999 * | | |1 = Compare up count interrupt Enabled. 1000 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 1001 * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits 1002 * | | |0 = Compare up count interrupt Disabled. 1003 * | | |1 = Compare up count interrupt Enabled. 1004 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 1005 * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits 1006 * | | |0 = Compare up count interrupt Disabled. 1007 * | | |1 = Compare up count interrupt Enabled. 1008 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 1009 * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits 1010 * | | |0 = Compare up count interrupt Disabled. 1011 * | | |1 = Compare up count interrupt Enabled. 1012 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 1013 * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits 1014 * | | |0 = Compare up count interrupt Disabled. 1015 * | | |1 = Compare up count interrupt Enabled. 1016 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 1017 * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits 1018 * | | |0 = Compare up count interrupt Disabled. 1019 * | | |1 = Compare up count interrupt Enabled. 1020 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 1021 * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits 1022 * | | |0 = Compare down count interrupt Disabled. 1023 * | | |1 = Compare down count interrupt Enabled. 1024 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1025 * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits 1026 * | | |0 = Compare down count interrupt Disabled. 1027 * | | |1 = Compare down count interrupt Enabled. 1028 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1029 * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits 1030 * | | |0 = Compare down count interrupt Disabled. 1031 * | | |1 = Compare down count interrupt Enabled. 1032 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1033 * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits 1034 * | | |0 = Compare down count interrupt Disabled. 1035 * | | |1 = Compare down count interrupt Enabled. 1036 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1037 * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits 1038 * | | |0 = Compare down count interrupt Disabled. 1039 * | | |1 = Compare down count interrupt Enabled. 1040 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1041 * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits 1042 * | | |0 = Compare down count interrupt Disabled. 1043 * | | |1 = Compare down count interrupt Enabled. 1044 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1045 * @var EPWM_T::INTEN1 1046 * Offset: 0xE4 EPWM Interrupt Enable Register 1 1047 * --------------------------------------------------------------------------------------------------- 1048 * |Bits |Field |Descriptions 1049 * | :----: | :----: | :---- | 1050 * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) 1051 * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. 1052 * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. 1053 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1054 * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) 1055 * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. 1056 * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. 1057 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1058 * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) 1059 * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. 1060 * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. 1061 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1062 * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) 1063 * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. 1064 * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. 1065 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1066 * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) 1067 * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. 1068 * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. 1069 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1070 * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) 1071 * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. 1072 * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. 1073 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1074 * @var EPWM_T::INTSTS0 1075 * Offset: 0xE8 EPWM Interrupt Flag Register 0 1076 * --------------------------------------------------------------------------------------------------- 1077 * |Bits |Field |Descriptions 1078 * | :----: | :----: | :---- | 1079 * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag 1080 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1081 * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag 1082 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1083 * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag 1084 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1085 * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag 1086 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1087 * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag 1088 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1089 * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag 1090 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1091 * |[8] |PIF0 |EPWM Period Point Interrupt Flag 1092 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. 1093 * |[9] |PIF1 |EPWM Period Point Interrupt Flag 1094 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. 1095 * |[10] |PIF2 |EPWM Period Point Interrupt Flag 1096 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. 1097 * |[11] |PIF3 |EPWM Period Point Interrupt Flag 1098 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. 1099 * |[12] |PIF4 |EPWM Period Point Interrupt Flag 1100 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. 1101 * |[13] |PIF5 |EPWM Period Point Interrupt Flag 1102 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. 1103 * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag 1104 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1105 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1106 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1107 * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag 1108 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1109 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1110 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1111 * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag 1112 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1113 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1114 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1115 * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag 1116 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1117 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1118 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1119 * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag 1120 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1121 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1122 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1123 * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag 1124 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1125 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1126 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1127 * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag 1128 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1129 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1130 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1131 * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag 1132 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1133 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1134 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1135 * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag 1136 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1137 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1138 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1139 * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag 1140 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1141 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1142 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1143 * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag 1144 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1145 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1146 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1147 * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag 1148 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1149 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1150 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1151 * @var EPWM_T::INTSTS1 1152 * Offset: 0xEC EPWM Interrupt Flag Register 1 1153 * --------------------------------------------------------------------------------------------------- 1154 * |Bits |Field |Descriptions 1155 * | :----: | :----: | :---- | 1156 * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect) 1157 * | | |0 = EPWM channel0 edge-detect brake event do not happened. 1158 * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1159 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1160 * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect) 1161 * | | |0 = EPWM channel1 edge-detect brake event do not happened. 1162 * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1163 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1164 * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect) 1165 * | | |0 = EPWM channel2 edge-detect brake event do not happened. 1166 * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1167 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1168 * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect) 1169 * | | |0 = EPWM channel3 edge-detect brake event do not happened. 1170 * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1171 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1172 * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect) 1173 * | | |0 = EPWM channel4 edge-detect brake event do not happened. 1174 * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1175 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1176 * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect) 1177 * | | |0 = EPWM channel5 edge-detect brake event do not happened. 1178 * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1179 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1180 * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect) 1181 * | | |0 = EPWM channel0 level-detect brake event do not happened. 1182 * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1183 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1184 * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect) 1185 * | | |0 = EPWM channel1 level-detect brake event do not happened. 1186 * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1187 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1188 * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect) 1189 * | | |0 = EPWM channel2 level-detect brake event do not happened. 1190 * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1191 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1192 * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) 1193 * | | |0 = EPWM channel3 level-detect brake event do not happened. 1194 * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1195 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1196 * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect) 1197 * | | |0 = EPWM channel4 level-detect brake event do not happened. 1198 * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1199 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1200 * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect) 1201 * | | |0 = EPWM channel5 level-detect brake event do not happened. 1202 * | | |1 = When EEPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1203 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 1204 * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only) 1205 * | | |0 = EPWM channel0 edge-detect brake state is released. 1206 * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear. 1207 * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only) 1208 * | | |0 = EPWM channel1 edge-detect brake state is released. 1209 * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear. 1210 * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only) 1211 * | | |0 = EPWM channel2 edge-detect brake state is released. 1212 * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear. 1213 * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only) 1214 * | | |0 = EPWM channel3 edge-detect brake state is released. 1215 * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear. 1216 * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only) 1217 * | | |0 = EPWM channel4 edge-detect brake state is released. 1218 * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear. 1219 * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only) 1220 * | | |0 = EPWM channel5 edge-detect brake state is released. 1221 * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear. 1222 * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only) 1223 * | | |0 = EPWM channel0 level-detect brake state is released. 1224 * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state. 1225 * | | |Note: This bit is read only and auto cleared by hardware 1226 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1227 * | | |The EPWM waveform will start output from next full EPWM period. 1228 * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only) 1229 * | | |0 = EPWM channel1 level-detect brake state is released. 1230 * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state. 1231 * | | |Note: This bit is read only and auto cleared by hardware 1232 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1233 * | | |The EPWM waveform will start output from next full EPWM period. 1234 * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only) 1235 * | | |0 = EPWM channel2 level-detect brake state is released. 1236 * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state. 1237 * | | |Note: This bit is read only and auto cleared by hardware 1238 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1239 * | | |The EPWM waveform will start output from next full EPWM period. 1240 * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only) 1241 * | | |0 = EPWM channel3 level-detect brake state is released. 1242 * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state. 1243 * | | |Note: This bit is read only and auto cleared by hardware 1244 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1245 * | | |The EPWM waveform will start output from next full EPWM period. 1246 * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only) 1247 * | | |0 = EPWM channel4 level-detect brake state is released. 1248 * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state. 1249 * | | |Note: This bit is read only and auto cleared by hardware 1250 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1251 * | | |The EPWM waveform will start output from next full EPWM period. 1252 * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only) 1253 * | | |0 = EPWM channel5 level-detect brake state is released. 1254 * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state. 1255 * | | |Note: This bit is read only and auto cleared by hardware 1256 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1257 * | | |The EPWM waveform will start output from next full EPWM period. 1258 * @var EPWM_T::DACTRGEN 1259 * Offset: 0xF4 EPWM Trigger DAC Enable Register 1260 * --------------------------------------------------------------------------------------------------- 1261 * |Bits |Field |Descriptions 1262 * | :----: | :----: | :---- | 1263 * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits 1264 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1265 * | | |0 = EPWM period point trigger DAC function Disabled. 1266 * | | |1 = EPWM period point trigger DAC function Enabled. 1267 * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits 1268 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1269 * | | |0 = EPWM period point trigger DAC function Disabled. 1270 * | | |1 = EPWM period point trigger DAC function Enabled. 1271 * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits 1272 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1273 * | | |0 = EPWM period point trigger DAC function Disabled. 1274 * | | |1 = EPWM period point trigger DAC function Enabled. 1275 * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits 1276 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1277 * | | |0 = EPWM period point trigger DAC function Disabled. 1278 * | | |1 = EPWM period point trigger DAC function Enabled. 1279 * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits 1280 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1281 * | | |0 = EPWM period point trigger DAC function Disabled. 1282 * | | |1 = EPWM period point trigger DAC function Enabled. 1283 * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits 1284 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1285 * | | |0 = EPWM period point trigger DAC function Disabled. 1286 * | | |1 = EPWM period point trigger DAC function Enabled. 1287 * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits 1288 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1289 * | | |0 = EPWM period point trigger DAC function Disabled. 1290 * | | |1 = EPWM period point trigger DAC function Enabled. 1291 * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits 1292 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1293 * | | |0 = EPWM period point trigger DAC function Disabled. 1294 * | | |1 = EPWM period point trigger DAC function Enabled. 1295 * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits 1296 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1297 * | | |0 = EPWM period point trigger DAC function Disabled. 1298 * | | |1 = EPWM period point trigger DAC function Enabled. 1299 * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits 1300 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1301 * | | |0 = EPWM period point trigger DAC function Disabled. 1302 * | | |1 = EPWM period point trigger DAC function Enabled. 1303 * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits 1304 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1305 * | | |0 = EPWM period point trigger DAC function Disabled. 1306 * | | |1 = EPWM period point trigger DAC function Enabled. 1307 * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits 1308 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1309 * | | |0 = EPWM period point trigger DAC function Disabled. 1310 * | | |1 = EPWM period point trigger DAC function Enabled. 1311 * |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1312 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1313 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1314 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1315 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1316 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1317 * |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1318 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1319 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1320 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1321 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1322 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1323 * |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1324 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1325 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1326 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1327 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1328 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1329 * |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1330 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1331 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1332 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1333 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1334 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1335 * |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1336 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1337 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1338 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1339 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1340 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1341 * |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1342 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1343 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1344 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1345 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1346 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1347 * |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1348 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1349 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1350 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1351 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1352 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1353 * |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1354 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1355 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1356 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1357 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1358 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1359 * |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1360 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1361 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1362 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1363 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1364 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1365 * |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1366 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1367 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1368 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1369 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1370 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1371 * |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1372 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1373 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1374 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1375 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1376 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1377 * |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1378 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1379 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1380 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1381 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1382 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1383 * @var EPWM_T::EADCTS0 1384 * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0 1385 * --------------------------------------------------------------------------------------------------- 1386 * |Bits |Field |Descriptions 1387 * | :----: | :----: | :---- | 1388 * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select 1389 * | | |0000 = EPWM_CH0 zero point. 1390 * | | |0001 = EPWM_CH0 period point. 1391 * | | |0010 = EPWM_CH0 zero or period point. 1392 * | | |0011 = EPWM_CH0 up-count CMPDAT point. 1393 * | | |0100 = EPWM_CH0 down-count CMPDAT point. 1394 * | | |0101 = EPWM_CH1 zero point. 1395 * | | |0110 = EPWM_CH1 period point. 1396 * | | |0111 = EPWM_CH1 zero or period point. 1397 * | | |1000 = EPWM_CH1 up-count CMPDAT point. 1398 * | | |1001 = EPWM_CH1 down-count CMPDAT point. 1399 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1400 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1401 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1402 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1403 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1404 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1405 * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit 1406 * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select 1407 * | | |0000 = EPWM_CH0 zero point. 1408 * | | |0001 = EPWM_CH0 period point. 1409 * | | |0010 = EPWM_CH0 zero or period point. 1410 * | | |0011 = EPWM_CH0 up-count CMPDAT point. 1411 * | | |0100 = EPWM_CH0 down-count CMPDAT point. 1412 * | | |0101 = EPWM_CH1 zero point. 1413 * | | |0110 = EPWM_CH1 period point. 1414 * | | |0111 = EPWM_CH1 zero or period point. 1415 * | | |1000 = EPWM_CH1 up-count CMPDAT point. 1416 * | | |1001 = EPWM_CH1 down-count CMPDAT point. 1417 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1418 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1419 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1420 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1421 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1422 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1423 * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit 1424 * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select 1425 * | | |0000 = EPWM_CH2 zero point. 1426 * | | |0001 = EPWM_CH2 period point. 1427 * | | |0010 = EPWM_CH2 zero or period point. 1428 * | | |0011 = EPWM_CH2 up-count CMPDAT point. 1429 * | | |0100 = EPWM_CH2 down-count CMPDAT point. 1430 * | | |0101 = EPWM_CH3 zero point. 1431 * | | |0110 = EPWM_CH3 period point. 1432 * | | |0111 = EPWM_CH3 zero or period point. 1433 * | | |1000 = EPWM_CH3 up-count CMPDAT point. 1434 * | | |1001 = EPWM_CH3 down-count CMPDAT point. 1435 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1436 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1437 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1438 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1439 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1440 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1441 * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit 1442 * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select 1443 * | | |0000 = EPWM_CH2 zero point. 1444 * | | |0001 = EPWM_CH2 period point. 1445 * | | |0010 = EPWM_CH2 zero or period point. 1446 * | | |0011 = EPWM_CH2 up-count CMPDAT point. 1447 * | | |0100 = EPWM_CH2 down-count CMPDAT point. 1448 * | | |0101 = EPWM_CH3 zero point. 1449 * | | |0110 = EPWM_CH3 period point. 1450 * | | |0111 = EPWM_CH3 zero or period point. 1451 * | | |1000 = EPWM_CH3 up-count CMPDAT point. 1452 * | | |1001 = EPWM_CH3 down-count CMPDAT point. 1453 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1454 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1455 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1456 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1457 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1458 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1459 * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit 1460 * @var EPWM_T::EADCTS1 1461 * Offset: 0xFC EPWM Trigger EADC Source Select Register 1 1462 * --------------------------------------------------------------------------------------------------- 1463 * |Bits |Field |Descriptions 1464 * | :----: | :----: | :---- | 1465 * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select 1466 * | | |0000 = EPWM_CH4 zero point. 1467 * | | |0001 = EPWM_CH4 period point. 1468 * | | |0010 = EPWM_CH4 zero or period point. 1469 * | | |0011 = EPWM_CH4 up-count CMPDAT point. 1470 * | | |0100 = EPWM_CH4 down-count CMPDAT point. 1471 * | | |0101 = EPWM_CH5 zero point. 1472 * | | |0110 = EPWM_CH5 period point. 1473 * | | |0111 = EPWM_CH5 zero or period point. 1474 * | | |1000 = EPWM_CH5 up-count CMPDAT point. 1475 * | | |1001 = EPWM_CH5 down-count CMPDAT point. 1476 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1477 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1478 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1479 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1480 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1481 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1482 * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit 1483 * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select 1484 * | | |0000 = EPWM_CH4 zero point. 1485 * | | |0001 = EPWM_CH4 period point. 1486 * | | |0010 = EPWM_CH4 zero or period point. 1487 * | | |0011 = EPWM_CH4 up-count CMPDAT point. 1488 * | | |0100 = EPWM_CH4 down-count CMPDAT point. 1489 * | | |0101 = EPWM_CH5 zero point. 1490 * | | |0110 = EPWM_CH5 period point. 1491 * | | |0111 = EPWM_CH5 zero or period point. 1492 * | | |1000 = EPWM_CH5 up-count CMPDAT point. 1493 * | | |1001 = EPWM_CH5 down-count CMPDAT point. 1494 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1495 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1496 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1497 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1498 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1499 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1500 * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit 1501 * @var EPWM_T::FTCMPDAT[3] 1502 * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5 1503 * --------------------------------------------------------------------------------------------------- 1504 * |Bits |Field |Descriptions 1505 * | :----: | :----: | :---- | 1506 * |[15:0] |FTCMP |EPWM Free Trigger Compare Register 1507 * | | |FTCMP use to compare with even CNTR to trigger EADC 1508 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. 1509 * @var EPWM_T::SSCTL 1510 * Offset: 0x110 EPWM Synchronous Start Control Register 1511 * --------------------------------------------------------------------------------------------------- 1512 * |Bits |Field |Descriptions 1513 * | :----: | :----: | :---- | 1514 * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits 1515 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1516 * | | |0 = EPWM synchronous start function Disabled. 1517 * | | |1 = EPWM synchronous start function Enabled. 1518 * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits 1519 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1520 * | | |0 = EPWM synchronous start function Disabled. 1521 * | | |1 = EPWM synchronous start function Enabled. 1522 * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits 1523 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1524 * | | |0 = EPWM synchronous start function Disabled. 1525 * | | |1 = EPWM synchronous start function Enabled. 1526 * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits 1527 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1528 * | | |0 = EPWM synchronous start function Disabled. 1529 * | | |1 = EPWM synchronous start function Enabled. 1530 * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits 1531 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1532 * | | |0 = EPWM synchronous start function Disabled. 1533 * | | |1 = EPWM synchronous start function Enabled. 1534 * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits 1535 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1536 * | | |0 = EPWM synchronous start function Disabled. 1537 * | | |1 = EPWM synchronous start function Enabled. 1538 * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits 1539 * | | |00 = Synchronous start source come from EPWM0. 1540 * | | |01 = Synchronous start source come from EPWM1. 1541 * | | |10 = Synchronous start source come from BPWM0. 1542 * | | |11 = Synchronous start source come from BPWM1. 1543 * @var EPWM_T::SSTRG 1544 * Offset: 0x114 EPWM Synchronous Start Trigger Register 1545 * --------------------------------------------------------------------------------------------------- 1546 * |Bits |Field |Descriptions 1547 * | :----: | :----: | :---- | 1548 * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only) 1549 * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. 1550 * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. 1551 * @var EPWM_T::LEBCTL 1552 * Offset: 0x118 EPWM Leading Edge Blanking Control Register 1553 * --------------------------------------------------------------------------------------------------- 1554 * |Bits |Field |Descriptions 1555 * | :----: | :----: | :---- | 1556 * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit 1557 * | | |0 = EPWM Leading Edge Blanking Disabled. 1558 * | | |1 = EPWM Leading Edge Blanking Enabled. 1559 * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit 1560 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled. 1561 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled. 1562 * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit 1563 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled. 1564 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled. 1565 * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit 1566 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled. 1567 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled. 1568 * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type 1569 * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting. 1570 * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting. 1571 * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting. 1572 * | | |3 = Reserved. 1573 * @var EPWM_T::LEBCNT 1574 * Offset: 0x11C EPWM Leading Edge Blanking Counter Register 1575 * --------------------------------------------------------------------------------------------------- 1576 * |Bits |Field |Descriptions 1577 * | :----: | :----: | :---- | 1578 * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter 1579 * | | |This counter value decides leading edge blanking window size 1580 * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK. 1581 * @var EPWM_T::STATUS 1582 * Offset: 0x120 EPWM Status Register 1583 * --------------------------------------------------------------------------------------------------- 1584 * |Bits |Field |Descriptions 1585 * | :----: | :----: | :---- | 1586 * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag 1587 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1588 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1589 * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag 1590 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1591 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1592 * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag 1593 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1594 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1595 * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag 1596 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1597 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1598 * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag 1599 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1600 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1601 * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag 1602 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1603 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1604 * |[8] |SYNCINF0 |Input Synchronization Latched Flag 1605 * | | |0 = Indicates no SYNC_IN event has occurred. 1606 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. 1607 * |[9] |SYNCINF2 |Input Synchronization Latched Flag 1608 * | | |0 = Indicates no SYNC_IN event has occurred. 1609 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. 1610 * |[10] |SYNCINF4 |Input Synchronization Latched Flag 1611 * | | |0 = Indicates no SYNC_IN event has occurred. 1612 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. 1613 * |[16] |EADCTRGF0 |EADC Start of Conversion Flag 1614 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1615 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1616 * |[17] |EADCTRGF1 |EADC Start of Conversion Flag 1617 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1618 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1619 * |[18] |EADCTRGF2 |EADC Start of Conversion Flag 1620 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1621 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1622 * |[19] |EADCTRGF3 |EADC Start of Conversion Flag 1623 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1624 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1625 * |[20] |EADCTRGF4 |EADC Start of Conversion Flag 1626 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1627 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1628 * |[21] |EADCTRGF5 |EADC Start of Conversion Flag 1629 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1630 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1631 * |[24] |DACTRGF |DAC Start of Conversion Flag 1632 * | | |0 = Indicates no DAC start of conversion trigger event has occurred. 1633 * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit 1634 * @var EPWM_T::IFA[6] 1635 * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5 1636 * --------------------------------------------------------------------------------------------------- 1637 * |Bits |Field |Descriptions 1638 * | :----: | :----: | :---- | 1639 * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter 1640 * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. 1641 * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. 1642 * |[24] |STPMOD |EPWM_CHn Interrupt Flag Accumulator Stop Mode Enable Bits 1643 * | | |0 = EPWM_CHn interrupt flag accumulator stop mode disable. 1644 * | | |1 = EPWM_CHn interrupt flag accumulator stop mode enable. 1645 * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select 1646 * | | |00 = CNT equal to Zero in channel n. 1647 * | | |01 = CNT equal to PERIOD in channel n. 1648 * | | |10 = CNT equal to CMPU in channel n. 1649 * | | |11 = CNT equal to CMPD in channel n. 1650 * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits 1651 * | | |0 = EPWM_CHn interrupt flag accumulator disable. 1652 * | | |1 = EPWM_CHn interrupt flag accumulator enable. 1653 * @var EPWM_T::AINTSTS 1654 * Offset: 0x150 EPWM Accumulator Interrupt Flag Register 1655 * --------------------------------------------------------------------------------------------------- 1656 * |Bits |Field |Descriptions 1657 * | :----: | :----: | :---- | 1658 * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1659 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1660 * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1661 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1662 * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1663 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1664 * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1665 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1666 * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1667 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1668 * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1669 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1670 * @var EPWM_T::AINTEN 1671 * Offset: 0x154 EPWM Accumulator Interrupt Enable Register 1672 * --------------------------------------------------------------------------------------------------- 1673 * |Bits |Field |Descriptions 1674 * | :----: | :----: | :---- | 1675 * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1676 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1677 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1678 * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1679 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1680 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1681 * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1682 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1683 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1684 * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1685 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1686 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1687 * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1688 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1689 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1690 * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1691 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1692 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1693 * @var EPWM_T::APDMACTL 1694 * Offset: 0x158 EPWM Accumulator PDMA Control Register 1695 * --------------------------------------------------------------------------------------------------- 1696 * |Bits |Field |Descriptions 1697 * | :----: | :----: | :---- | 1698 * |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits 1699 * | | |0 = Channel n PDMA function Disabled. 1700 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1701 * |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits 1702 * | | |0 = Channel n PDMA function Disabled. 1703 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1704 * |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits 1705 * | | |0 = Channel n PDMA function Disabled. 1706 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1707 * |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits 1708 * | | |0 = Channel n PDMA function Disabled. 1709 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1710 * |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits 1711 * | | |0 = Channel n PDMA function Disabled. 1712 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1713 * |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits 1714 * | | |0 = Channel n PDMA function Disabled. 1715 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1716 * @var EPWM_T::CAPINEN 1717 * Offset: 0x200 EPWM Capture Input Enable Register 1718 * --------------------------------------------------------------------------------------------------- 1719 * |Bits |Field |Descriptions 1720 * | :----: | :----: | :---- | 1721 * |[0] |CAPINEN0 |Capture Input Enable Bits 1722 * | | |0 = EPWM Channel capture input path Disabled 1723 * | | |The input of EPWM channel capture function is always regarded as 0. 1724 * | | |1 = EPWM Channel capture input path Enabled 1725 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1726 * |[1] |CAPINEN1 |Capture Input Enable Bits 1727 * | | |0 = EPWM Channel capture input path Disabled 1728 * | | |The input of EPWM channel capture function is always regarded as 0. 1729 * | | |1 = EPWM Channel capture input path Enabled 1730 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1731 * |[2] |CAPINEN2 |Capture Input Enable Bits 1732 * | | |0 = EPWM Channel capture input path Disabled 1733 * | | |The input of EPWM channel capture function is always regarded as 0. 1734 * | | |1 = EPWM Channel capture input path Enabled 1735 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1736 * |[3] |CAPINEN3 |Capture Input Enable Bits 1737 * | | |0 = EPWM Channel capture input path Disabled 1738 * | | |The input of EPWM channel capture function is always regarded as 0. 1739 * | | |1 = EPWM Channel capture input path Enabled 1740 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1741 * |[4] |CAPINEN4 |Capture Input Enable Bits 1742 * | | |0 = EPWM Channel capture input path Disabled 1743 * | | |The input of EPWM channel capture function is always regarded as 0. 1744 * | | |1 = EPWM Channel capture input path Enabled 1745 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1746 * |[5] |CAPINEN5 |Capture Input Enable Bits 1747 * | | |0 = EPWM Channel capture input path Disabled 1748 * | | |The input of EPWM channel capture function is always regarded as 0. 1749 * | | |1 = EPWM Channel capture input path Enabled 1750 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1751 * @var EPWM_T::CAPCTL 1752 * Offset: 0x204 EPWM Capture Control Register 1753 * --------------------------------------------------------------------------------------------------- 1754 * |Bits |Field |Descriptions 1755 * | :----: | :----: | :---- | 1756 * |[0] |CAPEN0 |Capture Function Enable Bits 1757 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1758 * | | |1 = Capture function Enabled 1759 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1760 * |[1] |CAPEN1 |Capture Function Enable Bits 1761 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1762 * | | |1 = Capture function Enabled 1763 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1764 * |[2] |CAPEN2 |Capture Function Enable Bits 1765 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1766 * | | |1 = Capture function Enabled 1767 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1768 * |[3] |CAPEN3 |Capture Function Enable Bits 1769 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1770 * | | |1 = Capture function Enabled 1771 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1772 * |[4] |CAPEN4 |Capture Function Enable Bits 1773 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1774 * | | |1 = Capture function Enabled 1775 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1776 * |[5] |CAPEN5 |Capture Function Enable Bits 1777 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1778 * | | |1 = Capture function Enabled 1779 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1780 * |[8] |CAPINV0 |Capture Inverter Enable Bits 1781 * | | |0 = Capture source inverter Disabled. 1782 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1783 * |[9] |CAPINV1 |Capture Inverter Enable Bits 1784 * | | |0 = Capture source inverter Disabled. 1785 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1786 * |[10] |CAPINV2 |Capture Inverter Enable Bits 1787 * | | |0 = Capture source inverter Disabled. 1788 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1789 * |[11] |CAPINV3 |Capture Inverter Enable Bits 1790 * | | |0 = Capture source inverter Disabled. 1791 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1792 * |[12] |CAPINV4 |Capture Inverter Enable Bits 1793 * | | |0 = Capture source inverter Disabled. 1794 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1795 * |[13] |CAPINV5 |Capture Inverter Enable Bits 1796 * | | |0 = Capture source inverter Disabled. 1797 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1798 * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits 1799 * | | |0 = Rising capture reload counter Disabled. 1800 * | | |1 = Rising capture reload counter Enabled. 1801 * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits 1802 * | | |0 = Rising capture reload counter Disabled. 1803 * | | |1 = Rising capture reload counter Enabled. 1804 * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits 1805 * | | |0 = Rising capture reload counter Disabled. 1806 * | | |1 = Rising capture reload counter Enabled. 1807 * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits 1808 * | | |0 = Rising capture reload counter Disabled. 1809 * | | |1 = Rising capture reload counter Enabled. 1810 * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits 1811 * | | |0 = Rising capture reload counter Disabled. 1812 * | | |1 = Rising capture reload counter Enabled. 1813 * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits 1814 * | | |0 = Rising capture reload counter Disabled. 1815 * | | |1 = Rising capture reload counter Enabled. 1816 * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits 1817 * | | |0 = Falling capture reload counter Disabled. 1818 * | | |1 = Falling capture reload counter Enabled. 1819 * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits 1820 * | | |0 = Falling capture reload counter Disabled. 1821 * | | |1 = Falling capture reload counter Enabled. 1822 * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits 1823 * | | |0 = Falling capture reload counter Disabled. 1824 * | | |1 = Falling capture reload counter Enabled. 1825 * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits 1826 * | | |0 = Falling capture reload counter Disabled. 1827 * | | |1 = Falling capture reload counter Enabled. 1828 * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits 1829 * | | |0 = Falling capture reload counter Disabled. 1830 * | | |1 = Falling capture reload counter Enabled. 1831 * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits 1832 * | | |0 = Falling capture reload counter Disabled. 1833 * | | |1 = Falling capture reload counter Enabled. 1834 * @var EPWM_T::CAPSTS 1835 * Offset: 0x208 EPWM Capture Status Register 1836 * --------------------------------------------------------------------------------------------------- 1837 * |Bits |Field |Descriptions 1838 * | :----: | :----: | :---- | 1839 * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1840 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1841 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1842 * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1843 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1844 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1845 * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1846 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1847 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1848 * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1849 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1850 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1851 * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1852 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1853 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1854 * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1855 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1856 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1857 * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1858 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1859 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1860 * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1861 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1862 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1863 * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1864 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1865 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1866 * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1867 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1868 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1869 * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1870 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1871 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1872 * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1873 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1874 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1875 * @var EPWM_T::PDMACTL 1876 * Offset: 0x23C EPWM PDMA Control Register 1877 * --------------------------------------------------------------------------------------------------- 1878 * |Bits |Field |Descriptions 1879 * | :----: | :----: | :---- | 1880 * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable 1881 * | | |0 = Channel 0/1 PDMA function Disabled. 1882 * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. 1883 * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer 1884 * | | |00 = Reserved. 1885 * | | |01 = EPWM_RCAPDAT0/1. 1886 * | | |10 = EPWM_FCAPDAT0/1. 1887 * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1. 1888 * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order 1889 * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11. 1890 * | | |0 = EPWM_FCAPDAT0/1 is the first captured data to memory. 1891 * | | |1 = EPWM_RCAPDAT0/1 is the first captured data to memory. 1892 * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer 1893 * | | |0 = Channel0. 1894 * | | |1 = Channel1. 1895 * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable 1896 * | | |0 = Channel 2/3 PDMA function Disabled. 1897 * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. 1898 * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer 1899 * | | |00 = Reserved. 1900 * | | |01 = EPWM_RCAPDAT2/3. 1901 * | | |10 = EPWM_FCAPDAT2/3. 1902 * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3. 1903 * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order 1904 * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11. 1905 * | | |0 = EPWM_FCAPDAT2/3 is the first captured data to memory. 1906 * | | |1 = EPWM_RCAPDAT2/3 is the first captured data to memory. 1907 * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer 1908 * | | |0 = Channel2. 1909 * | | |1 = Channel3. 1910 * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable 1911 * | | |0 = Channel 4/5 PDMA function Disabled. 1912 * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. 1913 * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer 1914 * | | |00 = Reserved. 1915 * | | |01 = EPWM_RCAPDAT4/5. 1916 * | | |10 = EPWM_FCAPDAT4/5. 1917 * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5. 1918 * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order 1919 * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11. 1920 * | | |0 = EPWM_FCAPDAT4/5 is the first captured data to memory. 1921 * | | |1 = EPWM_RCAPDAT4/5 is the first captured data to memory. 1922 * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer 1923 * | | |0 = Channel4. 1924 * | | |1 = Channel5. 1925 * @var EPWM_T::PDMACAP[3] 1926 * Offset: 0x240 EPWM Capture Channel 01 PDMA Register 1927 * --------------------------------------------------------------------------------------------------- 1928 * |Bits |Field |Descriptions 1929 * | :----: | :----: | :---- | 1930 * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) 1931 * | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. 1932 * @var EPWM_T::CAPIEN 1933 * Offset: 0x250 EPWM Capture Interrupt Enable Register 1934 * --------------------------------------------------------------------------------------------------- 1935 * |Bits |Field |Descriptions 1936 * | :----: | :----: | :---- | 1937 * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits 1938 * | | |0 = Capture rising edge latch interrupt Disabled. 1939 * | | |1 = Capture rising edge latch interrupt Enabled. 1940 * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits 1941 * | | |0 = Capture rising edge latch interrupt Disabled. 1942 * | | |1 = Capture rising edge latch interrupt Enabled. 1943 * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits 1944 * | | |0 = Capture rising edge latch interrupt Disabled. 1945 * | | |1 = Capture rising edge latch interrupt Enabled. 1946 * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits 1947 * | | |0 = Capture rising edge latch interrupt Disabled. 1948 * | | |1 = Capture rising edge latch interrupt Enabled. 1949 * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits 1950 * | | |0 = Capture rising edge latch interrupt Disabled. 1951 * | | |1 = Capture rising edge latch interrupt Enabled. 1952 * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits 1953 * | | |0 = Capture rising edge latch interrupt Disabled. 1954 * | | |1 = Capture rising edge latch interrupt Enabled. 1955 * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits 1956 * | | |0 = Capture falling edge latch interrupt Disabled. 1957 * | | |1 = Capture falling edge latch interrupt Enabled. 1958 * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits 1959 * | | |0 = Capture falling edge latch interrupt Disabled. 1960 * | | |1 = Capture falling edge latch interrupt Enabled. 1961 * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits 1962 * | | |0 = Capture falling edge latch interrupt Disabled. 1963 * | | |1 = Capture falling edge latch interrupt Enabled. 1964 * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits 1965 * | | |0 = Capture falling edge latch interrupt Disabled. 1966 * | | |1 = Capture falling edge latch interrupt Enabled. 1967 * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits 1968 * | | |0 = Capture falling edge latch interrupt Disabled. 1969 * | | |1 = Capture falling edge latch interrupt Enabled. 1970 * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits 1971 * | | |0 = Capture falling edge latch interrupt Disabled. 1972 * | | |1 = Capture falling edge latch interrupt Enabled. 1973 * @var EPWM_T::CAPIF 1974 * Offset: 0x254 EPWM Capture Interrupt Flag Register 1975 * --------------------------------------------------------------------------------------------------- 1976 * |Bits |Field |Descriptions 1977 * | :----: | :----: | :---- | 1978 * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag 1979 * | | |This bit is writing 1 to clear. 1980 * | | |0 = No capture rising latch condition happened. 1981 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1982 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. 1983 * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag 1984 * | | |This bit is writing 1 to clear. 1985 * | | |0 = No capture rising latch condition happened. 1986 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1987 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. 1988 * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag 1989 * | | |This bit is writing 1 to clear. 1990 * | | |0 = No capture rising latch condition happened. 1991 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1992 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. 1993 * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag 1994 * | | |This bit is writing 1 to clear. 1995 * | | |0 = No capture rising latch condition happened. 1996 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1997 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. 1998 * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag 1999 * | | |This bit is writing 1 to clear. 2000 * | | |0 = No capture rising latch condition happened. 2001 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 2002 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. 2003 * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag 2004 * | | |This bit is writing 1 to clear. 2005 * | | |0 = No capture rising latch condition happened. 2006 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 2007 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. 2008 * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag 2009 * | | |This bit is writing 1 to clear. 2010 * | | |0 = No capture falling latch condition happened. 2011 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2012 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. 2013 * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag 2014 * | | |This bit is writing 1 to clear. 2015 * | | |0 = No capture falling latch condition happened. 2016 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2017 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. 2018 * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag 2019 * | | |This bit is writing 1 to clear. 2020 * | | |0 = No capture falling latch condition happened. 2021 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2022 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. 2023 * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag 2024 * | | |This bit is writing 1 to clear. 2025 * | | |0 = No capture falling latch condition happened. 2026 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2027 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. 2028 * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag 2029 * | | |This bit is writing 1 to clear. 2030 * | | |0 = No capture falling latch condition happened. 2031 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2032 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. 2033 * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag 2034 * | | |This bit is writing 1 to clear. 2035 * | | |0 = No capture falling latch condition happened. 2036 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2037 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. 2038 * @var EPWM_T::PBUF[6] 2039 * Offset: 0x304 EPWM PERIOD0~5 Buffer 2040 * --------------------------------------------------------------------------------------------------- 2041 * |Bits |Field |Descriptions 2042 * | :----: | :----: | :---- | 2043 * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) 2044 * | | |Used as PERIOD active register. 2045 * @var EPWM_T::CMPBUF[6] 2046 * Offset: 0x31C EPWM CMPDAT0~5 Buffer 2047 * --------------------------------------------------------------------------------------------------- 2048 * |Bits |Field |Descriptions 2049 * | :----: | :----: | :---- | 2050 * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) 2051 * | | |Used as CMP active register. 2052 * @var EPWM_T::CPSCBUF[3] 2053 * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer 2054 * --------------------------------------------------------------------------------------------------- 2055 * |Bits |Field |Descriptions 2056 * | :----: | :----: | :---- | 2057 * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer 2058 * | | |Use as EPWM counter clock prescale active register. 2059 * @var EPWM_T::FTCBUF[3] 2060 * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer 2061 * --------------------------------------------------------------------------------------------------- 2062 * |Bits |Field |Descriptions 2063 * | :----: | :----: | :---- | 2064 * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) 2065 * | | |Used as FTCMPDAT active register. 2066 * @var EPWM_T::FTCI 2067 * Offset: 0x34C EPWM FTCMPDAT Indicator Register 2068 * --------------------------------------------------------------------------------------------------- 2069 * |Bits |Field |Descriptions 2070 * | :----: | :----: | :---- | 2071 * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator 2072 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. 2073 * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator 2074 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. 2075 * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator 2076 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. 2077 * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator 2078 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. 2079 * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator 2080 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. 2081 * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator 2082 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. 2083 */ 2084 __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */ 2085 __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */ 2086 __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */ 2087 __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */ 2088 __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */ 2089 __IO uint32_t CLKPSC[3]; /*!< [0x0014] EPWM Clock Prescale Register 0/1,2/3,4/5 */ 2090 __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */ 2091 __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */ 2092 __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */ 2093 /// @cond HIDDEN_SYMBOLS 2094 __I uint32_t RESERVE0[1]; 2095 /// @endcond //HIDDEN_SYMBOLS 2096 __IO uint32_t PERIOD[6]; /*!< [0x0030] EPWM Period Register 0~5 */ 2097 /// @cond HIDDEN_SYMBOLS 2098 __I uint32_t RESERVE1[2]; 2099 /// @endcond //HIDDEN_SYMBOLS 2100 __IO uint32_t CMPDAT[6]; /*!< [0x0050] EPWM Comparator Register 0~5 */ 2101 /// @cond HIDDEN_SYMBOLS 2102 __I uint32_t RESERVE2[2]; 2103 /// @endcond //HIDDEN_SYMBOLS 2104 __IO uint32_t DTCTL[3]; /*!< [0x0070] EPWM Dead-Time Control Register 0/1,2/3,4/5 */ 2105 /// @cond HIDDEN_SYMBOLS 2106 __I uint32_t RESERVE3[1]; 2107 /// @endcond //HIDDEN_SYMBOLS 2108 __IO uint32_t PHS[3]; /*!< [0x0080] EPWM Counter Phase Register 0/1,2/3,4/5 */ 2109 /// @cond HIDDEN_SYMBOLS 2110 __I uint32_t RESERVE4[1]; 2111 /// @endcond //HIDDEN_SYMBOLS 2112 __I uint32_t CNT[6]; /*!< [0x0090] EPWM Counter Register 0~5 */ 2113 /// @cond HIDDEN_SYMBOLS 2114 __I uint32_t RESERVE5[2]; 2115 /// @endcond //HIDDEN_SYMBOLS 2116 __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */ 2117 __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */ 2118 __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */ 2119 __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */ 2120 __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */ 2121 __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */ 2122 __IO uint32_t BRKCTL[3]; /*!< [0x00c8] EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 */ 2123 __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */ 2124 __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */ 2125 __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */ 2126 __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */ 2127 __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */ 2128 __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */ 2129 __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */ 2130 /// @cond HIDDEN_SYMBOLS 2131 __I uint32_t RESERVE6[1]; 2132 /// @endcond //HIDDEN_SYMBOLS 2133 __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */ 2134 __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */ 2135 __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */ 2136 __IO uint32_t FTCMPDAT[3]; /*!< [0x0100] EPWM Free Trigger Compare Register 0/1,2/3,4/5 */ 2137 /// @cond HIDDEN_SYMBOLS 2138 __I uint32_t RESERVE7[1]; 2139 /// @endcond //HIDDEN_SYMBOLS 2140 __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */ 2141 __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */ 2142 __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */ 2143 __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */ 2144 __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */ 2145 /// @cond HIDDEN_SYMBOLS 2146 __I uint32_t RESERVE8[3]; 2147 /// @endcond //HIDDEN_SYMBOLS 2148 __IO uint32_t IFA[6]; /*!< [0x0130] EPWM Interrupt Flag Accumulator Register 0~5 */ 2149 /// @cond HIDDEN_SYMBOLS 2150 __I uint32_t RESERVE9[2]; 2151 /// @endcond //HIDDEN_SYMBOLS 2152 __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */ 2153 __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */ 2154 __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */ 2155 /// @cond HIDDEN_SYMBOLS 2156 __I uint32_t RESERVE10[1]; 2157 /// @endcond //HIDDEN_SYMBOLS 2158 __IO uint32_t FDEN; /*!< [0x0160] EPWM Fault Detect Enable Register */ 2159 __IO uint32_t FDCTL[6]; /*!< [0x0164~0x178] EPWM Fault Detect Control Register 0~5 */ 2160 __IO uint32_t FDIEN; /*!< [0x017C] EPWM Fault Detect Interrupt Enable Register */ 2161 __IO uint32_t FDSTS; /*!< [0x0180] EPWM Fault Detect Interrupt Flag Register */ 2162 __IO uint32_t EADCPSCCTL; /*!< [0x0184] EPWM Trigger EADC Prescale Control Register */ 2163 __IO uint32_t EADCPSC0; /*!< [0x0188] EPWM Trigger EADC Prescale Register 0 */ 2164 __IO uint32_t EADCPSC1; /*!< [0x018C] EPWM Trigger EADC Prescale Register 1 */ 2165 __IO uint32_t EADCPSCNT0; /*!< [0x0190] EPWM Trigger EADC Prescale Counter Register 0 */ 2166 __IO uint32_t EADCPSCNT1; /*!< [0x0194] EPWM Trigger EADC Prescale Counter Register 1 */ 2167 /// @cond HIDDEN_SYMBOLS 2168 __I uint32_t RESERVE11[26]; 2169 /// @endcond //HIDDEN_SYMBOLS 2170 __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */ 2171 __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */ 2172 __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */ 2173 ECAPDAT_T CAPDAT[6]; /*!< [0x020C] EPWM Rising and Falling Capture Data Register 0~5 */ 2174 __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */ 2175 __I uint32_t PDMACAP[3]; /*!< [0x0240] EPWM Capture Channel 01,23,45 PDMA Register */ 2176 /// @cond HIDDEN_SYMBOLS 2177 __I uint32_t RESERVE12[1]; 2178 /// @endcond //HIDDEN_SYMBOLS 2179 __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */ 2180 __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */ 2181 /// @cond HIDDEN_SYMBOLS 2182 __I uint32_t RESERVE13[43]; 2183 /// @endcond //HIDDEN_SYMBOLS 2184 __I uint32_t PBUF[6]; /*!< [0x0304] EPWM PERIOD0~5 Buffer */ 2185 __I uint32_t CMPBUF[6]; /*!< [0x031c] EPWM CMPDAT0~5 Buffer */ 2186 __I uint32_t CPSCBUF[3]; /*!< [0x0334] EPWM CLKPSC0_1/2_3/4_5 Buffer */ 2187 __I uint32_t FTCBUF[3]; /*!< [0x0340] EPWM FTCMPDAT0_1/2_3/4_5 Buffer */ 2188 __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */ 2189 2190 } EPWM_T; 2191 2192 /** 2193 @addtogroup EPWM_CONST EPWM Bit Field Definition 2194 Constant Definitions for EPWM Controller 2195 @{ */ 2196 2197 #define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */ 2198 #define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */ 2199 2200 #define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */ 2201 #define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */ 2202 2203 #define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */ 2204 #define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */ 2205 2206 #define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */ 2207 #define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */ 2208 2209 #define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */ 2210 #define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */ 2211 2212 #define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */ 2213 #define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */ 2214 2215 #define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */ 2216 #define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */ 2217 2218 #define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */ 2219 #define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */ 2220 2221 #define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */ 2222 #define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */ 2223 2224 #define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */ 2225 #define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */ 2226 2227 #define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */ 2228 #define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */ 2229 2230 #define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */ 2231 #define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */ 2232 2233 #define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */ 2234 #define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */ 2235 2236 #define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */ 2237 #define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */ 2238 2239 #define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */ 2240 #define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */ 2241 2242 #define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */ 2243 #define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */ 2244 2245 #define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */ 2246 #define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */ 2247 2248 #define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */ 2249 #define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */ 2250 2251 #define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */ 2252 #define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */ 2253 2254 #define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */ 2255 #define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */ 2256 2257 #define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */ 2258 #define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */ 2259 2260 #define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */ 2261 #define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */ 2262 2263 #define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */ 2264 #define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */ 2265 2266 #define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */ 2267 #define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */ 2268 2269 #define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */ 2270 #define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */ 2271 2272 #define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */ 2273 #define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */ 2274 2275 #define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */ 2276 #define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */ 2277 2278 #define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */ 2279 #define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */ 2280 2281 #define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */ 2282 #define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */ 2283 2284 #define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */ 2285 #define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */ 2286 2287 #define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */ 2288 #define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */ 2289 2290 #define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */ 2291 #define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */ 2292 2293 #define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */ 2294 #define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */ 2295 2296 #define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */ 2297 #define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */ 2298 2299 #define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */ 2300 #define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */ 2301 2302 #define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */ 2303 #define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */ 2304 2305 #define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */ 2306 #define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */ 2307 2308 #define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */ 2309 #define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */ 2310 2311 #define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */ 2312 #define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */ 2313 2314 #define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */ 2315 #define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */ 2316 2317 #define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */ 2318 #define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */ 2319 2320 #define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */ 2321 #define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */ 2322 2323 #define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */ 2324 #define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */ 2325 2326 #define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */ 2327 #define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */ 2328 2329 #define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */ 2330 #define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */ 2331 2332 #define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */ 2333 #define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */ 2334 2335 #define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */ 2336 #define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */ 2337 2338 #define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */ 2339 #define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */ 2340 2341 #define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */ 2342 #define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */ 2343 2344 #define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */ 2345 #define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */ 2346 2347 #define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */ 2348 #define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */ 2349 2350 #define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */ 2351 #define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */ 2352 2353 #define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */ 2354 #define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */ 2355 2356 #define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */ 2357 #define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */ 2358 2359 #define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */ 2360 #define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */ 2361 2362 #define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */ 2363 #define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */ 2364 2365 #define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */ 2366 #define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */ 2367 2368 #define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */ 2369 #define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */ 2370 2371 #define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */ 2372 #define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */ 2373 2374 #define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */ 2375 #define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */ 2376 2377 #define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */ 2378 #define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */ 2379 2380 #define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */ 2381 #define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */ 2382 2383 #define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */ 2384 #define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */ 2385 2386 #define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */ 2387 #define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */ 2388 2389 #define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */ 2390 #define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */ 2391 2392 #define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */ 2393 #define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */ 2394 2395 #define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */ 2396 #define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */ 2397 2398 #define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */ 2399 #define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */ 2400 2401 #define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */ 2402 #define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */ 2403 2404 #define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */ 2405 #define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */ 2406 2407 #define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */ 2408 #define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */ 2409 2410 #define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */ 2411 #define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */ 2412 2413 #define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */ 2414 #define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */ 2415 2416 #define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */ 2417 #define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */ 2418 2419 #define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */ 2420 #define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */ 2421 2422 #define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */ 2423 #define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */ 2424 2425 #define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */ 2426 #define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */ 2427 2428 #define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */ 2429 #define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */ 2430 2431 #define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */ 2432 #define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */ 2433 2434 #define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */ 2435 #define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */ 2436 2437 #define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */ 2438 #define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */ 2439 2440 #define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */ 2441 #define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */ 2442 2443 #define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */ 2444 #define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */ 2445 2446 #define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */ 2447 #define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */ 2448 2449 #define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */ 2450 #define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */ 2451 2452 #define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */ 2453 #define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */ 2454 2455 #define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */ 2456 #define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */ 2457 2458 #define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */ 2459 #define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */ 2460 2461 #define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */ 2462 #define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */ 2463 2464 #define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */ 2465 #define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */ 2466 2467 #define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */ 2468 #define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */ 2469 2470 #define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */ 2471 #define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */ 2472 2473 #define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */ 2474 #define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */ 2475 2476 #define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */ 2477 #define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */ 2478 2479 #define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */ 2480 #define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */ 2481 2482 #define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */ 2483 #define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */ 2484 2485 #define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */ 2486 #define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */ 2487 2488 #define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */ 2489 #define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */ 2490 2491 #define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */ 2492 #define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */ 2493 2494 #define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */ 2495 #define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */ 2496 2497 #define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */ 2498 #define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */ 2499 2500 #define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */ 2501 #define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */ 2502 2503 #define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */ 2504 #define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */ 2505 2506 #define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */ 2507 #define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */ 2508 2509 #define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */ 2510 #define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */ 2511 2512 #define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */ 2513 #define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */ 2514 2515 #define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */ 2516 #define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */ 2517 2518 #define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */ 2519 #define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */ 2520 2521 #define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */ 2522 #define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */ 2523 2524 #define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */ 2525 #define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */ 2526 2527 #define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */ 2528 #define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */ 2529 2530 #define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */ 2531 #define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */ 2532 2533 #define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */ 2534 #define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */ 2535 2536 #define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */ 2537 #define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */ 2538 2539 #define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */ 2540 #define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */ 2541 2542 #define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */ 2543 #define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */ 2544 2545 #define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */ 2546 #define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */ 2547 2548 #define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */ 2549 #define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */ 2550 2551 #define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */ 2552 #define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */ 2553 2554 #define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */ 2555 #define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */ 2556 2557 #define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */ 2558 #define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */ 2559 2560 #define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */ 2561 #define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */ 2562 2563 #define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */ 2564 #define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */ 2565 2566 #define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */ 2567 #define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */ 2568 2569 #define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */ 2570 #define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */ 2571 2572 #define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */ 2573 #define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */ 2574 2575 #define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */ 2576 #define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */ 2577 2578 #define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */ 2579 #define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */ 2580 2581 #define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */ 2582 #define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */ 2583 2584 #define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */ 2585 #define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */ 2586 2587 #define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */ 2588 #define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */ 2589 2590 #define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */ 2591 #define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */ 2592 2593 #define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */ 2594 #define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */ 2595 2596 #define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */ 2597 #define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */ 2598 2599 #define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */ 2600 #define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */ 2601 2602 #define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */ 2603 #define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */ 2604 2605 #define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */ 2606 #define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */ 2607 2608 #define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */ 2609 #define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */ 2610 2611 #define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */ 2612 #define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */ 2613 2614 #define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */ 2615 #define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */ 2616 2617 #define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */ 2618 #define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */ 2619 2620 #define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */ 2621 #define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */ 2622 2623 #define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */ 2624 #define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */ 2625 2626 #define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */ 2627 #define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */ 2628 2629 #define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */ 2630 #define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */ 2631 2632 #define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */ 2633 #define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */ 2634 2635 #define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */ 2636 #define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */ 2637 2638 #define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */ 2639 #define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */ 2640 2641 #define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */ 2642 #define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */ 2643 2644 #define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */ 2645 #define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */ 2646 2647 #define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */ 2648 #define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */ 2649 2650 #define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */ 2651 #define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */ 2652 2653 #define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */ 2654 #define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */ 2655 2656 #define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */ 2657 #define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */ 2658 2659 #define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */ 2660 #define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */ 2661 2662 #define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */ 2663 #define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */ 2664 2665 #define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */ 2666 #define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */ 2667 2668 #define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */ 2669 #define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */ 2670 2671 #define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */ 2672 #define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */ 2673 2674 #define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */ 2675 #define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */ 2676 2677 #define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */ 2678 #define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */ 2679 2680 #define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */ 2681 #define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */ 2682 2683 #define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */ 2684 #define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */ 2685 2686 #define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */ 2687 #define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */ 2688 2689 #define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */ 2690 #define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */ 2691 2692 #define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */ 2693 #define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */ 2694 2695 #define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */ 2696 #define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */ 2697 2698 #define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */ 2699 #define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */ 2700 2701 #define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */ 2702 #define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */ 2703 2704 #define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */ 2705 #define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */ 2706 2707 #define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */ 2708 #define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */ 2709 2710 #define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */ 2711 #define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */ 2712 2713 #define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */ 2714 #define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */ 2715 2716 #define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */ 2717 #define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */ 2718 2719 #define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */ 2720 #define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */ 2721 2722 #define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */ 2723 #define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */ 2724 2725 #define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */ 2726 #define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */ 2727 2728 #define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */ 2729 #define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */ 2730 2731 #define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */ 2732 #define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */ 2733 2734 #define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */ 2735 #define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */ 2736 2737 #define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */ 2738 #define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */ 2739 2740 #define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */ 2741 #define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */ 2742 2743 #define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */ 2744 #define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */ 2745 2746 #define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */ 2747 #define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */ 2748 2749 #define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */ 2750 #define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */ 2751 2752 #define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */ 2753 #define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */ 2754 2755 #define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */ 2756 #define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */ 2757 2758 #define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */ 2759 #define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */ 2760 2761 #define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */ 2762 #define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */ 2763 2764 #define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */ 2765 #define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */ 2766 2767 #define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */ 2768 #define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */ 2769 2770 #define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */ 2771 #define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */ 2772 2773 #define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */ 2774 #define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */ 2775 2776 #define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */ 2777 #define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */ 2778 2779 #define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */ 2780 #define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */ 2781 2782 #define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */ 2783 #define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */ 2784 2785 #define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */ 2786 #define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */ 2787 2788 #define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */ 2789 #define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */ 2790 2791 #define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */ 2792 #define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */ 2793 2794 #define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */ 2795 #define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */ 2796 2797 #define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */ 2798 #define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */ 2799 2800 #define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */ 2801 #define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */ 2802 2803 #define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */ 2804 #define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */ 2805 2806 #define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */ 2807 #define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */ 2808 2809 #define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */ 2810 #define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */ 2811 2812 #define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */ 2813 #define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */ 2814 2815 #define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */ 2816 #define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */ 2817 2818 #define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */ 2819 #define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */ 2820 2821 #define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */ 2822 #define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */ 2823 2824 #define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */ 2825 #define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */ 2826 2827 #define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */ 2828 #define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */ 2829 2830 #define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */ 2831 #define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */ 2832 2833 #define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */ 2834 #define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */ 2835 2836 #define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */ 2837 #define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */ 2838 2839 #define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */ 2840 #define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */ 2841 2842 #define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */ 2843 #define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */ 2844 2845 #define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */ 2846 #define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */ 2847 2848 #define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */ 2849 #define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */ 2850 2851 #define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */ 2852 #define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */ 2853 2854 #define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */ 2855 #define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */ 2856 2857 #define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */ 2858 #define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */ 2859 2860 #define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */ 2861 #define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */ 2862 2863 #define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */ 2864 #define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */ 2865 2866 #define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */ 2867 #define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */ 2868 2869 #define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */ 2870 #define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */ 2871 2872 #define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */ 2873 #define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */ 2874 2875 #define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */ 2876 #define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */ 2877 2878 #define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */ 2879 #define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */ 2880 2881 #define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */ 2882 #define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */ 2883 2884 #define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */ 2885 #define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */ 2886 2887 #define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */ 2888 #define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */ 2889 2890 #define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */ 2891 #define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */ 2892 2893 #define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */ 2894 #define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */ 2895 2896 #define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */ 2897 #define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */ 2898 2899 #define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */ 2900 #define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */ 2901 2902 #define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */ 2903 #define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */ 2904 2905 #define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */ 2906 #define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */ 2907 2908 #define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */ 2909 #define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */ 2910 2911 #define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */ 2912 #define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */ 2913 2914 #define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */ 2915 #define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */ 2916 2917 #define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */ 2918 #define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */ 2919 2920 #define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */ 2921 #define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */ 2922 2923 #define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */ 2924 #define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */ 2925 2926 #define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */ 2927 #define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */ 2928 2929 #define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */ 2930 #define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */ 2931 2932 #define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */ 2933 #define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */ 2934 2935 #define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */ 2936 #define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */ 2937 2938 #define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */ 2939 #define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */ 2940 2941 #define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */ 2942 #define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */ 2943 2944 #define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */ 2945 #define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */ 2946 2947 #define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */ 2948 #define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */ 2949 2950 #define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */ 2951 #define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */ 2952 2953 #define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */ 2954 #define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */ 2955 2956 #define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */ 2957 #define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */ 2958 2959 #define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */ 2960 #define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */ 2961 2962 #define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */ 2963 #define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */ 2964 2965 #define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */ 2966 #define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */ 2967 2968 #define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */ 2969 #define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */ 2970 2971 #define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */ 2972 #define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */ 2973 2974 #define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */ 2975 #define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */ 2976 2977 #define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */ 2978 #define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */ 2979 2980 #define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */ 2981 #define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */ 2982 2983 #define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */ 2984 #define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */ 2985 2986 #define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */ 2987 #define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */ 2988 2989 #define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */ 2990 #define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */ 2991 2992 #define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */ 2993 #define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */ 2994 2995 #define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */ 2996 #define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */ 2997 2998 #define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */ 2999 #define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */ 3000 3001 #define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */ 3002 #define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */ 3003 3004 #define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */ 3005 #define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */ 3006 3007 #define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */ 3008 #define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */ 3009 3010 #define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */ 3011 #define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */ 3012 3013 #define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */ 3014 #define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */ 3015 3016 #define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */ 3017 #define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */ 3018 3019 #define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */ 3020 #define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */ 3021 3022 #define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */ 3023 #define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */ 3024 3025 #define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */ 3026 #define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */ 3027 3028 #define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */ 3029 #define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */ 3030 3031 #define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */ 3032 #define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */ 3033 3034 #define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */ 3035 #define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */ 3036 3037 #define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */ 3038 #define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */ 3039 3040 #define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */ 3041 #define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */ 3042 3043 #define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */ 3044 #define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */ 3045 3046 #define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */ 3047 #define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */ 3048 3049 #define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */ 3050 #define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */ 3051 3052 #define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */ 3053 #define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */ 3054 3055 #define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */ 3056 #define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */ 3057 3058 #define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */ 3059 #define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */ 3060 3061 #define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */ 3062 #define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */ 3063 3064 #define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */ 3065 #define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */ 3066 3067 #define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */ 3068 #define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */ 3069 3070 #define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */ 3071 #define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */ 3072 3073 #define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */ 3074 #define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */ 3075 3076 #define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */ 3077 #define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */ 3078 3079 #define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */ 3080 #define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */ 3081 3082 #define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */ 3083 #define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */ 3084 3085 #define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */ 3086 #define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */ 3087 3088 #define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */ 3089 #define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */ 3090 3091 #define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */ 3092 #define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */ 3093 3094 #define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */ 3095 #define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */ 3096 3097 #define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */ 3098 #define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */ 3099 3100 #define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */ 3101 #define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */ 3102 3103 #define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */ 3104 #define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */ 3105 3106 #define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */ 3107 #define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */ 3108 3109 #define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */ 3110 #define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */ 3111 3112 #define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */ 3113 #define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */ 3114 3115 #define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */ 3116 #define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */ 3117 3118 #define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */ 3119 #define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */ 3120 3121 #define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */ 3122 #define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */ 3123 3124 #define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */ 3125 #define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */ 3126 3127 #define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */ 3128 #define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */ 3129 3130 #define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */ 3131 #define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */ 3132 3133 #define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */ 3134 #define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */ 3135 3136 #define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */ 3137 #define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */ 3138 3139 #define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */ 3140 #define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */ 3141 3142 #define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */ 3143 #define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */ 3144 3145 #define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */ 3146 #define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */ 3147 3148 #define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */ 3149 #define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */ 3150 3151 #define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */ 3152 #define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */ 3153 3154 #define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */ 3155 #define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */ 3156 3157 #define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */ 3158 #define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */ 3159 3160 #define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */ 3161 #define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */ 3162 3163 #define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */ 3164 #define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */ 3165 3166 #define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */ 3167 #define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */ 3168 3169 #define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */ 3170 #define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */ 3171 3172 #define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */ 3173 #define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */ 3174 3175 #define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */ 3176 #define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */ 3177 3178 #define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */ 3179 #define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */ 3180 3181 #define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */ 3182 #define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */ 3183 3184 #define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */ 3185 #define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */ 3186 3187 #define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */ 3188 #define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */ 3189 3190 #define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */ 3191 #define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */ 3192 3193 #define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */ 3194 #define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */ 3195 3196 #define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */ 3197 #define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */ 3198 3199 #define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */ 3200 #define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */ 3201 3202 #define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */ 3203 #define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */ 3204 3205 #define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */ 3206 #define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */ 3207 3208 #define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */ 3209 #define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */ 3210 3211 #define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */ 3212 #define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */ 3213 3214 #define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */ 3215 #define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */ 3216 3217 #define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */ 3218 #define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */ 3219 3220 #define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */ 3221 #define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */ 3222 3223 #define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */ 3224 #define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */ 3225 3226 #define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */ 3227 #define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */ 3228 3229 #define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */ 3230 #define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */ 3231 3232 #define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */ 3233 #define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */ 3234 3235 #define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */ 3236 #define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */ 3237 3238 #define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */ 3239 #define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */ 3240 3241 #define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */ 3242 #define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */ 3243 3244 #define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */ 3245 #define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */ 3246 3247 #define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */ 3248 #define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */ 3249 3250 #define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */ 3251 #define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */ 3252 3253 #define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */ 3254 #define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */ 3255 3256 #define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */ 3257 #define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */ 3258 3259 #define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */ 3260 #define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */ 3261 3262 #define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */ 3263 #define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */ 3264 3265 #define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */ 3266 #define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */ 3267 3268 #define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */ 3269 #define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */ 3270 3271 #define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */ 3272 #define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */ 3273 3274 #define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */ 3275 #define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */ 3276 3277 #define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */ 3278 #define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */ 3279 3280 #define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */ 3281 #define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */ 3282 3283 #define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */ 3284 #define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */ 3285 3286 #define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */ 3287 #define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */ 3288 3289 #define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */ 3290 #define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */ 3291 3292 #define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */ 3293 #define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */ 3294 3295 #define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */ 3296 #define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */ 3297 3298 #define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */ 3299 #define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */ 3300 3301 #define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */ 3302 #define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */ 3303 3304 #define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */ 3305 #define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */ 3306 3307 #define EPWM_IFA0_STPMOD_Pos (24) /*!< EPWM_T::IFA0: STPMOD Position */ 3308 #define EPWM_IFA0_STPMOD_Msk (0x1ul << EPWM_IFA0_STPMOD_Pos) /*!< EPWM_T::IFA0: STPMOD Mask */ 3309 3310 #define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */ 3311 #define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */ 3312 3313 #define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */ 3314 #define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */ 3315 3316 #define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */ 3317 #define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */ 3318 3319 #define EPWM_IFA1_STPMOD_Pos (24) /*!< EPWM_T::IFA1: STPMOD Position */ 3320 #define EPWM_IFA1_STPMOD_Msk (0x1ul << EPWM_IFA1_STPMOD_Pos) /*!< EPWM_T::IFA1: STPMOD Mask */ 3321 3322 #define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */ 3323 #define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */ 3324 3325 #define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */ 3326 #define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */ 3327 3328 #define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */ 3329 #define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */ 3330 3331 #define EPWM_IFA2_STPMOD_Pos (24) /*!< EPWM_T::IFA2: STPMOD Position */ 3332 #define EPWM_IFA2_STPMOD_Msk (0x1ul << EPWM_IFA2_STPMOD_Pos) /*!< EPWM_T::IFA2: STPMOD Mask */ 3333 3334 #define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */ 3335 #define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */ 3336 3337 #define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */ 3338 #define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */ 3339 3340 #define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */ 3341 #define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */ 3342 3343 #define EPWM_IFA3_STPMOD_Pos (24) /*!< EPWM_T::IFA3: STPMOD Position */ 3344 #define EPWM_IFA3_STPMOD_Msk (0x1ul << EPWM_IFA3_STPMOD_Pos) /*!< EPWM_T::IFA3: STPMOD Mask */ 3345 3346 #define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */ 3347 #define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */ 3348 3349 #define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */ 3350 #define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */ 3351 3352 #define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */ 3353 #define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */ 3354 3355 #define EPWM_IFA4_STPMOD_Pos (24) /*!< EPWM_T::IFA4: STPMOD Position */ 3356 #define EPWM_IFA4_STPMOD_Msk (0x1ul << EPWM_IFA4_STPMOD_Pos) /*!< EPWM_T::IFA4: STPMOD Mask */ 3357 3358 #define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */ 3359 #define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */ 3360 3361 #define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */ 3362 #define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */ 3363 3364 #define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */ 3365 #define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */ 3366 3367 #define EPWM_IFA5_STPMOD_Pos (24) /*!< EPWM_T::IFA5: STPMOD Position */ 3368 #define EPWM_IFA5_STPMOD_Msk (0x1ul << EPWM_IFA5_STPMOD_Pos) /*!< EPWM_T::IFA5: STPMOD Mask */ 3369 3370 #define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */ 3371 #define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */ 3372 3373 #define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */ 3374 #define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */ 3375 3376 #define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */ 3377 #define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */ 3378 3379 #define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */ 3380 #define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */ 3381 3382 #define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */ 3383 #define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */ 3384 3385 #define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */ 3386 #define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */ 3387 3388 #define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */ 3389 #define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */ 3390 3391 #define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */ 3392 #define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */ 3393 3394 #define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */ 3395 #define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */ 3396 3397 #define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */ 3398 #define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */ 3399 3400 #define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */ 3401 #define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */ 3402 3403 #define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */ 3404 #define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */ 3405 3406 #define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */ 3407 #define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */ 3408 3409 #define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */ 3410 #define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */ 3411 3412 #define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */ 3413 #define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */ 3414 3415 #define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */ 3416 #define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */ 3417 3418 #define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */ 3419 #define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */ 3420 3421 #define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */ 3422 #define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */ 3423 3424 #define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */ 3425 #define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */ 3426 3427 #define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */ 3428 #define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */ 3429 3430 #define EPWM_FDEN_FDEN0_Pos (0) /*!< EPWM_T::FDEN: FDEN0 Position */ 3431 #define EPWM_FDEN_FDEN0_Msk (0x1ul << EPWM_FDEN_FDEN0_Pos) /*!< EPWM_T::FDEN: FDEN0 Mask */ 3432 3433 #define EPWM_FDEN_FDEN1_Pos (1) /*!< EPWM_T::FDEN: FDEN1 Position */ 3434 #define EPWM_FDEN_FDEN1_Msk (0x1ul << EPWM_FDEN_FDEN1_Pos) /*!< EPWM_T::FDEN: FDEN1 Mask */ 3435 3436 #define EPWM_FDEN_FDEN2_Pos (2) /*!< EPWM_T::FDEN: FDEN2 Position */ 3437 #define EPWM_FDEN_FDEN2_Msk (0x1ul << EPWM_FDEN_FDEN2_Pos) /*!< EPWM_T::FDEN: FDEN2 Mask */ 3438 3439 #define EPWM_FDEN_FDEN3_Pos (3) /*!< EPWM_T::FDEN: FDEN3 Position */ 3440 #define EPWM_FDEN_FDEN3_Msk (0x1ul << EPWM_FDEN_FDEN3_Pos) /*!< EPWM_T::FDEN: FDEN3 Mask */ 3441 3442 #define EPWM_FDEN_FDEN4_Pos (4) /*!< EPWM_T::FDEN: FDEN4 Position */ 3443 #define EPWM_FDEN_FDEN4_Msk (0x1ul << EPWM_FDEN_FDEN4_Pos) /*!< EPWM_T::FDEN: FDEN4 Mask */ 3444 3445 #define EPWM_FDEN_FDEN5_Pos (5) /*!< EPWM_T::FDEN: FDEN5 Position */ 3446 #define EPWM_FDEN_FDEN5_Msk (0x1ul << EPWM_FDEN_FDEN5_Pos) /*!< EPWM_T::FDEN: FDEN5 Mask */ 3447 3448 #define EPWM_FDEN_FDODIS0_Pos (8) /*!< EPWM_T::FDEN: FDODIS0 Position */ 3449 #define EPWM_FDEN_FDODIS0_Msk (0x1ul << EPWM_FDEN_FDODIS0_Pos) /*!< EPWM_T::FDEN: FDODIS0 Mask */ 3450 3451 #define EPWM_FDEN_FDODIS1_Pos (9) /*!< EPWM_T::FDEN: FDODIS1 Position */ 3452 #define EPWM_FDEN_FDODIS1_Msk (0x1ul << EPWM_FDEN_FDODIS1_Pos) /*!< EPWM_T::FDEN: FDODIS1 Mask */ 3453 3454 #define EPWM_FDEN_FDODIS2_Pos (10) /*!< EPWM_T::FDEN: FDODIS2 Position */ 3455 #define EPWM_FDEN_FDODIS2_Msk (0x1ul << EPWM_FDEN_FDODIS2_Pos) /*!< EPWM_T::FDEN: FDODIS2 Mask */ 3456 3457 #define EPWM_FDEN_FDODIS3_Pos (11) /*!< EPWM_T::FDEN: FDODIS3 Position */ 3458 #define EPWM_FDEN_FDODIS3_Msk (0x1ul << EPWM_FDEN_FDODIS3_Pos) /*!< EPWM_T::FDEN: FDODIS3 Mask */ 3459 3460 #define EPWM_FDEN_FDODIS4_Pos (12) /*!< EPWM_T::FDEN: FDODIS4 Position */ 3461 #define EPWM_FDEN_FDODIS4_Msk (0x1ul << EPWM_FDEN_FDODIS4_Pos) /*!< EPWM_T::FDEN: FDODIS4 Mask */ 3462 3463 #define EPWM_FDEN_FDODIS5_Pos (13) /*!< EPWM_T::FDEN: FDODIS5 Position */ 3464 #define EPWM_FDEN_FDODIS5_Msk (0x1ul << EPWM_FDEN_FDODIS5_Pos) /*!< EPWM_T::FDEN: FDODIS5 Mask */ 3465 3466 #define EPWM_FDEN_FDCKS0_Pos (16) /*!< EPWM_T::FDEN: FDCKS0 Position */ 3467 #define EPWM_FDEN_FDCKS0_Msk (0x1ul << EPWM_FDEN_FDCKS0_Pos) /*!< EPWM_T::FDEN: FDCKS0 Mask */ 3468 3469 #define EPWM_FDEN_FDCKS1_Pos (17) /*!< EPWM_T::FDEN: FDCKS1 Position */ 3470 #define EPWM_FDEN_FDCKS1_Msk (0x1ul << EPWM_FDEN_FDCKS1_Pos) /*!< EPWM_T::FDEN: FDCKS1 Mask */ 3471 3472 #define EPWM_FDEN_FDCKS2_Pos (18) /*!< EPWM_T::FDEN: FDCKS2 Position */ 3473 #define EPWM_FDEN_FDCKS2_Msk (0x1ul << EPWM_FDEN_FDCKS2_Pos) /*!< EPWM_T::FDEN: FDCKS2 Mask */ 3474 3475 #define EPWM_FDEN_FDCKS3_Pos (19) /*!< EPWM_T::FDEN: FDCKS3 Position */ 3476 #define EPWM_FDEN_FDCKS3_Msk (0x1ul << EPWM_FDEN_FDCKS3_Pos) /*!< EPWM_T::FDEN: FDCKS3 Mask */ 3477 3478 #define EPWM_FDEN_FDCKS4_Pos (20) /*!< EPWM_T::FDEN: FDCKS4 Position */ 3479 #define EPWM_FDEN_FDCKS4_Msk (0x1ul << EPWM_FDEN_FDCKS4_Pos) /*!< EPWM_T::FDEN: FDCKS4 Mask */ 3480 3481 #define EPWM_FDEN_FDCKS5_Pos (21) /*!< EPWM_T::FDEN: FDCKS5 Position */ 3482 #define EPWM_FDEN_FDCKS5_Msk (0x1ul << EPWM_FDEN_FDCKS5_Pos) /*!< EPWM_T::FDEN: FDCKS5 Mask */ 3483 3484 #define EPWM_FDCTL0_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL0: TRMSKCNT Position */ 3485 #define EPWM_FDCTL0_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL0_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL0: TRMSKCNT Mask */ 3486 3487 #define EPWM_FDCTL0_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL0: FDMSKEN Position */ 3488 #define EPWM_FDCTL0_FDMSKEN_Msk (0x1ul << EPWM_FDCTL0_FDMSKEN_Pos) /*!< EPWM_T::FDCTL0: FDMSKEN Mask */ 3489 3490 #define EPWM_FDCTL0_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL0: DGSMPCYC Position */ 3491 #define EPWM_FDCTL0_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL0_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL0: DGSMPCYC Mask */ 3492 3493 #define EPWM_FDCTL0_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL0: FDCKSEL Position */ 3494 #define EPWM_FDCTL0_FDCKSEL_Msk (0x3ul << EPWM_FDCTL0_FDCKSEL_Pos) /*!< EPWM_T::FDCTL0: FDCKSEL Mask */ 3495 3496 #define EPWM_FDCTL0_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL0: FDDGEN Position */ 3497 #define EPWM_FDCTL0_FDDGEN_Msk (0x1ul << EPWM_FDCTL0_FDDGEN_Pos) /*!< EPWM_T::FDCTL0: FDDGEN Mask */ 3498 3499 #define EPWM_FDCTL1_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL1: TRMSKCNT Position */ 3500 #define EPWM_FDCTL1_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL1_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL1: TRMSKCNT Mask */ 3501 3502 #define EPWM_FDCTL1_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL1: FDMSKEN Position */ 3503 #define EPWM_FDCTL1_FDMSKEN_Msk (0x1ul << EPWM_FDCTL1_FDMSKEN_Pos) /*!< EPWM_T::FDCTL1: FDMSKEN Mask */ 3504 3505 #define EPWM_FDCTL1_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL1: DGSMPCYC Position */ 3506 #define EPWM_FDCTL1_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL1_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL1: DGSMPCYC Mask */ 3507 3508 #define EPWM_FDCTL1_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL1: FDCKSEL Position */ 3509 #define EPWM_FDCTL1_FDCKSEL_Msk (0x3ul << EPWM_FDCTL1_FDCKSEL_Pos) /*!< EPWM_T::FDCTL1: FDCKSEL Mask */ 3510 3511 #define EPWM_FDCTL1_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL1: FDDGEN Position */ 3512 #define EPWM_FDCTL1_FDDGEN_Msk (0x1ul << EPWM_FDCTL1_FDDGEN_Pos) /*!< EPWM_T::FDCTL1: FDDGEN Mask */ 3513 3514 #define EPWM_FDCTL2_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL2: TRMSKCNT Position */ 3515 #define EPWM_FDCTL2_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL2_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL2: TRMSKCNT Mask */ 3516 3517 #define EPWM_FDCTL2_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL2: FDMSKEN Position */ 3518 #define EPWM_FDCTL2_FDMSKEN_Msk (0x1ul << EPWM_FDCTL2_FDMSKEN_Pos) /*!< EPWM_T::FDCTL2: FDMSKEN Mask */ 3519 3520 #define EPWM_FDCTL2_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL2: DGSMPCYC Position */ 3521 #define EPWM_FDCTL2_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL2_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL2: DGSMPCYC Mask */ 3522 3523 #define EPWM_FDCTL2_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL2: FDCKSEL Position */ 3524 #define EPWM_FDCTL2_FDCKSEL_Msk (0x3ul << EPWM_FDCTL2_FDCKSEL_Pos) /*!< EPWM_T::FDCTL2: FDCKSEL Mask */ 3525 3526 #define EPWM_FDCTL2_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL2: FDDGEN Position */ 3527 #define EPWM_FDCTL2_FDDGEN_Msk (0x1ul << EPWM_FDCTL2_FDDGEN_Pos) /*!< EPWM_T::FDCTL2: FDDGEN Mask */ 3528 3529 #define EPWM_FDCTL3_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL3: TRMSKCNT Position */ 3530 #define EPWM_FDCTL3_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL3_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL3: TRMSKCNT Mask */ 3531 3532 #define EPWM_FDCTL3_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL3: FDMSKEN Position */ 3533 #define EPWM_FDCTL3_FDMSKEN_Msk (0x1ul << EPWM_FDCTL3_FDMSKEN_Pos) /*!< EPWM_T::FDCTL3: FDMSKEN Mask */ 3534 3535 #define EPWM_FDCTL3_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL3: DGSMPCYC Position */ 3536 #define EPWM_FDCTL3_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL3_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL3: DGSMPCYC Mask */ 3537 3538 #define EPWM_FDCTL3_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL3: FDCKSEL Position */ 3539 #define EPWM_FDCTL3_FDCKSEL_Msk (0x3ul << EPWM_FDCTL3_FDCKSEL_Pos) /*!< EPWM_T::FDCTL3: FDCKSEL Mask */ 3540 3541 #define EPWM_FDCTL3_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL3: FDDGEN Position */ 3542 #define EPWM_FDCTL3_FDDGEN_Msk (0x1ul << EPWM_FDCTL3_FDDGEN_Pos) /*!< EPWM_T::FDCTL3: FDDGEN Mask */ 3543 3544 #define EPWM_FDCTL4_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL4: TRMSKCNT Position */ 3545 #define EPWM_FDCTL4_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL4_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL4: TRMSKCNT Mask */ 3546 3547 #define EPWM_FDCTL4_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL4: FDMSKEN Position */ 3548 #define EPWM_FDCTL4_FDMSKEN_Msk (0x1ul << EPWM_FDCTL4_FDMSKEN_Pos) /*!< EPWM_T::FDCTL4: FDMSKEN Mask */ 3549 3550 #define EPWM_FDCTL4_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL4: DGSMPCYC Position */ 3551 #define EPWM_FDCTL4_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL4_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL4: DGSMPCYC Mask */ 3552 3553 #define EPWM_FDCTL4_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL4: FDCKSEL Position */ 3554 #define EPWM_FDCTL4_FDCKSEL_Msk (0x3ul << EPWM_FDCTL4_FDCKSEL_Pos) /*!< EPWM_T::FDCTL4: FDCKSEL Mask */ 3555 3556 #define EPWM_FDCTL4_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL4: FDDGEN Position */ 3557 #define EPWM_FDCTL4_FDDGEN_Msk (0x1ul << EPWM_FDCTL4_FDDGEN_Pos) /*!< EPWM_T::FDCTL4: FDDGEN Mask */ 3558 3559 #define EPWM_FDCTL5_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL5: TRMSKCNT Position */ 3560 #define EPWM_FDCTL5_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL5_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL5: TRMSKCNT Mask */ 3561 3562 #define EPWM_FDCTL5_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL5: FDMSKEN Position */ 3563 #define EPWM_FDCTL5_FDMSKEN_Msk (0x1ul << EPWM_FDCTL5_FDMSKEN_Pos) /*!< EPWM_T::FDCTL5: FDMSKEN Mask */ 3564 3565 #define EPWM_FDCTL5_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL5: DGSMPCYC Position */ 3566 #define EPWM_FDCTL5_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL5_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL5: DGSMPCYC Mask */ 3567 3568 #define EPWM_FDCTL5_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL5: FDCKSEL Position */ 3569 #define EPWM_FDCTL5_FDCKSEL_Msk (0x3ul << EPWM_FDCTL5_FDCKSEL_Pos) /*!< EPWM_T::FDCTL5: FDCKSEL Mask */ 3570 3571 #define EPWM_FDCTL5_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL5: FDDGEN Position */ 3572 #define EPWM_FDCTL5_FDDGEN_Msk (0x1ul << EPWM_FDCTL5_FDDGEN_Pos) /*!< EPWM_T::FDCTL5: FDDGEN Mask */ 3573 3574 #define EPWM_FDIEN_FDIEN0_Pos (0) /*!< EPWM_T::FDIEN: FDIEN0 Position */ 3575 #define EPWM_FDIEN_FDIEN0_Msk (0x1ul << EPWM_FDIEN_FDIEN0_Pos) /*!< EPWM_T::FDIEN: FDIEN0 Mask */ 3576 3577 #define EPWM_FDIEN_FDIEN1_Pos (1) /*!< EPWM_T::FDIEN: FDIEN1 Position */ 3578 #define EPWM_FDIEN_FDIEN1_Msk (0x1ul << EPWM_FDIEN_FDIEN1_Pos) /*!< EPWM_T::FDIEN: FDIEN1 Mask */ 3579 3580 #define EPWM_FDIEN_FDIEN2_Pos (2) /*!< EPWM_T::FDIEN: FDIEN2 Position */ 3581 #define EPWM_FDIEN_FDIEN2_Msk (0x1ul << EPWM_FDIEN_FDIEN2_Pos) /*!< EPWM_T::FDIEN: FDIEN2 Mask */ 3582 3583 #define EPWM_FDIEN_FDIEN3_Pos (3) /*!< EPWM_T::FDIEN: FDIEN3 Position */ 3584 #define EPWM_FDIEN_FDIEN3_Msk (0x1ul << EPWM_FDIEN_FDIEN3_Pos) /*!< EPWM_T::FDIEN: FDIEN3 Mask */ 3585 3586 #define EPWM_FDIEN_FDIEN4_Pos (4) /*!< EPWM_T::FDIEN: FDIEN4 Position */ 3587 #define EPWM_FDIEN_FDIEN4_Msk (0x1ul << EPWM_FDIEN_FDIEN4_Pos) /*!< EPWM_T::FDIEN: FDIEN4 Mask */ 3588 3589 #define EPWM_FDIEN_FDIEN5_Pos (5) /*!< EPWM_T::FDIEN: FDIEN5 Position */ 3590 #define EPWM_FDIEN_FDIEN5_Msk (0x1ul << EPWM_FDIEN_FDIEN5_Pos) /*!< EPWM_T::FDIEN: FDIEN5 Mask */ 3591 3592 #define EPWM_FDSTS_FDIF0_Pos (0) /*!< EPWM_T::FDSTS: FDIF0 Position */ 3593 #define EPWM_FDSTS_FDIF0_Msk (0x1ul << EPWM_FDSTS_FDIF0_Pos) /*!< EPWM_T::FDSTS: FDIF0 Mask */ 3594 3595 #define EPWM_FDSTS_FDIF1_Pos (1) /*!< EPWM_T::FDSTS: FDIF1 Position */ 3596 #define EPWM_FDSTS_FDIF1_Msk (0x1ul << EPWM_FDSTS_FDIF1_Pos) /*!< EPWM_T::FDSTS: FDIF1 Mask */ 3597 3598 #define EPWM_FDSTS_FDIF2_Pos (2) /*!< EPWM_T::FDSTS: FDIF2 Position */ 3599 #define EPWM_FDSTS_FDIF2_Msk (0x1ul << EPWM_FDSTS_FDIF2_Pos) /*!< EPWM_T::FDSTS: FDIF2 Mask */ 3600 3601 #define EPWM_FDSTS_FDIF3_Pos (3) /*!< EPWM_T::FDSTS: FDIF3 Position */ 3602 #define EPWM_FDSTS_FDIF3_Msk (0x1ul << EPWM_FDSTS_FDIF3_Pos) /*!< EPWM_T::FDSTS: FDIF3 Mask */ 3603 3604 #define EPWM_FDSTS_FDIF4_Pos (4) /*!< EPWM_T::FDSTS: FDIF4 Position */ 3605 #define EPWM_FDSTS_FDIF4_Msk (0x1ul << EPWM_FDSTS_FDIF4_Pos) /*!< EPWM_T::FDSTS: FDIF4 Mask */ 3606 3607 #define EPWM_FDSTS_FDIF5_Pos (5) /*!< EPWM_T::FDSTS: FDIF5 Position */ 3608 #define EPWM_FDSTS_FDIF5_Msk (0x1ul << EPWM_FDSTS_FDIF5_Pos) /*!< EPWM_T::FDSTS: FDIF5 Mask */ 3609 3610 #define EPWM_EADCPSCCTL_PSCEN0_Pos (0) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Position */ 3611 #define EPWM_EADCPSCCTL_PSCEN0_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN0_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Mask */ 3612 3613 #define EPWM_EADCPSCCTL_PSCEN1_Pos (1) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Position */ 3614 #define EPWM_EADCPSCCTL_PSCEN1_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN1_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Mask */ 3615 3616 #define EPWM_EADCPSCCTL_PSCEN2_Pos (2) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Position */ 3617 #define EPWM_EADCPSCCTL_PSCEN2_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN2_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Mask */ 3618 3619 #define EPWM_EADCPSCCTL_PSCEN3_Pos (3) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Position */ 3620 #define EPWM_EADCPSCCTL_PSCEN3_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN3_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Mask */ 3621 3622 #define EPWM_EADCPSCCTL_PSCEN4_Pos (4) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Position */ 3623 #define EPWM_EADCPSCCTL_PSCEN4_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN4_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Mask */ 3624 3625 #define EPWM_EADCPSCCTL_PSCEN5_Pos (5) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Position */ 3626 #define EPWM_EADCPSCCTL_PSCEN5_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN5_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Mask */ 3627 3628 #define EPWM_EADCPSC0_EADCPSC0_Pos (0) /*!< EPWM_T::EADCPSC0: EADCPSC0 Position */ 3629 #define EPWM_EADCPSC0_EADCPSC0_Msk (0xful << EPWM_EADCPSC0_EADCPSC0_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC0 Mask */ 3630 3631 #define EPWM_EADCPSC0_EADCPSC1_Pos (8) /*!< EPWM_T::EADCPSC0: EADCPSC1 Position */ 3632 #define EPWM_EADCPSC0_EADCPSC1_Msk (0xful << EPWM_EADCPSC0_EADCPSC1_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC1 Mask */ 3633 3634 #define EPWM_EADCPSC0_EADCPSC2_Pos (16) /*!< EPWM_T::EADCPSC0: EADCPSC2 Position */ 3635 #define EPWM_EADCPSC0_EADCPSC2_Msk (0xful << EPWM_EADCPSC0_EADCPSC2_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC2 Mask */ 3636 3637 #define EPWM_EADCPSC0_EADCPSC3_Pos (24) /*!< EPWM_T::EADCPSC0: EADCPSC3 Position */ 3638 #define EPWM_EADCPSC0_EADCPSC3_Msk (0xful << EPWM_EADCPSC0_EADCPSC3_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC3 Mask */ 3639 3640 #define EPWM_EADCPSC1_EADCPSC4_Pos (0) /*!< EPWM_T::EADCPSC1: EADCPSC4 Position */ 3641 #define EPWM_EADCPSC1_EADCPSC4_Msk (0xful << EPWM_EADCPSC1_EADCPSC4_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC4 Mask */ 3642 3643 #define EPWM_EADCPSC1_EADCPSC5_Pos (8) /*!< EPWM_T::EADCPSC1: EADCPSC5 Position */ 3644 #define EPWM_EADCPSC1_EADCPSC5_Msk (0xful << EPWM_EADCPSC1_EADCPSC5_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC5 Mask */ 3645 3646 #define EPWM_EADCPSCNT0_PSCNT0_Pos (0) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Position */ 3647 #define EPWM_EADCPSCNT0_PSCNT0_Msk (0xful << EPWM_EADCPSCNT0_PSCNT0_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Mask */ 3648 3649 #define EPWM_EADCPSCNT0_PSCNT1_Pos (8) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Position */ 3650 #define EPWM_EADCPSCNT0_PSCNT1_Msk (0xful << EPWM_EADCPSCNT0_PSCNT1_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Mask */ 3651 3652 #define EPWM_EADCPSCNT0_PSCNT2_Pos (16) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Position */ 3653 #define EPWM_EADCPSCNT0_PSCNT2_Msk (0xful << EPWM_EADCPSCNT0_PSCNT2_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Mask */ 3654 3655 #define EPWM_EADCPSCNT0_PSCNT3_Pos (24) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Position */ 3656 #define EPWM_EADCPSCNT0_PSCNT3_Msk (0xful << EPWM_EADCPSCNT0_PSCNT3_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Mask */ 3657 3658 #define EPWM_EADCPSCNT1_PSCNT4_Pos (0) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Position */ 3659 #define EPWM_EADCPSCNT1_PSCNT4_Msk (0xful << EPWM_EADCPSCNT1_PSCNT4_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Mask */ 3660 3661 #define EPWM_EADCPSCNT1_PSCNT5_Pos (8) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Position */ 3662 #define EPWM_EADCPSCNT1_PSCNT5_Msk (0xful << EPWM_EADCPSCNT1_PSCNT5_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Mask */ 3663 3664 #define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */ 3665 #define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */ 3666 3667 #define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */ 3668 #define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */ 3669 3670 #define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */ 3671 #define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */ 3672 3673 #define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */ 3674 #define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */ 3675 3676 #define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */ 3677 #define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */ 3678 3679 #define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */ 3680 #define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */ 3681 3682 #define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */ 3683 #define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */ 3684 3685 #define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */ 3686 #define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */ 3687 3688 #define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */ 3689 #define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */ 3690 3691 #define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */ 3692 #define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */ 3693 3694 #define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */ 3695 #define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */ 3696 3697 #define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */ 3698 #define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */ 3699 3700 #define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */ 3701 #define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */ 3702 3703 #define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */ 3704 #define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */ 3705 3706 #define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */ 3707 #define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */ 3708 3709 #define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */ 3710 #define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */ 3711 3712 #define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */ 3713 #define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */ 3714 3715 #define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */ 3716 #define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */ 3717 3718 #define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */ 3719 #define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */ 3720 3721 #define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */ 3722 #define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */ 3723 3724 #define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */ 3725 #define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */ 3726 3727 #define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */ 3728 #define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */ 3729 3730 #define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */ 3731 #define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */ 3732 3733 #define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */ 3734 #define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */ 3735 3736 #define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */ 3737 #define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */ 3738 3739 #define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */ 3740 #define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */ 3741 3742 #define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */ 3743 #define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */ 3744 3745 #define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */ 3746 #define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */ 3747 3748 #define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */ 3749 #define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */ 3750 3751 #define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */ 3752 #define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */ 3753 3754 #define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */ 3755 #define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */ 3756 3757 #define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */ 3758 #define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */ 3759 3760 #define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */ 3761 #define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */ 3762 3763 #define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */ 3764 #define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */ 3765 3766 #define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */ 3767 #define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */ 3768 3769 #define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */ 3770 #define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */ 3771 3772 #define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */ 3773 #define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */ 3774 3775 #define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */ 3776 #define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */ 3777 3778 #define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */ 3779 #define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */ 3780 3781 #define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */ 3782 #define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */ 3783 3784 #define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */ 3785 #define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */ 3786 3787 #define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */ 3788 #define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */ 3789 3790 #define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */ 3791 #define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */ 3792 3793 #define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */ 3794 #define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */ 3795 3796 #define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */ 3797 #define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */ 3798 3799 #define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */ 3800 #define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */ 3801 3802 #define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */ 3803 #define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */ 3804 3805 #define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */ 3806 #define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */ 3807 3808 #define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */ 3809 #define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */ 3810 3811 #define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */ 3812 #define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */ 3813 3814 #define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */ 3815 #define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */ 3816 3817 #define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */ 3818 #define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */ 3819 3820 #define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */ 3821 #define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */ 3822 3823 #define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */ 3824 #define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */ 3825 3826 #define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */ 3827 #define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */ 3828 3829 #define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */ 3830 #define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */ 3831 3832 #define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */ 3833 #define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */ 3834 3835 #define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */ 3836 #define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */ 3837 3838 #define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */ 3839 #define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */ 3840 3841 #define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */ 3842 #define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */ 3843 3844 #define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */ 3845 #define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */ 3846 3847 #define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */ 3848 #define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */ 3849 3850 #define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */ 3851 #define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */ 3852 3853 #define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */ 3854 #define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */ 3855 3856 #define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */ 3857 #define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */ 3858 3859 #define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */ 3860 #define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */ 3861 3862 #define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */ 3863 #define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */ 3864 3865 #define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */ 3866 #define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */ 3867 3868 #define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */ 3869 #define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */ 3870 3871 #define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */ 3872 #define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */ 3873 3874 #define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */ 3875 #define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */ 3876 3877 #define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */ 3878 #define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */ 3879 3880 #define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */ 3881 #define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */ 3882 3883 #define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */ 3884 #define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */ 3885 3886 #define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */ 3887 #define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */ 3888 3889 #define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */ 3890 #define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */ 3891 3892 #define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */ 3893 #define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */ 3894 3895 #define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */ 3896 #define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */ 3897 3898 #define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */ 3899 #define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */ 3900 3901 #define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */ 3902 #define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */ 3903 3904 #define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */ 3905 #define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */ 3906 3907 #define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */ 3908 #define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */ 3909 3910 #define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */ 3911 #define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */ 3912 3913 #define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */ 3914 #define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */ 3915 3916 #define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */ 3917 #define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */ 3918 3919 #define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */ 3920 #define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */ 3921 3922 #define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */ 3923 #define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */ 3924 3925 #define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */ 3926 #define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */ 3927 3928 #define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */ 3929 #define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */ 3930 3931 #define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */ 3932 #define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */ 3933 3934 #define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */ 3935 #define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */ 3936 3937 #define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */ 3938 #define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */ 3939 3940 #define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */ 3941 #define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */ 3942 3943 #define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */ 3944 #define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */ 3945 3946 #define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */ 3947 #define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */ 3948 3949 #define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */ 3950 #define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */ 3951 3952 #define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */ 3953 #define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */ 3954 3955 #define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */ 3956 #define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */ 3957 3958 #define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */ 3959 #define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */ 3960 3961 #define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */ 3962 #define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */ 3963 3964 #define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */ 3965 #define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */ 3966 3967 #define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */ 3968 #define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */ 3969 3970 #define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */ 3971 #define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */ 3972 3973 #define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */ 3974 #define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */ 3975 3976 #define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */ 3977 #define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */ 3978 3979 #define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */ 3980 #define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */ 3981 3982 #define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */ 3983 #define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */ 3984 3985 #define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */ 3986 #define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */ 3987 3988 #define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */ 3989 #define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */ 3990 3991 #define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */ 3992 #define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */ 3993 3994 #define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */ 3995 #define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */ 3996 3997 #define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */ 3998 #define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */ 3999 4000 #define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */ 4001 #define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */ 4002 4003 #define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */ 4004 #define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */ 4005 4006 #define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */ 4007 #define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */ 4008 4009 #define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */ 4010 #define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */ 4011 4012 #define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */ 4013 #define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */ 4014 4015 /**@}*/ /* EPWM_CONST */ 4016 /**@}*/ /* end of EPWM register group */ 4017 /**@}*/ /* end of REGISTER group */ 4018 4019 #if defined ( __CC_ARM ) 4020 #pragma no_anon_unions 4021 #endif 4022 4023 #endif /* __EPWM_REG_H__ */ 4024
