1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F3xx_LL_RCC_H
22 #define __STM32F3xx_LL_RCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f3xx.h"
30
31 /** @addtogroup STM32F3xx_LL_Driver
32 * @{
33 */
34
35 #if defined(RCC)
36
37 /** @defgroup RCC_LL RCC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
45 * @{
46 */
47 /* Defines used for the bit position in the register and perform offsets*/
48 #define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */
49 #define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */
50 #define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */
51 #define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */
52 #define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */
53 #define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /*!< field position in register RCC_CFGR */
54 #define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */
55 #define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */
56 #define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */
57 #define RCC_POSITION_TIM1SW (uint32_t)8U /*!< field position in register RCC_CFGR3 */
58 #define RCC_POSITION_TIM8SW (uint32_t)9U /*!< field position in register RCC_CFGR3 */
59 #define RCC_POSITION_TIM15SW (uint32_t)10U /*!< field position in register RCC_CFGR3 */
60 #define RCC_POSITION_TIM16SW (uint32_t)11U /*!< field position in register RCC_CFGR3 */
61 #define RCC_POSITION_TIM17SW (uint32_t)13U /*!< field position in register RCC_CFGR3 */
62 #define RCC_POSITION_TIM20SW (uint32_t)15U /*!< field position in register RCC_CFGR3 */
63 #define RCC_POSITION_TIM2SW (uint32_t)24U /*!< field position in register RCC_CFGR3 */
64 #define RCC_POSITION_TIM34SW (uint32_t)25U /*!< field position in register RCC_CFGR3 */
65
66 /**
67 * @}
68 */
69
70 /* Private macros ------------------------------------------------------------*/
71 #if defined(USE_FULL_LL_DRIVER)
72 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
73 * @{
74 */
75 /**
76 * @}
77 */
78 #endif /*USE_FULL_LL_DRIVER*/
79 /* Exported types ------------------------------------------------------------*/
80 #if defined(USE_FULL_LL_DRIVER)
81 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
82 * @{
83 */
84
85 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
86 * @{
87 */
88
89 /**
90 * @brief RCC Clocks Frequency Structure
91 */
92 typedef struct
93 {
94 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
95 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
96 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
97 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
98 } LL_RCC_ClocksTypeDef;
99
100 /**
101 * @}
102 */
103
104 /**
105 * @}
106 */
107 #endif /* USE_FULL_LL_DRIVER */
108
109 /* Exported constants --------------------------------------------------------*/
110 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
111 * @{
112 */
113
114 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
115 * @brief Defines used to adapt values of different oscillators
116 * @note These values could be modified in the user environment according to
117 * HW set-up.
118 * @{
119 */
120 #if !defined (HSE_VALUE)
121 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
122 #endif /* HSE_VALUE */
123
124 #if !defined (HSI_VALUE)
125 #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
126 #endif /* HSI_VALUE */
127
128 #if !defined (LSE_VALUE)
129 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
130 #endif /* LSE_VALUE */
131
132 #if !defined (LSI_VALUE)
133 #define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */
134 #endif /* LSI_VALUE */
135
136 #if !defined (EXTERNAL_CLOCK_VALUE)
137 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
138 #endif /* EXTERNAL_CLOCK_VALUE */
139 /**
140 * @}
141 */
142
143 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
144 * @brief Flags defines which can be used with LL_RCC_WriteReg function
145 * @{
146 */
147 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
148 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
149 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
150 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
151 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
152 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
153 /**
154 * @}
155 */
156
157 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
158 * @brief Flags defines which can be used with LL_RCC_ReadReg function
159 * @{
160 */
161 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
162 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
163 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
164 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
165 #define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF /*!< MCO flag */
166 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
167 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
168 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
169 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
170 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
171 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
172 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
173 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
174 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
175 #if defined(RCC_CSR_V18PWRRSTF)
176 #define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */
177 #endif /* RCC_CSR_V18PWRRSTF */
178 /**
179 * @}
180 */
181
182 /** @defgroup RCC_LL_EC_IT IT Defines
183 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
184 * @{
185 */
186 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
187 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
188 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
189 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
190 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
191 /**
192 * @}
193 */
194
195 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
196 * @{
197 */
198 #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */
199 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
200 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
201 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
202 /**
203 * @}
204 */
205
206 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
207 * @{
208 */
209 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
210 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
211 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
212 /**
213 * @}
214 */
215
216 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
217 * @{
218 */
219 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
220 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
221 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
222 /**
223 * @}
224 */
225
226 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
227 * @{
228 */
229 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
230 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
231 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
232 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
233 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
234 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
235 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
236 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
237 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
238 /**
239 * @}
240 */
241
242 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
243 * @{
244 */
245 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
246 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
247 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
248 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
249 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
250 /**
251 * @}
252 */
253
254 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
255 * @{
256 */
257 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
258 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
259 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
260 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
261 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
262 /**
263 * @}
264 */
265
266 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
267 * @{
268 */
269 #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
270 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
271 #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
272 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
273 #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */
274 #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */
275 #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
276 #if defined(RCC_CFGR_PLLNODIV)
277 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/
278 #endif /* RCC_CFGR_PLLNODIV */
279 /**
280 * @}
281 */
282
283 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
284 * @{
285 */
286 #define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */
287 #if defined(RCC_CFGR_MCOPRE)
288 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
289 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */
290 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */
291 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
292 #define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */
293 #define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */
294 #define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */
295 #endif /* RCC_CFGR_MCOPRE */
296 /**
297 * @}
298 */
299
300 #if defined(USE_FULL_LL_DRIVER)
301 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
302 * @{
303 */
304 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
305 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
306 /**
307 * @}
308 */
309 #endif /* USE_FULL_LL_DRIVER */
310
311 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
312 * @{
313 */
314 #if defined(RCC_CFGR3_USART1SW_PCLK1)
315 #define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1) /*!< PCLK1 clock used as USART1 clock source */
316 #else
317 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2) /*!< PCLK2 clock used as USART1 clock source */
318 #endif /*RCC_CFGR3_USART1SW_PCLK1*/
319 #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */
320 #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */
321 #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */
322 #if defined(RCC_CFGR3_USART2SW)
323 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */
324 #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */
325 #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */
326 #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */
327 #endif /* RCC_CFGR3_USART2SW */
328 #if defined(RCC_CFGR3_USART3SW)
329 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */
330 #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */
331 #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */
332 #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */
333 #endif /* RCC_CFGR3_USART3SW */
334 /**
335 * @}
336 */
337
338 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
339 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
340 * @{
341 */
342 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK) /*!< PCLK1 clock used as UART4 clock source */
343 #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) /*!< System clock selected as UART4 clock source */
344 #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE) /*!< LSE oscillator clock used as UART4 clock source */
345 #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI) /*!< HSI oscillator clock used as UART4 clock source */
346 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK) /*!< PCLK1 clock used as UART5 clock source */
347 #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) /*!< System clock selected as UART5 clock source */
348 #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE) /*!< LSE oscillator clock used as UART5 clock source */
349 #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI) /*!< HSI oscillator clock used as UART5 clock source */
350 /**
351 * @}
352 */
353
354 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
355
356 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
357 * @{
358 */
359 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI) /*!< HSI oscillator clock used as I2C1 clock source */
360 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) /*!< System clock selected as I2C1 clock source */
361 #if defined(RCC_CFGR3_I2C2SW)
362 #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI) /*!< HSI oscillator clock used as I2C2 clock source */
363 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) /*!< System clock selected as I2C2 clock source */
364 #endif /*RCC_CFGR3_I2C2SW*/
365 #if defined(RCC_CFGR3_I2C3SW)
366 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI) /*!< HSI oscillator clock used as I2C3 clock source */
367 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) /*!< System clock selected as I2C3 clock source */
368 #endif /*RCC_CFGR3_I2C3SW*/
369 /**
370 * @}
371 */
372
373 #if defined(RCC_CFGR_I2SSRC)
374 /** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
375 * @{
376 */
377 #define LL_RCC_I2S_CLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK /*!< System clock selected as I2S clock source */
378 #define LL_RCC_I2S_CLKSOURCE_PIN RCC_CFGR_I2SSRC_EXT /*!< External clock selected as I2S clock source */
379 /**
380 * @}
381 */
382
383 #endif /* RCC_CFGR_I2SSRC */
384
385 #if defined(RCC_CFGR3_TIMSW)
386 /** @defgroup RCC_LL_EC_TIM1_CLKSOURCE Peripheral TIM clock source selection
387 * @{
388 */
389 #define LL_RCC_TIM1_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2) /*!< PCLK2 used as TIM1 clock source */
390 #define LL_RCC_TIM1_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL) /*!< PLL clock used as TIM1 clock source */
391 #if defined(RCC_CFGR3_TIM8SW)
392 #define LL_RCC_TIM8_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2) /*!< PCLK2 used as TIM8 clock source */
393 #define LL_RCC_TIM8_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL) /*!< PLL clock used as TIM8 clock source */
394 #endif /*RCC_CFGR3_TIM8SW*/
395 #if defined(RCC_CFGR3_TIM15SW)
396 #define LL_RCC_TIM15_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) /*!< PCLK2 used as TIM15 clock source */
397 #define LL_RCC_TIM15_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL) /*!< PLL clock used as TIM15 clock source */
398 #endif /*RCC_CFGR3_TIM15SW*/
399 #if defined(RCC_CFGR3_TIM16SW)
400 #define LL_RCC_TIM16_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) /*!< PCLK2 used as TIM16 clock source */
401 #define LL_RCC_TIM16_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL) /*!< PLL clock used as TIM16 clock source */
402 #endif /*RCC_CFGR3_TIM16SW*/
403 #if defined(RCC_CFGR3_TIM17SW)
404 #define LL_RCC_TIM17_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) /*!< PCLK2 used as TIM17 clock source */
405 #define LL_RCC_TIM17_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL) /*!< PLL clock used as TIM17 clock source */
406 #endif /*RCC_CFGR3_TIM17SW*/
407 #if defined(RCC_CFGR3_TIM20SW)
408 #define LL_RCC_TIM20_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) /*!< PCLK2 used as TIM20 clock source */
409 #define LL_RCC_TIM20_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL) /*!< PLL clock used as TIM20 clock source */
410 #endif /*RCC_CFGR3_TIM20SW*/
411 #if defined(RCC_CFGR3_TIM2SW)
412 #define LL_RCC_TIM2_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1) /*!< PCLK1 used as TIM2 clock source */
413 #define LL_RCC_TIM2_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL) /*!< PLL clock used as TIM2 clock source */
414 #endif /*RCC_CFGR3_TIM2SW*/
415 #if defined(RCC_CFGR3_TIM34SW)
416 #define LL_RCC_TIM34_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) /*!< PCLK1 used as TIM3/4 clock source */
417 #define LL_RCC_TIM34_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL) /*!< PLL clock used as TIM3/4 clock source */
418 #endif /*RCC_CFGR3_TIM34SW*/
419 /**
420 * @}
421 */
422
423 #endif /* RCC_CFGR3_TIMSW */
424
425 #if defined(HRTIM1)
426 /** @defgroup RCC_LL_EC_HRTIM1_CLKSOURCE Peripheral HRTIM1 clock source selection
427 * @{
428 */
429 #define LL_RCC_HRTIM1_CLKSOURCE_PCLK2 RCC_CFGR3_HRTIM1SW_PCLK2 /*!< PCLK2 used as HRTIM1 clock source */
430 #define LL_RCC_HRTIM1_CLKSOURCE_PLL RCC_CFGR3_HRTIM1SW_PLL /*!< PLL clock used as HRTIM1 clock source */
431 /**
432 * @}
433 */
434
435 #endif /* HRTIM1 */
436
437 #if defined(CEC)
438 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
439 * @{
440 */
441 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
442 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */
443 /**
444 * @}
445 */
446
447 #endif /* CEC */
448
449 #if defined(USB)
450 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
451 * @{
452 */
453 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 /*!< USB prescaler is PLL clock divided by 1 */
454 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5 /*!< USB prescaler is PLL clock divided by 1.5 */
455 /**
456 * @}
457 */
458
459 #endif /* USB */
460
461 #if defined(RCC_CFGR_ADCPRE)
462 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
463 * @{
464 */
465 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*!< ADC prescaler PCLK divided by 2 */
466 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*!< ADC prescaler PCLK divided by 4 */
467 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*!< ADC prescaler PCLK divided by 6 */
468 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*!< ADC prescaler PCLK divided by 8 */
469 /**
470 * @}
471 */
472
473 #elif defined(RCC_CFGR2_ADC1PRES)
474 /** @defgroup RCC_LL_EC_ADC1_CLKSOURCE Peripheral ADC clock source selection
475 * @{
476 */
477 #define LL_RCC_ADC1_CLKSRC_HCLK RCC_CFGR2_ADC1PRES_NO /*!< ADC1 clock disabled, ADC1 can use AHB clock */
478 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADC1PRES_DIV1 /*!< ADC1 PLL clock divided by 1 */
479 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADC1PRES_DIV2 /*!< ADC1 PLL clock divided by 2 */
480 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADC1PRES_DIV4 /*!< ADC1 PLL clock divided by 4 */
481 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADC1PRES_DIV6 /*!< ADC1 PLL clock divided by 6 */
482 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADC1PRES_DIV8 /*!< ADC1 PLL clock divided by 8 */
483 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADC1PRES_DIV10 /*!< ADC1 PLL clock divided by 10 */
484 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADC1PRES_DIV12 /*!< ADC1 PLL clock divided by 12 */
485 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADC1PRES_DIV16 /*!< ADC1 PLL clock divided by 16 */
486 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADC1PRES_DIV32 /*!< ADC1 PLL clock divided by 32 */
487 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADC1PRES_DIV64 /*!< ADC1 PLL clock divided by 64 */
488 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADC1PRES_DIV128 /*!< ADC1 PLL clock divided by 128 */
489 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADC1PRES_DIV256 /*!< ADC1 PLL clock divided by 256 */
490 /**
491 * @}
492 */
493
494 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
495 #if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
496 /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC12 clock source selection
497 * @{
498 */
499 #define LL_RCC_ADC12_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
500 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1) /*!< ADC12 PLL clock divided by 1 */
501 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2) /*!< ADC12 PLL clock divided by 2 */
502 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4) /*!< ADC12 PLL clock divided by 4 */
503 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6) /*!< ADC12 PLL clock divided by 6 */
504 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8) /*!< ADC12 PLL clock divided by 8 */
505 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10) /*!< ADC12 PLL clock divided by 10 */
506 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12) /*!< ADC12 PLL clock divided by 12 */
507 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16) /*!< ADC12 PLL clock divided by 16 */
508 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32) /*!< ADC12 PLL clock divided by 32 */
509 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64) /*!< ADC12 PLL clock divided by 64 */
510 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) /*!< ADC12 PLL clock divided by 128 */
511 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) /*!< ADC12 PLL clock divided by 256 */
512 /**
513 * @}
514 */
515
516 /** @defgroup RCC_LL_EC_ADC34_CLKSOURCE Peripheral ADC34 clock source selection
517 * @{
518 */
519 #define LL_RCC_ADC34_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
520 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1) /*!< ADC34 PLL clock divided by 1 */
521 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2) /*!< ADC34 PLL clock divided by 2 */
522 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4) /*!< ADC34 PLL clock divided by 4 */
523 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6) /*!< ADC34 PLL clock divided by 6 */
524 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8) /*!< ADC34 PLL clock divided by 8 */
525 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10) /*!< ADC34 PLL clock divided by 10 */
526 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12) /*!< ADC34 PLL clock divided by 12 */
527 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16) /*!< ADC34 PLL clock divided by 16 */
528 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32) /*!< ADC34 PLL clock divided by 32 */
529 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64) /*!< ADC34 PLL clock divided by 64 */
530 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) /*!< ADC34 PLL clock divided by 128 */
531 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) /*!< ADC34 PLL clock divided by 256 */
532 /**
533 * @}
534 */
535
536 #else
537 /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC clock source selection
538 * @{
539 */
540 #define LL_RCC_ADC12_CLKSRC_HCLK RCC_CFGR2_ADCPRE12_NO /*!< ADC12 clock disabled, ADC12 can use AHB clock */
541 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADCPRE12_DIV1 /*!< ADC12 PLL clock divided by 1 */
542 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADCPRE12_DIV2 /*!< ADC12 PLL clock divided by 2 */
543 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADCPRE12_DIV4 /*!< ADC12 PLL clock divided by 4 */
544 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADCPRE12_DIV6 /*!< ADC12 PLL clock divided by 6 */
545 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADCPRE12_DIV8 /*!< ADC12 PLL clock divided by 8 */
546 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADCPRE12_DIV10 /*!< ADC12 PLL clock divided by 10 */
547 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADCPRE12_DIV12 /*!< ADC12 PLL clock divided by 12 */
548 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADCPRE12_DIV16 /*!< ADC12 PLL clock divided by 16 */
549 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADCPRE12_DIV32 /*!< ADC12 PLL clock divided by 32 */
550 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADCPRE12_DIV64 /*!< ADC12 PLL clock divided by 64 */
551 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADCPRE12_DIV128 /*!< ADC12 PLL clock divided by 128 */
552 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADCPRE12_DIV256 /*!< ADC12 PLL clock divided by 256 */
553 /**
554 * @}
555 */
556
557 #endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */
558
559 #endif /* RCC_CFGR_ADCPRE */
560
561 #if defined(RCC_CFGR_SDPRE)
562 /** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection
563 * @{
564 */
565 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1 /*!< SDADC CLK not divided */
566 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2 /*!< SDADC CLK divided by 2 */
567 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4 /*!< SDADC CLK divided by 4 */
568 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6 /*!< SDADC CLK divided by 6 */
569 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8 /*!< SDADC CLK divided by 8 */
570 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10 /*!< SDADC CLK divided by 10 */
571 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12 /*!< SDADC CLK divided by 12 */
572 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14 /*!< SDADC CLK divided by 14 */
573 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16 /*!< SDADC CLK divided by 16 */
574 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20 /*!< SDADC CLK divided by 20 */
575 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24 /*!< SDADC CLK divided by 24 */
576 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28 /*!< SDADC CLK divided by 28 */
577 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32 /*!< SDADC CLK divided by 32 */
578 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36 /*!< SDADC CLK divided by 36 */
579 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40 /*!< SDADC CLK divided by 40 */
580 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44 /*!< SDADC CLK divided by 44 */
581 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48 /*!< SDADC CLK divided by 48 */
582 /**
583 * @}
584 */
585
586 #endif /* RCC_CFGR_SDPRE */
587
588 /** @defgroup RCC_LL_EC_USART Peripheral USART get clock source
589 * @{
590 */
591 #define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */
592 #if defined(RCC_CFGR3_USART2SW)
593 #define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */
594 #endif /* RCC_CFGR3_USART2SW */
595 #if defined(RCC_CFGR3_USART3SW)
596 #define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */
597 #endif /* RCC_CFGR3_USART3SW */
598 /**
599 * @}
600 */
601
602 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
603 /** @defgroup RCC_LL_EC_UART Peripheral UART get clock source
604 * @{
605 */
606 #define LL_RCC_UART4_CLKSOURCE RCC_CFGR3_UART4SW /*!< UART4 Clock source selection */
607 #define LL_RCC_UART5_CLKSOURCE RCC_CFGR3_UART5SW /*!< UART5 Clock source selection */
608 /**
609 * @}
610 */
611
612 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
613
614 /** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source
615 * @{
616 */
617 #define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */
618 #if defined(RCC_CFGR3_I2C2SW)
619 #define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW /*!< I2C2 Clock source selection */
620 #endif /*RCC_CFGR3_I2C2SW*/
621 #if defined(RCC_CFGR3_I2C3SW)
622 #define LL_RCC_I2C3_CLKSOURCE RCC_CFGR3_I2C3SW /*!< I2C3 Clock source selection */
623 #endif /*RCC_CFGR3_I2C3SW*/
624 /**
625 * @}
626 */
627
628 #if defined(RCC_CFGR_I2SSRC)
629 /** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
630 * @{
631 */
632 #define LL_RCC_I2S_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
633 /**
634 * @}
635 */
636
637 #endif /* RCC_CFGR_I2SSRC */
638
639 #if defined(RCC_CFGR3_TIMSW)
640 /** @defgroup RCC_LL_EC_TIM TIMx Peripheral TIM get clock source
641 * @{
642 */
643 #define LL_RCC_TIM1_CLKSOURCE (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) /*!< TIM1 Clock source selection */
644 #if defined(RCC_CFGR3_TIM2SW)
645 #define LL_RCC_TIM2_CLKSOURCE (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) /*!< TIM2 Clock source selection */
646 #endif /*RCC_CFGR3_TIM2SW*/
647 #if defined(RCC_CFGR3_TIM8SW)
648 #define LL_RCC_TIM8_CLKSOURCE (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) /*!< TIM8 Clock source selection */
649 #endif /*RCC_CFGR3_TIM8SW*/
650 #if defined(RCC_CFGR3_TIM15SW)
651 #define LL_RCC_TIM15_CLKSOURCE (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) /*!< TIM15 Clock source selection */
652 #endif /*RCC_CFGR3_TIM15SW*/
653 #if defined(RCC_CFGR3_TIM16SW)
654 #define LL_RCC_TIM16_CLKSOURCE (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) /*!< TIM16 Clock source selection */
655 #endif /*RCC_CFGR3_TIM16SW*/
656 #if defined(RCC_CFGR3_TIM17SW)
657 #define LL_RCC_TIM17_CLKSOURCE (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) /*!< TIM17 Clock source selection */
658 #endif /*RCC_CFGR3_TIM17SW*/
659 #if defined(RCC_CFGR3_TIM20SW)
660 #define LL_RCC_TIM20_CLKSOURCE (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) /*!< TIM20 Clock source selection */
661 #endif /*RCC_CFGR3_TIM20SW*/
662 #if defined(RCC_CFGR3_TIM34SW)
663 #define LL_RCC_TIM34_CLKSOURCE (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) /*!< TIM3/4 Clock source selection */
664 #endif /*RCC_CFGR3_TIM34SW*/
665 /**
666 * @}
667 */
668
669 #endif /* RCC_CFGR3_TIMSW */
670
671 #if defined(HRTIM1)
672 /** @defgroup RCC_LL_EC_HRTIM1 Peripheral HRTIM1 get clock source
673 * @{
674 */
675 #define LL_RCC_HRTIM1_CLKSOURCE RCC_CFGR3_HRTIM1SW /*!< HRTIM1 Clock source selection */
676 /**
677 * @}
678 */
679
680 #endif /* HRTIM1 */
681
682 #if defined(CEC)
683 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
684 * @{
685 */
686 #define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */
687 /**
688 * @}
689 */
690
691 #endif /* CEC */
692
693 #if defined(USB)
694 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
695 * @{
696 */
697 #define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE /*!< USB Clock source selection */
698 /**
699 * @}
700 */
701
702 #endif /* USB */
703
704 #if defined(RCC_CFGR_ADCPRE)
705 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
706 * @{
707 */
708 #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
709 /**
710 * @}
711 */
712
713 #endif /* RCC_CFGR_ADCPRE */
714
715 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
716 /** @defgroup RCC_LL_EC_ADCXX Peripheral ADC get clock source
717 * @{
718 */
719 #if defined(RCC_CFGR2_ADC1PRES)
720 #define LL_RCC_ADC1_CLKSOURCE RCC_CFGR2_ADC1PRES /*!< ADC1 Clock source selection */
721 #else
722 #define LL_RCC_ADC12_CLKSOURCE RCC_CFGR2_ADCPRE12 /*!< ADC12 Clock source selection */
723 #if defined(RCC_CFGR2_ADCPRE34)
724 #define LL_RCC_ADC34_CLKSOURCE RCC_CFGR2_ADCPRE34 /*!< ADC34 Clock source selection */
725 #endif /*RCC_CFGR2_ADCPRE34*/
726 #endif /*RCC_CFGR2_ADC1PRES*/
727 /**
728 * @}
729 */
730
731 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
732
733 #if defined(RCC_CFGR_SDPRE)
734 /** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source
735 * @{
736 */
737 #define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE /*!< SDADC Clock source selection */
738 /**
739 * @}
740 */
741
742 #endif /* RCC_CFGR_SDPRE */
743
744
745 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
746 * @{
747 */
748 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
749 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
750 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
751 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
752 /**
753 * @}
754 */
755
756 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
757 * @{
758 */
759 #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */
760 #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */
761 #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */
762 #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */
763 #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */
764 #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */
765 #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */
766 #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */
767 #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */
768 #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */
769 #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */
770 #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */
771 #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */
772 #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */
773 #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */
774 /**
775 * @}
776 */
777
778 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
779 * @{
780 */
781 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as main PLL entry clock source */
782 #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */
783 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
784 #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */
785 #else
786 #define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
787 #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */
788 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
789 #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
790 #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
791 #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
792 #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
793 #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
794 #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
795 #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
796 #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
797 #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
798 #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
799 #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
800 #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
801 #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
802 #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
803 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
804 /**
805 * @}
806 */
807
808 /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
809 * @{
810 */
811 #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */
812 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */
813 #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */
814 #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */
815 #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */
816 #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */
817 #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */
818 #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */
819 #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */
820 #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */
821 #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */
822 #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */
823 #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */
824 #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */
825 #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */
826 #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */
827 /**
828 * @}
829 */
830
831 /**
832 * @}
833 */
834
835 /* Exported macro ------------------------------------------------------------*/
836 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
837 * @{
838 */
839
840 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
841 * @{
842 */
843
844 /**
845 * @brief Write a value in RCC register
846 * @param __REG__ Register to be written
847 * @param __VALUE__ Value to be written in the register
848 * @retval None
849 */
850 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
851
852 /**
853 * @brief Read a value in RCC register
854 * @param __REG__ Register to be read
855 * @retval Register value
856 */
857 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
858 /**
859 * @}
860 */
861
862 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
863 * @{
864 */
865
866 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
867 /**
868 * @brief Helper macro to calculate the PLLCLK frequency
869 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator()
870 * , @ref LL_RCC_PLL_GetPrediv());
871 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
872 * @param __PLLMUL__ This parameter can be one of the following values:
873 * @arg @ref LL_RCC_PLL_MUL_2
874 * @arg @ref LL_RCC_PLL_MUL_3
875 * @arg @ref LL_RCC_PLL_MUL_4
876 * @arg @ref LL_RCC_PLL_MUL_5
877 * @arg @ref LL_RCC_PLL_MUL_6
878 * @arg @ref LL_RCC_PLL_MUL_7
879 * @arg @ref LL_RCC_PLL_MUL_8
880 * @arg @ref LL_RCC_PLL_MUL_9
881 * @arg @ref LL_RCC_PLL_MUL_10
882 * @arg @ref LL_RCC_PLL_MUL_11
883 * @arg @ref LL_RCC_PLL_MUL_12
884 * @arg @ref LL_RCC_PLL_MUL_13
885 * @arg @ref LL_RCC_PLL_MUL_14
886 * @arg @ref LL_RCC_PLL_MUL_15
887 * @arg @ref LL_RCC_PLL_MUL_16
888 * @param __PLLPREDIV__ This parameter can be one of the following values:
889 * @arg @ref LL_RCC_PREDIV_DIV_1
890 * @arg @ref LL_RCC_PREDIV_DIV_2
891 * @arg @ref LL_RCC_PREDIV_DIV_3
892 * @arg @ref LL_RCC_PREDIV_DIV_4
893 * @arg @ref LL_RCC_PREDIV_DIV_5
894 * @arg @ref LL_RCC_PREDIV_DIV_6
895 * @arg @ref LL_RCC_PREDIV_DIV_7
896 * @arg @ref LL_RCC_PREDIV_DIV_8
897 * @arg @ref LL_RCC_PREDIV_DIV_9
898 * @arg @ref LL_RCC_PREDIV_DIV_10
899 * @arg @ref LL_RCC_PREDIV_DIV_11
900 * @arg @ref LL_RCC_PREDIV_DIV_12
901 * @arg @ref LL_RCC_PREDIV_DIV_13
902 * @arg @ref LL_RCC_PREDIV_DIV_14
903 * @arg @ref LL_RCC_PREDIV_DIV_15
904 * @arg @ref LL_RCC_PREDIV_DIV_16
905 * @retval PLL clock frequency (in Hz)
906 */
907 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
908 (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
909
910 #else
911 /**
912 * @brief Helper macro to calculate the PLLCLK frequency
913 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
914 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
915 * @param __PLLMUL__ This parameter can be one of the following values:
916 * @arg @ref LL_RCC_PLL_MUL_2
917 * @arg @ref LL_RCC_PLL_MUL_3
918 * @arg @ref LL_RCC_PLL_MUL_4
919 * @arg @ref LL_RCC_PLL_MUL_5
920 * @arg @ref LL_RCC_PLL_MUL_6
921 * @arg @ref LL_RCC_PLL_MUL_7
922 * @arg @ref LL_RCC_PLL_MUL_8
923 * @arg @ref LL_RCC_PLL_MUL_9
924 * @arg @ref LL_RCC_PLL_MUL_10
925 * @arg @ref LL_RCC_PLL_MUL_11
926 * @arg @ref LL_RCC_PLL_MUL_12
927 * @arg @ref LL_RCC_PLL_MUL_13
928 * @arg @ref LL_RCC_PLL_MUL_14
929 * @arg @ref LL_RCC_PLL_MUL_15
930 * @arg @ref LL_RCC_PLL_MUL_16
931 * @retval PLL clock frequency (in Hz)
932 */
933 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
934 ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
935 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
936 /**
937 * @brief Helper macro to calculate the HCLK frequency
938 * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
939 * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
940 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
941 * @param __AHBPRESCALER__ This parameter can be one of the following values:
942 * @arg @ref LL_RCC_SYSCLK_DIV_1
943 * @arg @ref LL_RCC_SYSCLK_DIV_2
944 * @arg @ref LL_RCC_SYSCLK_DIV_4
945 * @arg @ref LL_RCC_SYSCLK_DIV_8
946 * @arg @ref LL_RCC_SYSCLK_DIV_16
947 * @arg @ref LL_RCC_SYSCLK_DIV_64
948 * @arg @ref LL_RCC_SYSCLK_DIV_128
949 * @arg @ref LL_RCC_SYSCLK_DIV_256
950 * @arg @ref LL_RCC_SYSCLK_DIV_512
951 * @retval HCLK clock frequency (in Hz)
952 */
953 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
954
955 /**
956 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
957 * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
958 * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
959 * @param __HCLKFREQ__ HCLK frequency
960 * @param __APB1PRESCALER__: This parameter can be one of the following values:
961 * @arg @ref LL_RCC_APB1_DIV_1
962 * @arg @ref LL_RCC_APB1_DIV_2
963 * @arg @ref LL_RCC_APB1_DIV_4
964 * @arg @ref LL_RCC_APB1_DIV_8
965 * @arg @ref LL_RCC_APB1_DIV_16
966 * @retval PCLK1 clock frequency (in Hz)
967 */
968 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
969
970 /**
971 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
972 * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
973 * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
974 * @param __HCLKFREQ__ HCLK frequency
975 * @param __APB2PRESCALER__: This parameter can be one of the following values:
976 * @arg @ref LL_RCC_APB2_DIV_1
977 * @arg @ref LL_RCC_APB2_DIV_2
978 * @arg @ref LL_RCC_APB2_DIV_4
979 * @arg @ref LL_RCC_APB2_DIV_8
980 * @arg @ref LL_RCC_APB2_DIV_16
981 * @retval PCLK2 clock frequency (in Hz)
982 */
983 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
984
985 /**
986 * @}
987 */
988
989 /**
990 * @}
991 */
992
993 /* Exported functions --------------------------------------------------------*/
994 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
995 * @{
996 */
997
998 /** @defgroup RCC_LL_EF_HSE HSE
999 * @{
1000 */
1001
1002 /**
1003 * @brief Enable the Clock Security System.
1004 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1005 * @retval None
1006 */
LL_RCC_HSE_EnableCSS(void)1007 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1008 {
1009 SET_BIT(RCC->CR, RCC_CR_CSSON);
1010 }
1011
1012 /**
1013 * @brief Disable the Clock Security System.
1014 * @note Cannot be disabled in HSE is ready (only by hardware)
1015 * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
1016 * @retval None
1017 */
LL_RCC_HSE_DisableCSS(void)1018 __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
1019 {
1020 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
1021 }
1022
1023 /**
1024 * @brief Enable HSE external oscillator (HSE Bypass)
1025 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1026 * @retval None
1027 */
LL_RCC_HSE_EnableBypass(void)1028 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1029 {
1030 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1031 }
1032
1033 /**
1034 * @brief Disable HSE external oscillator (HSE Bypass)
1035 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1036 * @retval None
1037 */
LL_RCC_HSE_DisableBypass(void)1038 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1039 {
1040 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1041 }
1042
1043 /**
1044 * @brief Enable HSE crystal oscillator (HSE ON)
1045 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1046 * @retval None
1047 */
LL_RCC_HSE_Enable(void)1048 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1049 {
1050 SET_BIT(RCC->CR, RCC_CR_HSEON);
1051 }
1052
1053 /**
1054 * @brief Disable HSE crystal oscillator (HSE ON)
1055 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1056 * @retval None
1057 */
LL_RCC_HSE_Disable(void)1058 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1059 {
1060 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1061 }
1062
1063 /**
1064 * @brief Check if HSE oscillator Ready
1065 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1066 * @retval State of bit (1 or 0).
1067 */
LL_RCC_HSE_IsReady(void)1068 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1069 {
1070 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
1071 }
1072
1073 /**
1074 * @}
1075 */
1076
1077 /** @defgroup RCC_LL_EF_HSI HSI
1078 * @{
1079 */
1080
1081 /**
1082 * @brief Enable HSI oscillator
1083 * @rmtoll CR HSION LL_RCC_HSI_Enable
1084 * @retval None
1085 */
LL_RCC_HSI_Enable(void)1086 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1087 {
1088 SET_BIT(RCC->CR, RCC_CR_HSION);
1089 }
1090
1091 /**
1092 * @brief Disable HSI oscillator
1093 * @rmtoll CR HSION LL_RCC_HSI_Disable
1094 * @retval None
1095 */
LL_RCC_HSI_Disable(void)1096 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1097 {
1098 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1099 }
1100
1101 /**
1102 * @brief Check if HSI clock is ready
1103 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1104 * @retval State of bit (1 or 0).
1105 */
LL_RCC_HSI_IsReady(void)1106 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1107 {
1108 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
1109 }
1110
1111 /**
1112 * @brief Get HSI Calibration value
1113 * @note When HSITRIM is written, HSICAL is updated with the sum of
1114 * HSITRIM and the factory trim value
1115 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
1116 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1117 */
LL_RCC_HSI_GetCalibration(void)1118 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1119 {
1120 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
1121 }
1122
1123 /**
1124 * @brief Set HSI Calibration trimming
1125 * @note user-programmable trimming value that is added to the HSICAL
1126 * @note Default value is 16, which, when added to the HSICAL value,
1127 * should trim the HSI to 16 MHz +/- 1 %
1128 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
1129 * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
1130 * @retval None
1131 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1132 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1133 {
1134 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
1135 }
1136
1137 /**
1138 * @brief Get HSI Calibration trimming
1139 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
1140 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
1141 */
LL_RCC_HSI_GetCalibTrimming(void)1142 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1143 {
1144 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
1145 }
1146
1147 /**
1148 * @}
1149 */
1150
1151 /** @defgroup RCC_LL_EF_LSE LSE
1152 * @{
1153 */
1154
1155 /**
1156 * @brief Enable Low Speed External (LSE) crystal.
1157 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1158 * @retval None
1159 */
LL_RCC_LSE_Enable(void)1160 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1161 {
1162 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1163 }
1164
1165 /**
1166 * @brief Disable Low Speed External (LSE) crystal.
1167 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1168 * @retval None
1169 */
LL_RCC_LSE_Disable(void)1170 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1171 {
1172 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1173 }
1174
1175 /**
1176 * @brief Enable external clock source (LSE bypass).
1177 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1178 * @retval None
1179 */
LL_RCC_LSE_EnableBypass(void)1180 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1181 {
1182 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1183 }
1184
1185 /**
1186 * @brief Disable external clock source (LSE bypass).
1187 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1188 * @retval None
1189 */
LL_RCC_LSE_DisableBypass(void)1190 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1191 {
1192 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1193 }
1194
1195 /**
1196 * @brief Set LSE oscillator drive capability
1197 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1198 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1199 * @param LSEDrive This parameter can be one of the following values:
1200 * @arg @ref LL_RCC_LSEDRIVE_LOW
1201 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1202 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1203 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1204 * @retval None
1205 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1206 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1207 {
1208 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1209 }
1210
1211 /**
1212 * @brief Get LSE oscillator drive capability
1213 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1214 * @retval Returned value can be one of the following values:
1215 * @arg @ref LL_RCC_LSEDRIVE_LOW
1216 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1217 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1218 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1219 */
LL_RCC_LSE_GetDriveCapability(void)1220 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1221 {
1222 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1223 }
1224
1225 /**
1226 * @brief Check if LSE oscillator Ready
1227 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1228 * @retval State of bit (1 or 0).
1229 */
LL_RCC_LSE_IsReady(void)1230 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1231 {
1232 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
1233 }
1234
1235 /**
1236 * @}
1237 */
1238
1239 /** @defgroup RCC_LL_EF_LSI LSI
1240 * @{
1241 */
1242
1243 /**
1244 * @brief Enable LSI Oscillator
1245 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1246 * @retval None
1247 */
LL_RCC_LSI_Enable(void)1248 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1249 {
1250 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1251 }
1252
1253 /**
1254 * @brief Disable LSI Oscillator
1255 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1256 * @retval None
1257 */
LL_RCC_LSI_Disable(void)1258 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1259 {
1260 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1261 }
1262
1263 /**
1264 * @brief Check if LSI is Ready
1265 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1266 * @retval State of bit (1 or 0).
1267 */
LL_RCC_LSI_IsReady(void)1268 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1269 {
1270 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
1271 }
1272
1273 /**
1274 * @}
1275 */
1276
1277 /** @defgroup RCC_LL_EF_System System
1278 * @{
1279 */
1280
1281 /**
1282 * @brief Configure the system clock source
1283 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1284 * @param Source This parameter can be one of the following values:
1285 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1286 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1287 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1288 * @retval None
1289 */
LL_RCC_SetSysClkSource(uint32_t Source)1290 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1291 {
1292 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1293 }
1294
1295 /**
1296 * @brief Get the system clock source
1297 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1298 * @retval Returned value can be one of the following values:
1299 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1300 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1301 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1302 */
LL_RCC_GetSysClkSource(void)1303 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1304 {
1305 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1306 }
1307
1308 /**
1309 * @brief Set AHB prescaler
1310 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1311 * @param Prescaler This parameter can be one of the following values:
1312 * @arg @ref LL_RCC_SYSCLK_DIV_1
1313 * @arg @ref LL_RCC_SYSCLK_DIV_2
1314 * @arg @ref LL_RCC_SYSCLK_DIV_4
1315 * @arg @ref LL_RCC_SYSCLK_DIV_8
1316 * @arg @ref LL_RCC_SYSCLK_DIV_16
1317 * @arg @ref LL_RCC_SYSCLK_DIV_64
1318 * @arg @ref LL_RCC_SYSCLK_DIV_128
1319 * @arg @ref LL_RCC_SYSCLK_DIV_256
1320 * @arg @ref LL_RCC_SYSCLK_DIV_512
1321 * @retval None
1322 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1323 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1324 {
1325 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1326 }
1327
1328 /**
1329 * @brief Set APB1 prescaler
1330 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
1331 * @param Prescaler This parameter can be one of the following values:
1332 * @arg @ref LL_RCC_APB1_DIV_1
1333 * @arg @ref LL_RCC_APB1_DIV_2
1334 * @arg @ref LL_RCC_APB1_DIV_4
1335 * @arg @ref LL_RCC_APB1_DIV_8
1336 * @arg @ref LL_RCC_APB1_DIV_16
1337 * @retval None
1338 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1339 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1340 {
1341 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
1342 }
1343
1344 /**
1345 * @brief Set APB2 prescaler
1346 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
1347 * @param Prescaler This parameter can be one of the following values:
1348 * @arg @ref LL_RCC_APB2_DIV_1
1349 * @arg @ref LL_RCC_APB2_DIV_2
1350 * @arg @ref LL_RCC_APB2_DIV_4
1351 * @arg @ref LL_RCC_APB2_DIV_8
1352 * @arg @ref LL_RCC_APB2_DIV_16
1353 * @retval None
1354 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)1355 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1356 {
1357 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
1358 }
1359
1360 /**
1361 * @brief Get AHB prescaler
1362 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1363 * @retval Returned value can be one of the following values:
1364 * @arg @ref LL_RCC_SYSCLK_DIV_1
1365 * @arg @ref LL_RCC_SYSCLK_DIV_2
1366 * @arg @ref LL_RCC_SYSCLK_DIV_4
1367 * @arg @ref LL_RCC_SYSCLK_DIV_8
1368 * @arg @ref LL_RCC_SYSCLK_DIV_16
1369 * @arg @ref LL_RCC_SYSCLK_DIV_64
1370 * @arg @ref LL_RCC_SYSCLK_DIV_128
1371 * @arg @ref LL_RCC_SYSCLK_DIV_256
1372 * @arg @ref LL_RCC_SYSCLK_DIV_512
1373 */
LL_RCC_GetAHBPrescaler(void)1374 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1375 {
1376 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1377 }
1378
1379 /**
1380 * @brief Get APB1 prescaler
1381 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
1382 * @retval Returned value can be one of the following values:
1383 * @arg @ref LL_RCC_APB1_DIV_1
1384 * @arg @ref LL_RCC_APB1_DIV_2
1385 * @arg @ref LL_RCC_APB1_DIV_4
1386 * @arg @ref LL_RCC_APB1_DIV_8
1387 * @arg @ref LL_RCC_APB1_DIV_16
1388 */
LL_RCC_GetAPB1Prescaler(void)1389 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1390 {
1391 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1392 }
1393
1394 /**
1395 * @brief Get APB2 prescaler
1396 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
1397 * @retval Returned value can be one of the following values:
1398 * @arg @ref LL_RCC_APB2_DIV_1
1399 * @arg @ref LL_RCC_APB2_DIV_2
1400 * @arg @ref LL_RCC_APB2_DIV_4
1401 * @arg @ref LL_RCC_APB2_DIV_8
1402 * @arg @ref LL_RCC_APB2_DIV_16
1403 */
LL_RCC_GetAPB2Prescaler(void)1404 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1405 {
1406 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1407 }
1408
1409 /**
1410 * @}
1411 */
1412
1413 /** @defgroup RCC_LL_EF_MCO MCO
1414 * @{
1415 */
1416
1417 /**
1418 * @brief Configure MCOx
1419 * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n
1420 * CFGR MCOPRE LL_RCC_ConfigMCO\n
1421 * CFGR PLLNODIV LL_RCC_ConfigMCO
1422 * @param MCOxSource This parameter can be one of the following values:
1423 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1424 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1425 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1426 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1427 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1428 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1429 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*)
1430 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
1431 *
1432 * (*) value not defined in all devices
1433 * @param MCOxPrescaler This parameter can be one of the following values:
1434 * @arg @ref LL_RCC_MCO1_DIV_1
1435 * @arg @ref LL_RCC_MCO1_DIV_2 (*)
1436 * @arg @ref LL_RCC_MCO1_DIV_4 (*)
1437 * @arg @ref LL_RCC_MCO1_DIV_8 (*)
1438 * @arg @ref LL_RCC_MCO1_DIV_16 (*)
1439 * @arg @ref LL_RCC_MCO1_DIV_32 (*)
1440 * @arg @ref LL_RCC_MCO1_DIV_64 (*)
1441 * @arg @ref LL_RCC_MCO1_DIV_128 (*)
1442 *
1443 * (*) value not defined in all devices
1444 * @retval None
1445 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1446 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1447 {
1448 #if defined(RCC_CFGR_MCOPRE)
1449 #if defined(RCC_CFGR_PLLNODIV)
1450 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler);
1451 #else
1452 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1453 #endif /* RCC_CFGR_PLLNODIV */
1454 #else
1455 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
1456 #endif /* RCC_CFGR_MCOPRE */
1457 }
1458
1459 /**
1460 * @}
1461 */
1462
1463 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1464 * @{
1465 */
1466
1467 /**
1468 * @brief Configure USARTx clock source
1469 * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n
1470 * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n
1471 * CFGR3 USART3SW LL_RCC_SetUSARTClockSource
1472 * @param USARTxSource This parameter can be one of the following values:
1473 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
1474 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
1475 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1476 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1477 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1478 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
1479 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
1480 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
1481 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
1482 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
1483 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
1484 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
1485 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
1486 *
1487 * (*) value not defined in all devices.
1488 * @retval None
1489 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1490 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1491 {
1492 MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU));
1493 }
1494
1495 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
1496 /**
1497 * @brief Configure UARTx clock source
1498 * @rmtoll CFGR3 UART4SW LL_RCC_SetUARTClockSource\n
1499 * CFGR3 UART5SW LL_RCC_SetUARTClockSource
1500 * @param UARTxSource This parameter can be one of the following values:
1501 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
1502 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
1503 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
1504 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
1505 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
1506 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
1507 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
1508 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
1509 * @retval None
1510 */
LL_RCC_SetUARTClockSource(uint32_t UARTxSource)1511 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
1512 {
1513 MODIFY_REG(RCC->CFGR3, ((UARTxSource & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW)));
1514 }
1515 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
1516
1517 /**
1518 * @brief Configure I2Cx clock source
1519 * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource\n
1520 * CFGR3 I2C2SW LL_RCC_SetI2CClockSource\n
1521 * CFGR3 I2C3SW LL_RCC_SetI2CClockSource
1522 * @param I2CxSource This parameter can be one of the following values:
1523 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1524 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1525 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
1526 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
1527 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
1528 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
1529 *
1530 * (*) value not defined in all devices.
1531 * @retval None
1532 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1533 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1534 {
1535 MODIFY_REG(RCC->CFGR3, ((I2CxSource & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU));
1536 }
1537
1538 #if defined(RCC_CFGR_I2SSRC)
1539 /**
1540 * @brief Configure I2Sx clock source
1541 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
1542 * @param I2SxSource This parameter can be one of the following values:
1543 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1544 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1545 * @retval None
1546 */
LL_RCC_SetI2SClockSource(uint32_t I2SxSource)1547 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
1548 {
1549 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource);
1550 }
1551 #endif /* RCC_CFGR_I2SSRC */
1552
1553 #if defined(RCC_CFGR3_TIMSW)
1554 /**
1555 * @brief Configure TIMx clock source
1556 * @rmtoll CFGR3 TIM1SW LL_RCC_SetTIMClockSource\n
1557 * CFGR3 TIM8SW LL_RCC_SetTIMClockSource\n
1558 * CFGR3 TIM15SW LL_RCC_SetTIMClockSource\n
1559 * CFGR3 TIM16SW LL_RCC_SetTIMClockSource\n
1560 * CFGR3 TIM17SW LL_RCC_SetTIMClockSource\n
1561 * CFGR3 TIM20SW LL_RCC_SetTIMClockSource\n
1562 * CFGR3 TIM2SW LL_RCC_SetTIMClockSource\n
1563 * CFGR3 TIM34SW LL_RCC_SetTIMClockSource
1564 * @param TIMxSource This parameter can be one of the following values:
1565 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
1566 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
1567 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
1568 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
1569 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
1570 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
1571 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
1572 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
1573 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
1574 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
1575 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
1576 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
1577 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
1578 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
1579 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
1580 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
1581 *
1582 * (*) value not defined in all devices.
1583 * @retval None
1584 */
LL_RCC_SetTIMClockSource(uint32_t TIMxSource)1585 __STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
1586 {
1587 MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU));
1588 }
1589 #endif /* RCC_CFGR3_TIMSW */
1590
1591 #if defined(HRTIM1)
1592 /**
1593 * @brief Configure HRTIMx clock source
1594 * @rmtoll CFGR3 HRTIMSW LL_RCC_SetHRTIMClockSource
1595 * @param HRTIMxSource This parameter can be one of the following values:
1596 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
1597 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
1598 * @retval None
1599 */
LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource)1600 __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource)
1601 {
1602 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource);
1603 }
1604 #endif /* HRTIM1 */
1605
1606 #if defined(CEC)
1607 /**
1608 * @brief Configure CEC clock source
1609 * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource
1610 * @param CECxSource This parameter can be one of the following values:
1611 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
1612 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
1613 * @retval None
1614 */
LL_RCC_SetCECClockSource(uint32_t CECxSource)1615 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
1616 {
1617 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource);
1618 }
1619 #endif /* CEC */
1620
1621 #if defined(USB)
1622 /**
1623 * @brief Configure USB clock source
1624 * @rmtoll CFGR USBPRE LL_RCC_SetUSBClockSource
1625 * @param USBxSource This parameter can be one of the following values:
1626 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1627 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
1628 * @retval None
1629 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)1630 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
1631 {
1632 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
1633 }
1634 #endif /* USB */
1635
1636 #if defined(RCC_CFGR_ADCPRE)
1637 /**
1638 * @brief Configure ADC clock source
1639 * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
1640 * @param ADCxSource This parameter can be one of the following values:
1641 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
1642 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
1643 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
1644 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
1645 * @retval None
1646 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)1647 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1648 {
1649 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
1650 }
1651
1652 #elif defined(RCC_CFGR2_ADC1PRES)
1653 /**
1654 * @brief Configure ADC clock source
1655 * @rmtoll CFGR2 ADC1PRES LL_RCC_SetADCClockSource
1656 * @param ADCxSource This parameter can be one of the following values:
1657 * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
1658 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
1659 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
1660 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
1661 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
1662 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
1663 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
1664 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
1665 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
1666 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
1667 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
1668 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
1669 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
1670 * @retval None
1671 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)1672 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1673 {
1674 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource);
1675 }
1676
1677 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
1678 /**
1679 * @brief Configure ADC clock source
1680 * @rmtoll CFGR2 ADCPRE12 LL_RCC_SetADCClockSource\n
1681 * CFGR2 ADCPRE34 LL_RCC_SetADCClockSource
1682 * @param ADCxSource This parameter can be one of the following values:
1683 * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
1684 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
1685 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
1686 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
1687 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
1688 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
1689 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
1690 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
1691 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
1692 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
1693 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
1694 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
1695 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
1696 * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
1697 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
1698 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
1699 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
1700 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
1701 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
1702 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
1703 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
1704 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
1705 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
1706 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
1707 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
1708 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
1709 *
1710 * (*) value not defined in all devices.
1711 * @retval None
1712 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)1713 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1714 {
1715 #if defined(RCC_CFGR2_ADCPRE34)
1716 MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU));
1717 #else
1718 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource);
1719 #endif /* RCC_CFGR2_ADCPRE34 */
1720 }
1721 #endif /* RCC_CFGR_ADCPRE */
1722
1723 #if defined(RCC_CFGR_SDPRE)
1724 /**
1725 * @brief Configure SDADCx clock source
1726 * @rmtoll CFGR SDPRE LL_RCC_SetSDADCClockSource
1727 * @param SDADCxSource This parameter can be one of the following values:
1728 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
1729 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
1730 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
1731 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
1732 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
1733 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
1734 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
1735 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
1736 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
1737 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
1738 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
1739 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
1740 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
1741 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
1742 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
1743 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
1744 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
1745 * @retval None
1746 */
LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource)1747 __STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource)
1748 {
1749 MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource);
1750 }
1751 #endif /* RCC_CFGR_SDPRE */
1752
1753 /**
1754 * @brief Get USARTx clock source
1755 * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n
1756 * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n
1757 * CFGR3 USART3SW LL_RCC_GetUSARTClockSource
1758 * @param USARTx This parameter can be one of the following values:
1759 * @arg @ref LL_RCC_USART1_CLKSOURCE
1760 * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
1761 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
1762 *
1763 * (*) value not defined in all devices.
1764 * @retval Returned value can be one of the following values:
1765 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
1766 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
1767 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1768 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1769 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1770 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
1771 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
1772 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
1773 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
1774 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
1775 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
1776 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
1777 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
1778 *
1779 * (*) value not defined in all devices.
1780 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)1781 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1782 {
1783 return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U));
1784 }
1785
1786 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
1787 /**
1788 * @brief Get UARTx clock source
1789 * @rmtoll CFGR3 UART4SW LL_RCC_GetUARTClockSource\n
1790 * CFGR3 UART5SW LL_RCC_GetUARTClockSource
1791 * @param UARTx This parameter can be one of the following values:
1792 * @arg @ref LL_RCC_UART4_CLKSOURCE
1793 * @arg @ref LL_RCC_UART5_CLKSOURCE
1794 * @retval Returned value can be one of the following values:
1795 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
1796 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
1797 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
1798 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
1799 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
1800 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
1801 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
1802 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
1803 */
LL_RCC_GetUARTClockSource(uint32_t UARTx)1804 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
1805 {
1806 return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U));
1807 }
1808 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
1809
1810 /**
1811 * @brief Get I2Cx clock source
1812 * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource\n
1813 * CFGR3 I2C2SW LL_RCC_GetI2CClockSource\n
1814 * CFGR3 I2C3SW LL_RCC_GetI2CClockSource
1815 * @param I2Cx This parameter can be one of the following values:
1816 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1817 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
1818 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
1819 *
1820 * (*) value not defined in all devices.
1821 * @retval Returned value can be one of the following values:
1822 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1823 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1824 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
1825 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
1826 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
1827 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
1828 *
1829 * (*) value not defined in all devices.
1830 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)1831 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
1832 {
1833 return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U));
1834 }
1835
1836 #if defined(RCC_CFGR_I2SSRC)
1837 /**
1838 * @brief Get I2Sx clock source
1839 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
1840 * @param I2Sx This parameter can be one of the following values:
1841 * @arg @ref LL_RCC_I2S_CLKSOURCE
1842 * @retval Returned value can be one of the following values:
1843 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1844 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1845 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)1846 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
1847 {
1848 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
1849 }
1850 #endif /* RCC_CFGR_I2SSRC */
1851
1852 #if defined(RCC_CFGR3_TIMSW)
1853 /**
1854 * @brief Get TIMx clock source
1855 * @rmtoll CFGR3 TIM1SW LL_RCC_GetTIMClockSource\n
1856 * CFGR3 TIM8SW LL_RCC_GetTIMClockSource\n
1857 * CFGR3 TIM15SW LL_RCC_GetTIMClockSource\n
1858 * CFGR3 TIM16SW LL_RCC_GetTIMClockSource\n
1859 * CFGR3 TIM17SW LL_RCC_GetTIMClockSource\n
1860 * CFGR3 TIM20SW LL_RCC_GetTIMClockSource\n
1861 * CFGR3 TIM2SW LL_RCC_GetTIMClockSource\n
1862 * CFGR3 TIM34SW LL_RCC_GetTIMClockSource
1863 * @param TIMx This parameter can be one of the following values:
1864 * @arg @ref LL_RCC_TIM1_CLKSOURCE
1865 * @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
1866 * @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
1867 * @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
1868 * @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
1869 * @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
1870 * @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
1871 * @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
1872 *
1873 * (*) value not defined in all devices.
1874 * @retval Returned value can be one of the following values:
1875 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
1876 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
1877 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
1878 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
1879 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
1880 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
1881 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
1882 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
1883 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
1884 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
1885 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
1886 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
1887 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
1888 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
1889 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
1890 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
1891 *
1892 * (*) value not defined in all devices.
1893 */
LL_RCC_GetTIMClockSource(uint32_t TIMx)1894 __STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
1895 {
1896 return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U));
1897 }
1898 #endif /* RCC_CFGR3_TIMSW */
1899
1900 #if defined(HRTIM1)
1901 /**
1902 * @brief Get HRTIMx clock source
1903 * @rmtoll CFGR3 HRTIMSW LL_RCC_GetHRTIMClockSource
1904 * @param HRTIMx This parameter can be one of the following values:
1905 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE
1906 * @retval Returned value can be one of the following values:
1907 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
1908 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
1909 */
LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx)1910 __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx)
1911 {
1912 return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx));
1913 }
1914 #endif /* HRTIM1 */
1915
1916 #if defined(CEC)
1917 /**
1918 * @brief Get CEC clock source
1919 * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource
1920 * @param CECx This parameter can be one of the following values:
1921 * @arg @ref LL_RCC_CEC_CLKSOURCE
1922 * @retval Returned value can be one of the following values:
1923 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
1924 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
1925 */
LL_RCC_GetCECClockSource(uint32_t CECx)1926 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
1927 {
1928 return (uint32_t)(READ_BIT(RCC->CFGR3, CECx));
1929 }
1930 #endif /* CEC */
1931
1932 #if defined(USB)
1933 /**
1934 * @brief Get USBx clock source
1935 * @rmtoll CFGR USBPRE LL_RCC_GetUSBClockSource
1936 * @param USBx This parameter can be one of the following values:
1937 * @arg @ref LL_RCC_USB_CLKSOURCE
1938 * @retval Returned value can be one of the following values:
1939 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1940 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
1941 */
LL_RCC_GetUSBClockSource(uint32_t USBx)1942 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
1943 {
1944 return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
1945 }
1946 #endif /* USB */
1947
1948 #if defined(RCC_CFGR_ADCPRE)
1949 /**
1950 * @brief Get ADCx clock source
1951 * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
1952 * @param ADCx This parameter can be one of the following values:
1953 * @arg @ref LL_RCC_ADC_CLKSOURCE
1954 * @retval Returned value can be one of the following values:
1955 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
1956 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
1957 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
1958 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
1959 */
LL_RCC_GetADCClockSource(uint32_t ADCx)1960 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1961 {
1962 return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
1963 }
1964
1965 #elif defined(RCC_CFGR2_ADC1PRES)
1966 /**
1967 * @brief Get ADCx clock source
1968 * @rmtoll CFGR2 ADC1PRES LL_RCC_GetADCClockSource
1969 * @param ADCx This parameter can be one of the following values:
1970 * @arg @ref LL_RCC_ADC1_CLKSOURCE
1971 * @retval Returned value can be one of the following values:
1972 * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
1973 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
1974 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
1975 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
1976 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
1977 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
1978 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
1979 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
1980 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
1981 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
1982 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
1983 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
1984 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
1985 */
LL_RCC_GetADCClockSource(uint32_t ADCx)1986 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1987 {
1988 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
1989 }
1990
1991 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
1992 /**
1993 * @brief Get ADCx clock source
1994 * @rmtoll CFGR2 ADCPRE12 LL_RCC_GetADCClockSource\n
1995 * CFGR2 ADCPRE34 LL_RCC_GetADCClockSource
1996 * @param ADCx This parameter can be one of the following values:
1997 * @arg @ref LL_RCC_ADC12_CLKSOURCE
1998 * @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
1999 *
2000 * (*) value not defined in all devices.
2001 * @retval Returned value can be one of the following values:
2002 * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
2003 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
2004 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
2005 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
2006 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
2007 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
2008 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
2009 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
2010 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
2011 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
2012 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
2013 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
2014 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
2015 * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
2016 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
2017 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
2018 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
2019 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
2020 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
2021 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
2022 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
2023 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
2024 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
2025 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
2026 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
2027 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
2028 *
2029 * (*) value not defined in all devices.
2030 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2031 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2032 {
2033 #if defined(RCC_CFGR2_ADCPRE34)
2034 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U));
2035 #else
2036 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
2037 #endif /*RCC_CFGR2_ADCPRE34*/
2038 }
2039 #endif /* RCC_CFGR_ADCPRE */
2040
2041 #if defined(RCC_CFGR_SDPRE)
2042 /**
2043 * @brief Get SDADCx clock source
2044 * @rmtoll CFGR SDPRE LL_RCC_GetSDADCClockSource
2045 * @param SDADCx This parameter can be one of the following values:
2046 * @arg @ref LL_RCC_SDADC_CLKSOURCE
2047 * @retval Returned value can be one of the following values:
2048 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
2049 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
2050 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
2051 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
2052 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
2053 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
2054 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
2055 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
2056 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
2057 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
2058 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
2059 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
2060 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
2061 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
2062 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
2063 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
2064 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
2065 */
LL_RCC_GetSDADCClockSource(uint32_t SDADCx)2066 __STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx)
2067 {
2068 return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx));
2069 }
2070 #endif /* RCC_CFGR_SDPRE */
2071
2072 /**
2073 * @}
2074 */
2075
2076 /** @defgroup RCC_LL_EF_RTC RTC
2077 * @{
2078 */
2079
2080 /**
2081 * @brief Set RTC Clock Source
2082 * @note Once the RTC clock source has been selected, it cannot be changed any more unless
2083 * the Backup domain is reset. The BDRST bit can be used to reset them.
2084 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2085 * @param Source This parameter can be one of the following values:
2086 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2087 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2088 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2089 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2090 * @retval None
2091 */
LL_RCC_SetRTCClockSource(uint32_t Source)2092 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2093 {
2094 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2095 }
2096
2097 /**
2098 * @brief Get RTC Clock Source
2099 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2100 * @retval Returned value can be one of the following values:
2101 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2102 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2103 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2104 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2105 */
LL_RCC_GetRTCClockSource(void)2106 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2107 {
2108 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2109 }
2110
2111 /**
2112 * @brief Enable RTC
2113 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2114 * @retval None
2115 */
LL_RCC_EnableRTC(void)2116 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2117 {
2118 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2119 }
2120
2121 /**
2122 * @brief Disable RTC
2123 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2124 * @retval None
2125 */
LL_RCC_DisableRTC(void)2126 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2127 {
2128 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2129 }
2130
2131 /**
2132 * @brief Check if RTC has been enabled or not
2133 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2134 * @retval State of bit (1 or 0).
2135 */
LL_RCC_IsEnabledRTC(void)2136 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2137 {
2138 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
2139 }
2140
2141 /**
2142 * @brief Force the Backup domain reset
2143 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2144 * @retval None
2145 */
LL_RCC_ForceBackupDomainReset(void)2146 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2147 {
2148 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2149 }
2150
2151 /**
2152 * @brief Release the Backup domain reset
2153 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2154 * @retval None
2155 */
LL_RCC_ReleaseBackupDomainReset(void)2156 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2157 {
2158 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2159 }
2160
2161 /**
2162 * @}
2163 */
2164
2165 /** @defgroup RCC_LL_EF_PLL PLL
2166 * @{
2167 */
2168
2169 /**
2170 * @brief Enable PLL
2171 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2172 * @retval None
2173 */
LL_RCC_PLL_Enable(void)2174 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2175 {
2176 SET_BIT(RCC->CR, RCC_CR_PLLON);
2177 }
2178
2179 /**
2180 * @brief Disable PLL
2181 * @note Cannot be disabled if the PLL clock is used as the system clock
2182 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2183 * @retval None
2184 */
LL_RCC_PLL_Disable(void)2185 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2186 {
2187 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2188 }
2189
2190 /**
2191 * @brief Check if PLL Ready
2192 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2193 * @retval State of bit (1 or 0).
2194 */
LL_RCC_PLL_IsReady(void)2195 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2196 {
2197 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
2198 }
2199
2200 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
2201 /**
2202 * @brief Configure PLL used for SYSCLK Domain
2203 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2204 * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
2205 * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
2206 * @param Source This parameter can be one of the following values:
2207 * @arg @ref LL_RCC_PLLSOURCE_HSI
2208 * @arg @ref LL_RCC_PLLSOURCE_HSE
2209 * @param PLLMul This parameter can be one of the following values:
2210 * @arg @ref LL_RCC_PLL_MUL_2
2211 * @arg @ref LL_RCC_PLL_MUL_3
2212 * @arg @ref LL_RCC_PLL_MUL_4
2213 * @arg @ref LL_RCC_PLL_MUL_5
2214 * @arg @ref LL_RCC_PLL_MUL_6
2215 * @arg @ref LL_RCC_PLL_MUL_7
2216 * @arg @ref LL_RCC_PLL_MUL_8
2217 * @arg @ref LL_RCC_PLL_MUL_9
2218 * @arg @ref LL_RCC_PLL_MUL_10
2219 * @arg @ref LL_RCC_PLL_MUL_11
2220 * @arg @ref LL_RCC_PLL_MUL_12
2221 * @arg @ref LL_RCC_PLL_MUL_13
2222 * @arg @ref LL_RCC_PLL_MUL_14
2223 * @arg @ref LL_RCC_PLL_MUL_15
2224 * @arg @ref LL_RCC_PLL_MUL_16
2225 * @param PLLDiv This parameter can be one of the following values:
2226 * @arg @ref LL_RCC_PREDIV_DIV_1
2227 * @arg @ref LL_RCC_PREDIV_DIV_2
2228 * @arg @ref LL_RCC_PREDIV_DIV_3
2229 * @arg @ref LL_RCC_PREDIV_DIV_4
2230 * @arg @ref LL_RCC_PREDIV_DIV_5
2231 * @arg @ref LL_RCC_PREDIV_DIV_6
2232 * @arg @ref LL_RCC_PREDIV_DIV_7
2233 * @arg @ref LL_RCC_PREDIV_DIV_8
2234 * @arg @ref LL_RCC_PREDIV_DIV_9
2235 * @arg @ref LL_RCC_PREDIV_DIV_10
2236 * @arg @ref LL_RCC_PREDIV_DIV_11
2237 * @arg @ref LL_RCC_PREDIV_DIV_12
2238 * @arg @ref LL_RCC_PREDIV_DIV_13
2239 * @arg @ref LL_RCC_PREDIV_DIV_14
2240 * @arg @ref LL_RCC_PREDIV_DIV_15
2241 * @arg @ref LL_RCC_PREDIV_DIV_16
2242 * @retval None
2243 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLMul,uint32_t PLLDiv)2244 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
2245 {
2246 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul);
2247 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv);
2248 }
2249
2250 #else
2251
2252 /**
2253 * @brief Configure PLL used for SYSCLK Domain
2254 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2255 * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
2256 * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
2257 * @param Source This parameter can be one of the following values:
2258 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
2259 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
2260 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2
2261 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3
2262 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4
2263 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5
2264 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6
2265 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7
2266 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8
2267 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9
2268 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10
2269 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11
2270 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12
2271 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13
2272 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14
2273 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15
2274 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16
2275 * @param PLLMul This parameter can be one of the following values:
2276 * @arg @ref LL_RCC_PLL_MUL_2
2277 * @arg @ref LL_RCC_PLL_MUL_3
2278 * @arg @ref LL_RCC_PLL_MUL_4
2279 * @arg @ref LL_RCC_PLL_MUL_5
2280 * @arg @ref LL_RCC_PLL_MUL_6
2281 * @arg @ref LL_RCC_PLL_MUL_7
2282 * @arg @ref LL_RCC_PLL_MUL_8
2283 * @arg @ref LL_RCC_PLL_MUL_9
2284 * @arg @ref LL_RCC_PLL_MUL_10
2285 * @arg @ref LL_RCC_PLL_MUL_11
2286 * @arg @ref LL_RCC_PLL_MUL_12
2287 * @arg @ref LL_RCC_PLL_MUL_13
2288 * @arg @ref LL_RCC_PLL_MUL_14
2289 * @arg @ref LL_RCC_PLL_MUL_15
2290 * @arg @ref LL_RCC_PLL_MUL_16
2291 * @retval None
2292 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLMul)2293 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
2294 {
2295 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
2296 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
2297 }
2298 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
2299
2300 /**
2301 * @brief Configure PLL clock source
2302 * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource
2303 * @param PLLSource This parameter can be one of the following values:
2304 * @arg @ref LL_RCC_PLLSOURCE_NONE
2305 * @arg @ref LL_RCC_PLLSOURCE_HSI (*)
2306 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
2307 * @arg @ref LL_RCC_PLLSOURCE_HSE
2308 * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*)
2309 *
2310 * (*) value not defined in all devices
2311 * @retval None
2312 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)2313 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
2314 {
2315 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
2316 }
2317
2318 /**
2319 * @brief Get the oscillator used as PLL clock source.
2320 * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
2321 * @retval Returned value can be one of the following values:
2322 * @arg @ref LL_RCC_PLLSOURCE_NONE
2323 * @arg @ref LL_RCC_PLLSOURCE_HSI (*)
2324 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
2325 * @arg @ref LL_RCC_PLLSOURCE_HSE
2326 *
2327 * (*) value not defined in all devices
2328 */
LL_RCC_PLL_GetMainSource(void)2329 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
2330 {
2331 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
2332 }
2333
2334 /**
2335 * @brief Get PLL multiplication Factor
2336 * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
2337 * @retval Returned value can be one of the following values:
2338 * @arg @ref LL_RCC_PLL_MUL_2
2339 * @arg @ref LL_RCC_PLL_MUL_3
2340 * @arg @ref LL_RCC_PLL_MUL_4
2341 * @arg @ref LL_RCC_PLL_MUL_5
2342 * @arg @ref LL_RCC_PLL_MUL_6
2343 * @arg @ref LL_RCC_PLL_MUL_7
2344 * @arg @ref LL_RCC_PLL_MUL_8
2345 * @arg @ref LL_RCC_PLL_MUL_9
2346 * @arg @ref LL_RCC_PLL_MUL_10
2347 * @arg @ref LL_RCC_PLL_MUL_11
2348 * @arg @ref LL_RCC_PLL_MUL_12
2349 * @arg @ref LL_RCC_PLL_MUL_13
2350 * @arg @ref LL_RCC_PLL_MUL_14
2351 * @arg @ref LL_RCC_PLL_MUL_15
2352 * @arg @ref LL_RCC_PLL_MUL_16
2353 */
LL_RCC_PLL_GetMultiplicator(void)2354 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
2355 {
2356 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
2357 }
2358
2359 /**
2360 * @brief Get PREDIV division factor for the main PLL
2361 * @note They can be written only when the PLL is disabled
2362 * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv
2363 * @retval Returned value can be one of the following values:
2364 * @arg @ref LL_RCC_PREDIV_DIV_1
2365 * @arg @ref LL_RCC_PREDIV_DIV_2
2366 * @arg @ref LL_RCC_PREDIV_DIV_3
2367 * @arg @ref LL_RCC_PREDIV_DIV_4
2368 * @arg @ref LL_RCC_PREDIV_DIV_5
2369 * @arg @ref LL_RCC_PREDIV_DIV_6
2370 * @arg @ref LL_RCC_PREDIV_DIV_7
2371 * @arg @ref LL_RCC_PREDIV_DIV_8
2372 * @arg @ref LL_RCC_PREDIV_DIV_9
2373 * @arg @ref LL_RCC_PREDIV_DIV_10
2374 * @arg @ref LL_RCC_PREDIV_DIV_11
2375 * @arg @ref LL_RCC_PREDIV_DIV_12
2376 * @arg @ref LL_RCC_PREDIV_DIV_13
2377 * @arg @ref LL_RCC_PREDIV_DIV_14
2378 * @arg @ref LL_RCC_PREDIV_DIV_15
2379 * @arg @ref LL_RCC_PREDIV_DIV_16
2380 */
LL_RCC_PLL_GetPrediv(void)2381 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
2382 {
2383 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV));
2384 }
2385
2386 /**
2387 * @}
2388 */
2389
2390 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
2391 * @{
2392 */
2393
2394 /**
2395 * @brief Clear LSI ready interrupt flag
2396 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
2397 * @retval None
2398 */
LL_RCC_ClearFlag_LSIRDY(void)2399 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
2400 {
2401 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
2402 }
2403
2404 /**
2405 * @brief Clear LSE ready interrupt flag
2406 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
2407 * @retval None
2408 */
LL_RCC_ClearFlag_LSERDY(void)2409 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2410 {
2411 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
2412 }
2413
2414 /**
2415 * @brief Clear HSI ready interrupt flag
2416 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2417 * @retval None
2418 */
LL_RCC_ClearFlag_HSIRDY(void)2419 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2420 {
2421 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
2422 }
2423
2424 /**
2425 * @brief Clear HSE ready interrupt flag
2426 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
2427 * @retval None
2428 */
LL_RCC_ClearFlag_HSERDY(void)2429 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2430 {
2431 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
2432 }
2433
2434 /**
2435 * @brief Clear PLL ready interrupt flag
2436 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
2437 * @retval None
2438 */
LL_RCC_ClearFlag_PLLRDY(void)2439 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
2440 {
2441 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
2442 }
2443
2444 /**
2445 * @brief Clear Clock security system interrupt flag
2446 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
2447 * @retval None
2448 */
LL_RCC_ClearFlag_HSECSS(void)2449 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
2450 {
2451 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
2452 }
2453
2454 /**
2455 * @brief Check if LSI ready interrupt occurred or not
2456 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
2457 * @retval State of bit (1 or 0).
2458 */
LL_RCC_IsActiveFlag_LSIRDY(void)2459 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
2460 {
2461 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
2462 }
2463
2464 /**
2465 * @brief Check if LSE ready interrupt occurred or not
2466 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2467 * @retval State of bit (1 or 0).
2468 */
LL_RCC_IsActiveFlag_LSERDY(void)2469 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2470 {
2471 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
2472 }
2473
2474 /**
2475 * @brief Check if HSI ready interrupt occurred or not
2476 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2477 * @retval State of bit (1 or 0).
2478 */
LL_RCC_IsActiveFlag_HSIRDY(void)2479 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2480 {
2481 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
2482 }
2483
2484 /**
2485 * @brief Check if HSE ready interrupt occurred or not
2486 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2487 * @retval State of bit (1 or 0).
2488 */
LL_RCC_IsActiveFlag_HSERDY(void)2489 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2490 {
2491 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
2492 }
2493
2494 #if defined(RCC_CFGR_MCOF)
2495 /**
2496 * @brief Check if switch to new MCO source is effective or not
2497 * @rmtoll CFGR MCOF LL_RCC_IsActiveFlag_MCO1
2498 * @retval State of bit (1 or 0).
2499 */
LL_RCC_IsActiveFlag_MCO1(void)2500 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void)
2501 {
2502 return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF));
2503 }
2504 #endif /* RCC_CFGR_MCOF */
2505
2506 /**
2507 * @brief Check if PLL ready interrupt occurred or not
2508 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
2509 * @retval State of bit (1 or 0).
2510 */
LL_RCC_IsActiveFlag_PLLRDY(void)2511 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
2512 {
2513 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
2514 }
2515
2516 /**
2517 * @brief Check if Clock security system interrupt occurred or not
2518 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
2519 * @retval State of bit (1 or 0).
2520 */
LL_RCC_IsActiveFlag_HSECSS(void)2521 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
2522 {
2523 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
2524 }
2525
2526 /**
2527 * @brief Check if RCC flag Independent Watchdog reset is set or not.
2528 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2529 * @retval State of bit (1 or 0).
2530 */
LL_RCC_IsActiveFlag_IWDGRST(void)2531 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2532 {
2533 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
2534 }
2535
2536 /**
2537 * @brief Check if RCC flag Low Power reset is set or not.
2538 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2539 * @retval State of bit (1 or 0).
2540 */
LL_RCC_IsActiveFlag_LPWRRST(void)2541 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2542 {
2543 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
2544 }
2545
2546 /**
2547 * @brief Check if RCC flag is set or not.
2548 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
2549 * @retval State of bit (1 or 0).
2550 */
LL_RCC_IsActiveFlag_OBLRST(void)2551 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
2552 {
2553 return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
2554 }
2555
2556 /**
2557 * @brief Check if RCC flag Pin reset is set or not.
2558 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2559 * @retval State of bit (1 or 0).
2560 */
LL_RCC_IsActiveFlag_PINRST(void)2561 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2562 {
2563 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
2564 }
2565
2566 /**
2567 * @brief Check if RCC flag POR/PDR reset is set or not.
2568 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
2569 * @retval State of bit (1 or 0).
2570 */
LL_RCC_IsActiveFlag_PORRST(void)2571 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
2572 {
2573 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
2574 }
2575
2576 /**
2577 * @brief Check if RCC flag Software reset is set or not.
2578 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2579 * @retval State of bit (1 or 0).
2580 */
LL_RCC_IsActiveFlag_SFTRST(void)2581 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2582 {
2583 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
2584 }
2585
2586 /**
2587 * @brief Check if RCC flag Window Watchdog reset is set or not.
2588 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2589 * @retval State of bit (1 or 0).
2590 */
LL_RCC_IsActiveFlag_WWDGRST(void)2591 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2592 {
2593 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
2594 }
2595
2596 #if defined(RCC_CSR_V18PWRRSTF)
2597 /**
2598 * @brief Check if RCC Reset flag of the 1.8 V domain is set or not.
2599 * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST
2600 * @retval State of bit (1 or 0).
2601 */
LL_RCC_IsActiveFlag_V18PWRRST(void)2602 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void)
2603 {
2604 return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF));
2605 }
2606 #endif /* RCC_CSR_V18PWRRSTF */
2607
2608 /**
2609 * @brief Set RMVF bit to clear the reset flags.
2610 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2611 * @retval None
2612 */
LL_RCC_ClearResetFlags(void)2613 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2614 {
2615 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2616 }
2617
2618 /**
2619 * @}
2620 */
2621
2622 /** @defgroup RCC_LL_EF_IT_Management IT Management
2623 * @{
2624 */
2625
2626 /**
2627 * @brief Enable LSI ready interrupt
2628 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
2629 * @retval None
2630 */
LL_RCC_EnableIT_LSIRDY(void)2631 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
2632 {
2633 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
2634 }
2635
2636 /**
2637 * @brief Enable LSE ready interrupt
2638 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
2639 * @retval None
2640 */
LL_RCC_EnableIT_LSERDY(void)2641 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
2642 {
2643 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
2644 }
2645
2646 /**
2647 * @brief Enable HSI ready interrupt
2648 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
2649 * @retval None
2650 */
LL_RCC_EnableIT_HSIRDY(void)2651 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
2652 {
2653 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
2654 }
2655
2656 /**
2657 * @brief Enable HSE ready interrupt
2658 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
2659 * @retval None
2660 */
LL_RCC_EnableIT_HSERDY(void)2661 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
2662 {
2663 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
2664 }
2665
2666 /**
2667 * @brief Enable PLL ready interrupt
2668 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
2669 * @retval None
2670 */
LL_RCC_EnableIT_PLLRDY(void)2671 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
2672 {
2673 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
2674 }
2675
2676 /**
2677 * @brief Disable LSI ready interrupt
2678 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
2679 * @retval None
2680 */
LL_RCC_DisableIT_LSIRDY(void)2681 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
2682 {
2683 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
2684 }
2685
2686 /**
2687 * @brief Disable LSE ready interrupt
2688 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
2689 * @retval None
2690 */
LL_RCC_DisableIT_LSERDY(void)2691 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
2692 {
2693 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
2694 }
2695
2696 /**
2697 * @brief Disable HSI ready interrupt
2698 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
2699 * @retval None
2700 */
LL_RCC_DisableIT_HSIRDY(void)2701 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
2702 {
2703 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
2704 }
2705
2706 /**
2707 * @brief Disable HSE ready interrupt
2708 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
2709 * @retval None
2710 */
LL_RCC_DisableIT_HSERDY(void)2711 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
2712 {
2713 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
2714 }
2715
2716 /**
2717 * @brief Disable PLL ready interrupt
2718 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
2719 * @retval None
2720 */
LL_RCC_DisableIT_PLLRDY(void)2721 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
2722 {
2723 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
2724 }
2725
2726 /**
2727 * @brief Checks if LSI ready interrupt source is enabled or disabled.
2728 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
2729 * @retval State of bit (1 or 0).
2730 */
LL_RCC_IsEnabledIT_LSIRDY(void)2731 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
2732 {
2733 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
2734 }
2735
2736 /**
2737 * @brief Checks if LSE ready interrupt source is enabled or disabled.
2738 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
2739 * @retval State of bit (1 or 0).
2740 */
LL_RCC_IsEnabledIT_LSERDY(void)2741 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
2742 {
2743 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
2744 }
2745
2746 /**
2747 * @brief Checks if HSI ready interrupt source is enabled or disabled.
2748 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
2749 * @retval State of bit (1 or 0).
2750 */
LL_RCC_IsEnabledIT_HSIRDY(void)2751 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
2752 {
2753 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
2754 }
2755
2756 /**
2757 * @brief Checks if HSE ready interrupt source is enabled or disabled.
2758 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
2759 * @retval State of bit (1 or 0).
2760 */
LL_RCC_IsEnabledIT_HSERDY(void)2761 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
2762 {
2763 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
2764 }
2765
2766 /**
2767 * @brief Checks if PLL ready interrupt source is enabled or disabled.
2768 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
2769 * @retval State of bit (1 or 0).
2770 */
LL_RCC_IsEnabledIT_PLLRDY(void)2771 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
2772 {
2773 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
2774 }
2775
2776 /**
2777 * @}
2778 */
2779
2780 #if defined(USE_FULL_LL_DRIVER)
2781 /** @defgroup RCC_LL_EF_Init De-initialization function
2782 * @{
2783 */
2784 ErrorStatus LL_RCC_DeInit(void);
2785 /**
2786 * @}
2787 */
2788
2789 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
2790 * @{
2791 */
2792 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2793 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
2794 #if defined(UART4) || defined(UART5)
2795 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
2796 #endif /* UART4 || UART5 */
2797 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
2798 #if defined(RCC_CFGR_I2SSRC)
2799 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
2800 #endif /* RCC_CFGR_I2SSRC */
2801 #if defined(USB_OTG_FS) || defined(USB)
2802 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
2803 #endif /* USB_OTG_FS || USB */
2804 #if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34))
2805 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
2806 #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
2807 #if defined(RCC_CFGR_SDPRE)
2808 uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource);
2809 #endif /*RCC_CFGR_SDPRE */
2810 #if defined(CEC)
2811 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
2812 #endif /* CEC */
2813 #if defined(RCC_CFGR3_TIMSW)
2814 uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
2815 #endif /*RCC_CFGR3_TIMSW*/
2816 uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource);
2817 /**
2818 * @}
2819 */
2820 #endif /* USE_FULL_LL_DRIVER */
2821
2822 /**
2823 * @}
2824 */
2825
2826 /**
2827 * @}
2828 */
2829
2830 #endif /* RCC */
2831
2832 /**
2833 * @}
2834 */
2835
2836 #ifdef __cplusplus
2837 }
2838 #endif
2839
2840 #endif /* __STM32F3xx_LL_RCC_H */
2841
2842 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2843
