1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32N6xx_LL_RCC_H
21 #define STM32N6xx_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32n6xx.h"
29 #include <math.h>
30
31 /** @addtogroup STM32N6xx_LL_Driver
32 * @{
33 */
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
43 * @{
44 */
45
46 /**
47 * @}
48 */
49
50 /* Private constants ---------------------------------------------------------*/
51 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
52 * @{
53 */
54 /* Constants for LL_CLKSOURCE_xxx() macros
55 31 24 16 8 0
56 --------------------------------------------------------
57 | Mask | ClkSource | Bit | Register |
58 | | Config | Position | Offset |
59 --------------------------------------------------------*/
60
61 /* Clock source register offset Vs CCIPR1 register */
62 #define CCIPR1_OFFSET 0x0UL
63 #define CCIPR2_OFFSET 0x4UL
64 #define CCIPR3_OFFSET 0x8UL
65 #define CCIPR4_OFFSET 0xCUL
66 #define CCIPR5_OFFSET 0x10UL
67 #define CCIPR6_OFFSET 0x14UL
68 #define CCIPR7_OFFSET 0x18UL
69 #define CCIPR8_OFFSET 0x1CUL
70 #define CCIPR9_OFFSET 0x20UL
71 #define CCIPR12_OFFSET 0x2CUL
72 #define CCIPR13_OFFSET 0x30UL
73 #define CCIPR14_OFFSET 0x34UL
74
75 #define LL_RCC_REG_SHIFT 0U
76 #define LL_RCC_POS_SHIFT 8U
77 #define LL_RCC_CONFIG_SHIFT 16U
78 #define LL_RCC_MASK_SHIFT 24U
79 /**
80 * @}
81 */
82
83 /* Private macros ------------------------------------------------------------*/
84 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
85 * @{
86 */
87 #if !defined(UNUSED)
88 #define UNUSED(x) ((void)(x))
89 #endif /* UNUSED */
90
91 #define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)
92
93 #define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) &\
94 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
95
96 #define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) &\
97 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
98
99 #define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL)
100
101 #define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
102 (( __POS__ ) << LL_RCC_POS_SHIFT) | \
103 (( __REG__ ) << LL_RCC_REG_SHIFT) | \
104 (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
105 /**
106 * @}
107 */
108
109 /* Exported types ------------------------------------------------------------*/
110 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
111 * @{
112 */
113
114 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
115 * @{
116 */
117
118 /**
119 * @brief RCC Clocks Frequency Structure
120 */
121 typedef struct
122 {
123 uint32_t SYSCLK_Frequency;
124 uint32_t CPUCLK_Frequency;
125 uint32_t HCLK_Frequency;
126 uint32_t PCLK1_Frequency;
127 uint32_t PCLK2_Frequency;
128 uint32_t PCLK4_Frequency;
129 uint32_t PCLK5_Frequency;
130 } LL_RCC_ClocksTypeDef;
131
132 /**
133 * @}
134 */
135
136 /**
137 * @}
138 */
139
140 /* Exported constants --------------------------------------------------------*/
141 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
142 * @{
143 */
144
145 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
146 * @brief Defines used to adapt values of different oscillators
147 * @note These values could be modified in the user environment according to
148 * HW set-up.
149 * @{
150 */
151 #if !defined (HSE_VALUE)
152 #define HSE_VALUE 48000000U /*!< Value of the HSE oscillator in Hz */ /* N6 FPGA was 30 MHz */
153 #endif /* HSE_VALUE */
154
155 #if !defined (HSI_VALUE)
156 #define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */ /* N6 FPGA was 48 MHz */
157 #endif /* HSI_VALUE */
158
159 #if !defined (MSI_VALUE)
160 #define MSI_VALUE 4000000U /*!< Value of the MSI oscillator in Hz */
161 #endif /* MSI_VALUE */
162
163 #if !defined (LSE_VALUE)
164 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ /* N6 FPGA was 32 KHz*/
165 #endif /* LSE_VALUE */
166
167 #if !defined (LSI_VALUE)
168 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
169 #endif /* LSI_VALUE */
170
171 #if !defined (EXTERNAL_CLOCK_VALUE)
172 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
173 #endif /* EXTERNAL_CLOCK_VALUE */
174
175 /**
176 * @}
177 */
178
179 /** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider
180 * @{
181 */
182 #define LL_RCC_HSI_DIV_1 0U
183 #define LL_RCC_HSI_DIV_2 RCC_HSICFGR_HSIDIV_0
184 #define LL_RCC_HSI_DIV_4 RCC_HSICFGR_HSIDIV_1
185 #define LL_RCC_HSI_DIV_8 RCC_HSICFGR_HSIDIV
186 /**
187 * @}
188 */
189
190 /** @defgroup RCC_LL_EC_MSIFREQ MSI oscillator frequency select
191 * @{
192 */
193 #define LL_RCC_MSI_FREQ_4MHZ 0U
194 #define LL_RCC_MSI_FREQ_16MHZ RCC_MSICFGR_MSIFREQSEL
195 /**
196 * @}
197 */
198
199 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
200 * @{
201 */
202 #define LL_RCC_LSEDRIVE_LOW 0U
203 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_LSECFGR_LSEDRV_1
204 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_LSECFGR_LSEDRV_0
205 #define LL_RCC_LSEDRIVE_HIGH RCC_LSECFGR_LSEDRV
206 /**
207 * @}
208 */
209
210 /** @defgroup RCC_LL_EC_HSECSSBYP_DIV HSI divider to apply for replacement of HSE on CSS bypass
211 * @{
212 */
213 #define LL_RCC_HSECSSBYP_DIV_1 0U
214 #define LL_RCC_HSECSSBYP_DIV_2 RCC_HSECFGR_HSECSSBPRE_0
215 #define LL_RCC_HSECSSBYP_DIV_3 RCC_HSECFGR_HSECSSBPRE_1
216 #define LL_RCC_HSECSSBYP_DIV_4 (RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0)
217 #define LL_RCC_HSECSSBYP_DIV_5 RCC_HSECFGR_HSECSSBPRE_2
218 #define LL_RCC_HSECSSBYP_DIV_6 (RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_0)
219 #define LL_RCC_HSECSSBYP_DIV_7 (RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_1)
220 #define LL_RCC_HSECSSBYP_DIV_8 (RCC_HSECFGR_HSECSSBPRE_2 |\
221 RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0)
222 #define LL_RCC_HSECSSBYP_DIV_9 RCC_HSECFGR_HSECSSBPRE_3
223 #define LL_RCC_HSECSSBYP_DIV_10 (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_0)
224 #define LL_RCC_HSECSSBYP_DIV_11 (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_1)
225 #define LL_RCC_HSECSSBYP_DIV_12 (RCC_HSECFGR_HSECSSBPRE_3 |\
226 RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0)
227 #define LL_RCC_HSECSSBYP_DIV_13 (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_2)
228 #define LL_RCC_HSECSSBYP_DIV_14 (RCC_HSECFGR_HSECSSBPRE_3 |\
229 RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_0)
230 #define LL_RCC_HSECSSBYP_DIV_15 (RCC_HSECFGR_HSECSSBPRE_3 |\
231 RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_1)
232 #define LL_RCC_HSECSSBYP_DIV_16 (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_2 |\
233 RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0)
234 /**
235 * @}
236 */
237
238
239 /** @defgroup RCC_LL_EC_CPU_CLKSOURCE CPU clock switch
240 * @{
241 */
242 #define LL_RCC_CPU_CLKSOURCE_HSI 0U /*!< Select HSI as CPU clock */
243 #define LL_RCC_CPU_CLKSOURCE_MSI RCC_CFGR1_CPUSW_0 /*!< Select MSI as CPU clock */
244 #define LL_RCC_CPU_CLKSOURCE_HSE RCC_CFGR1_CPUSW_1 /*!< Select HSE as CPU clock */
245 #define LL_RCC_CPU_CLKSOURCE_IC1 (RCC_CFGR1_CPUSW_1 | RCC_CFGR1_CPUSW_0) /*!< Select IC1 as CPU clock */
246 /**
247 * @}
248 */
249
250 /** @defgroup RCC_LL_EC_CPU_CLKSOURCE_STATUS CPU clock switch status
251 * @{
252 */
253 #define LL_RCC_CPU_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as CPU clock */
254 #define LL_RCC_CPU_CLKSOURCE_STATUS_MSI RCC_CFGR1_CPUSWS_0 /*!< MSI used as CPU clock */
255 #define LL_RCC_CPU_CLKSOURCE_STATUS_HSE RCC_CFGR1_CPUSWS_1 /*!< HSE used as CPU clock */
256 #define LL_RCC_CPU_CLKSOURCE_STATUS_IC1 (RCC_CFGR1_CPUSWS_1 | RCC_CFGR1_CPUSWS_0) /*!< IC1 used as CPU clock */
257 /**
258 * @}
259 */
260
261 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System bus clock switch
262 * @{
263 */
264 #define LL_RCC_SYS_CLKSOURCE_HSI 0U /*!< Select HSI as system bus clocks */
265 #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR1_SYSSW_0 /*!< Select MSI as system bus clocks */
266 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SYSSW_1 /*!< Select HSE as system bus clocks */
267 #define LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11 (RCC_CFGR1_SYSSW_1 | RCC_CFGR1_SYSSW_0) /*!< Select IC2/IC6/IC11 as system bus clocks */
268 /**
269 * @}
270 */
271
272 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System bus clock switch status
273 * @{
274 */
275 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as system bus clocks */
276 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR1_SYSSWS_0 /*!< MSI used as system bus clocks */
277 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SYSSWS_1 /*!< HSE used as system bus clocks */
278 #define LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11 (RCC_CFGR1_SYSSWS_1 | RCC_CFGR1_SYSSWS_0) /*!< IC2/IC6/IC11 used as system bus clocks */
279 /**
280 * @}
281 */
282
283 /** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source
284 * @{
285 */
286 #define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI 0U
287 #define LL_RCC_SYSWAKEUP_CLKSOURCE_MSI RCC_CFGR1_STOPWUCK
288 /**
289 * @}
290 */
291
292 /** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler
293 * @{
294 */
295 #define LL_RCC_AHB_DIV_1 0U
296 #define LL_RCC_AHB_DIV_2 RCC_CFGR2_HPRE_0
297 #define LL_RCC_AHB_DIV_4 RCC_CFGR2_HPRE_1
298 #define LL_RCC_AHB_DIV_8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0)
299 #define LL_RCC_AHB_DIV_16 RCC_CFGR2_HPRE_2
300 #define LL_RCC_AHB_DIV_32 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0)
301 #define LL_RCC_AHB_DIV_64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1)
302 #define LL_RCC_AHB_DIV_128 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0)
303 /**
304 * @}
305 */
306
307 /** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler
308 * @{
309 */
310 #define LL_RCC_APB1_DIV_1 0U
311 #define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_0
312 #define LL_RCC_APB1_DIV_4 RCC_CFGR2_PPRE1_1
313 #define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0)
314 #define LL_RCC_APB1_DIV_16 RCC_CFGR2_PPRE1_2
315 #define LL_RCC_APB1_DIV_32 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0)
316 #define LL_RCC_APB1_DIV_64 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1)
317 #define LL_RCC_APB1_DIV_128 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0)
318 /**
319 * @}
320 */
321
322 /** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler
323 * @{
324 */
325 #define LL_RCC_APB2_DIV_1 0U
326 #define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_0
327 #define LL_RCC_APB2_DIV_4 RCC_CFGR2_PPRE2_1
328 #define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0)
329 #define LL_RCC_APB2_DIV_16 RCC_CFGR2_PPRE2_2
330 #define LL_RCC_APB2_DIV_32 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0)
331 #define LL_RCC_APB2_DIV_64 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1)
332 #define LL_RCC_APB2_DIV_128 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0)
333 /**
334 * @}
335 */
336
337 /** @defgroup RCC_LL_EC_APB4_DIV APB4 prescaler
338 * @{
339 */
340 #define LL_RCC_APB4_DIV_1 0U
341 #define LL_RCC_APB4_DIV_2 RCC_CFGR2_PPRE4_0
342 #define LL_RCC_APB4_DIV_4 RCC_CFGR2_PPRE4_1
343 #define LL_RCC_APB4_DIV_8 (RCC_CFGR2_PPRE4_1 | RCC_CFGR2_PPRE4_0)
344 #define LL_RCC_APB4_DIV_16 RCC_CFGR2_PPRE4_2
345 #define LL_RCC_APB4_DIV_32 (RCC_CFGR2_PPRE4_2 | RCC_CFGR2_PPRE4_0)
346 #define LL_RCC_APB4_DIV_64 (RCC_CFGR2_PPRE4_2 | RCC_CFGR2_PPRE4_1)
347 #define LL_RCC_APB4_DIV_128 (RCC_CFGR2_PPRE4_2 | RCC_CFGR2_PPRE4_1 | RCC_CFGR2_PPRE4_0)
348 /**
349 * @}
350 */
351
352 /** @defgroup RCC_LL_EC_APB5_DIV APB5 prescaler
353 * @{
354 */
355 #define LL_RCC_APB5_DIV_1 0U
356 #define LL_RCC_APB5_DIV_2 RCC_CFGR2_PPRE5_0
357 #define LL_RCC_APB5_DIV_4 RCC_CFGR2_PPRE5_1
358 #define LL_RCC_APB5_DIV_8 (RCC_CFGR2_PPRE5_1 | RCC_CFGR2_PPRE5_0)
359 #define LL_RCC_APB5_DIV_16 RCC_CFGR2_PPRE5_2
360 #define LL_RCC_APB5_DIV_32 (RCC_CFGR2_PPRE5_2 | RCC_CFGR2_PPRE5_0)
361 #define LL_RCC_APB5_DIV_64 (RCC_CFGR2_PPRE5_2 | RCC_CFGR2_PPRE5_1)
362 #define LL_RCC_APB5_DIV_128 (RCC_CFGR2_PPRE5_2 | RCC_CFGR2_PPRE5_1 | RCC_CFGR2_PPRE5_0)
363 /**
364 * @}
365 */
366
367 /** @defgroup RCC_LL_EC_MCOx MCO selection
368 * @{
369 */
370 #define LL_RCC_MCO1 RCC_MISCENR_MCO1EN
371 #define LL_RCC_MCO2 RCC_MISCENR_MCO2EN
372 /**
373 * @}
374 */
375
376 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
377 * @{
378 */
379 #define LL_RCC_MCO1SOURCE_HSI ((RCC_CCIPR5_MCO1SEL<<16U) | 0U)
380 #define LL_RCC_MCO1SOURCE_LSE ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_0)
381 #define LL_RCC_MCO1SOURCE_MSI ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_1)
382 #define LL_RCC_MCO1SOURCE_LSI ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_1 | RCC_CCIPR5_MCO1SEL_0)
383 #define LL_RCC_MCO1SOURCE_HSE ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_2)
384 #define LL_RCC_MCO1SOURCE_IC5 ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_2 | RCC_CCIPR5_MCO1SEL_0)
385 #define LL_RCC_MCO1SOURCE_IC10 ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_2 | RCC_CCIPR5_MCO1SEL_1)
386 #define LL_RCC_MCO1SOURCE_SYSA ((RCC_CCIPR5_MCO1SEL<<16U) |\
387 RCC_CCIPR5_MCO1SEL_2 | RCC_CCIPR5_MCO1SEL_1 | RCC_CCIPR5_MCO1SEL_0)
388 #define LL_RCC_MCO2SOURCE_HSI ((RCC_CCIPR5_MCO2SEL<<16U) | 0U)
389 #define LL_RCC_MCO2SOURCE_LSE ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_0)
390 #define LL_RCC_MCO2SOURCE_MSI ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_1)
391 #define LL_RCC_MCO2SOURCE_LSI ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_1 | RCC_CCIPR5_MCO2SEL_0)
392 #define LL_RCC_MCO2SOURCE_HSE ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_2)
393 #define LL_RCC_MCO2SOURCE_IC15 ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_2 | RCC_CCIPR5_MCO2SEL_0)
394 #define LL_RCC_MCO2SOURCE_IC20 ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_2 | RCC_CCIPR5_MCO2SEL_1)
395 #define LL_RCC_MCO2SOURCE_SYSB ((RCC_CCIPR5_MCO2SEL<<16U) |\
396 RCC_CCIPR5_MCO2SEL_2 | RCC_CCIPR5_MCO2SEL_1 | RCC_CCIPR5_MCO2SEL_0)
397 /**
398 * @}
399 */
400
401 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
402 * @{
403 */
404 #define LL_RCC_MCO1_DIV_1 (RCC_CCIPR5_MCO1PRE<<16U)
405 #define LL_RCC_MCO1_DIV_2 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_0)
406 #define LL_RCC_MCO1_DIV_3 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_1)
407 #define LL_RCC_MCO1_DIV_4 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_1 | RCC_CCIPR5_MCO1PRE_0)
408 #define LL_RCC_MCO1_DIV_5 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_2)
409 #define LL_RCC_MCO1_DIV_6 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_0)
410 #define LL_RCC_MCO1_DIV_7 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_1)
411 #define LL_RCC_MCO1_DIV_8 ((RCC_CCIPR5_MCO1PRE<<16U) |\
412 RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_1 | RCC_CCIPR5_MCO1PRE_0)
413 #define LL_RCC_MCO1_DIV_9 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3)
414 #define LL_RCC_MCO1_DIV_10 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_0)
415 #define LL_RCC_MCO1_DIV_11 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_1)
416 #define LL_RCC_MCO1_DIV_12 ((RCC_CCIPR5_MCO1PRE<<16U) |\
417 RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_1 | RCC_CCIPR5_MCO1PRE_0)
418 #define LL_RCC_MCO1_DIV_13 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_2)
419 #define LL_RCC_MCO1_DIV_14 ((RCC_CCIPR5_MCO1PRE<<16U) |\
420 RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_0)
421 #define LL_RCC_MCO1_DIV_15 ((RCC_CCIPR5_MCO1PRE<<16U) |\
422 RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_1)
423 #define LL_RCC_MCO1_DIV_16 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE)
424 #define LL_RCC_MCO2_DIV_1 (RCC_CCIPR5_MCO2PRE<<16U)
425 #define LL_RCC_MCO2_DIV_2 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_0)
426 #define LL_RCC_MCO2_DIV_3 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_1)
427 #define LL_RCC_MCO2_DIV_4 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_1 | RCC_CCIPR5_MCO2PRE_0)
428 #define LL_RCC_MCO2_DIV_5 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_2)
429 #define LL_RCC_MCO2_DIV_6 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_0)
430 #define LL_RCC_MCO2_DIV_7 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_1)
431 #define LL_RCC_MCO2_DIV_8 ((RCC_CCIPR5_MCO2PRE<<16U) |\
432 RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_1 | RCC_CCIPR5_MCO2PRE_0)
433 #define LL_RCC_MCO2_DIV_9 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3)
434 #define LL_RCC_MCO2_DIV_10 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_0)
435 #define LL_RCC_MCO2_DIV_11 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_1)
436 #define LL_RCC_MCO2_DIV_12 ((RCC_CCIPR5_MCO2PRE<<16U) |\
437 RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_1 | RCC_CCIPR5_MCO2PRE_0)
438 #define LL_RCC_MCO2_DIV_13 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_2)
439 #define LL_RCC_MCO2_DIV_14 ((RCC_CCIPR5_MCO2PRE<<16U) |\
440 RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_0)
441 #define LL_RCC_MCO2_DIV_15 ((RCC_CCIPR5_MCO2PRE<<16U) |\
442 RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_1)
443 #define LL_RCC_MCO2_DIV_16 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE)
444
445 /**
446 * @}
447 */
448
449 /** @defgroup RCC_LL_EC_RTC_HSE_DIV Prescaler for RTC clock
450 * @{
451 */
452 #define LL_RCC_RTC_HSE_DIV_1 0U
453 #define LL_RCC_RTC_HSE_DIV_2 RCC_CCIPR7_RTCPRE_0
454 #define LL_RCC_RTC_HSE_DIV_3 RCC_CCIPR7_RTCPRE_1
455 #define LL_RCC_RTC_HSE_DIV_4 (RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
456 #define LL_RCC_RTC_HSE_DIV_5 RCC_CCIPR7_RTCPRE_2
457 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
458 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
459 #define LL_RCC_RTC_HSE_DIV_8 (RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
460 #define LL_RCC_RTC_HSE_DIV_9 RCC_CCIPR7_RTCPRE_3
461 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0)
462 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1)
463 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
464 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2)
465 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
466 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
467 #define LL_RCC_RTC_HSE_DIV_16 (RCC_CCIPR7_RTCPRE_3 |\
468 RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
469 #define LL_RCC_RTC_HSE_DIV_17 RCC_CCIPR7_RTCPRE_4
470 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_0)
471 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1)
472 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
473 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2)
474 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
475 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
476 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CCIPR7_RTCPRE_4 |\
477 RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
478 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3)
479 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0)
480 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1)
481 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CCIPR7_RTCPRE_4 |\
482 RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
483 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2)
484 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CCIPR7_RTCPRE_4 |\
485 RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
486 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CCIPR7_RTCPRE_4 |\
487 RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
488 #define LL_RCC_RTC_HSE_DIV_32 (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 |\
489 RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
490 #define LL_RCC_RTC_HSE_DIV_33 RCC_CCIPR7_RTCPRE_5
491 #define LL_RCC_RTC_HSE_DIV_34 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_0)
492 #define LL_RCC_RTC_HSE_DIV_35 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_1)
493 #define LL_RCC_RTC_HSE_DIV_36 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
494 #define LL_RCC_RTC_HSE_DIV_37 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_2)
495 #define LL_RCC_RTC_HSE_DIV_38 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
496 #define LL_RCC_RTC_HSE_DIV_39 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
497 #define LL_RCC_RTC_HSE_DIV_40 (RCC_CCIPR7_RTCPRE_5 |\
498 RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
499 #define LL_RCC_RTC_HSE_DIV_41 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3)
500 #define LL_RCC_RTC_HSE_DIV_42 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0)
501 #define LL_RCC_RTC_HSE_DIV_43 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1)
502 #define LL_RCC_RTC_HSE_DIV_44 (RCC_CCIPR7_RTCPRE_5 |\
503 RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
504 #define LL_RCC_RTC_HSE_DIV_45 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2)
505 #define LL_RCC_RTC_HSE_DIV_46 (RCC_CCIPR7_RTCPRE_5 |\
506 RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
507 #define LL_RCC_RTC_HSE_DIV_47 (RCC_CCIPR7_RTCPRE_5 |\
508 RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
509 #define LL_RCC_RTC_HSE_DIV_48 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 |\
510 RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
511 #define LL_RCC_RTC_HSE_DIV_49 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4)
512 #define LL_RCC_RTC_HSE_DIV_50 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_0)
513 #define LL_RCC_RTC_HSE_DIV_51 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1)
514 #define LL_RCC_RTC_HSE_DIV_52 (RCC_CCIPR7_RTCPRE_5 |\
515 RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
516 #define LL_RCC_RTC_HSE_DIV_53 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2)
517 #define LL_RCC_RTC_HSE_DIV_54 (RCC_CCIPR7_RTCPRE_5 |\
518 RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
519 #define LL_RCC_RTC_HSE_DIV_55 (RCC_CCIPR7_RTCPRE_5 |\
520 RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
521 #define LL_RCC_RTC_HSE_DIV_56 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 |\
522 RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
523 #define LL_RCC_RTC_HSE_DIV_57 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3)
524 #define LL_RCC_RTC_HSE_DIV_58 (RCC_CCIPR7_RTCPRE_5 |\
525 RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0)
526 #define LL_RCC_RTC_HSE_DIV_59 (RCC_CCIPR7_RTCPRE_5 |\
527 RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1)
528 #define LL_RCC_RTC_HSE_DIV_60 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\
529 RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
530 #define LL_RCC_RTC_HSE_DIV_61 (RCC_CCIPR7_RTCPRE_5 |\
531 RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2)
532 #define LL_RCC_RTC_HSE_DIV_62 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\
533 RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
534 #define LL_RCC_RTC_HSE_DIV_63 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\
535 RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
536 #define LL_RCC_RTC_HSE_DIV_64 (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\
537 RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
538 /**
539 * @}
540 */
541
542 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
543 * @{
544 */
545 #define LL_RCC_ADC_CLKSOURCE_HCLK 0U
546 #define LL_RCC_ADC_CLKSOURCE_CLKP RCC_CCIPR1_ADC12SEL_0
547 #define LL_RCC_ADC_CLKSOURCE_IC7 RCC_CCIPR1_ADC12SEL_1
548 #define LL_RCC_ADC_CLKSOURCE_IC8 (RCC_CCIPR1_ADC12SEL_1 | RCC_CCIPR1_ADC12SEL_0)
549 #define LL_RCC_ADC_CLKSOURCE_MSI RCC_CCIPR1_ADC12SEL_2
550 #define LL_RCC_ADC_CLKSOURCE_HSI (RCC_CCIPR1_ADC12SEL_2 | RCC_CCIPR1_ADC12SEL_0)
551 #define LL_RCC_ADC_CLKSOURCE_I2S_CKIN (RCC_CCIPR1_ADC12SEL_2 | RCC_CCIPR1_ADC12SEL_1)
552 #define LL_RCC_ADC_CLKSOURCE_TIMG (RCC_CCIPR1_ADC12SEL_2 | RCC_CCIPR1_ADC12SEL_1 | RCC_CCIPR1_ADC12SEL_0)
553 /**
554 * @}
555 */
556
557 /** @defgroup RCC_LL_EC_ADF_CLKSOURCE Peripheral ADF clock source selection
558 * @{
559 */
560 #define LL_RCC_ADF1_CLKSOURCE_HCLK 0U
561 #define LL_RCC_ADF1_CLKSOURCE_CLKP RCC_CCIPR1_ADF1SEL_0
562 #define LL_RCC_ADF1_CLKSOURCE_IC7 RCC_CCIPR1_ADF1SEL_1
563 #define LL_RCC_ADF1_CLKSOURCE_IC8 (RCC_CCIPR1_ADF1SEL_1 | RCC_CCIPR1_ADF1SEL_0)
564 #define LL_RCC_ADF1_CLKSOURCE_MSI RCC_CCIPR1_ADF1SEL_2
565 #define LL_RCC_ADF1_CLKSOURCE_HSI (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_0)
566 #define LL_RCC_ADF1_CLKSOURCE_I2S_CKIN (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_1)
567 #define LL_RCC_ADF1_CLKSOURCE_TIMG (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_1 | RCC_CCIPR1_ADF1SEL_0)
568 /**
569 * @}
570 */
571
572 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection
573 * @{
574 */
575 #define LL_RCC_CLKP_CLKSOURCE_HSI 0U
576 #define LL_RCC_CLKP_CLKSOURCE_MSI RCC_CCIPR7_PERSEL_0
577 #define LL_RCC_CLKP_CLKSOURCE_HSE RCC_CCIPR7_PERSEL_1
578 #define LL_RCC_CLKP_CLKSOURCE_IC19 (RCC_CCIPR7_PERSEL_1 | RCC_CCIPR7_PERSEL_0)
579 #define LL_RCC_CLKP_CLKSOURCE_IC5 RCC_CCIPR7_PERSEL_2
580 #define LL_RCC_CLKP_CLKSOURCE_IC10 (RCC_CCIPR7_PERSEL_2 | RCC_CCIPR7_PERSEL_0)
581 #define LL_RCC_CLKP_CLKSOURCE_IC15 (RCC_CCIPR7_PERSEL_2 | RCC_CCIPR7_PERSEL_1)
582 #define LL_RCC_CLKP_CLKSOURCE_IC20 (RCC_CCIPR7_PERSEL_2 | RCC_CCIPR7_PERSEL_1 | RCC_CCIPR7_PERSEL_0)
583 /**
584 * @}
585 */
586
587 /** @defgroup RCC_LL_EC_DCMIPP_CLKSOURCE Peripheral DCMIPP clock source selection
588 * @{
589 */
590 #define LL_RCC_DCMIPP_CLKSOURCE_PCLK5 0U
591 #define LL_RCC_DCMIPP_CLKSOURCE_CLKP RCC_CCIPR1_DCMIPPSEL_0
592 #define LL_RCC_DCMIPP_CLKSOURCE_IC17 RCC_CCIPR1_DCMIPPSEL_1
593 #define LL_RCC_DCMIPP_CLKSOURCE_HSI (RCC_CCIPR1_DCMIPPSEL_1 | RCC_CCIPR1_DCMIPPSEL_0)
594 /**
595 * @}
596 */
597
598 /** @defgroup RCC_LL_EC_ETH_CLKSOURCE Peripheral ETH kernel clock source selection
599 * @{
600 */
601 #define LL_RCC_ETH1_CLKSOURCE_HCLK 0U
602 #define LL_RCC_ETH1_CLKSOURCE_CLKP RCC_CCIPR2_ETH1CLKSEL_0
603 #define LL_RCC_ETH1_CLKSOURCE_IC12 RCC_CCIPR2_ETH1CLKSEL_1
604 #define LL_RCC_ETH1_CLKSOURCE_HSE (RCC_CCIPR2_ETH1CLKSEL_1 | RCC_CCIPR2_ETH1CLKSEL_0)
605 /**
606 * @}
607 */
608
609 /** @defgroup RCC_LL_EC_ETHPHY_IF Peripheral ETH PHY interface selection
610 * @{
611 */
612 #define LL_RCC_ETH1PHY_IF_MII 0U
613 #define LL_RCC_ETH1PHY_IF_RGMII RCC_CCIPR2_ETH1SEL_0
614 #define LL_RCC_ETH1PHY_IF_RMII RCC_CCIPR2_ETH1SEL_2
615 /**
616 * @}
617 */
618
619 /** @defgroup RCC_LL_EC_ETHREFRX_CLKSOURCE Peripheral ETH Reference RX clock source selection
620 * @{
621 */
622 #define LL_RCC_ETH1REFRX_CLKSOURCE_EXT 0U
623 #define LL_RCC_ETH1REFRX_CLKSOURCE_INT RCC_CCIPR2_ETH1REFCLKSEL
624 /**
625 * @}
626 */
627
628 /** @defgroup RCC_LL_EC_ETHREFTX_CLKSOURCE Peripheral ETH Reference TX clock source selection
629 * @{
630 */
631 #define LL_RCC_ETH1REFTX_CLKSOURCE_EXT 0U
632 #define LL_RCC_ETH1REFTX_CLKSOURCE_INT RCC_CCIPR2_ETH1GTXCLKSEL
633 /**
634 * @}
635 */
636
637 /** @defgroup RCC_LL_EC_ETHPTP_CLKSOURCE Peripheral ETH PTP kernel clock source selection
638 * @{
639 */
640 #define LL_RCC_ETH1PTP_CLKSOURCE_HCLK 0U
641 #define LL_RCC_ETH1PTP_CLKSOURCE_CLKP RCC_CCIPR2_ETH1PTPSEL_0
642 #define LL_RCC_ETH1PTP_CLKSOURCE_IC13 RCC_CCIPR2_ETH1PTPSEL_1
643 #define LL_RCC_ETH1PTP_CLKSOURCE_HSE (RCC_CCIPR2_ETH1PTPSEL_1 | RCC_CCIPR2_ETH1PTPSEL_0)
644 /**
645 * @}
646 */
647
648 /** @defgroup RCC_LL_EC_ETH1PTP_DIV ETH1 PTP kernel clock divider selection
649 * @{
650 */
651 #define LL_RCC_ETH1PTP_DIV_1 0U
652 #define LL_RCC_ETH1PTP_DIV_2 RCC_CCIPR2_ETH1PTPDIV_0
653 #define LL_RCC_ETH1PTP_DIV_3 RCC_CCIPR2_ETH1PTPDIV_1
654 #define LL_RCC_ETH1PTP_DIV_4 (RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0)
655 #define LL_RCC_ETH1PTP_DIV_5 RCC_CCIPR2_ETH1PTPDIV_2
656 #define LL_RCC_ETH1PTP_DIV_6 (RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_0)
657 #define LL_RCC_ETH1PTP_DIV_7 (RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1)
658 #define LL_RCC_ETH1PTP_DIV_8 (RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0)
659 #define LL_RCC_ETH1PTP_DIV_9 RCC_CCIPR2_ETH1PTPDIV_3
660 #define LL_RCC_ETH1PTP_DIV_10 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_0)
661 #define LL_RCC_ETH1PTP_DIV_11 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_1)
662 #define LL_RCC_ETH1PTP_DIV_12 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0)
663 #define LL_RCC_ETH1PTP_DIV_13 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_2)
664 #define LL_RCC_ETH1PTP_DIV_14 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_0)
665 #define LL_RCC_ETH1PTP_DIV_15 (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1)
666 #define LL_RCC_ETH1PTP_DIV_16 (RCC_CCIPR2_ETH1PTPDIV_3 |\
667 RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0)
668 /**
669 * @}
670 */
671
672 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
673 * @{
674 */
675 #define LL_RCC_FDCAN_CLKSOURCE_PCLK1 0U
676 #define LL_RCC_FDCAN_CLKSOURCE_CLKP RCC_CCIPR3_FDCANSEL_0
677 #define LL_RCC_FDCAN_CLKSOURCE_IC19 RCC_CCIPR3_FDCANSEL_1
678 #define LL_RCC_FDCAN_CLKSOURCE_HSE (RCC_CCIPR3_FDCANSEL_1 | RCC_CCIPR3_FDCANSEL_0)
679 /**
680 * @}
681 */
682
683 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection
684 * @{
685 */
686 #define LL_RCC_FMC_CLKSOURCE_HCLK 0U
687 #define LL_RCC_FMC_CLKSOURCE_CLKP RCC_CCIPR3_FMCSEL_0
688 #define LL_RCC_FMC_CLKSOURCE_IC3 RCC_CCIPR3_FMCSEL_1
689 #define LL_RCC_FMC_CLKSOURCE_IC4 (RCC_CCIPR3_FMCSEL_1 | RCC_CCIPR3_FMCSEL_0)
690 /**
691 * @}
692 */
693
694 /** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2C clock source selection
695 * @{
696 */
697 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0U)
698 #define LL_RCC_I2C1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\
699 RCC_CCIPR4_I2C1SEL_0)
700 #define LL_RCC_I2C1_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\
701 RCC_CCIPR4_I2C1SEL_1)
702 #define LL_RCC_I2C1_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\
703 RCC_CCIPR4_I2C1SEL_1 | RCC_CCIPR4_I2C1SEL_0)
704 #define LL_RCC_I2C1_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\
705 RCC_CCIPR4_I2C1SEL_2)
706 #define LL_RCC_I2C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\
707 RCC_CCIPR4_I2C1SEL_2| RCC_CCIPR4_I2C1SEL_0)
708
709 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0U)
710 #define LL_RCC_I2C2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\
711 RCC_CCIPR4_I2C2SEL_0)
712 #define LL_RCC_I2C2_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\
713 RCC_CCIPR4_I2C2SEL_1)
714 #define LL_RCC_I2C2_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\
715 RCC_CCIPR4_I2C2SEL_1 | RCC_CCIPR4_I2C2SEL_0)
716 #define LL_RCC_I2C2_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\
717 RCC_CCIPR4_I2C2SEL_2)
718 #define LL_RCC_I2C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\
719 RCC_CCIPR4_I2C2SEL_2 | RCC_CCIPR4_I2C2SEL_0)
720
721 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0U)
722 #define LL_RCC_I2C3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\
723 RCC_CCIPR4_I2C3SEL_0)
724 #define LL_RCC_I2C3_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\
725 RCC_CCIPR4_I2C3SEL_1)
726 #define LL_RCC_I2C3_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\
727 RCC_CCIPR4_I2C3SEL_1 | RCC_CCIPR4_I2C3SEL_0)
728 #define LL_RCC_I2C3_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\
729 RCC_CCIPR4_I2C3SEL_2)
730 #define LL_RCC_I2C3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\
731 RCC_CCIPR4_I2C3SEL_2| RCC_CCIPR4_I2C3SEL_0)
732
733 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0U)
734 #define LL_RCC_I2C4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\
735 RCC_CCIPR4_I2C4SEL_0)
736 #define LL_RCC_I2C4_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\
737 RCC_CCIPR4_I2C4SEL_1)
738 #define LL_RCC_I2C4_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\
739 RCC_CCIPR4_I2C4SEL_1 | RCC_CCIPR4_I2C4SEL_0)
740 #define LL_RCC_I2C4_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\
741 RCC_CCIPR4_I2C4SEL_2)
742 #define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\
743 RCC_CCIPR4_I2C4SEL_2| RCC_CCIPR4_I2C4SEL_0)
744 /**
745 * @}
746 */
747
748 /** @defgroup RCC_LL_EC_I3C_CLKSOURCE Peripheral I3C clock source selection
749 * @{
750 */
751 #define LL_RCC_I3C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0U)
752 #define LL_RCC_I3C1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
753 RCC_CCIPR4_I3C1SEL_0)
754 #define LL_RCC_I3C1_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
755 RCC_CCIPR4_I3C1SEL_1)
756 #define LL_RCC_I3C1_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
757 RCC_CCIPR4_I3C1SEL_1 | RCC_CCIPR4_I3C1SEL_0)
758 #define LL_RCC_I3C1_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
759 RCC_CCIPR4_I3C1SEL_2)
760 #define LL_RCC_I3C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
761 RCC_CCIPR4_I3C1SEL_2| RCC_CCIPR4_I3C1SEL_0)
762
763 #define LL_RCC_I3C2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0U)
764 #define LL_RCC_I3C2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\
765 RCC_CCIPR4_I3C2SEL_0)
766 #define LL_RCC_I3C2_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\
767 RCC_CCIPR4_I3C2SEL_1)
768 #define LL_RCC_I3C2_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\
769 RCC_CCIPR4_I3C2SEL_1 | RCC_CCIPR4_I3C2SEL_0)
770 #define LL_RCC_I3C2_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\
771 RCC_CCIPR4_I3C2SEL_2)
772 #define LL_RCC_I3C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\
773 RCC_CCIPR4_I3C2SEL_2 | RCC_CCIPR4_I3C2SEL_0)
774 /**
775 * @}
776 */
777
778 /** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIM clock source selection
779 * @{
780 */
781 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, 0U)
782 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_0)
783 #define LL_RCC_LPTIM1_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_1)
784 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_1 |\
785 RCC_CCIPR12_LPTIM1SEL_0)
786 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_2)
787 #define LL_RCC_LPTIM1_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_2 |\
788 RCC_CCIPR12_LPTIM1SEL_0)
789
790 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, 0U)
791 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_0)
792 #define LL_RCC_LPTIM2_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_1)
793 #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_1 |\
794 RCC_CCIPR12_LPTIM2SEL_0)
795 #define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_2)
796 #define LL_RCC_LPTIM2_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_2 |\
797 RCC_CCIPR12_LPTIM2SEL_0)
798
799 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, 0U)
800 #define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_0)
801 #define LL_RCC_LPTIM3_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_1)
802 #define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_1 |\
803 RCC_CCIPR12_LPTIM3SEL_0)
804 #define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_2)
805 #define LL_RCC_LPTIM3_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_2 |\
806 RCC_CCIPR12_LPTIM3SEL_0)
807
808 #define LL_RCC_LPTIM4_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, 0U)
809 #define LL_RCC_LPTIM4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_0)
810 #define LL_RCC_LPTIM4_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_1)
811 #define LL_RCC_LPTIM4_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_1 |\
812 RCC_CCIPR12_LPTIM4SEL_0)
813 #define LL_RCC_LPTIM4_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_2)
814 #define LL_RCC_LPTIM4_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_2 |\
815 RCC_CCIPR12_LPTIM4SEL_0)
816
817 #define LL_RCC_LPTIM5_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, 0U)
818 #define LL_RCC_LPTIM5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_0)
819 #define LL_RCC_LPTIM5_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_1)
820 #define LL_RCC_LPTIM5_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_1 |\
821 RCC_CCIPR12_LPTIM5SEL_0)
822 #define LL_RCC_LPTIM5_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_2)
823 #define LL_RCC_LPTIM5_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_2 |\
824 RCC_CCIPR12_LPTIM5SEL_0)
825 /**
826 * @}
827 */
828
829 /** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUART clock source selection
830 * @{
831 */
832 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4 0U
833 #define LL_RCC_LPUART1_CLKSOURCE_CLKP RCC_CCIPR14_LPUART1SEL_0
834 #define LL_RCC_LPUART1_CLKSOURCE_IC9 RCC_CCIPR14_LPUART1SEL_1
835 #define LL_RCC_LPUART1_CLKSOURCE_IC14 (RCC_CCIPR14_LPUART1SEL_1 | RCC_CCIPR14_LPUART1SEL_0)
836 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR14_LPUART1SEL_2
837 #define LL_RCC_LPUART1_CLKSOURCE_MSI (RCC_CCIPR14_LPUART1SEL_2 | RCC_CCIPR14_LPUART1SEL_0)
838 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_CCIPR14_LPUART1SEL_2 | RCC_CCIPR14_LPUART1SEL_1)
839 /**
840 * @}
841 */
842
843 /** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection
844 * @{
845 */
846 #define LL_RCC_LTDC_CLKSOURCE_PCLK5 0U
847 #define LL_RCC_LTDC_CLKSOURCE_CLKP RCC_CCIPR4_LTDCSEL_0
848 #define LL_RCC_LTDC_CLKSOURCE_IC16 RCC_CCIPR4_LTDCSEL_1
849 #define LL_RCC_LTDC_CLKSOURCE_HSI (RCC_CCIPR4_LTDCSEL_1 | RCC_CCIPR4_LTDCSEL_0)
850 /**
851 * @}
852 */
853
854 /** @defgroup RCC_LL_EC_MDF_CLKSOURCE Peripheral MDF clock source selection
855 * @{
856 */
857 #define LL_RCC_MDF1_CLKSOURCE_HCLK 0U
858 #define LL_RCC_MDF1_CLKSOURCE_CLKP RCC_CCIPR5_MDF1SEL_0
859 #define LL_RCC_MDF1_CLKSOURCE_IC7 RCC_CCIPR5_MDF1SEL_1
860 #define LL_RCC_MDF1_CLKSOURCE_IC8 (RCC_CCIPR5_MDF1SEL_1 | RCC_CCIPR5_MDF1SEL_0)
861 #define LL_RCC_MDF1_CLKSOURCE_MSI RCC_CCIPR5_MDF1SEL_2
862 #define LL_RCC_MDF1_CLKSOURCE_HSI (RCC_CCIPR5_MDF1SEL_2 | RCC_CCIPR5_MDF1SEL_0)
863 #define LL_RCC_MDF1_CLKSOURCE_I2S_CKIN (RCC_CCIPR5_MDF1SEL_2 | RCC_CCIPR5_MDF1SEL_1)
864 #define LL_RCC_MDF1_CLKSOURCE_TIMG (RCC_CCIPR5_MDF1SEL_2 | RCC_CCIPR5_MDF1SEL_1 | RCC_CCIPR5_MDF1SEL_0)
865 /**
866 * @}
867 */
868
869 /** @defgroup RCC_LL_EC_OTGPHY_CLKSOURCE Peripheral OTGPHY clock source selection
870 * @{
871 */
872 #define LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, 0U)
873 #define LL_RCC_OTGPHY1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_0)
874 #define LL_RCC_OTGPHY1_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_1)
875 #define LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_1 |\
876 RCC_CCIPR6_OTGPHY1SEL_0)
877
878 #define LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, 0U)
879 #define LL_RCC_OTGPHY2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_0)
880 #define LL_RCC_OTGPHY2_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_1)
881 #define LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_1 |\
882 RCC_CCIPR6_OTGPHY2SEL_0)
883 /**
884 * @}
885 */
886
887 /** @defgroup RCC_LL_EC_OTGPHYCKREF_CLKSOURCE Peripheral OTGPHYCKREF clock source selection
888 * @{
889 */
890 #define LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, 0U)
891 #define LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, RCC_CCIPR6_OTGPHY1CKREFSEL)
892
893 #define LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, 0U)
894 #define LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, RCC_CCIPR6_OTGPHY2CKREFSEL)
895 /**
896 * @}
897 */
898
899 /** @defgroup RCC_LL_EC_PSSI_CLKSOURCE Peripheral PSSI clock source selection
900 * @{
901 */
902 #define LL_RCC_PSSI_CLKSOURCE_HCLK 0U
903 #define LL_RCC_PSSI_CLKSOURCE_CLKP RCC_CCIPR7_PSSISEL_0
904 #define LL_RCC_PSSI_CLKSOURCE_IC20 RCC_CCIPR7_PSSISEL_1
905 #define LL_RCC_PSSI_CLKSOURCE_HSI (RCC_CCIPR7_PSSISEL_1 | RCC_CCIPR7_PSSISEL_0)
906 /**
907 * @}
908 */
909
910 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
911 * @{
912 */
913 #define LL_RCC_RTC_CLKSOURCE_NONE 0U
914 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_CCIPR7_RTCSEL_0
915 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_CCIPR7_RTCSEL_1
916 #define LL_RCC_RTC_CLKSOURCE_HSE (RCC_CCIPR7_RTCSEL_1 | RCC_CCIPR7_RTCSEL_0)
917 /**
918 * @}
919 */
920
921 /** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAI clock source selection
922 * @{
923 */
924 #define LL_RCC_SAI1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, 0U)
925 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_0)
926 #define LL_RCC_SAI1_CLKSOURCE_IC7 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_1)
927 #define LL_RCC_SAI1_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_1 |\
928 RCC_CCIPR7_SAI1SEL_0)
929 #define LL_RCC_SAI1_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2)
930 #define LL_RCC_SAI1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2 |\
931 RCC_CCIPR7_SAI1SEL_0)
932 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2 |\
933 RCC_CCIPR7_SAI1SEL_1)
934 #define LL_RCC_SAI1_CLKSOURCE_SPDIFRX1 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2 |\
935 RCC_CCIPR7_SAI1SEL_1 | RCC_CCIPR7_SAI1SEL_0)
936
937 #define LL_RCC_SAI2_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, 0U)
938 #define LL_RCC_SAI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_0)
939 #define LL_RCC_SAI2_CLKSOURCE_IC7 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_1)
940 #define LL_RCC_SAI2_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_1 |\
941 RCC_CCIPR7_SAI2SEL_0)
942 #define LL_RCC_SAI2_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2)
943 #define LL_RCC_SAI2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2 |\
944 RCC_CCIPR7_SAI2SEL_0)
945 #define LL_RCC_SAI2_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2 |\
946 RCC_CCIPR7_SAI2SEL_1)
947 #define LL_RCC_SAI2_CLKSOURCE_SPDIFRX1 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2 |\
948 RCC_CCIPR7_SAI2SEL_1 | RCC_CCIPR7_SAI2SEL_0)
949 /**
950 * @}
951 */
952
953 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection
954 * @{
955 */
956 #define LL_RCC_SDMMC1_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, 0U)
957 #define LL_RCC_SDMMC1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_0)
958 #define LL_RCC_SDMMC1_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_1)
959 #define LL_RCC_SDMMC1_CLKSOURCE_IC5 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_1 |\
960 RCC_CCIPR8_SDMMC1SEL_0)
961
962 #define LL_RCC_SDMMC2_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, 0U)
963 #define LL_RCC_SDMMC2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_0)
964 #define LL_RCC_SDMMC2_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_1)
965 #define LL_RCC_SDMMC2_CLKSOURCE_IC5 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_1 |\
966 RCC_CCIPR8_SDMMC2SEL_0)
967 /**
968 * @}
969 */
970
971 /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
972 * @{
973 */
974 #define LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1 0U
975 #define LL_RCC_SPDIFRX1_CLKSOURCE_CLKP RCC_CCIPR9_SPDIFRX1SEL_0
976 #define LL_RCC_SPDIFRX1_CLKSOURCE_IC7 RCC_CCIPR9_SPDIFRX1SEL_1
977 #define LL_RCC_SPDIFRX1_CLKSOURCE_IC8 (RCC_CCIPR9_SPDIFRX1SEL_1 | RCC_CCIPR9_SPDIFRX1SEL_0)
978 #define LL_RCC_SPDIFRX1_CLKSOURCE_MSI RCC_CCIPR9_SPDIFRX1SEL_2
979 #define LL_RCC_SPDIFRX1_CLKSOURCE_HSI (RCC_CCIPR9_SPDIFRX1SEL_2 | RCC_CCIPR9_SPDIFRX1SEL_0)
980 #define LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN (RCC_CCIPR9_SPDIFRX1SEL_2 | RCC_CCIPR9_SPDIFRX1SEL_1)
981 /**
982 * @}
983 */
984
985 /** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPI clock source selection
986 * @{
987 */
988 #define LL_RCC_SPI1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, 0U)
989 #define LL_RCC_SPI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_0)
990 #define LL_RCC_SPI1_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_1)
991 #define LL_RCC_SPI1_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_1 |\
992 RCC_CCIPR9_SPI1SEL_0)
993 #define LL_RCC_SPI1_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_2)
994 #define LL_RCC_SPI1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_2 |\
995 RCC_CCIPR9_SPI1SEL_0)
996 #define LL_RCC_SPI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_2 |\
997 RCC_CCIPR9_SPI1SEL_1)
998
999 #define LL_RCC_SPI2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, 0U)
1000 #define LL_RCC_SPI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_0)
1001 #define LL_RCC_SPI2_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_1)
1002 #define LL_RCC_SPI2_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_1 |\
1003 RCC_CCIPR9_SPI2SEL_0)
1004 #define LL_RCC_SPI2_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_2)
1005 #define LL_RCC_SPI2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_2 |\
1006 RCC_CCIPR9_SPI2SEL_0)
1007 #define LL_RCC_SPI2_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_2 |\
1008 RCC_CCIPR9_SPI2SEL_1)
1009
1010 #define LL_RCC_SPI3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, 0U)
1011 #define LL_RCC_SPI3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_0)
1012 #define LL_RCC_SPI3_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_1)
1013 #define LL_RCC_SPI3_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_1 |\
1014 RCC_CCIPR9_SPI3SEL_0)
1015 #define LL_RCC_SPI3_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_2)
1016 #define LL_RCC_SPI3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_2 |\
1017 RCC_CCIPR9_SPI3SEL_0)
1018 #define LL_RCC_SPI3_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_2 |\
1019 RCC_CCIPR9_SPI3SEL_1)
1020
1021 #define LL_RCC_SPI4_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, 0U)
1022 #define LL_RCC_SPI4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_0)
1023 #define LL_RCC_SPI4_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_1)
1024 #define LL_RCC_SPI4_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_1 |\
1025 RCC_CCIPR9_SPI4SEL_0)
1026 #define LL_RCC_SPI4_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_2)
1027 #define LL_RCC_SPI4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_2 |\
1028 RCC_CCIPR9_SPI4SEL_0)
1029 #define LL_RCC_SPI4_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_2 |\
1030 RCC_CCIPR9_SPI4SEL_1)
1031
1032 #define LL_RCC_SPI5_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, 0U)
1033 #define LL_RCC_SPI5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_0)
1034 #define LL_RCC_SPI5_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_1)
1035 #define LL_RCC_SPI5_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_1 |\
1036 RCC_CCIPR9_SPI5SEL_0)
1037 #define LL_RCC_SPI5_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_2)
1038 #define LL_RCC_SPI5_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_2 |\
1039 RCC_CCIPR9_SPI5SEL_0)
1040 #define LL_RCC_SPI5_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_2 |\
1041 RCC_CCIPR9_SPI5SEL_1)
1042
1043 #define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, 0U)
1044 #define LL_RCC_SPI6_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_0)
1045 #define LL_RCC_SPI6_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_1)
1046 #define LL_RCC_SPI6_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_1 |\
1047 RCC_CCIPR9_SPI6SEL_0)
1048 #define LL_RCC_SPI6_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_2)
1049 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_2 |\
1050 RCC_CCIPR9_SPI6SEL_0)
1051 #define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_2 |\
1052 RCC_CCIPR9_SPI6SEL_1)
1053 /**
1054 * @}
1055 */
1056
1057 /** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UART clock source selection
1058 * @{
1059 */
1060 #define LL_RCC_UART4_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, 0U)
1061 #define LL_RCC_UART4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_0)
1062 #define LL_RCC_UART4_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_1)
1063 #define LL_RCC_UART4_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_1 |\
1064 RCC_CCIPR13_UART4SEL_0)
1065 #define LL_RCC_UART4_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_2)
1066 #define LL_RCC_UART4_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_2 |\
1067 RCC_CCIPR13_UART4SEL_0)
1068 #define LL_RCC_UART4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_2 |\
1069 RCC_CCIPR13_UART4SEL_1)
1070
1071 #define LL_RCC_UART5_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, 0U)
1072 #define LL_RCC_UART5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_0)
1073 #define LL_RCC_UART5_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_1)
1074 #define LL_RCC_UART5_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_1 |\
1075 RCC_CCIPR13_UART5SEL_0)
1076 #define LL_RCC_UART5_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_2)
1077 #define LL_RCC_UART5_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_2 |\
1078 RCC_CCIPR13_UART5SEL_0)
1079 #define LL_RCC_UART5_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_2 |\
1080 RCC_CCIPR13_UART5SEL_1)
1081
1082 #define LL_RCC_UART7_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, 0U)
1083 #define LL_RCC_UART7_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_0)
1084 #define LL_RCC_UART7_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_1)
1085 #define LL_RCC_UART7_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_1 |\
1086 RCC_CCIPR13_UART7SEL_0)
1087 #define LL_RCC_UART7_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_2)
1088 #define LL_RCC_UART7_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_2 |\
1089 RCC_CCIPR13_UART7SEL_0)
1090 #define LL_RCC_UART7_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_2 |\
1091 RCC_CCIPR13_UART7SEL_1)
1092
1093 #define LL_RCC_UART8_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, 0U)
1094 #define LL_RCC_UART8_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_0)
1095 #define LL_RCC_UART8_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_1)
1096 #define LL_RCC_UART8_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_1 |\
1097 RCC_CCIPR13_UART8SEL_0)
1098 #define LL_RCC_UART8_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_2)
1099 #define LL_RCC_UART8_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_2 |\
1100 RCC_CCIPR13_UART8SEL_0)
1101 #define LL_RCC_UART8_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_2 |\
1102 RCC_CCIPR13_UART8SEL_1)
1103
1104 #define LL_RCC_UART9_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, 0U)
1105 #define LL_RCC_UART9_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_0)
1106 #define LL_RCC_UART9_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_1)
1107 #define LL_RCC_UART9_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_1 |\
1108 RCC_CCIPR14_UART9SEL_0)
1109 #define LL_RCC_UART9_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_2)
1110 #define LL_RCC_UART9_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_2 |\
1111 RCC_CCIPR14_UART9SEL_0)
1112 #define LL_RCC_UART9_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_2 |\
1113 RCC_CCIPR14_UART9SEL_1)
1114 /**
1115 * @}
1116 */
1117
1118 /** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USART clock source selection
1119 * @{
1120 */
1121 #define LL_RCC_USART1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, 0U)
1122 #define LL_RCC_USART1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_0)
1123 #define LL_RCC_USART1_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_1)
1124 #define LL_RCC_USART1_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_1 |\
1125 RCC_CCIPR13_USART1SEL_0)
1126 #define LL_RCC_USART1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_2)
1127 #define LL_RCC_USART1_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_2 |\
1128 RCC_CCIPR13_USART1SEL_0)
1129 #define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_2 |\
1130 RCC_CCIPR13_USART1SEL_1)
1131
1132 #define LL_RCC_USART2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, 0U)
1133 #define LL_RCC_USART2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_0)
1134 #define LL_RCC_USART2_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_1)
1135 #define LL_RCC_USART2_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_1 |\
1136 RCC_CCIPR13_USART2SEL_0)
1137 #define LL_RCC_USART2_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_2)
1138 #define LL_RCC_USART2_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_2 |\
1139 RCC_CCIPR13_USART2SEL_0)
1140 #define LL_RCC_USART2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_2 |\
1141 RCC_CCIPR13_USART2SEL_1)
1142
1143 #define LL_RCC_USART3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, 0U)
1144 #define LL_RCC_USART3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_0)
1145 #define LL_RCC_USART3_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_1)
1146 #define LL_RCC_USART3_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_1 |\
1147 RCC_CCIPR13_USART3SEL_0)
1148 #define LL_RCC_USART3_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_2)
1149 #define LL_RCC_USART3_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_2 |\
1150 RCC_CCIPR13_USART3SEL_0)
1151 #define LL_RCC_USART3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_2 |\
1152 RCC_CCIPR13_USART3SEL_1)
1153
1154 #define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, 0U)
1155 #define LL_RCC_USART6_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_0)
1156 #define LL_RCC_USART6_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_1)
1157 #define LL_RCC_USART6_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_1 |\
1158 RCC_CCIPR13_USART6SEL_0)
1159 #define LL_RCC_USART6_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_2)
1160 #define LL_RCC_USART6_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_2 |\
1161 RCC_CCIPR13_USART6SEL_0)
1162 #define LL_RCC_USART6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_2 |\
1163 RCC_CCIPR13_USART6SEL_1)
1164
1165 #define LL_RCC_USART10_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, 0U)
1166 #define LL_RCC_USART10_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_0)
1167 #define LL_RCC_USART10_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_1)
1168 #define LL_RCC_USART10_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_1 |\
1169 RCC_CCIPR14_USART10SEL_0)
1170 #define LL_RCC_USART10_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_2)
1171 #define LL_RCC_USART10_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_2 |\
1172 RCC_CCIPR14_USART10SEL_0)
1173 #define LL_RCC_USART10_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_2 |\
1174 RCC_CCIPR14_USART10SEL_1)
1175 /**
1176 * @}
1177 */
1178
1179 /** @defgroup RCC_LL_EC_XSPI_CLKSOURCE Peripheral XSPI clock source selection
1180 * @{
1181 */
1182 #define LL_RCC_XSPI1_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, 0U)
1183 #define LL_RCC_XSPI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_0)
1184 #define LL_RCC_XSPI1_CLKSOURCE_IC3 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_1)
1185 #define LL_RCC_XSPI1_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_1 |\
1186 RCC_CCIPR6_XSPI1SEL_0)
1187
1188 #define LL_RCC_XSPI2_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, 0U)
1189 #define LL_RCC_XSPI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_0)
1190 #define LL_RCC_XSPI2_CLKSOURCE_IC3 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_1)
1191 #define LL_RCC_XSPI2_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_1 |\
1192 RCC_CCIPR6_XSPI2SEL_0)
1193
1194 #define LL_RCC_XSPI3_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, 0U)
1195 #define LL_RCC_XSPI3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_0)
1196 #define LL_RCC_XSPI3_CLKSOURCE_IC3 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_1)
1197 #define LL_RCC_XSPI3_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_1 |\
1198 RCC_CCIPR6_XSPI3SEL_0)
1199 /**
1200 * @}
1201 */
1202
1203 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
1204 * @{
1205 */
1206 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR1_ADC12SEL
1207 /**
1208 * @}
1209 */
1210
1211 /** @defgroup RCC_LL_EC_ADF Peripheral ADF get clock source
1212 * @{
1213 */
1214 #define LL_RCC_ADF1_CLKSOURCE RCC_CCIPR1_ADF1SEL
1215 /**
1216 * @}
1217 */
1218
1219 /** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source
1220 * @{
1221 */
1222 #define LL_RCC_CLKP_CLKSOURCE RCC_CCIPR7_PERSEL
1223 /**
1224 * @}
1225 */
1226
1227 /** @defgroup RCC_LL_EC_DCMIPP Peripheral DCMIPP get clock source
1228 * @{
1229 */
1230 #define LL_RCC_DCMIPP_CLKSOURCE RCC_CCIPR1_DCMIPPSEL
1231 /**
1232 * @}
1233 */
1234
1235 /** @defgroup RCC_LL_EC_ETH Peripheral ETH get clock source
1236 * @{
1237 */
1238 #define LL_RCC_ETH1_CLKSOURCE RCC_CCIPR2_ETH1CLKSEL
1239 /**
1240 * @}
1241 */
1242
1243 /** @defgroup RCC_LL_EC_ETHPHY Peripheral ETH PHY get interface
1244 * @{
1245 */
1246 #define LL_RCC_ETH1PHY_IF RCC_CCIPR2_ETH1SEL
1247 /**
1248 * @}
1249 */
1250
1251 /** @defgroup RCC_LL_EC_ETHPTP Peripheral ETHPTP get clock source
1252 * @{
1253 */
1254 #define LL_RCC_ETH1PTP_CLKSOURCE RCC_CCIPR2_ETH1PTPSEL
1255 /**
1256 * @}
1257 */
1258
1259 /** @defgroup RCC_LL_EC_ETHREFRX Peripheral ETH Reference RX get clock source
1260 * @{
1261 */
1262 #define LL_RCC_ETH1REFRX_CLKSOURCE RCC_CCIPR2_ETH1REFCLKSEL
1263 /**
1264 * @}
1265 */
1266
1267 /** @defgroup RCC_LL_EC_ETHREFTX Peripheral ETH Reference TX get clock source
1268 * @{
1269 */
1270 #define LL_RCC_ETH1REFTX_CLKSOURCE RCC_CCIPR2_ETH1GTXCLKSEL
1271 /**
1272 * @}
1273 */
1274
1275 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
1276 * @{
1277 */
1278 #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR3_FDCANSEL
1279 /**
1280 * @}
1281 */
1282
1283 /** @defgroup RCC_LL_EC_FMC Peripheral FMC get clock source
1284 * @{
1285 */
1286 #define LL_RCC_FMC_CLKSOURCE RCC_CCIPR3_FMCSEL
1287 /**
1288 * @}
1289 */
1290
1291 /** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source
1292 * @{
1293 */
1294 #define LL_RCC_I2C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0U)
1295 #define LL_RCC_I2C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0U)
1296 #define LL_RCC_I2C3_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0U)
1297 #define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0U)
1298 /**
1299 * @}
1300 */
1301
1302 /** @defgroup RCC_LL_EC_I3C Peripheral I3C get clock source
1303 * @{
1304 */
1305 #define LL_RCC_I3C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0U)
1306 #define LL_RCC_I3C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0U)
1307 /**
1308 * @}
1309 */
1310
1311 /** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIM get clock source
1312 * @{
1313 */
1314 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, 0U)
1315 #define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, 0U)
1316 #define LL_RCC_LPTIM3_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, 0U)
1317 #define LL_RCC_LPTIM4_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, 0U)
1318 #define LL_RCC_LPTIM5_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, 0U)
1319 /**
1320 * @}
1321 */
1322
1323 /** @defgroup RCC_LL_EC_LPUART Peripheral LPUART get clock source
1324 * @{
1325 */
1326 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR14_LPUART1SEL
1327 /**
1328 * @}
1329 */
1330
1331 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
1332 * @{
1333 */
1334 #define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR4_LTDCSEL
1335 /**
1336 * @}
1337 */
1338
1339 /** @defgroup RCC_LL_EC_MDF Peripheral MDF get clock source
1340 * @{
1341 */
1342 #define LL_RCC_MDF1_CLKSOURCE RCC_CCIPR5_MDF1SEL
1343 /**
1344 * @}
1345 */
1346
1347 /** @defgroup RCC_LL_EC_OTGPHY Peripheral OTGPHY get clock source
1348 * @{
1349 */
1350 #define LL_RCC_OTGPHY1_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, 0U)
1351 #define LL_RCC_OTGPHY2_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, 0U)
1352 /**
1353 * @}
1354 */
1355
1356 /** @defgroup RCC_LL_EC_OTGPHYCKREF Peripheral OTGPHYCKREF get clock source
1357 * @{
1358 */
1359 #define LL_RCC_OTGPHY1CKREF_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, 0U)
1360 #define LL_RCC_OTGPHY2CKREF_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, 0U)
1361 /**
1362 * @}
1363 */
1364
1365 /** @defgroup RCC_LL_EC_PSSI Peripheral PSSI get clock source
1366 * @{
1367 */
1368 #define LL_RCC_PSSI_CLKSOURCE RCC_CCIPR7_PSSISEL
1369 /**
1370 * @}
1371 */
1372
1373 /** @defgroup RCC_LL_EC_SAI Peripheral SAI get clock source
1374 * @{
1375 */
1376 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, 0U)
1377 #define LL_RCC_SAI2_CLKSOURCE LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, 0U)
1378 /**
1379 * @}
1380 */
1381
1382 /** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source
1383 * @{
1384 */
1385 #define LL_RCC_SDMMC1_CLKSOURCE LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, 0U)
1386 #define LL_RCC_SDMMC2_CLKSOURCE LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, 0U)
1387 /**
1388 * @}
1389 */
1390
1391 /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
1392 * @{
1393 */
1394 #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_CCIPR9_SPDIFRX1SEL
1395 /**
1396 * @}
1397 */
1398
1399 /** @defgroup RCC_LL_EC_SPI Peripheral SPI get clock source
1400 * @{
1401 */
1402 #define LL_RCC_SPI1_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, 0U)
1403 #define LL_RCC_SPI2_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, 0U)
1404 #define LL_RCC_SPI3_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, 0U)
1405 #define LL_RCC_SPI4_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, 0U)
1406 #define LL_RCC_SPI5_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, 0U)
1407 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, 0U)
1408 /**
1409 * @}
1410 */
1411
1412 /** @defgroup RCC_LL_EC_UART Peripheral UART get clock source
1413 * @{
1414 */
1415 #define LL_RCC_UART4_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, 0U)
1416 #define LL_RCC_UART5_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, 0U)
1417 #define LL_RCC_UART7_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, 0U)
1418 #define LL_RCC_UART8_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, 0U)
1419 #define LL_RCC_UART9_CLKSOURCE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, 0U)
1420 /**
1421 * @}
1422 */
1423
1424 /** @defgroup RCC_LL_EC_USART Peripheral USART get clock source
1425 * @{
1426 */
1427 #define LL_RCC_USART1_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, 0U)
1428 #define LL_RCC_USART2_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, 0U)
1429 #define LL_RCC_USART3_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, 0U)
1430 #define LL_RCC_USART6_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, 0U)
1431 #define LL_RCC_USART10_CLKSOURCE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, 0U)
1432 /**
1433 * @}
1434 */
1435
1436 /** @defgroup RCC_LL_EC_XSPI Peripheral XSPI get clock source
1437 * @{
1438 */
1439 #define LL_RCC_XSPI1_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, 0U)
1440 #define LL_RCC_XSPI2_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, 0U)
1441 #define LL_RCC_XSPI3_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, 0U)
1442 /**
1443 * @}
1444 */
1445
1446 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
1447 * @{
1448 */
1449 #define LL_RCC_TIM_PRESCALER_1 0U
1450 #define LL_RCC_TIM_PRESCALER_2 1U
1451 #define LL_RCC_TIM_PRESCALER_4 2U
1452 #define LL_RCC_TIM_PRESCALER_8 3U
1453 /**
1454 * @}
1455 */
1456
1457 /** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source
1458 * @{
1459 */
1460 #define LL_RCC_PLLSOURCE_HSI 0U
1461 #define LL_RCC_PLLSOURCE_MSI RCC_PLL1CFGR1_PLL1SEL_0
1462 #define LL_RCC_PLLSOURCE_HSE RCC_PLL1CFGR1_PLL1SEL_1
1463 #define LL_RCC_PLLSOURCE_I2S_CKIN (RCC_PLL1CFGR1_PLL1SEL_1 | RCC_PLL1CFGR1_PLL1SEL_0)
1464 /**
1465 * @}
1466 */
1467
1468 /** @defgroup RCC_LL_EC_ICSOURCE All ICs entry clock source
1469 * @{
1470 */
1471 #define LL_RCC_ICCLKSOURCE_PLL1 0U
1472 #define LL_RCC_ICCLKSOURCE_PLL2 RCC_IC1CFGR_IC1SEL_0
1473 #define LL_RCC_ICCLKSOURCE_PLL3 RCC_IC1CFGR_IC1SEL_1
1474 #define LL_RCC_ICCLKSOURCE_PLL4 (RCC_IC1CFGR_IC1SEL_1 | RCC_IC1CFGR_IC1SEL_0)
1475 /**
1476 * @}
1477 */
1478
1479 /**
1480 * @}
1481 */
1482
1483 /* Exported macros -----------------------------------------------------------*/
1484 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1485 * @{
1486 */
1487
1488 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1489 * @{
1490 */
1491
1492 /**
1493 * @brief Write a value in RCC register
1494 * @param __REG__ Register to be written
1495 * @param __VALUE__ Value to be written in the register
1496 * @retval None
1497 */
1498 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1499
1500 /**
1501 * @brief Read a value in RCC register
1502 * @param __REG__ Register to be read
1503 * @retval Register value
1504 */
1505 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1506 /**
1507 * @}
1508 */
1509
1510 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1511 * @{
1512 */
1513
1514 /**
1515 * @brief Helper macro to calculate the HCLK frequency
1516 * @param __SYSCLKFREQ__ SYSCLK frequency.
1517 * @param __HPRESCALER__ This parameter can be one of the following values:
1518 * @arg @ref LL_RCC_AHB_DIV_1
1519 * @arg @ref LL_RCC_AHB_DIV_2
1520 * @arg @ref LL_RCC_AHB_DIV_4
1521 * @arg @ref LL_RCC_AHB_DIV_8
1522 * @arg @ref LL_RCC_AHB_DIV_16
1523 * @arg @ref LL_RCC_AHB_DIV_32
1524 * @arg @ref LL_RCC_AHB_DIV_64
1525 * @arg @ref LL_RCC_AHB_DIV_128
1526 * @retval HCLK clock frequency (in Hz)
1527 */
1528 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> (((__HPRESCALER__) &\
1529 RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos))
1530
1531 /**
1532 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1533 * @param __HCLKFREQ__ HCLK frequency
1534 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1535 * @arg @ref LL_RCC_APB1_DIV_1
1536 * @arg @ref LL_RCC_APB1_DIV_2
1537 * @arg @ref LL_RCC_APB1_DIV_4
1538 * @arg @ref LL_RCC_APB1_DIV_8
1539 * @arg @ref LL_RCC_APB1_DIV_16
1540 * @arg @ref LL_RCC_APB1_DIV_32
1541 * @arg @ref LL_RCC_APB1_DIV_64
1542 * @arg @ref LL_RCC_APB1_DIV_128
1543 * @retval PCLK1 clock frequency (in Hz)
1544 */
1545 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (((__APB1PRESCALER__) &\
1546 RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos))
1547
1548 /**
1549 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1550 * @param __HCLKFREQ__ HCLK frequency
1551 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1552 * @arg @ref LL_RCC_APB2_DIV_1
1553 * @arg @ref LL_RCC_APB2_DIV_2
1554 * @arg @ref LL_RCC_APB2_DIV_4
1555 * @arg @ref LL_RCC_APB2_DIV_8
1556 * @arg @ref LL_RCC_APB2_DIV_16
1557 * @arg @ref LL_RCC_APB2_DIV_32
1558 * @arg @ref LL_RCC_APB2_DIV_64
1559 * @arg @ref LL_RCC_APB2_DIV_128
1560 * @retval PCLK2 clock frequency (in Hz)
1561 */
1562 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (((__APB2PRESCALER__) &\
1563 RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_Pos))
1564
1565 /**
1566 * @brief Helper macro to calculate the PCLK4 frequency (ABP4)
1567 * @param __HCLKFREQ__ HCLK frequency
1568 * @param __APB4PRESCALER__ This parameter can be one of the following values:
1569 * @arg @ref LL_RCC_APB4_DIV_1
1570 * @arg @ref LL_RCC_APB4_DIV_2
1571 * @arg @ref LL_RCC_APB4_DIV_4
1572 * @arg @ref LL_RCC_APB4_DIV_8
1573 * @arg @ref LL_RCC_APB4_DIV_16
1574 * @arg @ref LL_RCC_APB4_DIV_32
1575 * @arg @ref LL_RCC_APB4_DIV_64
1576 * @arg @ref LL_RCC_APB4_DIV_128
1577 * @retval PCLK1 clock frequency (in Hz)
1578 */
1579 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> (((__APB4PRESCALER__) &\
1580 RCC_CFGR2_PPRE4) >> RCC_CFGR2_PPRE4_Pos))
1581
1582 /**
1583 * @brief Helper macro to calculate the PCLK5 frequency (APB5)
1584 * @param __HCLKFREQ__ HCLK frequency
1585 * @param __APB5PRESCALER__ This parameter can be one of the following values:
1586 * @arg @ref LL_RCC_APB5_DIV_1
1587 * @arg @ref LL_RCC_APB5_DIV_2
1588 * @arg @ref LL_RCC_APB5_DIV_4
1589 * @arg @ref LL_RCC_APB5_DIV_8
1590 * @arg @ref LL_RCC_APB5_DIV_16
1591 * @arg @ref LL_RCC_APB5_DIV_32
1592 * @arg @ref LL_RCC_APB5_DIV_64
1593 * @arg @ref LL_RCC_APB5_DIV_128
1594 * @retval PCLK1 clock frequency (in Hz)
1595 */
1596 #define LL_RCC_CALC_PCLK5_FREQ(__HCLKFREQ__, __APB5PRESCALER__) ((__HCLKFREQ__) >> (((__APB5PRESCALER__) &\
1597 RCC_CFGR2_PPRE5) >> RCC_CFGR2_PPRE5_Pos))
1598
1599 /**
1600 * @}
1601 */
1602
1603 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
1604 * @{
1605 */
1606 #define LL_RCC_PERIPH_FREQUENCY_NO 0U /*!< No clock enabled for the peripheral */
1607 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFUL /*!< Frequency cannot be provided as external clock */
1608 /**
1609 * @}
1610 */
1611
1612 /**
1613 * @}
1614 */
1615
1616 /* Exported functions --------------------------------------------------------*/
1617 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1618 * @{
1619 */
1620
1621 /** @defgroup RCC_LL_EF_HSE HSE
1622 * @{
1623 */
1624
1625 /**
1626 * @brief Enable the HSE Clock Security System.
1627 * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
1628 * a reset occurs or system enter in standby mode.
1629 * @rmtoll HSECFGR HSECSSON LL_RCC_HSE_EnableCSS
1630 * @retval None
1631 */
LL_RCC_HSE_EnableCSS(void)1632 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1633 {
1634 SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSON);
1635 }
1636
1637 /**
1638 * @brief Check if HSE failure is detected by Clock Security System
1639 * @rmtoll HSECFGR HSECSSD LL_RCC_HSE_IsFailureDetected
1640 * @retval State of bit (1 or 0).
1641 */
LL_RCC_HSE_IsFailureDetected(void)1642 __STATIC_INLINE uint32_t LL_RCC_HSE_IsFailureDetected(void)
1643 {
1644 return ((READ_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSD) != 0UL) ? 1UL : 0UL);
1645 }
1646
1647 /**
1648 * @brief Enable the HSE Clock Security System bypass.
1649 * @note Bypass the HSE oscillator when a failure is detected and get the clock from
1650 * the HSI oscillator (HSI injection)
1651 * @rmtoll HSECFGR HSECSSBYP LL_RCC_HSE_EnableCSSBypass
1652 * @retval None
1653 */
LL_RCC_HSE_EnableCSSBypass(void)1654 __STATIC_INLINE void LL_RCC_HSE_EnableCSSBypass(void)
1655 {
1656 SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSBYP);
1657 }
1658
1659 /**
1660 * @brief Disable the HSE Clock Security System bypass.
1661 * @rmtoll HSECFGR HSECSSBYP LL_RCC_HSE_DisableCSSBypass
1662 * @retval None
1663 */
LL_RCC_HSE_DisableCSSBypass(void)1664 __STATIC_INLINE void LL_RCC_HSE_DisableCSSBypass(void)
1665 {
1666 CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSBYP);
1667 }
1668
1669 /**
1670 * @brief Set HSE Clock Security System bypass divider
1671 * @note To divide the replacement internal HSI oscillator that
1672 * bypasses the HSE oscillator when a failure is detected
1673 * @rmtoll HSECFGR HSECSSBPRE LL_RCC_HSE_SetCSSBypassDivider
1674 * @param Divider This parameter can be a value from RCC_LL_EC_HSECSSBYP_DIV.
1675 * @retval None
1676 */
LL_RCC_HSE_SetCSSBypassDivider(uint32_t Divider)1677 __STATIC_INLINE void LL_RCC_HSE_SetCSSBypassDivider(uint32_t Divider)
1678 {
1679 MODIFY_REG(RCC->HSECFGR, RCC_HSECFGR_HSECSSBPRE, Divider);
1680 }
1681
1682 /**
1683 * @brief Get HSE Clock Security System bypass divider
1684 * @note To divide the replacement internal HSI oscillator that
1685 * bypasses the HSE oscillator when a failure is detected
1686 * @rmtoll HSECFGR HSECSSBPRE LL_RCC_HSE_GetCSSBypassDivider
1687 * @retval can be a value from RCC_LL_EC_HSECSSBYP_DIV.
1688 */
LL_RCC_HSE_GetCSSBypassDivider(void)1689 __STATIC_INLINE uint32_t LL_RCC_HSE_GetCSSBypassDivider(void)
1690 {
1691 return (READ_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSBPRE));
1692 }
1693
1694 /**
1695 * @brief Enable HSE external oscillator (HSE Bypass)
1696 * @rmtoll HSECFGR HSEBYP LL_RCC_HSE_EnableBypass
1697 * @retval None
1698 */
LL_RCC_HSE_EnableBypass(void)1699 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1700 {
1701 SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEBYP);
1702 }
1703
1704 /**
1705 * @brief Disable HSE external oscillator (HSE Bypass)
1706 * @rmtoll HSECFGR HSEBYP LL_RCC_HSE_DisableBypass
1707 * @retval None
1708 */
LL_RCC_HSE_DisableBypass(void)1709 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1710 {
1711 CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEBYP);
1712 }
1713
1714 /**
1715 * @brief Select the Analog HSE external clock type in Bypass mode
1716 * @rmtoll HSECFGR HSEEXT LL_RCC_HSE_SelectAnalogClock
1717 * @retval None
1718 */
LL_RCC_HSE_SelectAnalogClock(void)1719 __STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
1720 {
1721 CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT);
1722 }
1723
1724 /**
1725 * @brief Select the Digital HSE external clock type in Bypass mode
1726 * @rmtoll HSECFGR HSEEXT LL_RCC_HSE_SelectDigitalClock
1727 * @retval None
1728 */
LL_RCC_HSE_SelectDigitalClock(void)1729 __STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
1730 {
1731 SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT);
1732 }
1733
1734 /**
1735 * @brief Select the HSE as hse_div2_osc_ck output clock
1736 * @rmtoll HSECFGR HSEDIV2SEL LL_RCC_HSE_SelectHSEAsDiv2Clock
1737 * @retval None
1738 */
LL_RCC_HSE_SelectHSEAsDiv2Clock(void)1739 __STATIC_INLINE void LL_RCC_HSE_SelectHSEAsDiv2Clock(void)
1740 {
1741 CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEDIV2SEL);
1742 }
1743
1744 /**
1745 * @brief Select the HSE divided by 2 as hse_div2_osc_ck output clock
1746 * @rmtoll HSECFGR HSEDIV2SEL LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock
1747 * @retval None
1748 */
LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock(void)1749 __STATIC_INLINE void LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock(void)
1750 {
1751 SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEDIV2SEL);
1752 }
1753
1754 /**
1755 * @brief Check if hse_div2_osc_ck output clock is divided by 2
1756 * @rmtoll HSECFGR HSEDIV2SEL LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock
1757 * @retval State of bit (1 or 0).
1758 */
LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock(void)1759 __STATIC_INLINE uint32_t LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock(void)
1760 {
1761 return ((READ_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEDIV2SEL) == RCC_HSECFGR_HSEDIV2SEL) ? 1UL : 0UL);
1762 }
1763
1764 /**
1765 * @brief Enable HSE crystal oscillator (HSE ON)
1766 * @rmtoll CSR HSEONS LL_RCC_HSE_Enable
1767 * @retval None
1768 */
LL_RCC_HSE_Enable(void)1769 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1770 {
1771 WRITE_REG(RCC->CSR, RCC_CSR_HSEONS);
1772 }
1773
1774 /**
1775 * @brief Disable HSE crystal oscillator (HSE ON)
1776 * @rmtoll CCR HSEONC LL_RCC_HSE_Disable
1777 * @retval None
1778 */
LL_RCC_HSE_Disable(void)1779 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1780 {
1781 WRITE_REG(RCC->CCR, RCC_CCR_HSEONC);
1782 }
1783
1784 /**
1785 * @brief Check if HSE oscillator Ready
1786 * @rmtoll SR HSERDY LL_RCC_HSE_IsReady
1787 * @retval State of bit (1 or 0).
1788 */
LL_RCC_HSE_IsReady(void)1789 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1790 {
1791 return ((READ_BIT(RCC->SR, RCC_SR_HSERDY) != 0UL) ? 1UL : 0UL);
1792 }
1793
1794 /**
1795 * @}
1796 */
1797
1798 /** @defgroup RCC_LL_EF_HSI HSI
1799 * @{
1800 */
1801
1802 /**
1803 * @brief Enable HSI oscillator
1804 * @rmtoll CSR HSIONS LL_RCC_HSI_Enable
1805 * @retval None
1806 */
LL_RCC_HSI_Enable(void)1807 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1808 {
1809 WRITE_REG(RCC->CSR, RCC_CSR_HSIONS);
1810 }
1811
1812 /**
1813 * @brief Disable HSI oscillator
1814 * @rmtoll CCR HSIONC LL_RCC_HSI_Disable
1815 * @retval None
1816 */
LL_RCC_HSI_Disable(void)1817 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1818 {
1819 WRITE_REG(RCC->CCR, RCC_CCR_HSIONC);
1820 }
1821
1822 /**
1823 * @brief Check if HSI clock is ready
1824 * @rmtoll SR HSIRDY LL_RCC_HSI_IsReady
1825 * @retval State of bit (1 or 0).
1826 */
LL_RCC_HSI_IsReady(void)1827 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1828 {
1829 return ((READ_BIT(RCC->SR, RCC_SR_HSIRDY) != 0UL) ? 1UL : 0UL);
1830 }
1831
1832 /**
1833 * @brief Set HSI divider
1834 * @rmtoll HSICFGR HSIDIV LL_RCC_HSI_SetDivider
1835 * @param Divider This parameter can be one of the following values:
1836 * @arg @ref LL_RCC_HSI_DIV_1
1837 * @arg @ref LL_RCC_HSI_DIV_2
1838 * @arg @ref LL_RCC_HSI_DIV_4
1839 * @arg @ref LL_RCC_HSI_DIV_8
1840 * @retval None.
1841 */
LL_RCC_HSI_SetDivider(uint32_t Divider)1842 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
1843 {
1844 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSIDIV, Divider);
1845 }
1846
1847 /**
1848 * @brief Get HSI divider
1849 * @rmtoll HSICFGR HSIDIV LL_RCC_HSI_GetDivider
1850 * @retval can be one of the following values:
1851 * @arg @ref LL_RCC_HSI_DIV_1
1852 * @arg @ref LL_RCC_HSI_DIV_2
1853 * @arg @ref LL_RCC_HSI_DIV_4
1854 * @arg @ref LL_RCC_HSI_DIV_8
1855 */
LL_RCC_HSI_GetDivider(void)1856 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
1857 {
1858 return (READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSIDIV));
1859 }
1860
1861 /**
1862 * @brief Get HSI Calibration value
1863 * @note When HSITRIM is written, HSICAL is updated with the sum of
1864 * HSITRIM and the factory trim value
1865 * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration
1866 * @retval A value between 0 and 511 (0x1FF)
1867 */
LL_RCC_HSI_GetCalibration(void)1868 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1869 {
1870 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
1871 }
1872
1873 /**
1874 * @brief Set HSI Calibration trimming
1875 * @note user-programmable trimming value that is added to the HSICAL
1876 * @note Default value is 32, which, when added to the HSICAL value,
1877 * should trim the HSI to 32 MHz +/- 1 %
1878 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming
1879 * @param Value This parameter can be a value between 0 and 63
1880 * @retval None
1881 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1882 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1883 {
1884 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1885 }
1886
1887 /**
1888 * @brief Get HSI Calibration trimming
1889 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming
1890 * @retval A value between 0 and 63
1891 */
LL_RCC_HSI_GetCalibTrimming(void)1892 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1893 {
1894 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1895 }
1896
1897 /**
1898 * @brief Enable HSI even in stop mode
1899 * @note HSI oscillator is forced ON even in Stop mode
1900 * @rmtoll STOPCR HSISTOPEN LL_RCC_HSI_EnableInStopMode
1901 * @retval None
1902 */
LL_RCC_HSI_EnableInStopMode(void)1903 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1904 {
1905 SET_BIT(RCC->STOPCR, RCC_STOPCR_HSISTOPEN);
1906 }
1907
1908 /**
1909 * @brief Disable HSI in stop mode
1910 * @rmtoll STOPCR HSISTOPEN LL_RCC_HSI_DisableInStopMode
1911 * @retval None
1912 */
LL_RCC_HSI_DisableInStopMode(void)1913 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1914 {
1915 CLEAR_BIT(RCC->STOPCR, RCC_STOPCR_HSISTOPEN);
1916 }
1917
1918 /**
1919 * @brief Check if HSI is enabled in stop mode
1920 * @rmtoll STOPCR HSISTOPEN LL_RCC_HSI_IsEnabledInStopMode
1921 * @retval State of bit (1 or 0).
1922 */
LL_RCC_HSI_IsEnabledInStopMode(void)1923 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
1924 {
1925 return ((READ_BIT(RCC->STOPCR, RCC_STOPCR_HSISTOPEN) == RCC_STOPCR_HSISTOPEN) ? 1UL : 0UL);
1926 }
1927
1928 /**
1929 * @}
1930 */
1931
1932 /** @defgroup RCC_LL_EF_MSI MSI
1933 * @{
1934 */
1935
1936 /**
1937 * @brief Enable MSI oscillator
1938 * @rmtoll CSR MSIONS LL_RCC_MSI_Enable
1939 * @retval None
1940 */
LL_RCC_MSI_Enable(void)1941 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
1942 {
1943 WRITE_REG(RCC->CSR, RCC_CSR_MSIONS);
1944 }
1945
1946 /**
1947 * @brief Disable MSI oscillator
1948 * @rmtoll CCR MSIONC LL_RCC_MSI_Disable
1949 * @retval None
1950 */
LL_RCC_MSI_Disable(void)1951 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
1952 {
1953 WRITE_REG(RCC->CCR, RCC_CCR_MSIONC);
1954 }
1955
1956 /**
1957 * @brief Check if MSI clock is ready
1958 * @rmtoll SR MSIRDY LL_RCC_MSI_IsReady
1959 * @retval State of bit (1 or 0).
1960 */
LL_RCC_MSI_IsReady(void)1961 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
1962 {
1963 return ((READ_BIT(RCC->SR, RCC_SR_MSIRDY) != 0UL) ? 1UL : 0UL);
1964 }
1965
1966 /**
1967 * @brief Set MSI frequency
1968 * @rmtoll MSICFGR MSIFREQSEL LL_RCC_MSI_SetFrequency
1969 * @param Value This parameter can be one of the following values:
1970 * @arg @ref LL_RCC_MSI_FREQ_4MHZ
1971 * @arg @ref LL_RCC_MSI_FREQ_16MHZ
1972 * @retval None.
1973 */
LL_RCC_MSI_SetFrequency(uint32_t Value)1974 __STATIC_INLINE void LL_RCC_MSI_SetFrequency(uint32_t Value)
1975 {
1976 MODIFY_REG(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL, Value);
1977 }
1978
1979 /**
1980 * @brief Get HSI divider
1981 * @rmtoll MSICFGR MSIFREQSEL LL_RCC_MSI_GetFrequency
1982 * @retval can be one of the following values:
1983 * @arg @ref LL_RCC_MSI_FREQ_4MHZ
1984 * @arg @ref LL_RCC_MSI_FREQ_16MHZ
1985 */
LL_RCC_MSI_GetFrequency(void)1986 __STATIC_INLINE uint32_t LL_RCC_MSI_GetFrequency(void)
1987 {
1988 return (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL));
1989 }
1990
1991
1992 /**
1993 * @brief Get MSI Calibration value
1994 * @note When MSITRIM is written, MSICAL is updated with the sum of
1995 * MSITRIM and the factory trim value
1996 * @rmtoll MSICFGR MSICAL LL_RCC_MSI_GetCalibration
1997 * @retval A value between 0 and 255 (0xFF)
1998 */
LL_RCC_MSI_GetCalibration(void)1999 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
2000 {
2001 return (uint32_t)(READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSICAL) >> RCC_MSICFGR_MSICAL_Pos);
2002 }
2003
2004 /**
2005 * @brief Set MSI Calibration trimming
2006 * @note user-programmable trimming value that is added to the MSICAL
2007 * @note Default value is 16, which, when added to the MSICAL value,
2008 * should trim the MSI to 4 MHz +/- 1 %
2009 * @rmtoll MSICFGR MSITRIM LL_RCC_MSI_SetCalibTrimming
2010 * @param Value can be a value between 0 and 31
2011 * @retval None
2012 */
LL_RCC_MSI_SetCalibTrimming(uint32_t Value)2013 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
2014 {
2015 MODIFY_REG(RCC->MSICFGR, RCC_MSICFGR_MSITRIM, Value << RCC_MSICFGR_MSITRIM_Pos);
2016 }
2017
2018 /**
2019 * @brief Get MSI Calibration trimming
2020 * @rmtoll MSICFGR MSITRIM LL_RCC_MSI_GetCalibTrimming
2021 * @retval A value between 0 and 31
2022 */
LL_RCC_MSI_GetCalibTrimming(void)2023 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
2024 {
2025 return (uint32_t)(READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSITRIM) >> RCC_MSICFGR_MSITRIM_Pos);
2026 }
2027
2028 /**
2029 * @brief Enable MSI even in stop mode
2030 * @note MSI oscillator is forced ON even in Stop mode
2031 * @rmtoll STOPCR MSISTOPEN LL_RCC_MSI_EnableInStopMode
2032 * @retval None
2033 */
LL_RCC_MSI_EnableInStopMode(void)2034 __STATIC_INLINE void LL_RCC_MSI_EnableInStopMode(void)
2035 {
2036 SET_BIT(RCC->STOPCR, RCC_STOPCR_MSISTOPEN);
2037 }
2038
2039 /**
2040 * @brief Disable MSI in stop mode
2041 * @rmtoll STOPCR MSISTOPEN LL_RCC_MSI_DisableInStopMode
2042 * @retval None
2043 */
LL_RCC_MSI_DisableInStopMode(void)2044 __STATIC_INLINE void LL_RCC_MSI_DisableInStopMode(void)
2045 {
2046 CLEAR_BIT(RCC->STOPCR, RCC_STOPCR_MSISTOPEN);
2047 }
2048
2049 /**
2050 * @brief Check if MSI is enabled in stop mode
2051 * @rmtoll STOPCR MSISTOPEN LL_RCC_MSI_IsEnabledInStopMode
2052 * @retval State of bit (1 or 0).
2053 */
LL_RCC_MSI_IsEnabledInStopMode(void)2054 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledInStopMode(void)
2055 {
2056 return ((READ_BIT(RCC->STOPCR, RCC_STOPCR_MSISTOPEN) == RCC_STOPCR_MSISTOPEN) ? 1UL : 0UL);
2057 }
2058
2059 /**
2060 * @}
2061 */
2062
2063 /** @defgroup RCC_LL_EF_LSE LSE
2064 * @{
2065 */
2066
2067 /**
2068 * @brief Enable the Clock Security System on LSE
2069 * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
2070 * a clock failure is detected.
2071 * @rmtoll LSECFGR LSECSSON LL_RCC_LSE_EnableCSS
2072 * @retval None
2073 */
LL_RCC_LSE_EnableCSS(void)2074 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
2075 {
2076 SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSON);
2077 }
2078
2079 /**
2080 * @brief Disable the Clock Security System on LSE
2081 * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
2082 * a clock failure is detected.
2083 * @rmtoll LSECFGR LSECSSON LL_RCC_LSE_DisableCSS
2084 * @retval None
2085 */
LL_RCC_LSE_DisableCSS(void)2086 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
2087 {
2088 CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSON);
2089 }
2090
2091 /**
2092 * @brief Check if LSE failure is detected by Clock Security System
2093 * @rmtoll LSECFGR LSECSSD LL_RCC_LSE_IsFailureDetected
2094 * @retval State of bit (1 or 0).
2095 */
LL_RCC_LSE_IsFailureDetected(void)2096 __STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
2097 {
2098 return ((READ_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSD) != 0UL) ? 1UL : 0UL);
2099 }
2100
2101 /**
2102 * @brief Re-arm the Clock Security System on LSE
2103 * @note Once a clock failure is detected, the LSE Clock Security System can be re-armed providing that
2104 * LSECSSON is disabled.
2105 * @rmtoll LSECFGR LSECSSRA LL_RCC_LSE_ReArmCSS
2106 * @retval None
2107 */
LL_RCC_LSE_ReArmCSS(void)2108 __STATIC_INLINE void LL_RCC_LSE_ReArmCSS(void)
2109 {
2110 SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSRA);
2111 }
2112
2113 /**
2114 * @brief Enable external clock source (LSE bypass)
2115 * @rmtoll LSECFGR LSEBYP LL_RCC_LSE_EnableBypass
2116 * @retval None
2117 */
LL_RCC_LSE_EnableBypass(void)2118 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
2119 {
2120 SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP);
2121 }
2122
2123 /**
2124 * @brief Disable external clock source (LSE bypass)
2125 * @rmtoll LSECFGR LSEBYP LL_RCC_LSE_DisableBypass
2126 * @retval None
2127 */
LL_RCC_LSE_DisableBypass(void)2128 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
2129 {
2130 CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP);
2131 }
2132
2133 /**
2134 * @brief Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
2135 * @note The external clock must be enabled with the LSEON bit, to be used by the device.
2136 * The LSEEXT bit can be written only if the LSE oscillator is disabled.
2137 * @rmtoll LSECFGR LSEEXT LL_RCC_LSE_SelectDigitalClock
2138 * @retval None
2139 */
LL_RCC_LSE_SelectDigitalClock(void)2140 __STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
2141 {
2142 SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT);
2143 }
2144
2145 /**
2146 * @brief Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
2147 * @note The external clock must be enabled with the LSEON bit, to be used by the device.
2148 * The LSEEXT bit can be written only if the LSE oscillator is disabled.
2149 * @rmtoll LSECFGR LSEEXT LL_RCC_LSE_SelectAnalogClock
2150 * @retval None
2151 */
LL_RCC_LSE_SelectAnalogClock(void)2152 __STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
2153 {
2154 CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT);
2155 }
2156
2157 /**
2158 * @brief Set LSE oscillator drive capability
2159 * @note The oscillator is in Xtal mode when it is not in bypass mode.
2160 * @rmtoll LSECFGR LSEDRV LL_RCC_LSE_SetDriveCapability
2161 * @param LSEDrive This parameter can be one of the following values:
2162 * @arg @ref LL_RCC_LSEDRIVE_LOW
2163 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2164 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2165 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2166 * @retval None
2167 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)2168 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2169 {
2170 MODIFY_REG(RCC->LSECFGR, RCC_LSECFGR_LSEDRV, LSEDrive);
2171 }
2172
2173 /**
2174 * @brief Get LSE oscillator drive capability
2175 * @rmtoll LSECFGR LSEDRV LL_RCC_LSE_GetDriveCapability
2176 * @retval Returned value can be one of the following values:
2177 * @arg @ref LL_RCC_LSEDRIVE_LOW
2178 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2179 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2180 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2181 */
LL_RCC_LSE_GetDriveCapability(void)2182 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2183 {
2184 return (uint32_t)(READ_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEDRV));
2185 }
2186
2187 /**
2188 * @brief Enable Low Speed External (LSE) crystal
2189 * @rmtoll CSR LSEONS LL_RCC_LSE_Enable
2190 * @retval None
2191 */
LL_RCC_LSE_Enable(void)2192 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
2193 {
2194 WRITE_REG(RCC->CSR, RCC_CSR_LSEONS);
2195 }
2196
2197 /**
2198 * @brief Disable Low Speed External (LSE) crystal
2199 * @rmtoll CCR LSEONC LL_RCC_LSE_Disable
2200 * @retval None
2201 */
LL_RCC_LSE_Disable(void)2202 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
2203 {
2204 WRITE_REG(RCC->CCR, RCC_CCR_LSEONC);
2205 }
2206
2207 /**
2208 * @brief Check if LSE oscillator Ready
2209 * @rmtoll SR LSERDY LL_RCC_LSE_IsReady
2210 * @retval State of bit (1 or 0).
2211 */
LL_RCC_LSE_IsReady(void)2212 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
2213 {
2214 return ((READ_BIT(RCC->SR, RCC_SR_LSERDY) != 0UL) ? 1UL : 0UL);
2215 }
2216
2217 /**
2218 * @brief Enable the LSE clock glitch filter
2219 * @note This API shall be called only when LSE is disabled.
2220 * @rmtoll LSECFGR LSEGFON LL_RCC_LSE_EnableGlitchFilter
2221 * @retval None
2222 */
LL_RCC_LSE_EnableGlitchFilter(void)2223 __STATIC_INLINE void LL_RCC_LSE_EnableGlitchFilter(void)
2224 {
2225 SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEGFON);
2226 }
2227
2228 /**
2229 * @brief Disable the LSE clock glitch filter
2230 * @note This API shall be called only when LSE is disabled.
2231 * @rmtoll LSECFGR LSEGFON LL_RCC_LSE_DisableGlitchFilter
2232 * @retval None
2233 */
LL_RCC_LSE_DisableGlitchFilter(void)2234 __STATIC_INLINE void LL_RCC_LSE_DisableGlitchFilter(void)
2235 {
2236 CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEGFON);
2237 }
2238
2239 /**
2240 * @brief Check if LSE clock glitch filter is enabled
2241 * @rmtoll LSECFGR LSEGFON LL_RCC_LSE_IsEnabledGlitchFilter
2242 * @retval State of bit (1 or 0).
2243 */
LL_RCC_LSE_IsEnabledGlitchFilter(void)2244 __STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabledGlitchFilter(void)
2245 {
2246 return ((READ_BIT(RCC->STOPCR, RCC_LSECFGR_LSEGFON) == RCC_LSECFGR_LSEGFON) ? 1UL : 0UL);
2247 }
2248
2249 /**
2250 * @}
2251 */
2252
2253 /** @defgroup RCC_LL_EF_LSI LSI
2254 * @{
2255 */
2256
2257 /**
2258 * @brief Enable LSI Oscillator
2259 * @rmtoll CSR LSIONS LL_RCC_LSI_Enable
2260 * @retval None
2261 */
LL_RCC_LSI_Enable(void)2262 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2263 {
2264 WRITE_REG(RCC->CSR, RCC_CSR_LSIONS);
2265 }
2266
2267 /**
2268 * @brief Disable LSI Oscillator
2269 * @rmtoll CCR LSIONC LL_RCC_LSI_Disable
2270 * @retval None
2271 */
LL_RCC_LSI_Disable(void)2272 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2273 {
2274 WRITE_REG(RCC->CCR, RCC_CCR_LSIONC);
2275 }
2276
2277 /**
2278 * @brief Check if LSI is Ready
2279 * @rmtoll SR LSIRDY LL_RCC_LSI_IsReady
2280 * @retval State of bit (1 or 0).
2281 */
LL_RCC_LSI_IsReady(void)2282 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2283 {
2284 return ((READ_BIT(RCC->SR, RCC_SR_LSIRDY) != 0UL) ? 1UL : 0UL);
2285 }
2286
2287 /**
2288 * @}
2289 */
2290
2291 /** @defgroup RCC_LL_EF_System System
2292 * @{
2293 */
2294
2295 /**
2296 * @brief Configure the CPU clock source
2297 * @rmtoll CFGR1 CPUSW LL_RCC_SetCpuClkSource
2298 * @param Source This parameter can be one of the following values:
2299 * @arg @ref LL_RCC_CPU_CLKSOURCE_HSI
2300 * @arg @ref LL_RCC_CPU_CLKSOURCE_MSI
2301 * @arg @ref LL_RCC_CPU_CLKSOURCE_HSE
2302 * @arg @ref LL_RCC_CPU_CLKSOURCE_IC1
2303 * @retval None
2304 */
LL_RCC_SetCpuClkSource(uint32_t Source)2305 __STATIC_INLINE void LL_RCC_SetCpuClkSource(uint32_t Source)
2306 {
2307 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_CPUSW, Source);
2308 }
2309
2310 /**
2311 * @brief Get the CPU clock source
2312 * @rmtoll CFGR1 CPUSWS LL_RCC_GetCpuClkSource
2313 * @retval Returned value can be one of the following values:
2314 * @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_HSI
2315 * @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_MSI
2316 * @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_HSE
2317 * @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_IC1
2318 */
LL_RCC_GetCpuClkSource(void)2319 __STATIC_INLINE uint32_t LL_RCC_GetCpuClkSource(void)
2320 {
2321 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_CPUSWS));
2322 }
2323
2324 /**
2325 * @brief Configure the system clock source (bus clock)
2326 * @rmtoll CFGR1 SYSSW LL_RCC_SetSysClkSource
2327 * @param Source This parameter can be one of the following values:
2328 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2329 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
2330 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2331 * @arg @ref LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11
2332 * @retval None
2333 */
LL_RCC_SetSysClkSource(uint32_t Source)2334 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2335 {
2336 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SYSSW, Source);
2337 }
2338
2339 /**
2340 * @brief Get the system clock source (bus clock)
2341 * @rmtoll CFGR1 SYSSWS LL_RCC_GetSysClkSource
2342 * @retval Returned value can be one of the following values:
2343 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2344 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
2345 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2346 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11
2347 */
LL_RCC_GetSysClkSource(void)2348 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2349 {
2350 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SYSSWS));
2351 }
2352
2353 /**
2354 * @brief Configure the system wakeup clock source
2355 * @rmtoll CFGR1 STOPWUCK LL_RCC_SetSysWakeUpClkSource
2356 * @param Source This parameter can be one of the following values:
2357 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2358 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_MSI
2359 * @retval None
2360 */
LL_RCC_SetSysWakeUpClkSource(uint32_t Source)2361 __STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
2362 {
2363 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, Source);
2364 }
2365
2366 /**
2367 * @brief Get the system wakeup clock source
2368 * @rmtoll CFGR1 STOPWUCK LL_RCC_GetSysWakeUpClkSource
2369 * @retval Returned value can be one of the following values:
2370 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2371 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_MSI
2372 */
LL_RCC_GetSysWakeUpClkSource(void)2373 __STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
2374 {
2375 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK));
2376 }
2377
2378 /**
2379 * @brief Set AHB prescaler
2380 * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler
2381 * @param Prescaler This parameter can be one of the following values:
2382 * @arg @ref LL_RCC_AHB_DIV_1
2383 * @arg @ref LL_RCC_AHB_DIV_2
2384 * @arg @ref LL_RCC_AHB_DIV_4
2385 * @arg @ref LL_RCC_AHB_DIV_8
2386 * @arg @ref LL_RCC_AHB_DIV_16
2387 * @arg @ref LL_RCC_AHB_DIV_32
2388 * @arg @ref LL_RCC_AHB_DIV_64
2389 * @arg @ref LL_RCC_AHB_DIV_128
2390 * @retval None
2391 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2392 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2393 {
2394 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler);
2395 }
2396
2397 /**
2398 * @brief Get AHB prescaler
2399 * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler
2400 * @retval Returned value can be one of the following values:
2401 * @arg @ref LL_RCC_AHB_DIV_1
2402 * @arg @ref LL_RCC_AHB_DIV_2
2403 * @arg @ref LL_RCC_AHB_DIV_4
2404 * @arg @ref LL_RCC_AHB_DIV_8
2405 * @arg @ref LL_RCC_AHB_DIV_16
2406 * @arg @ref LL_RCC_AHB_DIV_32
2407 * @arg @ref LL_RCC_AHB_DIV_64
2408 * @arg @ref LL_RCC_AHB_DIV_128
2409 */
LL_RCC_GetAHBPrescaler(void)2410 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2411 {
2412 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE));
2413 }
2414
2415 /**
2416 * @brief Set APB1 prescaler
2417 * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler
2418 * @param Prescaler This parameter can be one of the following values:
2419 * @arg @ref LL_RCC_APB1_DIV_1
2420 * @arg @ref LL_RCC_APB1_DIV_2
2421 * @arg @ref LL_RCC_APB1_DIV_4
2422 * @arg @ref LL_RCC_APB1_DIV_8
2423 * @arg @ref LL_RCC_APB1_DIV_16
2424 * @arg @ref LL_RCC_APB1_DIV_32
2425 * @arg @ref LL_RCC_APB1_DIV_64
2426 * @arg @ref LL_RCC_APB1_DIV_128
2427 * @retval None
2428 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2429 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2430 {
2431 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler);
2432 }
2433
2434 /**
2435 * @brief Get APB1 prescaler
2436 * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler
2437 * @retval Returned value can be one of the following values:
2438 * @arg @ref LL_RCC_APB1_DIV_1
2439 * @arg @ref LL_RCC_APB1_DIV_2
2440 * @arg @ref LL_RCC_APB1_DIV_4
2441 * @arg @ref LL_RCC_APB1_DIV_8
2442 * @arg @ref LL_RCC_APB1_DIV_16
2443 * @arg @ref LL_RCC_APB1_DIV_32
2444 * @arg @ref LL_RCC_APB1_DIV_64
2445 * @arg @ref LL_RCC_APB1_DIV_128
2446 */
LL_RCC_GetAPB1Prescaler(void)2447 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2448 {
2449 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1));
2450 }
2451
2452 /**
2453 * @brief Set APB2 prescaler
2454 * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler
2455 * @param Prescaler This parameter can be one of the following values:
2456 * @arg @ref LL_RCC_APB2_DIV_1
2457 * @arg @ref LL_RCC_APB2_DIV_2
2458 * @arg @ref LL_RCC_APB2_DIV_4
2459 * @arg @ref LL_RCC_APB2_DIV_8
2460 * @arg @ref LL_RCC_APB2_DIV_16
2461 * @arg @ref LL_RCC_APB2_DIV_32
2462 * @arg @ref LL_RCC_APB2_DIV_64
2463 * @arg @ref LL_RCC_APB2_DIV_128
2464 * @retval None
2465 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2466 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2467 {
2468 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler);
2469 }
2470
2471 /**
2472 * @brief Get APB2 prescaler
2473 * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler
2474 * @retval Returned value can be one of the following values:
2475 * @arg @ref LL_RCC_APB2_DIV_1
2476 * @arg @ref LL_RCC_APB2_DIV_2
2477 * @arg @ref LL_RCC_APB2_DIV_4
2478 * @arg @ref LL_RCC_APB2_DIV_8
2479 * @arg @ref LL_RCC_APB2_DIV_16
2480 * @arg @ref LL_RCC_APB2_DIV_32
2481 * @arg @ref LL_RCC_APB2_DIV_64
2482 * @arg @ref LL_RCC_APB2_DIV_128
2483 */
LL_RCC_GetAPB2Prescaler(void)2484 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2485 {
2486 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2));
2487 }
2488
2489 /**
2490 * @brief Set APB4 prescaler
2491 * @rmtoll CFGR2 PPRE4 LL_RCC_SetAPB4Prescaler
2492 * @param Prescaler This parameter can be one of the following values:
2493 * @arg @ref LL_RCC_APB4_DIV_1
2494 * @arg @ref LL_RCC_APB4_DIV_2
2495 * @arg @ref LL_RCC_APB4_DIV_4
2496 * @arg @ref LL_RCC_APB4_DIV_8
2497 * @arg @ref LL_RCC_APB4_DIV_16
2498 * @arg @ref LL_RCC_APB4_DIV_32
2499 * @arg @ref LL_RCC_APB4_DIV_64
2500 * @arg @ref LL_RCC_APB4_DIV_128
2501 * @retval None
2502 */
LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)2503 __STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
2504 {
2505 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE4, Prescaler);
2506 }
2507
2508 /**
2509 * @brief Get APB4 prescaler
2510 * @rmtoll CFGR2 PPRE4 LL_RCC_GetAPB4Prescaler
2511 * @retval Returned value can be one of the following values:
2512 * @arg @ref LL_RCC_APB4_DIV_1
2513 * @arg @ref LL_RCC_APB4_DIV_2
2514 * @arg @ref LL_RCC_APB4_DIV_4
2515 * @arg @ref LL_RCC_APB4_DIV_8
2516 * @arg @ref LL_RCC_APB4_DIV_16
2517 * @arg @ref LL_RCC_APB4_DIV_32
2518 * @arg @ref LL_RCC_APB4_DIV_64
2519 * @arg @ref LL_RCC_APB4_DIV_128
2520 */
LL_RCC_GetAPB4Prescaler(void)2521 __STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
2522 {
2523 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE4));
2524 }
2525
2526 /**
2527 * @brief Set APB5 prescaler
2528 * @rmtoll CFGR2 PPRE5 LL_RCC_SetAPB5Prescaler
2529 * @param Prescaler This parameter can be one of the following values:
2530 * @arg @ref LL_RCC_APB5_DIV_1
2531 * @arg @ref LL_RCC_APB5_DIV_2
2532 * @arg @ref LL_RCC_APB5_DIV_4
2533 * @arg @ref LL_RCC_APB5_DIV_8
2534 * @arg @ref LL_RCC_APB5_DIV_16
2535 * @arg @ref LL_RCC_APB5_DIV_32
2536 * @arg @ref LL_RCC_APB5_DIV_64
2537 * @arg @ref LL_RCC_APB5_DIV_128
2538 * @retval None
2539 */
LL_RCC_SetAPB5Prescaler(uint32_t Prescaler)2540 __STATIC_INLINE void LL_RCC_SetAPB5Prescaler(uint32_t Prescaler)
2541 {
2542 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE5, Prescaler);
2543 }
2544
2545 /**
2546 * @brief Get APB5 prescaler
2547 * @rmtoll CFGR2 PPRE5 LL_RCC_GetAPB5Prescaler
2548 * @retval Returned value can be one of the following values:
2549 * @arg @ref LL_RCC_APB5_DIV_1
2550 * @arg @ref LL_RCC_APB5_DIV_2
2551 * @arg @ref LL_RCC_APB5_DIV_4
2552 * @arg @ref LL_RCC_APB5_DIV_8
2553 * @arg @ref LL_RCC_APB5_DIV_16
2554 * @arg @ref LL_RCC_APB5_DIV_32
2555 * @arg @ref LL_RCC_APB5_DIV_64
2556 * @arg @ref LL_RCC_APB5_DIV_128
2557 */
LL_RCC_GetAPB5Prescaler(void)2558 __STATIC_INLINE uint32_t LL_RCC_GetAPB5Prescaler(void)
2559 {
2560 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE5));
2561 }
2562
2563 /**
2564 * @}
2565 */
2566
2567 /** @defgroup RCC_LL_EF_MCO MCO
2568 * @{
2569 */
2570
2571 /**
2572 * @brief Enable MCOx output
2573 * @note The clock provided to the MCOx outputs must not exceed the maximum IO speed,
2574 * refer to the product datasheet for information about the supported IO speed.
2575 * @rmtoll MISCENSR MCO1ENS LL_RCC_EnableMCO\n
2576 * MISCENSR MCO2ENS LL_RCC_EnableMCO
2577 * @param MCOx This parameter can be one or a combination of the following values:
2578 * @arg @ref LL_RCC_MCO1
2579 * @arg @ref LL_RCC_MCO2
2580 * @retval None
2581 */
LL_RCC_EnableMCO(uint32_t MCOx)2582 __STATIC_INLINE void LL_RCC_EnableMCO(uint32_t MCOx)
2583 {
2584 WRITE_REG(RCC->MISCENSR, MCOx);
2585 }
2586
2587 /**
2588 * @brief Disable MCOx output
2589 * @rmtoll MISCENCR MCO1ENC LL_RCC_DisableMCO\n
2590 * MISCENCR MCO2ENC LL_RCC_DisableMCO
2591 * @param MCOx This parameter can be one or a combination of the following values:
2592 * @arg @ref LL_RCC_MCO1
2593 * @arg @ref LL_RCC_MCO2
2594 * @retval None
2595 */
LL_RCC_DisableMCO(uint32_t MCOx)2596 __STATIC_INLINE void LL_RCC_DisableMCO(uint32_t MCOx)
2597 {
2598 WRITE_REG(RCC->MISCENCR, MCOx);
2599 }
2600
2601 /**
2602 * @brief Configure MCOx
2603 * @note The clock provided to the MCOx outputs must not exceed the maximum IO speed,
2604 * refer to the product datasheet for information about the supported IO speed.
2605 * @note The MCO switch to the new clock source only occurs when the previous clock source is active (dynamic switch).
2606 * @rmtoll CCIPR5 MCO1SEL LL_RCC_ConfigMCO\n
2607 * CCIPR5 MCO1PRE LL_RCC_ConfigMCO\n
2608 * CCIPR5 MCO2SEL LL_RCC_ConfigMCO\n
2609 * CCIPR5 MCO2PRE LL_RCC_ConfigMCO
2610 * @param MCOxSource This parameter can be one of the following values:
2611 * @arg @ref LL_RCC_MCO1SOURCE_LSI
2612 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2613 * @arg @ref LL_RCC_MCO1SOURCE_MSI
2614 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2615 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2616 * @arg @ref LL_RCC_MCO1SOURCE_IC5
2617 * @arg @ref LL_RCC_MCO1SOURCE_IC10
2618 * @arg @ref LL_RCC_MCO1SOURCE_SYSA
2619 * @arg @ref LL_RCC_MCO2SOURCE_LSI
2620 * @arg @ref LL_RCC_MCO2SOURCE_LSE
2621 * @arg @ref LL_RCC_MCO2SOURCE_MSI
2622 * @arg @ref LL_RCC_MCO2SOURCE_HSI
2623 * @arg @ref LL_RCC_MCO2SOURCE_HSE
2624 * @arg @ref LL_RCC_MCO2SOURCE_IC15
2625 * @arg @ref LL_RCC_MCO2SOURCE_IC20
2626 * @arg @ref LL_RCC_MCO2SOURCE_SYSB
2627 * @param MCOxPrescaler This parameter can be one of the following values:
2628 * @arg @ref LL_RCC_MCO1_DIV_1
2629 * @arg @ref LL_RCC_MCO1_DIV_2
2630 * @arg @ref LL_RCC_MCO1_DIV_3
2631 * @arg @ref LL_RCC_MCO1_DIV_4
2632 * @arg @ref LL_RCC_MCO1_DIV_5
2633 * @arg @ref LL_RCC_MCO1_DIV_6
2634 * @arg @ref LL_RCC_MCO1_DIV_7
2635 * @arg @ref LL_RCC_MCO1_DIV_8
2636 * @arg @ref LL_RCC_MCO1_DIV_9
2637 * @arg @ref LL_RCC_MCO1_DIV_10
2638 * @arg @ref LL_RCC_MCO1_DIV_11
2639 * @arg @ref LL_RCC_MCO1_DIV_12
2640 * @arg @ref LL_RCC_MCO1_DIV_13
2641 * @arg @ref LL_RCC_MCO1_DIV_14
2642 * @arg @ref LL_RCC_MCO1_DIV_15
2643 * @arg @ref LL_RCC_MCO2_DIV_1
2644 * @arg @ref LL_RCC_MCO2_DIV_2
2645 * @arg @ref LL_RCC_MCO2_DIV_3
2646 * @arg @ref LL_RCC_MCO2_DIV_4
2647 * @arg @ref LL_RCC_MCO2_DIV_5
2648 * @arg @ref LL_RCC_MCO2_DIV_6
2649 * @arg @ref LL_RCC_MCO2_DIV_7
2650 * @arg @ref LL_RCC_MCO2_DIV_8
2651 * @arg @ref LL_RCC_MCO2_DIV_9
2652 * @arg @ref LL_RCC_MCO2_DIV_10
2653 * @arg @ref LL_RCC_MCO2_DIV_11
2654 * @arg @ref LL_RCC_MCO2_DIV_12
2655 * @arg @ref LL_RCC_MCO2_DIV_13
2656 * @arg @ref LL_RCC_MCO2_DIV_14
2657 * @arg @ref LL_RCC_MCO2_DIV_15
2658 * @arg @ref LL_RCC_MCO2_DIV_16
2659 * @retval None
2660 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2661 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2662 {
2663 MODIFY_REG(RCC->CCIPR5, ((MCOxSource | MCOxPrescaler) >> 16U), \
2664 (MCOxSource & (RCC_CCIPR5_MCO1SEL | RCC_CCIPR5_MCO2SEL)) | (MCOxPrescaler & (RCC_CCIPR5_MCO1PRE | RCC_CCIPR5_MCO2PRE)));
2665 }
2666
2667 /**
2668 * @}
2669 */
2670
2671 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2672 * @{
2673 */
2674
2675 /**
2676 * @brief Configure periph clock source
2677 * @rmtoll CCIPR4 * LL_RCC_SetClockSource\n
2678 * CCIPR6 * LL_RCC_SetClockSource\n
2679 * CCIPR8 * LL_RCC_SetClockSource\n
2680 * CCIPR9 * LL_RCC_SetClockSource\n
2681 * CCIPR12 * LL_RCC_SetClockSource\n
2682 * CCIPR13 * LL_RCC_SetClockSource\n
2683 * CCIPR14 * LL_RCC_SetClockSource
2684 * @param ClkSource This parameter can be one of the following values:
2685 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2686 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP
2687 * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10
2688 * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15
2689 * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI
2690 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2691 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2692 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP
2693 * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10
2694 * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15
2695 * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI
2696 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2697 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2698 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP
2699 * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10
2700 * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15
2701 * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI
2702 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2703 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
2704 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP
2705 * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10
2706 * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15
2707 * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI
2708 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
2709 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
2710 * @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP
2711 * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10
2712 * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15
2713 * @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI
2714 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
2715 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1
2716 * @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP
2717 * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10
2718 * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15
2719 * @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI
2720 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI
2721 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2722 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2723 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15
2724 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2725 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2726 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG
2727 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
2728 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2729 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15
2730 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2731 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2732 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG
2733 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4
2734 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP
2735 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15
2736 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
2737 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
2738 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG
2739 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4
2740 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP
2741 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15
2742 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE
2743 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI
2744 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG
2745 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4
2746 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP
2747 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15
2748 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE
2749 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI
2750 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG
2751 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
2752 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
2753 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
2754 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
2755 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
2756 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
2757 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
2758 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
2759 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
2760 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
2761 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
2762 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
2763 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2
2764 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
2765 * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7
2766 * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8
2767 * @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI
2768 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
2769 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
2770 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1
2771 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2
2772 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
2773 * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7
2774 * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8
2775 * @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI
2776 * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
2777 * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
2778 * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1
2779 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK
2780 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP
2781 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4
2782 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5
2783 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK
2784 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP
2785 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4
2786 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5
2787 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
2788 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
2789 * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8
2790 * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9
2791 * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI
2792 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
2793 * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
2794 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
2795 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
2796 * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8
2797 * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9
2798 * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI
2799 * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
2800 * @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN
2801 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1
2802 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
2803 * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8
2804 * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9
2805 * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI
2806 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
2807 * @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN
2808 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2
2809 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP
2810 * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9
2811 * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14
2812 * @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI
2813 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI
2814 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE
2815 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2
2816 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP
2817 * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9
2818 * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14
2819 * @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI
2820 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI
2821 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE
2822 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
2823 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP
2824 * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8
2825 * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9
2826 * @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI
2827 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
2828 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN
2829 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2830 * @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP
2831 * @arg @ref LL_RCC_UART4_CLKSOURCE_IC9
2832 * @arg @ref LL_RCC_UART4_CLKSOURCE_IC14
2833 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2834 * @arg @ref LL_RCC_UART4_CLKSOURCE_MSI
2835 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2836 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2837 * @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP
2838 * @arg @ref LL_RCC_UART5_CLKSOURCE_IC9
2839 * @arg @ref LL_RCC_UART5_CLKSOURCE_IC14
2840 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2841 * @arg @ref LL_RCC_UART5_CLKSOURCE_MSI
2842 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2843 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
2844 * @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP
2845 * @arg @ref LL_RCC_UART7_CLKSOURCE_IC9
2846 * @arg @ref LL_RCC_UART7_CLKSOURCE_IC14
2847 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
2848 * @arg @ref LL_RCC_UART7_CLKSOURCE_MSI
2849 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
2850 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
2851 * @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP
2852 * @arg @ref LL_RCC_UART8_CLKSOURCE_IC9
2853 * @arg @ref LL_RCC_UART8_CLKSOURCE_IC14
2854 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
2855 * @arg @ref LL_RCC_UART8_CLKSOURCE_MSI
2856 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
2857 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2
2858 * @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP
2859 * @arg @ref LL_RCC_UART9_CLKSOURCE_IC9
2860 * @arg @ref LL_RCC_UART9_CLKSOURCE_IC14
2861 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
2862 * @arg @ref LL_RCC_UART9_CLKSOURCE_MSI
2863 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
2864 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2865 * @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP
2866 * @arg @ref LL_RCC_USART1_CLKSOURCE_IC9
2867 * @arg @ref LL_RCC_USART1_CLKSOURCE_IC14
2868 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2869 * @arg @ref LL_RCC_USART1_CLKSOURCE_MSI
2870 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2871 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2872 * @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP
2873 * @arg @ref LL_RCC_USART2_CLKSOURCE_IC9
2874 * @arg @ref LL_RCC_USART2_CLKSOURCE_IC14
2875 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2876 * @arg @ref LL_RCC_USART2_CLKSOURCE_MSI
2877 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2878 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2879 * @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP
2880 * @arg @ref LL_RCC_USART3_CLKSOURCE_IC9
2881 * @arg @ref LL_RCC_USART3_CLKSOURCE_IC14
2882 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2883 * @arg @ref LL_RCC_USART3_CLKSOURCE_MSI
2884 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2885 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
2886 * @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP
2887 * @arg @ref LL_RCC_USART6_CLKSOURCE_IC9
2888 * @arg @ref LL_RCC_USART6_CLKSOURCE_IC14
2889 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
2890 * @arg @ref LL_RCC_USART6_CLKSOURCE_MSI
2891 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
2892 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2
2893 * @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP
2894 * @arg @ref LL_RCC_USART10_CLKSOURCE_IC9
2895 * @arg @ref LL_RCC_USART10_CLKSOURCE_IC14
2896 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE
2897 * @arg @ref LL_RCC_USART10_CLKSOURCE_MSI
2898 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI
2899 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
2900 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP
2901 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3
2902 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4
2903 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
2904 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP
2905 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3
2906 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4
2907 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK
2908 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP
2909 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3
2910 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4
2911 * @retval None
2912 */
LL_RCC_SetClockSource(uint32_t ClkSource)2913 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
2914 {
2915 volatile uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CCIPR1 + LL_CLKSOURCE_REG(ClkSource));
2916 MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
2917 }
2918
2919 /**
2920 * @brief Set ADC prescaler
2921 * @rmtoll CCIPR1 ADCPRE LL_RCC_SetADCPrescaler
2922 * @param Prescaler This parameter must be a number between Min_Data = 0 and Max_Data = 255 for prescaler 1 to 256
2923 * @retval None
2924 */
LL_RCC_SetADCPrescaler(uint32_t Prescaler)2925 __STATIC_INLINE void LL_RCC_SetADCPrescaler(uint32_t Prescaler)
2926 {
2927 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCPRE, (Prescaler << RCC_CCIPR1_ADCPRE_Pos));
2928 }
2929
2930 /**
2931 * @brief Get ADC prescaler
2932 * @rmtoll CCIPR1 ADCPRE LL_RCC_GetADCPrescaler
2933 * @retval Returned value between Min_Data = 0 and Max_Data = 255 for prescaler 1 to 256
2934 */
LL_RCC_GetADCPrescaler(void)2935 __STATIC_INLINE uint32_t LL_RCC_GetADCPrescaler(void)
2936 {
2937 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADCPRE) >> RCC_CCIPR1_ADCPRE_Pos);
2938 }
2939
2940 /**
2941 * @brief Configure ADCx Kernel clock source
2942 * @rmtoll CCIPR1 ADC12SEL LL_RCC_SetADCClockSource
2943 * @param ClkSource This parameter can be one of the following values:
2944 * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK
2945 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
2946 * @arg @ref LL_RCC_ADC_CLKSOURCE_IC7
2947 * @arg @ref LL_RCC_ADC_CLKSOURCE_IC8
2948 * @arg @ref LL_RCC_ADC_CLKSOURCE_MSI
2949 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
2950 * @arg @ref LL_RCC_ADC_CLKSOURCE_I2S_CKIN
2951 * @arg @ref LL_RCC_ADC_CLKSOURCE_TIMG
2952 * @retval None
2953 */
LL_RCC_SetADCClockSource(uint32_t ClkSource)2954 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
2955 {
2956 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADC12SEL, ClkSource);
2957 }
2958
2959 /**
2960 * @brief Configure ADFx Kernel clock source
2961 * @rmtoll CCIPR1 ADF1SEL LL_RCC_SetADFClockSource
2962 * @param ClkSource This parameter can be one of the following values:
2963 * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK
2964 * @arg @ref LL_RCC_ADF1_CLKSOURCE_CLKP
2965 * @arg @ref LL_RCC_ADF1_CLKSOURCE_IC7
2966 * @arg @ref LL_RCC_ADF1_CLKSOURCE_IC8
2967 * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSI
2968 * @arg @ref LL_RCC_ADF1_CLKSOURCE_HSI
2969 * @arg @ref LL_RCC_ADF1_CLKSOURCE_I2S_CKIN
2970 * @arg @ref LL_RCC_ADF1_CLKSOURCE_TIMG
2971 * @retval None
2972 */
LL_RCC_SetADFClockSource(uint32_t ClkSource)2973 __STATIC_INLINE void LL_RCC_SetADFClockSource(uint32_t ClkSource)
2974 {
2975 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL, ClkSource);
2976 }
2977
2978 /**
2979 * @brief Configure CLKP Kernel clock source
2980 * @rmtoll CCIPR7 PERSEL LL_RCC_SetCLKPClockSource
2981 * @param ClkSource This parameter can be one of the following values:
2982 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
2983 * @arg @ref LL_RCC_CLKP_CLKSOURCE_MSI
2984 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
2985 * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC19
2986 * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC5
2987 * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC10
2988 * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC15
2989 * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC20
2990 * @retval None
2991 */
LL_RCC_SetCLKPClockSource(uint32_t ClkSource)2992 __STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
2993 {
2994 MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_PERSEL, ClkSource);
2995 }
2996
2997 /**
2998 * @brief Configure DCMIPP Kernel clock source
2999 * @rmtoll CCIPR1 DCMIPPSEL LL_RCC_SetDCMIPPClockSource
3000 * @param ClkSource This parameter can be one of the following values:
3001 * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_PCLK5
3002 * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_CLKP
3003 * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_IC17
3004 * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_HSI
3005 * @retval None
3006 */
LL_RCC_SetDCMIPPClockSource(uint32_t ClkSource)3007 __STATIC_INLINE void LL_RCC_SetDCMIPPClockSource(uint32_t ClkSource)
3008 {
3009 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_DCMIPPSEL, ClkSource);
3010 }
3011
3012 /**
3013 * @brief Configure ETHx Kernel clock source
3014 * @rmtoll CCIPR2 ETH1CLKSEL LL_RCC_SetETHClockSource
3015 * @param ClkSource This parameter can be one of the following values:
3016 * @arg @ref LL_RCC_ETH1_CLKSOURCE_HCLK
3017 * @arg @ref LL_RCC_ETH1_CLKSOURCE_CLKP
3018 * @arg @ref LL_RCC_ETH1_CLKSOURCE_IC12
3019 * @arg @ref LL_RCC_ETH1_CLKSOURCE_HSE
3020 * @retval None
3021 */
LL_RCC_SetETHClockSource(uint32_t ClkSource)3022 __STATIC_INLINE void LL_RCC_SetETHClockSource(uint32_t ClkSource)
3023 {
3024 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1CLKSEL, ClkSource);
3025 }
3026
3027 /**
3028 * @brief Configure ETHx PTP Kernel clock source
3029 * @rmtoll CCIPR2 ETH1PTPSEL LL_RCC_SetETHPTPClockSource
3030 * @param ClkSource This parameter can be one of the following values:
3031 * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HCLK
3032 * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_CLKP
3033 * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_IC13
3034 * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HSE
3035 * @retval None
3036 */
LL_RCC_SetETHPTPClockSource(uint32_t ClkSource)3037 __STATIC_INLINE void LL_RCC_SetETHPTPClockSource(uint32_t ClkSource)
3038 {
3039 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPSEL, ClkSource);
3040 }
3041
3042 /**
3043 * @brief Configure ETHx PHY interface
3044 * @rmtoll CCIPR2 ETH1SEL LL_RCC_SetETHPHYInterface
3045 * @param Interface This parameter can be one of the following values:
3046 * @arg @ref LL_RCC_ETH1PHY_IF_MII
3047 * @arg @ref LL_RCC_ETH1PHY_IF_RGMII
3048 * @arg @ref LL_RCC_ETH1PHY_IF_RMII
3049 * @retval None
3050 */
LL_RCC_SetETHPHYInterface(uint32_t Interface)3051 __STATIC_INLINE void LL_RCC_SetETHPHYInterface(uint32_t Interface)
3052 {
3053 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1SEL, Interface);
3054 }
3055
3056 /**
3057 * @brief Set ETH1 PTP Kernel clock divider
3058 * @rmtoll CCIPR2 ETH1PTPDIV LL_RCC_SetETH1PTPDivider
3059 * @param Divider This parameter can be one of the following values:
3060 * @arg @ref LL_RCC_ETH1PTP_DIV_1
3061 * @arg @ref LL_RCC_ETH1PTP_DIV_2
3062 * @arg @ref LL_RCC_ETH1PTP_DIV_3
3063 * @arg @ref LL_RCC_ETH1PTP_DIV_4
3064 * @arg @ref LL_RCC_ETH1PTP_DIV_5
3065 * @arg @ref LL_RCC_ETH1PTP_DIV_6
3066 * @arg @ref LL_RCC_ETH1PTP_DIV_7
3067 * @arg @ref LL_RCC_ETH1PTP_DIV_8
3068 * @arg @ref LL_RCC_ETH1PTP_DIV_9
3069 * @arg @ref LL_RCC_ETH1PTP_DIV_10
3070 * @arg @ref LL_RCC_ETH1PTP_DIV_11
3071 * @arg @ref LL_RCC_ETH1PTP_DIV_12
3072 * @arg @ref LL_RCC_ETH1PTP_DIV_13
3073 * @arg @ref LL_RCC_ETH1PTP_DIV_14
3074 * @arg @ref LL_RCC_ETH1PTP_DIV_15
3075 * @arg @ref LL_RCC_ETH1PTP_DIV_16
3076 * @retval None.
3077 */
LL_RCC_SetETH1PTPDivider(uint32_t Divider)3078 __STATIC_INLINE void LL_RCC_SetETH1PTPDivider(uint32_t Divider)
3079 {
3080 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPDIV, Divider);
3081 }
3082
3083 /**
3084 * @brief Get ETH1 PTP Kernel clock divider
3085 * @rmtoll CCIPR2 ETH1PTPDIV LL_RCC_GetETH1PTPDivider
3086 * @retval can be one of the following values:
3087 * @arg @ref LL_RCC_ETH1PTP_DIV_1
3088 * @arg @ref LL_RCC_ETH1PTP_DIV_2
3089 * @arg @ref LL_RCC_ETH1PTP_DIV_3
3090 * @arg @ref LL_RCC_ETH1PTP_DIV_4
3091 * @arg @ref LL_RCC_ETH1PTP_DIV_5
3092 * @arg @ref LL_RCC_ETH1PTP_DIV_6
3093 * @arg @ref LL_RCC_ETH1PTP_DIV_7
3094 * @arg @ref LL_RCC_ETH1PTP_DIV_8
3095 * @arg @ref LL_RCC_ETH1PTP_DIV_9
3096 * @arg @ref LL_RCC_ETH1PTP_DIV_10
3097 * @arg @ref LL_RCC_ETH1PTP_DIV_11
3098 * @arg @ref LL_RCC_ETH1PTP_DIV_12
3099 * @arg @ref LL_RCC_ETH1PTP_DIV_13
3100 * @arg @ref LL_RCC_ETH1PTP_DIV_14
3101 * @arg @ref LL_RCC_ETH1PTP_DIV_15
3102 * @arg @ref LL_RCC_ETH1PTP_DIV_16
3103 */
LL_RCC_GetETH1PTPDivider(void)3104 __STATIC_INLINE uint32_t LL_RCC_GetETH1PTPDivider(void)
3105 {
3106 return (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPDIV));
3107 }
3108
3109 /**
3110 * @brief Configure ETHx Reference RX Kernel clock source
3111 * @rmtoll CCIPR2 ETH1REFCLKSEL LL_RCC_SetETHREFRXClockSource
3112 * @param ClkSource This parameter can be one of the following values:
3113 * @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_EXT
3114 * @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_INT
3115 * @retval None
3116 */
LL_RCC_SetETHREFRXClockSource(uint32_t ClkSource)3117 __STATIC_INLINE void LL_RCC_SetETHREFRXClockSource(uint32_t ClkSource)
3118 {
3119 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1REFCLKSEL, ClkSource);
3120 }
3121
3122 /**
3123 * @brief Configure ETHx Reference TX Kernel clock source
3124 * @rmtoll CCIPR2 ETH1GTXCLKSEL LL_RCC_SetETHREFTXClockSource
3125 * @param ClkSource This parameter can be one of the following values:
3126 * @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_EXT
3127 * @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_INT
3128 * @retval None
3129 */
LL_RCC_SetETHREFTXClockSource(uint32_t ClkSource)3130 __STATIC_INLINE void LL_RCC_SetETHREFTXClockSource(uint32_t ClkSource)
3131 {
3132 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1GTXCLKSEL, ClkSource);
3133 }
3134
3135 /**
3136 * @brief Configure FDCANx Kernel clock source
3137 * @rmtoll CCIPR3 FDCANSEL LL_RCC_SetFDCANClockSource
3138 * @param ClkSource This parameter can be one of the following values:
3139 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
3140 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_CLKP
3141 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_IC19
3142 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3143 * @retval None
3144 */
LL_RCC_SetFDCANClockSource(uint32_t ClkSource)3145 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
3146 {
3147 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_FDCANSEL, ClkSource);
3148 }
3149
3150 /**
3151 * @brief Configure FMCx Kernel clock source
3152 * @rmtoll CCIPR3 FMCSEL LL_RCC_SetFMCClockSource
3153 * @param ClkSource This parameter can be one of the following values:
3154 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
3155 * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
3156 * @arg @ref LL_RCC_FMC_CLKSOURCE_IC3
3157 * @arg @ref LL_RCC_FMC_CLKSOURCE_IC4
3158 * @retval None
3159 */
LL_RCC_SetFMCClockSource(uint32_t ClkSource)3160 __STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
3161 {
3162 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_FMCSEL, ClkSource);
3163 }
3164
3165 /**
3166 * @brief Configure I2Cx clock source
3167 * @rmtoll CCIPR4 I2C1SEL LL_RCC_SetI2CClockSource\n
3168 * @rmtoll CCIPR4 I2C2SEL LL_RCC_SetI2CClockSource\n
3169 * @rmtoll CCIPR4 I2C3SEL LL_RCC_SetI2CClockSource\n
3170 * @rmtoll CCIPR4 I2C4SEL LL_RCC_SetI2CClockSource
3171 * @param ClkSource This parameter can be one of the following values:
3172 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
3173 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP
3174 * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10
3175 * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15
3176 * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI
3177 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
3178 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
3179 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP
3180 * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10
3181 * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15
3182 * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI
3183 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
3184 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
3185 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP
3186 * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10
3187 * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15
3188 * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI
3189 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
3190 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
3191 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP
3192 * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10
3193 * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15
3194 * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI
3195 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
3196 * @retval None
3197 */
LL_RCC_SetI2CClockSource(uint32_t ClkSource)3198 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
3199 {
3200 LL_RCC_SetClockSource(ClkSource);
3201 }
3202
3203 /**
3204 * @brief Configure I3Cx clock source
3205 * @rmtoll CCIPR4 I3C1SEL LL_RCC_SetI3CClockSource\n
3206 * @rmtoll CCIPR4 I3C2SEL LL_RCC_SetI3CClockSource
3207 * @param ClkSource This parameter can be one of the following values:
3208 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
3209 * @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP
3210 * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10
3211 * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15
3212 * @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI
3213 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
3214 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1
3215 * @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP
3216 * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10
3217 * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15
3218 * @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI
3219 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI
3220 * @retval None
3221 */
LL_RCC_SetI3CClockSource(uint32_t ClkSource)3222 __STATIC_INLINE void LL_RCC_SetI3CClockSource(uint32_t ClkSource)
3223 {
3224 LL_RCC_SetClockSource(ClkSource);
3225 }
3226
3227 /**
3228 * @brief Configure LPTIMx clock source
3229 * @rmtoll CCIPR12 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n
3230 * CCIPR12 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
3231 * CCIPR12 LPTIM3SEL LL_RCC_SetLPTIMClockSource\n
3232 * CCIPR12 LPTIM4SEL LL_RCC_SetLPTIMClockSource\n
3233 * CCIPR12 LPTIM5SEL LL_RCC_SetLPTIMClockSource
3234 * @param ClkSource This parameter can be one of the following values:
3235 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3236 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3237 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15
3238 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3239 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3240 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG
3241 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
3242 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3243 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15
3244 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3245 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3246 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG
3247 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4
3248 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP
3249 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15
3250 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
3251 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
3252 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG
3253 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4
3254 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP
3255 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15
3256 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE
3257 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI
3258 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG
3259 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4
3260 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP
3261 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15
3262 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE
3263 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI
3264 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG
3265 * @retval None
3266 */
LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)3267 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
3268 {
3269 LL_RCC_SetClockSource(ClkSource);
3270 }
3271
3272 /**
3273 * @brief Configure LPUARTx clock source
3274 * @rmtoll CCIPR14 LPUART1SEL LL_RCC_SetLPUARTClockSource
3275 * @param ClkSource This parameter can be one of the following values:
3276 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
3277 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CLKP
3278 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC9
3279 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC14
3280 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3281 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_MSI
3282 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3283 * @retval None
3284 */
LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)3285 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
3286 {
3287 MODIFY_REG(RCC->CCIPR14, RCC_CCIPR14_LPUART1SEL, ClkSource);
3288 }
3289
3290 /**
3291 * @brief Configure LTDC clock source
3292 * @rmtoll CCIPR4 LTDCSEL LL_RCC_SetLTDCClockSource
3293 * @param ClkSource This parameter can be one of the following values:
3294 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PCLK5
3295 * @arg @ref LL_RCC_LTDC_CLKSOURCE_CLKP
3296 * @arg @ref LL_RCC_LTDC_CLKSOURCE_IC16
3297 * @arg @ref LL_RCC_LTDC_CLKSOURCE_HSI
3298 * @retval None
3299 */
LL_RCC_SetLTDCClockSource(uint32_t ClkSource)3300 __STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t ClkSource)
3301 {
3302 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_LTDCSEL, ClkSource);
3303 }
3304
3305 /**
3306 * @brief Configure MDFx Kernel clock source
3307 * @rmtoll CCIPR5 MDF1SEL LL_RCC_SetMDFClockSource
3308 * @param ClkSource This parameter can be one of the following values:
3309 * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK
3310 * @arg @ref LL_RCC_MDF1_CLKSOURCE_CLKP
3311 * @arg @ref LL_RCC_MDF1_CLKSOURCE_IC7
3312 * @arg @ref LL_RCC_MDF1_CLKSOURCE_IC8
3313 * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSI
3314 * @arg @ref LL_RCC_MDF1_CLKSOURCE_HSI
3315 * @arg @ref LL_RCC_MDF1_CLKSOURCE_I2S_CKIN
3316 * @arg @ref LL_RCC_MDF1_CLKSOURCE_TIMG
3317 * @retval None
3318 */
LL_RCC_SetMDFClockSource(uint32_t ClkSource)3319 __STATIC_INLINE void LL_RCC_SetMDFClockSource(uint32_t ClkSource)
3320 {
3321 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_MDF1SEL, ClkSource);
3322 }
3323
3324 /**
3325 * @brief Configure OTGPHY clock source
3326 * @rmtoll CCIPR6 OTGPHY1SEL LL_RCC_SetOTGPHYClockSource\n
3327 * CCIPR6 OTGPHY2SEL LL_RCC_SetOTGPHYClockSource
3328 * @param ClkSource This parameter can be one of the following values:
3329 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
3330 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
3331 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
3332 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
3333 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
3334 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
3335 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
3336 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
3337 * @retval None
3338 */
LL_RCC_SetOTGPHYClockSource(uint32_t ClkSource)3339 __STATIC_INLINE void LL_RCC_SetOTGPHYClockSource(uint32_t ClkSource)
3340 {
3341 LL_RCC_SetClockSource(ClkSource);
3342 }
3343
3344 /**
3345 * @brief Configure OTGPHYCKREF clock source
3346 * @rmtoll CCIPR6 OTGPHY1CKREFSEL LL_RCC_SetOTGPHYCKREFClockSource\n
3347 * CCIPR6 OTGPHY2CKREFSEL LL_RCC_SetOTGPHYCKREFClockSource
3348 * @param ClkSource This parameter can be one of the following values:
3349 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
3350 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
3351 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
3352 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
3353 * @retval None
3354 */
LL_RCC_SetOTGPHYCKREFClockSource(uint32_t ClkSource)3355 __STATIC_INLINE void LL_RCC_SetOTGPHYCKREFClockSource(uint32_t ClkSource)
3356 {
3357 LL_RCC_SetClockSource(ClkSource);
3358 }
3359
3360 /**
3361 * @brief Configure PSSI clock source
3362 * @rmtoll CCIPR7 PSSISEL LL_RCC_SetPSSIClockSource
3363 * @param ClkSource This parameter can be one of the following values:
3364 * @arg @ref LL_RCC_PSSI_CLKSOURCE_HCLK
3365 * @arg @ref LL_RCC_PSSI_CLKSOURCE_CLKP
3366 * @arg @ref LL_RCC_PSSI_CLKSOURCE_IC20
3367 * @arg @ref LL_RCC_PSSI_CLKSOURCE_HSI
3368 * @retval None
3369 */
LL_RCC_SetPSSIClockSource(uint32_t ClkSource)3370 __STATIC_INLINE void LL_RCC_SetPSSIClockSource(uint32_t ClkSource)
3371 {
3372 MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_PSSISEL, ClkSource);
3373 }
3374
3375 /**
3376 * @brief Configure SAIx clock source
3377 * @rmtoll CCIPR7 SAI1SEL LL_RCC_SetSAIClockSource\n
3378 * CCIPR7 SAI2SEL LL_RCC_SetSAIClockSource
3379 * @param ClkSource This parameter can be one of the following values:
3380 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2
3381 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3382 * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7
3383 * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8
3384 * @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI
3385 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
3386 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3387 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1
3388 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2
3389 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
3390 * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7
3391 * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8
3392 * @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI
3393 * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
3394 * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
3395 * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1
3396 * @retval None
3397 */
LL_RCC_SetSAIClockSource(uint32_t ClkSource)3398 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
3399 {
3400 LL_RCC_SetClockSource(ClkSource);
3401 }
3402
3403 /**
3404 * @brief Configure SDMMCx clock source
3405 * @rmtoll CCIPR8 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n
3406 * CCIPR8 SDMMC2SEL LL_RCC_SetSDMMCClockSource
3407 * @param ClkSource This parameter can be one of the following values:
3408 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK
3409 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP
3410 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4
3411 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5
3412 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK
3413 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP
3414 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4
3415 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5
3416 * @retval None
3417 */
LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)3418 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
3419 {
3420 LL_RCC_SetClockSource(ClkSource);
3421 }
3422
3423 /**
3424 * @brief Configure SPDIFRX1 Kernel clock source
3425 * @rmtoll CCIPR9 SPDIFRX1SEL LL_RCC_SetSPDIFRXClockSource
3426 * @param ClkSource This parameter can be one of the following values:
3427 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1
3428 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_CLKP
3429 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC7
3430 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC8
3431 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_MSI
3432 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_HSI
3433 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN
3434 * @retval None
3435 */
LL_RCC_SetSPDIFRXClockSource(uint32_t ClkSource)3436 __STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t ClkSource)
3437 {
3438 MODIFY_REG(RCC->CCIPR9, RCC_CCIPR9_SPDIFRX1SEL, ClkSource);
3439 }
3440
3441 /**
3442 * @brief Configure SPIx Kernel clock source
3443 * @rmtoll CCIPR9 SPI1SEL LL_RCC_SetSPIClockSource\n
3444 * CCIPR9 SPI2SEL LL_RCC_SetSPIClockSource\n
3445 * CCIPR9 SPI3SEL LL_RCC_SetSPIClockSource\n
3446 * CCIPR9 SPI4SEL LL_RCC_SetSPIClockSource\n
3447 * CCIPR9 SPI5SEL LL_RCC_SetSPIClockSource\n
3448 * CCIPR9 SPI6SEL LL_RCC_SetSPIClockSource
3449 * @param ClkSource This parameter can be one of the following values:
3450 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
3451 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
3452 * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8
3453 * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9
3454 * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI
3455 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
3456 * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
3457 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
3458 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
3459 * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8
3460 * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9
3461 * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI
3462 * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
3463 * @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN
3464 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1
3465 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
3466 * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8
3467 * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9
3468 * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI
3469 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
3470 * @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN
3471 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2
3472 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP
3473 * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9
3474 * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14
3475 * @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI
3476 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI
3477 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE
3478 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2
3479 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP
3480 * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9
3481 * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14
3482 * @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI
3483 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI
3484 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE
3485 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3486 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP
3487 * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8
3488 * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9
3489 * @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI
3490 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3491 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN
3492 * @retval None
3493 */
LL_RCC_SetSPIClockSource(uint32_t ClkSource)3494 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
3495 {
3496 LL_RCC_SetClockSource(ClkSource);
3497 }
3498
3499 /**
3500 * @brief Configure USARTx clock source
3501 * @rmtoll CCIPR13 USART1SEL LL_RCC_SetUSARTClockSource\n
3502 * CCIPR13 USART2SEL LL_RCC_SetUSARTClockSource\n
3503 * CCIPR13 USART3SEL LL_RCC_SetUSARTClockSource\n
3504 * CCIPR13 USART6SEL LL_RCC_SetUSARTClockSource\n
3505 * CCIPR14 USART10SEL LL_RCC_SetUSARTClockSource
3506 * @param ClkSource This parameter can be one of the following values:
3507 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
3508 * @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP
3509 * @arg @ref LL_RCC_USART1_CLKSOURCE_IC9
3510 * @arg @ref LL_RCC_USART1_CLKSOURCE_IC14
3511 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
3512 * @arg @ref LL_RCC_USART1_CLKSOURCE_MSI
3513 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
3514 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
3515 * @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP
3516 * @arg @ref LL_RCC_USART2_CLKSOURCE_IC9
3517 * @arg @ref LL_RCC_USART2_CLKSOURCE_IC14
3518 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
3519 * @arg @ref LL_RCC_USART2_CLKSOURCE_MSI
3520 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
3521 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
3522 * @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP
3523 * @arg @ref LL_RCC_USART3_CLKSOURCE_IC9
3524 * @arg @ref LL_RCC_USART3_CLKSOURCE_IC14
3525 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
3526 * @arg @ref LL_RCC_USART3_CLKSOURCE_MSI
3527 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
3528 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
3529 * @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP
3530 * @arg @ref LL_RCC_USART6_CLKSOURCE_IC9
3531 * @arg @ref LL_RCC_USART6_CLKSOURCE_IC14
3532 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
3533 * @arg @ref LL_RCC_USART6_CLKSOURCE_MSI
3534 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
3535 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2
3536 * @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP
3537 * @arg @ref LL_RCC_USART10_CLKSOURCE_IC9
3538 * @arg @ref LL_RCC_USART10_CLKSOURCE_IC14
3539 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE
3540 * @arg @ref LL_RCC_USART10_CLKSOURCE_MSI
3541 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI
3542 * @retval None
3543 */
LL_RCC_SetUSARTClockSource(uint32_t ClkSource)3544 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
3545 {
3546 LL_RCC_SetClockSource(ClkSource);
3547 }
3548
3549 /**
3550 * @brief Configure UARTx clock source
3551 * @rmtoll CCIPR13 UART4SEL LL_RCC_SetUARTClockSource\n
3552 * CCIPR13 UART5SEL LL_RCC_SetUARTClockSource\n
3553 * CCIPR13 UART7SEL LL_RCC_SetUARTClockSource\n
3554 * CCIPR13 UART8SEL LL_RCC_SetUARTClockSource\n
3555 * CCIPR14 UART9SEL LL_RCC_SetUARTClockSource
3556 * @param ClkSource This parameter can be one of the following values:
3557 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
3558 * @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP
3559 * @arg @ref LL_RCC_UART4_CLKSOURCE_IC9
3560 * @arg @ref LL_RCC_UART4_CLKSOURCE_IC14
3561 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
3562 * @arg @ref LL_RCC_UART4_CLKSOURCE_MSI
3563 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
3564 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
3565 * @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP
3566 * @arg @ref LL_RCC_UART5_CLKSOURCE_IC9
3567 * @arg @ref LL_RCC_UART5_CLKSOURCE_IC14
3568 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
3569 * @arg @ref LL_RCC_UART5_CLKSOURCE_MSI
3570 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
3571 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
3572 * @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP
3573 * @arg @ref LL_RCC_UART7_CLKSOURCE_IC9
3574 * @arg @ref LL_RCC_UART7_CLKSOURCE_IC14
3575 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
3576 * @arg @ref LL_RCC_UART7_CLKSOURCE_MSI
3577 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
3578 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
3579 * @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP
3580 * @arg @ref LL_RCC_UART8_CLKSOURCE_IC9
3581 * @arg @ref LL_RCC_UART8_CLKSOURCE_IC14
3582 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
3583 * @arg @ref LL_RCC_UART8_CLKSOURCE_MSI
3584 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
3585 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2
3586 * @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP
3587 * @arg @ref LL_RCC_UART9_CLKSOURCE_IC9
3588 * @arg @ref LL_RCC_UART9_CLKSOURCE_IC14
3589 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
3590 * @arg @ref LL_RCC_UART9_CLKSOURCE_MSI
3591 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
3592 * @retval None
3593 */
LL_RCC_SetUARTClockSource(uint32_t ClkSource)3594 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t ClkSource)
3595 {
3596 LL_RCC_SetClockSource(ClkSource);
3597 }
3598
3599 /**
3600 * @brief Configure USBx clock source
3601 * @rmtoll CCIPR6 OTGPHY1SEL LL_RCC_GetUSBClockSource\n
3602 * CCIPR6 OTGPHY1CKREFSEL LL_RCC_GetUSBClockSource\n
3603 * CCIPR6 OTGPHY2SEL LL_RCC_GetUSBClockSource\n
3604 * CCIPR6 OTGPHY2CKREFSEL LL_RCC_GetUSBClockSource\n
3605 * @param ClkSource This parameter can be one of the following values:
3606 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
3607 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
3608 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
3609 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
3610 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
3611 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
3612 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
3613 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
3614 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
3615 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
3616 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
3617 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
3618 * @retval None
3619 */
LL_RCC_SetUSBClockSource(uint32_t ClkSource)3620 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
3621 {
3622 LL_RCC_SetClockSource(ClkSource);
3623 }
3624
3625 /**
3626 * @brief Configure XSPIx Kernel clock source
3627 * @rmtoll CCIPR6 XSPI1SEL LL_RCC_SetXSPIClockSource\n
3628 * CCIPR6 XSPI2SEL LL_RCC_SetXSPIClockSource\n
3629 * CCIPR6 XSPI3SEL LL_RCC_SetXSPIClockSource
3630 * @param ClkSource This parameter can be one of the following values:
3631 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
3632 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP
3633 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3
3634 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4
3635 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
3636 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP
3637 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3
3638 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4
3639 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK
3640 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP
3641 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3
3642 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4
3643 * @retval None
3644 */
LL_RCC_SetXSPIClockSource(uint32_t ClkSource)3645 __STATIC_INLINE void LL_RCC_SetXSPIClockSource(uint32_t ClkSource)
3646 {
3647 LL_RCC_SetClockSource(ClkSource);
3648 }
3649
3650 /**
3651 * @brief Get periph clock source
3652 * @rmtoll CCIPR1 * LL_RCC_GetClockSource\n
3653 * CCIPR3 * LL_RCC_GetClockSource\n
3654 * CCIPR4 * LL_RCC_GetClockSource\n
3655 * CCIPR6 * LL_RCC_GetClockSource\n
3656 * CCIPR7 * LL_RCC_GetClockSource\n
3657 * CCIPR8 * LL_RCC_GetClockSource\n
3658 * CCIPR9 * LL_RCC_GetClockSource\n
3659 * CCIPR12 * LL_RCC_GetClockSource\n
3660 * CCIPR13 * LL_RCC_GetClockSource\n
3661 * CCIPR14 * LL_RCC_GetClockSource
3662 * @param Periph This parameter can be one of the following values:
3663 * @arg @ref LL_RCC_I2C1_CLKSOURCE
3664 * @arg @ref LL_RCC_I2C2_CLKSOURCE
3665 * @arg @ref LL_RCC_I2C3_CLKSOURCE
3666 * @arg @ref LL_RCC_I2C4_CLKSOURCE
3667 * @arg @ref LL_RCC_I3C1_CLKSOURCE
3668 * @arg @ref LL_RCC_I3C2_CLKSOURCE
3669 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3670 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3671 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE
3672 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE
3673 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE
3674 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE
3675 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE
3676 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE
3677 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE
3678 * @arg @ref LL_RCC_SAI1_CLKSOURCE
3679 * @arg @ref LL_RCC_SAI2_CLKSOURCE
3680 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
3681 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE
3682 * @arg @ref LL_RCC_SPI1_CLKSOURCE
3683 * @arg @ref LL_RCC_SPI2_CLKSOURCE
3684 * @arg @ref LL_RCC_SPI3_CLKSOURCE
3685 * @arg @ref LL_RCC_SPI4_CLKSOURCE
3686 * @arg @ref LL_RCC_SPI5_CLKSOURCE
3687 * @arg @ref LL_RCC_SPI6_CLKSOURCE
3688 * @arg @ref LL_RCC_UART4_CLKSOURCE
3689 * @arg @ref LL_RCC_UART5_CLKSOURCE
3690 * @arg @ref LL_RCC_UART7_CLKSOURCE
3691 * @arg @ref LL_RCC_UART8_CLKSOURCE
3692 * @arg @ref LL_RCC_UART9_CLKSOURCE
3693 * @arg @ref LL_RCC_USART1_CLKSOURCE
3694 * @arg @ref LL_RCC_USART2_CLKSOURCE
3695 * @arg @ref LL_RCC_USART3_CLKSOURCE
3696 * @arg @ref LL_RCC_USART6_CLKSOURCE
3697 * @arg @ref LL_RCC_USART10_CLKSOURCE
3698 * @arg @ref LL_RCC_XSPI1_CLKSOURCE
3699 * @arg @ref LL_RCC_XSPI2_CLKSOURCE
3700 * @arg @ref LL_RCC_XSPI3_CLKSOURCE
3701 * @retval Returned value can be one of the following values:
3702 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
3703 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP
3704 * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10
3705 * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15
3706 * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI
3707 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
3708 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
3709 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP
3710 * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10
3711 * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15
3712 * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI
3713 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
3714 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
3715 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP
3716 * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10
3717 * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15
3718 * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI
3719 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
3720 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
3721 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP
3722 * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10
3723 * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15
3724 * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI
3725 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
3726 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
3727 * @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP
3728 * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10
3729 * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15
3730 * @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI
3731 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
3732 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1
3733 * @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP
3734 * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10
3735 * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15
3736 * @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI
3737 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI
3738 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3739 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3740 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15
3741 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3742 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3743 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG
3744 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
3745 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3746 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15
3747 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3748 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3749 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG
3750 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4
3751 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP
3752 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15
3753 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
3754 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
3755 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG
3756 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4
3757 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP
3758 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15
3759 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE
3760 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI
3761 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG
3762 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4
3763 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP
3764 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15
3765 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE
3766 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI
3767 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG
3768 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
3769 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
3770 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
3771 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
3772 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
3773 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
3774 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
3775 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
3776 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
3777 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
3778 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
3779 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
3780 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2
3781 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3782 * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7
3783 * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8
3784 * @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI
3785 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
3786 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3787 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1
3788 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2
3789 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
3790 * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7
3791 * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8
3792 * @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI
3793 * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
3794 * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
3795 * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1
3796 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK
3797 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP
3798 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4
3799 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5
3800 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK
3801 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP
3802 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4
3803 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5
3804 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
3805 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
3806 * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8
3807 * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9
3808 * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI
3809 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
3810 * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
3811 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
3812 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
3813 * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8
3814 * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9
3815 * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI
3816 * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
3817 * @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN
3818 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1
3819 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
3820 * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8
3821 * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9
3822 * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI
3823 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
3824 * @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN
3825 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2
3826 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP
3827 * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9
3828 * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14
3829 * @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI
3830 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI
3831 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE
3832 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2
3833 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP
3834 * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9
3835 * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14
3836 * @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI
3837 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI
3838 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE
3839 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3840 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP
3841 * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8
3842 * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9
3843 * @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI
3844 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3845 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN
3846 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
3847 * @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP
3848 * @arg @ref LL_RCC_UART4_CLKSOURCE_IC9
3849 * @arg @ref LL_RCC_UART4_CLKSOURCE_IC14
3850 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
3851 * @arg @ref LL_RCC_UART4_CLKSOURCE_MSI
3852 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
3853 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
3854 * @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP
3855 * @arg @ref LL_RCC_UART5_CLKSOURCE_IC9
3856 * @arg @ref LL_RCC_UART5_CLKSOURCE_IC14
3857 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
3858 * @arg @ref LL_RCC_UART5_CLKSOURCE_MSI
3859 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
3860 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
3861 * @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP
3862 * @arg @ref LL_RCC_UART7_CLKSOURCE_IC9
3863 * @arg @ref LL_RCC_UART7_CLKSOURCE_IC14
3864 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
3865 * @arg @ref LL_RCC_UART7_CLKSOURCE_MSI
3866 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
3867 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
3868 * @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP
3869 * @arg @ref LL_RCC_UART8_CLKSOURCE_IC9
3870 * @arg @ref LL_RCC_UART8_CLKSOURCE_IC14
3871 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
3872 * @arg @ref LL_RCC_UART8_CLKSOURCE_MSI
3873 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
3874 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2
3875 * @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP
3876 * @arg @ref LL_RCC_UART9_CLKSOURCE_IC9
3877 * @arg @ref LL_RCC_UART9_CLKSOURCE_IC14
3878 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
3879 * @arg @ref LL_RCC_UART9_CLKSOURCE_MSI
3880 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
3881 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
3882 * @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP
3883 * @arg @ref LL_RCC_USART1_CLKSOURCE_IC9
3884 * @arg @ref LL_RCC_USART1_CLKSOURCE_IC14
3885 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
3886 * @arg @ref LL_RCC_USART1_CLKSOURCE_MSI
3887 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
3888 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
3889 * @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP
3890 * @arg @ref LL_RCC_USART2_CLKSOURCE_IC9
3891 * @arg @ref LL_RCC_USART2_CLKSOURCE_IC14
3892 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
3893 * @arg @ref LL_RCC_USART2_CLKSOURCE_MSI
3894 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
3895 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
3896 * @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP
3897 * @arg @ref LL_RCC_USART3_CLKSOURCE_IC9
3898 * @arg @ref LL_RCC_USART3_CLKSOURCE_IC14
3899 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
3900 * @arg @ref LL_RCC_USART3_CLKSOURCE_MSI
3901 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
3902 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
3903 * @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP
3904 * @arg @ref LL_RCC_USART6_CLKSOURCE_IC9
3905 * @arg @ref LL_RCC_USART6_CLKSOURCE_IC14
3906 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
3907 * @arg @ref LL_RCC_USART6_CLKSOURCE_MSI
3908 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
3909 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2
3910 * @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP
3911 * @arg @ref LL_RCC_USART10_CLKSOURCE_IC9
3912 * @arg @ref LL_RCC_USART10_CLKSOURCE_IC14
3913 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE
3914 * @arg @ref LL_RCC_USART10_CLKSOURCE_MSI
3915 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI
3916 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
3917 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP
3918 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3
3919 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4
3920 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
3921 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP
3922 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3
3923 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4
3924 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK
3925 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP
3926 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3
3927 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4
3928 * @retval None
3929 */
LL_RCC_GetClockSource(uint32_t Periph)3930 __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
3931 {
3932 const volatile uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CCIPR1) + LL_CLKSOURCE_REG(Periph)));
3933 return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT));
3934 }
3935
3936 /**
3937 * @brief Get ADC Kernel clock source
3938 * @rmtoll CCIPR1 ADC12SEL LL_RCC_GetADCClockSource
3939 * @param Periph This parameter can be one of the following values:
3940 * @arg @ref LL_RCC_ADC_CLKSOURCE
3941 * @retval Returned value can be one of the following values:
3942 * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK
3943 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
3944 * @arg @ref LL_RCC_ADC_CLKSOURCE_IC7
3945 * @arg @ref LL_RCC_ADC_CLKSOURCE_IC8
3946 * @arg @ref LL_RCC_ADC_CLKSOURCE_MSI
3947 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
3948 * @arg @ref LL_RCC_ADC_CLKSOURCE_I2S_CKIN
3949 * @arg @ref LL_RCC_ADC_CLKSOURCE_TIMG
3950 */
LL_RCC_GetADCClockSource(uint32_t Periph)3951 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
3952 {
3953 UNUSED(Periph);
3954 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADC12SEL));
3955 }
3956
3957 /**
3958 * @brief Get ADFx clock source
3959 * @rmtoll CCIPR1 ADF1SEL LL_RCC_GetADFClockSource
3960 * @param Periph This parameter can be one of the following values:
3961 * @arg @ref LL_RCC_ADF1_CLKSOURCE
3962 * @retval Returned value can be one of the following values:
3963 * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK
3964 * @arg @ref LL_RCC_ADF1_CLKSOURCE_CLKP
3965 * @arg @ref LL_RCC_ADF1_CLKSOURCE_IC7
3966 * @arg @ref LL_RCC_ADF1_CLKSOURCE_IC8
3967 * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSI
3968 * @arg @ref LL_RCC_ADF1_CLKSOURCE_HSI
3969 * @arg @ref LL_RCC_ADF1_CLKSOURCE_I2S_CKIN
3970 * @arg @ref LL_RCC_ADF1_CLKSOURCE_TIMG
3971 */
LL_RCC_GetADFClockSource(uint32_t Periph)3972 __STATIC_INLINE uint32_t LL_RCC_GetADFClockSource(uint32_t Periph)
3973 {
3974 UNUSED(Periph);
3975 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL));
3976 }
3977
3978 /**
3979 * @brief Get CLKP Kernel clock source
3980 * @rmtoll CCIPR7 PERSEL LL_RCC_GetCLKPClockSource
3981 * @param Periph This parameter can be one of the following values:
3982 * @arg @ref LL_RCC_CLKP_CLKSOURCE
3983 * @retval Returned value can be one of the following values:
3984 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3985 * @arg @ref LL_RCC_CLKP_CLKSOURCE_MSI
3986 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3987 * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC19
3988 * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC5
3989 * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC10
3990 * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC15
3991 * @arg @ref LL_RCC_CLKP_CLKSOURCE_IC20
3992 */
LL_RCC_GetCLKPClockSource(uint32_t Periph)3993 __STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
3994 {
3995 UNUSED(Periph);
3996 return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_PERSEL));
3997 }
3998
3999 /**
4000 * @brief Get DCMIPP clock source
4001 * @rmtoll CCIPR1 DCMIPPSEL LL_RCC_GetDCMIPPClockSource
4002 * @param Periph This parameter can be one of the following values:
4003 * @arg @ref LL_RCC_DCMIPP_CLKSOURCE
4004 * @retval Returned value can be one of the following values:
4005 * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_PCLK5
4006 * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_CLKP
4007 * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_IC17
4008 * @arg @ref LL_RCC_DCMIPP_CLKSOURCE_HSI
4009 */
LL_RCC_GetDCMIPPClockSource(uint32_t Periph)4010 __STATIC_INLINE uint32_t LL_RCC_GetDCMIPPClockSource(uint32_t Periph)
4011 {
4012 UNUSED(Periph);
4013 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_DCMIPPSEL));
4014 }
4015
4016 /**
4017 * @brief Get ETHx Kernel clock source
4018 * @rmtoll CCIPR2 ETH1CLKSEL LL_RCC_GetETHClockSource
4019 * @param Periph This parameter can be one of the following values:
4020 * @arg @ref LL_RCC_ETH1_CLKSOURCE
4021 * @retval Returned value can be one of the following values:
4022 * @arg @ref LL_RCC_ETH1_CLKSOURCE_HCLK
4023 * @arg @ref LL_RCC_ETH1_CLKSOURCE_CLKP
4024 * @arg @ref LL_RCC_ETH1_CLKSOURCE_IC12
4025 * @arg @ref LL_RCC_ETH1_CLKSOURCE_HSE
4026 */
LL_RCC_GetETHClockSource(uint32_t Periph)4027 __STATIC_INLINE uint32_t LL_RCC_GetETHClockSource(uint32_t Periph)
4028 {
4029 UNUSED(Periph);
4030 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1CLKSEL));
4031 }
4032
4033 /**
4034 * @brief Get ETHx PTP Kernel clock source
4035 * @rmtoll CCIPR2 ETH1PTPSEL LL_RCC_GetETHPTPClockSource
4036 * @param Periph This parameter can be one of the following values:
4037 * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE
4038 * @retval Returned value can be one of the following values:
4039 * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HCLK
4040 * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_CLKP
4041 * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_IC13
4042 * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HSE
4043 */
LL_RCC_GetETHPTPClockSource(uint32_t Periph)4044 __STATIC_INLINE uint32_t LL_RCC_GetETHPTPClockSource(uint32_t Periph)
4045 {
4046 UNUSED(Periph);
4047 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPSEL));
4048 }
4049
4050 /**
4051 * @brief Get ETHx PHY interface
4052 * @rmtoll CCIPR2 ETH1SEL LL_RCC_GetETHPHYInterface
4053 * @param Periph This parameter can be one of the following values:
4054 * @arg @ref LL_RCC_ETH1PHY_IF
4055 * @retval Returned value can be one of the following values:
4056 * @arg @ref LL_RCC_ETH1PHY_IF_MII
4057 * @arg @ref LL_RCC_ETH1PHY_IF_RGMII
4058 * @arg @ref LL_RCC_ETH1PHY_IF_RMII
4059 */
LL_RCC_GetETHPHYInterface(uint32_t Periph)4060 __STATIC_INLINE uint32_t LL_RCC_GetETHPHYInterface(uint32_t Periph)
4061 {
4062 UNUSED(Periph);
4063 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1SEL));
4064 }
4065
4066 /**
4067 * @brief Get ETHx Reference RX Kernel clock source
4068 * @rmtoll CCIPR2 ETH1REFCLKSEL LL_RCC_GetETHREFRXClockSource
4069 * @param Periph This parameter can be one of the following values:
4070 * @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE
4071 * @retval Returned value can be one of the following values:
4072 * @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_EXT
4073 * @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_INT
4074 */
LL_RCC_GetETHREFRXClockSource(uint32_t Periph)4075 __STATIC_INLINE uint32_t LL_RCC_GetETHREFRXClockSource(uint32_t Periph)
4076 {
4077 UNUSED(Periph);
4078 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1REFCLKSEL));
4079 }
4080
4081 /**
4082 * @brief Get ETHx Reference TX Kernel clock source
4083 * @rmtoll CCIPR2 ETH1GTXCLKSEL LL_RCC_GetETHREFTXClockSource
4084 * @param Periph This parameter can be one of the following values:
4085 * @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE
4086 * @retval Returned value can be one of the following values:
4087 * @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_EXT
4088 * @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_INT
4089 */
LL_RCC_GetETHREFTXClockSource(uint32_t Periph)4090 __STATIC_INLINE uint32_t LL_RCC_GetETHREFTXClockSource(uint32_t Periph)
4091 {
4092 UNUSED(Periph);
4093 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1GTXCLKSEL));
4094 }
4095
4096 /**
4097 * @brief Get FDCAN Kernel clock source
4098 * @rmtoll CCIPR3 FDCANSEL LL_RCC_GetFDCANClockSource
4099 * @param Periph This parameter can be one of the following values:
4100 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
4101 * @retval Returned value can be one of the following values:
4102 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
4103 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_CLKP
4104 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_IC19
4105 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
4106 */
LL_RCC_GetFDCANClockSource(uint32_t Periph)4107 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
4108 {
4109 UNUSED(Periph);
4110 return (uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_FDCANSEL));
4111 }
4112
4113 /**
4114 * @brief Get FMC Kernel clock source
4115 * @rmtoll CCIPR3 FMCSEL LL_RCC_GetFMCClockSource
4116 * @param Periph This parameter can be one of the following values:
4117 * @arg @ref LL_RCC_FMC_CLKSOURCE
4118 * @retval Returned value can be one of the following values:
4119 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
4120 * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
4121 * @arg @ref LL_RCC_FMC_CLKSOURCE_IC3
4122 * @arg @ref LL_RCC_FMC_CLKSOURCE_IC4
4123 */
LL_RCC_GetFMCClockSource(uint32_t Periph)4124 __STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
4125 {
4126 UNUSED(Periph);
4127 return (uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_FMCSEL));
4128 }
4129
4130 /**
4131 * @brief Get I2Cx clock source
4132 * @rmtoll CCIPR4 I2C1SEL LL_RCC_GetI2CClockSource\n
4133 * @rmtoll CCIPR4 I2C2SEL LL_RCC_GetI2CClockSource\n
4134 * @rmtoll CCIPR4 I2C3SEL LL_RCC_GetI2CClockSource\n
4135 * @rmtoll CCIPR4 I2C4SEL LL_RCC_GetI2CClockSource
4136 * @param Periph This parameter can be one of the following values:
4137 * @arg @ref LL_RCC_I2C1_CLKSOURCE
4138 * @arg @ref LL_RCC_I2C2_CLKSOURCE
4139 * @arg @ref LL_RCC_I2C3_CLKSOURCE
4140 * @arg @ref LL_RCC_I2C4_CLKSOURCE
4141 * @retval Returned value can be one of the following values:
4142 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
4143 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP
4144 * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10
4145 * @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15
4146 * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI
4147 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
4148 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
4149 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP
4150 * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10
4151 * @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15
4152 * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI
4153 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
4154 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
4155 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP
4156 * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10
4157 * @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15
4158 * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI
4159 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
4160 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
4161 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP
4162 * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10
4163 * @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15
4164 * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI
4165 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
4166 */
LL_RCC_GetI2CClockSource(uint32_t Periph)4167 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
4168 {
4169 return LL_RCC_GetClockSource(Periph);
4170 }
4171
4172 /**
4173 * @brief Get I3Cx clock source
4174 * @rmtoll CCIPR4 I3C1SEL LL_RCC_GetI3CClockSource\n
4175 * @rmtoll CCIPR4 I3C2SEL LL_RCC_GetI3CClockSource
4176 * @param Periph This parameter can be one of the following values:
4177 * @arg @ref LL_RCC_I3C1_CLKSOURCE
4178 * @arg @ref LL_RCC_I3C2_CLKSOURCE
4179 * @retval Returned value can be one of the following values:
4180 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
4181 * @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP
4182 * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10
4183 * @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15
4184 * @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI
4185 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
4186 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1
4187 * @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP
4188 * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10
4189 * @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15
4190 * @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI
4191 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI
4192 */
LL_RCC_GetI3CClockSource(uint32_t Periph)4193 __STATIC_INLINE uint32_t LL_RCC_GetI3CClockSource(uint32_t Periph)
4194 {
4195 UNUSED(Periph);
4196 return LL_RCC_GetClockSource(Periph);
4197 }
4198
4199 /**
4200 * @brief Get LPTIM clock source
4201 * @rmtoll CCIPR12 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
4202 * CCIPR12 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
4203 * CCIPR12 LPTIM3SEL LL_RCC_GetLPTIMClockSource\n
4204 * CCIPR12 LPTIM4SEL LL_RCC_GetLPTIMClockSource\n
4205 * CCIPR12 LPTIM5SEL LL_RCC_GetLPTIMClockSource
4206 * @param Periph This parameter can be one of the following values:
4207 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
4208 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
4209 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE
4210 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE
4211 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE
4212 * @retval Returned value can be one of the following values:
4213 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
4214 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
4215 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15
4216 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
4217 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
4218 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG
4219 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
4220 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
4221 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15
4222 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
4223 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
4224 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG
4225 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4
4226 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP
4227 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15
4228 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
4229 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
4230 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG
4231 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4
4232 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP
4233 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15
4234 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE
4235 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI
4236 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG
4237 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4
4238 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP
4239 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15
4240 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE
4241 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI
4242 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG
4243 * @retval None
4244 */
LL_RCC_GetLPTIMClockSource(uint32_t Periph)4245 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
4246 {
4247 return LL_RCC_GetClockSource(Periph);
4248 }
4249
4250 /**
4251 * @brief Get LPUART clock source
4252 * @rmtoll CCIPR14 LPUART1SEL LL_RCC_GetLPUARTClockSource
4253 * @param Periph This parameter can be one of the following values:
4254 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
4255 * @retval Returned value can be one of the following values:
4256 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
4257 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CLKP
4258 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC9
4259 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC14
4260 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
4261 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_MSI
4262 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
4263 */
LL_RCC_GetLPUARTClockSource(uint32_t Periph)4264 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
4265 {
4266 UNUSED(Periph);
4267 return (uint32_t)(READ_BIT(RCC->CCIPR14, RCC_CCIPR14_LPUART1SEL));
4268 }
4269
4270 /**
4271 * @brief Get LTDC clock source
4272 * @rmtoll CCIPR4 LTDCSEL LL_RCC_GetLTDCClockSource
4273 * @param Periph This parameter can be one of the following values:
4274 * @arg @ref LL_RCC_LTDC_CLKSOURCE
4275 * @retval Returned value can be one of the following values:
4276 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PCLK5
4277 * @arg @ref LL_RCC_LTDC_CLKSOURCE_CLKP
4278 * @arg @ref LL_RCC_LTDC_CLKSOURCE_IC16
4279 * @arg @ref LL_RCC_LTDC_CLKSOURCE_HSI
4280 */
LL_RCC_GetLTDCClockSource(uint32_t Periph)4281 __STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t Periph)
4282 {
4283 UNUSED(Periph);
4284 return (uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_LTDCSEL));
4285 }
4286
4287 /**
4288 * @brief Get MDFx clock source
4289 * @rmtoll CCIPR5 MDF1SEL LL_RCC_GetMDFClockSource
4290 * @param Periph This parameter can be one of the following values:
4291 * @arg @ref LL_RCC_MDF1_CLKSOURCE
4292 * @retval Returned value can be one of the following values:
4293 * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK
4294 * @arg @ref LL_RCC_MDF1_CLKSOURCE_CLKP
4295 * @arg @ref LL_RCC_MDF1_CLKSOURCE_IC7
4296 * @arg @ref LL_RCC_MDF1_CLKSOURCE_IC8
4297 * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSI
4298 * @arg @ref LL_RCC_MDF1_CLKSOURCE_HSI
4299 * @arg @ref LL_RCC_MDF1_CLKSOURCE_I2S_CKIN
4300 * @arg @ref LL_RCC_MDF1_CLKSOURCE_TIMG
4301 */
LL_RCC_GetMDFClockSource(uint32_t Periph)4302 __STATIC_INLINE uint32_t LL_RCC_GetMDFClockSource(uint32_t Periph)
4303 {
4304 UNUSED(Periph);
4305 return (uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_MDF1SEL));
4306 }
4307
4308 /**
4309 * @brief Get OTGPHY clock source
4310 * @rmtoll CCIPR6 OTGPHY1SEL LL_RCC_GetOTGPHYClockSource\n
4311 * CCIPR6 OTGPHY2SEL LL_RCC_GetOTGPHYClockSource
4312 * @param Periph This parameter can be one of the following values:
4313 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE
4314 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE
4315 * @retval Returned value can be one of the following values:
4316 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
4317 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
4318 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
4319 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
4320 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
4321 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
4322 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
4323 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
4324 */
LL_RCC_GetOTGPHYClockSource(uint32_t Periph)4325 __STATIC_INLINE uint32_t LL_RCC_GetOTGPHYClockSource(uint32_t Periph)
4326 {
4327 return LL_RCC_GetClockSource(Periph);
4328 }
4329
4330 /**
4331 * @brief Get OTGPHYCKREF clock source
4332 * @rmtoll CCIPR6 OTGPHY1CKREFSEL LL_RCC_GetOTGPHYCKREFClockSource\n
4333 * CCIPR6 OTGPHY2CKREFSEL LL_RCC_GetOTGPHYCKREFClockSource
4334 * @param Periph This parameter can be one of the following values:
4335 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE
4336 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE
4337 * @retval Returned value can be one of the following values:
4338 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
4339 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
4340 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
4341 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
4342 */
LL_RCC_GetOTGPHYCKREFClockSource(uint32_t Periph)4343 __STATIC_INLINE uint32_t LL_RCC_GetOTGPHYCKREFClockSource(uint32_t Periph)
4344 {
4345 return LL_RCC_GetClockSource(Periph);
4346 }
4347
4348 /**
4349 * @brief Get PSSI clock source
4350 * @rmtoll CCIPR7 PSSISEL LL_RCC_GetPSSIClockSource
4351 * @param Periph This parameter can be one of the following values:
4352 * @arg @ref LL_RCC_PSSI_CLKSOURCE
4353 * @retval Returned value can be one of the following values:
4354 * @arg @ref LL_RCC_PSSI_CLKSOURCE_HCLK
4355 * @arg @ref LL_RCC_PSSI_CLKSOURCE_CLKP
4356 * @arg @ref LL_RCC_PSSI_CLKSOURCE_IC20
4357 * @arg @ref LL_RCC_PSSI_CLKSOURCE_HSI
4358 */
LL_RCC_GetPSSIClockSource(uint32_t Periph)4359 __STATIC_INLINE uint32_t LL_RCC_GetPSSIClockSource(uint32_t Periph)
4360 {
4361 UNUSED(Periph);
4362 return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_PSSISEL));
4363 }
4364
4365 /**
4366 * @brief Get SAIx clock source
4367 * @rmtoll CCIPR7 SAI1SEL LL_RCC_GetSAIClockSource\n
4368 * CCIPR7 SAI2SEL LL_RCC_GetSAIClockSource
4369 * @param Periph This parameter can be one of the following values:
4370 * @arg @ref LL_RCC_SAI1_CLKSOURCE
4371 * @arg @ref LL_RCC_SAI2_CLKSOURCE
4372 * @retval Returned value can be one of the following values:
4373 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2
4374 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
4375 * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7
4376 * @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8
4377 * @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI
4378 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
4379 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
4380 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1
4381 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2
4382 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
4383 * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7
4384 * @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8
4385 * @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI
4386 * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
4387 * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
4388 * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1
4389 */
LL_RCC_GetSAIClockSource(uint32_t Periph)4390 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
4391 {
4392 return LL_RCC_GetClockSource(Periph);
4393 }
4394
4395 /**
4396 * @brief Get SDMMC clock source
4397 * @rmtoll CCIPR8 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n
4398 * CCIPR8 SDMMC2SEL LL_RCC_GetSDMMCClockSource
4399 * @param Periph This parameter can be one of the following values:
4400 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
4401 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE
4402 * @retval Returned value can be one of the following values:
4403 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK
4404 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP
4405 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4
4406 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5
4407 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK
4408 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP
4409 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4
4410 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5
4411 */
LL_RCC_GetSDMMCClockSource(uint32_t Periph)4412 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
4413 {
4414 return LL_RCC_GetClockSource(Periph);
4415 }
4416
4417 /**
4418 * @brief Get SPDIFRX Kernel clock source
4419 * @rmtoll CCIPR9 SPDIFRX1SEL LL_RCC_GetSPDIFRXClockSource
4420 * @param Periph This parameter can be one of the following values:
4421 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
4422 * @retval Returned value can be one of the following values:
4423 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1
4424 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_CLKP
4425 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC7
4426 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC8
4427 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_MSI
4428 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_HSI
4429 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN
4430 */
LL_RCC_GetSPDIFRXClockSource(uint32_t Periph)4431 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t Periph)
4432 {
4433 UNUSED(Periph);
4434 return (uint32_t)(READ_BIT(RCC->CCIPR9, RCC_CCIPR9_SPDIFRX1SEL));
4435 }
4436
4437 /**
4438 * @brief Get SPIx Kernel clock source
4439 * @rmtoll CCIPR9 SPI1SEL LL_RCC_GetSPIClockSource\n
4440 * CCIPR9 SPI2SEL LL_RCC_GetSPIClockSource\n
4441 * CCIPR9 SPI3SEL LL_RCC_GetSPIClockSource\n
4442 * CCIPR9 SPI4SEL LL_RCC_GetSPIClockSource\n
4443 * CCIPR9 SPI5SEL LL_RCC_GetSPIClockSource\n
4444 * CCIPR9 SPI6SEL LL_RCC_GetSPIClockSource
4445 * @param Periph This parameter can be one of the following values:
4446 * @arg @ref LL_RCC_SPI1_CLKSOURCE
4447 * @arg @ref LL_RCC_SPI2_CLKSOURCE
4448 * @arg @ref LL_RCC_SPI3_CLKSOURCE
4449 * @arg @ref LL_RCC_SPI4_CLKSOURCE
4450 * @arg @ref LL_RCC_SPI5_CLKSOURCE
4451 * @arg @ref LL_RCC_SPI6_CLKSOURCE
4452 * @retval Returned value can be one of the following values:
4453 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
4454 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
4455 * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8
4456 * @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9
4457 * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI
4458 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
4459 * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
4460 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
4461 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
4462 * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8
4463 * @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9
4464 * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI
4465 * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
4466 * @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN
4467 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1
4468 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
4469 * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8
4470 * @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9
4471 * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI
4472 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
4473 * @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN
4474 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2
4475 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP
4476 * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9
4477 * @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14
4478 * @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI
4479 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI
4480 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE
4481 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2
4482 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP
4483 * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9
4484 * @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14
4485 * @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI
4486 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI
4487 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE
4488 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
4489 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP
4490 * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8
4491 * @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9
4492 * @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI
4493 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
4494 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN
4495 */
LL_RCC_GetSPIClockSource(uint32_t Periph)4496 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
4497 {
4498 return LL_RCC_GetClockSource(Periph);
4499 }
4500
4501 /**
4502 * @brief Get USARTx clock source
4503 * @rmtoll CCIPR13 USART1SEL LL_RCC_GetUSARTClockSource\n
4504 * CCIPR13 USART2SEL LL_RCC_GetUSARTClockSource\n
4505 * CCIPR13 USART3SEL LL_RCC_GetUSARTClockSource\n
4506 * CCIPR13 USART6SEL LL_RCC_GetUSARTClockSource\n
4507 * CCIPR14 USART10SEL LL_RCC_GetUSARTClockSource
4508 * @param Periph This parameter can be one of the following values:
4509 * @arg @ref LL_RCC_USART1_CLKSOURCE
4510 * @arg @ref LL_RCC_USART2_CLKSOURCE
4511 * @arg @ref LL_RCC_USART3_CLKSOURCE
4512 * @arg @ref LL_RCC_USART6_CLKSOURCE
4513 * @arg @ref LL_RCC_USART10_CLKSOURCE
4514 * @retval Returned value can be one of the following values:
4515 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
4516 * @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP
4517 * @arg @ref LL_RCC_USART1_CLKSOURCE_IC9
4518 * @arg @ref LL_RCC_USART1_CLKSOURCE_IC14
4519 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
4520 * @arg @ref LL_RCC_USART1_CLKSOURCE_MSI
4521 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
4522 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
4523 * @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP
4524 * @arg @ref LL_RCC_USART2_CLKSOURCE_IC9
4525 * @arg @ref LL_RCC_USART2_CLKSOURCE_IC14
4526 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
4527 * @arg @ref LL_RCC_USART2_CLKSOURCE_MSI
4528 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
4529 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
4530 * @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP
4531 * @arg @ref LL_RCC_USART3_CLKSOURCE_IC9
4532 * @arg @ref LL_RCC_USART3_CLKSOURCE_IC14
4533 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
4534 * @arg @ref LL_RCC_USART3_CLKSOURCE_MSI
4535 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
4536 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
4537 * @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP
4538 * @arg @ref LL_RCC_USART6_CLKSOURCE_IC9
4539 * @arg @ref LL_RCC_USART6_CLKSOURCE_IC14
4540 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
4541 * @arg @ref LL_RCC_USART6_CLKSOURCE_MSI
4542 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
4543 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2
4544 * @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP
4545 * @arg @ref LL_RCC_USART10_CLKSOURCE_IC9
4546 * @arg @ref LL_RCC_USART10_CLKSOURCE_IC14
4547 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE
4548 * @arg @ref LL_RCC_USART10_CLKSOURCE_MSI
4549 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI
4550 */
LL_RCC_GetUSARTClockSource(uint32_t Periph)4551 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
4552 {
4553 return LL_RCC_GetClockSource(Periph);
4554 }
4555
4556 /**
4557 * @brief Get USARTx clock source
4558 * @rmtoll CCIPR13 UART4SEL LL_RCC_GetUARTClockSource\n
4559 * CCIPR13 UART5SEL LL_RCC_GetUARTClockSource\n
4560 * CCIPR13 UART7SEL LL_RCC_GetUARTClockSource\n
4561 * CCIPR13 UART8SEL LL_RCC_GetUARTClockSource\n
4562 * CCIPR14 UART9SEL LL_RCC_GetUARTClockSource
4563 * @param Periph This parameter can be one of the following values:
4564 * @arg @ref LL_RCC_UART4_CLKSOURCE
4565 * @arg @ref LL_RCC_UART5_CLKSOURCE
4566 * @arg @ref LL_RCC_UART7_CLKSOURCE
4567 * @arg @ref LL_RCC_UART8_CLKSOURCE
4568 * @arg @ref LL_RCC_UART9_CLKSOURCE
4569 * @retval Returned value can be one of the following values:
4570 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
4571 * @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP
4572 * @arg @ref LL_RCC_UART4_CLKSOURCE_IC9
4573 * @arg @ref LL_RCC_UART4_CLKSOURCE_IC14
4574 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
4575 * @arg @ref LL_RCC_UART4_CLKSOURCE_MSI
4576 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
4577 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
4578 * @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP
4579 * @arg @ref LL_RCC_UART5_CLKSOURCE_IC9
4580 * @arg @ref LL_RCC_UART5_CLKSOURCE_IC14
4581 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
4582 * @arg @ref LL_RCC_UART5_CLKSOURCE_MSI
4583 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
4584 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
4585 * @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP
4586 * @arg @ref LL_RCC_UART7_CLKSOURCE_IC9
4587 * @arg @ref LL_RCC_UART7_CLKSOURCE_IC14
4588 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
4589 * @arg @ref LL_RCC_UART7_CLKSOURCE_MSI
4590 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
4591 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
4592 * @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP
4593 * @arg @ref LL_RCC_UART8_CLKSOURCE_IC9
4594 * @arg @ref LL_RCC_UART8_CLKSOURCE_IC14
4595 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
4596 * @arg @ref LL_RCC_UART8_CLKSOURCE_MSI
4597 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
4598 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2
4599 * @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP
4600 * @arg @ref LL_RCC_UART9_CLKSOURCE_IC9
4601 * @arg @ref LL_RCC_UART9_CLKSOURCE_IC14
4602 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
4603 * @arg @ref LL_RCC_UART9_CLKSOURCE_MSI
4604 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
4605 * @retval None
4606 */
LL_RCC_GetUARTClockSource(uint32_t Periph)4607 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t Periph)
4608 {
4609 return LL_RCC_GetClockSource(Periph);
4610 }
4611
4612 /**
4613 * @brief Get USB clock source
4614 * @rmtoll CCIPR6 OTGPHY1SEL LL_RCC_GetUSBClockSource\n
4615 * CCIPR6 OTGPHY1CKREFSEL LL_RCC_GetUSBClockSource\n
4616 * CCIPR6 OTGPHY2SEL LL_RCC_GetUSBClockSource\n
4617 * CCIPR6 OTGPHY2CKREFSEL LL_RCC_GetUSBClockSource\n
4618 * @param Periph This parameter can be one of the following values:
4619 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE
4620 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE
4621 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE
4622 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE
4623 * @retval Returned value can be one of the following values:
4624 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
4625 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
4626 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
4627 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
4628 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
4629 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
4630 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
4631 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
4632 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
4633 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
4634 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
4635 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
4636 */
LL_RCC_GetUSBClockSource(uint32_t Periph)4637 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
4638 {
4639 return LL_RCC_GetClockSource(Periph);
4640 }
4641
4642
4643 /**
4644 * @brief Get XSPI Kernel clock source
4645 * @rmtoll CCIPR6 XSPI1SEL LL_RCC_GetXSPIClockSource\n
4646 * CCIPR6 XSPI2SEL LL_RCC_GetXSPIClockSource\n
4647 * CCIPR6 XSPI3SEL LL_RCC_GetXSPIClockSource
4648 * @param Periph This parameter can be one of the following values:
4649 * @arg @ref LL_RCC_XSPI1_CLKSOURCE
4650 * @arg @ref LL_RCC_XSPI2_CLKSOURCE
4651 * @arg @ref LL_RCC_XSPI3_CLKSOURCE
4652 * @retval Returned value can be one of the following values:
4653 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
4654 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP
4655 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3
4656 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4
4657 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
4658 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP
4659 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3
4660 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4
4661 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK
4662 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP
4663 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3
4664 * @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4
4665 */
LL_RCC_GetXSPIClockSource(uint32_t Periph)4666 __STATIC_INLINE uint32_t LL_RCC_GetXSPIClockSource(uint32_t Periph)
4667 {
4668 return LL_RCC_GetClockSource(Periph);
4669 }
4670
4671
4672 /**
4673 * @}
4674 */
4675
4676 /** @defgroup RCC_LL_EF_RTC RTC
4677 * @{
4678 */
4679
4680 /**
4681 * @brief Set RTC Clock Source
4682 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
4683 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
4684 * set).
4685 * @rmtoll CCIPR7 RTCSEL LL_RCC_SetRTCClockSource
4686 * @param Source This parameter can be one of the following values:
4687 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
4688 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
4689 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
4690 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
4691 * @retval None
4692 */
LL_RCC_SetRTCClockSource(uint32_t Source)4693 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
4694 {
4695 MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_RTCSEL, Source);
4696 }
4697
4698 /**
4699 * @brief Get RTC Clock Source
4700 * @rmtoll CCIPR7 RTCSEL LL_RCC_GetRTCClockSource
4701 * @retval Returned value can be one of the following values:
4702 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
4703 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
4704 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
4705 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
4706 */
LL_RCC_GetRTCClockSource(void)4707 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
4708 {
4709 return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCSEL));
4710 }
4711
4712 /**
4713 * @brief Enable RTC
4714 * @rmtoll APB4ENSR1 RTCENS LL_RCC_EnableRTC
4715 * @retval None
4716 */
LL_RCC_EnableRTC(void)4717 __STATIC_INLINE void LL_RCC_EnableRTC(void)
4718 {
4719 WRITE_REG(RCC->APB4ENSR1, RCC_APB4ENSR1_RTCENS);
4720 }
4721
4722 /**
4723 * @brief Disable RTC
4724 * @rmtoll APB4ENCR1 RTCENC LL_RCC_DisableRTC
4725 * @retval None
4726 */
LL_RCC_DisableRTC(void)4727 __STATIC_INLINE void LL_RCC_DisableRTC(void)
4728 {
4729 WRITE_REG(RCC->APB4ENCR1, RCC_APB4ENCR1_RTCENC);
4730 }
4731
4732 /**
4733 * @brief Check if RTC has been enabled or not
4734 * @rmtoll APB4ENR1 RTCEN LL_RCC_IsEnabledRTC
4735 * @retval State of bit (1 or 0).
4736 */
LL_RCC_IsEnabledRTC(void)4737 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
4738 {
4739 return ((READ_BIT(RCC->APB4ENR1, RCC_APB4ENR1_RTCEN) == (RCC_APB4ENR1_RTCEN)) ? 1UL : 0UL);
4740 }
4741
4742 /**
4743 * @brief Force the Backup domain reset
4744 * @rmtoll BDCR VSWRST LL_RCC_ForceBackupDomainReset
4745 * @retval None
4746 */
LL_RCC_ForceBackupDomainReset(void)4747 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
4748 {
4749 SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
4750 }
4751
4752 /**
4753 * @brief Release the Backup domain reset
4754 * @rmtoll BDCR VSWRST LL_RCC_ReleaseBackupDomainReset
4755 * @retval None
4756 */
LL_RCC_ReleaseBackupDomainReset(void)4757 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
4758 {
4759 CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
4760 }
4761
4762 /**
4763 * @brief Set HSE Prescaler for RTC Clock
4764 * @rmtoll CCIPR7 RTCPRE LL_RCC_SetRTC_HSEPrescaler
4765 * @param Prescaler This parameter can be one of the following values:
4766 * @arg @ref LL_RCC_RTC_HSE_DIV_1
4767 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4768 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4769 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4770 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4771 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4772 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4773 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4774 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4775 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4776 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4777 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4778 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4779 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4780 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4781 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4782 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4783 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4784 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4785 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4786 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4787 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4788 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4789 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4790 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4791 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4792 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4793 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4794 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4795 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4796 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4797 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4798 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4799 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4800 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4801 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4802 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4803 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4804 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4805 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4806 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4807 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4808 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4809 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4810 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4811 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4812 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4813 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4814 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4815 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4816 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4817 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4818 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4819 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4820 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4821 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4822 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4823 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4824 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4825 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4826 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4827 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4828 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4829 * @retval None
4830 */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)4831 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4832 {
4833 MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_RTCPRE, Prescaler);
4834 }
4835
4836 /**
4837 * @brief Get HSE Prescaler for RTC Clock
4838 * @rmtoll CCIPR7 RTCPRE LL_RCC_GetRTC_HSEPrescaler
4839 * @retval Returned value can be one of the following values:
4840 * @arg @ref LL_RCC_RTC_HSE_DIV_1
4841 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4842 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4843 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4844 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4845 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4846 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4847 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4848 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4849 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4850 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4851 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4852 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4853 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4854 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4855 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4856 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4857 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4858 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4859 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4860 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4861 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4862 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4863 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4864 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4865 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4866 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4867 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4868 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4869 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4870 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4871 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4872 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4873 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4874 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4875 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4876 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4877 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4878 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4879 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4880 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4881 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4882 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4883 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4884 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4885 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4886 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4887 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4888 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4889 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4890 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4891 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4892 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4893 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4894 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4895 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4896 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4897 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4898 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4899 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4900 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4901 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4902 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4903 */
LL_RCC_GetRTC_HSEPrescaler(void)4904 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4905 {
4906 return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCPRE));
4907 }
4908
4909 /**
4910 * @}
4911 */
4912
4913 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4914 * @{
4915 */
4916
4917 /**
4918 * @brief Set Timers Clock Prescalers
4919 * @rmtoll CFGR2 TIMPRE LL_RCC_SetTIMPrescaler
4920 * @param Prescaler This parameter can be one of the following values:
4921 * @arg @ref LL_RCC_TIM_PRESCALER_1
4922 * @arg @ref LL_RCC_TIM_PRESCALER_2
4923 * @arg @ref LL_RCC_TIM_PRESCALER_4
4924 * @arg @ref LL_RCC_TIM_PRESCALER_8
4925 * @retval None
4926 */
LL_RCC_SetTIMPrescaler(uint32_t Prescaler)4927 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4928 {
4929 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_TIMPRE, Prescaler << RCC_CFGR2_TIMPRE_Pos);
4930 }
4931
4932 /**
4933 * @brief Get Timers Clock Prescalers
4934 * @rmtoll CFGR2 TIMPRE LL_RCC_GetTIMPrescaler
4935 * @retval Returned value can be one of the following values:
4936 * @arg @ref LL_RCC_TIM_PRESCALER_1
4937 * @arg @ref LL_RCC_TIM_PRESCALER_2
4938 * @arg @ref LL_RCC_TIM_PRESCALER_4
4939 * @arg @ref LL_RCC_TIM_PRESCALER_8
4940 */
LL_RCC_GetTIMPrescaler(void)4941 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4942 {
4943 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_TIMPRE) >> RCC_CFGR2_TIMPRE_Pos);
4944 }
4945
4946 /**
4947 * @}
4948 */
4949
4950 /** @defgroup RCC_LL_EF_PLL PLL
4951 * @{
4952 */
4953
4954 /**
4955 * @brief Set the oscillator used as PLL clock source.
4956 * @note PLL1SEL can be written only when All PLLs are disabled.
4957 * @rmtoll PLL1CFGR1 PLL1SEL LL_RCC_PLL1_SetSource
4958 * @param PLLSource parameter can be one of the following values:
4959 * @arg @ref LL_RCC_PLLSOURCE_HSI
4960 * @arg @ref LL_RCC_PLLSOURCE_MSI
4961 * @arg @ref LL_RCC_PLLSOURCE_HSE
4962 * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
4963 * @retval None
4964 */
LL_RCC_PLL1_SetSource(uint32_t PLLSource)4965 __STATIC_INLINE void LL_RCC_PLL1_SetSource(uint32_t PLLSource)
4966 {
4967 MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1SEL, PLLSource);
4968 }
4969
4970 /**
4971 * @brief Get the oscillator used as PLL clock source.
4972 * @rmtoll PLL1CFGR1 PLL1SEL LL_RCC_PLL1_GetSource
4973 * @retval Returned value can be one of the following values:
4974 * @arg @ref LL_RCC_PLLSOURCE_HSI
4975 * @arg @ref LL_RCC_PLLSOURCE_MSI
4976 * @arg @ref LL_RCC_PLLSOURCE_HSE
4977 * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
4978 */
LL_RCC_PLL1_GetSource(void)4979 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetSource(void)
4980 {
4981 return (uint32_t)(READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1SEL));
4982 }
4983
4984 /**
4985 * @brief Enable PLL1
4986 * @rmtoll CSR PLL1ONS LL_RCC_PLL1_Enable
4987 * @retval None
4988 */
LL_RCC_PLL1_Enable(void)4989 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
4990 {
4991 WRITE_REG(RCC->CSR, RCC_CSR_PLL1ONS);
4992 }
4993
4994 /**
4995 * @brief Disable PLL1
4996 * @note Cannot be disabled if the PLL1 clock is used as the system clock
4997 * @rmtoll CCR PLL1ONC LL_RCC_PLL1_Disable
4998 * @retval None
4999 */
LL_RCC_PLL1_Disable(void)5000 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
5001 {
5002 WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC);
5003 }
5004
5005 /**
5006 * @brief Check if PLL1 Ready
5007 * @rmtoll SR PLL1RDY LL_RCC_PLL1_IsReady
5008 * @retval State of bit (1 or 0).
5009 */
LL_RCC_PLL1_IsReady(void)5010 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
5011 {
5012 return ((READ_BIT(RCC->SR, RCC_SR_PLL1RDY) == (RCC_SR_PLL1RDY)) ? 1UL : 0UL);
5013 }
5014
5015 /**
5016 * @brief Enable PLL1 bypass (PLL1 output is driven by the PLL1 reference clock)
5017 * @note This API shall be called only when PLL1 is disabled.
5018 * @rmtoll PLL1CFGR1 PLL1BYP LL_RCC_PLL1_EnableBypass
5019 * @retval None
5020 */
LL_RCC_PLL1_EnableBypass(void)5021 __STATIC_INLINE void LL_RCC_PLL1_EnableBypass(void)
5022 {
5023 SET_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1BYP);
5024 }
5025
5026 /**
5027 * @brief Disable PLL1 bypass (PLL1 output is driven by the VCO)
5028 * @note This API shall be called only when PLL1 is disabled.
5029 * @rmtoll PLL1CFGR1 PLL1BYP LL_RCC_PLL1_DisableBypass
5030 * @retval None
5031 */
LL_RCC_PLL1_DisableBypass(void)5032 __STATIC_INLINE void LL_RCC_PLL1_DisableBypass(void)
5033 {
5034 CLEAR_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1BYP);
5035 }
5036
5037 /**
5038 * @brief Check if PLL1 bypass is enabled
5039 * @rmtoll PLL1CFGR1 PLL1BYP LL_RCC_PLL1_IsEnabledBypass
5040 * @retval State of bit (1 or 0).
5041 */
LL_RCC_PLL1_IsEnabledBypass(void)5042 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledBypass(void)
5043 {
5044 return ((READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1BYP) == RCC_PLL1CFGR1_PLL1BYP) ? 1UL : 0UL);
5045 }
5046
5047 /**
5048 * @brief Assert PLL1 modulation spread-spectrum reset
5049 * @note This API shall be called only when PLL1 is disabled.
5050 * @rmtoll PLL1CFGR3 PLL1MODSSRST LL_RCC_PLL1_AssertModulationSpreadSpectrumReset
5051 * @retval None
5052 */
LL_RCC_PLL1_AssertModulationSpreadSpectrumReset(void)5053 __STATIC_INLINE void LL_RCC_PLL1_AssertModulationSpreadSpectrumReset(void)
5054 {
5055 SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSRST);
5056 }
5057
5058 /**
5059 * @brief Release PLL1 modulation spread-spectrum reset
5060 * @note This API shall be called only when PLL1 is disabled.
5061 * @rmtoll PLL1CFGR3 PLL1MODSSRST LL_RCC_PLL1_ReleaseModulationSpreadSpectrumReset
5062 * @retval None
5063 */
LL_RCC_PLL1_ReleaseModulationSpreadSpectrumReset(void)5064 __STATIC_INLINE void LL_RCC_PLL1_ReleaseModulationSpreadSpectrumReset(void)
5065 {
5066 CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSRST);
5067 }
5068
5069 /**
5070 * @brief Enable PLL1 noise canceling DAC in fractional mode
5071 * @note This API shall be called only when PLL1 is disabled.
5072 * @rmtoll PLL1CFGR3 PLL1DACEN LL_RCC_PLL1_EnableDAC
5073 * @retval None
5074 */
LL_RCC_PLL1_EnableDAC(void)5075 __STATIC_INLINE void LL_RCC_PLL1_EnableDAC(void)
5076 {
5077 SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN);
5078 }
5079
5080 /**
5081 * @brief Disable PLL1 noise canceling DAC in fractional mode
5082 * @note This API shall be called only when PLL1 is disabled.
5083 * @rmtoll PLL1CFGR3 PLL1DACEN LL_RCC_PLL1_DisableDAC
5084 * @retval None
5085 */
LL_RCC_PLL1_DisableDAC(void)5086 __STATIC_INLINE void LL_RCC_PLL1_DisableDAC(void)
5087 {
5088 CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN);
5089 }
5090
5091 /**
5092 * @brief Check if PLL1 noise canceling DAC in fractional mode is enabled
5093 * @rmtoll PLL1CFGR3 PLL1DACEN LL_RCC_PLL1_IsEnabledDAC
5094 * @retval State of bit (1 or 0).
5095 */
LL_RCC_PLL1_IsEnabledDAC(void)5096 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDAC(void)
5097 {
5098 return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN) == RCC_PLL1CFGR3_PLL1DACEN) ? 1UL : 0UL);
5099 }
5100
5101 /**
5102 * @brief Enable PLL1 modulation spread-spectrum with fractional divide inactive
5103 * @note This API shall be called only when PLL1 is disabled.
5104 * @rmtoll PLL1CFGR3 PLL1MODSSDIS LL_RCC_PLL1_EnableModulationSpreadSpectrum
5105 * @retval None
5106 */
LL_RCC_PLL1_EnableModulationSpreadSpectrum(void)5107 __STATIC_INLINE void LL_RCC_PLL1_EnableModulationSpreadSpectrum(void)
5108 {
5109 CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS);
5110 }
5111
5112 /**
5113 * @brief Disable PLL1 modulation spread-spectrum but active fractional divide
5114 * @note This API shall be called only when PLL1 is disabled.
5115 * @rmtoll PLL1CFGR3 PLL1MODSSDIS LL_RCC_PLL1_DisableModulationSpreadSpectrum
5116 * @retval None
5117 */
LL_RCC_PLL1_DisableModulationSpreadSpectrum(void)5118 __STATIC_INLINE void LL_RCC_PLL1_DisableModulationSpreadSpectrum(void)
5119 {
5120 SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS);
5121 }
5122
5123 /**
5124 * @brief Check if PLL1 modulation spread-spectrum and inactive fractional divide is enabled
5125 * @rmtoll PLL1CFGR3 PLL1MODSSDIS LL_RCC_PLL1_IsEnabledModulationSpreadSpectrum
5126 * @retval State of bit (1 or 0).
5127 */
LL_RCC_PLL1_IsEnabledModulationSpreadSpectrum(void)5128 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledModulationSpreadSpectrum(void)
5129 {
5130 return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS) == 0UL) ? 1UL : 0UL);
5131 }
5132
5133 /**
5134 * @brief Enable PLL1 fractional divide and modulation spread-spectrum
5135 * @note This API shall be called only when PLL1 is disabled.
5136 * @rmtoll PLL1CFGR3 PLL1MODDSEN LL_RCC_PLL1_EnableFractionalModulationSpreadSpectrum
5137 * @retval None
5138 */
LL_RCC_PLL1_EnableFractionalModulationSpreadSpectrum(void)5139 __STATIC_INLINE void LL_RCC_PLL1_EnableFractionalModulationSpreadSpectrum(void)
5140 {
5141 SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODDSEN);
5142 }
5143
5144 /**
5145 * @brief Disable PLL1 fractional divide and modulation spread-spectrum
5146 * @note This API shall be called only when PLL1 is disabled.
5147 * @rmtoll PLL1CFGR3 PLL1MODDSEN LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum
5148 * @retval None
5149 */
LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum(void)5150 __STATIC_INLINE void LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum(void)
5151 {
5152 CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODDSEN);
5153 }
5154
5155 /**
5156 * @brief Check if PLL1 fractional divide and modulation spread-spectrum is enabled
5157 * @rmtoll PLL1CFGR3 PLL1MODDSEN LL_RCC_PLL1_IsEnabledFractionalModulationSpreadSpectrum
5158 * @retval State of bit (1 or 0).
5159 */
LL_RCC_PLL1_IsEnabledFractionalModulationSpreadSpectrum(void)5160 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledFractionalModulationSpreadSpectrum(void)
5161 {
5162 return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODDSEN) == RCC_PLL1CFGR3_PLL1MODDSEN) ? 1UL : 0UL);
5163 }
5164
5165 /**
5166 * @brief Set PLL1 DIVN Coefficient
5167 * @note This API shall be called only when PLL1 is disabled.
5168 * @rmtoll PLL1CFGR1 PLL1DIVN LL_RCC_PLL1_SetN
5169 * @param N In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4).
5170 * In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4).
5171 */
LL_RCC_PLL1_SetN(uint32_t N)5172 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
5173 {
5174 MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVN, N << RCC_PLL1CFGR1_PLL1DIVN_Pos);
5175 }
5176
5177 /**
5178 * @brief Get PLL1 DIVN Coefficient
5179 * @rmtoll PLL1CFGR1 PLL1DIVN LL_RCC_PLL1_GetN
5180 * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4).
5181 * In fractional mode, a value between 20 (0x14) and 500 (0x1F4).
5182 */
LL_RCC_PLL1_GetN(void)5183 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
5184 {
5185 return (uint32_t)((READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos));
5186 }
5187
5188 /**
5189 * @brief Set PLL1 DIVM Coefficient
5190 * @note This API shall be called only when PLL1 is disabled.
5191 * @rmtoll PLL1CFGR1 PLL1DIVM LL_RCC_PLL1_SetM
5192 * @param M parameter can be a value between 1 and 63
5193 */
LL_RCC_PLL1_SetM(uint32_t M)5194 __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
5195 {
5196 MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVM, M << RCC_PLL1CFGR1_PLL1DIVM_Pos);
5197 }
5198
5199 /**
5200 * @brief Get PLL1 DIVM Coefficient
5201 * @rmtoll PLL1CFGR1 PLL1DIVM LL_RCC_PLL1_GetM
5202 * @retval A value between 1 and 63
5203 */
LL_RCC_PLL1_GetM(void)5204 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
5205 {
5206 return (uint32_t)(READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos);
5207 }
5208
5209 /**
5210 * @brief Set PLL1 PDIV1 Coefficient
5211 * @note This API shall be called only when PLL1 is disabled.
5212 * @rmtoll PLL1CFGR3 PLL1PDIV1 LL_RCC_PLL1_SetP1
5213 * @param P1 parameter can be a value between 1 and 7 when PLL1 is enabled, 0 when disabled
5214 */
LL_RCC_PLL1_SetP1(uint32_t P1)5215 __STATIC_INLINE void LL_RCC_PLL1_SetP1(uint32_t P1)
5216 {
5217 MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV1, P1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos);
5218 }
5219
5220 /**
5221 * @brief Get PLL1 PDIV2 Coefficient
5222 * @rmtoll PLL1CFGR3 PLL1PDIV1 LL_RCC_PLL1_GetP1
5223 * @retval A value between 0 and 7
5224 */
LL_RCC_PLL1_GetP1(void)5225 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP1(void)
5226 {
5227 return (uint32_t)(READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV1) >> RCC_PLL1CFGR3_PLL1PDIV1_Pos);
5228 }
5229
5230 /**
5231 * @brief Set PLL1 PDIV2 Coefficient
5232 * @note This API shall be called only when PLL1 is disabled.
5233 * @rmtoll PLL1CFGR3 PLL1PDIV2 LL_RCC_PLL1_SetP2
5234 * @param P2 parameter can be a value between 1 and 7
5235 */
LL_RCC_PLL1_SetP2(uint32_t P2)5236 __STATIC_INLINE void LL_RCC_PLL1_SetP2(uint32_t P2)
5237 {
5238 MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV2, P2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos);
5239 }
5240
5241 /**
5242 * @brief Get PLL1 PDIV2 Coefficient
5243 * @rmtoll PLL1CFGR3 PLL1PDIV2 LL_RCC_PLL1_GetP2
5244 * @retval A value between 1 and 7
5245 */
LL_RCC_PLL1_GetP2(void)5246 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP2(void)
5247 {
5248 return (uint32_t)(READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos);
5249 }
5250
5251 /**
5252 * @brief Enable PLL1P
5253 * @note This API shall be called only when PLL1 is disabled.
5254 * @rmtoll PLL1CFGR3 PLL1PDIVEN LL_RCC_PLL1P_Enable
5255 * @retval None
5256 */
LL_RCC_PLL1P_Enable(void)5257 __STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
5258 {
5259 SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN);
5260 }
5261
5262 /**
5263 * @brief Disable PLL1P
5264 * @note This API shall be called only when PLL1 is disabled.
5265 * @rmtoll PLL1CFGR3 PLL1PDIVEN LL_RCC_PLL1P_Disable
5266 * @retval None
5267 */
LL_RCC_PLL1P_Disable(void)5268 __STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
5269 {
5270 CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN);
5271 }
5272
5273 /**
5274 * @brief Check if PLL1 P is enabled
5275 * @rmtoll PLL1CFGR3 PLL1PDIVEN LL_RCC_PLL1P_IsEnabled
5276 * @retval State of bit (1 or 0).
5277 */
LL_RCC_PLL1P_IsEnabled(void)5278 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
5279 {
5280 return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN) == RCC_PLL1CFGR3_PLL1PDIVEN) ? 1UL : 0UL);
5281 }
5282
5283 /**
5284 * @brief Set PLL1 FRACN Coefficient
5285 * @note This API shall be called only when PLL1 is disabled.
5286 * @rmtoll PLL1CFGR2 PLL1DIVNFRAC LL_RCC_PLL1_SetFRACN
5287 * @param FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF)
5288 */
LL_RCC_PLL1_SetFRACN(uint32_t FRACN)5289 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
5290 {
5291 MODIFY_REG(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC, FRACN << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos);
5292 }
5293
5294 /**
5295 * @brief Get PLL1 FRACN Coefficient
5296 * @rmtoll PLL1CFGR2 PLL1DIVNFRAC LL_RCC_PLL1_GetFRACN
5297 * @retval A value between 0 and 2^24 (0xFFFFFF)
5298 */
LL_RCC_PLL1_GetFRACN(void)5299 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
5300 {
5301 return (uint32_t)(READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC) >> RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos);
5302 }
5303
5304 /**
5305 * @brief Set the oscillator used as PLL clock source.
5306 * @note PLL2SEL can be written only when All PLLs are disabled.
5307 * @rmtoll PLL2CFGR1 PLL2SEL LL_RCC_PLL2_SetSource
5308 * @param PLLSource parameter can be one of the following values:
5309 * @arg @ref LL_RCC_PLLSOURCE_HSI
5310 * @arg @ref LL_RCC_PLLSOURCE_MSI
5311 * @arg @ref LL_RCC_PLLSOURCE_HSE
5312 * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
5313 * @retval None
5314 */
LL_RCC_PLL2_SetSource(uint32_t PLLSource)5315 __STATIC_INLINE void LL_RCC_PLL2_SetSource(uint32_t PLLSource)
5316 {
5317 MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2SEL, PLLSource);
5318 }
5319
5320 /**
5321 * @brief Get the oscillator used as PLL clock source.
5322 * @rmtoll PLL2CFGR1 PLL2SEL LL_RCC_PLL2_GetSource
5323 * @retval Returned value can be one of the following values:
5324 * @arg @ref LL_RCC_PLLSOURCE_HSI
5325 * @arg @ref LL_RCC_PLLSOURCE_MSI
5326 * @arg @ref LL_RCC_PLLSOURCE_HSE
5327 * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
5328 */
LL_RCC_PLL2_GetSource(void)5329 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetSource(void)
5330 {
5331 return (uint32_t)(READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2SEL));
5332 }
5333
5334 /**
5335 * @brief Enable PLL2
5336 * @rmtoll CSR PLL2ONS LL_RCC_PLL2_Enable
5337 * @retval None
5338 */
LL_RCC_PLL2_Enable(void)5339 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
5340 {
5341 WRITE_REG(RCC->CSR, RCC_CSR_PLL2ONS);
5342 }
5343
5344 /**
5345 * @brief Disable PLL2
5346 * @note Cannot be disabled if the PLL2 clock is used as the system clock
5347 * @rmtoll CCR PLL2ONC LL_RCC_PLL2_Disable
5348 * @retval None
5349 */
LL_RCC_PLL2_Disable(void)5350 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
5351 {
5352 WRITE_REG(RCC->CCR, RCC_CCR_PLL2ONC);
5353 }
5354
5355 /**
5356 * @brief Check if PLL2 Ready
5357 * @rmtoll SR PLL2RDY LL_RCC_PLL2_IsReady
5358 * @retval State of bit (1 or 0).
5359 */
LL_RCC_PLL2_IsReady(void)5360 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
5361 {
5362 return ((READ_BIT(RCC->SR, RCC_SR_PLL2RDY) == (RCC_SR_PLL2RDY)) ? 1UL : 0UL);
5363 }
5364
5365 /**
5366 * @brief Enable PLL2 bypass (PLL2 output is driven by the PLL2 reference clock)
5367 * @note This API shall be called only when PLL2 is disabled.
5368 * @rmtoll PLL2CFGR1 PLL2BYP LL_RCC_PLL2_EnableBypass
5369 * @retval None
5370 */
LL_RCC_PLL2_EnableBypass(void)5371 __STATIC_INLINE void LL_RCC_PLL2_EnableBypass(void)
5372 {
5373 SET_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP);
5374 }
5375
5376 /**
5377 * @brief Disable PLL2 bypass (PLL2 output is driven by the VCO)
5378 * @note This API shall be called only when PLL2 is disabled.
5379 * @rmtoll PLL2CFGR1 PLL2BYP LL_RCC_PLL2_DisableBypass
5380 * @retval None
5381 */
LL_RCC_PLL2_DisableBypass(void)5382 __STATIC_INLINE void LL_RCC_PLL2_DisableBypass(void)
5383 {
5384 CLEAR_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP);
5385 }
5386
5387 /**
5388 * @brief Check if PLL2 bypass is enabled
5389 * @rmtoll PLL2CFGR1 PLL2BYP LL_RCC_PLL2_IsEnabledBypass
5390 * @retval State of bit (1 or 0).
5391 */
LL_RCC_PLL2_IsEnabledBypass(void)5392 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledBypass(void)
5393 {
5394 return ((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP) == RCC_PLL2CFGR1_PLL2BYP) ? 1UL : 0UL);
5395 }
5396
5397 /**
5398 * @brief Assert PLL2 modulation spread-spectrum reset
5399 * @note This API shall be called only when PLL2 is disabled.
5400 * @rmtoll PLL2CFGR3 PLL2MODSSRST LL_RCC_PLL2_AssertModulationSpreadSpectrumReset
5401 * @retval None
5402 */
LL_RCC_PLL2_AssertModulationSpreadSpectrumReset(void)5403 __STATIC_INLINE void LL_RCC_PLL2_AssertModulationSpreadSpectrumReset(void)
5404 {
5405 SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSRST);
5406 }
5407
5408 /**
5409 * @brief Release PLL2 modulation spread-spectrum reset
5410 * @note This API shall be called only when PLL2 is disabled.
5411 * @rmtoll PLL2CFGR3 PLL2MODSSRST LL_RCC_PLL2_ReleaseModulationSpreadSpectrumReset
5412 * @retval None
5413 */
LL_RCC_PLL2_ReleaseModulationSpreadSpectrumReset(void)5414 __STATIC_INLINE void LL_RCC_PLL2_ReleaseModulationSpreadSpectrumReset(void)
5415 {
5416 CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSRST);
5417 }
5418
5419 /**
5420 * @brief Enable PLL2 noise canceling DAC in fractional mode
5421 * @note This API shall be called only when PLL2 is disabled.
5422 * @rmtoll PLL2CFGR3 PLL2DACEN LL_RCC_PLL2_EnableDAC
5423 * @retval None
5424 */
LL_RCC_PLL2_EnableDAC(void)5425 __STATIC_INLINE void LL_RCC_PLL2_EnableDAC(void)
5426 {
5427 SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN);
5428 }
5429
5430 /**
5431 * @brief Disable PLL2 noise canceling DAC in fractional mode
5432 * @note This API shall be called only when PLL2 is disabled.
5433 * @rmtoll PLL2CFGR3 PLL2DACEN LL_RCC_PLL2_DisableDAC
5434 * @retval None
5435 */
LL_RCC_PLL2_DisableDAC(void)5436 __STATIC_INLINE void LL_RCC_PLL2_DisableDAC(void)
5437 {
5438 CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN);
5439 }
5440
5441 /**
5442 * @brief Check if PLL2 noise canceling DAC in fractional mode is enabled
5443 * @rmtoll PLL2CFGR3 PLL2DACEN LL_RCC_PLL2_IsEnabledDAC
5444 * @retval State of bit (1 or 0).
5445 */
LL_RCC_PLL2_IsEnabledDAC(void)5446 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDAC(void)
5447 {
5448 return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN) == RCC_PLL2CFGR3_PLL2DACEN) ? 1UL : 0UL);
5449 }
5450
5451 /**
5452 * @brief Enable PLL2 modulation spread-spectrum with fractional divide inactive
5453 * @note This API shall be called only when PLL2 is disabled.
5454 * @rmtoll PLL2CFGR3 PLL2MODSSDIS LL_RCC_PLL2_EnableModulationSpreadSpectrum
5455 * @retval None
5456 */
LL_RCC_PLL2_EnableModulationSpreadSpectrum(void)5457 __STATIC_INLINE void LL_RCC_PLL2_EnableModulationSpreadSpectrum(void)
5458 {
5459 CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS);
5460 }
5461
5462 /**
5463 * @brief Disable PLL2 modulation spread-spectrum but active fractional divide
5464 * @note This API shall be called only when PLL2 is disabled.
5465 * @rmtoll PLL2CFGR3 PLL2MODSSDIS LL_RCC_PLL2_DisableModulationSpreadSpectrum
5466 * @retval None
5467 */
LL_RCC_PLL2_DisableModulationSpreadSpectrum(void)5468 __STATIC_INLINE void LL_RCC_PLL2_DisableModulationSpreadSpectrum(void)
5469 {
5470 SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS);
5471 }
5472
5473 /**
5474 * @brief Check if PLL2 modulation spread-spectrum and inactive fractional divide is enabled
5475 * @rmtoll PLL2CFGR3 PLL2MODSSDIS LL_RCC_PLL2_IsEnabledModulationSpreadSpectrum
5476 * @retval State of bit (1 or 0).
5477 */
LL_RCC_PLL2_IsEnabledModulationSpreadSpectrum(void)5478 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledModulationSpreadSpectrum(void)
5479 {
5480 return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS) == 0UL) ? 1UL : 0UL);
5481 }
5482
5483 /**
5484 * @brief Enable PLL2 fractional divide and modulation spread-spectrum
5485 * @note This API shall be called only when PLL2 is disabled.
5486 * @rmtoll PLL2CFGR3 PLL2MODDSEN LL_RCC_PLL2_EnableFractionalModulationSpreadSpectrum
5487 * @retval None
5488 */
LL_RCC_PLL2_EnableFractionalModulationSpreadSpectrum(void)5489 __STATIC_INLINE void LL_RCC_PLL2_EnableFractionalModulationSpreadSpectrum(void)
5490 {
5491 SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODDSEN);
5492 }
5493
5494 /**
5495 * @brief Disable PLL2 fractional divide and modulation spread-spectrum
5496 * @note This API shall be called only when PLL2 is disabled.
5497 * @rmtoll PLL2CFGR3 PLL2MODDSEN LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum
5498 * @retval None
5499 */
LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum(void)5500 __STATIC_INLINE void LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum(void)
5501 {
5502 CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODDSEN);
5503 }
5504
5505 /**
5506 * @brief Check if PLL2 fractional divide and modulation spread-spectrum is enabled
5507 * @rmtoll PLL2CFGR3 PLL2MODDSEN LL_RCC_PLL2_IsEnabledFractionalModulationSpreadSpectrum
5508 * @retval State of bit (1 or 0).
5509 */
LL_RCC_PLL2_IsEnabledFractionalModulationSpreadSpectrum(void)5510 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledFractionalModulationSpreadSpectrum(void)
5511 {
5512 return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODDSEN) == RCC_PLL2CFGR3_PLL2MODDSEN) ? 1UL : 0UL);
5513 }
5514
5515 /**
5516 * @brief Set PLL2 DIVN Coefficient
5517 * @note This API shall be called only when PLL2 is disabled.
5518 * @rmtoll PLL2CFGR1 PLL2DIVN LL_RCC_PLL2_SetN
5519 * @param N In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4).
5520 * In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4).
5521 */
LL_RCC_PLL2_SetN(uint32_t N)5522 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
5523 {
5524 MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVN, N << RCC_PLL2CFGR1_PLL2DIVN_Pos);
5525 }
5526
5527 /**
5528 * @brief Get PLL2 DIVN Coefficient
5529 * @rmtoll PLL2CFGR1 PLL2DIVN LL_RCC_PLL2_GetN
5530 * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4).
5531 * In fractional mode, a value between 20 (0x14) and 500 (0x1F4).
5532 */
LL_RCC_PLL2_GetN(void)5533 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
5534 {
5535 return (uint32_t)((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVN) >> RCC_PLL2CFGR1_PLL2DIVN_Pos));
5536 }
5537
5538 /**
5539 * @brief Set PLL2 DIVM Coefficient
5540 * @note This API shall be called only when PLL2 is disabled.
5541 * @rmtoll PLL2CFGR1 PLL2DIVM LL_RCC_PLL2_SetM
5542 * @param M parameter can be a value between 1 and 63
5543 */
LL_RCC_PLL2_SetM(uint32_t M)5544 __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
5545 {
5546 MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVM, M << RCC_PLL2CFGR1_PLL2DIVM_Pos);
5547 }
5548
5549 /**
5550 * @brief Get PLL2 DIVM Coefficient
5551 * @rmtoll PLL2CFGR1 PLL2DIVM LL_RCC_PLL2_GetM
5552 * @retval A value between 1 and 63
5553 */
LL_RCC_PLL2_GetM(void)5554 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
5555 {
5556 return (uint32_t)(READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVM) >> RCC_PLL2CFGR1_PLL2DIVM_Pos);
5557 }
5558
5559 /**
5560 * @brief Set PLL2 PDIV1 Coefficient
5561 * @note This API shall be called only when PLL2 is disabled.
5562 * @rmtoll PLL2CFGR3 PLL2PDIV1 LL_RCC_PLL2_SetP1
5563 * @param P1 parameter can be a value between 1 and 7 when PLL2 is enabled, 0 when disabled
5564 */
LL_RCC_PLL2_SetP1(uint32_t P1)5565 __STATIC_INLINE void LL_RCC_PLL2_SetP1(uint32_t P1)
5566 {
5567 MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV1, P1 << RCC_PLL2CFGR3_PLL2PDIV1_Pos);
5568 }
5569
5570 /**
5571 * @brief Get PLL2 PDIV2 Coefficient
5572 * @rmtoll PLL2CFGR3 PLL2PDIV1 LL_RCC_PLL2_GetP1
5573 * @retval A value between 0 and 7
5574 */
LL_RCC_PLL2_GetP1(void)5575 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP1(void)
5576 {
5577 return (uint32_t)(READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos);
5578 }
5579
5580 /**
5581 * @brief Set PLL2 PDIV2 Coefficient
5582 * @note This API shall be called only when PLL2 is disabled.
5583 * @rmtoll PLL2CFGR3 PLL2PDIV2 LL_RCC_PLL2_SetP2
5584 * @param P2 parameter can be a value between 1 and 7
5585 */
LL_RCC_PLL2_SetP2(uint32_t P2)5586 __STATIC_INLINE void LL_RCC_PLL2_SetP2(uint32_t P2)
5587 {
5588 MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV2, P2 << RCC_PLL2CFGR3_PLL2PDIV2_Pos);
5589 }
5590
5591 /**
5592 * @brief Get PLL2 PDIV2 Coefficient
5593 * @rmtoll PLL2CFGR3 PLL2PDIV2 LL_RCC_PLL2_GetP2
5594 * @retval A value between 1 and 7
5595 */
LL_RCC_PLL2_GetP2(void)5596 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP2(void)
5597 {
5598 return (uint32_t)(READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV2) >> RCC_PLL2CFGR3_PLL2PDIV2_Pos);
5599 }
5600
5601 /**
5602 * @brief Enable PLL2P
5603 * @note This API shall be called only when PLL2 is disabled.
5604 * @rmtoll PLL2CFGR3 PLL2PDIVEN LL_RCC_PLL2P_Enable
5605 * @retval None
5606 */
LL_RCC_PLL2P_Enable(void)5607 __STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
5608 {
5609 SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIVEN);
5610 }
5611
5612 /**
5613 * @brief Disable PLL2P
5614 * @note This API shall be called only when PLL2 is disabled.
5615 * @rmtoll PLL2CFGR3 PLL2PDIVEN LL_RCC_PLL2P_Disable
5616 * @retval None
5617 */
LL_RCC_PLL2P_Disable(void)5618 __STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
5619 {
5620 CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIVEN);
5621 }
5622
5623 /**
5624 * @brief Check if PLL2 P is enabled
5625 * @rmtoll PLL2CFGR3 PLL2PDIVEN LL_RCC_PLL2P_IsEnabled
5626 * @retval State of bit (1 or 0).
5627 */
LL_RCC_PLL2P_IsEnabled(void)5628 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
5629 {
5630 return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIVEN) == RCC_PLL2CFGR3_PLL2PDIVEN) ? 1UL : 0UL);
5631 }
5632
5633 /**
5634 * @brief Set PLL2 FRACN Coefficient
5635 * @note This API shall be called only when PLL2 is disabled.
5636 * @rmtoll PLL2CFGR2 PLL2DIVNFRAC LL_RCC_PLL2_SetFRACN
5637 * @param FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF)
5638 */
LL_RCC_PLL2_SetFRACN(uint32_t FRACN)5639 __STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
5640 {
5641 MODIFY_REG(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC, FRACN << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos);
5642 }
5643
5644 /**
5645 * @brief Get PLL2 FRACN Coefficient
5646 * @rmtoll PLL2CFGR2 PLL2DIVNFRAC LL_RCC_PLL2_GetFRACN
5647 * @retval A value between 0 and 2^24 (0xFFFFFF)
5648 */
LL_RCC_PLL2_GetFRACN(void)5649 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
5650 {
5651 return (uint32_t)(READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC) >> RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos);
5652 }
5653
5654 /**
5655 * @brief Set the oscillator used as PLL clock source.
5656 * @note PLL3SEL can be written only when All PLLs are disabled.
5657 * @rmtoll PLL3CFGR1 PLL3SEL LL_RCC_PLL3_SetSource
5658 * @param PLLSource parameter can be one of the following values:
5659 * @arg @ref LL_RCC_PLLSOURCE_HSI
5660 * @arg @ref LL_RCC_PLLSOURCE_MSI
5661 * @arg @ref LL_RCC_PLLSOURCE_HSE
5662 * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
5663 * @retval None
5664 */
LL_RCC_PLL3_SetSource(uint32_t PLLSource)5665 __STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource)
5666 {
5667 MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3SEL, PLLSource);
5668 }
5669
5670 /**
5671 * @brief Get the oscillator used as PLL clock source.
5672 * @rmtoll PLL3CFGR1 PLL3SEL LL_RCC_PLL3_GetSource
5673 * @retval Returned value can be one of the following values:
5674 * @arg @ref LL_RCC_PLLSOURCE_HSI
5675 * @arg @ref LL_RCC_PLLSOURCE_MSI
5676 * @arg @ref LL_RCC_PLLSOURCE_HSE
5677 * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
5678 */
LL_RCC_PLL3_GetSource(void)5679 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void)
5680 {
5681 return (uint32_t)(READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3SEL));
5682 }
5683
5684 /**
5685 * @brief Enable PLL3
5686 * @rmtoll CSR PLL3ONS LL_RCC_PLL3_Enable
5687 * @retval None
5688 */
LL_RCC_PLL3_Enable(void)5689 __STATIC_INLINE void LL_RCC_PLL3_Enable(void)
5690 {
5691 WRITE_REG(RCC->CSR, RCC_CSR_PLL3ONS);
5692 }
5693
5694 /**
5695 * @brief Disable PLL3
5696 * @note Cannot be disabled if the PLL3 clock is used as the system clock
5697 * @rmtoll CCR PLL3ONC LL_RCC_PLL3_Disable
5698 * @retval None
5699 */
LL_RCC_PLL3_Disable(void)5700 __STATIC_INLINE void LL_RCC_PLL3_Disable(void)
5701 {
5702 WRITE_REG(RCC->CCR, RCC_CCR_PLL3ONC);
5703 }
5704
5705 /**
5706 * @brief Check if PLL3 Ready
5707 * @rmtoll SR PLL3RDY LL_RCC_PLL3_IsReady
5708 * @retval State of bit (1 or 0).
5709 */
LL_RCC_PLL3_IsReady(void)5710 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
5711 {
5712 return ((READ_BIT(RCC->SR, RCC_SR_PLL3RDY) == (RCC_SR_PLL3RDY)) ? 1UL : 0UL);
5713 }
5714
5715 /**
5716 * @brief Enable PLL3 bypass (PLL3 output is driven by the PLL3 reference clock)
5717 * @note This API shall be called only when PLL3 is disabled.
5718 * @rmtoll PLL3CFGR1 PLL3BYP LL_RCC_PLL3_EnableBypass
5719 * @retval None
5720 */
LL_RCC_PLL3_EnableBypass(void)5721 __STATIC_INLINE void LL_RCC_PLL3_EnableBypass(void)
5722 {
5723 SET_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3BYP);
5724 }
5725
5726 /**
5727 * @brief Disable PLL3 bypass (PLL3 output is driven by the VCO)
5728 * @note This API shall be called only when PLL3 is disabled.
5729 * @rmtoll PLL3CFGR1 PLL3BYP LL_RCC_PLL3_DisableBypass
5730 * @retval None
5731 */
LL_RCC_PLL3_DisableBypass(void)5732 __STATIC_INLINE void LL_RCC_PLL3_DisableBypass(void)
5733 {
5734 CLEAR_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3BYP);
5735 }
5736
5737 /**
5738 * @brief Check if PLL3 bypass is enabled
5739 * @rmtoll PLL3CFGR1 PLL3BYP LL_RCC_PLL3_IsEnabledBypass
5740 * @retval State of bit (1 or 0).
5741 */
LL_RCC_PLL3_IsEnabledBypass(void)5742 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledBypass(void)
5743 {
5744 return ((READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3BYP) == RCC_PLL3CFGR1_PLL3BYP) ? 1UL : 0UL);
5745 }
5746
5747 /**
5748 * @brief Assert PLL3 modulation spread-spectrum reset
5749 * @note This API shall be called only when PLL3 is disabled.
5750 * @rmtoll PLL3CFGR3 PLL3MODSSRST LL_RCC_PLL3_AssertModulationSpreadSpectrumReset
5751 * @retval None
5752 */
LL_RCC_PLL3_AssertModulationSpreadSpectrumReset(void)5753 __STATIC_INLINE void LL_RCC_PLL3_AssertModulationSpreadSpectrumReset(void)
5754 {
5755 SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSRST);
5756 }
5757
5758 /**
5759 * @brief Release PLL3 modulation spread-spectrum reset
5760 * @note This API shall be called only when PLL3 is disabled.
5761 * @rmtoll PLL3CFGR3 PLL3MODSSRST LL_RCC_PLL3_ReleaseModulationSpreadSpectrumReset
5762 * @retval None
5763 */
LL_RCC_PLL3_ReleaseModulationSpreadSpectrumReset(void)5764 __STATIC_INLINE void LL_RCC_PLL3_ReleaseModulationSpreadSpectrumReset(void)
5765 {
5766 CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSRST);
5767 }
5768
5769 /**
5770 * @brief Enable PLL3 noise canceling DAC in fractional mode
5771 * @note This API shall be called only when PLL3 is disabled.
5772 * @rmtoll PLL3CFGR3 PLL3DACEN LL_RCC_PLL3_EnableDAC
5773 * @retval None
5774 */
LL_RCC_PLL3_EnableDAC(void)5775 __STATIC_INLINE void LL_RCC_PLL3_EnableDAC(void)
5776 {
5777 SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3DACEN);
5778 }
5779
5780 /**
5781 * @brief Disable PLL3 noise canceling DAC in fractional mode
5782 * @note This API shall be called only when PLL3 is disabled.
5783 * @rmtoll PLL3CFGR3 PLL3DACEN LL_RCC_PLL3_DisableDAC
5784 * @retval None
5785 */
LL_RCC_PLL3_DisableDAC(void)5786 __STATIC_INLINE void LL_RCC_PLL3_DisableDAC(void)
5787 {
5788 CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3DACEN);
5789 }
5790
5791 /**
5792 * @brief Check if PLL3 noise canceling DAC in fractional mode is enabled
5793 * @rmtoll PLL3CFGR3 PLL3DACEN LL_RCC_PLL3_IsEnabledDAC
5794 * @retval State of bit (1 or 0).
5795 */
LL_RCC_PLL3_IsEnabledDAC(void)5796 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDAC(void)
5797 {
5798 return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3DACEN) == RCC_PLL3CFGR3_PLL3DACEN) ? 1UL : 0UL);
5799 }
5800
5801 /**
5802 * @brief Enable PLL3 modulation spread-spectrum with fractional divide inactive
5803 * @note This API shall be called only when PLL3 is disabled.
5804 * @rmtoll PLL3CFGR3 PLL3MODSSDIS LL_RCC_PLL3_EnableModulationSpreadSpectrum
5805 * @retval None
5806 */
LL_RCC_PLL3_EnableModulationSpreadSpectrum(void)5807 __STATIC_INLINE void LL_RCC_PLL3_EnableModulationSpreadSpectrum(void)
5808 {
5809 CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSDIS);
5810 }
5811
5812 /**
5813 * @brief Disable PLL3 modulation spread-spectrum but active fractional divide
5814 * @note This API shall be called only when PLL3 is disabled.
5815 * @rmtoll PLL3CFGR3 PLL3MODSSDIS LL_RCC_PLL3_DisableModulationSpreadSpectrum
5816 * @retval None
5817 */
LL_RCC_PLL3_DisableModulationSpreadSpectrum(void)5818 __STATIC_INLINE void LL_RCC_PLL3_DisableModulationSpreadSpectrum(void)
5819 {
5820 SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSDIS);
5821 }
5822
5823 /**
5824 * @brief Check if PLL3 modulation spread-spectrum and inactive fractional divide is enabled
5825 * @rmtoll PLL3CFGR3 PLL3MODSSDIS LL_RCC_PLL3_IsEnabledModulationSpreadSpectrum
5826 * @retval State of bit (1 or 0).
5827 */
LL_RCC_PLL3_IsEnabledModulationSpreadSpectrum(void)5828 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledModulationSpreadSpectrum(void)
5829 {
5830 return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSDIS) == 0UL) ? 1UL : 0UL);
5831 }
5832
5833 /**
5834 * @brief Enable PLL3 fractional divide and modulation spread-spectrum
5835 * @note This API shall be called only when PLL3 is disabled.
5836 * @rmtoll PLL3CFGR3 PLL3MODDSEN LL_RCC_PLL3_EnableFractionalModulationSpreadSpectrum
5837 * @retval None
5838 */
LL_RCC_PLL3_EnableFractionalModulationSpreadSpectrum(void)5839 __STATIC_INLINE void LL_RCC_PLL3_EnableFractionalModulationSpreadSpectrum(void)
5840 {
5841 SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODDSEN);
5842 }
5843
5844 /**
5845 * @brief Disable PLL3 fractional divide and modulation spread-spectrum
5846 * @note This API shall be called only when PLL3 is disabled.
5847 * @rmtoll PLL3CFGR3 PLL3MODDSEN LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum
5848 * @retval None
5849 */
LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum(void)5850 __STATIC_INLINE void LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum(void)
5851 {
5852 CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODDSEN);
5853 }
5854
5855 /**
5856 * @brief Check if PLL3 fractional divide and modulation spread-spectrum is enabled
5857 * @rmtoll PLL3CFGR3 PLL3MODDSEN LL_RCC_PLL3_IsEnabledFractionalModulationSpreadSpectrum
5858 * @retval State of bit (1 or 0).
5859 */
LL_RCC_PLL3_IsEnabledFractionalModulationSpreadSpectrum(void)5860 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledFractionalModulationSpreadSpectrum(void)
5861 {
5862 return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODDSEN) == RCC_PLL3CFGR3_PLL3MODDSEN) ? 1UL : 0UL);
5863 }
5864
5865 /**
5866 * @brief Set PLL3 DIVN Coefficient
5867 * @note This API shall be called only when PLL3 is disabled.
5868 * @rmtoll PLL3CFGR1 PLL3DIVN LL_RCC_PLL3_SetN
5869 * @param N In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4).
5870 * In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4).
5871 */
LL_RCC_PLL3_SetN(uint32_t N)5872 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
5873 {
5874 MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVN, N << RCC_PLL3CFGR1_PLL3DIVN_Pos);
5875 }
5876
5877 /**
5878 * @brief Get PLL3 DIVN Coefficient
5879 * @rmtoll PLL3CFGR1 PLL3DIVN LL_RCC_PLL3_GetN
5880 * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4).
5881 * In fractional mode, a value between 20 (0x14) and 500 (0x1F4).
5882 */
LL_RCC_PLL3_GetN(void)5883 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
5884 {
5885 return (uint32_t)((READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos));
5886 }
5887
5888 /**
5889 * @brief Set PLL3 DIVM Coefficient
5890 * @note This API shall be called only when PLL3 is disabled.
5891 * @rmtoll PLL3CFGR1 PLL3DIVM LL_RCC_PLL3_SetM
5892 * @param M parameter can be a value between 1 and 63
5893 */
LL_RCC_PLL3_SetM(uint32_t M)5894 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
5895 {
5896 MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVM, M << RCC_PLL3CFGR1_PLL3DIVM_Pos);
5897 }
5898
5899 /**
5900 * @brief Get PLL3 DIVM Coefficient
5901 * @rmtoll PLL3CFGR1 PLL3DIVM LL_RCC_PLL3_GetM
5902 * @retval A value between 1 and 63
5903 */
LL_RCC_PLL3_GetM(void)5904 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
5905 {
5906 return (uint32_t)(READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos);
5907 }
5908
5909 /**
5910 * @brief Set PLL3 PDIV1 Coefficient
5911 * @note This API shall be called only when PLL3 is disabled.
5912 * @rmtoll PLL3CFGR3 PLL3PDIV1 LL_RCC_PLL3_SetP1
5913 * @param P1 parameter can be a value between 1 and 7 when PLL3 is enabled, 0 when disabled
5914 */
LL_RCC_PLL3_SetP1(uint32_t P1)5915 __STATIC_INLINE void LL_RCC_PLL3_SetP1(uint32_t P1)
5916 {
5917 MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV1, P1 << RCC_PLL3CFGR3_PLL3PDIV1_Pos);
5918 }
5919
5920 /**
5921 * @brief Get PLL3 PDIV2 Coefficient
5922 * @rmtoll PLL3CFGR3 PLL3PDIV1 LL_RCC_PLL3_GetP1
5923 * @retval A value between 1 and 7
5924 */
LL_RCC_PLL3_GetP1(void)5925 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP1(void)
5926 {
5927 return (uint32_t)(READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos);
5928 }
5929
5930 /**
5931 * @brief Set PLL3 PDIV2 Coefficient
5932 * @note This API shall be called only when PLL3 is disabled.
5933 * @rmtoll PLL3CFGR3 PLL3PDIV2 LL_RCC_PLL3_SetP2
5934 * @param P2 parameter can be a value between 0 and 7
5935 */
LL_RCC_PLL3_SetP2(uint32_t P2)5936 __STATIC_INLINE void LL_RCC_PLL3_SetP2(uint32_t P2)
5937 {
5938 MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV2, P2 << RCC_PLL3CFGR3_PLL3PDIV2_Pos);
5939 }
5940
5941 /**
5942 * @brief Get PLL3 PDIV2 Coefficient
5943 * @rmtoll PLL3CFGR3 PLL3PDIV2 LL_RCC_PLL3_GetP2
5944 * @retval A value between 1 and 7
5945 */
LL_RCC_PLL3_GetP2(void)5946 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP2(void)
5947 {
5948 return (uint32_t)(READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos);
5949 }
5950
5951 /**
5952 * @brief Enable PLL3P
5953 * @note This API shall be called only when PLL3 is disabled.
5954 * @rmtoll PLL3CFGR3 PLL3PDIVEN LL_RCC_PLL3P_Enable
5955 * @retval None
5956 */
LL_RCC_PLL3P_Enable(void)5957 __STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
5958 {
5959 SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIVEN);
5960 }
5961
5962 /**
5963 * @brief Disable PLL3P
5964 * @note This API shall be called only when PLL3 is disabled.
5965 * @rmtoll PLL3CFGR3 PLL3PDIVEN LL_RCC_PLL3P_Disable
5966 * @retval None
5967 */
LL_RCC_PLL3P_Disable(void)5968 __STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
5969 {
5970 CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIVEN);
5971 }
5972
5973 /**
5974 * @brief Check if PLL3 P is enabled
5975 * @rmtoll PLL3CFGR3 PLL3PDIVEN LL_RCC_PLL3P_IsEnabled
5976 * @retval State of bit (1 or 0).
5977 */
LL_RCC_PLL3P_IsEnabled(void)5978 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
5979 {
5980 return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIVEN) == RCC_PLL3CFGR3_PLL3PDIVEN) ? 1UL : 0UL);
5981 }
5982
5983 /**
5984 * @brief Set PLL3 FRACN Coefficient
5985 * @note This API shall be called only when PLL3 is disabled.
5986 * @rmtoll PLL3CFGR2 PLL3DIVNFRAC LL_RCC_PLL3_SetFRACN
5987 * @param FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF)
5988 */
LL_RCC_PLL3_SetFRACN(uint32_t FRACN)5989 __STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
5990 {
5991 MODIFY_REG(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC, FRACN << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos);
5992 }
5993
5994 /**
5995 * @brief Get PLL3 FRACN Coefficient
5996 * @rmtoll PLL3CFGR2 PLL3DIVNFRAC LL_RCC_PLL3_GetFRACN
5997 * @retval A value between 0 and 2^24 (0xFFFFFF)
5998 */
LL_RCC_PLL3_GetFRACN(void)5999 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
6000 {
6001 return (uint32_t)(READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC) >> RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos);
6002 }
6003
6004 /**
6005 * @brief Set the oscillator used as PLL clock source.
6006 * @note PLL4SEL can be written only when All PLLs are disabled.
6007 * @rmtoll PLL4CFGR1 PLL4SEL LL_RCC_PLL4_SetSource
6008 * @param PLLSource parameter can be one of the following values:
6009 * @arg @ref LL_RCC_PLLSOURCE_HSI
6010 * @arg @ref LL_RCC_PLLSOURCE_MSI
6011 * @arg @ref LL_RCC_PLLSOURCE_HSE
6012 * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
6013 * @retval None
6014 */
LL_RCC_PLL4_SetSource(uint32_t PLLSource)6015 __STATIC_INLINE void LL_RCC_PLL4_SetSource(uint32_t PLLSource)
6016 {
6017 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4SEL, PLLSource);
6018 }
6019
6020 /**
6021 * @brief Get the oscillator used as PLL clock source.
6022 * @rmtoll PLL4CFGR1 PLL4SEL LL_RCC_PLL4_GetSource
6023 * @retval Returned value can be one of the following values:
6024 * @arg @ref LL_RCC_PLLSOURCE_HSI
6025 * @arg @ref LL_RCC_PLLSOURCE_MSI
6026 * @arg @ref LL_RCC_PLLSOURCE_HSE
6027 * @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
6028 */
LL_RCC_PLL4_GetSource(void)6029 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetSource(void)
6030 {
6031 return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4SEL));
6032 }
6033
6034 /**
6035 * @brief Enable PLL4
6036 * @rmtoll CSR PLL4ONS LL_RCC_PLL4_Enable
6037 * @retval None
6038 */
LL_RCC_PLL4_Enable(void)6039 __STATIC_INLINE void LL_RCC_PLL4_Enable(void)
6040 {
6041 WRITE_REG(RCC->CSR, RCC_CSR_PLL4ONS);
6042 }
6043
6044 /**
6045 * @brief Disable PLL4
6046 * @note Cannot be disabled if the PLL4 clock is used as the system clock
6047 * @rmtoll CCR PLL4ONC LL_RCC_PLL4_Disable
6048 * @retval None
6049 */
LL_RCC_PLL4_Disable(void)6050 __STATIC_INLINE void LL_RCC_PLL4_Disable(void)
6051 {
6052 WRITE_REG(RCC->CCR, RCC_CCR_PLL4ONC);
6053 }
6054
6055 /**
6056 * @brief Check if PLL4 Ready
6057 * @rmtoll SR PLL4RDY LL_RCC_PLL4_IsReady
6058 * @retval State of bit (1 or 0).
6059 */
LL_RCC_PLL4_IsReady(void)6060 __STATIC_INLINE uint32_t LL_RCC_PLL4_IsReady(void)
6061 {
6062 return ((READ_BIT(RCC->SR, RCC_SR_PLL4RDY) == (RCC_SR_PLL4RDY)) ? 1UL : 0UL);
6063 }
6064
6065 /**
6066 * @brief Enable PLL4 bypass (PLL4 output is driven by the PLL4 reference clock)
6067 * @note This API shall be called only when PLL4 is disabled.
6068 * @rmtoll PLL4CFGR1 PLL4BYP LL_RCC_PLL4_EnableBypass
6069 * @retval None
6070 */
LL_RCC_PLL4_EnableBypass(void)6071 __STATIC_INLINE void LL_RCC_PLL4_EnableBypass(void)
6072 {
6073 SET_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP);
6074 }
6075
6076 /**
6077 * @brief Disable PLL4 bypass (PLL4 output is driven by the VCO)
6078 * @note This API shall be called only when PLL4 is disabled.
6079 * @rmtoll PLL4CFGR1 PLL4BYP LL_RCC_PLL4_DisableBypass
6080 * @retval None
6081 */
LL_RCC_PLL4_DisableBypass(void)6082 __STATIC_INLINE void LL_RCC_PLL4_DisableBypass(void)
6083 {
6084 CLEAR_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP);
6085 }
6086
6087 /**
6088 * @brief Check if PLL4 bypass is enabled
6089 * @rmtoll PLL4CFGR1 PLL4BYP LL_RCC_PLL4_IsEnabledBypass
6090 * @retval State of bit (1 or 0).
6091 */
LL_RCC_PLL4_IsEnabledBypass(void)6092 __STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledBypass(void)
6093 {
6094 return ((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP) == RCC_PLL4CFGR1_PLL4BYP) ? 1UL : 0UL);
6095 }
6096
6097 /**
6098 * @brief Assert PLL4 modulation spread-spectrum reset
6099 * @note This API shall be called only when PLL4 is disabled.
6100 * @rmtoll PLL4CFGR3 PLL4MODSSRST LL_RCC_PLL4_AssertModulationSpreadSpectrumReset
6101 * @retval None
6102 */
LL_RCC_PLL4_AssertModulationSpreadSpectrumReset(void)6103 __STATIC_INLINE void LL_RCC_PLL4_AssertModulationSpreadSpectrumReset(void)
6104 {
6105 SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSRST);
6106 }
6107
6108 /**
6109 * @brief Release PLL4 modulation spread-spectrum reset
6110 * @note This API shall be called only when PLL4 is disabled.
6111 * @rmtoll PLL4CFGR3 PLL4MODSSRST LL_RCC_PLL4_ReleaseModulationSpreadSpectrumReset
6112 * @retval None
6113 */
LL_RCC_PLL4_ReleaseModulationSpreadSpectrumReset(void)6114 __STATIC_INLINE void LL_RCC_PLL4_ReleaseModulationSpreadSpectrumReset(void)
6115 {
6116 CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSRST);
6117 }
6118
6119 /**
6120 * @brief Enable PLL4 noise canceling DAC in fractional mode
6121 * @note This API shall be called only when PLL4 is disabled.
6122 * @rmtoll PLL4CFGR3 PLL4DACEN LL_RCC_PLL4_EnableDAC
6123 * @retval None
6124 */
LL_RCC_PLL4_EnableDAC(void)6125 __STATIC_INLINE void LL_RCC_PLL4_EnableDAC(void)
6126 {
6127 SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN);
6128 }
6129
6130 /**
6131 * @brief Disable PLL4 noise canceling DAC in fractional mode
6132 * @note This API shall be called only when PLL4 is disabled.
6133 * @rmtoll PLL4CFGR3 PLL4DACEN LL_RCC_PLL4_DisableDAC
6134 * @retval None
6135 */
LL_RCC_PLL4_DisableDAC(void)6136 __STATIC_INLINE void LL_RCC_PLL4_DisableDAC(void)
6137 {
6138 CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN);
6139 }
6140
6141 /**
6142 * @brief Check if PLL4 noise canceling DAC in fractional mode is enabled
6143 * @rmtoll PLL4CFGR3 PLL4DACEN LL_RCC_PLL4_IsEnabledDAC
6144 * @retval State of bit (1 or 0).
6145 */
LL_RCC_PLL4_IsEnabledDAC(void)6146 __STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledDAC(void)
6147 {
6148 return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN) == RCC_PLL4CFGR3_PLL4DACEN) ? 1UL : 0UL);
6149 }
6150
6151 /**
6152 * @brief Enable PLL4 modulation spread-spectrum with fractional divide inactive
6153 * @note This API shall be called only when PLL4 is disabled.
6154 * @rmtoll PLL4CFGR3 PLL4MODSSDIS LL_RCC_PLL4_EnableModulationSpreadSpectrum
6155 * @retval None
6156 */
LL_RCC_PLL4_EnableModulationSpreadSpectrum(void)6157 __STATIC_INLINE void LL_RCC_PLL4_EnableModulationSpreadSpectrum(void)
6158 {
6159 CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS);
6160 }
6161
6162 /**
6163 * @brief Disable PLL4 modulation spread-spectrum but active fractional divide
6164 * @note This API shall be called only when PLL4 is disabled.
6165 * @rmtoll PLL4CFGR3 PLL4MODSSDIS LL_RCC_PLL4_DisableModulationSpreadSpectrum
6166 * @retval None
6167 */
LL_RCC_PLL4_DisableModulationSpreadSpectrum(void)6168 __STATIC_INLINE void LL_RCC_PLL4_DisableModulationSpreadSpectrum(void)
6169 {
6170 SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS);
6171 }
6172
6173 /**
6174 * @brief Check if PLL4 modulation spread-spectrum and inactive fractional divide is enabled
6175 * @rmtoll PLL4CFGR3 PLL4MODSSDIS LL_RCC_PLL4_IsEnabledModulationSpreadSpectrum
6176 * @retval State of bit (1 or 0).
6177 */
LL_RCC_PLL4_IsEnabledModulationSpreadSpectrum(void)6178 __STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledModulationSpreadSpectrum(void)
6179 {
6180 return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS) == 0UL) ? 1UL : 0UL);
6181 }
6182
6183 /**
6184 * @brief Enable PLL4 fractional divide and modulation spread-spectrum
6185 * @note This API shall be called only when PLL4 is disabled.
6186 * @rmtoll PLL4CFGR3 PLL4MODDSEN LL_RCC_PLL4_EnableFractionalModulationSpreadSpectrum
6187 * @retval None
6188 */
LL_RCC_PLL4_EnableFractionalModulationSpreadSpectrum(void)6189 __STATIC_INLINE void LL_RCC_PLL4_EnableFractionalModulationSpreadSpectrum(void)
6190 {
6191 SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODDSEN);
6192 }
6193
6194 /**
6195 * @brief Disable PLL4 fractional divide and modulation spread-spectrum
6196 * @note This API shall be called only when PLL4 is disabled.
6197 * @rmtoll PLL4CFGR3 PLL4MODDSEN LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum
6198 * @retval None
6199 */
LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum(void)6200 __STATIC_INLINE void LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum(void)
6201 {
6202 CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODDSEN);
6203 }
6204
6205 /**
6206 * @brief Check if PLL4 fractional divide and modulation spread-spectrum is enabled
6207 * @rmtoll PLL4CFGR3 PLL4MODDSEN LL_RCC_PLL4_IsEnabledFractionalModulationSpreadSpectrum
6208 * @retval State of bit (1 or 0).
6209 */
LL_RCC_PLL4_IsEnabledFractionalModulationSpreadSpectrum(void)6210 __STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledFractionalModulationSpreadSpectrum(void)
6211 {
6212 return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODDSEN) == RCC_PLL4CFGR3_PLL4MODDSEN) ? 1UL : 0UL);
6213 }
6214
6215 /**
6216 * @brief Set PLL4 DIVN Coefficient
6217 * @note This API shall be called only when PLL4 is disabled.
6218 * @rmtoll PLL4CFGR1 PLL4DIVN LL_RCC_PLL4_SetN
6219 * @param N In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4).
6220 * In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4).
6221 */
LL_RCC_PLL4_SetN(uint32_t N)6222 __STATIC_INLINE void LL_RCC_PLL4_SetN(uint32_t N)
6223 {
6224 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVN, N << RCC_PLL4CFGR1_PLL4DIVN_Pos);
6225 }
6226
6227 /**
6228 * @brief Get PLL4 DIVN Coefficient
6229 * @rmtoll PLL4CFGR1 PLL4DIVN LL_RCC_PLL4_GetN
6230 * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4).
6231 * In fractional mode, a value between 20 (0x14) and 500 (0x1F4).
6232 */
LL_RCC_PLL4_GetN(void)6233 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetN(void)
6234 {
6235 return (uint32_t)((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos));
6236 }
6237
6238 /**
6239 * @brief Set PLL4 DIVM Coefficient
6240 * @note This API shall be called only when PLL4 is disabled.
6241 * @rmtoll PLL4CFGR1 PLL4DIVM LL_RCC_PLL4_SetM
6242 * @param M parameter can be a value between 1 and 63
6243 */
LL_RCC_PLL4_SetM(uint32_t M)6244 __STATIC_INLINE void LL_RCC_PLL4_SetM(uint32_t M)
6245 {
6246 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM, M << RCC_PLL4CFGR1_PLL4DIVM_Pos);
6247 }
6248
6249 /**
6250 * @brief Get PLL4 DIVM Coefficient
6251 * @rmtoll PLL4CFGR1 PLL4DIVM LL_RCC_PLL4_GetM
6252 * @retval A value between 1 and 63
6253 */
LL_RCC_PLL4_GetM(void)6254 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetM(void)
6255 {
6256 return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos);
6257 }
6258
6259 /**
6260 * @brief Set PLL4 PDIV1 Coefficient
6261 * @note This API shall be called only when PLL4 is disabled.
6262 * @rmtoll PLL4CFGR3 PLL4PDIV1 LL_RCC_PLL4_SetP1
6263 * @param P1 parameter can be a value between 1 and 7 when PLL4 is enabled, 0 when disabled
6264 */
LL_RCC_PLL4_SetP1(uint32_t P1)6265 __STATIC_INLINE void LL_RCC_PLL4_SetP1(uint32_t P1)
6266 {
6267 MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV1, P1 << RCC_PLL4CFGR3_PLL4PDIV1_Pos);
6268 }
6269
6270 /**
6271 * @brief Get PLL4 PDIV2 Coefficient
6272 * @rmtoll PLL4CFGR3 PLL4PDIV1 LL_RCC_PLL4_GetP1
6273 * @retval A value between 0 and 7
6274 */
LL_RCC_PLL4_GetP1(void)6275 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetP1(void)
6276 {
6277 return (uint32_t)(READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos);
6278 }
6279
6280 /**
6281 * @brief Set PLL4 PDIV2 Coefficient
6282 * @note This API shall be called only when PLL4 is disabled.
6283 * @rmtoll PLL4CFGR3 PLL4PDIV2 LL_RCC_PLL4_SetP2
6284 * @param P2 parameter can be a value between 1 and 7
6285 */
LL_RCC_PLL4_SetP2(uint32_t P2)6286 __STATIC_INLINE void LL_RCC_PLL4_SetP2(uint32_t P2)
6287 {
6288 MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV2, P2 << RCC_PLL4CFGR3_PLL4PDIV2_Pos);
6289 }
6290
6291 /**
6292 * @brief Get PLL4 PDIV2 Coefficient
6293 * @rmtoll PLL4CFGR3 PLL4PDIV2 LL_RCC_PLL4_GetP2
6294 * @retval A value between 1 and 7
6295 */
LL_RCC_PLL4_GetP2(void)6296 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetP2(void)
6297 {
6298 return (uint32_t)(READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos);
6299 }
6300
6301 /**
6302 * @brief Enable PLL4P
6303 * @note This API shall be called only when PLL4 is disabled.
6304 * @rmtoll PLL4CFGR3 PLL4PDIVEN LL_RCC_PLL4P_Enable
6305 * @retval None
6306 */
LL_RCC_PLL4P_Enable(void)6307 __STATIC_INLINE void LL_RCC_PLL4P_Enable(void)
6308 {
6309 SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIVEN);
6310 }
6311
6312 /**
6313 * @brief Disable PLL4P
6314 * @note This API shall be called only when PLL4 is disabled.
6315 * @rmtoll PLL4CFGR3 PLL4PDIVEN LL_RCC_PLL4P_Disable
6316 * @retval None
6317 */
LL_RCC_PLL4P_Disable(void)6318 __STATIC_INLINE void LL_RCC_PLL4P_Disable(void)
6319 {
6320 CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIVEN);
6321 }
6322
6323 /**
6324 * @brief Check if PLL4 P is enabled
6325 * @rmtoll PLL4CFGR3 PLL4PDIVEN LL_RCC_PLL4P_IsEnabled
6326 * @retval State of bit (1 or 0).
6327 */
LL_RCC_PLL4P_IsEnabled(void)6328 __STATIC_INLINE uint32_t LL_RCC_PLL4P_IsEnabled(void)
6329 {
6330 return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIVEN) == RCC_PLL4CFGR3_PLL4PDIVEN) ? 1UL : 0UL);
6331 }
6332
6333 /**
6334 * @brief Set PLL4 FRACN Coefficient
6335 * @note This API shall be called only when PLL4 is disabled.
6336 * @rmtoll PLL4CFGR2 PLL4DIVNFRAC LL_RCC_PLL4_SetFRACN
6337 * @param FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF)
6338 */
LL_RCC_PLL4_SetFRACN(uint32_t FRACN)6339 __STATIC_INLINE void LL_RCC_PLL4_SetFRACN(uint32_t FRACN)
6340 {
6341 MODIFY_REG(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC, FRACN << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos);
6342 }
6343
6344 /**
6345 * @brief Get PLL4 FRACN Coefficient
6346 * @rmtoll PLL4CFGR2 PLL4DIVNFRAC LL_RCC_PLL4_GetFRACN
6347 * @retval A value between 0 and 2^24 (0xFFFFFF)
6348 */
LL_RCC_PLL4_GetFRACN(void)6349 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetFRACN(void)
6350 {
6351 return (uint32_t)(READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC) >> RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos);
6352 }
6353
6354 /**
6355 * @brief Enable IC1
6356 * @rmtoll DIVENSR IC1ENS LL_RCC_IC1_Enable
6357 * @retval None
6358 */
LL_RCC_IC1_Enable(void)6359 __STATIC_INLINE void LL_RCC_IC1_Enable(void)
6360 {
6361 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC1ENS);
6362 }
6363
6364 /**
6365 * @brief Disable IC1
6366 * @rmtoll DIVENCR IC1ENC LL_RCC_IC1_Disable
6367 * @retval None
6368 */
LL_RCC_IC1_Disable(void)6369 __STATIC_INLINE void LL_RCC_IC1_Disable(void)
6370 {
6371 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC1ENC);
6372 }
6373
6374 /**
6375 * @brief Check if IC1 is enabled
6376 * @rmtoll DIVENR IC1EN LL_RCC_IC1_IsEnabled
6377 * @retval State of bit (1 or 0).
6378 */
LL_RCC_IC1_IsEnabled(void)6379 __STATIC_INLINE uint32_t LL_RCC_IC1_IsEnabled(void)
6380 {
6381 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC1EN) == RCC_DIVENR_IC1EN) ? 1UL : 0UL);
6382 }
6383
6384 /**
6385 * @brief Set the PLL source used as IC1 clock source.
6386 * @rmtoll IC1CFGR IC1SEL LL_RCC_IC1_SetSource
6387 * @param Source parameter can be one of the following values:
6388 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6389 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6390 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6391 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6392 * @retval None
6393 */
LL_RCC_IC1_SetSource(uint32_t Source)6394 __STATIC_INLINE void LL_RCC_IC1_SetSource(uint32_t Source)
6395 {
6396 MODIFY_REG(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL, Source);
6397 }
6398
6399 /**
6400 * @brief Get the PLL source used as IC1 clock source.
6401 * @rmtoll IC1CFGR IC1SEL LL_RCC_IC1_GetSource
6402 * @retval Returned value can be one of the following values:
6403 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6404 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6405 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6406 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6407 */
LL_RCC_IC1_GetSource(void)6408 __STATIC_INLINE uint32_t LL_RCC_IC1_GetSource(void)
6409 {
6410 return (uint32_t)(READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL));
6411 }
6412
6413 /**
6414 * @brief Set divider
6415 * @rmtoll IC1CFGR IC1INT LL_RCC_IC1_SetDivider
6416 * @param Divider This parameter can be a value between 1 and 256.
6417 * @retval None
6418 */
LL_RCC_IC1_SetDivider(uint32_t Divider)6419 __STATIC_INLINE void LL_RCC_IC1_SetDivider(uint32_t Divider)
6420 {
6421 MODIFY_REG(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT, (Divider - 1UL) << RCC_IC1CFGR_IC1INT_Pos);
6422 }
6423
6424 /**
6425 * @brief Get IC1 divider
6426 * @rmtoll IC1CFGR IC1INT LL_RCC_IC1_GetDivider
6427 * @retval can be a value between 1 and 256.
6428 */
LL_RCC_IC1_GetDivider(void)6429 __STATIC_INLINE uint32_t LL_RCC_IC1_GetDivider(void)
6430 {
6431 return ((READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1UL);
6432 }
6433
6434 /**
6435 * @brief Enable IC2
6436 * @rmtoll DIVENSR IC2ENS LL_RCC_IC2_Enable
6437 * @retval None
6438 */
LL_RCC_IC2_Enable(void)6439 __STATIC_INLINE void LL_RCC_IC2_Enable(void)
6440 {
6441 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC2ENS);
6442 }
6443
6444 /**
6445 * @brief Disable IC2
6446 * @rmtoll DIVENCR IC2ENC LL_RCC_IC2_Disable
6447 * @retval None
6448 */
LL_RCC_IC2_Disable(void)6449 __STATIC_INLINE void LL_RCC_IC2_Disable(void)
6450 {
6451 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC2ENC);
6452 }
6453
6454 /**
6455 * @brief Check if IC2 is enabled
6456 * @rmtoll DIVENR IC2EN LL_RCC_IC2_IsEnabled
6457 * @retval State of bit (1 or 0).
6458 */
LL_RCC_IC2_IsEnabled(void)6459 __STATIC_INLINE uint32_t LL_RCC_IC2_IsEnabled(void)
6460 {
6461 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC2EN) == RCC_DIVENR_IC2EN) ? 1UL : 0UL);
6462 }
6463
6464 /**
6465 * @brief Set the PLL source used as IC2 clock source.
6466 * @rmtoll IC2CFGR IC2SEL LL_RCC_IC2_SetSource
6467 * @param Source parameter can be one of the following values:
6468 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6469 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6470 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6471 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6472 * @retval None
6473 */
LL_RCC_IC2_SetSource(uint32_t Source)6474 __STATIC_INLINE void LL_RCC_IC2_SetSource(uint32_t Source)
6475 {
6476 MODIFY_REG(RCC->IC2CFGR, RCC_IC2CFGR_IC2SEL, Source);
6477 }
6478
6479 /**
6480 * @brief Get the PLL source used as IC2 clock source.
6481 * @rmtoll IC2CFGR IC2SEL LL_RCC_IC2_GetSource
6482 * @retval Returned value can be one of the following values:
6483 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6484 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6485 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6486 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6487 */
LL_RCC_IC2_GetSource(void)6488 __STATIC_INLINE uint32_t LL_RCC_IC2_GetSource(void)
6489 {
6490 return (uint32_t)(READ_BIT(RCC->IC2CFGR, RCC_IC2CFGR_IC2SEL));
6491 }
6492
6493 /**
6494 * @brief Set divider
6495 * @rmtoll IC2CFGR IC2INT LL_RCC_IC2_SetDivider
6496 * @param Divider This parameter can be a value between 1 and 256.
6497 * @retval None
6498 */
LL_RCC_IC2_SetDivider(uint32_t Divider)6499 __STATIC_INLINE void LL_RCC_IC2_SetDivider(uint32_t Divider)
6500 {
6501 MODIFY_REG(RCC->IC2CFGR, RCC_IC2CFGR_IC2INT, (Divider - 1UL) << RCC_IC2CFGR_IC2INT_Pos);
6502 }
6503
6504 /**
6505 * @brief Get IC2 divider
6506 * @rmtoll IC2CFGR IC2INT LL_RCC_IC2_GetDivider
6507 * @retval can be a value between 1 and 256.
6508 */
LL_RCC_IC2_GetDivider(void)6509 __STATIC_INLINE uint32_t LL_RCC_IC2_GetDivider(void)
6510 {
6511 return ((READ_BIT(RCC->IC2CFGR, RCC_IC2CFGR_IC2INT) >> RCC_IC2CFGR_IC2INT_Pos) + 1UL);
6512 }
6513
6514 /**
6515 * @brief Enable IC3
6516 * @rmtoll DIVENSR IC3ENS LL_RCC_IC3_Enable
6517 * @retval None
6518 */
LL_RCC_IC3_Enable(void)6519 __STATIC_INLINE void LL_RCC_IC3_Enable(void)
6520 {
6521 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC3ENS);
6522 }
6523
6524 /**
6525 * @brief Disable IC3
6526 * @rmtoll DIVENCR IC3ENC LL_RCC_IC3_Disable
6527 * @retval None
6528 */
LL_RCC_IC3_Disable(void)6529 __STATIC_INLINE void LL_RCC_IC3_Disable(void)
6530 {
6531 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC3ENC);
6532 }
6533
6534 /**
6535 * @brief Check if IC3 is enabled
6536 * @rmtoll DIVENR IC3EN LL_RCC_IC3_IsEnabled
6537 * @retval State of bit (1 or 0).
6538 */
LL_RCC_IC3_IsEnabled(void)6539 __STATIC_INLINE uint32_t LL_RCC_IC3_IsEnabled(void)
6540 {
6541 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC3EN) == RCC_DIVENR_IC3EN) ? 1UL : 0UL);
6542 }
6543
6544 /**
6545 * @brief Set the PLL source used as IC3 clock source.
6546 * @rmtoll IC3CFGR IC3SEL LL_RCC_IC3_SetSource
6547 * @param Source parameter can be one of the following values:
6548 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6549 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6550 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6551 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6552 * @retval None
6553 */
LL_RCC_IC3_SetSource(uint32_t Source)6554 __STATIC_INLINE void LL_RCC_IC3_SetSource(uint32_t Source)
6555 {
6556 MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL, Source);
6557 }
6558
6559 /**
6560 * @brief Get the PLL source used as IC3 clock source.
6561 * @rmtoll IC3CFGR IC3SEL LL_RCC_IC3_GetSource
6562 * @retval Returned value can be one of the following values:
6563 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6564 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6565 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6566 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6567 */
LL_RCC_IC3_GetSource(void)6568 __STATIC_INLINE uint32_t LL_RCC_IC3_GetSource(void)
6569 {
6570 return (uint32_t)(READ_BIT(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL));
6571 }
6572
6573 /**
6574 * @brief Set divider
6575 * @rmtoll IC3CFGR IC3INT LL_RCC_IC3_SetDivider
6576 * @param Divider This parameter can be a value between 1 and 256.
6577 * @retval None
6578 */
LL_RCC_IC3_SetDivider(uint32_t Divider)6579 __STATIC_INLINE void LL_RCC_IC3_SetDivider(uint32_t Divider)
6580 {
6581 MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3INT, (Divider - 1UL) << RCC_IC3CFGR_IC3INT_Pos);
6582 }
6583
6584 /**
6585 * @brief Get IC3 divider
6586 * @rmtoll IC3CFGR IC3INT LL_RCC_IC3_GetDivider
6587 * @retval can be a value between 1 and 256.
6588 */
LL_RCC_IC3_GetDivider(void)6589 __STATIC_INLINE uint32_t LL_RCC_IC3_GetDivider(void)
6590 {
6591 return ((READ_BIT(RCC->IC3CFGR, RCC_IC3CFGR_IC3INT) >> RCC_IC3CFGR_IC3INT_Pos) + 1UL);
6592 }
6593
6594 /**
6595 * @brief Enable IC4
6596 * @rmtoll DIVENSR IC4ENS LL_RCC_IC4_Enable
6597 * @retval None
6598 */
LL_RCC_IC4_Enable(void)6599 __STATIC_INLINE void LL_RCC_IC4_Enable(void)
6600 {
6601 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC4ENS);
6602 }
6603
6604 /**
6605 * @brief Disable IC4
6606 * @rmtoll DIVENCR IC4ENC LL_RCC_IC4_Disable
6607 * @retval None
6608 */
LL_RCC_IC4_Disable(void)6609 __STATIC_INLINE void LL_RCC_IC4_Disable(void)
6610 {
6611 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC4ENC);
6612 }
6613
6614 /**
6615 * @brief Check if IC4 is enabled
6616 * @rmtoll DIVENR IC4EN LL_RCC_IC4_IsEnabled
6617 * @retval State of bit (1 or 0).
6618 */
LL_RCC_IC4_IsEnabled(void)6619 __STATIC_INLINE uint32_t LL_RCC_IC4_IsEnabled(void)
6620 {
6621 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC4EN) == RCC_DIVENR_IC4EN) ? 1UL : 0UL);
6622 }
6623
6624 /**
6625 * @brief Set the PLL source used as IC4 clock source.
6626 * @rmtoll IC4CFGR IC4SEL LL_RCC_IC4_SetSource
6627 * @param Source parameter can be one of the following values:
6628 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6629 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6630 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6631 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6632 * @retval None
6633 */
LL_RCC_IC4_SetSource(uint32_t Source)6634 __STATIC_INLINE void LL_RCC_IC4_SetSource(uint32_t Source)
6635 {
6636 MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL, Source);
6637 }
6638
6639 /**
6640 * @brief Get the PLL source used as IC4 clock source.
6641 * @rmtoll IC4CFGR IC4SEL LL_RCC_IC4_GetSource
6642 * @retval Returned value can be one of the following values:
6643 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6644 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6645 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6646 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6647 */
LL_RCC_IC4_GetSource(void)6648 __STATIC_INLINE uint32_t LL_RCC_IC4_GetSource(void)
6649 {
6650 return (uint32_t)(READ_BIT(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL));
6651 }
6652
6653 /**
6654 * @brief Set divider
6655 * @rmtoll IC4CFGR IC4INT LL_RCC_IC4_SetDivider
6656 * @param Divider This parameter can be a value between 1 and 256.
6657 * @retval None
6658 */
LL_RCC_IC4_SetDivider(uint32_t Divider)6659 __STATIC_INLINE void LL_RCC_IC4_SetDivider(uint32_t Divider)
6660 {
6661 MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4INT, (Divider - 1UL) << RCC_IC4CFGR_IC4INT_Pos);
6662 }
6663
6664 /**
6665 * @brief Get IC4 divider
6666 * @rmtoll IC4CFGR IC4INT LL_RCC_IC4_GetDivider
6667 * @retval can be a value between 1 and 256.
6668 */
LL_RCC_IC4_GetDivider(void)6669 __STATIC_INLINE uint32_t LL_RCC_IC4_GetDivider(void)
6670 {
6671 return ((READ_BIT(RCC->IC4CFGR, RCC_IC4CFGR_IC4INT) >> RCC_IC4CFGR_IC4INT_Pos) + 1UL);
6672 }
6673
6674 /**
6675 * @brief Enable IC5
6676 * @rmtoll DIVENSR IC5ENS LL_RCC_IC5_Enable
6677 * @retval None
6678 */
LL_RCC_IC5_Enable(void)6679 __STATIC_INLINE void LL_RCC_IC5_Enable(void)
6680 {
6681 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC5ENS);
6682 }
6683
6684 /**
6685 * @brief Disable IC5
6686 * @rmtoll DIVENCR IC5ENC LL_RCC_IC5_Disable
6687 * @retval None
6688 */
LL_RCC_IC5_Disable(void)6689 __STATIC_INLINE void LL_RCC_IC5_Disable(void)
6690 {
6691 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC5ENC);
6692 }
6693
6694 /**
6695 * @brief Check if IC5 is enabled
6696 * @rmtoll DIVENR IC5EN LL_RCC_IC5_IsEnabled
6697 * @retval State of bit (1 or 0).
6698 */
LL_RCC_IC5_IsEnabled(void)6699 __STATIC_INLINE uint32_t LL_RCC_IC5_IsEnabled(void)
6700 {
6701 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC5EN) == RCC_DIVENR_IC5EN) ? 1UL : 0UL);
6702 }
6703
6704 /**
6705 * @brief Set the PLL source used as IC5 clock source.
6706 * @rmtoll IC5CFGR IC5SEL LL_RCC_IC5_SetSource
6707 * @param Source parameter can be one of the following values:
6708 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6709 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6710 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6711 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6712 * @retval None
6713 */
LL_RCC_IC5_SetSource(uint32_t Source)6714 __STATIC_INLINE void LL_RCC_IC5_SetSource(uint32_t Source)
6715 {
6716 MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL, Source);
6717 }
6718
6719 /**
6720 * @brief Get the PLL source used as IC5 clock source.
6721 * @rmtoll IC5CFGR IC5SEL LL_RCC_IC5_GetSource
6722 * @retval Returned value can be one of the following values:
6723 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6724 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6725 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6726 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6727 */
LL_RCC_IC5_GetSource(void)6728 __STATIC_INLINE uint32_t LL_RCC_IC5_GetSource(void)
6729 {
6730 return (uint32_t)(READ_BIT(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL));
6731 }
6732
6733 /**
6734 * @brief Set divider
6735 * @rmtoll IC5CFGR IC5INT LL_RCC_IC5_SetDivider
6736 * @param Divider This parameter can be a value between 1 and 256.
6737 * @retval None
6738 */
LL_RCC_IC5_SetDivider(uint32_t Divider)6739 __STATIC_INLINE void LL_RCC_IC5_SetDivider(uint32_t Divider)
6740 {
6741 MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5INT, (Divider - 1UL) << RCC_IC5CFGR_IC5INT_Pos);
6742 }
6743
6744 /**
6745 * @brief Get IC5 divider
6746 * @rmtoll IC5CFGR IC5INT LL_RCC_IC5_GetDivider
6747 * @retval can be a value between 1 and 256.
6748 */
LL_RCC_IC5_GetDivider(void)6749 __STATIC_INLINE uint32_t LL_RCC_IC5_GetDivider(void)
6750 {
6751 return ((READ_BIT(RCC->IC5CFGR, RCC_IC5CFGR_IC5INT) >> RCC_IC5CFGR_IC5INT_Pos) + 1UL);
6752 }
6753
6754 /**
6755 * @brief Enable IC6
6756 * @rmtoll DIVENSR IC6ENS LL_RCC_IC6_Enable
6757 * @retval None
6758 */
LL_RCC_IC6_Enable(void)6759 __STATIC_INLINE void LL_RCC_IC6_Enable(void)
6760 {
6761 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC6ENS);
6762 }
6763
6764 /**
6765 * @brief Disable IC6
6766 * @rmtoll DIVENCR IC6ENC LL_RCC_IC6_Disable
6767 * @retval None
6768 */
LL_RCC_IC6_Disable(void)6769 __STATIC_INLINE void LL_RCC_IC6_Disable(void)
6770 {
6771 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC6ENC);
6772 }
6773
6774 /**
6775 * @brief Check if IC6 is enabled
6776 * @rmtoll DIVENR IC6EN LL_RCC_IC6_IsEnabled
6777 * @retval State of bit (1 or 0).
6778 */
LL_RCC_IC6_IsEnabled(void)6779 __STATIC_INLINE uint32_t LL_RCC_IC6_IsEnabled(void)
6780 {
6781 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC6EN) == RCC_DIVENR_IC6EN) ? 1UL : 0UL);
6782 }
6783
6784 /**
6785 * @brief Set the PLL source used as IC6 clock source.
6786 * @rmtoll IC6CFGR IC6SEL LL_RCC_IC6_SetSource
6787 * @param Source parameter can be one of the following values:
6788 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6789 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6790 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6791 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6792 * @retval None
6793 */
LL_RCC_IC6_SetSource(uint32_t Source)6794 __STATIC_INLINE void LL_RCC_IC6_SetSource(uint32_t Source)
6795 {
6796 MODIFY_REG(RCC->IC6CFGR, RCC_IC6CFGR_IC6SEL, Source);
6797 }
6798
6799 /**
6800 * @brief Get the PLL source used as IC6 clock source.
6801 * @rmtoll IC6CFGR IC6SEL LL_RCC_IC6_GetSource
6802 * @retval Returned value can be one of the following values:
6803 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6804 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6805 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6806 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6807 */
LL_RCC_IC6_GetSource(void)6808 __STATIC_INLINE uint32_t LL_RCC_IC6_GetSource(void)
6809 {
6810 return (uint32_t)(READ_BIT(RCC->IC6CFGR, RCC_IC6CFGR_IC6SEL));
6811 }
6812
6813 /**
6814 * @brief Set divider
6815 * @rmtoll IC6CFGR IC6INT LL_RCC_IC6_SetDivider
6816 * @param Divider This parameter can be a value between 1 and 256.
6817 * @retval None
6818 */
LL_RCC_IC6_SetDivider(uint32_t Divider)6819 __STATIC_INLINE void LL_RCC_IC6_SetDivider(uint32_t Divider)
6820 {
6821 MODIFY_REG(RCC->IC6CFGR, RCC_IC6CFGR_IC6INT, (Divider - 1UL) << RCC_IC6CFGR_IC6INT_Pos);
6822 }
6823
6824 /**
6825 * @brief Get IC6 divider
6826 * @rmtoll IC6CFGR IC6INT LL_RCC_IC6_GetDivider
6827 * @retval can be a value between 1 and 256.
6828 */
LL_RCC_IC6_GetDivider(void)6829 __STATIC_INLINE uint32_t LL_RCC_IC6_GetDivider(void)
6830 {
6831 return ((READ_BIT(RCC->IC6CFGR, RCC_IC6CFGR_IC6INT) >> RCC_IC6CFGR_IC6INT_Pos) + 1UL);
6832 }
6833
6834 /**
6835 * @brief Enable IC7
6836 * @rmtoll DIVENSR IC7ENS LL_RCC_IC7_Enable
6837 * @retval None
6838 */
LL_RCC_IC7_Enable(void)6839 __STATIC_INLINE void LL_RCC_IC7_Enable(void)
6840 {
6841 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC7ENS);
6842 }
6843
6844 /**
6845 * @brief Disable IC7
6846 * @rmtoll DIVENCR IC7ENC LL_RCC_IC7_Disable
6847 * @retval None
6848 */
LL_RCC_IC7_Disable(void)6849 __STATIC_INLINE void LL_RCC_IC7_Disable(void)
6850 {
6851 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC7ENC);
6852 }
6853
6854 /**
6855 * @brief Check if IC7 is enabled
6856 * @rmtoll DIVENR IC7EN LL_RCC_IC7_IsEnabled
6857 * @retval State of bit (1 or 0).
6858 */
LL_RCC_IC7_IsEnabled(void)6859 __STATIC_INLINE uint32_t LL_RCC_IC7_IsEnabled(void)
6860 {
6861 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC7EN) == RCC_DIVENR_IC7EN) ? 1UL : 0UL);
6862 }
6863
6864 /**
6865 * @brief Set the PLL source used as IC7 clock source.
6866 * @rmtoll IC7CFGR IC7SEL LL_RCC_IC7_SetSource
6867 * @param Source parameter can be one of the following values:
6868 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6869 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6870 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6871 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6872 * @retval None
6873 */
LL_RCC_IC7_SetSource(uint32_t Source)6874 __STATIC_INLINE void LL_RCC_IC7_SetSource(uint32_t Source)
6875 {
6876 MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL, Source);
6877 }
6878
6879 /**
6880 * @brief Get the PLL source used as IC7 clock source.
6881 * @rmtoll IC7CFGR IC7SEL LL_RCC_IC7_GetSource
6882 * @retval Returned value can be one of the following values:
6883 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6884 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6885 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6886 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6887 */
LL_RCC_IC7_GetSource(void)6888 __STATIC_INLINE uint32_t LL_RCC_IC7_GetSource(void)
6889 {
6890 return (uint32_t)(READ_BIT(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL));
6891 }
6892
6893 /**
6894 * @brief Set divider
6895 * @rmtoll IC7CFGR IC7INT LL_RCC_IC7_SetDivider
6896 * @param Divider This parameter can be a value between 1 and 256.
6897 * @retval None
6898 */
LL_RCC_IC7_SetDivider(uint32_t Divider)6899 __STATIC_INLINE void LL_RCC_IC7_SetDivider(uint32_t Divider)
6900 {
6901 MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7INT, (Divider - 1UL) << RCC_IC7CFGR_IC7INT_Pos);
6902 }
6903
6904 /**
6905 * @brief Get IC7 divider
6906 * @rmtoll IC7CFGR IC7INT LL_RCC_IC7_GetDivider
6907 * @retval can be a value between 1 and 256.
6908 */
LL_RCC_IC7_GetDivider(void)6909 __STATIC_INLINE uint32_t LL_RCC_IC7_GetDivider(void)
6910 {
6911 return ((READ_BIT(RCC->IC7CFGR, RCC_IC7CFGR_IC7INT) >> RCC_IC7CFGR_IC7INT_Pos) + 1UL);
6912 }
6913
6914 /**
6915 * @brief Enable IC8
6916 * @rmtoll DIVENSR IC8ENS LL_RCC_IC8_Enable
6917 * @retval None
6918 */
LL_RCC_IC8_Enable(void)6919 __STATIC_INLINE void LL_RCC_IC8_Enable(void)
6920 {
6921 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC8ENS);
6922 }
6923
6924 /**
6925 * @brief Disable IC8
6926 * @rmtoll DIVENCR IC8ENC LL_RCC_IC8_Disable
6927 * @retval None
6928 */
LL_RCC_IC8_Disable(void)6929 __STATIC_INLINE void LL_RCC_IC8_Disable(void)
6930 {
6931 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC8ENC);
6932 }
6933
6934 /**
6935 * @brief Check if IC8 is enabled
6936 * @rmtoll DIVENR IC8EN LL_RCC_IC8_IsEnabled
6937 * @retval State of bit (1 or 0).
6938 */
LL_RCC_IC8_IsEnabled(void)6939 __STATIC_INLINE uint32_t LL_RCC_IC8_IsEnabled(void)
6940 {
6941 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC8EN) == RCC_DIVENR_IC8EN) ? 1UL : 0UL);
6942 }
6943
6944 /**
6945 * @brief Set the PLL source used as IC8 clock source.
6946 * @rmtoll IC8CFGR IC8SEL LL_RCC_IC8_SetSource
6947 * @param Source parameter can be one of the following values:
6948 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6949 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6950 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6951 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6952 * @retval None
6953 */
LL_RCC_IC8_SetSource(uint32_t Source)6954 __STATIC_INLINE void LL_RCC_IC8_SetSource(uint32_t Source)
6955 {
6956 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL, Source);
6957 }
6958
6959 /**
6960 * @brief Get the PLL source used as IC8 clock source.
6961 * @rmtoll IC8CFGR IC8SEL LL_RCC_IC8_GetSource
6962 * @retval Returned value can be one of the following values:
6963 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
6964 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
6965 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
6966 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
6967 */
LL_RCC_IC8_GetSource(void)6968 __STATIC_INLINE uint32_t LL_RCC_IC8_GetSource(void)
6969 {
6970 return (uint32_t)(READ_BIT(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL));
6971 }
6972
6973 /**
6974 * @brief Set divider
6975 * @rmtoll IC8CFGR IC8INT LL_RCC_IC8_SetDivider
6976 * @param Divider This parameter can be a value between 1 and 256.
6977 * @retval None
6978 */
LL_RCC_IC8_SetDivider(uint32_t Divider)6979 __STATIC_INLINE void LL_RCC_IC8_SetDivider(uint32_t Divider)
6980 {
6981 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8INT, (Divider - 1UL) << RCC_IC8CFGR_IC8INT_Pos);
6982 }
6983
6984 /**
6985 * @brief Get IC8 divider
6986 * @rmtoll IC8CFGR IC8INT LL_RCC_IC8_GetDivider
6987 * @retval can be a value between 1 and 256.
6988 */
LL_RCC_IC8_GetDivider(void)6989 __STATIC_INLINE uint32_t LL_RCC_IC8_GetDivider(void)
6990 {
6991 return ((READ_BIT(RCC->IC8CFGR, RCC_IC8CFGR_IC8INT) >> RCC_IC8CFGR_IC8INT_Pos) + 1UL);
6992 }
6993
6994 /**
6995 * @brief Enable IC9
6996 * @rmtoll DIVENSR IC9ENS LL_RCC_IC9_Enable
6997 * @retval None
6998 */
LL_RCC_IC9_Enable(void)6999 __STATIC_INLINE void LL_RCC_IC9_Enable(void)
7000 {
7001 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC9ENS);
7002 }
7003
7004 /**
7005 * @brief Disable IC9
7006 * @rmtoll DIVENCR IC9ENC LL_RCC_IC9_Disable
7007 * @retval None
7008 */
LL_RCC_IC9_Disable(void)7009 __STATIC_INLINE void LL_RCC_IC9_Disable(void)
7010 {
7011 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC9ENC);
7012 }
7013
7014 /**
7015 * @brief Check if IC9 is enabled
7016 * @rmtoll DIVENR IC9EN LL_RCC_IC9_IsEnabled
7017 * @retval State of bit (1 or 0).
7018 */
LL_RCC_IC9_IsEnabled(void)7019 __STATIC_INLINE uint32_t LL_RCC_IC9_IsEnabled(void)
7020 {
7021 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC9EN) == RCC_DIVENR_IC9EN) ? 1UL : 0UL);
7022 }
7023
7024 /**
7025 * @brief Set the PLL source used as IC9 clock source.
7026 * @rmtoll IC9CFGR IC9SEL LL_RCC_IC9_SetSource
7027 * @param Source parameter can be one of the following values:
7028 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7029 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7030 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7031 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7032 * @retval None
7033 */
LL_RCC_IC9_SetSource(uint32_t Source)7034 __STATIC_INLINE void LL_RCC_IC9_SetSource(uint32_t Source)
7035 {
7036 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL, Source);
7037 }
7038
7039 /**
7040 * @brief Get the PLL source used as IC9 clock source.
7041 * @rmtoll IC9CFGR IC9SEL LL_RCC_IC9_GetSource
7042 * @retval Returned value can be one of the following values:
7043 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7044 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7045 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7046 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7047 */
LL_RCC_IC9_GetSource(void)7048 __STATIC_INLINE uint32_t LL_RCC_IC9_GetSource(void)
7049 {
7050 return (uint32_t)(READ_BIT(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL));
7051 }
7052
7053 /**
7054 * @brief Set divider
7055 * @rmtoll IC9CFGR IC9INT LL_RCC_IC9_SetDivider
7056 * @param Divider This parameter can be a value between 1 and 256.
7057 * @retval None
7058 */
LL_RCC_IC9_SetDivider(uint32_t Divider)7059 __STATIC_INLINE void LL_RCC_IC9_SetDivider(uint32_t Divider)
7060 {
7061 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9INT, (Divider - 1UL) << RCC_IC9CFGR_IC9INT_Pos);
7062 }
7063
7064 /**
7065 * @brief Get IC9 divider
7066 * @rmtoll IC9CFGR IC9INT LL_RCC_IC9_GetDivider
7067 * @retval can be a value between 1 and 256.
7068 */
LL_RCC_IC9_GetDivider(void)7069 __STATIC_INLINE uint32_t LL_RCC_IC9_GetDivider(void)
7070 {
7071 return ((READ_BIT(RCC->IC9CFGR, RCC_IC9CFGR_IC9INT) >> RCC_IC9CFGR_IC9INT_Pos) + 1UL);
7072 }
7073
7074 /**
7075 * @brief Enable IC10
7076 * @rmtoll DIVENSR IC10ENS LL_RCC_IC10_Enable
7077 * @retval None
7078 */
LL_RCC_IC10_Enable(void)7079 __STATIC_INLINE void LL_RCC_IC10_Enable(void)
7080 {
7081 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC10ENS);
7082 }
7083
7084 /**
7085 * @brief Disable IC10
7086 * @rmtoll DIVENCR IC10ENC LL_RCC_IC10_Disable
7087 * @retval None
7088 */
LL_RCC_IC10_Disable(void)7089 __STATIC_INLINE void LL_RCC_IC10_Disable(void)
7090 {
7091 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC10ENC);
7092 }
7093
7094 /**
7095 * @brief Check if IC10 is enabled
7096 * @rmtoll DIVENR IC10EN LL_RCC_IC10_IsEnabled
7097 * @retval State of bit (1 or 0).
7098 */
LL_RCC_IC10_IsEnabled(void)7099 __STATIC_INLINE uint32_t LL_RCC_IC10_IsEnabled(void)
7100 {
7101 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC10EN) == RCC_DIVENR_IC10EN) ? 1UL : 0UL);
7102 }
7103
7104 /**
7105 * @brief Set the PLL source used as IC10 clock source.
7106 * @rmtoll IC10CFGR IC10SEL LL_RCC_IC10_SetSource
7107 * @param Source parameter can be one of the following values:
7108 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7109 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7110 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7111 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7112 * @retval None
7113 */
LL_RCC_IC10_SetSource(uint32_t Source)7114 __STATIC_INLINE void LL_RCC_IC10_SetSource(uint32_t Source)
7115 {
7116 MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL, Source);
7117 }
7118
7119 /**
7120 * @brief Get the PLL source used as IC10 clock source.
7121 * @rmtoll IC10CFGR IC10SEL LL_RCC_IC10_GetSource
7122 * @retval Returned value can be one of the following values:
7123 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7124 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7125 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7126 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7127 */
LL_RCC_IC10_GetSource(void)7128 __STATIC_INLINE uint32_t LL_RCC_IC10_GetSource(void)
7129 {
7130 return (uint32_t)(READ_BIT(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL));
7131 }
7132
7133 /**
7134 * @brief Set divider
7135 * @rmtoll IC10CFGR IC10INT LL_RCC_IC10_SetDivider
7136 * @param Divider This parameter can be a value between 1 and 256.
7137 * @retval None
7138 */
LL_RCC_IC10_SetDivider(uint32_t Divider)7139 __STATIC_INLINE void LL_RCC_IC10_SetDivider(uint32_t Divider)
7140 {
7141 MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10INT, (Divider - 1UL) << RCC_IC10CFGR_IC10INT_Pos);
7142 }
7143
7144 /**
7145 * @brief Get IC10 divider
7146 * @rmtoll IC10CFGR IC10INT LL_RCC_IC10_GetDivider
7147 * @retval can be a value between 1 and 256.
7148 */
LL_RCC_IC10_GetDivider(void)7149 __STATIC_INLINE uint32_t LL_RCC_IC10_GetDivider(void)
7150 {
7151 return ((READ_BIT(RCC->IC10CFGR, RCC_IC10CFGR_IC10INT) >> RCC_IC10CFGR_IC10INT_Pos) + 1UL);
7152 }
7153
7154 /**
7155 * @brief Enable IC11
7156 * @rmtoll DIVENSR IC11ENS LL_RCC_IC11_Enable
7157 * @retval None
7158 */
LL_RCC_IC11_Enable(void)7159 __STATIC_INLINE void LL_RCC_IC11_Enable(void)
7160 {
7161 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC11ENS);
7162 }
7163
7164 /**
7165 * @brief Disable IC11
7166 * @rmtoll DIVENCR IC11ENC LL_RCC_IC11_Disable
7167 * @retval None
7168 */
LL_RCC_IC11_Disable(void)7169 __STATIC_INLINE void LL_RCC_IC11_Disable(void)
7170 {
7171 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC11ENC);
7172 }
7173
7174 /**
7175 * @brief Check if IC11 is enabled
7176 * @rmtoll DIVENR IC11EN LL_RCC_IC11_IsEnabled
7177 * @retval State of bit (1 or 0).
7178 */
LL_RCC_IC11_IsEnabled(void)7179 __STATIC_INLINE uint32_t LL_RCC_IC11_IsEnabled(void)
7180 {
7181 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC11EN) == RCC_DIVENR_IC11EN) ? 1UL : 0UL);
7182 }
7183
7184 /**
7185 * @brief Set the PLL source used as IC11 clock source.
7186 * @rmtoll IC11CFGR IC11SEL LL_RCC_IC11_SetSource
7187 * @param Source parameter can be one of the following values:
7188 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7189 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7190 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7191 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7192 * @retval None
7193 */
LL_RCC_IC11_SetSource(uint32_t Source)7194 __STATIC_INLINE void LL_RCC_IC11_SetSource(uint32_t Source)
7195 {
7196 MODIFY_REG(RCC->IC11CFGR, RCC_IC11CFGR_IC11SEL, Source);
7197 }
7198
7199 /**
7200 * @brief Get the PLL source used as IC11 clock source.
7201 * @rmtoll IC11CFGR IC11SEL LL_RCC_IC11_GetSource
7202 * @retval Returned value can be one of the following values:
7203 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7204 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7205 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7206 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7207 */
LL_RCC_IC11_GetSource(void)7208 __STATIC_INLINE uint32_t LL_RCC_IC11_GetSource(void)
7209 {
7210 return (uint32_t)(READ_BIT(RCC->IC11CFGR, RCC_IC11CFGR_IC11SEL));
7211 }
7212
7213 /**
7214 * @brief Set divider
7215 * @rmtoll IC11CFGR IC11INT LL_RCC_IC11_SetDivider
7216 * @param Divider This parameter can be a value between 1 and 256.
7217 * @retval None
7218 */
LL_RCC_IC11_SetDivider(uint32_t Divider)7219 __STATIC_INLINE void LL_RCC_IC11_SetDivider(uint32_t Divider)
7220 {
7221 MODIFY_REG(RCC->IC11CFGR, RCC_IC11CFGR_IC11INT, (Divider - 1UL) << RCC_IC11CFGR_IC11INT_Pos);
7222 }
7223
7224 /**
7225 * @brief Get IC11 divider
7226 * @rmtoll IC11CFGR IC11INT LL_RCC_IC11_GetDivider
7227 * @retval can be a value between 1 and 256.
7228 */
LL_RCC_IC11_GetDivider(void)7229 __STATIC_INLINE uint32_t LL_RCC_IC11_GetDivider(void)
7230 {
7231 return ((READ_BIT(RCC->IC11CFGR, RCC_IC11CFGR_IC11INT) >> RCC_IC11CFGR_IC11INT_Pos) + 1UL);
7232 }
7233
7234 /**
7235 * @brief Enable IC12
7236 * @rmtoll DIVENSR IC12ENS LL_RCC_IC12_Enable
7237 * @retval None
7238 */
LL_RCC_IC12_Enable(void)7239 __STATIC_INLINE void LL_RCC_IC12_Enable(void)
7240 {
7241 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC12ENS);
7242 }
7243
7244 /**
7245 * @brief Disable IC12
7246 * @rmtoll DIVENCR IC12ENC LL_RCC_IC12_Disable
7247 * @retval None
7248 */
LL_RCC_IC12_Disable(void)7249 __STATIC_INLINE void LL_RCC_IC12_Disable(void)
7250 {
7251 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC12ENC);
7252 }
7253
7254 /**
7255 * @brief Check if IC12 is enabled
7256 * @rmtoll DIVENR IC12EN LL_RCC_IC12_IsEnabled
7257 * @retval State of bit (1 or 0).
7258 */
LL_RCC_IC12_IsEnabled(void)7259 __STATIC_INLINE uint32_t LL_RCC_IC12_IsEnabled(void)
7260 {
7261 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC12EN) == RCC_DIVENR_IC12EN) ? 1UL : 0UL);
7262 }
7263
7264 /**
7265 * @brief Set the PLL source used as IC12 clock source.
7266 * @rmtoll IC12CFGR IC12SEL LL_RCC_IC12_SetSource
7267 * @param Source parameter can be one of the following values:
7268 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7269 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7270 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7271 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7272 * @retval None
7273 */
LL_RCC_IC12_SetSource(uint32_t Source)7274 __STATIC_INLINE void LL_RCC_IC12_SetSource(uint32_t Source)
7275 {
7276 MODIFY_REG(RCC->IC12CFGR, RCC_IC12CFGR_IC12SEL, Source);
7277 }
7278
7279 /**
7280 * @brief Get the PLL source used as IC12 clock source.
7281 * @rmtoll IC12CFGR IC12SEL LL_RCC_IC12_GetSource
7282 * @retval Returned value can be one of the following values:
7283 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7284 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7285 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7286 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7287 */
LL_RCC_IC12_GetSource(void)7288 __STATIC_INLINE uint32_t LL_RCC_IC12_GetSource(void)
7289 {
7290 return (uint32_t)(READ_BIT(RCC->IC12CFGR, RCC_IC12CFGR_IC12SEL));
7291 }
7292
7293 /**
7294 * @brief Set divider
7295 * @rmtoll IC12CFGR IC12INT LL_RCC_IC12_SetDivider
7296 * @param Divider This parameter can be a value between 1 and 256.
7297 * @retval None
7298 */
LL_RCC_IC12_SetDivider(uint32_t Divider)7299 __STATIC_INLINE void LL_RCC_IC12_SetDivider(uint32_t Divider)
7300 {
7301 MODIFY_REG(RCC->IC12CFGR, RCC_IC12CFGR_IC12INT, (Divider - 1UL) << RCC_IC12CFGR_IC12INT_Pos);
7302 }
7303
7304 /**
7305 * @brief Get IC12 divider
7306 * @rmtoll IC12CFGR IC12INT LL_RCC_IC12_GetDivider
7307 * @retval can be a value between 1 and 256.
7308 */
LL_RCC_IC12_GetDivider(void)7309 __STATIC_INLINE uint32_t LL_RCC_IC12_GetDivider(void)
7310 {
7311 return ((READ_BIT(RCC->IC12CFGR, RCC_IC12CFGR_IC12INT) >> RCC_IC12CFGR_IC12INT_Pos) + 1UL);
7312 }
7313
7314 /**
7315 * @brief Enable IC13
7316 * @rmtoll DIVENSR IC13ENS LL_RCC_IC13_Enable
7317 * @retval None
7318 */
LL_RCC_IC13_Enable(void)7319 __STATIC_INLINE void LL_RCC_IC13_Enable(void)
7320 {
7321 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC13ENS);
7322 }
7323
7324 /**
7325 * @brief Disable IC13
7326 * @rmtoll DIVENCR IC13ENC LL_RCC_IC13_Disable
7327 * @retval None
7328 */
LL_RCC_IC13_Disable(void)7329 __STATIC_INLINE void LL_RCC_IC13_Disable(void)
7330 {
7331 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC13ENC);
7332 }
7333
7334 /**
7335 * @brief Check if IC13 is enabled
7336 * @rmtoll DIVENR IC13EN LL_RCC_IC13_IsEnabled
7337 * @retval State of bit (1 or 0).
7338 */
LL_RCC_IC13_IsEnabled(void)7339 __STATIC_INLINE uint32_t LL_RCC_IC13_IsEnabled(void)
7340 {
7341 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC13EN) == RCC_DIVENR_IC13EN) ? 1UL : 0UL);
7342 }
7343
7344 /**
7345 * @brief Set the PLL source used as IC13 clock source.
7346 * @rmtoll IC13CFGR IC13SEL LL_RCC_IC13_SetSource
7347 * @param Source parameter can be one of the following values:
7348 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7349 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7350 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7351 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7352 * @retval None
7353 */
LL_RCC_IC13_SetSource(uint32_t Source)7354 __STATIC_INLINE void LL_RCC_IC13_SetSource(uint32_t Source)
7355 {
7356 MODIFY_REG(RCC->IC13CFGR, RCC_IC13CFGR_IC13SEL, Source);
7357 }
7358
7359 /**
7360 * @brief Get the PLL source used as IC13 clock source.
7361 * @rmtoll IC13CFGR IC13SEL LL_RCC_IC13_GetSource
7362 * @retval Returned value can be one of the following values:
7363 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7364 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7365 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7366 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7367 */
LL_RCC_IC13_GetSource(void)7368 __STATIC_INLINE uint32_t LL_RCC_IC13_GetSource(void)
7369 {
7370 return (uint32_t)(READ_BIT(RCC->IC13CFGR, RCC_IC13CFGR_IC13SEL));
7371 }
7372
7373 /**
7374 * @brief Set divider
7375 * @rmtoll IC13CFGR IC13INT LL_RCC_IC13_SetDivider
7376 * @param Divider This parameter can be a value between 1 and 256.
7377 * @retval None
7378 */
LL_RCC_IC13_SetDivider(uint32_t Divider)7379 __STATIC_INLINE void LL_RCC_IC13_SetDivider(uint32_t Divider)
7380 {
7381 MODIFY_REG(RCC->IC13CFGR, RCC_IC13CFGR_IC13INT, (Divider - 1UL) << RCC_IC13CFGR_IC13INT_Pos);
7382 }
7383
7384 /**
7385 * @brief Get IC13 divider
7386 * @rmtoll IC13CFGR IC13INT LL_RCC_IC13_GetDivider
7387 * @retval can be a value between 1 and 256.
7388 */
LL_RCC_IC13_GetDivider(void)7389 __STATIC_INLINE uint32_t LL_RCC_IC13_GetDivider(void)
7390 {
7391 return ((READ_BIT(RCC->IC13CFGR, RCC_IC13CFGR_IC13INT) >> RCC_IC13CFGR_IC13INT_Pos) + 1UL);
7392 }
7393
7394 /**
7395 * @brief Enable IC14
7396 * @rmtoll DIVENSR IC14ENS LL_RCC_IC14_Enable
7397 * @retval None
7398 */
LL_RCC_IC14_Enable(void)7399 __STATIC_INLINE void LL_RCC_IC14_Enable(void)
7400 {
7401 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC14ENS);
7402 }
7403
7404 /**
7405 * @brief Disable IC14
7406 * @rmtoll DIVENCR IC14ENC LL_RCC_IC14_Disable
7407 * @retval None
7408 */
LL_RCC_IC14_Disable(void)7409 __STATIC_INLINE void LL_RCC_IC14_Disable(void)
7410 {
7411 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC14ENC);
7412 }
7413
7414 /**
7415 * @brief Check if IC14 is enabled
7416 * @rmtoll DIVENR IC14EN LL_RCC_IC14_IsEnabled
7417 * @retval State of bit (1 or 0).
7418 */
LL_RCC_IC14_IsEnabled(void)7419 __STATIC_INLINE uint32_t LL_RCC_IC14_IsEnabled(void)
7420 {
7421 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC14EN) == RCC_DIVENR_IC14EN) ? 1UL : 0UL);
7422 }
7423
7424 /**
7425 * @brief Set the PLL source used as IC14 clock source.
7426 * @rmtoll IC14CFGR IC14SEL LL_RCC_IC14_SetSource
7427 * @param Source parameter can be one of the following values:
7428 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7429 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7430 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7431 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7432 * @retval None
7433 */
LL_RCC_IC14_SetSource(uint32_t Source)7434 __STATIC_INLINE void LL_RCC_IC14_SetSource(uint32_t Source)
7435 {
7436 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL, Source);
7437 }
7438
7439 /**
7440 * @brief Get the PLL source used as IC14 clock source.
7441 * @rmtoll IC14CFGR IC14SEL LL_RCC_IC14_GetSource
7442 * @retval Returned value can be one of the following values:
7443 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7444 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7445 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7446 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7447 */
LL_RCC_IC14_GetSource(void)7448 __STATIC_INLINE uint32_t LL_RCC_IC14_GetSource(void)
7449 {
7450 return (uint32_t)(READ_BIT(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL));
7451 }
7452
7453 /**
7454 * @brief Set divider
7455 * @rmtoll IC14CFGR IC14INT LL_RCC_IC14_SetDivider
7456 * @param Divider This parameter can be a value between 1 and 256.
7457 * @retval None
7458 */
LL_RCC_IC14_SetDivider(uint32_t Divider)7459 __STATIC_INLINE void LL_RCC_IC14_SetDivider(uint32_t Divider)
7460 {
7461 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14INT, (Divider - 1UL) << RCC_IC14CFGR_IC14INT_Pos);
7462 }
7463
7464 /**
7465 * @brief Get IC14 divider
7466 * @rmtoll IC14CFGR IC14INT LL_RCC_IC14_GetDivider
7467 * @retval can be a value between 1 and 256.
7468 */
LL_RCC_IC14_GetDivider(void)7469 __STATIC_INLINE uint32_t LL_RCC_IC14_GetDivider(void)
7470 {
7471 return ((READ_BIT(RCC->IC14CFGR, RCC_IC14CFGR_IC14INT) >> RCC_IC14CFGR_IC14INT_Pos) + 1UL);
7472 }
7473
7474 /**
7475 * @brief Enable IC15
7476 * @rmtoll DIVENSR IC15ENS LL_RCC_IC15_Enable
7477 * @retval None
7478 */
LL_RCC_IC15_Enable(void)7479 __STATIC_INLINE void LL_RCC_IC15_Enable(void)
7480 {
7481 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC15ENS);
7482 }
7483
7484 /**
7485 * @brief Disable IC15
7486 * @rmtoll DIVENCR IC15ENC LL_RCC_IC15_Disable
7487 * @retval None
7488 */
LL_RCC_IC15_Disable(void)7489 __STATIC_INLINE void LL_RCC_IC15_Disable(void)
7490 {
7491 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC15ENC);
7492 }
7493
7494 /**
7495 * @brief Check if IC15 is enabled
7496 * @rmtoll DIVENR IC15EN LL_RCC_IC15_IsEnabled
7497 * @retval State of bit (1 or 0).
7498 */
LL_RCC_IC15_IsEnabled(void)7499 __STATIC_INLINE uint32_t LL_RCC_IC15_IsEnabled(void)
7500 {
7501 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC15EN) == RCC_DIVENR_IC15EN) ? 1UL : 0UL);
7502 }
7503
7504 /**
7505 * @brief Set the PLL source used as IC15 clock source.
7506 * @rmtoll IC15CFGR IC15SEL LL_RCC_IC15_SetSource
7507 * @param Source parameter can be one of the following values:
7508 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7509 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7510 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7511 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7512 * @retval None
7513 */
LL_RCC_IC15_SetSource(uint32_t Source)7514 __STATIC_INLINE void LL_RCC_IC15_SetSource(uint32_t Source)
7515 {
7516 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL, Source);
7517 }
7518
7519 /**
7520 * @brief Get the PLL source used as IC15 clock source.
7521 * @rmtoll IC15CFGR IC15SEL LL_RCC_IC15_GetSource
7522 * @retval Returned value can be one of the following values:
7523 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7524 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7525 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7526 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7527 */
LL_RCC_IC15_GetSource(void)7528 __STATIC_INLINE uint32_t LL_RCC_IC15_GetSource(void)
7529 {
7530 return (uint32_t)(READ_BIT(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL));
7531 }
7532
7533 /**
7534 * @brief Set divider
7535 * @rmtoll IC15CFGR IC15INT LL_RCC_IC15_SetDivider
7536 * @param Divider This parameter can be a value between 1 and 256.
7537 * @retval None
7538 */
LL_RCC_IC15_SetDivider(uint32_t Divider)7539 __STATIC_INLINE void LL_RCC_IC15_SetDivider(uint32_t Divider)
7540 {
7541 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15INT, (Divider - 1UL) << RCC_IC15CFGR_IC15INT_Pos);
7542 }
7543
7544 /**
7545 * @brief Get IC15 divider
7546 * @rmtoll IC15CFGR IC15INT LL_RCC_IC15_GetDivider
7547 * @retval can be a value between 1 and 256.
7548 */
LL_RCC_IC15_GetDivider(void)7549 __STATIC_INLINE uint32_t LL_RCC_IC15_GetDivider(void)
7550 {
7551 return ((READ_BIT(RCC->IC15CFGR, RCC_IC15CFGR_IC15INT) >> RCC_IC15CFGR_IC15INT_Pos) + 1UL);
7552 }
7553
7554 /**
7555 * @brief Enable IC16
7556 * @rmtoll DIVENSR IC16ENS LL_RCC_IC16_Enable
7557 * @retval None
7558 */
LL_RCC_IC16_Enable(void)7559 __STATIC_INLINE void LL_RCC_IC16_Enable(void)
7560 {
7561 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC16ENS);
7562 }
7563
7564 /**
7565 * @brief Disable IC16
7566 * @rmtoll DIVENCR IC16ENC LL_RCC_IC16_Disable
7567 * @retval None
7568 */
LL_RCC_IC16_Disable(void)7569 __STATIC_INLINE void LL_RCC_IC16_Disable(void)
7570 {
7571 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC16ENC);
7572 }
7573
7574 /**
7575 * @brief Check if IC16 is enabled
7576 * @rmtoll DIVENR IC16EN LL_RCC_IC16_IsEnabled
7577 * @retval State of bit (1 or 0).
7578 */
LL_RCC_IC16_IsEnabled(void)7579 __STATIC_INLINE uint32_t LL_RCC_IC16_IsEnabled(void)
7580 {
7581 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC16EN) == RCC_DIVENR_IC16EN) ? 1UL : 0UL);
7582 }
7583
7584 /**
7585 * @brief Set the PLL source used as IC16 clock source.
7586 * @rmtoll IC16CFGR IC16SEL LL_RCC_IC16_SetSource
7587 * @param Source parameter can be one of the following values:
7588 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7589 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7590 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7591 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7592 * @retval None
7593 */
LL_RCC_IC16_SetSource(uint32_t Source)7594 __STATIC_INLINE void LL_RCC_IC16_SetSource(uint32_t Source)
7595 {
7596 MODIFY_REG(RCC->IC16CFGR, RCC_IC16CFGR_IC16SEL, Source);
7597 }
7598
7599 /**
7600 * @brief Get the PLL source used as IC16 clock source.
7601 * @rmtoll IC16CFGR IC16SEL LL_RCC_IC16_GetSource
7602 * @retval Returned value can be one of the following values:
7603 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7604 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7605 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7606 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7607 */
LL_RCC_IC16_GetSource(void)7608 __STATIC_INLINE uint32_t LL_RCC_IC16_GetSource(void)
7609 {
7610 return (uint32_t)(READ_BIT(RCC->IC16CFGR, RCC_IC16CFGR_IC16SEL));
7611 }
7612
7613 /**
7614 * @brief Set divider
7615 * @rmtoll IC16CFGR IC16INT LL_RCC_IC16_SetDivider
7616 * @param Divider This parameter can be a value between 1 and 256.
7617 * @retval None
7618 */
LL_RCC_IC16_SetDivider(uint32_t Divider)7619 __STATIC_INLINE void LL_RCC_IC16_SetDivider(uint32_t Divider)
7620 {
7621 MODIFY_REG(RCC->IC16CFGR, RCC_IC16CFGR_IC16INT, (Divider - 1UL) << RCC_IC16CFGR_IC16INT_Pos);
7622 }
7623
7624 /**
7625 * @brief Get IC16 divider
7626 * @rmtoll IC16CFGR IC16INT LL_RCC_IC16_GetDivider
7627 * @retval can be a value between 1 and 256.
7628 */
LL_RCC_IC16_GetDivider(void)7629 __STATIC_INLINE uint32_t LL_RCC_IC16_GetDivider(void)
7630 {
7631 return ((READ_BIT(RCC->IC16CFGR, RCC_IC16CFGR_IC16INT) >> RCC_IC16CFGR_IC16INT_Pos) + 1UL);
7632 }
7633
7634 /**
7635 * @brief Enable IC17
7636 * @rmtoll DIVENSR IC17ENS LL_RCC_IC17_Enable
7637 * @retval None
7638 */
LL_RCC_IC17_Enable(void)7639 __STATIC_INLINE void LL_RCC_IC17_Enable(void)
7640 {
7641 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC17ENS);
7642 }
7643
7644 /**
7645 * @brief Disable IC17
7646 * @rmtoll DIVENCR IC17ENC LL_RCC_IC17_Disable
7647 * @retval None
7648 */
LL_RCC_IC17_Disable(void)7649 __STATIC_INLINE void LL_RCC_IC17_Disable(void)
7650 {
7651 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC17ENC);
7652 }
7653
7654 /**
7655 * @brief Check if IC17 is enabled
7656 * @rmtoll DIVENR IC17EN LL_RCC_IC17_IsEnabled
7657 * @retval State of bit (1 or 0).
7658 */
LL_RCC_IC17_IsEnabled(void)7659 __STATIC_INLINE uint32_t LL_RCC_IC17_IsEnabled(void)
7660 {
7661 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC17EN) == RCC_DIVENR_IC17EN) ? 1UL : 0UL);
7662 }
7663
7664 /**
7665 * @brief Set the PLL source used as IC17 clock source.
7666 * @rmtoll IC17CFGR IC17SEL LL_RCC_IC17_SetSource
7667 * @param Source parameter can be one of the following values:
7668 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7669 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7670 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7671 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7672 * @retval None
7673 */
LL_RCC_IC17_SetSource(uint32_t Source)7674 __STATIC_INLINE void LL_RCC_IC17_SetSource(uint32_t Source)
7675 {
7676 MODIFY_REG(RCC->IC17CFGR, RCC_IC17CFGR_IC17SEL, Source);
7677 }
7678
7679 /**
7680 * @brief Get the PLL source used as IC17 clock source.
7681 * @rmtoll IC17CFGR IC17SEL LL_RCC_IC17_GetSource
7682 * @retval Returned value can be one of the following values:
7683 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7684 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7685 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7686 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7687 */
LL_RCC_IC17_GetSource(void)7688 __STATIC_INLINE uint32_t LL_RCC_IC17_GetSource(void)
7689 {
7690 return (uint32_t)(READ_BIT(RCC->IC17CFGR, RCC_IC17CFGR_IC17SEL));
7691 }
7692
7693 /**
7694 * @brief Set divider
7695 * @rmtoll IC17CFGR IC17INT LL_RCC_IC17_SetDivider
7696 * @param Divider This parameter can be a value between 1 and 256.
7697 * @retval None
7698 */
LL_RCC_IC17_SetDivider(uint32_t Divider)7699 __STATIC_INLINE void LL_RCC_IC17_SetDivider(uint32_t Divider)
7700 {
7701 MODIFY_REG(RCC->IC17CFGR, RCC_IC17CFGR_IC17INT, (Divider - 1UL) << RCC_IC17CFGR_IC17INT_Pos);
7702 }
7703
7704 /**
7705 * @brief Get IC17 divider
7706 * @rmtoll IC17CFGR IC17INT LL_RCC_IC17_GetDivider
7707 * @retval can be a value between 1 and 256.
7708 */
LL_RCC_IC17_GetDivider(void)7709 __STATIC_INLINE uint32_t LL_RCC_IC17_GetDivider(void)
7710 {
7711 return ((READ_BIT(RCC->IC17CFGR, RCC_IC17CFGR_IC17INT) >> RCC_IC17CFGR_IC17INT_Pos) + 1UL);
7712 }
7713
7714 /**
7715 * @brief Enable IC18
7716 * @rmtoll DIVENSR IC18ENS LL_RCC_IC18_Enable
7717 * @retval None
7718 */
LL_RCC_IC18_Enable(void)7719 __STATIC_INLINE void LL_RCC_IC18_Enable(void)
7720 {
7721 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC18ENS);
7722 }
7723
7724 /**
7725 * @brief Disable IC18
7726 * @rmtoll DIVENCR IC18ENC LL_RCC_IC18_Disable
7727 * @retval None
7728 */
LL_RCC_IC18_Disable(void)7729 __STATIC_INLINE void LL_RCC_IC18_Disable(void)
7730 {
7731 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC18ENC);
7732 }
7733
7734 /**
7735 * @brief Check if IC18 is enabled
7736 * @rmtoll DIVENR IC18EN LL_RCC_IC18_IsEnabled
7737 * @retval State of bit (1 or 0).
7738 */
LL_RCC_IC18_IsEnabled(void)7739 __STATIC_INLINE uint32_t LL_RCC_IC18_IsEnabled(void)
7740 {
7741 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC18EN) == RCC_DIVENR_IC18EN) ? 1UL : 0UL);
7742 }
7743
7744 /**
7745 * @brief Set the PLL source used as IC18 clock source.
7746 * @rmtoll IC18CFGR IC18SEL LL_RCC_IC18_SetSource
7747 * @param Source parameter can be one of the following values:
7748 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7749 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7750 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7751 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7752 * @retval None
7753 */
LL_RCC_IC18_SetSource(uint32_t Source)7754 __STATIC_INLINE void LL_RCC_IC18_SetSource(uint32_t Source)
7755 {
7756 MODIFY_REG(RCC->IC18CFGR, RCC_IC18CFGR_IC18SEL, Source);
7757 }
7758
7759 /**
7760 * @brief Get the PLL source used as IC18 clock source.
7761 * @rmtoll IC18CFGR IC18SEL LL_RCC_IC18_GetSource
7762 * @retval Returned value can be one of the following values:
7763 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7764 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7765 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7766 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7767 */
LL_RCC_IC18_GetSource(void)7768 __STATIC_INLINE uint32_t LL_RCC_IC18_GetSource(void)
7769 {
7770 return (uint32_t)(READ_BIT(RCC->IC18CFGR, RCC_IC18CFGR_IC18SEL));
7771 }
7772
7773 /**
7774 * @brief Set divider
7775 * @rmtoll IC18CFGR IC18INT LL_RCC_IC18_SetDivider
7776 * @param Divider This parameter can be a value between 1 and 256.
7777 * @retval None
7778 */
LL_RCC_IC18_SetDivider(uint32_t Divider)7779 __STATIC_INLINE void LL_RCC_IC18_SetDivider(uint32_t Divider)
7780 {
7781 MODIFY_REG(RCC->IC18CFGR, RCC_IC18CFGR_IC18INT, (Divider - 1UL) << RCC_IC18CFGR_IC18INT_Pos);
7782 }
7783
7784 /**
7785 * @brief Get IC18 divider
7786 * @rmtoll IC18CFGR IC18INT LL_RCC_IC18_GetDivider
7787 * @retval can be a value between 1 and 256.
7788 */
LL_RCC_IC18_GetDivider(void)7789 __STATIC_INLINE uint32_t LL_RCC_IC18_GetDivider(void)
7790 {
7791 return ((READ_BIT(RCC->IC18CFGR, RCC_IC18CFGR_IC18INT) >> RCC_IC18CFGR_IC18INT_Pos) + 1UL);
7792 }
7793
7794 /**
7795 * @brief Enable IC19
7796 * @rmtoll DIVENSR IC19ENS LL_RCC_IC19_Enable
7797 * @retval None
7798 */
LL_RCC_IC19_Enable(void)7799 __STATIC_INLINE void LL_RCC_IC19_Enable(void)
7800 {
7801 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC19ENS);
7802 }
7803
7804 /**
7805 * @brief Disable IC19
7806 * @rmtoll DIVENCR IC19ENC LL_RCC_IC19_Disable
7807 * @retval None
7808 */
LL_RCC_IC19_Disable(void)7809 __STATIC_INLINE void LL_RCC_IC19_Disable(void)
7810 {
7811 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC19ENC);
7812 }
7813
7814 /**
7815 * @brief Check if IC19 is enabled
7816 * @rmtoll DIVENR IC19EN LL_RCC_IC19_IsEnabled
7817 * @retval State of bit (1 or 0).
7818 */
LL_RCC_IC19_IsEnabled(void)7819 __STATIC_INLINE uint32_t LL_RCC_IC19_IsEnabled(void)
7820 {
7821 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC19EN) == RCC_DIVENR_IC19EN) ? 1UL : 0UL);
7822 }
7823
7824 /**
7825 * @brief Set the PLL source used as IC19 clock source.
7826 * @rmtoll IC19CFGR IC19SEL LL_RCC_IC19_SetSource
7827 * @param Source parameter can be one of the following values:
7828 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7829 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7830 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7831 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7832 * @retval None
7833 */
LL_RCC_IC19_SetSource(uint32_t Source)7834 __STATIC_INLINE void LL_RCC_IC19_SetSource(uint32_t Source)
7835 {
7836 MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL, Source);
7837 }
7838
7839 /**
7840 * @brief Get the PLL source used as IC19 clock source.
7841 * @rmtoll IC19CFGR IC19SEL LL_RCC_IC19_GetSource
7842 * @retval Returned value can be one of the following values:
7843 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7844 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7845 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7846 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7847 */
LL_RCC_IC19_GetSource(void)7848 __STATIC_INLINE uint32_t LL_RCC_IC19_GetSource(void)
7849 {
7850 return (uint32_t)(READ_BIT(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL));
7851 }
7852
7853 /**
7854 * @brief Set divider
7855 * @rmtoll IC19CFGR IC19INT LL_RCC_IC19_SetDivider
7856 * @param Divider This parameter can be a value between 1 and 256.
7857 * @retval None
7858 */
LL_RCC_IC19_SetDivider(uint32_t Divider)7859 __STATIC_INLINE void LL_RCC_IC19_SetDivider(uint32_t Divider)
7860 {
7861 MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19INT, (Divider - 1UL) << RCC_IC19CFGR_IC19INT_Pos);
7862 }
7863
7864 /**
7865 * @brief Get IC19 divider
7866 * @rmtoll IC19CFGR IC19INT LL_RCC_IC19_GetDivider
7867 * @retval can be a value between 1 and 256.
7868 */
LL_RCC_IC19_GetDivider(void)7869 __STATIC_INLINE uint32_t LL_RCC_IC19_GetDivider(void)
7870 {
7871 return ((READ_BIT(RCC->IC19CFGR, RCC_IC19CFGR_IC19INT) >> RCC_IC19CFGR_IC19INT_Pos) + 1UL);
7872 }
7873
7874 /**
7875 * @brief Enable IC20
7876 * @rmtoll DIVENSR IC20ENS LL_RCC_IC20_Enable
7877 * @retval None
7878 */
LL_RCC_IC20_Enable(void)7879 __STATIC_INLINE void LL_RCC_IC20_Enable(void)
7880 {
7881 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC20ENS);
7882 }
7883
7884 /**
7885 * @brief Disable IC20
7886 * @rmtoll DIVENCR IC20ENC LL_RCC_IC20_Disable
7887 * @retval None
7888 */
LL_RCC_IC20_Disable(void)7889 __STATIC_INLINE void LL_RCC_IC20_Disable(void)
7890 {
7891 WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC20ENC);
7892 }
7893
7894 /**
7895 * @brief Check if IC20 is enabled
7896 * @rmtoll DIVENR IC20EN LL_RCC_IC20_IsEnabled
7897 * @retval State of bit (1 or 0).
7898 */
LL_RCC_IC20_IsEnabled(void)7899 __STATIC_INLINE uint32_t LL_RCC_IC20_IsEnabled(void)
7900 {
7901 return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC20EN) == RCC_DIVENR_IC20EN) ? 1UL : 0UL);
7902 }
7903
7904 /**
7905 * @brief Set the PLL source used as IC20 clock source.
7906 * @rmtoll IC20CFGR IC20SEL LL_RCC_IC20_SetSource
7907 * @param Source parameter can be one of the following values:
7908 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7909 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7910 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7911 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7912 * @retval None
7913 */
LL_RCC_IC20_SetSource(uint32_t Source)7914 __STATIC_INLINE void LL_RCC_IC20_SetSource(uint32_t Source)
7915 {
7916 MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL, Source);
7917 }
7918
7919 /**
7920 * @brief Get the PLL source used as IC20 clock source.
7921 * @rmtoll IC20CFGR IC20SEL LL_RCC_IC20_GetSource
7922 * @retval Returned value can be one of the following values:
7923 * @arg @ref LL_RCC_ICCLKSOURCE_PLL1
7924 * @arg @ref LL_RCC_ICCLKSOURCE_PLL2
7925 * @arg @ref LL_RCC_ICCLKSOURCE_PLL3
7926 * @arg @ref LL_RCC_ICCLKSOURCE_PLL4
7927 */
LL_RCC_IC20_GetSource(void)7928 __STATIC_INLINE uint32_t LL_RCC_IC20_GetSource(void)
7929 {
7930 return (uint32_t)(READ_BIT(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL));
7931 }
7932
7933 /**
7934 * @brief Set divider
7935 * @rmtoll IC20CFGR IC20INT LL_RCC_IC20_SetDivider
7936 * @param Divider This parameter can be a value between 1 and 256.
7937 * @retval None
7938 */
LL_RCC_IC20_SetDivider(uint32_t Divider)7939 __STATIC_INLINE void LL_RCC_IC20_SetDivider(uint32_t Divider)
7940 {
7941 MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20INT, (Divider - 1UL) << RCC_IC20CFGR_IC20INT_Pos);
7942 }
7943
7944 /**
7945 * @brief Get IC20 divider
7946 * @rmtoll IC20CFGR IC20INT LL_RCC_IC20_GetDivider
7947 * @retval can be a value between 1 and 256.
7948 */
LL_RCC_IC20_GetDivider(void)7949 __STATIC_INLINE uint32_t LL_RCC_IC20_GetDivider(void)
7950 {
7951 return ((READ_BIT(RCC->IC20CFGR, RCC_IC20CFGR_IC20INT) >> RCC_IC20CFGR_IC20INT_Pos) + 1UL);
7952 }
7953
7954 /**
7955 * @brief Enable CLKP
7956 * @rmtoll MISCENSR PERENS LL_RCC_CLKP_Enable
7957 * @retval None
7958 */
LL_RCC_CLKP_Enable(void)7959 __STATIC_INLINE void LL_RCC_CLKP_Enable(void)
7960 {
7961 WRITE_REG(RCC->MISCENSR, RCC_MISCENSR_PERENS);
7962 }
7963
7964 /**
7965 * @brief Disable CLKP
7966 * @rmtoll MISCENCR PERENC LL_RCC_CLKP_Disable
7967 * @retval None
7968 */
LL_RCC_CLKP_Disable(void)7969 __STATIC_INLINE void LL_RCC_CLKP_Disable(void)
7970 {
7971 WRITE_REG(RCC->MISCENCR, RCC_MISCENCR_PERENC);
7972 }
7973
7974 /**
7975 * @brief Check if CLKP is enabled
7976 * @rmtoll MISCENR PEREN LL_RCC_CLKP_IsEnabled
7977 * @retval State of bit (1 or 0).
7978 */
LL_RCC_CLKP_IsEnabled(void)7979 __STATIC_INLINE uint32_t LL_RCC_CLKP_IsEnabled(void)
7980 {
7981 return ((READ_BIT(RCC->MISCENR, RCC_MISCENR_PEREN) == RCC_MISCENR_PEREN) ? 1UL : 0UL);
7982 }
7983
7984 /**
7985 * @}
7986 */
7987
7988
7989 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
7990 * @{
7991 */
7992
7993 /**
7994 * @brief Clear LSI ready interrupt flag
7995 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
7996 * @retval None
7997 */
LL_RCC_ClearFlag_LSIRDY(void)7998 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
7999 {
8000 WRITE_REG(RCC->CICR, RCC_CICR_LSIRDYC);
8001 }
8002
8003 /**
8004 * @brief Clear LSE ready interrupt flag
8005 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
8006 * @retval None
8007 */
LL_RCC_ClearFlag_LSERDY(void)8008 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
8009 {
8010 WRITE_REG(RCC->CICR, RCC_CICR_LSERDYC);
8011 }
8012
8013 /**
8014 * @brief Clear HSI ready interrupt flag
8015 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
8016 * @retval None
8017 */
LL_RCC_ClearFlag_HSIRDY(void)8018 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
8019 {
8020 WRITE_REG(RCC->CICR, RCC_CICR_HSIRDYC);
8021 }
8022
8023 /**
8024 * @brief Clear HSE ready interrupt flag
8025 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
8026 * @retval None
8027 */
LL_RCC_ClearFlag_HSERDY(void)8028 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
8029 {
8030 WRITE_REG(RCC->CICR, RCC_CICR_HSERDYC);
8031 }
8032
8033 /**
8034 * @brief Clear MSI ready interrupt flag
8035 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
8036 * @retval None
8037 */
LL_RCC_ClearFlag_MSIRDY(void)8038 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
8039 {
8040 WRITE_REG(RCC->CICR, RCC_CICR_MSIRDYC);
8041 }
8042
8043 /**
8044 * @brief Clear PLL1 ready interrupt flag
8045 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
8046 * @retval None
8047 */
LL_RCC_ClearFlag_PLL1RDY(void)8048 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
8049 {
8050 WRITE_REG(RCC->CICR, RCC_CICR_PLL1RDYC);
8051 }
8052
8053 /**
8054 * @brief Clear PLL2 ready interrupt flag
8055 * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
8056 * @retval None
8057 */
LL_RCC_ClearFlag_PLL2RDY(void)8058 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
8059 {
8060 WRITE_REG(RCC->CICR, RCC_CICR_PLL2RDYC);
8061 }
8062
8063 /**
8064 * @brief Clear PLL3 ready interrupt flag
8065 * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY
8066 * @retval None
8067 */
LL_RCC_ClearFlag_PLL3RDY(void)8068 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
8069 {
8070 WRITE_REG(RCC->CICR, RCC_CICR_PLL3RDYC);
8071 }
8072
8073 /**
8074 * @brief Clear PLL4 ready interrupt flag
8075 * @rmtoll CICR PLL4RDYC LL_RCC_ClearFlag_PLL4RDY
8076 * @retval None
8077 */
LL_RCC_ClearFlag_PLL4RDY(void)8078 __STATIC_INLINE void LL_RCC_ClearFlag_PLL4RDY(void)
8079 {
8080 WRITE_REG(RCC->CICR, RCC_CICR_PLL4RDYC);
8081 }
8082
8083 /**
8084 * @brief Clear LSE Clock security system interrupt flag
8085 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
8086 * @retval None
8087 */
LL_RCC_ClearFlag_LSECSS(void)8088 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
8089 {
8090 WRITE_REG(RCC->CICR, RCC_CICR_LSECSSC);
8091 }
8092
8093 /**
8094 * @brief Clear HSE Clock security system interrupt flag
8095 * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS
8096 * @retval None
8097 */
LL_RCC_ClearFlag_HSECSS(void)8098 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
8099 {
8100 SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
8101 }
8102
8103 /**
8104 * @brief Clear WKUP ready interrupt flag
8105 * @rmtoll CICR WKUPFC LL_RCC_ClearFlag_WKUP
8106 * @retval None
8107 */
LL_RCC_ClearFlag_WKUP(void)8108 __STATIC_INLINE void LL_RCC_ClearFlag_WKUP(void)
8109 {
8110 WRITE_REG(RCC->CICR, RCC_CICR_WKUPFC);
8111 }
8112
8113 /**
8114 * @brief Check if LSI ready interrupt occurred or not
8115 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
8116 * @retval State of bit (1 or 0).
8117 */
LL_RCC_IsActiveFlag_LSIRDY(void)8118 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
8119 {
8120 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
8121 }
8122
8123 /**
8124 * @brief Check if LSE ready interrupt occurred or not
8125 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
8126 * @retval State of bit (1 or 0).
8127 */
LL_RCC_IsActiveFlag_LSERDY(void)8128 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
8129 {
8130 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
8131 }
8132
8133 /**
8134 * @brief Check if HSI ready interrupt occurred or not
8135 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
8136 * @retval State of bit (1 or 0).
8137 */
LL_RCC_IsActiveFlag_HSIRDY(void)8138 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
8139 {
8140 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
8141 }
8142
8143 /**
8144 * @brief Check if HSE ready interrupt occurred or not
8145 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
8146 * @retval State of bit (1 or 0).
8147 */
LL_RCC_IsActiveFlag_HSERDY(void)8148 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
8149 {
8150 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
8151 }
8152
8153 /**
8154 * @brief Check if MSI ready interrupt occurred or not
8155 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
8156 * @retval State of bit (1 or 0).
8157 */
LL_RCC_IsActiveFlag_MSIRDY(void)8158 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
8159 {
8160 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL);
8161 }
8162
8163 /**
8164 * @brief Check if PLL1 ready interrupt occurred or not
8165 * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY
8166 * @retval State of bit (1 or 0).
8167 */
LL_RCC_IsActiveFlag_PLL1RDY(void)8168 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
8169 {
8170 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL);
8171 }
8172
8173 /**
8174 * @brief Check if PLL2 ready interrupt occurred or not
8175 * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
8176 * @retval State of bit (1 or 0).
8177 */
LL_RCC_IsActiveFlag_PLL2RDY(void)8178 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
8179 {
8180 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL);
8181 }
8182
8183 /**
8184 * @brief Check if PLL3 ready interrupt occurred or not
8185 * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY
8186 * @retval State of bit (1 or 0).
8187 */
LL_RCC_IsActiveFlag_PLL3RDY(void)8188 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
8189 {
8190 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL);
8191 }
8192
8193 /**
8194 * @brief Check if PLL4 ready interrupt occurred or not
8195 * @rmtoll CIFR PLL4RDYF LL_RCC_IsActiveFlag_PLL4RDY
8196 * @retval State of bit (1 or 0).
8197 */
LL_RCC_IsActiveFlag_PLL4RDY(void)8198 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL4RDY(void)
8199 {
8200 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL4RDYF) == RCC_CIFR_PLL4RDYF) ? 1UL : 0UL);
8201 }
8202
8203 /**
8204 * @brief Check if LSE Clock security system interrupt occurred or not
8205 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
8206 * @retval State of bit (1 or 0).
8207 */
LL_RCC_IsActiveFlag_LSECSS(void)8208 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
8209 {
8210 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL);
8211 }
8212
8213 /**
8214 * @brief Check if HSE Clock security system interrupt occurred or not
8215 * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS
8216 * @retval State of bit (1 or 0).
8217 */
LL_RCC_IsActiveFlag_HSECSS(void)8218 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
8219 {
8220 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL);
8221 }
8222
8223 /**
8224 * @brief Check if WKUP from STOP interrupt occurred or not
8225 * @rmtoll CIFR WKUPF LL_RCC_IsActiveFlag_WKUP
8226 * @retval State of bit (1 or 0).
8227 */
LL_RCC_IsActiveFlag_WKUP(void)8228 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WKUP(void)
8229 {
8230 return ((READ_BIT(RCC->CIFR, RCC_CIFR_WKUPF) == RCC_CIFR_WKUPF) ? 1UL : 0UL);
8231 }
8232
8233 /**
8234 * @brief Check if RCC flag Low Power D1 reset is set or not.
8235 * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
8236 * @retval State of bit (1 or 0).
8237 */
LL_RCC_IsActiveFlag_LPWRRST(void)8238 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
8239 {
8240 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == RCC_RSR_LPWRRSTF) ? 1UL : 0UL);
8241 }
8242
8243 /**
8244 * @brief Check if RCC flag Window Watchdog reset is set or not.
8245 * @rmtoll RSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
8246 * @retval State of bit (1 or 0).
8247 */
LL_RCC_IsActiveFlag_WWDGRST(void)8248 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
8249 {
8250 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDGRSTF) == RCC_RSR_WWDGRSTF) ? 1UL : 0UL);
8251 }
8252
8253 /**
8254 * @brief Check if RCC flag Independent Watchdog reset is set or not.
8255 * @rmtoll RSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
8256 * @retval State of bit (1 or 0).
8257 */
LL_RCC_IsActiveFlag_IWDGRST(void)8258 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
8259 {
8260 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDGRSTF) == RCC_RSR_IWDGRSTF) ? 1UL : 0UL);
8261 }
8262
8263 /**
8264 * @brief Check if RCC flag Software reset is set or not.
8265 * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
8266 * @retval State of bit (1 or 0).
8267 */
LL_RCC_IsActiveFlag_SFTRST(void)8268 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
8269 {
8270 return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == RCC_RSR_SFTRSTF) ? 1UL : 0UL);
8271 }
8272
8273 /**
8274 * @brief Check if RCC flag POR/PDR reset is set or not.
8275 * @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST
8276 * @retval State of bit (1 or 0).
8277 */
LL_RCC_IsActiveFlag_PORRST(void)8278 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
8279 {
8280 return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == RCC_RSR_PORRSTF) ? 1UL : 0UL);
8281 }
8282
8283 /**
8284 * @brief Check if RCC flag Pin reset is set or not.
8285 * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST
8286 * @retval State of bit (1 or 0).
8287 */
LL_RCC_IsActiveFlag_PINRST(void)8288 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
8289 {
8290 return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == RCC_RSR_PINRSTF) ? 1UL : 0UL);
8291 }
8292
8293 /**
8294 * @brief Check if RCC flag BOR reset is set or not.
8295 * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST
8296 * @retval State of bit (1 or 0).
8297 */
LL_RCC_IsActiveFlag_BORRST(void)8298 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
8299 {
8300 return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
8301 }
8302
8303 /**
8304 * @brief Check if RCC flag CPU Lockup reset is set or not.
8305 * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_LCKRST
8306 * @retval State of bit (1 or 0).
8307 */
LL_RCC_IsActiveFlag_LCKRST(void)8308 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LCKRST(void)
8309 {
8310 return ((READ_BIT(RCC->RSR, RCC_RSR_LCKRSTF) == (RCC_RSR_LCKRSTF)) ? 1UL : 0UL);
8311 }
8312
8313 /**
8314 * @brief Check if RCC ETH1 power-down start acknowledged is set or not.
8315 * @rmtoll CCIPR2 ETH1PWRDOWNACK LL_RCC_IsActiveFlag_ETH1PWRDOWNACK
8316 * @retval State of bit (1 or 0).
8317 */
LL_RCC_IsActiveFlag_ETH1PWRDOWNACK(void)8318 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_ETH1PWRDOWNACK(void)
8319 {
8320 return ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1PWRDOWNACK) == (RCC_CCIPR2_ETH1PWRDOWNACK)) ? 1UL : 0UL);
8321 }
8322
8323 /**
8324 * @brief Set RMVF bit to clear all reset flags.
8325 * @rmtoll RSR RMVF LL_RCC_ClearResetFlags
8326 * @retval None
8327 */
LL_RCC_ClearResetFlags(void)8328 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
8329 {
8330 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
8331 }
8332
8333 /**
8334 * @}
8335 */
8336
8337 /** @defgroup RCC_LL_EF_IT_Management IT Management
8338 * @{
8339 */
8340
8341 /**
8342 * @brief Enable LSI ready interrupt
8343 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
8344 * @retval None
8345 */
LL_RCC_EnableIT_LSIRDY(void)8346 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
8347 {
8348 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
8349 }
8350
8351 /**
8352 * @brief Enable LSE ready interrupt
8353 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
8354 * @retval None
8355 */
LL_RCC_EnableIT_LSERDY(void)8356 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
8357 {
8358 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
8359 }
8360
8361 /**
8362 * @brief Enable MSI ready interrupt
8363 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
8364 * @retval None
8365 */
LL_RCC_EnableIT_MSIRDY(void)8366 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
8367 {
8368 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
8369 }
8370
8371 /**
8372 * @brief Enable HSI ready interrupt
8373 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
8374 * @retval None
8375 */
LL_RCC_EnableIT_HSIRDY(void)8376 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
8377 {
8378 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
8379 }
8380
8381 /**
8382 * @brief Enable HSE ready interrupt
8383 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
8384 * @retval None
8385 */
LL_RCC_EnableIT_HSERDY(void)8386 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
8387 {
8388 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
8389 }
8390
8391 /**
8392 * @brief Enable PLL1 ready interrupt
8393 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
8394 * @retval None
8395 */
LL_RCC_EnableIT_PLL1RDY(void)8396 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
8397 {
8398 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
8399 }
8400
8401 /**
8402 * @brief Enable PLL2 ready interrupt
8403 * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
8404 * @retval None
8405 */
LL_RCC_EnableIT_PLL2RDY(void)8406 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
8407 {
8408 SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
8409 }
8410
8411 /**
8412 * @brief Enable PLL3 ready interrupt
8413 * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY
8414 * @retval None
8415 */
LL_RCC_EnableIT_PLL3RDY(void)8416 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
8417 {
8418 SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
8419 }
8420
8421 /**
8422 * @brief Enable PLL4 ready interrupt
8423 * @rmtoll CIER PLL4RDYIE LL_RCC_EnableIT_PLL4RDY
8424 * @retval None
8425 */
LL_RCC_EnableIT_PLL4RDY(void)8426 __STATIC_INLINE void LL_RCC_EnableIT_PLL4RDY(void)
8427 {
8428 SET_BIT(RCC->CIER, RCC_CIER_PLL4RDYIE);
8429 }
8430
8431 /**
8432 * @brief Enable LSECSS interrupt
8433 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
8434 * @retval None
8435 */
LL_RCC_EnableIT_LSECSS(void)8436 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
8437 {
8438 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
8439 }
8440
8441 /**
8442 * @brief Enable HSECSS interrupt
8443 * @rmtoll CIER HSECSSIE LL_RCC_EnableIT_HSECSS
8444 * @retval None
8445 */
LL_RCC_EnableIT_HSECSS(void)8446 __STATIC_INLINE void LL_RCC_EnableIT_HSECSS(void)
8447 {
8448 SET_BIT(RCC->CIER, RCC_CIER_HSECSSIE);
8449 }
8450
8451 /**
8452 * @brief Enable WKUP interrupt
8453 * @rmtoll CIER WKUPIE LL_RCC_EnableIT_WKUP
8454 * @retval None
8455 */
LL_RCC_EnableIT_WKUP(void)8456 __STATIC_INLINE void LL_RCC_EnableIT_WKUP(void)
8457 {
8458 SET_BIT(RCC->CIER, RCC_CIER_WKUPIE);
8459 }
8460
8461 /**
8462 * @brief Disable LSI ready interrupt
8463 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
8464 * @retval None
8465 */
LL_RCC_DisableIT_LSIRDY(void)8466 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
8467 {
8468 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
8469 }
8470
8471 /**
8472 * @brief Disable LSE ready interrupt
8473 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
8474 * @retval None
8475 */
LL_RCC_DisableIT_LSERDY(void)8476 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
8477 {
8478 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
8479 }
8480
8481 /**
8482 * @brief Disable MSI ready interrupt
8483 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
8484 * @retval None
8485 */
LL_RCC_DisableIT_MSIRDY(void)8486 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
8487 {
8488 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
8489 }
8490
8491 /**
8492 * @brief Disable HSI ready interrupt
8493 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
8494 * @retval None
8495 */
LL_RCC_DisableIT_HSIRDY(void)8496 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
8497 {
8498 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
8499 }
8500
8501 /**
8502 * @brief Disable HSE ready interrupt
8503 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
8504 * @retval None
8505 */
LL_RCC_DisableIT_HSERDY(void)8506 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
8507 {
8508 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
8509 }
8510
8511 /**
8512 * @brief Disable PLL1 ready interrupt
8513 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
8514 * @retval None
8515 */
LL_RCC_DisableIT_PLL1RDY(void)8516 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
8517 {
8518 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
8519 }
8520
8521 /**
8522 * @brief Disable PLL2 ready interrupt
8523 * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
8524 * @retval None
8525 */
LL_RCC_DisableIT_PLL2RDY(void)8526 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
8527 {
8528 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
8529 }
8530
8531 /**
8532 * @brief Disable PLL3 ready interrupt
8533 * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY
8534 * @retval None
8535 */
LL_RCC_DisableIT_PLL3RDY(void)8536 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
8537 {
8538 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
8539 }
8540
8541 /**
8542 * @brief Disable PLL4 ready interrupt
8543 * @rmtoll CIER PLL4RDYIE LL_RCC_DisableIT_PLL4RDY
8544 * @retval None
8545 */
LL_RCC_DisableIT_PLL4RDY(void)8546 __STATIC_INLINE void LL_RCC_DisableIT_PLL4RDY(void)
8547 {
8548 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL4RDYIE);
8549 }
8550
8551 /**
8552 * @brief Disable LSECSS interrupt
8553 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
8554 * @retval None
8555 */
LL_RCC_DisableIT_LSECSS(void)8556 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
8557 {
8558 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
8559 }
8560
8561 /**
8562 * @brief Disable HSECSS interrupt
8563 * @rmtoll CIER HSECSSIE LL_RCC_DisableIT_HSECSS
8564 * @retval None
8565 */
LL_RCC_DisableIT_HSECSS(void)8566 __STATIC_INLINE void LL_RCC_DisableIT_HSECSS(void)
8567 {
8568 CLEAR_BIT(RCC->CIER, RCC_CIER_HSECSSIE);
8569 }
8570
8571 /**
8572 * @brief Disable WKUP interrupt
8573 * @rmtoll CIER WKUPIE LL_RCC_DisableIT_WKUP
8574 * @retval None
8575 */
LL_RCC_DisableIT_WKUP(void)8576 __STATIC_INLINE void LL_RCC_DisableIT_WKUP(void)
8577 {
8578 CLEAR_BIT(RCC->CIER, RCC_CIER_WKUPIE);
8579 }
8580
8581 /**
8582 * @brief Checks if LSI ready interrupt source is enabled or disabled.
8583 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
8584 * @retval State of bit (1 or 0).
8585 */
LL_RCC_IsEnabledIT_LSIRDY(void)8586 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
8587 {
8588 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
8589 }
8590
8591 /**
8592 * @brief Checks if LSE ready interrupt source is enabled or disabled.
8593 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
8594 * @retval State of bit (1 or 0).
8595 */
LL_RCC_IsEnabledIT_LSERDY(void)8596 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
8597 {
8598 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
8599 }
8600
8601 /**
8602 * @brief Checks if MSI ready interrupt source is enabled or disabled.
8603 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
8604 * @retval State of bit (1 or 0).
8605 */
LL_RCC_IsEnabledIT_MSIRDY(void)8606 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
8607 {
8608 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL);
8609 }
8610
8611 /**
8612 * @brief Checks if HSI ready interrupt source is enabled or disabled.
8613 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
8614 * @retval State of bit (1 or 0).
8615 */
LL_RCC_IsEnabledIT_HSIRDY(void)8616 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
8617 {
8618 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
8619 }
8620
8621 /**
8622 * @brief Checks if HSE ready interrupt source is enabled or disabled.
8623 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
8624 * @retval State of bit (1 or 0).
8625 */
LL_RCC_IsEnabledIT_HSERDY(void)8626 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
8627 {
8628 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
8629 }
8630
8631 /**
8632 * @brief Checks if PLL1 ready interrupt source is enabled or disabled.
8633 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY
8634 * @retval State of bit (1 or 0).
8635 */
LL_RCC_IsEnabledIT_PLL1RDY(void)8636 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void)
8637 {
8638 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
8639 }
8640
8641 /**
8642 * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
8643 * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
8644 * @retval State of bit (1 or 0).
8645 */
LL_RCC_IsEnabledIT_PLL2RDY(void)8646 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
8647 {
8648 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL);
8649 }
8650
8651 /**
8652 * @brief Checks if PLL3 ready interrupt source is enabled or disabled.
8653 * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnabledIT_PLL3RDY
8654 * @retval State of bit (1 or 0).
8655 */
LL_RCC_IsEnabledIT_PLL3RDY(void)8656 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void)
8657 {
8658 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL);
8659 }
8660
8661 /**
8662 * @brief Checks if PLL4 ready interrupt source is enabled or disabled.
8663 * @rmtoll CIER PLL4RDYIE LL_RCC_IsEnabledIT_PLL4RDY
8664 * @retval State of bit (1 or 0).
8665 */
LL_RCC_IsEnabledIT_PLL4RDY(void)8666 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL4RDY(void)
8667 {
8668 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL4RDYIE) == RCC_CIER_PLL4RDYIE) ? 1UL : 0UL);
8669 }
8670
8671 /**
8672 * @brief Checks if LSECSS interrupt source is enabled or disabled.
8673 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
8674 * @retval State of bit (1 or 0).
8675 */
LL_RCC_IsEnabledIT_LSECSS(void)8676 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
8677 {
8678 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
8679 }
8680
8681 /**
8682 * @brief Checks if HSECSS interrupt source is enabled or disabled.
8683 * @rmtoll CIER HSECSSIE LL_RCC_IsEnabledIT_HSECSS
8684 * @retval State of bit (1 or 0).
8685 */
LL_RCC_IsEnabledIT_HSECSS(void)8686 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSECSS(void)
8687 {
8688 return ((READ_BIT(RCC->CIER, RCC_CIER_HSECSSIE) == RCC_CIER_HSECSSIE) ? 1UL : 0UL);
8689 }
8690
8691 /**
8692 * @brief Checks if WKUP interrupt source is enabled or disabled.
8693 * @rmtoll CIER WKUPIE LL_RCC_IsEnabledIT_WKUP
8694 * @retval State of bit (1 or 0).
8695 */
LL_RCC_IsEnabledIT_WKUP(void)8696 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_WKUP(void)
8697 {
8698 return ((READ_BIT(RCC->CIER, RCC_CIER_WKUPIE) == RCC_CIER_WKUPIE) ? 1UL : 0UL);
8699 }
8700 /**
8701 * @}
8702 */
8703
8704 /** @defgroup RCC_LL_EF_Init De-initialization function
8705 * @{
8706 */
8707 void LL_RCC_DeInit(void);
8708 /**
8709 * @}
8710 */
8711
8712 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
8713 * @{
8714 */
8715 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
8716
8717 uint32_t LL_RCC_GetCpuClockFreq(void);
8718 uint32_t LL_RCC_GetSystemClockFreq(void);
8719 uint32_t LL_RCC_GetPLL1ClockFreq(void);
8720 uint32_t LL_RCC_GetPLL2ClockFreq(void);
8721 uint32_t LL_RCC_GetPLL3ClockFreq(void);
8722 uint32_t LL_RCC_GetPLL4ClockFreq(void);
8723 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t P1,
8724 uint32_t P2);
8725
8726 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
8727 uint32_t LL_RCC_GetADFClockFreq(uint32_t ADFxSource);
8728 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
8729 uint32_t LL_RCC_GetDCMIPPClockFreq(uint32_t DCMIPPxSource);
8730 uint32_t LL_RCC_GetETHClockFreq(uint32_t ETHxSource);
8731 uint32_t LL_RCC_GetETHPTPClockFreq(uint32_t ETHxPTPSource);
8732 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
8733 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
8734 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
8735 uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource);
8736 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
8737 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
8738 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
8739 uint32_t LL_RCC_GetMDFClockFreq(uint32_t MDFxSource);
8740 uint32_t LL_RCC_GetOTGPHYClockFreq(uint32_t OTGPHYxSource);
8741 uint32_t LL_RCC_GetOTGPHYCKREFClockFreq(uint32_t OTGPHYxCKREFSource);
8742 uint32_t LL_RCC_GetPSSIClockFreq(uint32_t PSSIxSource);
8743 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
8744 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
8745 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
8746 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
8747 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
8748 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
8749 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
8750 uint32_t LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource);
8751
8752 /**
8753 * @}
8754 */
8755
8756 /**
8757 * @}
8758 */
8759
8760
8761 /**
8762 * @}
8763 */
8764 #endif /* defined(RCC) */
8765
8766 /**
8767 * @}
8768 */
8769
8770 #ifdef __cplusplus
8771 }
8772 #endif
8773
8774 #endif /* STM32N6xx_LL_RCC_H */
8775
