1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32H5xx_LL_RCC_H
21 #define __STM32H5xx_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
44 * @{
45 */
46 /* Defines used for security configuration extension */
47 #define RCC_SECURE_MASK 0x3BFFU
48 /**
49 * @}
50 */
51
52 /* Private macros ------------------------------------------------------------*/
53 #if !defined(UNUSED)
54 #define UNUSED(x) ((void)(x))
55 #endif /* !UNUSED */
56
57 /* 32 24 16 8 0
58 --------------------------------------------------------
59 | Mask | ClkSource | Bit | Register |
60 | | Config | Position | Offset |
61 --------------------------------------------------------*/
62
63 /* Clock source register offset */
64 #define CCIPR1_OFFSET 0x00UL
65 #define CCIPR2_OFFSET 0x04UL
66 #define CCIPR3_OFFSET 0x08UL
67 #define CCIPR4_OFFSET 0x0CUL
68 #define CCIPR5_OFFSET 0x10UL
69
70 #define LL_RCC_REG_SHIFT 0U
71 #define LL_RCC_POS_SHIFT 8U
72 #define LL_RCC_CONFIG_SHIFT 16U
73 #define LL_RCC_MASK_SHIFT 24U
74
75 #define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)
76
77 #define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) &\
78 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
79
80 #define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) &\
81 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
82
83 #define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL)
84
85 #define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
86 (( __POS__ ) << LL_RCC_POS_SHIFT) | \
87 (( __REG__ ) << LL_RCC_REG_SHIFT) | \
88 (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
89
90 /* Exported types ------------------------------------------------------------*/
91 #if defined(USE_FULL_LL_DRIVER)
92 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
93 * @{
94 */
95
96 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
97 * @{
98 */
99
100 /**
101 * @brief RCC Clocks Frequency Structure
102 */
103 typedef struct
104 {
105 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
106 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
107 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
108 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
109 uint32_t PCLK3_Frequency; /*!< PCLK3 clock frequency */
110 } LL_RCC_ClocksTypeDef;
111
112 /**
113 * @brief PLL Clocks Frequency Structure
114 */
115 typedef struct
116 {
117 uint32_t PLL_P_Frequency;
118 uint32_t PLL_Q_Frequency;
119 uint32_t PLL_R_Frequency;
120 } LL_PLL_ClocksTypeDef;
121
122 /**
123 * @}
124 */
125
126 /**
127 * @}
128 */
129 #endif /* USE_FULL_LL_DRIVER */
130
131 /* Exported constants --------------------------------------------------------*/
132 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
133 * @{
134 */
135
136 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
137 * @brief Defines used to adapt values of different oscillators
138 * @note These values could be modified in the user environment according to
139 * HW set-up.
140 * @{
141 */
142 #if !defined (HSE_VALUE)
143 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
144 #endif /* HSE_VALUE */
145
146 #if !defined (HSI_VALUE)
147 #define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */
148 #endif /* HSI_VALUE */
149
150 #if !defined (CSI_VALUE)
151 #define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */
152 #endif /* CSI_VALUE */
153
154 #if !defined (LSE_VALUE)
155 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
156 #endif /* LSE_VALUE */
157
158 #if !defined (LSI_VALUE)
159 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
160 #endif /* LSI_VALUE */
161
162 #if !defined (HSI48_VALUE)
163 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
164 #endif /* HSI48_VALUE */
165
166 #if !defined (EXTERNAL_CLOCK_VALUE)
167 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
168 #endif /* EXTERNAL_CLOCK_VALUE */
169
170 /**
171 * @}
172 */
173
174 /** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider
175 * @{
176 */
177 #define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI_DIV1 clock activation */
178 #define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI_DIV2 clock activation */
179 #define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI_DIV4 clock activation */
180 #define LL_RCC_HSI_DIV_8 RCC_CR_HSIDIV /*!< HSI_DIV8 clock activation */
181 /**
182 * @}
183 */
184
185 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
186 * @{
187 */
188 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
189 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
190 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
191 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
192 /**
193 * @}
194 */
195
196 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
197 * @{
198 */
199 #define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U /*!< HSI oscillator selection as system clock */
200 #define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR1_SW_0 /*!< CSI oscillator selection as system clock */
201 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE oscillator selection as system clock */
202 #define LL_RCC_SYS_CLKSOURCE_PLL1 (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL1 selection as system clock */
203 /**
204 * @}
205 */
206
207 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
208 * @{
209 */
210 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
211 #define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR1_SWS_0 /*!< CSI oscillator used as system clock */
212 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE oscillator used as system clock */
213 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1 used as system clock */
214 /**
215 * @}
216 */
217
218 /** @defgroup RCC_LL_EC_HSEEXT EXTERNAL HSE clock Type
219 * @{
220 */
221 #define LL_RCC_HSE_ANALOG_TYPE 0U /*!< ANALOG clock used as HSE external clock source */
222 #define LL_RCC_HSE_DIGITAL_TYPE RCC_CR_HSEEXT /*!< DIGITAL clock used as HSE external clock source */
223 /**
224 * @}
225 */
226
227 /** @defgroup RCC_LL_EC_LSEEXT EXTERNAL LSE clock Type
228 * @{
229 */
230 #define LL_RCC_LSE_ANALOG_TYPE 0U /*!< ANALOG clock used as LSE external clock source */
231 #define LL_RCC_LSE_DIGITAL_TYPE RCC_BDCR_LSEEXT /*!< DIGITAL clock used as LSE external clock source */
232 /**
233 * @}
234 */
235
236 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
237 * @{
238 */
239 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
240 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
241 /**
242 * @}
243 */
244
245 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
246 * @{
247 */
248 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
249 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */
250 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */
251 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */
252 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */
253 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */
254 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */
255 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */
256 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */
257 /**
258 * @}
259 */
260
261 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
262 * @{
263 */
264 #define LL_RCC_APB1_DIV_1 (0x00000000U) /*!< HCLK not divided */
265 #define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */
266 #define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */
267 #define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */
268 #define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */
269 /**
270 * @}
271 */
272
273 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
274 * @{
275 */
276 #define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK not divided */
277 #define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */
278 #define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */
279 #define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */
280 #define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */
281 /**
282 * @}
283 */
284
285 /** @defgroup RCC_LL_EC_APB3_DIV APB high-speed prescaler (APB3)
286 * @{
287 */
288 #define LL_RCC_APB3_DIV_1 0x00000000U /*!< HCLK not divided */
289 #define LL_RCC_APB3_DIV_2 RCC_CFGR2_PPRE3_2 /*!< HCLK divided by 2 */
290 #define LL_RCC_APB3_DIV_4 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_0) /*!< HCLK divided by 4 */
291 #define LL_RCC_APB3_DIV_8 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_1) /*!< HCLK divided by 8 */
292 #define LL_RCC_APB3_DIV_16 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_1 | RCC_CFGR2_PPRE3_0) /*!< HCLK divided by 16 */
293 /**
294 * @}
295 */
296
297 /** @defgroup RCC_LL_EC_AHB1_PERIPH AHB1 peripherals clock branch disable
298 * @{
299 */
300 #define LL_RCC_AHB1_PERIPH_DIS RCC_CFGR2_AHB1DIS /*!< Clock Branch disable for all AHB1 peripherals */
301 /**
302 * @}
303 */
304
305 /** @defgroup RCC_LL_EC_AHB2_PERIPH AHB2 peripherals clock branch disable
306 * @{
307 */
308 #define LL_RCC_AHB2_PERIPH_DIS RCC_CFGR2_AHB2DIS /*!< Clock Branch disable for all AHB2 peripherals */
309 /**
310 * @}
311 */
312
313 /** @defgroup RCC_LL_EC_AHB4_PERIPH AHB4 peripherals clock branch disable
314 * @{
315 */
316 #define LL_RCC_AHB4_PERIPH_DIS RCC_CFGR2_AHB4DIS /*!< Clock Branch disable for all AHB4 peripherals */
317 /**
318 * @}
319 */
320
321 /** @defgroup RCC_LL_EC_APB1_PERIPH APB1 peripherals clock branch disable
322 * @{
323 */
324 #define LL_RCC_APB1_PERIPH_DIS RCC_CFGR2_APB1DIS /*!< Clock Branch disable for all APB1 peripherals */
325 /**
326 * @}
327 */
328
329 /** @defgroup RCC_LL_EC_APB2_PERIPH APB2 peripherals clock branch disable
330 * @{
331 */
332 #define LL_RCC_APB2_PERIPH_DIS RCC_CFGR2_APB2DIS /*!< Clock Branch disable for all APB2 peripherals */
333 /**
334 * @}
335 */
336
337 /** @defgroup RCC_LL_EC_APB3_PERIPH APB3 peripherals clock branch disable
338 * @{
339 */
340 #define LL_RCC_APB3_PERIPH_DIS RCC_CFGR2_APB3DIS /*!< Clock Branch disable for all APB3 peripherals */
341 /**
342 * @}
343 */
344
345 /** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection
346 * @{
347 */
348 #define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0x00000000U /*!< HCLKDIV8 clock used as SYSTICK clock source */
349 #define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR4_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */
350 #define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR4_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */
351 /**
352 * @}
353 */
354
355 /** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup from stop and CSS backup clock selection
356 * @{
357 */
358 #define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock after wake-up from STOP */
359 #define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI RCC_CFGR1_STOPWUCK /*!< CSI selection as system clock after wake-up from STOP */
360 /**
361 * @}
362 */
363
364 /** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup from stop clock source
365 * @{
366 */
367 #define LL_RCC_KERWAKEUP_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as kernel clock after wake-up from STOP */
368 #define LL_RCC_KERWAKEUP_CLKSOURCE_CSI RCC_CFGR1_STOPKERWUCK /*!< CSI selection as kernel clock after wake-up from STOP */
369 /**
370 * @}
371 */
372
373 /** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
374 * @{
375 */
376 #define LL_RCC_RTC_HSE_NOCLOCK (0x00000000U)
377 #define LL_RCC_RTC_HSE_DIV_2 (0x00000200U)
378 #define LL_RCC_RTC_HSE_DIV_3 (0x00000300U)
379 #define LL_RCC_RTC_HSE_DIV_4 (0x00000400U)
380 #define LL_RCC_RTC_HSE_DIV_5 (0x00000500U)
381 #define LL_RCC_RTC_HSE_DIV_6 (0x00000600U)
382 #define LL_RCC_RTC_HSE_DIV_7 (0x00000700U)
383 #define LL_RCC_RTC_HSE_DIV_8 (0x00000800U)
384 #define LL_RCC_RTC_HSE_DIV_9 (0x00000900U)
385 #define LL_RCC_RTC_HSE_DIV_10 (0x00000A00U)
386 #define LL_RCC_RTC_HSE_DIV_11 (0x00000B00U)
387 #define LL_RCC_RTC_HSE_DIV_12 (0x00000C00U)
388 #define LL_RCC_RTC_HSE_DIV_13 (0x00000D00U)
389 #define LL_RCC_RTC_HSE_DIV_14 (0x00000E00U)
390 #define LL_RCC_RTC_HSE_DIV_15 (0x00000F00U)
391 #define LL_RCC_RTC_HSE_DIV_16 (0x00001000U)
392 #define LL_RCC_RTC_HSE_DIV_17 (0x00001100U)
393 #define LL_RCC_RTC_HSE_DIV_18 (0x00001200U)
394 #define LL_RCC_RTC_HSE_DIV_19 (0x00001300U)
395 #define LL_RCC_RTC_HSE_DIV_20 (0x00001400U)
396 #define LL_RCC_RTC_HSE_DIV_21 (0x00001500U)
397 #define LL_RCC_RTC_HSE_DIV_22 (0x00001600U)
398 #define LL_RCC_RTC_HSE_DIV_23 (0x00001700U)
399 #define LL_RCC_RTC_HSE_DIV_24 (0x00001800U)
400 #define LL_RCC_RTC_HSE_DIV_25 (0x00001900U)
401 #define LL_RCC_RTC_HSE_DIV_26 (0x00001A00U)
402 #define LL_RCC_RTC_HSE_DIV_27 (0x00001B00U)
403 #define LL_RCC_RTC_HSE_DIV_28 (0x00001C00U)
404 #define LL_RCC_RTC_HSE_DIV_29 (0x00001D00U)
405 #define LL_RCC_RTC_HSE_DIV_30 (0x00001E00U)
406 #define LL_RCC_RTC_HSE_DIV_31 (0x00001F00U)
407 #define LL_RCC_RTC_HSE_DIV_32 (0x00002000U)
408 #define LL_RCC_RTC_HSE_DIV_33 (0x00002100U)
409 #define LL_RCC_RTC_HSE_DIV_34 (0x00002200U)
410 #define LL_RCC_RTC_HSE_DIV_35 (0x00002300U)
411 #define LL_RCC_RTC_HSE_DIV_36 (0x00002400U)
412 #define LL_RCC_RTC_HSE_DIV_37 (0x00002500U)
413 #define LL_RCC_RTC_HSE_DIV_38 (0x00002600U)
414 #define LL_RCC_RTC_HSE_DIV_39 (0x00002700U)
415 #define LL_RCC_RTC_HSE_DIV_40 (0x00002800U)
416 #define LL_RCC_RTC_HSE_DIV_41 (0x00002900U)
417 #define LL_RCC_RTC_HSE_DIV_42 (0x00002A00U)
418 #define LL_RCC_RTC_HSE_DIV_43 (0x00002B00U)
419 #define LL_RCC_RTC_HSE_DIV_44 (0x00002C00U)
420 #define LL_RCC_RTC_HSE_DIV_45 (0x00002D00U)
421 #define LL_RCC_RTC_HSE_DIV_46 (0x00002E00U)
422 #define LL_RCC_RTC_HSE_DIV_47 (0x00002F00U)
423 #define LL_RCC_RTC_HSE_DIV_48 (0x00003000U)
424 #define LL_RCC_RTC_HSE_DIV_49 (0x00003100U)
425 #define LL_RCC_RTC_HSE_DIV_50 (0x00003200U)
426 #define LL_RCC_RTC_HSE_DIV_51 (0x00003300U)
427 #define LL_RCC_RTC_HSE_DIV_52 (0x00003400U)
428 #define LL_RCC_RTC_HSE_DIV_53 (0x00003500U)
429 #define LL_RCC_RTC_HSE_DIV_54 (0x00003600U)
430 #define LL_RCC_RTC_HSE_DIV_55 (0x00003700U)
431 #define LL_RCC_RTC_HSE_DIV_56 (0x00003800U)
432 #define LL_RCC_RTC_HSE_DIV_57 (0x00003900U)
433 #define LL_RCC_RTC_HSE_DIV_58 (0x00003A00U)
434 #define LL_RCC_RTC_HSE_DIV_59 (0x00003B00U)
435 #define LL_RCC_RTC_HSE_DIV_60 (0x00003C00U)
436 #define LL_RCC_RTC_HSE_DIV_61 (0x00003D00U)
437 #define LL_RCC_RTC_HSE_DIV_62 (0x00003E00U)
438 #define LL_RCC_RTC_HSE_DIV_63 (0x00003F00U)
439 /**
440 * @}
441 */
442
443 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
444 * @{
445 */
446 #define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U)
447 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR1_TIMPRE)
448 /**
449 * @}
450 */
451
452 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO SOURCE selection
453 * @{
454 */
455 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | 0x00000000U)
456 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_0)
457 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_1)
458 #define LL_RCC_MCO1SOURCE_PLL1Q (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) |\
459 RCC_CFGR1_MCO1SEL_1|RCC_CFGR1_MCO1SEL_0)
460 #define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_2)
461 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | 0x00000000U)
462 #define LL_RCC_MCO2SOURCE_PLL2P (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_0)
463 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_1)
464 #define LL_RCC_MCO2SOURCE_PLL1P (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) |\
465 RCC_CFGR1_MCO2SEL_1|RCC_CFGR1_MCO2SEL_0)
466 #define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_2)
467 #define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) |\
468 RCC_CFGR1_MCO2SEL_2|RCC_CFGR1_MCO2SEL_0)
469 /**
470 * @}
471 */
472
473 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
474 * @{
475 */
476 #define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_0)
477 #define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_1)
478 #define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
479 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1)
480 #define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_2)
481 #define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
482 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2)
483 #define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
484 RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2)
485 #define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
486 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2)
487 #define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3)
488 #define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
489 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_3)
490 #define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
491 RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3)
492 #define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
493 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3)
494 #define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
495 RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3)
496 #define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
497 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3)
498 #define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
499 RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3)
500 #define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE)
501 #define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_0)
502 #define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_1)
503 #define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
504 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_1)
505 #define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_2)
506 #define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
507 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_2)
508 #define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
509 RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_2)
510 #define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
511 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_2)
512 #define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3)
513 #define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
514 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_3)
515 #define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
516 RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_3)
517 #define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
518 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_3)
519 #define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
520 RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_3)
521 #define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
522 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_3)
523 #define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
524 RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_3)
525 #define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE)
526 /**
527 * @}
528 */
529
530 #if defined(USE_FULL_LL_DRIVER)
531 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
532 * @{
533 */
534 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
535 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
536 /**
537 * @}
538 */
539 #endif /* USE_FULL_LL_DRIVER */
540
541 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
542 * @{
543 */
544 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
545 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
546 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
547 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by RTCPRE used as RTC clock */
548 /**
549 * @}
550 */
551
552 /** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection
553 * @{
554 */
555 #define LL_RCC_USART1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as USART1 clock source */
556 #define LL_RCC_USART1_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_0) /*!< PLL2 Q clock used as USART1 clock source */
557 #if defined(RCC_CR_PLL3ON)
558 #define LL_RCC_USART1_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_1) /*!< PLL3 Q clock used as USART1 clock source */
559 #endif /* PLL3 */
560 #define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_1 | RCC_CCIPR1_USART1SEL_0) /*!< HSI clock used as USART1 clock source */
561 #define LL_RCC_USART1_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_2) /*!< CSI clock used as USART1 clock source */
562 #define LL_RCC_USART1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_2 | RCC_CCIPR1_USART1SEL_0) /*!< LSE clock used as USART1 clock source */
563
564 #define LL_RCC_USART2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */
565 #define LL_RCC_USART2_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_0) /*!< PLL2 Q clock used as USART2 clock source */
566 #if defined(RCC_CR_PLL3ON)
567 #define LL_RCC_USART2_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_1) /*!< PLL3 Q clock used as USART2 clock source */
568 #endif /* PLL3 */
569 #define LL_RCC_USART2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_1 | RCC_CCIPR1_USART2SEL_0) /*!< HSI clock used as USART2 clock source */
570 #define LL_RCC_USART2_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_2) /*!< CSI clock used as USART2 clock source */
571 #define LL_RCC_USART2_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_2 | RCC_CCIPR1_USART2SEL_0) /*!< LSE clock used as USART2 clock source */
572
573 #define LL_RCC_USART3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */
574 #define LL_RCC_USART3_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_0) /*!< PLL2 Q clock used as USART3 clock source */
575 #if defined(RCC_CR_PLL3ON)
576 #define LL_RCC_USART3_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_1) /*!< PLL3 Q clock used as USART3 clock source */
577 #endif /* PLL3 */
578 #define LL_RCC_USART3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_1 | RCC_CCIPR1_USART3SEL_0) /*!< HSI clock used as USART3 clock source */
579 #define LL_RCC_USART3_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_2) /*!< CSI clock used as USART3 clock source */
580 #define LL_RCC_USART3_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_2 | RCC_CCIPR1_USART3SEL_0) /*!< LSE clock used as USART3 clock source */
581
582 #if defined(USART6)
583 #define LL_RCC_USART6_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART6 clock source */
584 #define LL_RCC_USART6_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_0) /*!< PLL2 Q clock used as USART6 clock source */
585 #define LL_RCC_USART6_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_1) /*!< PLL3 Q clock used as USART6 clock source */
586 #define LL_RCC_USART6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_1 | RCC_CCIPR1_USART6SEL_0) /*!< HSI clock used as USART6 clock source */
587 #define LL_RCC_USART6_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_2) /*!< CSI clock used as USART6 clock source */
588 #define LL_RCC_USART6_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_2 | RCC_CCIPR1_USART6SEL_0) /*!< LSE clock used as USART6 clock source */
589 #endif /* USART6 */
590
591 #if defined(USART10)
592 #define LL_RCC_USART10_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART10 clock source */
593 #define LL_RCC_USART10_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_0) /*!< PLL2 Q clock used as USART10 clock source */
594 #define LL_RCC_USART10_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_1) /*!< PLL3 Q clock used as USART10 clock source */
595 #define LL_RCC_USART10_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_1 | RCC_CCIPR1_USART10SEL_0) /*!< HSI clock used as USART10 clock source */
596 #define LL_RCC_USART10_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_2) /*!< CSI clock used as USART10 clock source */
597 #define LL_RCC_USART10_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_2 | RCC_CCIPR1_USART10SEL_0) /*!< LSE clock used as USART10 clock source */
598 #endif /* USART10 */
599
600 #if defined(USART11)
601 #define LL_RCC_USART11_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART11 clock source */
602 #define LL_RCC_USART11_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_0) /*!< PLL2 Q clock used as USART11 clock source */
603 #define LL_RCC_USART11_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_1) /*!< PLL3 Q clock used as USART11 clock source */
604 #define LL_RCC_USART11_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_1 | RCC_CCIPR2_USART11SEL_0) /*!< HSI clock used as USART11 clock source */
605 #define LL_RCC_USART11_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_2) /*!< CSI clock used as USART11 clock source */
606 #define LL_RCC_USART11_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_2 | RCC_CCIPR2_USART11SEL_0) /*!< LSE clock used as USART11 clock source */
607 #endif /* USART11 */
608 /**
609 * @}
610 */
611
612 #if defined(UART4)
613 /** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UARTx clock source selection
614 * @{
615 */
616 #define LL_RCC_UART4_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART4 clock source */
617 #define LL_RCC_UART4_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_0) /*!< PLL2 Q clock used as UART4 clock source */
618 #define LL_RCC_UART4_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_1) /*!< PLL3 Q clock used as UART4 clock source */
619 #define LL_RCC_UART4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_1 | RCC_CCIPR1_UART4SEL_0) /*!< HSI clock used as UART4 clock source */
620 #define LL_RCC_UART4_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_2) /*!< CSI clock used as UART4 clock source */
621 #define LL_RCC_UART4_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_2 | RCC_CCIPR1_UART4SEL_0) /*!< LSE clock used as UART4 clock source */
622
623 #define LL_RCC_UART5_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART5 clock source */
624 #define LL_RCC_UART5_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_0) /*!< PLL2 Q clock used as UART5 clock source */
625 #define LL_RCC_UART5_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_1) /*!< PLL3 Q clock used as UART5 clock source */
626 #define LL_RCC_UART5_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_1 | RCC_CCIPR1_UART5SEL_0) /*!< HSI clock used as UART5 clock source */
627 #define LL_RCC_UART5_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_2) /*!< CSI clock used as UART5 clock source */
628 #define LL_RCC_UART5_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_2 | RCC_CCIPR1_UART5SEL_0) /*!< LSE clock used as UART5 clock source */
629
630 #define LL_RCC_UART7_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART7 clock source */
631 #define LL_RCC_UART7_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_0) /*!< PLL2 Q clock used as UART7 clock source */
632 #define LL_RCC_UART7_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_1) /*!< PLL3 Q clock used as UART7 clock source */
633 #define LL_RCC_UART7_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_1 | RCC_CCIPR1_UART7SEL_0) /*!< HSI clock used as UART7 clock source */
634 #define LL_RCC_UART7_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_2) /*!< CSI clock used as UART7 clock source */
635 #define LL_RCC_UART7_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_2 | RCC_CCIPR1_UART7SEL_0) /*!< LSE clock used as UART7 clock source */
636
637 #define LL_RCC_UART8_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART8 clock source */
638 #define LL_RCC_UART8_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_0) /*!< PLL2 Q clock used as UART8 clock source */
639 #define LL_RCC_UART8_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_1) /*!< PLL3 Q clock used as UART8 clock source */
640 #define LL_RCC_UART8_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_1 | RCC_CCIPR1_UART8SEL_0) /*!< HSI clock used as UART8 clock source */
641 #define LL_RCC_UART8_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_2) /*!< CSI clock used as UART8 clock source */
642 #define LL_RCC_UART8_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_2 | RCC_CCIPR1_UART8SEL_0) /*!< LSE clock used as UART8 clock source */
643
644 #define LL_RCC_UART9_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART9 clock source */
645 #define LL_RCC_UART9_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_0) /*!< PLL2 Q clock used as UART9 clock source */
646 #define LL_RCC_UART9_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_1) /*!< PLL3 Q clock used as UART9 clock source */
647 #define LL_RCC_UART9_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_1 | RCC_CCIPR1_UART9SEL_0) /*!< HSI clock used as UART9 clock source */
648 #define LL_RCC_UART9_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_2) /*!< CSI clock used as UART9 clock source */
649 #define LL_RCC_UART9_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_2 | RCC_CCIPR1_UART9SEL_0) /*!< LSE clock used as UART9 clock source */
650
651 #define LL_RCC_UART12_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART12 clock source */
652 #define LL_RCC_UART12_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_0) /*!< PLL2 Q clock used as UART12 clock source */
653 #define LL_RCC_UART12_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_1) /*!< PLL3 Q clock used as UART12 clock source */
654 #define LL_RCC_UART12_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_1 | RCC_CCIPR2_UART12SEL_0) /*!< HSI clock used as UART12 clock source */
655 #define LL_RCC_UART12_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_2) /*!< CSI clock used as UART12 clock source */
656 #define LL_RCC_UART12_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_2 | RCC_CCIPR2_UART12SEL_0) /*!< LSE clock used as UART12 clock source */
657 /**
658 * @}
659 */
660 #endif /* UART4 */
661
662 /** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection
663 * @{
664 */
665 #define LL_RCC_LPUART1_CLKSOURCE_PCLK3 0x00000000U /*!< PCLK3 clock used as LPUART1 clock source */
666 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q RCC_CCIPR3_LPUART1SEL_0 /*!< PLL2Q clock used as LPUART1 clock source */
667 #if defined(RCC_CR_PLL3ON)
668 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q RCC_CCIPR3_LPUART1SEL_1 /*!< PLL3Q clock used as LPUART1 clock source */
669 #endif /* PLL3 */
670 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< HSI clock used as LPUART1 clock source */
671 #define LL_RCC_LPUART1_CLKSOURCE_CSI RCC_CCIPR3_LPUART1SEL_2 /*!< CSI clock used as LPUART1 clock source */
672 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_2) /*!< LSE clock used as LPUART1 clock source */
673 /**
674 * @}
675 */
676
677 /** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection
678 * @{
679 */
680 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */
681 #if defined(RCC_CR_PLL3ON)
682 #define LL_RCC_I2C1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL_0) /*!< PLL3 R clock used as I2C1 clock source */
683 #else
684 #define LL_RCC_I2C1_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL_0) /*!< PLL2 R clock used as I2C1 clock source */
685 #endif /* PLL3 */
686 #define LL_RCC_I2C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL_1) /*!< HSI clock used as I2C1 clock source */
687 #define LL_RCC_I2C1_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL) /*!< CSI clock used as I2C1 clock source */
688
689 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */
690 #if defined(RCC_CR_PLL3ON)
691 #define LL_RCC_I2C2_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL_0) /*!< PLL3 R clock used as I2C2 clock source */
692 #else
693 #define LL_RCC_I2C2_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL_0) /*!< PLL2 R clock used as I2C2 clock source */
694 #endif /* PLL3 */
695 #define LL_RCC_I2C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL_1) /*!< HSI clock used as I2C2 clock source */
696 #define LL_RCC_I2C2_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL) /*!< CSI clock used as I2C2 clock source */
697
698 #if defined(I2C3)
699 #define LL_RCC_I2C3_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as I2C3 clock source */
700 #define LL_RCC_I2C3_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, RCC_CCIPR4_I2C3SEL_0) /*!< PLL3 R clock used as I2C3 clock source */
701 #define LL_RCC_I2C3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, RCC_CCIPR4_I2C3SEL_1) /*!< HSI clock used as I2C3 clock source */
702 #define LL_RCC_I2C3_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, RCC_CCIPR4_I2C3SEL) /*!< CSI clock used as I2C3 clock source */
703 #endif /* I2C3 */
704
705 #if defined(I2C4)
706 #define LL_RCC_I2C4_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as I2C4 clock source */
707 #define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, RCC_CCIPR4_I2C4SEL_0) /*!< PLL3 R clock used as I2C4 clock source */
708 #define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, RCC_CCIPR4_I2C4SEL_1) /*!< HSI clock used as I2C4 clock source */
709 #define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, RCC_CCIPR4_I2C4SEL) /*!< CSI clock used as I2C4 clock source */
710 #endif /* I2C4 */
711 /**
712 * @}
713 */
714
715 /** @defgroup RCC_LL_EC_I3C_CLKSOURCE Peripheral I3Cx clock source selection
716 * @{
717 */
718 #define LL_RCC_I3C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as I3C1 clock source */
719 #if defined(RCC_CR_PLL3ON)
720 #define LL_RCC_I3C1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL_0) /*!< PLL3 R clock used as I3C1 clock source */
721 #else
722 #define LL_RCC_I3C1_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL_0) /*!< PLL2 R clock used as I3C1 clock source */
723 #endif /* PLL3 */
724 #define LL_RCC_I3C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL_1) /*!< HSI clock used as I3C1 clock source */
725 #define LL_RCC_I3C1_CLKSOURCE_NONE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL) /*!< NONE clock used as I3C1 clock source */
726
727 #if defined(I3C2)
728 #define LL_RCC_I3C2_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as I3C2 clock source */
729 #define LL_RCC_I3C2_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_0) /*!< PLL2 R clock used as I3C2 clock source */
730 #define LL_RCC_I3C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_1) /*!< HSI clock used as I3C2 clock source */
731 #define LL_RCC_I3C2_CLKSOURCE_NONE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL) /*!< NONE clock used as I3C2 clock source */
732 #endif /* I3C2 */
733 /**
734 * @}
735 */
736
737 /** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection
738 * @{
739 */
740 #define LL_RCC_SPI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SPI1 clock source */
741 #define LL_RCC_SPI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_0) /*!< PLL2 P clock used as SPI1 clock source */
742 #if defined(RCC_CR_PLL3ON)
743 #define LL_RCC_SPI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_1) /*!< PLL3 P clock used as SPI1 clock source */
744 #endif /* PLL3 */
745 #define LL_RCC_SPI1_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_1 | RCC_CCIPR3_SPI1SEL_0) /*!< PIN clock used as SPI1 clock source */
746 #define LL_RCC_SPI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_2) /*!< CLKP clock used as SPI1 clock source */
747
748 #define LL_RCC_SPI2_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SPI2 clock source */
749 #define LL_RCC_SPI2_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_0) /*!< PLL2 P clock used as SPI2 clock source */
750 #if defined(RCC_CR_PLL3ON)
751 #define LL_RCC_SPI2_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_1) /*!< PLL3 P clock used as SPI2 clock source */
752 #endif /* PLL3 */
753 #define LL_RCC_SPI2_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_1 | RCC_CCIPR3_SPI2SEL_0) /*!< PIN clock used as SPI2 clock source */
754 #define LL_RCC_SPI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_2) /*!< CLKP clock used as SPI2 clock source */
755
756 #define LL_RCC_SPI3_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SPI3 clock source */
757 #define LL_RCC_SPI3_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_0) /*!< PLL2 P clock used as SPI3 clock source */
758 #if defined(RCC_CR_PLL3ON)
759 #define LL_RCC_SPI3_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_1) /*!< PLL3 P clock used as SPI3 clock source */
760 #endif /* PLL3 */
761 #define LL_RCC_SPI3_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_1 | RCC_CCIPR3_SPI3SEL_0) /*!< PIN clock used as SPI3 clock source */
762 #define LL_RCC_SPI3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_2) /*!< CLKP clock used as SPI3 clock source */
763
764 #if defined(SPI4)
765 #define LL_RCC_SPI4_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as SPI4 clock source */
766 #define LL_RCC_SPI4_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_0) /*!< PLL2 Q clock used as SPI4 clock source */
767 #define LL_RCC_SPI4_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_1) /*!< PLL3 Q clock used as SPI4 clock source */
768 #define LL_RCC_SPI4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_1 | RCC_CCIPR3_SPI4SEL_0) /*!< HSI clock used as SPI4 clock source */
769 #define LL_RCC_SPI4_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_2) /*!< CSI clock used as SPI4 clock source */
770 #define LL_RCC_SPI4_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_2 | RCC_CCIPR3_SPI4SEL_0) /*!< HSE clock used as SPI4 clock source */
771 #endif /* SPI4 */
772
773 #if defined(SPI5)
774 #define LL_RCC_SPI5_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as SPI5 clock source */
775 #define LL_RCC_SPI5_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_0) /*!< PLL2 Q clock used as SPI5 clock source */
776 #define LL_RCC_SPI5_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_1) /*!< PLL3 Q clock used as SPI5 clock source */
777 #define LL_RCC_SPI5_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_1 | RCC_CCIPR3_SPI5SEL_0) /*!< HSI clock used as SPI5 clock source */
778 #define LL_RCC_SPI5_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_2) /*!< CSI clock used as SPI5 clock source */
779 #define LL_RCC_SPI5_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_2 | RCC_CCIPR3_SPI5SEL_0) /*!< HSE clock used as SPI5 clock source */
780 #endif /* SPI5 */
781
782 #if defined(SPI6)
783 #define LL_RCC_SPI6_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as SPI6 clock source */
784 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_0) /*!< PLL2 Q clock used as SPI6 clock source */
785 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_1) /*!< PLL3 Q clock used as SPI6 clock source */
786 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_1 | RCC_CCIPR3_SPI6SEL_0) /*!< HSI clock used as SPI6 clock source */
787 #define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_2) /*!< CSI clock used as SPI6 clock source */
788 #define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_2 | RCC_CCIPR3_SPI6SEL_0) /*!< HSE clock used as SPI6 clock source */
789 #endif /* SPI6 */
790 /**
791 * @}
792 */
793
794 /** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection
795 * @{
796 */
797 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM1 clock source */
798 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_0) /*!< PLL2 P clock used as LPTIM1 clock source */
799 #if defined(RCC_CR_PLL3ON)
800 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_1) /*!< PLL3 R clock used as LPTIM1 clock source */
801 #endif /* PLL3 */
802 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_1) /*!< LSE clock used as LPTIM1 clock source */
803 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_2) /*!< LSI clock used as LPTIM1 clock source */
804 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_2) /*!< CLKP clock used as LPTIM1 clock source */
805
806 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as LPTIM2 clock source */
807 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_0) /*!< PLL2 P clock used as LPTIM2 clock source */
808 #if defined(RCC_CR_PLL3ON)
809 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_1) /*!< PLL3 R clock used as LPTIM2 clock source */
810 #endif /* PLL3 */
811 #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_1) /*!< LSE clock used as LPTIM2 clock source */
812 #define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_2) /*!< LSI clock used as LPTIM2 clock source */
813 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_2) /*!< CLKP clock used as LPTIM2 clock source */
814
815 #if defined(LPTIM3)
816 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM3 clock source */
817 #define LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_0) /*!< PLL2 P clock used as LPTIM3 clock source */
818 #define LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_1) /*!< PLL3 R clock used as LPTIM3 clock source */
819 #define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_1) /*!< LSE clock used as LPTIM3 clock source */
820 #define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_2) /*!< LSI clock used as LPTIM3 clock source */
821 #define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_2) /*!< CLKP clock used as LPTIM3 clock source */
822 #endif /* LPTIM3 */
823
824 #if defined(LPTIM4)
825 #define LL_RCC_LPTIM4_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM4 clock source */
826 #define LL_RCC_LPTIM4_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_0) /*!< PLL2 P clock used as LPTIM4 clock source */
827 #define LL_RCC_LPTIM4_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_1) /*!< PLL3 R clock used as LPTIM4 clock source */
828 #define LL_RCC_LPTIM4_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_1) /*!< LSE clock used as LPTIM4 clock source */
829 #define LL_RCC_LPTIM4_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_2) /*!< LSI clock used as LPTIM4 clock source */
830 #define LL_RCC_LPTIM4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_2) /*!< CLKP clock used as LPTIM4 clock source */
831 #endif /* LPTIM4 */
832
833 #if defined(LPTIM5)
834 #define LL_RCC_LPTIM5_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM5 clock source */
835 #define LL_RCC_LPTIM5_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_0) /*!< PLL2 P clock used as LPTIM5 clock source */
836 #define LL_RCC_LPTIM5_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_1) /*!< PLL3 R clock used as LPTIM5 clock source */
837 #define LL_RCC_LPTIM5_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_1) /*!< LSE clock used as LPTIM5 clock source */
838 #define LL_RCC_LPTIM5_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_2) /*!< LSI clock used as LPTIM5 clock source */
839 #define LL_RCC_LPTIM5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_2) /*!< CLKP clock used as LPTIM5 clock source */
840 #endif /* LPTIM5 */
841
842 #if defined(LPTIM6)
843 #define LL_RCC_LPTIM6_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM6 clock source */
844 #define LL_RCC_LPTIM6_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_0) /*!< PLL2 P clock used as LPTIM6 clock source */
845 #define LL_RCC_LPTIM6_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_1) /*!< PLL3 R clock used as LPTIM6 clock source */
846 #define LL_RCC_LPTIM6_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_1) /*!< LSE clock used as LPTIM6 clock source */
847 #define LL_RCC_LPTIM6_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_2) /*!< LSI clock used as LPTIM6 clock source */
848 #define LL_RCC_LPTIM6_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_2) /*!< CLKP clock used as LPTIM6 clock source */
849 #endif /* LPTIM6 */
850 /**
851 * @}
852 */
853
854 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN kernel clock source selection
855 * @{
856 */
857 #define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN kernel clock source */
858 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q RCC_CCIPR5_FDCANSEL_0 /*!< PLL1 Q clock used as FDCAN kernel clock source */
859 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q RCC_CCIPR5_FDCANSEL_1 /*!< PLL2 Q clock used as FDCAN kernel clock source */
860 #define LL_RCC_FDCAN_CLKSOURCE_NONE RCC_CCIPR5_FDCANSEL /*!< NO clock used as FDCAN kernel clock source */
861 /**
862 * @}
863 */
864
865 #if defined(SAI1)
866 /** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection
867 * @{
868 */
869 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SAI1 clock source */
870 #define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_0) /*!< PLL2 P clock used as SAI1 clock source */
871 #define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_1) /*!< PLL3 P clock used as SAI1 clock source */
872 #define LL_RCC_SAI1_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_1 | RCC_CCIPR5_SAI1SEL_0) /*!< External input clock used as SAI1 clock source */
873 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_2) /*!< CLKP clock used as SAI1 clock source */
874
875 #define LL_RCC_SAI2_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SAI2 clock source */
876 #define LL_RCC_SAI2_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_0) /*!< PLL2 P clock used as SAI2 clock source */
877 #define LL_RCC_SAI2_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_1) /*!< PLL3 P clock used as SAI2 clock source */
878 #define LL_RCC_SAI2_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_1 | RCC_CCIPR5_SAI2SEL_0) /*!< External input clock used as SAI2 clock source */
879 #define LL_RCC_SAI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_2) /*!< CLKP clock used as SAI2 clock source */
880 /**
881 * @}
882 */
883 #endif /* SAI1 */
884
885 #if defined(SDMMC1)
886 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMCx kernel clock source selection
887 * @{
888 */
889 #define LL_RCC_SDMMC1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC1SEL, RCC_CCIPR4_SDMMC1SEL_Pos, 0x00000000U) /*!< PLL1 Q used as SDMMC1 clock source */
890 #define LL_RCC_SDMMC1_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC1SEL, RCC_CCIPR4_SDMMC1SEL_Pos, RCC_CCIPR4_SDMMC1SEL) /*!< PLL2 R used as SDMMC1 clock source */
891 #if defined(SDMMC2)
892 #define LL_RCC_SDMMC2_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC2SEL, RCC_CCIPR4_SDMMC2SEL_Pos, 0x00000000U) /*!< PLL1 Q used as SDMMC2 clock source */
893 #define LL_RCC_SDMMC2_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC2SEL, RCC_CCIPR4_SDMMC2SEL_Pos, RCC_CCIPR4_SDMMC2SEL) /*!< PLL2 R used as SDMMC2 clock source */
894 #endif /*SDMMC2*/
895 /**
896 * @}
897 */
898 #endif /* SDMMC1 */
899
900 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
901 * @{
902 */
903 #define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
904 #define LL_RCC_RNG_CLKSOURCE_PLL1Q RCC_CCIPR5_RNGSEL_0 /*!< PLL1 Q clock used as RNG clock source */
905 #define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR5_RNGSEL_1 /*!< LSE clock used as RNG clock source */
906 #define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR5_RNGSEL /*!< LSI clock used as RNG clock source */
907 /**
908 * @}
909 */
910
911 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
912 * @{
913 */
914 #define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */
915 #define LL_RCC_USB_CLKSOURCE_PLL1Q RCC_CCIPR4_USBSEL_0 /*!< PLL1 Q clock used as USB clock source */
916 #if defined(RCC_CR_PLL3ON)
917 #define LL_RCC_USB_CLKSOURCE_PLL3Q RCC_CCIPR4_USBSEL_1 /*!< PLL3 Q clock used as USB clock source */
918 #endif /* PLL3 */
919 #define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CCIPR4_USBSEL /*!< HSI48 clock used as USB clock source */
920 /**
921 * @}
922 */
923
924 /** @defgroup RCC_LL_EC_ADCDAC_CLKSOURCE Peripheral ADCDAC clock source selection
925 * @{
926 */
927 #define LL_RCC_ADCDAC_CLKSOURCE_HCLK 0x00000000U /*!< AHB clock used as ADCDAC clock source */
928 #define LL_RCC_ADCDAC_CLKSOURCE_SYSCLK RCC_CCIPR5_ADCDACSEL_0 /*!< SYSCLK clock used as ADCDAC clock source */
929 #define LL_RCC_ADCDAC_CLKSOURCE_PLL2R RCC_CCIPR5_ADCDACSEL_1 /*!< PLL2 R clock used as ADCDAC clock source */
930 #define LL_RCC_ADCDAC_CLKSOURCE_HSE (RCC_CCIPR5_ADCDACSEL_0 | RCC_CCIPR5_ADCDACSEL_1) /*!< HSE clock used as ADCDAC clock source */
931 #define LL_RCC_ADCDAC_CLKSOURCE_HSI RCC_CCIPR5_ADCDACSEL_2 /*!< HSI clock used as ADCDAC clock source */
932 #define LL_RCC_ADCDAC_CLKSOURCE_CSI (RCC_CCIPR5_ADCDACSEL_0 | RCC_CCIPR5_ADCDACSEL_2) /*!< CSI clock used as ADCDAC clock source */
933 /**
934 * @}
935 */
936
937 /** @defgroup RCC_LL_EC_DAC_CLKSOURCE Peripheral DAC low-power clock source selection
938 * @{
939 */
940 #define LL_RCC_DAC_LP_CLKSOURCE_LSE 0x00000000U /*!< LSE clock used as DAC low-power clock */
941 #define LL_RCC_DAC_LP_CLKSOURCE_LSI RCC_CCIPR5_DACSEL /*!< LSI clock used as DAC low-power clock */
942 /**
943 * @}
944 */
945
946 #if defined(CEC)
947 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
948 * @{
949 */
950 #define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /*!< LSE clock used as CEC clock */
951 #define LL_RCC_CEC_CLKSOURCE_LSI RCC_CCIPR5_CECSEL_0 /*!< LSI clock used as CEC clock */
952 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 RCC_CCIPR5_CECSEL_1 /*!< CSI clock divied by 122 used as CEC clock */
953 #define LL_RCC_CEC_CLKSOURCE_NONE RCC_CCIPR5_CECSEL /*!< NO clock used as CEC clock source */
954 /**
955 * @}
956 */
957 #endif /* CEC */
958
959 #if defined(OCTOSPI1)
960 /** @defgroup RCC_LL_EC_OCTOSPI_CLKSOURCE Peripheral OCTOSPI kernel clock source selection
961 * @{
962 */
963 #define LL_RCC_OSPI_CLKSOURCE_HCLK 0x00000000U /*!< AHB clock used as OctoSPI kernel clock source */
964 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q RCC_CCIPR4_OCTOSPISEL_0 /*!< PLL1 Q clock used as OctoSPI kernel clock source */
965 #define LL_RCC_OSPI_CLKSOURCE_PLL2R RCC_CCIPR4_OCTOSPISEL_1 /*!< PLL2 R clock used as OctoSPI kernel clock source */
966 #define LL_RCC_OSPI_CLKSOURCE_CLKP RCC_CCIPR4_OCTOSPISEL /*!< CLKP clock used as OctoSPI clock source */
967 /**
968 * @}
969 */
970 #endif /* OCTOSPI1 */
971
972 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection
973 * @{
974 */
975 #define LL_RCC_CLKP_CLKSOURCE_HSI 0x00000000U /*!< HSI clock used as CLKP clock source */
976 #define LL_RCC_CLKP_CLKSOURCE_CSI RCC_CCIPR5_CKERPSEL_0 /*!< CSI clock used as CLKP clock source */
977 #define LL_RCC_CLKP_CLKSOURCE_HSE RCC_CCIPR5_CKERPSEL_1 /*!< HSE clock used as CLKP clock source */
978 #define LL_RCC_CLKP_CLKSOURCE_NONE RCC_CCIPR5_CKERPSEL /*!< No clock selected as CLKP clock source */
979 /**
980 * @}
981 */
982
983 /** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source
984 * @{
985 */
986 #define LL_RCC_USART1_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, 0x00000000U) /*!< USART1 Clock source selection */
987 #define LL_RCC_USART2_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, 0x00000000U) /*!< USART2 Clock source selection */
988 #define LL_RCC_USART3_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, 0x00000000U) /*!< USART3 Clock source selection */
989 #if defined(USART6)
990 #define LL_RCC_USART6_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, 0x00000000U) /*!< USART6 Clock source selection */
991 #endif /* USART6 */
992 #if defined(USART10)
993 #define LL_RCC_USART10_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, 0x00000000U) /*!< USART10 Clock source selection */
994 #endif /* USART10 */
995 #if defined(USART11)
996 #define LL_RCC_USART11_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, 0x00000000U) /*!< USART11 Clock source selection */
997 #endif /* USART11 */
998 /**
999 * @}
1000 */
1001
1002 #if defined(UART4)
1003 /** @defgroup RCC_LL_EC_UART Peripheral UARTx get clock source
1004 * @{
1005 */
1006 #define LL_RCC_UART4_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, 0x00000000U) /*!< UART4 Clock source selection */
1007 #define LL_RCC_UART5_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, 0x00000000U) /*!< UART5 Clock source selection */
1008 #define LL_RCC_UART7_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, 0x00000000U) /*!< UART7 Clock source selection */
1009 #define LL_RCC_UART8_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, 0x00000000U) /*!< UART8 Clock source selection */
1010 #define LL_RCC_UART9_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, 0x00000000U) /*!< UART9 Clock source selection */
1011 #define LL_RCC_UART12_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, 0x00000000U) /*!< UART12 Clock source selection */
1012 /**
1013 * @}
1014 */
1015 #endif /*UART4*/
1016
1017 /** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source
1018 * @{
1019 */
1020 #define LL_RCC_SPI1_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0x00000000U) /*!< SPI1 Clock source selection */
1021 #define LL_RCC_SPI2_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, 0x00000000U) /*!< SPI2 Clock source selection */
1022 #define LL_RCC_SPI3_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, 0x00000000U) /*!< SPI3 Clock source selection */
1023 #if defined(SPI4)
1024 #define LL_RCC_SPI4_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, 0x00000000U) /*!< SPI4 Clock source selection */
1025 #endif /* SPI4 */
1026 #if defined(SPI5)
1027 #define LL_RCC_SPI5_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, 0x00000000U) /*!< SPI5 Clock source selection */
1028 #endif /* SPI5 */
1029 #if defined(SPI6)
1030 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, 0x00000000U) /*!< SPI6 Clock source selection */
1031 #endif /* SPI6 */
1032 /**
1033 * @}
1034 */
1035
1036 /** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source
1037 * @{
1038 */
1039 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source
1045 * @{
1046 */
1047 #define LL_RCC_I2C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0x00000000U) /*!< I2C1 Clock source selection */
1048 #define LL_RCC_I2C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0x00000000U) /*!< I2C2 Clock source selection */
1049 #if defined(I2C3)
1050 #define LL_RCC_I2C3_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0x00000000U) /*!< I2C3 Clock source selection */
1051 #endif /* I2C3 */
1052 #if defined(I2C4)
1053 #define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0x00000000U) /*!< I2C4 Clock source selection */
1054 #endif /* I2C4 */
1055 /**
1056 * @}
1057 */
1058
1059 /** @defgroup RCC_LL_EC_I3C Peripheral I3Cx get clock source
1060 * @{
1061 */
1062 #define LL_RCC_I3C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0x00000000U) /*!< I3C1 Clock source selection */
1063 #if defined(I3C2)
1064 #define LL_RCC_I3C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0x00000000U) /*!< I3C2 Clock source selection */
1065 #endif /* I3C2 */
1066 /**
1067 * @}
1068 */
1069
1070 /** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source
1071 * @{
1072 */
1073 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0x00000000U) /*!< LPTIM1 Clock source selection */
1074 #define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, 0x00000000U) /*!< LPTIM2 Clock source selection */
1075 #if defined(LPTIM3)
1076 #define LL_RCC_LPTIM3_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, 0x00000000U) /*!< LPTIM3 Clock source selection */
1077 #endif /* LPTIM3 */
1078 #if defined(LPTIM4)
1079 #define LL_RCC_LPTIM4_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, 0x00000000U) /*!< LPTIM4 Clock source selection */
1080 #endif /* LPTIM4 */
1081 #if defined(LPTIM5)
1082 #define LL_RCC_LPTIM5_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, 0x00000000U) /*!< LPTIM5 Clock source selection */
1083 #endif /* LPTIM5 */
1084 #if defined(LPTIM6)
1085 #define LL_RCC_LPTIM6_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, 0x00000000U) /*!< LPTIM6 Clock source selection */
1086 #endif /* LPTIM6 */
1087 /**
1088 * @}
1089 */
1090
1091 #if defined(SAI1)
1092 /** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source
1093 * @{
1094 */
1095 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, 0x00000000U) /*!< SAI1 Clock source selection */
1096 #define LL_RCC_SAI2_CLKSOURCE LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, 0x00000000U) /*!< SAI2 Clock source selection */
1097 /**
1098 * @}
1099 */
1100 #endif /* SAI1 */
1101
1102 #if defined(SDMMC1)
1103 /** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source
1104 * @{
1105 */
1106 #define LL_RCC_SDMMC1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC1SEL, RCC_CCIPR4_SDMMC1SEL_Pos, 0x00000000U) /*!< SDMMC1 Kernel Clock source selection */
1107 #if defined(SDMMC2)
1108 #define LL_RCC_SDMMC2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC2SEL, RCC_CCIPR4_SDMMC2SEL_Pos, 0x00000000U) /*!< SDMMC2 Kernel Clock source selection */
1109 #endif /*SDMMC2*/
1110 /**
1111 * @}
1112 */
1113 #endif /* SDMMC1 */
1114
1115 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
1116 * @{
1117 */
1118 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR5_RNGSEL /*!< RNG Clock source selection */
1119 /**
1120 * @}
1121 */
1122
1123 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
1124 * @{
1125 */
1126 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR4_USBSEL /*!< USB Clock source selection */
1127 /**
1128 * @}
1129 */
1130
1131 /** @defgroup RCC_LL_EC_ADCDAC Peripheral ADCDAC get clock source
1132 * @{
1133 */
1134 #define LL_RCC_ADCDAC_CLKSOURCE RCC_CCIPR5_ADCDACSEL /*!< ADCDACs Clock source selection */
1135 /**
1136 * @}
1137 */
1138
1139 /** @defgroup RCC_LL_EC_DAC Peripheral DAC get low-power clock source
1140 * @{
1141 */
1142 #define LL_RCC_DAC_LP_CLKSOURCE RCC_CCIPR5_DACSEL /*!< DAC low-power Clock source selection */
1143 /**
1144 * @}
1145 */
1146
1147 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
1148 * @{
1149 */
1150 #define LL_RCC_CEC_CLKSOURCE RCC_CCIPR5_CECSEL
1151 /**
1152 * @}
1153 */
1154
1155 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get kernel clock source
1156 * @{
1157 */
1158 #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR5_FDCANSEL /*!< FDCAN kernel Clock source selection */
1159 /**
1160 * @}
1161 */
1162
1163 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
1164 * @{
1165 */
1166 #define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR4_OCTOSPISEL /*!< OctoSPI Clock source selection */
1167 /**
1168 * @}
1169 */
1170
1171 /** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source
1172 * @{
1173 */
1174 #define LL_RCC_CLKP_CLKSOURCE RCC_CCIPR5_CKERPSEL /*!< CLKP Clock source selection */
1175 /**
1176 * @}
1177 */
1178
1179 /** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source
1180 * @{
1181 */
1182 #define LL_RCC_PLL1SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL1 entry clock source */
1183 #define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_0 /*!< HSI clock selected as main PLL1 entry clock source */
1184 #define LL_RCC_PLL1SOURCE_CSI RCC_PLL1CFGR_PLL1SRC_1 /*!< CSI clock selected as main PLL1 entry clock source */
1185 #define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as main PLL1 entry clock source */
1186 /**
1187 * @}
1188 */
1189
1190 /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges
1191 * @{
1192 */
1193 #define LL_RCC_PLLINPUTRANGE_1_2 0x00000000U /*!< VCO input range: 1 to 2 MHz */
1194 #define LL_RCC_PLLINPUTRANGE_2_4 0x00000001U /*!< VCO input range: 2 to 4 MHz */
1195 #define LL_RCC_PLLINPUTRANGE_4_8 0x00000002U /*!< VCO input range: 4 to 8 MHz */
1196 #define LL_RCC_PLLINPUTRANGE_8_16 0x00000003U /*!< VCO input range: 8 to 16 MHz */
1197 /**
1198 * @}
1199 */
1200
1201 /** @defgroup RCC_LL_EC_PLLOUTPUTRANGE All PLLs output ranges
1202 * @{
1203 */
1204 #define LL_RCC_PLLVCORANGE_WIDE 0x00000000U /*!< VCO output range: 192 to 836 MHz */
1205 #define LL_RCC_PLLVCORANGE_MEDIUM 0x00000001U /*!< VCO output range: 150 to 420 MHz */
1206
1207 /**
1208 * @}
1209 */
1210
1211 /** @defgroup RCC_LL_EC_PLL2SOURCE PLL2 entry clock source
1212 * @{
1213 */
1214 #define LL_RCC_PLL2SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL2 entry clock source */
1215 #define LL_RCC_PLL2SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_0 /*!< HSI clock selected as main PLL2 entry clock source */
1216 #define LL_RCC_PLL2SOURCE_CSI RCC_PLL2CFGR_PLL2SRC_1 /*!< CSI clock selected as main PLL2 entry clock source */
1217 #define LL_RCC_PLL2SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1) /*!< HSE clock selected as main PLL2 entry clock source */
1218 /**
1219 * @}
1220 */
1221
1222 /** @defgroup RCC_LL_EC_PLL3SOURCE PLL3 entry clock source
1223 * @{
1224 */
1225 #define LL_RCC_PLL3SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL3 entry clock source */
1226 #define LL_RCC_PLL3SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_0 /*!< HSI clock selected as main PLL3 entry clock source */
1227 #define LL_RCC_PLL3SOURCE_CSI RCC_PLL3CFGR_PLL3SRC_1 /*!< CSI clock selected as main PLL3 entry clock source */
1228 #define LL_RCC_PLL3SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1) /*!< HSE clock selected as main PLL3 entry clock source */
1229 /**
1230 * @}
1231 */
1232
1233 #if defined(RCC_SECCFGR_HSISEC)
1234 /** @defgroup RCC_LL_EC_SECURE_ATTRIBUTES Secure attributes
1235 * @note Only available when system implements security (TZEN=1)
1236 * @{
1237 */
1238 #define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */
1239 #define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */
1240
1241 #define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration secure-only access */
1242 #define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */
1243 #define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration secure-only access */
1244 #define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */
1245 #define LL_RCC_CSI_SEC RCC_SECCFGR_CSISEC /*!< CSI clock configuration secure-only access */
1246 #define LL_RCC_CSI_NSEC 0U /*!< CSI clock configuration secure/non-secure access */
1247 #define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration secure-only access */
1248 #define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */
1249 #define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration secure-only access */
1250 #define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */
1251 #define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure-only access */
1252 #define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */
1253 #define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration secure-only access */
1254 #define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */
1255 #define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< main PLL clock configuration secure-only access */
1256 #define LL_RCC_PLL1_NSEC 0U /*!< main PLL clock configuration secure/non-secure access */
1257 #define LL_RCC_PLL2_SEC RCC_SECCFGR_PLL2SEC /*!< PLL2 clock configuration secure-only access */
1258 #define LL_RCC_PLL2_NSEC 0U /*!< PLL2 clock configuration secure/non-secure access */
1259 #define LL_RCC_PLL3_SEC RCC_SECCFGR_PLL3SEC /*!< PLL3 clock configuration secure-only access */
1260 #define LL_RCC_PLL3_NSEC 0U /*!< PLL3 clock configuration secure/non-secure access */
1261 #define LL_RCC_HSI48_SEC RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration secure-only access */
1262 #define LL_RCC_HSI48_NSEC 0U /*!< HSI48 clock configuration secure/non-secure access */
1263 #define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag secure-ony access */
1264 #define LL_RCC_RESET_FLAGS_NSEC 0U /*!< Remove reset flag secure/non-secure access */
1265 #define LL_RCC_CKPERSEL_SEC RCC_SECCFGR_CKPERSELSEC /*!< Periph clock configuration secure-ony access */
1266 #define LL_RCC_CKPERSEL_NSEC 0U /*!< Periph clock configuration secure/non-secure access */
1267 /**
1268 * @}
1269 */
1270 #endif /* RCC_SECCFGR_HSISEC */
1271
1272 /**
1273 * @}
1274 */
1275
1276 /* Exported macro ------------------------------------------------------------*/
1277 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1278 * @{
1279 */
1280
1281 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1282 * @{
1283 */
1284
1285 /**
1286 * @brief Write a value in RCC register
1287 * @param __REG__ Register to be written
1288 * @param __VALUE__ Value to be written in the register
1289 * @retval None
1290 */
1291 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1292
1293 /**
1294 * @brief Read a value in RCC register
1295 * @param __REG__ Register to be read
1296 * @retval Register value
1297 */
1298 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1299 /**
1300 * @}
1301 */
1302
1303 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1304 * @{
1305 */
1306
1307 /**
1308 * @brief Helper macro to calculate the PLL1P clock frequency
1309 * @note ex: @ref __LL_RCC_CALC_PLL1CLK_P_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetM (),
1310 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ());
1311 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSI/HSE/CSI)
1312 * @param __PLL1M__ parameter can be a value between 1 and 63
1313 * @param __PLL1N__ parameter can be a value between 4 and 512
1314 * @param __PLL1P__ parameter can be a value between 1 and 128 (odd values not allowed)
1315 * @retval PLL1P clock frequency (in Hz)
1316 */
1317
1318 #define __LL_RCC_CALC_PLL1CLK_P_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) \
1319 ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__))
1320
1321 /**
1322 * @brief Helper macro to calculate the PLL1Q clock frequency
1323 * @note ex: @ref __LL_RCC_CALC_PLL1CLK_Q_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetM (),
1324 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ());
1325 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSI/HSE/CSI)
1326 * @param __PLL1M__ parameter can be a value between 1 and 63
1327 * @param __PLL1N__ parameter can be a value between 4 and 512
1328 * @param __PLL1Q__ parameter can be a value between 2 and 128
1329 * @retval PLL1Q clock frequency (in Hz)
1330 */
1331 #define __LL_RCC_CALC_PLL1CLK_Q_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) \
1332 ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__))
1333
1334 /**
1335 * @brief Helper macro to calculate the PLL1R clock frequency
1336 * @note ex: @ref __LL_RCC_CALC_PLL1CLK_R_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetM (),
1337 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetN ());
1338 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSI/HSE/CSI)
1339 * @param __PLL1M__ parameter can be a value between 1 and 63
1340 * @param __PLL1N__ parameter can be a value between 4 and 512
1341 * @param __PLL1R__ parameter can be a value between 1 and 128
1342 * @retval PLL1R clock frequency (in Hz)
1343 */
1344
1345 #define __LL_RCC_CALC_PLL1CLK_R_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) \
1346 ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1R__))
1347
1348 /**
1349 * @brief Helper macro to calculate the PLL2P clock frequency
1350 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_P_FREQ (HSE_ALUE,@ref LL_RCC_PLL2_GetM (),
1351 * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetP ());
1352 * @param __INPUTFREQ__ PLL Input frequency (based on HSI/HSE/CSI)
1353 * @param __PLL2M__ parameter can be a value between 1 and 63
1354 * @param __PLL2N__ parameter can be a value between 4 and 512
1355 * @param __PLL2P__ parameter can be a value between 2 and 128
1356 * @retval PLL2P clock frequency (in Hz)
1357 */
1358 #define __LL_RCC_CALC_PLL2CLK_P_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2P__) \
1359 ((((__INPUTFREQ__) /(__PLL2M__)) * (__PLL2N__)) / (__PLL2P__))
1360
1361 /**
1362 * @brief Helper macro to calculate the PLL2Q clock frequency
1363 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_Q_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetM (),
1364 * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetQ ());
1365 * @param __INPUTFREQ__ PLL Input frequency (based on HSI/HSE/CSI)
1366 * @param __PLL2M__ parameter can be a value between 1 and 63
1367 * @param __PLL2N__ parameter can be a value between 4 and 512
1368 * @param __PLL2Q__ parameter can be a value between 1 and 128
1369 * @retval PLL2Q clock frequency (in Hz)
1370 */
1371 #define __LL_RCC_CALC_PLL2CLK_Q_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2Q__) \
1372 ((((__INPUTFREQ__) /(__PLL2M__)) * (__PLL2N__)) / (__PLL2Q__))
1373
1374 /**
1375 * @brief Helper macro to calculate the PLL2R clock frequency
1376 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_R_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetM (),
1377 * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetR ());
1378 * @param __INPUTFREQ__ PLL2 Input frequency (based on HSI/HSE/CSI)
1379 * @param __PLL2M__ parameter can be a value between 1 and 63
1380 * @param __PLL2N__ parameter can be a value between 4 and 512
1381 * @param __PLL2R__ parameter can be a value between 1 and 128
1382 * @retval PLL2R clock frequency (in Hz)
1383 */
1384 #define __LL_RCC_CALC_PLL2CLK_R_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2R__) \
1385 ((((__INPUTFREQ__) /(__PLL2M__)) * (__PLL2N__)) / (__PLL2R__))
1386
1387 /**
1388 * @brief Helper macro to calculate the PLL3P clock frequency
1389 * @note ex: @ref __LL_RCC_CALC_PLL3CLK_P_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetM (),
1390 * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetP ());
1391 * @param __INPUTFREQ__ PLL3 Input frequency (based on HSI/HSE/CSI)
1392 * @param __PLL3M__ parameter can be a value between 1 and 63
1393 * @param __PLL3N__ parameter can be a value between 4 and 512
1394 * @param __PLL3P__ parameter can be a value between 2 and 128
1395 * @retval PLL3P clock frequency (in Hz)
1396 */
1397 #define __LL_RCC_CALC_PLL3CLK_P_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3P__) \
1398 ((((__INPUTFREQ__) /(__PLL3M__)) * (__PLL3N__)) / (__PLL3P__))
1399
1400 /**
1401 * @brief Helper macro to calculate the PLL3 frequency
1402 * @note ex: @ref __LL_RCC_CALC_PLL3CLK_Q_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetM (),
1403 * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ());
1404 * @param __INPUTFREQ__ PLL3 Input frequency (based on HSI/HSE/CSI)
1405 * @param __PLL3M__ parameter can be a value between 1 and 63
1406 * @param __PLL3N__ parameter can be a value between 4 and 512
1407 * @param __PLL3Q__ parameter can be a value between 1 and 128
1408 * @retval PLL3Q clock frequency (in Hz)
1409 */
1410 #define __LL_RCC_CALC_PLL3CLK_Q_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3Q__) \
1411 ((((__INPUTFREQ__) /(__PLL3M__)) * (__PLL3N__)) / (__PLL3Q__))
1412
1413 /**
1414 * @brief Helper macro to calculate the PLL3 frequency
1415 * @note ex: @ref __LL_RCC_CALC_PLL3CLK_R_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetM (),
1416 * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetR ());
1417 * @param __INPUTFREQ__ PLL3 Input frequency (based on HSI/HSE/CSI)
1418 * @param __PLL3M__ parameter can be a value between 1 and 63
1419 * @param __PLL3N__ parameter can be a value between 4 and 512
1420 * @param __PLL3R__ parameter can be a value between 1 and 128
1421 * @retval PLL3R clock frequency (in Hz)
1422 */
1423 #define __LL_RCC_CALC_PLL3CLK_R_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3R__) \
1424 ((((__INPUTFREQ__) /(__PLL3M__)) * (__PLL3N__)) / (__PLL3R__))
1425
1426 /**
1427 * @brief Helper macro to calculate the HCLK frequency
1428 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSI/HSE/CSI/PLLCLK)
1429 * @param __AHBPRESCALER__ This parameter can be one of the following values:
1430 * @arg @ref LL_RCC_SYSCLK_DIV_1
1431 * @arg @ref LL_RCC_SYSCLK_DIV_2
1432 * @arg @ref LL_RCC_SYSCLK_DIV_4
1433 * @arg @ref LL_RCC_SYSCLK_DIV_8
1434 * @arg @ref LL_RCC_SYSCLK_DIV_16
1435 * @arg @ref LL_RCC_SYSCLK_DIV_64
1436 * @arg @ref LL_RCC_SYSCLK_DIV_128
1437 * @arg @ref LL_RCC_SYSCLK_DIV_256
1438 * @arg @ref LL_RCC_SYSCLK_DIV_512
1439 * @retval HCLK clock frequency (in Hz)
1440 */
1441 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) \
1442 ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos])
1443
1444 /**
1445 * @brief Helper macro to calculate the PCLK1 frequency (APB1)
1446 * @param __HCLKFREQ__ HCLK frequency
1447 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1448 * @arg @ref LL_RCC_APB1_DIV_1
1449 * @arg @ref LL_RCC_APB1_DIV_2
1450 * @arg @ref LL_RCC_APB1_DIV_4
1451 * @arg @ref LL_RCC_APB1_DIV_8
1452 * @arg @ref LL_RCC_APB1_DIV_16
1453 * @retval PCLK1 clock frequency (in Hz)
1454 */
1455 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \
1456 ((__HCLKFREQ__) >> (APBPrescTable[((__APB1PRESCALER__) & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]))
1457
1458 /**
1459 * @brief Helper macro to calculate the PCLK2 frequency (APB2)
1460 * @param __HCLKFREQ__ HCLK frequency
1461 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1462 * @arg @ref LL_RCC_APB2_DIV_1
1463 * @arg @ref LL_RCC_APB2_DIV_2
1464 * @arg @ref LL_RCC_APB2_DIV_4
1465 * @arg @ref LL_RCC_APB2_DIV_8
1466 * @arg @ref LL_RCC_APB2_DIV_16
1467 * @retval PCLK2 clock frequency (in Hz)
1468 */
1469 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) \
1470 ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR2_PPRE2_Pos])
1471
1472
1473 /**
1474 * @brief Helper macro to calculate the PCLK3 frequency (APB3)
1475 * @param __HCLKFREQ__ HCLK frequency
1476 * @param __APB3PRESCALER__ This parameter can be one of the following values:
1477 * @arg @ref LL_RCC_APB3_DIV_1
1478 * @arg @ref LL_RCC_APB3_DIV_2
1479 * @arg @ref LL_RCC_APB3_DIV_4
1480 * @arg @ref LL_RCC_APB3_DIV_8
1481 * @arg @ref LL_RCC_APB3_DIV_16
1482 * @retval PCLK3 clock frequency (in Hz)
1483 */
1484 #define __LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) \
1485 ((__HCLKFREQ__) >> APBPrescTable[(__APB3PRESCALER__) >> RCC_CFGR2_PPRE3_Pos])
1486
1487 /**
1488 * @brief Helper macro to calculate the HSI frequency
1489 * @param __HSIDIV__ This parameter can be one of the following values:
1490 * @arg @ref LL_RCC_HSI_DIV_1
1491 * @arg @ref LL_RCC_HSI_DIV_2
1492 * @arg @ref LL_RCC_HSI_DIV_4
1493 * @arg @ref LL_RCC_HSI_DIV_8
1494 * @retval HSI clock frequency (in Hz)
1495 */
1496 #define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE >> ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos))
1497
1498 /**
1499 * @}
1500 */
1501
1502 /**
1503 * @}
1504 */
1505
1506 /* Exported functions --------------------------------------------------------*/
1507 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1508 * @{
1509 */
1510
1511 /** @defgroup RCC_LL_EF_HSE HSE
1512 * @{
1513 */
1514
1515 /**
1516 * @brief Enable the HSE Clock Security System.
1517 * @rmtoll CR HSECSSON LL_RCC_HSE_EnableCSS
1518 * @retval None
1519 */
LL_RCC_HSE_EnableCSS(void)1520 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1521 {
1522 SET_BIT(RCC->CR, RCC_CR_HSECSSON);
1523 }
1524
1525 /**
1526 * @brief Enable HSE external oscillator (HSE Bypass)
1527 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1528 * @retval None
1529 */
LL_RCC_HSE_EnableBypass(void)1530 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1531 {
1532 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1533 }
1534
1535 /**
1536 * @brief Disable HSE external oscillator (HSE Bypass)
1537 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1538 * @retval None
1539 */
LL_RCC_HSE_DisableBypass(void)1540 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1541 {
1542 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1543 }
1544
1545 /**
1546 * @brief Enable HSE crystal oscillator (HSE ON)
1547 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1548 * @retval None
1549 */
LL_RCC_HSE_Enable(void)1550 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1551 {
1552 SET_BIT(RCC->CR, RCC_CR_HSEON);
1553 }
1554
1555 /**
1556 * @brief Disable HSE crystal oscillator (HSE ON)
1557 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1558 * @retval None
1559 */
LL_RCC_HSE_Disable(void)1560 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1561 {
1562 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1563 }
1564
1565 /**
1566 * @brief Check if HSE oscillator Ready
1567 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1568 * @retval State of bit (1 or 0).
1569 */
LL_RCC_HSE_IsReady(void)1570 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1571 {
1572 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
1573 }
1574
1575 /**
1576 * @brief Set external HSE clock type in Bypass mode
1577 * @note This bit can be written only if the HSE oscillator is disabled
1578 * @rmtoll CR HSEEXT LL_RCC_HSE_SetExternalClockType
1579 * @param HSEClockMode This parameter can be one of the following values:
1580 * @arg @ref LL_RCC_HSE_ANALOG_TYPE
1581 * @arg @ref LL_RCC_HSE_DIGITAL_TYPE
1582 * @retval None
1583 */
LL_RCC_HSE_SetExternalClockType(uint32_t HSEClockMode)1584 __STATIC_INLINE void LL_RCC_HSE_SetExternalClockType(uint32_t HSEClockMode)
1585 {
1586 MODIFY_REG(RCC->CR, RCC_CR_HSEEXT, HSEClockMode);
1587 }
1588
1589 /**
1590 * @brief Get external HSE clock type in Bypass mode
1591 * @rmtoll CR HSEEXT LL_RCC_HSE_GetExternalClockType
1592 * @retval Returned value can be one of the following values:
1593 * @arg @ref LL_RCC_HSE_ANALOG_TYPE
1594 * @arg @ref LL_RCC_HSE_DIGITAL_TYPE
1595 */
LL_RCC_HSE_GetExternalClockType(void)1596 __STATIC_INLINE uint32_t LL_RCC_HSE_GetExternalClockType(void)
1597 {
1598 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSEEXT));
1599 }
1600
1601 /**
1602 * @}
1603 */
1604
1605 /** @defgroup RCC_LL_EF_HSI HSI
1606 * @{
1607 */
1608
1609 /**
1610 * @brief Enable HSI oscillator
1611 * @rmtoll CR HSION LL_RCC_HSI_Enable
1612 * @retval None
1613 */
LL_RCC_HSI_Enable(void)1614 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1615 {
1616 SET_BIT(RCC->CR, RCC_CR_HSION);
1617 }
1618
1619 /**
1620 * @brief Disable HSI oscillator
1621 * @rmtoll CR HSION LL_RCC_HSI_Disable
1622 * @retval None
1623 */
LL_RCC_HSI_Disable(void)1624 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1625 {
1626 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1627 }
1628
1629 /**
1630 * @brief Check if HSI clock is ready
1631 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1632 * @retval State of bit (1 or 0).
1633 */
LL_RCC_HSI_IsReady(void)1634 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1635 {
1636 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
1637 }
1638
1639 /**
1640 * @brief Enable HSI even in stop mode for some peripherals kernel
1641 * @note HSI oscillator is forced ON even in Stop mode
1642 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
1643 * @retval None
1644 */
LL_RCC_HSI_EnableInStopMode(void)1645 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1646 {
1647 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1648 }
1649
1650 /**
1651 * @brief Disable HSI in stop mode for some peripherals kernel
1652 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
1653 * @retval None
1654 */
LL_RCC_HSI_DisableInStopMode(void)1655 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1656 {
1657 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1658 }
1659
1660 /**
1661 * @brief Check if HSI is enabled in stop mode
1662 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
1663 * @retval State of bit (1 or 0).
1664 */
LL_RCC_HSI_IsEnabledInStopMode(void)1665 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
1666 {
1667 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
1668 }
1669
1670 /**
1671 * @brief Check if HSI new divider applied and ready
1672 * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady
1673 * @retval State of bit (1 or 0).
1674 */
LL_RCC_HSI_IsDividerReady(void)1675 __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
1676 {
1677 return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)) ? 1UL : 0UL);
1678 }
1679
1680 /**
1681 * @brief Set HSI divider
1682 * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider
1683 * @param Divider This parameter can be one of the following values:
1684 * @arg @ref LL_RCC_HSI_DIV_1
1685 * @arg @ref LL_RCC_HSI_DIV_2
1686 * @arg @ref LL_RCC_HSI_DIV_4
1687 * @arg @ref LL_RCC_HSI_DIV_8
1688 * @retval None.
1689 */
LL_RCC_HSI_SetDivider(uint32_t Divider)1690 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
1691 {
1692 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
1693 }
1694
1695 /**
1696 * @brief Get HSI divider
1697 * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider
1698 * @retval can be one of the following values:
1699 * @arg @ref LL_RCC_HSI_DIV_1
1700 * @arg @ref LL_RCC_HSI_DIV_2
1701 * @arg @ref LL_RCC_HSI_DIV_4
1702 * @arg @ref LL_RCC_HSI_DIV_8
1703 */
LL_RCC_HSI_GetDivider(void)1704 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
1705 {
1706 return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
1707 }
1708
1709 /**
1710 * @brief Get HSI Calibration value
1711 * @note When HSITRIM is written, HSICAL is updated with the sum of
1712 * HSITRIM and the factory trim value
1713 * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration
1714 * @retval A value between 0 and 4095 (0xFFF)
1715 */
LL_RCC_HSI_GetCalibration(void)1716 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1717 {
1718 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
1719 }
1720
1721 /**
1722 * @brief Set HSI Calibration trimming
1723 * @note user-programmable trimming value that is added to the HSICAL
1724 * @note Default value is 64, which, when added to the HSICAL value,
1725 * should trim the HSI to 64 MHz +/- 1 %
1726 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming
1727 * @param Value can be a value between Min_Data = 0 and Max_Data = 127 (0x7F)
1728 * @retval None
1729 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1730 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1731 {
1732 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1733 }
1734
1735 /**
1736 * @brief Get HSI Calibration trimming
1737 * @rmtoll ICSC3R HSITRIM LL_RCC_HSI_GetCalibTrimming
1738 * @retval A value between Min_Data = 0 and Max_Data = 127 (0x7F)
1739 */
LL_RCC_HSI_GetCalibTrimming(void)1740 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1741 {
1742 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1743 }
1744
1745 /**
1746 * @}
1747 */
1748
1749 /** @defgroup RCC_LL_EF_CSI CSI
1750 * @{
1751 */
1752
1753 /**
1754 * @brief Enable CSI oscillator
1755 * @rmtoll CR CSION LL_RCC_CSI_Enable
1756 * @retval None
1757 */
LL_RCC_CSI_Enable(void)1758 __STATIC_INLINE void LL_RCC_CSI_Enable(void)
1759 {
1760 SET_BIT(RCC->CR, RCC_CR_CSION);
1761 }
1762
1763 /**
1764 * @brief Disable CSI oscillator
1765 * @rmtoll CR CSION LL_RCC_CSI_Disable
1766 * @retval None
1767 */
LL_RCC_CSI_Disable(void)1768 __STATIC_INLINE void LL_RCC_CSI_Disable(void)
1769 {
1770 CLEAR_BIT(RCC->CR, RCC_CR_CSION);
1771 }
1772
1773 /**
1774 * @brief Check if CSI clock is ready
1775 * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady
1776 * @retval State of bit (1 or 0).
1777 */
LL_RCC_CSI_IsReady(void)1778 __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
1779 {
1780 return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY)) ? 1UL : 0UL);
1781 }
1782
1783 /**
1784 * @brief Enable CSI oscillator in Stop mode for some peripherals kernel clock
1785 * @rmtoll CR CSIKERON LL_RCC_CSI_EnableInStopMode
1786 * @retval None
1787 */
LL_RCC_CSI_EnableInStopMode(void)1788 __STATIC_INLINE void LL_RCC_CSI_EnableInStopMode(void)
1789 {
1790 SET_BIT(RCC->CR, RCC_CR_CSIKERON);
1791 }
1792
1793 /**
1794 * @brief Disable CSI oscillator in Stop mode for some peripherals kernel clock
1795 * @rmtoll CR CSIKERON LL_RCC_CSI_DisableInStopMode
1796 * @retval None
1797 */
LL_RCC_CSI_DisableInStopMode(void)1798 __STATIC_INLINE void LL_RCC_CSI_DisableInStopMode(void)
1799 {
1800 CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
1801 }
1802
1803 /**
1804 * @brief Check if CSI is enabled in stop mode
1805 * @rmtoll CR CSIKERON LL_RCC_CSI_IsEnabledInStopMode
1806 * @retval State of bit (1 or 0).
1807 */
LL_RCC_CSI_IsEnabledInStopMode(void)1808 __STATIC_INLINE uint32_t LL_RCC_CSI_IsEnabledInStopMode(void)
1809 {
1810 return ((READ_BIT(RCC->CR, RCC_CR_CSIKERON) == RCC_CR_CSIKERON) ? 1UL : 0UL);
1811 }
1812
1813 /**
1814 * @brief Get CSI Calibration value
1815 * @note When CSITRIM is written, CSICAL is updated with the sum of
1816 * CSITRIM and the factory trim value
1817 * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration
1818 * @retval A value between 0 and 255 (0xFF)
1819 */
LL_RCC_CSI_GetCalibration(void)1820 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
1821 {
1822 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
1823 }
1824
1825 /**
1826 * @brief Set CSI Calibration trimming
1827 * @note user-programmable trimming value that is added to the CSICAL
1828 * @note Default value is 16, which, when added to the CSICAL value,
1829 * should trim the CSI to 4 MHz +/- 1 %
1830 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming
1831 * @param Value can be a value between Min_Data = 0 and Max_Data = 63 (0x3F)
1832 * @retval None
1833 */
LL_RCC_CSI_SetCalibTrimming(uint32_t Value)1834 __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
1835 {
1836 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
1837 }
1838
1839 /**
1840 * @brief Get CSI Calibration trimming
1841 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming
1842 * @retval A value between 0 and 63 (0x3F)
1843 */
LL_RCC_CSI_GetCalibTrimming(void)1844 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
1845 {
1846 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1847 }
1848
1849 /**
1850 * @}
1851 */
1852
1853 /** @defgroup RCC_LL_EF_HSI48 HSI48
1854 * @{
1855 */
1856
1857 /**
1858 * @brief Enable HSI48
1859 * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
1860 * @retval None
1861 */
LL_RCC_HSI48_Enable(void)1862 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1863 {
1864 SET_BIT(RCC->CR, RCC_CR_HSI48ON);
1865 }
1866
1867 /**
1868 * @brief Disable HSI48
1869 * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
1870 * @retval None
1871 */
LL_RCC_HSI48_Disable(void)1872 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1873 {
1874 CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
1875 }
1876
1877 /**
1878 * @brief Check if HSI48 oscillator Ready
1879 * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
1880 * @retval State of bit (1 or 0).
1881 */
LL_RCC_HSI48_IsReady(void)1882 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1883 {
1884 return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL);
1885 }
1886
1887 /**
1888 * @brief Get HSI48 Calibration value
1889 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1890 * @retval A value between 0 and 1023 (0x3FF)
1891 */
LL_RCC_HSI48_GetCalibration(void)1892 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1893 {
1894 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1895 }
1896
1897 /**
1898 * @}
1899 */
1900
1901 /** @defgroup RCC_LL_EF_LSE LSE
1902 * @{
1903 */
1904
1905 /**
1906 * @brief Enable Low Speed External (LSE) crystal.
1907 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1908 * @retval None
1909 */
LL_RCC_LSE_Enable(void)1910 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1911 {
1912 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1913 }
1914
1915 /**
1916 * @brief Disable Low Speed External (LSE) crystal.
1917 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1918 * @retval None
1919 */
LL_RCC_LSE_Disable(void)1920 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1921 {
1922 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1923 }
1924
1925 /**
1926 * @brief Check if LSE oscillator Ready
1927 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1928 * @retval State of bit (1 or 0).
1929 */
LL_RCC_LSE_IsReady(void)1930 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1931 {
1932 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
1933 }
1934
1935 /**
1936 * @brief Enable external clock source (LSE bypass).
1937 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1938 * @retval None
1939 */
LL_RCC_LSE_EnableBypass(void)1940 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1941 {
1942 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1943 }
1944
1945 /**
1946 * @brief Disable external clock source (LSE bypass).
1947 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1948 * @retval None
1949 */
LL_RCC_LSE_DisableBypass(void)1950 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1951 {
1952 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1953 }
1954
1955 /**
1956 * @brief Set external LSE clock type in Bypass mode
1957 * @note This bit can be written only if the LSE oscillator is disabled
1958 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SetExternalClockType
1959 * @param LSEClockMode This parameter can be one of the following values:
1960 * @arg @ref LL_RCC_LSE_ANALOG_TYPE
1961 * @arg @ref LL_RCC_LSE_DIGITAL_TYPE (*)
1962 * @retval None
1963 *
1964 * (*) not to be used if RTC is active
1965 */
LL_RCC_LSE_SetExternalClockType(uint32_t LSEClockMode)1966 __STATIC_INLINE void LL_RCC_LSE_SetExternalClockType(uint32_t LSEClockMode)
1967 {
1968 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEEXT, LSEClockMode);
1969 }
1970
1971 /**
1972 * @brief Get external LSE clock type in Bypass mode
1973 * @rmtoll BDCR LSEEXT LL_RCC_LSE_GetExternalClockType
1974 * @retval Returned value can be one of the following values:
1975 * @arg @ref LL_RCC_LSE_ANALOG_TYPE
1976 * @arg @ref LL_RCC_LSE_DIGITAL_TYPE
1977 */
LL_RCC_LSE_GetExternalClockType(void)1978 __STATIC_INLINE uint32_t LL_RCC_LSE_GetExternalClockType(void)
1979 {
1980 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEEXT));
1981 }
1982
1983 /**
1984 * @brief Set LSE oscillator drive capability
1985 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1986 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1987 * @param LSEDrive This parameter can be one of the following values:
1988 * @arg @ref LL_RCC_LSEDRIVE_LOW
1989 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1990 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1991 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1992 * @retval None
1993 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1994 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1995 {
1996 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1997 }
1998
1999 /**
2000 * @brief Get LSE oscillator drive capability
2001 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
2002 * @retval Returned value can be one of the following values:
2003 * @arg @ref LL_RCC_LSEDRIVE_LOW
2004 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2005 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2006 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2007 */
LL_RCC_LSE_GetDriveCapability(void)2008 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2009 {
2010 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2011 }
2012
2013 /**
2014 * @brief Enable Clock security system on LSE.
2015 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
2016 * @retval None
2017 */
LL_RCC_LSE_EnableCSS(void)2018 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
2019 {
2020 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2021 }
2022
2023 /**
2024 * @brief Disable Clock security system on LSE.
2025 * @note Clock security system can be disabled only after a LSE
2026 * failure detection. In that case it MUST be disabled by software.
2027 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
2028 * @retval None
2029 */
LL_RCC_LSE_DisableCSS(void)2030 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
2031 {
2032 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2033 }
2034
2035 /**
2036 * @brief Check if CSS on LSE failure Detection
2037 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
2038 * @retval State of bit (1 or 0).
2039 */
LL_RCC_LSE_IsCSSDetected(void)2040 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
2041 {
2042 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL);
2043 }
2044
2045 /**
2046 * @}
2047 */
2048
2049 /** @defgroup RCC_LL_EF_LSI LSI
2050 * @{
2051 */
2052
2053 /**
2054 * @brief Enable LSI Oscillator
2055 * @rmtoll BDCR LSION LL_RCC_LSI_Enable
2056 * @retval None
2057 */
LL_RCC_LSI_Enable(void)2058 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2059 {
2060 SET_BIT(RCC->BDCR, RCC_BDCR_LSION);
2061 }
2062
2063 /**
2064 * @brief Disable LSI Oscillator
2065 * @rmtoll BDCR LSION LL_RCC_LSI_Disable
2066 * @retval None
2067 */
LL_RCC_LSI_Disable(void)2068 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2069 {
2070 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION);
2071 }
2072
2073 /**
2074 * @brief Check if LSI is Ready
2075 * @rmtoll BDCR LSIRDY LL_RCC_LSI_IsReady
2076 * @retval State of bit (1 or 0).
2077 */
LL_RCC_LSI_IsReady(void)2078 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2079 {
2080 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) ? 1UL : 0UL);
2081 }
2082
2083
2084 /**
2085 * @}
2086 */
2087
2088
2089 /** @defgroup RCC_LL_EF_LSCO LSCO
2090 * @{
2091 */
2092
2093 /**
2094 * @brief Enable Low Speed Microcontroller Clock Output
2095 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
2096 * @retval None
2097 */
LL_RCC_LSCO_Enable(void)2098 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
2099 {
2100 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2101 }
2102
2103 /**
2104 * @brief Disable Low Speed Microcontroller Clock Output
2105 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
2106 * @retval None
2107 */
LL_RCC_LSCO_Disable(void)2108 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
2109 {
2110 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2111 }
2112
2113 /**
2114 * @brief Configure Low Speed Microcontroller Clock Output selection
2115 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
2116 * @param Source This parameter can be one of the following values:
2117 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2118 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2119 * @retval None
2120 */
LL_RCC_LSCO_SetSource(uint32_t Source)2121 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
2122 {
2123 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
2124 }
2125
2126 /**
2127 * @brief Get Low Speed Microcontroller Clock Output selection
2128 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
2129 * @retval Returned value can be one of the following values:
2130 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2131 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2132 */
LL_RCC_LSCO_GetSource(void)2133 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
2134 {
2135 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
2136 }
2137
2138 /**
2139 * @}
2140 */
2141
2142 /** @defgroup RCC_LL_EF_System System
2143 * @{
2144 */
2145
2146 /**
2147 * @brief Configure the system clock source
2148 * @rmtoll CFGR1 SW LL_RCC_SetSysClkSource
2149 * @param Source This parameter can be one of the following values:
2150 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2151 * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
2152 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2153 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
2154 * @retval None
2155 */
LL_RCC_SetSysClkSource(uint32_t Source)2156 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2157 {
2158 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source);
2159 }
2160
2161 /**
2162 * @brief Get the system clock source
2163 * @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource
2164 * @retval Returned value can be one of the following values:
2165 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2166 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
2167 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2168 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
2169 */
LL_RCC_GetSysClkSource(void)2170 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2171 {
2172 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS));
2173 }
2174
2175 /**
2176 * @brief Set AHB prescaler
2177 * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler
2178 * @param Prescaler This parameter can be one of the following values:
2179 * @arg @ref LL_RCC_SYSCLK_DIV_1
2180 * @arg @ref LL_RCC_SYSCLK_DIV_2
2181 * @arg @ref LL_RCC_SYSCLK_DIV_4
2182 * @arg @ref LL_RCC_SYSCLK_DIV_8
2183 * @arg @ref LL_RCC_SYSCLK_DIV_16
2184 * @arg @ref LL_RCC_SYSCLK_DIV_64
2185 * @arg @ref LL_RCC_SYSCLK_DIV_128
2186 * @arg @ref LL_RCC_SYSCLK_DIV_256
2187 * @arg @ref LL_RCC_SYSCLK_DIV_512
2188 * @retval None
2189 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2190 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2191 {
2192 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler);
2193 }
2194
2195 /**
2196 * @brief Set Systick clock source
2197 * @rmtoll CCIPR4 SYSTICKSEL LL_RCC_SetSystickClockSource
2198 * @param SystickSource This parameter can be one of the following values:
2199 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
2200 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
2201 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
2202 * @retval None
2203 */
LL_RCC_SetSystickClockSource(uint32_t SystickSource)2204 __STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource)
2205 {
2206 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, SystickSource);
2207 }
2208
2209 /**
2210 * @brief Set APB1 prescaler
2211 * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler
2212 * @param Prescaler This parameter can be one of the following values:
2213 * @arg @ref LL_RCC_APB1_DIV_1
2214 * @arg @ref LL_RCC_APB1_DIV_2
2215 * @arg @ref LL_RCC_APB1_DIV_4
2216 * @arg @ref LL_RCC_APB1_DIV_8
2217 * @arg @ref LL_RCC_APB1_DIV_16
2218 * @retval None
2219 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2220 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2221 {
2222 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler);
2223 }
2224
2225 /**
2226 * @brief Set APB2 prescaler
2227 * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler
2228 * @param Prescaler This parameter can be one of the following values:
2229 * @arg @ref LL_RCC_APB2_DIV_1
2230 * @arg @ref LL_RCC_APB2_DIV_2
2231 * @arg @ref LL_RCC_APB2_DIV_4
2232 * @arg @ref LL_RCC_APB2_DIV_8
2233 * @arg @ref LL_RCC_APB2_DIV_16
2234 * @retval None
2235 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2236 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2237 {
2238 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler);
2239 }
2240
2241 /**
2242 * @brief Set APB3 prescaler
2243 * @rmtoll CFGR3 PPRE3 LL_RCC_SetAPB3Prescaler
2244 * @param Prescaler This parameter can be one of the following values:
2245 * @arg @ref LL_RCC_APB3_DIV_1
2246 * @arg @ref LL_RCC_APB3_DIV_2
2247 * @arg @ref LL_RCC_APB3_DIV_4
2248 * @arg @ref LL_RCC_APB3_DIV_8
2249 * @arg @ref LL_RCC_APB3_DIV_16
2250 * @retval None
2251 */
LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)2252 __STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
2253 {
2254 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE3, Prescaler);
2255 }
2256
2257 /**
2258 * @brief Get AHB prescaler
2259 * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler
2260 * @retval Returned value can be one of the following values:
2261 * @arg @ref LL_RCC_SYSCLK_DIV_1
2262 * @arg @ref LL_RCC_SYSCLK_DIV_2
2263 * @arg @ref LL_RCC_SYSCLK_DIV_4
2264 * @arg @ref LL_RCC_SYSCLK_DIV_8
2265 * @arg @ref LL_RCC_SYSCLK_DIV_16
2266 * @arg @ref LL_RCC_SYSCLK_DIV_64
2267 * @arg @ref LL_RCC_SYSCLK_DIV_128
2268 * @arg @ref LL_RCC_SYSCLK_DIV_256
2269 * @arg @ref LL_RCC_SYSCLK_DIV_512
2270 */
LL_RCC_GetAHBPrescaler(void)2271 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2272 {
2273 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE));
2274 }
2275
2276 /**
2277 * @brief Get Sysctick clock source
2278 * @rmtoll CCIPR4 SYSTICKSEL LL_RCC_SetSystickClockSource
2279 * @retval Returned value can be one of the following values:
2280 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
2281 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
2282 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
2283 */
LL_RCC_GetSystickClockSource(void)2284 __STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void)
2285 {
2286 return (uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL));
2287 }
2288
2289 /**
2290 * @brief Get APB1 prescaler
2291 * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler
2292 * @retval Returned value can be one of the following values:
2293 * @arg @ref LL_RCC_APB1_DIV_1
2294 * @arg @ref LL_RCC_APB1_DIV_2
2295 * @arg @ref LL_RCC_APB1_DIV_4
2296 * @arg @ref LL_RCC_APB1_DIV_8
2297 * @arg @ref LL_RCC_APB1_DIV_16
2298 */
LL_RCC_GetAPB1Prescaler(void)2299 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2300 {
2301 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1));
2302 }
2303
2304 /**
2305 * @brief Get APB2 prescaler
2306 * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler
2307 * @retval Returned value can be one of the following values:
2308 * @arg @ref LL_RCC_APB2_DIV_1
2309 * @arg @ref LL_RCC_APB2_DIV_2
2310 * @arg @ref LL_RCC_APB2_DIV_4
2311 * @arg @ref LL_RCC_APB2_DIV_8
2312 * @arg @ref LL_RCC_APB2_DIV_16
2313 */
LL_RCC_GetAPB2Prescaler(void)2314 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2315 {
2316 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2));
2317 }
2318
2319 /**
2320 * @brief Get APB3 prescaler
2321 * @rmtoll CFGR3 PPRE3 LL_RCC_GetAPB2Prescaler
2322 * @retval Returned value can be one of the following values:
2323 * @arg @ref LL_RCC_APB3_DIV_1
2324 * @arg @ref LL_RCC_APB3_DIV_2
2325 * @arg @ref LL_RCC_APB3_DIV_4
2326 * @arg @ref LL_RCC_APB3_DIV_8
2327 * @arg @ref LL_RCC_APB3_DIV_16
2328 */
LL_RCC_GetAPB3Prescaler(void)2329 __STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
2330 {
2331 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE3));
2332 }
2333
2334 /**
2335 * @brief Set System Clock After Wake-Up From Stop mode
2336 * @rmtoll CFGR1 STOPWUCK LL_RCC_SetClkAfterWakeFromStop
2337 * @param Clock This parameter can be one of the following values:
2338 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2339 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2340 * @retval None
2341 */
LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)2342 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
2343 {
2344 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, Clock);
2345 }
2346
2347 /**
2348 * @brief Get System Clock After Wake-Up From Stop mode
2349 * @rmtoll CFGR1 STOPWUCK LL_RCC_GetClkAfterWakeFromStop
2350 * @retval Returned value can be one of the following values:
2351 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2352 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2353 */
LL_RCC_GetClkAfterWakeFromStop(void)2354 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
2355 {
2356 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK));
2357 }
2358 /**
2359 * @}
2360 */
2361
2362 /** @defgroup RCC_LL_EF_MCO MCO
2363 * @{
2364 */
2365
2366 /**
2367 * @brief Configure MCO1 (pin PA8) or MCO2 (pin PC9)
2368 * @rmtoll CFGR1 MCO1 LL_RCC_ConfigMCO\n
2369 * CFGR1 MCO1PRE LL_RCC_ConfigMCO\n
2370 * CFGR1 MCO2 LL_RCC_ConfigMCO\n
2371 * CFGR1 MCO2PRE LL_RCC_ConfigMCO
2372 * @param MCOxSource This parameter can be one of the following values:
2373 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2374 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2375 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2376 * @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK
2377 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
2378 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
2379 * @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK
2380 * @arg @ref LL_RCC_MCO2SOURCE_HSE
2381 * @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK
2382 * @arg @ref LL_RCC_MCO2SOURCE_CSI
2383 * @arg @ref LL_RCC_MCO2SOURCE_LSI
2384 * @param MCOxPrescaler This parameter can be one of the following values:
2385 * @arg @ref LL_RCC_MCO1_DIV_1
2386 * @arg @ref LL_RCC_MCO1_DIV_2
2387 * @arg @ref LL_RCC_MCO1_DIV_3
2388 * @arg @ref LL_RCC_MCO1_DIV_4
2389 * @arg @ref LL_RCC_MCO1_DIV_5
2390 * @arg @ref LL_RCC_MCO1_DIV_6
2391 * @arg @ref LL_RCC_MCO1_DIV_7
2392 * @arg @ref LL_RCC_MCO1_DIV_8
2393 * @arg @ref LL_RCC_MCO1_DIV_9
2394 * @arg @ref LL_RCC_MCO1_DIV_10
2395 * @arg @ref LL_RCC_MCO1_DIV_11
2396 * @arg @ref LL_RCC_MCO1_DIV_12
2397 * @arg @ref LL_RCC_MCO1_DIV_13
2398 * @arg @ref LL_RCC_MCO1_DIV_14
2399 * @arg @ref LL_RCC_MCO1_DIV_15
2400 * @arg @ref LL_RCC_MCO2_DIV_1
2401 * @arg @ref LL_RCC_MCO2_DIV_2
2402 * @arg @ref LL_RCC_MCO2_DIV_3
2403 * @arg @ref LL_RCC_MCO2_DIV_4
2404 * @arg @ref LL_RCC_MCO2_DIV_5
2405 * @arg @ref LL_RCC_MCO2_DIV_6
2406 * @arg @ref LL_RCC_MCO2_DIV_7
2407 * @arg @ref LL_RCC_MCO2_DIV_8
2408 * @arg @ref LL_RCC_MCO2_DIV_9
2409 * @arg @ref LL_RCC_MCO2_DIV_10
2410 * @arg @ref LL_RCC_MCO2_DIV_11
2411 * @arg @ref LL_RCC_MCO2_DIV_12
2412 * @arg @ref LL_RCC_MCO2_DIV_13
2413 * @arg @ref LL_RCC_MCO2_DIV_14
2414 * @arg @ref LL_RCC_MCO2_DIV_15
2415 * @retval None
2416 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2417 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2418 {
2419 MODIFY_REG(RCC->CFGR1, (MCOxSource << 16U) | (MCOxPrescaler << 16U), \
2420 (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
2421 }
2422
2423 /**
2424 * @}
2425 */
2426
2427
2428 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2429 * @{
2430 */
2431
2432 /**
2433 * @brief Configure periph clock source
2434 * @rmtoll CCIPR1 * LL_RCC_SetClockSource\n
2435 * CCIPR2 * LL_RCC_SetClockSource\n
2436 * CCIPR3 * LL_RCC_SetClockSource\n
2437 * CCIPR4 * LL_RCC_SetClockSource\n
2438 * CCIPR5 * LL_RCC_SetClockSource
2439 * @param ClkSource This parameter can be one of the following values:
2440 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2441 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
2442 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*)
2443 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2444 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
2445 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2446 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2447 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q
2448 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*)
2449 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2450 * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI
2451 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2452 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2453 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q
2454 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*)
2455 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2456 * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI
2457 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2458 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*)
2459 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*)
2460 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*)
2461 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*)
2462 * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*)
2463 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*)
2464 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*)
2465 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*)
2466 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*)
2467 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*)
2468 * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*)
2469 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*)
2470 * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*)
2471 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*)
2472 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*)
2473 * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*)
2474 * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*)
2475 * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*)
2476 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
2477 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q (*)
2478 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q (*)
2479 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
2480 * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI (*)
2481 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
2482 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
2483 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q (*)
2484 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q (*)
2485 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
2486 * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI (*)
2487 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
2488 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 (*)
2489 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q (*)
2490 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q (*)
2491 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI (*)
2492 * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI (*)
2493 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE (*)
2494 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 (*)
2495 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q (*)
2496 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q (*)
2497 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI (*)
2498 * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI (*)
2499 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE (*)
2500 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1 (*)
2501 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q (*)
2502 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q (*)
2503 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI (*)
2504 * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI (*)
2505 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE (*)
2506 * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1 (*)
2507 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q (*)
2508 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q (*)
2509 * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI (*)
2510 * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI (*)
2511 * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE (*)
2512 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
2513 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
2514 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*)
2515 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2516 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
2517 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2518 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2519 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R
2520 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R
2521 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2522 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
2523 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2524 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R
2525 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R
2526 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2527 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI
2528 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*)
2529 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*)
2530 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
2531 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*)
2532 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*)
2533 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*)
2534 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
2535 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*)
2536 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
2537 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*)
2538 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (*)
2539 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
2540 * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE
2541 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (*)
2542 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (*)
2543 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (*)
2544 * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (*)
2545 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
2546 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
2547 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P
2548 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN
2549 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
2550 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q
2551 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P (*)
2552 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*)
2553 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN
2554 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
2555 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1Q
2556 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2P (*)
2557 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3P (*)
2558 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN
2559 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
2560 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*)
2561 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*)
2562 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*)
2563 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*)
2564 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*)
2565 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*)
2566 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*)
2567 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*)
2568 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*)
2569 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*)
2570 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*)
2571 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*)
2572 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*)
2573 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*)
2574 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*)
2575 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*)
2576 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*)
2577 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*)
2578 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3
2579 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2580 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2581 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2582 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2583 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2584 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2585 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P (*)
2586 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*)
2587 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2588 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2589 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2590 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*)
2591 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*)
2592 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*)
2593 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*)
2594 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*)
2595 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*)
2596 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*)
2597 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*)
2598 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*)
2599 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*)
2600 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*)
2601 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*)
2602 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*)
2603 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*)
2604 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*)
2605 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*)
2606 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*)
2607 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*)
2608 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*)
2609 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*)
2610 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*)
2611 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*)
2612 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*)
2613 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*)
2614 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q (*)
2615 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P (*)
2616 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P (*)
2617 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
2618 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP (*)
2619 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q (*)
2620 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P (*)
2621 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P (*)
2622 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
2623 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP (*)
2624 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q (*)
2625 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R (*)
2626 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q (*)
2627 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R (*)
2628 *
2629 * (*) value not defined in all devices.
2630 * @retval None
2631 */
LL_RCC_SetClockSource(uint32_t ClkSource)2632 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
2633 {
2634 uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CCIPR1 + LL_CLKSOURCE_REG(ClkSource));
2635 MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
2636 }
2637
2638 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2639 * @{
2640 */
2641
2642 /**
2643 * @brief Configure USARTx kernel clock source
2644 * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n
2645 * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n
2646 * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource\n
2647 * CCIPR1 USART6SEL LL_RCC_SetUSARTClockSource\n
2648 * CCIPR1 USART10SEL LL_RCC_SetUSARTClockSource\n
2649 * CCIPR2 USART11SEL LL_RCC_SetUSARTClockSource
2650 * @param USARTxSource This parameter can be one of the following values:
2651 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2652 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
2653 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*)
2654 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2655 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
2656 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2657 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2658 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q
2659 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*)
2660 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2661 * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI
2662 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2663 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2664 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q
2665 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*)
2666 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2667 * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI
2668 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2669 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*)
2670 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*)
2671 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*)
2672 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*)
2673 * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*)
2674 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*)
2675 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*)
2676 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*)
2677 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*)
2678 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*)
2679 * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*)
2680 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*)
2681 * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*)
2682 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*)
2683 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*)
2684 * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*)
2685 * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*)
2686 * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*)
2687 *
2688 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
2689 * @retval None
2690 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)2691 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2692 {
2693 LL_RCC_SetClockSource(USARTxSource);
2694 }
2695
2696 #if defined(UART4)
2697 /**
2698 * @brief Configure UARTx kernel clock source
2699 * @rmtoll CCIPR1 UART4SEL LL_RCC_SetUARTClockSource\n
2700 * CCIPR1 UART5SEL LL_RCC_SetUARTClockSource\n
2701 * CCIPR1 UART7SEL LL_RCC_SetUARTClockSource\n
2702 * CCIPR1 UART8SEL LL_RCC_SetUARTClockSource\n
2703 * CCIPR1 UART9SEL LL_RCC_SetUARTClockSource\n
2704 * CCIPR2 UART12SEL LL_RCC_SetUARTClockSource
2705 * @param UARTxSource This parameter can be one of the following values:
2706 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2707 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q
2708 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q
2709 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2710 * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI
2711 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2712 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2713 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q
2714 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q
2715 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2716 * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI
2717 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2718 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
2719 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q
2720 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q
2721 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
2722 * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI
2723 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
2724 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
2725 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q
2726 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q
2727 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
2728 * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI
2729 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
2730 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1
2731 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q
2732 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q
2733 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
2734 * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI
2735 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
2736 * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1
2737 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q
2738 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q
2739 * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI
2740 * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI
2741 * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE
2742 * @retval None
2743 */
LL_RCC_SetUARTClockSource(uint32_t UARTxSource)2744 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
2745 {
2746 LL_RCC_SetClockSource(UARTxSource);
2747 }
2748 #endif /* UART4 */
2749
2750 /**
2751 * @brief Configure LPUARTx kernel clock source
2752 * @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource
2753 * @param LPUARTxSource This parameter can be one of the following values:
2754 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
2755 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
2756 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*)
2757 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2758 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
2759 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2760 *
2761 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
2762 * @retval None
2763 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)2764 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
2765 {
2766 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource);
2767 }
2768
2769 /**
2770 * @brief Configure I2Cx kernel clock source
2771 * @rmtoll CCIPR4 I2C1SEL LL_RCC_SetI2CClockSource\n
2772 * CCIPR4 I2C2SEL LL_RCC_SetI2CClockSource\n
2773 * CCIPR4 I2C3SEL LL_RCC_SetI2CClockSource\n
2774 * CCIPR4 I2C4SEL LL_RCC_SetI2CClockSource
2775 * @param I2CxSource This parameter can be one of the following values:
2776 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2777 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R (*)
2778 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R (**)
2779 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2780 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
2781 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2782 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R (*)
2783 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R (**)
2784 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2785 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI
2786 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*)
2787 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*)
2788 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
2789 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*)
2790 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*)
2791 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*)
2792 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
2793 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*)
2794 *
2795 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
2796 * (**) : For stm32h503xx family line only.
2797 * @retval None
2798 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)2799 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
2800 {
2801 LL_RCC_SetClockSource(I2CxSource);
2802 }
2803
2804 /**
2805 * @brief Configure I3Cx kernel clock source
2806 * @rmtoll CCIPR4 I3C1SEL LL_RCC_SetI3CClockSource\n
2807 * CCIPR4 I3C2SEL LL_RCC_SetI3CClockSource
2808 * @param I3CxSource This parameter can be one of the following values:
2809 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
2810 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*)
2811 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (**)
2812 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
2813 * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE
2814 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (**)
2815 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (**)
2816 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (**)
2817 * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**)
2818 * @retval None
2819 *
2820 * (*) : For stm32h56xxx and stm32h57xxx family lines.
2821 * (**) : For stm32h503xx family line.
2822 */
LL_RCC_SetI3CClockSource(uint32_t I3CxSource)2823 __STATIC_INLINE void LL_RCC_SetI3CClockSource(uint32_t I3CxSource)
2824 {
2825 LL_RCC_SetClockSource(I3CxSource);
2826 }
2827
2828 /**
2829 * @brief Configure SPIx kernel clock source
2830 * @rmtoll CCIPR3 SPI1SEL LL_RCC_SetSPIClockSource\n
2831 * CCIPR3 SPI2SEL LL_RCC_SetSPIClockSource\n
2832 * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource\n
2833 * CCIPR3 SPI4SEL LL_RCC_SetSPIClockSource\n
2834 * CCIPR3 SPI5SEL LL_RCC_SetSPIClockSource\n
2835 * CCIPR3 SPI6SEL LL_RCC_SetSPIClockSource
2836 * @param SPIxSource This parameter can be one of the following values:
2837 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
2838 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
2839 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P (*)
2840 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN
2841 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
2842 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q
2843 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P
2844 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*)
2845 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN
2846 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
2847 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1P
2848 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2Q
2849 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3Q (*)
2850 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN
2851 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
2852 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*)
2853 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*)
2854 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*)
2855 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*)
2856 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*)
2857 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*)
2858 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*)
2859 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*)
2860 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*)
2861 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*)
2862 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*)
2863 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*)
2864 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*)
2865 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*)
2866 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*)
2867 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*)
2868 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*)
2869 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*)
2870 *
2871 * (*) : For stm32h56xxx and stm32h57xxx family lines.
2872 * @retval None
2873 */
LL_RCC_SetSPIClockSource(uint32_t SPIxSource)2874 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource)
2875 {
2876 LL_RCC_SetClockSource(SPIxSource);
2877 }
2878
2879 /**
2880 * @brief Configure LPTIMx kernel clock source
2881 * @rmtoll CCIPR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n
2882 * CCIPR2 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
2883 * CCIPR2 LPTIM3SEL LL_RCC_SetLPTIMClockSource\n
2884 * CCIPR2 LPTIM4SEL LL_RCC_SetLPTIMClockSource\n
2885 * CCIPR2 LPTIM5SEL LL_RCC_SetLPTIMClockSource\n
2886 * CCIPR2 LPTIM6SEL LL_RCC_SetLPTIMClockSource
2887 * @param LPTIMxSource This parameter can be one of the following values:
2888 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3
2889 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2890 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R (*)
2891 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2892 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2893 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2894 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2895 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
2896 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*)
2897 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2898 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2899 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2900 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*)
2901 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*)
2902 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*)
2903 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*)
2904 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*)
2905 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*)
2906 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*)
2907 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*)
2908 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*)
2909 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*)
2910 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*)
2911 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*)
2912 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*)
2913 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*)
2914 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*)
2915 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*)
2916 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*)
2917 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*)
2918 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*)
2919 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*)
2920 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*)
2921 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*)
2922 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*)
2923 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*)
2924 *
2925 * (*) : For stm32h56xxx and stm32h57xxx family lines.
2926 * @retval None
2927 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)2928 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2929 {
2930 LL_RCC_SetClockSource(LPTIMxSource);
2931 }
2932
2933 /**
2934 * @brief Configure FDCAN kernel clock source
2935 * @rmtoll CCIPR5 FDCANSEL LL_RCC_SetFDCANClockSource
2936 * @param FDCANxSource This parameter can be one of the following values:
2937 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
2938 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
2939 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
2940 * @retval None
2941 *
2942 */
LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)2943 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
2944 {
2945 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_FDCANSEL, FDCANxSource);
2946 }
2947
2948 #if defined(SAI1)
2949 /**
2950 * @brief Configure SAIx kernel clock source
2951 * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n
2952 * CCIPR2 SAI2SEL LL_RCC_SetSAIClockSource
2953 * @param SAIxSource This parameter can be one of the following values:
2954 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
2955 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
2956 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
2957 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2958 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
2959 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q
2960 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P
2961 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P
2962 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
2963 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
2964 * @retval None
2965 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)2966 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
2967 {
2968 LL_RCC_SetClockSource(SAIxSource);
2969 }
2970 #endif /* SAI1 */
2971
2972 #if defined(SDMMC1)
2973 /**
2974 * @brief Configure SDMMCx kernel clock source
2975 * @rmtoll CCIPR4 SDMMC1SEL LL_RCC_SetSDMMCClockSource
2976 * @rmtoll CCIPR4 SDMMC2SEL LL_RCC_SetSDMMCClockSource
2977 * @param SDMMCxSource This parameter can be one of the following values:
2978 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q
2979 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R
2980 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q
2981 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R
2982 * @retval None
2983 */
LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)2984 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
2985 {
2986 LL_RCC_SetClockSource(SDMMCxSource);
2987 }
2988 #endif /* SDMMC1 */
2989
2990 /**
2991 * @brief Configure RNG kernel clock source
2992 * @rmtoll CCIPR5 RNGSEL LL_RCC_SetRNGClockSource
2993 * @param RNGxSource This parameter can be one of the following values:
2994 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
2995 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
2996 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2997 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2998 * @retval None
2999 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)3000 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
3001 {
3002 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_RNGSEL, RNGxSource);
3003 }
3004
3005 /**
3006 * @brief Configure USB clock source
3007 * @rmtoll CCIPR4 USBSEL LL_RCC_SetUSBClockSource
3008 * @param USBxSource This parameter can be one of the following values:
3009 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE
3010 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3011 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q (*)
3012 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3013 *
3014 * (*) : For stm32h56xxx and stm32h57xxx family lines.
3015 * @retval None
3016 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)3017 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
3018 {
3019 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_USBSEL, USBxSource);
3020 }
3021
3022 /**
3023 * @brief Configure ADCx kernel clock source
3024 * @rmtoll CCIPR5 ADCDACSEL LL_RCC_SetADCDACClockSource
3025 * @param ADCDACxSource This parameter can be one of the following values:
3026 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK
3027 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK
3028 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2R
3029 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE
3030 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSI
3031 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_CSI
3032 * @retval None
3033 */
LL_RCC_SetADCDACClockSource(uint32_t ADCDACxSource)3034 __STATIC_INLINE void LL_RCC_SetADCDACClockSource(uint32_t ADCDACxSource)
3035 {
3036 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ADCDACSEL, ADCDACxSource);
3037 }
3038
3039 /**
3040 * @brief Configure DAC low-power kernel clock source
3041 * @rmtoll CCIPR5 DACSEL LL_RCC_SetDACLPClockSource
3042 * @param DACLPxSource This parameter can be one of the following values:
3043 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSE
3044 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSI
3045 * @retval None
3046 */
LL_RCC_SetDACLPClockSource(uint32_t DACLPxSource)3047 __STATIC_INLINE void LL_RCC_SetDACLPClockSource(uint32_t DACLPxSource)
3048 {
3049 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_DACSEL, DACLPxSource);
3050 }
3051
3052 #if defined(CEC)
3053 /**
3054 * @brief Configure CECx kernel clock source
3055 * @rmtoll CCIPR5 CECSEL LL_RCC_SetCECClockSource
3056 * @param CECxSource This parameter can be one of the following values:
3057 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3058 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3059 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3060 * @retval None
3061 */
LL_RCC_SetCECClockSource(uint32_t CECxSource)3062 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
3063 {
3064 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CECSEL, CECxSource);
3065 }
3066 #endif /* CEC */
3067
3068 #if defined(OCTOSPI1)
3069 /**
3070 * @brief Configure OCTOSPIx kernel clock source
3071 * @rmtoll CCIPR4 OCTOSPISEL LL_RCC_SetOCTOSPIClockSource
3072 * @param OCTOSPIxSource This parameter can be one of the following values:
3073 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3074 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3075 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3076 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3077 * @retval None
3078 */
LL_RCC_SetOCTOSPIClockSource(uint32_t OCTOSPIxSource)3079 __STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t OCTOSPIxSource)
3080 {
3081 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OCTOSPISEL, OCTOSPIxSource);
3082 }
3083 #endif /* OCTOSPI1 */
3084
3085 /**
3086 * @brief Configure CLKP Kernel clock source
3087 * @rmtoll CCIPR5 CKPERSEL LL_RCC_SetCLKPClockSource
3088 * @param ClkSource This parameter can be one of the following values:
3089 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3090 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3091 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3092 * @arg @ref LL_RCC_CLKP_CLKSOURCE_NONE
3093 * @retval None
3094 */
LL_RCC_SetCLKPClockSource(uint32_t ClkSource)3095 __STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
3096 {
3097 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CKERPSEL, ClkSource);
3098 }
3099
3100 /**
3101 * @brief Get periph clock source
3102 * @rmtoll CCIPR1 * LL_RCC_GetClockSource\n
3103 * CCIPR2 * LL_RCC_GetClockSource\n
3104 * CCIPR3 * LL_RCC_GetClockSource\n
3105 * CCIPR4 * LL_RCC_GetClockSource\n
3106 * CCIPR5 * LL_RCC_GetClockSource
3107 * @param Periph This parameter can be one of the following values:
3108 * @arg @ref LL_RCC_USART1_CLKSOURCE
3109 * @arg @ref LL_RCC_USART2_CLKSOURCE
3110 * @arg @ref LL_RCC_USART3_CLKSOURCE
3111 * @arg @ref LL_RCC_USART6_CLKSOURCE (*)
3112 * @arg @ref LL_RCC_USART10_CLKSOURCE (*)
3113 * @arg @ref LL_RCC_USART11_CLKSOURCE (*)
3114 * @arg @ref LL_RCC_UART4_CLKSOURCE (*)
3115 * @arg @ref LL_RCC_UART5_CLKSOURCE (*)
3116 * @arg @ref LL_RCC_UART7_CLKSOURCE (*)
3117 * @arg @ref LL_RCC_UART8_CLKSOURCE (*)
3118 * @arg @ref LL_RCC_UART9_CLKSOURCE (*)
3119 * @arg @ref LL_RCC_UART12_CLKSOURCE (*)
3120 * @arg @ref LL_RCC_SPI1_CLKSOURCE
3121 * @arg @ref LL_RCC_SPI2_CLKSOURCE
3122 * @arg @ref LL_RCC_SPI3_CLKSOURCE
3123 * @arg @ref LL_RCC_SPI4_CLKSOURCE (*)
3124 * @arg @ref LL_RCC_SPI5_CLKSOURCE (*)
3125 * @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
3126 * @arg @ref LL_RCC_I2C1_CLKSOURCE
3127 * @arg @ref LL_RCC_I2C2_CLKSOURCE
3128 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
3129 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
3130 * @arg @ref LL_RCC_I3C1_CLKSOURCE
3131 * @arg @ref LL_RCC_I3C2_CLKSOURCE (*)
3132 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3133 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3134 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE (*)
3135 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE (*)
3136 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE (*)
3137 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE (*)
3138 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
3139 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
3140 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*)
3141 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
3142 * @retval Returned value can be one of the following values:
3143 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
3144 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
3145 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*)
3146 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
3147 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
3148 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
3149 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
3150 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q
3151 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*)
3152 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
3153 * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI
3154 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
3155 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
3156 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q
3157 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*)
3158 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
3159 * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI
3160 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
3161 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*)
3162 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*)
3163 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*)
3164 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*)
3165 * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*)
3166 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*)
3167 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*)
3168 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*)
3169 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*)
3170 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*)
3171 * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*)
3172 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*)
3173 * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*)
3174 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*)
3175 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*)
3176 * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*)
3177 * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*)
3178 * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*)
3179 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
3180 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q (*)
3181 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q (*)
3182 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
3183 * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI (*)
3184 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
3185 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
3186 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q (*)
3187 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q (*)
3188 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
3189 * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI (*)
3190 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
3191 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 (*)
3192 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q (*)
3193 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q (*)
3194 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI (*)
3195 * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI (*)
3196 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE (*)
3197 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 (*)
3198 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q (*)
3199 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q (*)
3200 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI (*)
3201 * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI (*)
3202 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE (*)
3203 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1 (*)
3204 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q (*)
3205 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q (*)
3206 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI (*)
3207 * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI (*)
3208 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE (*)
3209 * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1 (*)
3210 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q (*)
3211 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q (*)
3212 * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI (*)
3213 * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI (*)
3214 * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE (*)
3215 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
3216 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
3217 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*)
3218 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3219 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
3220 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3221 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
3222 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R
3223 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R
3224 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
3225 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
3226 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
3227 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R
3228 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R
3229 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
3230 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI
3231 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*)
3232 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*)
3233 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
3234 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*)
3235 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*)
3236 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*)
3237 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
3238 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*)
3239 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
3240 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*)
3241 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (*)
3242 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
3243 * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE
3244 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (*)
3245 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (*)
3246 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (*)
3247 * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (*)
3248 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
3249 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
3250 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P
3251 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN
3252 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
3253 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q
3254 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P (*)
3255 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*)
3256 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN
3257 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
3258 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1Q
3259 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2P (*)
3260 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3P (*)
3261 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN
3262 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
3263 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*)
3264 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*)
3265 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*)
3266 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*)
3267 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*)
3268 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*)
3269 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*)
3270 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*)
3271 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*)
3272 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*)
3273 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*)
3274 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*)
3275 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*)
3276 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*)
3277 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*)
3278 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*)
3279 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*)
3280 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*)
3281 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3
3282 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3283 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3284 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3285 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3286 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3287 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
3288 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P (*)
3289 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*)
3290 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3291 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3292 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3293 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*)
3294 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*)
3295 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*)
3296 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*)
3297 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*)
3298 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*)
3299 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*)
3300 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*)
3301 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*)
3302 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*)
3303 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*)
3304 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*)
3305 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*)
3306 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*)
3307 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*)
3308 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*)
3309 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*)
3310 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*)
3311 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*)
3312 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*)
3313 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*)
3314 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*)
3315 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*)
3316 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*)
3317 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q (*)
3318 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P (*)
3319 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P (*)
3320 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3321 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP (*)
3322 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q (*)
3323 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P (*)
3324 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P (*)
3325 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
3326 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP (*)
3327 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q (*)
3328 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R (*)
3329 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q (*)
3330 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R (*)
3331 *
3332 * (*) value not defined in all devices.
3333 * @retval None
3334 */
LL_RCC_GetClockSource(uint32_t Periph)3335 __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
3336 {
3337 const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CCIPR1) + LL_CLKSOURCE_REG(Periph)));
3338 return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> \
3339 LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT));
3340 }
3341
3342 /**
3343 * @brief Get USARTx kernel clock source
3344 * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n
3345 * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n
3346 * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource\n
3347 * CCIPR1 USART6SEL LL_RCC_GetUSARTClockSource\n
3348 * CCIPR1 USART10SEL LL_RCC_GetUSARTClockSource\n
3349 * CCIPR2 USART11SEL LL_RCC_GetUSARTClockSource
3350 * @param USARTx This parameter can be one of the following values:
3351 * @arg @ref LL_RCC_USART1_CLKSOURCE
3352 * @arg @ref LL_RCC_USART2_CLKSOURCE
3353 * @arg @ref LL_RCC_USART3_CLKSOURCE
3354 * @arg @ref LL_RCC_USART6_CLKSOURCE (*)
3355 * @arg @ref LL_RCC_USART10_CLKSOURCE (*)
3356 * @arg @ref LL_RCC_USART11_CLKSOURCE (*)
3357 * @retval Returned value can be one of the following values:
3358 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
3359 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
3360 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*)
3361 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
3362 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
3363 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
3364 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
3365 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q
3366 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*)
3367 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
3368 * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI
3369 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
3370 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
3371 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q
3372 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*)
3373 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
3374 * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI
3375 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
3376 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*)
3377 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*)
3378 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*)
3379 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*)
3380 * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*)
3381 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*)
3382 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*)
3383 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*)
3384 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*)
3385 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*)
3386 * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*)
3387 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*)
3388 * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*)
3389 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*)
3390 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*)
3391 * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*)
3392 * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*)
3393 * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*)
3394 *
3395 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
3396 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)3397 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
3398 {
3399 return LL_RCC_GetClockSource(USARTx);
3400 }
3401
3402 #if defined(UART4)
3403 /**
3404 * @brief Get UARTx kernel clock source
3405 * @rmtoll CCIPR1 UART4SEL LL_RCC_GetUARTClockSource\n
3406 * CCIPR1 UART5SEL LL_RCC_GetUARTClockSource\n
3407 * CCIPR1 UART7SEL LL_RCC_GetUARTClockSource\n
3408 * CCIPR1 UART8SEL LL_RCC_GetUARTClockSource\n
3409 * CCIPR1 UART9SEL LL_RCC_GetUARTClockSource\n
3410 * CCIPR2 UART12SEL LL_RCC_GetUARTClockSource
3411 * @param USARTx This parameter can be one of the following values:
3412 * @arg @ref LL_RCC_UART4_CLKSOURCE
3413 * @arg @ref LL_RCC_UART5_CLKSOURCE
3414 * @arg @ref LL_RCC_UART7_CLKSOURCE
3415 * @arg @ref LL_RCC_UART8_CLKSOURCE
3416 * @arg @ref LL_RCC_UART9_CLKSOURCE
3417 * @arg @ref LL_RCC_UART12_CLKSOURCE
3418 * @retval Returned value can be one of the following values:
3419 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
3420 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q
3421 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q
3422 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
3423 * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI
3424 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
3425 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
3426 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q
3427 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q
3428 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
3429 * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI
3430 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
3431 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
3432 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q
3433 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q
3434 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
3435 * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI
3436 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
3437 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
3438 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q
3439 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q
3440 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
3441 * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI
3442 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
3443 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1
3444 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q
3445 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q
3446 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
3447 * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI
3448 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
3449 * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1
3450 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q
3451 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q
3452 * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI
3453 * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI
3454 * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE
3455 */
LL_RCC_GetUARTClockSource(uint32_t UARTx)3456 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
3457 {
3458 return LL_RCC_GetClockSource(UARTx);
3459 }
3460 #endif /* UART4 */
3461
3462 /**
3463 * @brief Get LPUARTx kernel clock source
3464 * @rmtoll CCIPR3 LPUART1SEL LL_RCC_GetLPUARTClockSource
3465 * @param LPUARTx This parameter can be one of the following values:
3466 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
3467 * @retval Returned value can be one of the following values:
3468 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
3469 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
3470 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*)
3471 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3472 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
3473 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3474 *
3475 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
3476 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)3477 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
3478 {
3479 return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx));
3480 }
3481
3482 /**
3483 * @brief Get I2Cx kernel clock source
3484 * @rmtoll CCIPR4 I2C1SEL LL_RCC_GetI2CClockSource\n
3485 * CCIPR4 I2C2SEL LL_RCC_GetI2CClockSource\n
3486 * CCIPR4 I2C3SEL LL_RCC_GetI2CClockSource\n
3487 * CCIPR4 I2C4SEL LL_RCC_GetI2CClockSource
3488 * @param I2Cx This parameter can be one of the following values:
3489 * @arg @ref LL_RCC_I2C1_CLKSOURCE
3490 * @arg @ref LL_RCC_I2C2_CLKSOURCE
3491 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
3492 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
3493 * @retval Returned value can be one of the following values:
3494 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
3495 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R (*)
3496 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R (**)
3497 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
3498 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
3499 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
3500 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R (*)
3501 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R (**)
3502 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
3503 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI
3504 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*)
3505 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*)
3506 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
3507 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*)
3508 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*)
3509 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*)
3510 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
3511 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*)
3512 *
3513 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
3514 * (**) : For stm32h503xx family line only.
3515 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)3516 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
3517 {
3518 return LL_RCC_GetClockSource(I2Cx);
3519 }
3520
3521 /**
3522 * @brief Get I3Cx kernel clock source
3523 * @rmtoll CCIPR4 I3C1SEL LL_RCC_GetI3CClockSource\n
3524 * CCIPR4 I3C2SEL LL_RCC_GetI3CClockSource
3525 * @param I3Cx This parameter can be one of the following values:
3526 * @arg @ref LL_RCC_I3C1_CLKSOURCE
3527 * @arg @ref LL_RCC_I3C2_CLKSOURCE (**)
3528 * @retval Returned value can be one of the following values:
3529 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
3530 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*)
3531 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (**)
3532 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
3533 * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE
3534 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (**)
3535 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (**)
3536 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (**)
3537 * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**)
3538 *
3539 * (*) : For stm32h56xxx and stm32h57xxx family lines.
3540 * (**) : For stm32h503xx family line.
3541 */
LL_RCC_GetI3CClockSource(uint32_t I3Cx)3542 __STATIC_INLINE uint32_t LL_RCC_GetI3CClockSource(uint32_t I3Cx)
3543 {
3544 return LL_RCC_GetClockSource(I3Cx);
3545 }
3546
3547 /**
3548 * @brief Get SPIx kernel clock source
3549 * @rmtoll CCIPR3 SPI1SEL LL_RCC_GetSPIClockSource\n
3550 * CCIPR3 SPI2SEL LL_RCC_GetSPIClockSource\n
3551 * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource\n
3552 * CCIPR3 SPI4SEL LL_RCC_GetSPIClockSource\n
3553 * CCIPR3 SPI5SEL LL_RCC_GetSPIClockSource\n
3554 * CCIPR3 SPI6SEL LL_RCC_GetSPIClockSource
3555 * @param SPIx This parameter can be one of the following values:
3556 * @arg @ref LL_RCC_SPI1_CLKSOURCE
3557 * @arg @ref LL_RCC_SPI2_CLKSOURCE
3558 * @arg @ref LL_RCC_SPI3_CLKSOURCE
3559 * @arg @ref LL_RCC_SPI4_CLKSOURCE (*)
3560 * @arg @ref LL_RCC_SPI5_CLKSOURCE (*)
3561 * @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
3562 * @retval Returned value can be one of the following values:
3563 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
3564 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
3565 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P (*)
3566 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN
3567 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
3568 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q
3569 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P
3570 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*)
3571 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN
3572 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
3573 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1P
3574 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2Q
3575 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3Q (*)
3576 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN
3577 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
3578 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*)
3579 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*)
3580 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*)
3581 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*)
3582 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*)
3583 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*)
3584 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*)
3585 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*)
3586 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*)
3587 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*)
3588 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*)
3589 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*)
3590 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*)
3591 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*)
3592 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*)
3593 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*)
3594 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*)
3595 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*)
3596 *
3597 * (*) : For stm32h56xxx and stm32h57xxx family lines.
3598 */
LL_RCC_GetSPIClockSource(uint32_t SPIx)3599 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx)
3600 {
3601 return LL_RCC_GetClockSource(SPIx);
3602 }
3603
3604 /**
3605 * @brief Get LPTIMx kernel clock source
3606 * @rmtoll CCIPR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
3607 * CCIPR2 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
3608 * CCIPR2 LPTIM3SEL LL_RCC_GetLPTIMClockSource\n
3609 * CCIPR2 LPTIM4SEL LL_RCC_GetLPTIMClockSource\n
3610 * CCIPR2 LPTIM5SEL LL_RCC_GetLPTIMClockSource\n
3611 * CCIPR2 LPTIM6SEL LL_RCC_GetLPTIMClockSource
3612 * @param LPTIMx This parameter can be one of the following values:
3613 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3614 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3615 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE (*)
3616 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE (*)
3617 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE (*)
3618 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE (*)
3619 * @retval Returned value can be one of the following values:
3620 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3
3621 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3622 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R (*)
3623 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3624 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3625 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3626 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
3627 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
3628 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*)
3629 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3630 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3631 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3632 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*)
3633 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*)
3634 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*)
3635 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*)
3636 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*)
3637 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*)
3638 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*)
3639 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*)
3640 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*)
3641 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*)
3642 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*)
3643 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*)
3644 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*)
3645 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*)
3646 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*)
3647 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*)
3648 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*)
3649 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*)
3650 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*)
3651 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*)
3652 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*)
3653 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*)
3654 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*)
3655 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*)
3656 *
3657 * (*) : For stm32h56xxx and stm32h57xxx family lines.
3658 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)3659 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
3660 {
3661 return LL_RCC_GetClockSource(LPTIMx);
3662 }
3663
3664 /**
3665 * @brief Enable TIM2,15 and LPTIM2 Input capture clock source
3666 * @rmtoll CCIPR1 TIMICSEL LL_RCC_TIMIC_Enable
3667 * @retval None
3668 */
LL_RCC_TIMIC_Enable(void)3669 __STATIC_INLINE void LL_RCC_TIMIC_Enable(void)
3670 {
3671 SET_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL);
3672 }
3673
3674 /**
3675 * @brief Disable TIM2,15 and LPTIM2 Input capture clock source
3676 * @rmtoll CCIPR1 TIMICSEL LL_RCC_TIMIC_Disable
3677 * @retval None
3678 */
LL_RCC_TIMIC_Disable(void)3679 __STATIC_INLINE void LL_RCC_TIMIC_Disable(void)
3680 {
3681 CLEAR_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL);
3682 }
3683
3684 /**
3685 * @brief Get FDCAN kernel clock source
3686 * @rmtoll CCIPR5 FDCANSEL LL_RCC_GetFDCANClockSource
3687 * @param FDCANx This parameter can be one of the following values:
3688 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
3689 * @retval Returned value can be one of the following values:
3690 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3691 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1
3692 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2
3693 */
LL_RCC_GetFDCANClockSource(uint32_t FDCANx)3694 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
3695 {
3696 return (uint32_t)(READ_BIT(RCC->CCIPR5, FDCANx));
3697 }
3698
3699 #if defined(SAI1)
3700 /**
3701 * @brief Get SAIx kernel clock source
3702 * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n
3703 * CCIPR2 SAI2SEL LL_RCC_GetSAIClockSource
3704 * @param SAIx This parameter can be one of the following values:
3705 * @arg @ref LL_RCC_SAI1_CLKSOURCE
3706 * @arg @ref LL_RCC_SAI2_CLKSOURCE
3707 * @retval Returned value can be one of the following values:
3708 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3709 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3710 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3711 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
3712 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3713 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q
3714 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P
3715 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P
3716 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
3717 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
3718 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)3719 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
3720 {
3721 return LL_RCC_GetClockSource(SAIx);
3722 }
3723 #endif /* SAI1 */
3724
3725 #if defined(SDMMC1)
3726 /**
3727 * @brief Get SDMMCx kernel clock source
3728 * @rmtoll CCIPR4 SDMMC1SEL LL_RCC_GetSDMMCClockSource
3729 * CCIPR4 SDMMC2SEL LL_RCC_GetSDMMCClockSource
3730 * @param SDMMCx This parameter can be one of the following values:
3731 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
3732 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
3733 * @retval Returned value can be one of the following values:
3734 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q
3735 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R
3736 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q (*)
3737 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R (*)
3738 *
3739 * (*) value not defined in all devices.
3740 */
LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)3741 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
3742 {
3743 return LL_RCC_GetClockSource(SDMMCx);
3744 }
3745 #endif /* SDMMC1 */
3746
3747 /**
3748 * @brief Get RNGx kernel clock source
3749 * @rmtoll CCIPR5 RNGSEL LL_RCC_GetRNGClockSource
3750 * @param RNGx This parameter can be one of the following values:
3751 * @arg @ref LL_RCC_RNG_CLKSOURCE
3752 * @retval Returned value can be one of the following values:
3753 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
3754 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
3755 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
3756 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
3757 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)3758 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
3759 {
3760 return (uint32_t)(READ_BIT(RCC->CCIPR5, RNGx));
3761 }
3762
3763 /**
3764 * @brief Get USB clock source
3765 * @rmtoll CCIPR4 USBSEL LL_RCC_GetUSBClockSource
3766 * @param USBx This parameter can be one of the following values:
3767 * @arg @ref LL_RCC_USB_CLKSOURCE
3768 * @retval Returned value can be one of the following values:
3769 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE
3770 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3771 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q (*)
3772 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3773 *
3774 * (*) : For stm32h56xxx and stm32h57xxx family lines.
3775 */
LL_RCC_GetUSBClockSource(uint32_t USBx)3776 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
3777 {
3778 return (uint32_t)(READ_BIT(RCC->CCIPR4, USBx));
3779 }
3780
3781 /**
3782 * @brief Get ADCDACx kernel clock source
3783 * @rmtoll CCIPR5 ADCDACSEL LL_RCC_GetADCDACClockSource
3784 * @param ADCDACx This parameter can be one of the following values:
3785 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE
3786 * @retval Returned value can be one of the following values:
3787 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK
3788 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK
3789 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2R
3790 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE
3791 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSI
3792 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_CSI
3793 */
LL_RCC_GetADCDACClockSource(uint32_t ADCDACx)3794 __STATIC_INLINE uint32_t LL_RCC_GetADCDACClockSource(uint32_t ADCDACx)
3795 {
3796 return (uint32_t)(READ_BIT(RCC->CCIPR5, ADCDACx));
3797 }
3798
3799 /**
3800 * @brief Get DAC low-power kernel Clock Source
3801 * @rmtoll CCIPR5 DACSEL LL_RCC_GetDACLPClockSource
3802 * @param DACLPx This parameter can be one of the following values:
3803 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE
3804 * @retval Returned value can be one of the following values:
3805 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSE
3806 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSI
3807 */
LL_RCC_GetDACLPClockSource(uint32_t DACLPx)3808 __STATIC_INLINE uint32_t LL_RCC_GetDACLPClockSource(uint32_t DACLPx)
3809 {
3810 return (uint32_t)(READ_BIT(RCC->CCIPR5, DACLPx));
3811 }
3812
3813 /**
3814 * @brief Get CECx kernel clock source
3815 * @rmtoll CCIPR5 CECSEL LL_RCC_GetCECClockSource
3816 * @param CECx This parameter can be one of the following values:
3817 * @arg @ref LL_RCC_CEC_CLKSOURCE
3818 * @retval Returned value can be one of the following values:
3819 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3820 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3821 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3822 */
LL_RCC_GetCECClockSource(uint32_t CECx)3823 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
3824 {
3825 return (uint32_t)(READ_BIT(RCC->CCIPR5, CECx));
3826 }
3827
3828 #if defined(OCTOSPI1)
3829 /**
3830 * @brief Get OCTOSPI kernel clock source
3831 * @rmtoll CCIPR4 OCTOSPISEL LL_RCC_GetOCTOSPIClockSource
3832 * @param OCTOSPIx This parameter can be one of the following values:
3833 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
3834 * @retval Returned value can be one of the following values:
3835 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3836 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3837 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3838 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3839 */
LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)3840 __STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
3841 {
3842 return (uint32_t)(READ_BIT(RCC->CCIPR4, OCTOSPIx));
3843 }
3844 #endif /* OCTOSPI1 */
3845
3846 /**
3847 * @brief Get CLKP kernel clock source
3848 * @rmtoll CCIPR5 CKPERSEL LL_RCC_GetCLKPClockSource
3849 * @param CLKPx This parameter can be one of the following values:
3850 * @arg @ref LL_RCC_CLKP_CLKSOURCE
3851 * @retval Returned value can be one of the following values:
3852 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3853 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3854 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3855 * @arg @ref LL_RCC_CLKP_CLKSOURCE_NONE
3856 */
LL_RCC_GetCLKPClockSource(uint32_t CLKPx)3857 __STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t CLKPx)
3858 {
3859 return (uint32_t)(READ_BIT(RCC->CCIPR5, CLKPx));
3860 }
3861
3862 /**
3863 * @brief Configure the Kernel wakeup clock source
3864 * @rmtoll CFGR1 STOPKERWUCK LL_RCC_SetKerWakeUpClkSource
3865 * @param Source This parameter can be one of the following values:
3866 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
3867 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
3868 * @retval None
3869 */
LL_RCC_SetKerWakeUpClkSource(uint32_t Source)3870 __STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
3871 {
3872 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, Source);
3873 }
3874
3875 /**
3876 * @brief Get the Kernel wakeup clock source
3877 * @rmtoll CFGR1 STOPKERWUCK LL_RCC_GetKerWakeUpClkSource
3878 * @retval Returned value can be one of the following values:
3879 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
3880 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
3881 */
LL_RCC_GetKerWakeUpClkSource(void)3882 __STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
3883 {
3884 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK));
3885 }
3886
3887 /**
3888 * @}
3889 */
3890
3891 /** @defgroup RCC_LL_EF_RTC RTC
3892 * @{
3893 */
3894
3895 /**
3896 * @brief Set RTC Clock Source
3897 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3898 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3899 * set). The BDRST bit can be used to reset them.
3900 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3901 * @param Source This parameter can be one of the following values:
3902 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3903 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3904 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3905 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV
3906 * @retval None
3907 */
LL_RCC_SetRTCClockSource(uint32_t Source)3908 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3909 {
3910 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3911 }
3912
3913 /**
3914 * @brief Get RTC Clock Source
3915 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
3916 * @retval Returned value can be one of the following values:
3917 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3918 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3919 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3920 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV
3921 */
LL_RCC_GetRTCClockSource(void)3922 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
3923 {
3924 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
3925 }
3926
3927 /**
3928 * @brief Enable RTC
3929 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
3930 * @retval None
3931 */
LL_RCC_EnableRTC(void)3932 __STATIC_INLINE void LL_RCC_EnableRTC(void)
3933 {
3934 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3935 }
3936
3937 /**
3938 * @brief Disable RTC
3939 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
3940 * @retval None
3941 */
LL_RCC_DisableRTC(void)3942 __STATIC_INLINE void LL_RCC_DisableRTC(void)
3943 {
3944 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3945 }
3946
3947 /**
3948 * @brief Check if RTC has been enabled or not
3949 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
3950 * @retval State of bit (1 or 0).
3951 */
LL_RCC_IsEnabledRTC(void)3952 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
3953 {
3954 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL);
3955 }
3956
3957 /**
3958 * @brief Force the Backup domain reset
3959 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
3960 * @retval None
3961 */
LL_RCC_ForceBackupDomainReset(void)3962 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
3963 {
3964 SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
3965 }
3966
3967 /**
3968 * @brief Release the Backup domain reset
3969 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
3970 * @retval None
3971 */
LL_RCC_ReleaseBackupDomainReset(void)3972 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
3973 {
3974 CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
3975 }
3976
3977 /**
3978 * @brief Set HSE Prescalers for RTC Clock
3979 * @rmtoll CFGR1 RTCPRE LL_RCC_SetRTC_HSEPrescaler
3980 * @param Prescaler This parameter can be one of the following values:
3981 * @arg @ref LL_RCC_RTC_HSE_NOCLOCK
3982 * @arg @ref LL_RCC_RTC_HSE_DIV_2
3983 * @arg @ref LL_RCC_RTC_HSE_DIV_3
3984 * @arg @ref LL_RCC_RTC_HSE_DIV_4
3985 * @arg @ref LL_RCC_RTC_HSE_DIV_5
3986 * @arg @ref LL_RCC_RTC_HSE_DIV_6
3987 * @arg @ref LL_RCC_RTC_HSE_DIV_7
3988 * @arg @ref LL_RCC_RTC_HSE_DIV_8
3989 * @arg @ref LL_RCC_RTC_HSE_DIV_9
3990 * @arg @ref LL_RCC_RTC_HSE_DIV_10
3991 * @arg @ref LL_RCC_RTC_HSE_DIV_11
3992 * @arg @ref LL_RCC_RTC_HSE_DIV_12
3993 * @arg @ref LL_RCC_RTC_HSE_DIV_13
3994 * @arg @ref LL_RCC_RTC_HSE_DIV_14
3995 * @arg @ref LL_RCC_RTC_HSE_DIV_15
3996 * @arg @ref LL_RCC_RTC_HSE_DIV_16
3997 * @arg @ref LL_RCC_RTC_HSE_DIV_17
3998 * @arg @ref LL_RCC_RTC_HSE_DIV_18
3999 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4000 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4001 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4002 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4003 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4004 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4005 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4006 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4007 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4008 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4009 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4010 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4011 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4012 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4013 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4014 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4015 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4016 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4017 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4018 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4019 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4020 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4021 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4022 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4023 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4024 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4025 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4026 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4027 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4028 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4029 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4030 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4031 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4032 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4033 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4034 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4035 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4036 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4037 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4038 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4039 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4040 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4041 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4042 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4043 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4044 * @retval None
4045 */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)4046 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4047 {
4048 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_RTCPRE, Prescaler);
4049 }
4050
4051 /**
4052 * @brief Get HSE Prescalers for RTC Clock
4053 * @rmtoll CFGR1 RTCPRE LL_RCC_GetRTC_HSEPrescaler
4054 * @retval Returned value can be one of the following values:
4055 * @arg @ref LL_RCC_RTC_HSE_NOCLOCK
4056 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4057 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4058 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4059 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4060 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4061 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4062 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4063 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4064 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4065 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4066 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4067 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4068 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4069 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4070 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4071 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4072 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4073 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4074 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4075 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4076 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4077 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4078 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4079 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4080 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4081 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4082 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4083 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4084 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4085 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4086 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4087 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4088 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4089 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4090 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4091 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4092 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4093 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4094 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4095 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4096 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4097 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4098 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4099 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4100 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4101 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4102 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4103 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4104 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4105 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4106 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4107 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4108 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4109 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4110 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4111 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4112 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4113 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4114 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4115 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4116 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4117 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4118 */
LL_RCC_GetRTC_HSEPrescaler(void)4119 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4120 {
4121 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE));
4122 }
4123
4124
4125 /**
4126 * @}
4127 */
4128
4129 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4130 * @{
4131 */
4132
4133 /**
4134 * @brief Set Timers Clock Prescalers
4135 * @rmtoll CFGR1 TIMPRE LL_RCC_SetTIMPrescaler
4136 * @param Prescaler This parameter can be one of the following values:
4137 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4138 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4139 * @retval None
4140 */
LL_RCC_SetTIMPrescaler(uint32_t Prescaler)4141 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4142 {
4143 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_TIMPRE, Prescaler);
4144 }
4145
4146 /**
4147 * @brief Get Timers Clock Prescalers
4148 * @rmtoll CFGR1 TIMPRE LL_RCC_GetTIMPrescaler
4149 * @retval Returned value can be one of the following values:
4150 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4151 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4152 */
LL_RCC_GetTIMPrescaler(void)4153 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4154 {
4155 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_TIMPRE));
4156 }
4157
4158 /**
4159 * @}
4160 */
4161
4162 /** @defgroup RCC_LL_EF_PLL1 PLL1
4163 * @{
4164 */
4165
4166 /**
4167 * @brief Enable PLL1
4168 * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
4169 * @retval None
4170 */
LL_RCC_PLL1_Enable(void)4171 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
4172 {
4173 SET_BIT(RCC->CR, RCC_CR_PLL1ON);
4174 }
4175
4176 /**
4177 * @brief Disable PLL1
4178 * @note Cannot be disabled if the PLL1 clock is used as the system clock
4179 * @rmtoll CR PLLON LL_RCC_PLL1_Disable
4180 * @retval None
4181 */
LL_RCC_PLL1_Disable(void)4182 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
4183 {
4184 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
4185 }
4186
4187 /**
4188 * @brief Check if PLL1 Ready
4189 * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
4190 * @retval State of bit (1 or 0).
4191 */
LL_RCC_PLL1_IsReady(void)4192 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
4193 {
4194 return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL);
4195 }
4196
4197 /**
4198 * @brief Enable PLL1 P output mapped to SYSCLK
4199 * @note This API shall be called only when PLL1 is disabled.
4200 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1P_Enable
4201 * @retval None
4202 */
LL_RCC_PLL1P_Enable(void)4203 __STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
4204 {
4205 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
4206 }
4207
4208 /**
4209 * @brief Disable PLL1 P output mapped to SYSCLK
4210 * @note Cannot be disabled if the PLL1 clock is used as the system
4211 * clock
4212 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1P_Disable
4213 * @retval None
4214 */
LL_RCC_PLL1P_Disable(void)4215 __STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
4216 {
4217 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
4218 }
4219
4220 /**
4221 * @brief Enable PLL1 Q output
4222 * @note This API shall be called only when PLL1 is disabled.
4223 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1Q_Enable
4224 * @retval None
4225 */
LL_RCC_PLL1Q_Enable(void)4226 __STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
4227 {
4228 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
4229 }
4230
4231 /**
4232 * @brief Disable PLL1 Q output
4233 * @note In order to save power, when the PLL1 Q output of the PLL1 is
4234 * not used, PLL1Q should be 0
4235 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1Q_Disable
4236 * @retval None
4237 */
LL_RCC_PLL1Q_Disable(void)4238 __STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
4239 {
4240 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
4241 }
4242
4243 /**
4244 * @brief Enable PLL1 R output
4245 * @note This API shall be called only when PLL1 is disabled.
4246 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1R_Enable
4247 * @retval None
4248 */
LL_RCC_PLL1R_Enable(void)4249 __STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
4250 {
4251 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
4252 }
4253
4254 /**
4255 * @brief Disable PLL1 R output
4256 * @note In order to save power, when the PLL1 R output of the PLL1 is
4257 * not used, PLL1R should be 0
4258 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1R_Disable
4259 * @retval None
4260 */
LL_RCC_PLL1R_Disable(void)4261 __STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
4262 {
4263 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
4264 }
4265
4266 /**
4267 * @brief Check if PLL1 P is enabled
4268 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled
4269 * @retval State of bit (1 or 0).
4270 */
LL_RCC_PLL1P_IsEnabled(void)4271 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
4272 {
4273 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == RCC_PLL1CFGR_PLL1PEN) ? 1UL : 0UL);
4274 }
4275
4276 /**
4277 * @brief Check if PLL1 Q is enabled
4278 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled
4279 * @retval State of bit (1 or 0).
4280 */
LL_RCC_PLL1Q_IsEnabled(void)4281 __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
4282 {
4283 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == RCC_PLL1CFGR_PLL1QEN) ? 1UL : 0UL);
4284 }
4285
4286 /**
4287 * @brief Check if PLL1 R is enabled
4288 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled
4289 * @retval State of bit (1 or 0).
4290 */
LL_RCC_PLL1R_IsEnabled(void)4291 __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
4292 {
4293 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == RCC_PLL1CFGR_PLL1REN) ? 1UL : 0UL);
4294 }
4295
4296 /**
4297 * @brief Configure PLL1 used for SYSCLK
4298 * @note PLL1 Source, PLL1M, PLL1N and PLL1P can be written only when PLL1 is disabled.
4299 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SYS\n
4300 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_SYS\n
4301 * PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_SYS\n
4302 * PLL1CFGR PLL1R LL_RCC_PLL1_ConfigDomain_SYS
4303 * @param Source This parameter can be one of the following values:
4304 * @arg @ref LL_RCC_PLL1SOURCE_NONE
4305 * @arg @ref LL_RCC_PLL1SOURCE_HSI
4306 * @arg @ref LL_RCC_PLL1SOURCE_CSI
4307 * @arg @ref LL_RCC_PLL1SOURCE_HSE
4308 * @param PLL1M parameter can be a value between 1 and 63
4309 * @param PLL1P parameter can be a value between 1 and 128 (odd values not allowed)
4310 * @param PLL1N parameter can be a value between 4 and 512
4311 * @retval None
4312 */
LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source,uint32_t PLL1M,uint32_t PLL1N,uint32_t PLL1P)4313 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t PLL1M, uint32_t PLL1N, uint32_t PLL1P)
4314 {
4315 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | (PLL1M << RCC_PLL1CFGR_PLL1M_Pos));
4316 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, \
4317 ((PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos));
4318 }
4319
4320 /**
4321 * @brief Configure PLL clock source
4322 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetSource
4323 * @param PLL1Source This parameter can be one of the following values:
4324 * @arg @ref LL_RCC_PLL1SOURCE_NONE
4325 * @arg @ref LL_RCC_PLL1SOURCE_HSI
4326 * @arg @ref LL_RCC_PLL1SOURCE_CSI
4327 * @arg @ref LL_RCC_PLL1SOURCE_HSE
4328 * @retval None
4329 */
LL_RCC_PLL1_SetSource(uint32_t PLLSource)4330 __STATIC_INLINE void LL_RCC_PLL1_SetSource(uint32_t PLLSource)
4331 {
4332 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLLSource);
4333 }
4334
4335 /**
4336 * @brief Get the oscillator used as PLL1 clock source.
4337 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetSource
4338 * @retval Returned value can be one of the following values:
4339 * @arg @ref LL_RCC_PLL1SOURCE_NONE
4340 * @arg @ref LL_RCC_PLL1SOURCE_CSI
4341 * @arg @ref LL_RCC_PLL1SOURCE_HSI
4342 * @arg @ref LL_RCC_PLL1SOURCE_HSE
4343 */
LL_RCC_PLL1_GetSource(void)4344 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetSource(void)
4345 {
4346 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC));
4347 }
4348
4349 /**
4350 * @brief Set Main PLL1 multiplication factor for VCO
4351 * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_SetN
4352 * @param PLLN parameter can be a value between 4 and 512
4353 */
LL_RCC_PLL1_SetN(uint32_t PLL1N)4354 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N)
4355 {
4356 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos);
4357 }
4358
4359 /**
4360 * @brief Get Main PLL1 multiplication factor for VCO
4361 * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_GetN
4362 * @retval Between 4 and 512
4363 */
LL_RCC_PLL1_GetN(void)4364 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
4365 {
4366 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL);
4367 }
4368
4369 /**
4370 * @brief Set Main PLL1 division factor for PLL1P
4371 * @note Used for System clock
4372 * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_SetP
4373 * @param PLLP parameter can be a value between 2 and 128 (odd value not allowed)
4374 */
LL_RCC_PLL1_SetP(uint32_t PLL1P)4375 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P)
4376 {
4377 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos);
4378 }
4379
4380 /**
4381 * @brief Get PLL1 division factor for PLL1P
4382 * @note Used for System clock
4383 * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_GetP
4384 * @retval Between 2 and 128
4385 */
LL_RCC_PLL1_GetP(void)4386 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
4387 {
4388 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL);
4389 }
4390
4391
4392 /**
4393 * @brief Set PLL1 division factor for PLL1Q
4394 * @note Used for peripherals clocks
4395 * @rmtoll PLLCFGR PLL1Q LL_RCC_PLL1_SetQ
4396 * @param PLLQ parameter can be a value between 1 and 128
4397 */
LL_RCC_PLL1_SetQ(uint32_t PLL1Q)4398 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q)
4399 {
4400 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos);
4401 }
4402
4403 /**
4404 * @brief Get PLL1 division factor for PLL1Q
4405 * @note Used for peripherals clocks
4406 * @rmtoll PLL1CFGR PLL1Q LL_RCC_PLL1_GetQ
4407 * @retval Between 1 and 128
4408 */
LL_RCC_PLL1_GetQ(void)4409 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
4410 {
4411 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL);
4412 }
4413
4414 /**
4415 * @brief Set PLL1 division factor for PLL1R
4416 * @note Used for trace
4417 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR
4418 * @param PLLQ parameter can be a value between 1 and 128
4419 */
LL_RCC_PLL1_SetR(uint32_t PLL1R)4420 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R)
4421 {
4422 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos);
4423 }
4424
4425 /**
4426 * @brief Get Main PLL1 division factor for PLL1R
4427 * @note Used for trace
4428 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR
4429 * @retval Between 1 and 128
4430 */
LL_RCC_PLL1_GetR(void)4431 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
4432 {
4433 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL);
4434 }
4435
4436 /**
4437 * @brief Set Division factor for the main PLL and other PLL
4438 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetM
4439 * @param PLL1M parameter can be a value between 1 and 63
4440 */
LL_RCC_PLL1_SetM(uint32_t PLL1M)4441 __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t PLL1M)
4442 {
4443 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, PLL1M << RCC_PLL1CFGR_PLL1M_Pos);
4444 }
4445
4446 /**
4447 * @brief Get Division factor for the main PLL and other PLL
4448 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetM
4449 * @retval Between 0 and 63
4450 */
LL_RCC_PLL1_GetM(void)4451 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
4452 {
4453 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos);
4454 }
4455
4456 /**
4457 * @brief Enable PLL1 FRACN
4458 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
4459 * @retval None
4460 */
LL_RCC_PLL1FRACN_Enable(void)4461 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
4462 {
4463 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
4464 }
4465
4466 /**
4467 * @brief Check if PLL1 FRACN is enabled
4468 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
4469 * @retval State of bit (1 or 0).
4470 */
LL_RCC_PLL1FRACN_IsEnabled(void)4471 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
4472 {
4473 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL);
4474 }
4475
4476 /**
4477 * @brief Disable PLL1 FRACN
4478 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable
4479 * @retval None
4480 */
LL_RCC_PLL1FRACN_Disable(void)4481 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
4482 {
4483 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
4484 }
4485
4486 /**
4487 * @brief Set PLL1 FRACN Coefficient
4488 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN
4489 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4490 */
LL_RCC_PLL1_SetFRACN(uint32_t FRACN)4491 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
4492 {
4493 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos);
4494 }
4495
4496 /**
4497 * @brief Get PLL1 FRACN Coefficient
4498 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN
4499 * @retval A value between 0 and 8191 (0x1FFF)
4500 */
LL_RCC_PLL1_GetFRACN(void)4501 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
4502 {
4503 return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos);
4504 }
4505
4506 /**
4507 * @brief Set PLL1 VCO Input Range
4508 * @note This API shall be called only when PLL1 is disabled.
4509 * @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
4510 * @param InputRange This parameter can be one of the following values:
4511 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4512 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4513 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4514 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4515 * @retval None
4516 */
LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)4517 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
4518 {
4519 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange << RCC_PLL1CFGR_PLL1RGE_Pos);
4520 }
4521
4522 /**
4523 * @brief Set PLL1 VCO OutputRange
4524 * @note This API shall be called only when PLL1 is disabled.
4525 * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOuputRange
4526 * @param VCORange This parameter can be one of the following values:
4527 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4528 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4529 * @retval None
4530 */
LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)4531 __STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
4532 {
4533 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1VCOSEL, VCORange << RCC_PLL1CFGR_PLL1VCOSEL_Pos);
4534 }
4535
4536 /**
4537 * @}
4538 */
4539
4540 /** @defgroup RCC_LL_EF_PLL2 PLL2
4541 * @{
4542 */
4543
4544 /**
4545 * @brief Enable PLL2
4546 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
4547 * @retval None
4548 */
LL_RCC_PLL2_Enable(void)4549 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
4550 {
4551 SET_BIT(RCC->CR, RCC_CR_PLL2ON);
4552 }
4553
4554 /**
4555 * @brief Disable PLL2
4556 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
4557 * @retval None
4558 */
LL_RCC_PLL2_Disable(void)4559 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
4560 {
4561 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
4562 }
4563
4564 /**
4565 * @brief Check if PLL2 Ready
4566 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
4567 * @retval State of bit (1 or 0).
4568 */
LL_RCC_PLL2_IsReady(void)4569 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
4570 {
4571 return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY) ? 1UL : 0UL);
4572 }
4573
4574 /**
4575 * @brief Configure PLL2 clock source
4576 * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_SetSource
4577 * @param PLL2Source This parameter can be one of the following values:
4578 * @arg @ref LL_RCC_PLL2SOURCE_NONE
4579 * @arg @ref LL_RCC_PLL2SOURCE_CSI
4580 * @arg @ref LL_RCC_PLL2SOURCE_HSI
4581 * @arg @ref LL_RCC_PLL2SOURCE_HSE
4582 * @retval None
4583 */
LL_RCC_PLL2_SetSource(uint32_t PLL2Source)4584 __STATIC_INLINE void LL_RCC_PLL2_SetSource(uint32_t PLL2Source)
4585 {
4586 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, PLL2Source);
4587 }
4588
4589 /**
4590 * @brief Get the oscillator used as PLL2 clock source.
4591 * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_GetSource
4592 * @retval Returned value can be one of the following values:
4593 * @arg @ref LL_RCC_PLL2SOURCE_NONE
4594 * @arg @ref LL_RCC_PLL2SOURCE_CSI
4595 * @arg @ref LL_RCC_PLL2SOURCE_HSI
4596 * @arg @ref LL_RCC_PLL2SOURCE_HSE
4597 */
LL_RCC_PLL2_GetSource(void)4598 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetSource(void)
4599 {
4600 return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC));
4601 }
4602
4603 /**
4604 * @brief Set PLL2 Division factor M
4605 * @note This API shall be called only when PLL2 is disabled.
4606 * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_SetM
4607 * @param PLL2M parameter can be a value between 1 and 63
4608 */
LL_RCC_PLL2_SetM(uint32_t PLL2M)4609 __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t PLL2M)
4610 {
4611 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M, PLL2M << RCC_PLL2CFGR_PLL2M_Pos);
4612 }
4613
4614 /**
4615 * @brief Get PLL2 division factor M
4616 * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_GetM
4617 * @retval Between 1 and 63
4618 */
LL_RCC_PLL2_GetM(void)4619 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
4620 {
4621 return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos);
4622 }
4623
4624 /**
4625 * @brief Set PLL2 multiplication factor N
4626 * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_SetN
4627 * @param PLL2N parameter can be a value between 4 and 512
4628 */
LL_RCC_PLL2_SetN(uint32_t PLL2N)4629 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t PLL2N)
4630 {
4631 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N, (PLL2N - 1UL) << RCC_PLL2DIVR_PLL2N_Pos);
4632 }
4633
4634 /**
4635 * @brief Get PLL2 multiplication factor N
4636 * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_GetN
4637 * @retval Between 4 and 512
4638 */
LL_RCC_PLL2_GetN(void)4639 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
4640 {
4641 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1UL);
4642 }
4643
4644 /**
4645 * @brief Set PLL2 division factor P
4646 * @note Used for peripherals clocks
4647 * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_SetP
4648 * @param PLL2P parameter can be a value between 1 and 128
4649 */
LL_RCC_PLL2_SetP(uint32_t PLL2P)4650 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t PLL2P)
4651 {
4652 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P, (PLL2P - 1UL) << RCC_PLL2DIVR_PLL2P_Pos);
4653 }
4654
4655 /**
4656 * @brief Get PLL2 division factor P
4657 * @note Used for peripherals clocks
4658 * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_GetP
4659 * @retval Between 1 and 128
4660 */
LL_RCC_PLL2_GetP(void)4661 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
4662 {
4663 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1UL);
4664 }
4665
4666
4667 /**
4668 * @brief Set PLL2 division factor Q
4669 * @note Used for peripherals clocks
4670 * @rmtoll PLLCFGR PLL2Q LL_RCC_PLL2_SetQ
4671 * @param PLL2Q parameter can be a value between 1 and 128
4672 */
LL_RCC_PLL2_SetQ(uint32_t PLL2Q)4673 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t PLL2Q)
4674 {
4675 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q, (PLL2Q - 1UL) << RCC_PLL2DIVR_PLL2Q_Pos);
4676 }
4677
4678 /**
4679 * @brief Get PLL2 division factor Q
4680 * @note Used for peripherals clocks
4681 * @rmtoll PLL2CFGR PLL2Q LL_RCC_PLL2_GetQ
4682 * @retval Between 1 and 128
4683 */
LL_RCC_PLL2_GetQ(void)4684 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
4685 {
4686 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL);
4687 }
4688
4689 /**
4690 * @brief Set PLL2 division factor R
4691 * @note Used for PLL2CLK selected for peripherals clocks
4692 * @rmtoll PLL2CFGR PLL2Q LL_RCC_PLL2_SetR
4693 * @param PLL2R parameter can be a value between 1 and 128
4694 */
LL_RCC_PLL2_SetR(uint32_t PLL2R)4695 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t PLL2R)
4696 {
4697 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2R, (PLL2R - 1UL) << RCC_PLL2DIVR_PLL2R_Pos);
4698 }
4699
4700 /**
4701 * @brief Get PLL2 division factor R
4702 * @note Used for PLL2CLK (system clock)
4703 * @rmtoll PLL2DIVR PLL2R LL_RCC_PLL2_GetR
4704 * @retval Between 1 and 128
4705 */
LL_RCC_PLL2_GetR(void)4706 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
4707 {
4708 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1UL);
4709 }
4710
4711 /**
4712 * @brief Enable PLL2 P output
4713 * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2P_Enable
4714 * @retval None
4715 */
LL_RCC_PLL2P_Enable(void)4716 __STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
4717 {
4718 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);
4719 }
4720
4721 /**
4722 * @brief Disable PLL2 P output
4723 * @note In order to save power, when PLL2P output is
4724 * not used, it should be disabled (at any time)
4725 * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2P_Disable
4726 * @retval None
4727 */
LL_RCC_PLL2P_Disable(void)4728 __STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
4729 {
4730 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);
4731 }
4732
4733 /**
4734 * @brief Enable PLL2 Q output
4735 * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2Q_Enable
4736 * @retval None
4737 */
LL_RCC_PLL2Q_Enable(void)4738 __STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
4739 {
4740 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);
4741 }
4742
4743 /**
4744 * @brief Disable PLL2 Q output
4745 * @note In order to save power, when PLL2Q output is
4746 * not used, it should be disabled (at any time)
4747 * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_Disable
4748 * @retval None
4749 */
LL_RCC_PLL2Q_Disable(void)4750 __STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
4751 {
4752 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);
4753 }
4754
4755 /**
4756 * @brief Enable PLL2 R output
4757 * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2R_Enable
4758 * @retval None
4759 */
LL_RCC_PLL2R_Enable(void)4760 __STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
4761 {
4762 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);
4763 }
4764
4765 /**
4766 * @brief Disable PLL2 R output
4767 * @note In order to save power, when PLL2R output is
4768 * not used, it should be disabled (at any time)
4769 * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2R_Disable
4770 * @retval None
4771 */
LL_RCC_PLL2R_Disable(void)4772 __STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
4773 {
4774 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);
4775 }
4776
4777 /**
4778 * @brief Check if PLL2 P is enabled
4779 * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2P_IsEnabled
4780 * @retval State of bit (1 or 0).
4781 */
LL_RCC_PLL2P_IsEnabled(void)4782 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
4783 {
4784 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN) == RCC_PLL2CFGR_PLL2PEN) ? 1UL : 0UL);
4785 }
4786
4787 /**
4788 * @brief Check if PLL2 Q is enabled
4789 * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2Q_IsEnabled
4790 * @retval State of bit (1 or 0).
4791 */
LL_RCC_PLL2Q_IsEnabled(void)4792 __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
4793 {
4794 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN) == RCC_PLL2CFGR_PLL2QEN) ? 1UL : 0UL);
4795 }
4796
4797 /**
4798 * @brief Check if PLL2 R is enabled
4799 * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2R_IsEnabled
4800 * @retval State of bit (1 or 0).
4801 */
LL_RCC_PLL2R_IsEnabled(void)4802 __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
4803 {
4804 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN) == RCC_PLL2CFGR_PLL2REN) ? 1UL : 0UL);
4805 }
4806
4807 /**
4808 * @brief Enable PLL2 FRACN
4809 * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
4810 * @retval None
4811 */
LL_RCC_PLL2FRACN_Enable(void)4812 __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
4813 {
4814 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN);
4815 }
4816
4817 /**
4818 * @brief Check if PLL2 FRACN is enabled
4819 * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled
4820 * @retval State of bit (1 or 0).
4821 */
LL_RCC_PLL2FRACN_IsEnabled(void)4822 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
4823 {
4824 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) == RCC_PLL2CFGR_PLL2FRACEN) ? 1UL : 0UL);
4825 }
4826
4827 /**
4828 * @brief Disable PLL2 FRACN
4829 * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Disable
4830 * @retval None
4831 */
LL_RCC_PLL2FRACN_Disable(void)4832 __STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
4833 {
4834 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN);
4835 }
4836
4837 /**
4838 * @brief Set PLL2 FRACN Coefficient
4839 * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_SetFRACN
4840 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4841 */
LL_RCC_PLL2_SetFRACN(uint32_t FRACN)4842 __STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
4843 {
4844 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, FRACN << RCC_PLL2FRACR_PLL2FRACN_Pos);
4845 }
4846
4847 /**
4848 * @brief Get PLL2 FRACN Coefficient
4849 * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_GetFRACN
4850 * @retval A value between 0 and 8191 (0x1FFF)
4851 */
LL_RCC_PLL2_GetFRACN(void)4852 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
4853 {
4854 return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN) >> RCC_PLL2FRACR_PLL2FRACN_Pos);
4855 }
4856
4857 /**
4858 * @brief Set PLL2 VCO Input Range
4859 * @note This API shall be called only when PLL2 is disabled.
4860 * @rmtoll PLL2CFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange
4861 * @param InputRange This parameter can be one of the following values:
4862 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4863 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4864 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4865 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4866 * @retval None
4867 */
LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)4868 __STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
4869 {
4870 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, InputRange << RCC_PLL2CFGR_PLL2RGE_Pos);
4871 }
4872
4873 /**
4874 * @brief Set PLL2 VCO OutputRange
4875 * @note This API shall be called only when PLL2 is disabled.
4876 * @rmtoll PLL2CFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOuputRange
4877 * @param VCORange This parameter can be one of the following values:
4878 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4879 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4880 * @retval None
4881 */
LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)4882 __STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
4883 {
4884 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2VCOSEL, VCORange << RCC_PLL2CFGR_PLL2VCOSEL_Pos);
4885 }
4886
4887 /**
4888 * @}
4889 */
4890
4891 #if defined(RCC_CR_PLL3ON)
4892 /** @defgroup RCC_LL_EF_PLL3 PLL3
4893 * @{
4894 */
4895
4896 /**
4897 * @brief Enable PLL3
4898 * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable
4899 * @retval None
4900 */
LL_RCC_PLL3_Enable(void)4901 __STATIC_INLINE void LL_RCC_PLL3_Enable(void)
4902 {
4903 SET_BIT(RCC->CR, RCC_CR_PLL3ON);
4904 }
4905
4906 /**
4907 * @brief Disable PLL3
4908 * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable
4909 * @retval None
4910 */
LL_RCC_PLL3_Disable(void)4911 __STATIC_INLINE void LL_RCC_PLL3_Disable(void)
4912 {
4913 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
4914 }
4915
4916 /**
4917 * @brief Check if PLL3 is Ready
4918 * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady
4919 * @retval State of bit (1 or 0).
4920 */
LL_RCC_PLL3_IsReady(void)4921 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
4922 {
4923 return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == RCC_CR_PLL3RDY) ? 1UL : 0UL);
4924 }
4925
4926
4927 /**
4928 * @brief Configure PLL3 clock source
4929 * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_SetSource
4930 * @param PLLSource This parameter can be one of the following values:
4931 * @arg @ref LL_RCC_PLL3SOURCE_NONE
4932 * @arg @ref LL_RCC_PLL3SOURCE_CSI
4933 * @arg @ref LL_RCC_PLL3SOURCE_HSI
4934 * @arg @ref LL_RCC_PLL3SOURCE_HSE
4935 * @retval None
4936 */
LL_RCC_PLL3_SetSource(uint32_t PLLSource)4937 __STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource)
4938 {
4939 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, PLLSource);
4940 }
4941
4942 /**
4943 * @brief Get the oscillator used as PLL3 clock source.
4944 * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_GetSource
4945 * @retval Returned value can be one of the following values:
4946 * @arg @ref LL_RCC_PLL3SOURCE_NONE
4947 * @arg @ref LL_RCC_PLL3SOURCE_CSI
4948 * @arg @ref LL_RCC_PLL3SOURCE_HSI
4949 * @arg @ref LL_RCC_PLL3SOURCE_HSE
4950 */
LL_RCC_PLL3_GetSource(void)4951 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void)
4952 {
4953 return (uint32_t)(READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC));
4954 }
4955
4956 /**
4957 * @brief Set PLL3 multiplication factor N
4958 * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_SetN
4959 * @param PLL3N parameter can be a value between 4 and 512
4960 */
LL_RCC_PLL3_SetN(uint32_t PLL3N)4961 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t PLL3N)
4962 {
4963 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N, (PLL3N - 1UL) << RCC_PLL3DIVR_PLL3N_Pos);
4964 }
4965
4966 /**
4967 * @brief Get PLL3 multiplication factor N
4968 * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_GetN
4969 * @retval Between 4 and 512
4970 */
LL_RCC_PLL3_GetN(void)4971 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
4972 {
4973 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1UL);
4974 }
4975
4976 /**
4977 * @brief Set PLL3 division factor P
4978 * @note Used for peripherals clocks
4979 * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_SetP
4980 * @param PLL3P parameter can be a value between 1 and 128
4981 */
LL_RCC_PLL3_SetP(uint32_t PLL3P)4982 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t PLL3P)
4983 {
4984 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P, (PLL3P - 1UL) << RCC_PLL3DIVR_PLL3P_Pos);
4985 }
4986
4987 /**
4988 * @brief Get PLL3 division factor P
4989 * @note Used for peripherals clocks
4990 * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_GetP
4991 * @retval Between 1 and 128
4992 */
LL_RCC_PLL3_GetP(void)4993 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
4994 {
4995 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1UL);
4996 }
4997
4998 /**
4999 * @brief Set PLL3 division factor Q
5000 * @note Used for peripherals clocks
5001 * @rmtoll PLLCFGR PLL3Q LL_RCC_PLL3_SetQ
5002 * @param PLL3Q parameter can be a value between 1 and 128
5003 */
LL_RCC_PLL3_SetQ(uint32_t PLL3Q)5004 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t PLL3Q)
5005 {
5006 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q, (PLL3Q - 1UL) << RCC_PLL3DIVR_PLL3Q_Pos);
5007 }
5008
5009 /**
5010 * @brief Get PLL3 division factor Q
5011 * @note Used for peripherals clocks
5012 * @rmtoll PLL3CFGR PLL3Q LL_RCC_PLL3_GetQ
5013 * @retval Between 1 and 128
5014 */
LL_RCC_PLL3_GetQ(void)5015 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
5016 {
5017 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1UL);
5018 }
5019
5020 /**
5021 * @brief Set PLL3 division factor R
5022 * @note Used for peripherals clocks
5023 * @rmtoll PLL3CFGR PLL3Q LL_RCC_PLL3_SetR
5024 * @param PLL3R parameter can be a value between 1 and 128
5025 */
LL_RCC_PLL3_SetR(uint32_t PLL3R)5026 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t PLL3R)
5027 {
5028 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R, (PLL3R - 1UL) << RCC_PLL3DIVR_PLL3R_Pos);
5029 }
5030
5031 /**
5032 * @brief Get PLL3 division factor R
5033 * @note Used for PLL3CLK (system clock)
5034 * @rmtoll PLL3DIVR PLL3R LL_RCC_PLL3_GetR
5035 * @retval Between 1 and 128
5036 */
LL_RCC_PLL3_GetR(void)5037 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
5038 {
5039 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1UL);
5040 }
5041
5042 /**
5043 * @brief Set PLL3 Division factor M
5044 * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_SetM
5045 * @param PLL3M parameter can be a value between 1 and 63
5046 */
LL_RCC_PLL3_SetM(uint32_t PLL3M)5047 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t PLL3M)
5048 {
5049 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M, PLL3M << RCC_PLL3CFGR_PLL3M_Pos);
5050 }
5051
5052 /**
5053 * @brief Get PLL3 Division factor M
5054 * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_GetM
5055 * @retval Between 1 and 63
5056 */
LL_RCC_PLL3_GetM(void)5057 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
5058 {
5059 return (uint32_t)(READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos);
5060 }
5061
5062 /**
5063 * @brief Enable PLL3 P output
5064 * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3P_Enable
5065 * @retval None
5066 */
LL_RCC_PLL3P_Enable(void)5067 __STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
5068 {
5069 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);
5070 }
5071
5072 /**
5073 * @brief Disable PLL3 P output
5074 * @note In order to save power, when PLL3P output is
5075 * not used, it should be disabled (at any time)
5076 * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3P_Disable
5077 * @retval None
5078 */
LL_RCC_PLL3P_Disable(void)5079 __STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
5080 {
5081 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);
5082 }
5083
5084 /**
5085 * @brief Enable PLL3 Q output
5086 * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3Q_Enable
5087 * @retval None
5088 */
LL_RCC_PLL3Q_Enable(void)5089 __STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
5090 {
5091 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);
5092 }
5093
5094 /**
5095 * @brief Disable PLL3 Q output
5096 * @note In order to save power, when PLL3Q output is
5097 * not used, it should be disabled (at any time)
5098 * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3Q_Disable
5099 * @retval None
5100 */
LL_RCC_PLL3Q_Disable(void)5101 __STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
5102 {
5103 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);
5104 }
5105
5106 /**
5107 * @brief Enable PLL3 R output
5108 * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3R_Enable
5109 * @retval None
5110 */
LL_RCC_PLL3R_Enable(void)5111 __STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
5112 {
5113 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN);
5114 }
5115
5116 /**
5117 * @brief Disable PLL3 R output
5118 * @note In order to save power, when PLL3R output is
5119 * not used, it should be disabled (at any time)
5120 * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3R_Disable
5121 * @retval None
5122 */
LL_RCC_PLL3R_Disable(void)5123 __STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
5124 {
5125 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN);
5126 }
5127
5128 /**
5129 * @brief Check if PLL3 P is enabled
5130 * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3P_IsEnabled
5131 * @retval State of bit (1 or 0).
5132 */
LL_RCC_PLL3P_IsEnabled(void)5133 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
5134 {
5135 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN) == RCC_PLL3CFGR_PLL3PEN) ? 1UL : 0UL);
5136 }
5137
5138 /**
5139 * @brief Check if PLL3 Q is enabled
5140 * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3Q_IsEnabled
5141 * @retval State of bit (1 or 0).
5142 */
LL_RCC_PLL3Q_IsEnabled(void)5143 __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
5144 {
5145 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN) == RCC_PLL3CFGR_PLL3QEN) ? 1UL : 0UL);
5146 }
5147
5148 /**
5149 * @brief Check if PLL3 R is enabled
5150 * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3R_IsEnabled
5151 * @retval State of bit (1 or 0).
5152 */
LL_RCC_PLL3R_IsEnabled(void)5153 __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
5154 {
5155 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN) == RCC_PLL3CFGR_PLL3REN) ? 1UL : 0UL);
5156 }
5157
5158 /**
5159 * @brief Enable PLL3 FRACN
5160 * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
5161 * @retval None
5162 */
LL_RCC_PLL3FRACN_Enable(void)5163 __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
5164 {
5165 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN);
5166 }
5167
5168 /**
5169 * @brief Check if PLL3 FRACN is enabled
5170 * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled
5171 * @retval State of bit (1 or 0).
5172 */
LL_RCC_PLL3FRACN_IsEnabled(void)5173 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
5174 {
5175 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) == RCC_PLL3CFGR_PLL3FRACEN) ? 1UL : 0UL);
5176 }
5177
5178 /**
5179 * @brief Disable PLL3 FRACN
5180 * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Disable
5181 * @retval None
5182 */
LL_RCC_PLL3FRACN_Disable(void)5183 __STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
5184 {
5185 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN);
5186 }
5187
5188 /**
5189 * @brief Set PLL3 FRACN Coefficient
5190 * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_SetFRACN
5191 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
5192 */
LL_RCC_PLL3_SetFRACN(uint32_t FRACN)5193 __STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
5194 {
5195 MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, FRACN << RCC_PLL3FRACR_PLL3FRACN_Pos);
5196 }
5197
5198 /**
5199 * @brief Get PLL3 FRACN Coefficient
5200 * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_GetFRACN
5201 * @retval A value between 0 and 8191 (0x1FFF)
5202 */
LL_RCC_PLL3_GetFRACN(void)5203 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
5204 {
5205 return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN) >> RCC_PLL3FRACR_PLL3FRACN_Pos);
5206 }
5207
5208 /**
5209 * @brief Set PLL3 VCO Input Range
5210 * @note This API shall be called only when PLL3 is disabled.
5211 * @rmtoll PLL3CFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange
5212 * @param InputRange This parameter can be one of the following values:
5213 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
5214 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
5215 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
5216 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
5217 * @retval None
5218 */
LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)5219 __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
5220 {
5221 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, InputRange << RCC_PLL3CFGR_PLL3RGE_Pos);
5222 }
5223
5224 /**
5225 * @brief Set PLL3 VCO OutputRange
5226 * @note This API shall be called only when PLL3 is disabled.
5227 * @rmtoll PLL3CFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOuputRange
5228 * @param VCORange This parameter can be one of the following values:
5229 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
5230 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
5231 * @retval None
5232 */
LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)5233 __STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
5234 {
5235 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3VCOSEL, VCORange << RCC_PLL3CFGR_PLL3VCOSEL_Pos);
5236 }
5237
5238 /**
5239 * @}
5240 */
5241 #endif /* PLL3 */
5242
5243 /** @defgroup RCC_LL_EF_PRIV Privileged mode
5244 * @{
5245 */
5246
5247 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
5248 /**
5249 * @brief Enable Secure Privileged mode
5250 * @rmtoll PRIVCFGR SPRIV LL_RCC_EnableSecPrivilegedMode
5251 * @retval None
5252 */
LL_RCC_EnableSecPrivilegedMode(void)5253 __STATIC_INLINE void LL_RCC_EnableSecPrivilegedMode(void)
5254 {
5255 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
5256 }
5257
5258 /**
5259 * @brief Disable Secure Privileged mode
5260 * @rmtoll PRIVCFGR SPRIV LL_RCC_DisableSecPrivilegedMode
5261 * @retval None
5262 */
LL_RCC_DisableSecPrivilegedMode(void)5263 __STATIC_INLINE void LL_RCC_DisableSecPrivilegedMode(void)
5264 {
5265 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
5266 }
5267
5268 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
5269
5270 #if defined(RCC_PRIVCFGR_NSPRIV)
5271 /**
5272 * @brief Enable Non Secure Privileged mode
5273 * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnableNSecPrivilegedMode
5274 * @retval None
5275 */
LL_RCC_EnableNSecPrivilegedMode(void)5276 __STATIC_INLINE void LL_RCC_EnableNSecPrivilegedMode(void)
5277 {
5278 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
5279 }
5280
5281 /**
5282 * @brief Disable Non Secure Privileged mode
5283 * @rmtoll PRIVCFGR NSPRIV LL_RCC_DisableNSecPrivilegedMode
5284 * @retval None
5285 */
LL_RCC_DisableNSecPrivilegedMode(void)5286 __STATIC_INLINE void LL_RCC_DisableNSecPrivilegedMode(void)
5287 {
5288 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
5289 }
5290
5291 /**
5292 * @brief Check if Secure Privileged mode has been enabled or not
5293 * @rmtoll PRIVCFGR SPRIV LL_RCC_IsEnabledSecPrivilegedMode
5294 * @retval State of bit (1 or 0).
5295 */
LL_RCC_IsEnabledSecPrivilegedMode(void)5296 __STATIC_INLINE uint32_t LL_RCC_IsEnabledSecPrivilegedMode(void)
5297 {
5298 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL);
5299 }
5300
5301 /**
5302 * @brief Check if Non Secure Privileged mode has been enabled or not
5303 * @rmtoll PRIVCFGR NSPRIV LL_RCC_IsEnabledNSecPrivilegedMode
5304 * @retval State of bit (1 or 0).
5305 */
LL_RCC_IsEnabledNSecPrivilegedMode(void)5306 __STATIC_INLINE uint32_t LL_RCC_IsEnabledNSecPrivilegedMode(void)
5307 {
5308 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
5309 }
5310
5311 #else
5312 /**
5313 * @brief Enable Privileged mode
5314 * @rmtoll PRIVCFGR PRIV LL_RCC_EnablePrivilegedMode
5315 * @retval None
5316 */
LL_RCC_EnablePrivilegedMode(void)5317 __STATIC_INLINE void LL_RCC_EnablePrivilegedMode(void)
5318 {
5319 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_PRIV);
5320 }
5321
5322 /**
5323 * @brief Disable Privileged mode
5324 * @rmtoll PRIVCFGR PRIV LL_RCC_DisablePrivilegedMode
5325 * @retval None
5326 */
LL_RCC_DisablePrivilegedMode(void)5327 __STATIC_INLINE void LL_RCC_DisablePrivilegedMode(void)
5328 {
5329 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_PRIV);
5330 }
5331
5332 /**
5333 * @brief Check if Privileged mode has been enabled or not
5334 * @rmtoll PRIVCFGR PRIV LL_RCC_IsEnabledPrivilegedMode
5335 * @retval State of bit (1 or 0).
5336 */
LL_RCC_IsEnabledPrivilegedMode(void)5337 __STATIC_INLINE uint32_t LL_RCC_IsEnabledPrivilegedMode(void)
5338 {
5339 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_PRIV) == RCC_PRIVCFGR_PRIV) ? 1UL : 0UL);
5340 }
5341
5342 #endif /* RCC_PRIVCFGR_NSPRIV */
5343
5344 /**
5345 * @}
5346 */
5347
5348 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
5349 * @{
5350 */
5351
5352 /**
5353 * @brief Clear LSI ready interrupt flag
5354 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
5355 * @retval None
5356 */
LL_RCC_ClearFlag_LSIRDY(void)5357 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
5358 {
5359 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
5360 }
5361
5362 /**
5363 * @brief Clear LSE ready interrupt flag
5364 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
5365 * @retval None
5366 */
LL_RCC_ClearFlag_LSERDY(void)5367 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
5368 {
5369 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
5370 }
5371
5372 /**
5373 * @brief Clear CSI ready interrupt flag
5374 * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY
5375 * @retval None
5376 */
LL_RCC_ClearFlag_CSIRDY(void)5377 __STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
5378 {
5379 SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
5380 }
5381
5382 /**
5383 * @brief Clear HSI ready interrupt flag
5384 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
5385 * @retval None
5386 */
LL_RCC_ClearFlag_HSIRDY(void)5387 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
5388 {
5389 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
5390 }
5391
5392 /**
5393 * @brief Clear HSE ready interrupt flag
5394 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
5395 * @retval None
5396 */
LL_RCC_ClearFlag_HSERDY(void)5397 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
5398 {
5399 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
5400 }
5401
5402
5403 /**
5404 * @brief Clear HSI48 ready interrupt flag
5405 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
5406 * @retval None
5407 */
LL_RCC_ClearFlag_HSI48RDY(void)5408 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
5409 {
5410 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
5411 }
5412
5413 /**
5414 * @brief Clear PLL1 ready interrupt flag
5415 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
5416 * @retval None
5417 */
LL_RCC_ClearFlag_PLL1RDY(void)5418 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
5419 {
5420 SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC);
5421 }
5422
5423 /**
5424 * @brief Clear PLL2 ready interrupt flag
5425 * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
5426 * @retval None
5427 */
LL_RCC_ClearFlag_PLL2RDY(void)5428 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
5429 {
5430 SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
5431 }
5432
5433 #if defined(RCC_CR_PLL3ON)
5434 /**
5435 * @brief Clear PLL3 ready interrupt flag
5436 * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY
5437 * @retval None
5438 */
LL_RCC_ClearFlag_PLL3RDY(void)5439 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
5440 {
5441 SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
5442 }
5443 #endif /* PLL3 */
5444
5445 /**
5446 * @brief Clear Clock security system interrupt flag
5447 * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS
5448 * @retval None
5449 */
LL_RCC_ClearFlag_HSECSS(void)5450 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
5451 {
5452 SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
5453 }
5454
5455 /**
5456 * @brief Check if LSI ready interrupt occurred or not
5457 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
5458 * @retval State of bit (1 or 0).
5459 */
LL_RCC_IsActiveFlag_LSIRDY(void)5460 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
5461 {
5462 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
5463 }
5464
5465 /**
5466 * @brief Check if LSE ready interrupt occurred or not
5467 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
5468 * @retval State of bit (1 or 0).
5469 */
LL_RCC_IsActiveFlag_LSERDY(void)5470 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
5471 {
5472 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
5473 }
5474
5475 /**
5476 * @brief Check if CSI ready interrupt occurred or not
5477 * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY
5478 * @retval State of bit (1 or 0).
5479 */
LL_RCC_IsActiveFlag_CSIRDY(void)5480 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
5481 {
5482 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == RCC_CIFR_CSIRDYF) ? 1UL : 0UL);
5483 }
5484
5485 /**
5486 * @brief Check if HSI ready interrupt occurred or not
5487 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
5488 * @retval State of bit (1 or 0).
5489 */
LL_RCC_IsActiveFlag_HSIRDY(void)5490 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
5491 {
5492 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
5493 }
5494
5495 /**
5496 * @brief Check if HSE ready interrupt occurred or not
5497 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
5498 * @retval State of bit (1 or 0).
5499 */
LL_RCC_IsActiveFlag_HSERDY(void)5500 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
5501 {
5502 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
5503 }
5504
5505 /**
5506 * @brief Check if HSI48 ready interrupt occurred or not
5507 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
5508 * @retval State of bit (1 or 0).
5509 */
LL_RCC_IsActiveFlag_HSI48RDY(void)5510 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
5511 {
5512 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
5513 }
5514 /**
5515 * @brief Check if PLL1 ready interrupt occurred or not
5516 * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY
5517 * @retval State of bit (1 or 0).
5518 */
LL_RCC_IsActiveFlag_PLL1RDY(void)5519 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
5520 {
5521 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL);
5522 }
5523
5524 /**
5525 * @brief Check if PLL2 ready interrupt occurred or not
5526 * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
5527 * @retval State of bit (1 or 0).
5528 */
LL_RCC_IsActiveFlag_PLL2RDY(void)5529 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
5530 {
5531 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL);
5532 }
5533
5534 #if defined(RCC_CR_PLL3ON)
5535 /**
5536 * @brief Check if PLL3 ready interrupt occurred or not
5537 * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY
5538 * @retval State of bit (1 or 0).
5539 */
LL_RCC_IsActiveFlag_PLL3RDY(void)5540 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
5541 {
5542 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL);
5543 }
5544 #endif /* PLL3 */
5545
5546 /**
5547 * @brief Check if Clock security system interrupt occurred or not
5548 * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS
5549 * @retval State of bit (1 or 0).
5550 */
LL_RCC_IsActiveFlag_HSECSS(void)5551 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
5552 {
5553 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL);
5554 }
5555
5556 /**
5557 * @brief Check if RCC flag Independent Watchdog reset is set or not.
5558 * @rmtoll RSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
5559 * @retval State of bit (1 or 0).
5560 */
LL_RCC_IsActiveFlag_IWDGRST(void)5561 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
5562 {
5563 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDGRSTF) == RCC_RSR_IWDGRSTF) ? 1UL : 0UL);
5564 }
5565
5566 /**
5567 * @brief Check if RCC flag Low Power reset is set or not.
5568 * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
5569 * @retval State of bit (1 or 0).
5570 */
LL_RCC_IsActiveFlag_LPWRRST(void)5571 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
5572 {
5573 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == RCC_RSR_LPWRRSTF) ? 1UL : 0UL);
5574 }
5575
5576 /**
5577 * @brief Check if RCC flag Pin reset is set or not.
5578 * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST
5579 * @retval State of bit (1 or 0).
5580 */
LL_RCC_IsActiveFlag_PINRST(void)5581 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
5582 {
5583 return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == RCC_RSR_PINRSTF) ? 1UL : 0UL);
5584 }
5585
5586 /**
5587 * @brief Check if RCC flag Software reset is set or not.
5588 * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
5589 * @retval State of bit (1 or 0).
5590 */
LL_RCC_IsActiveFlag_SFTRST(void)5591 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
5592 {
5593 return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == RCC_RSR_SFTRSTF) ? 1UL : 0UL);
5594 }
5595
5596 /**
5597 * @brief Check if RCC flag Window Watchdog reset is set or not.
5598 * @rmtoll RSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
5599 * @retval State of bit (1 or 0).
5600 */
LL_RCC_IsActiveFlag_WWDGRST(void)5601 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
5602 {
5603 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDGRSTF) == RCC_RSR_WWDGRSTF) ? 1UL : 0UL);
5604 }
5605
5606 /**
5607 * @brief Check if RCC flag BOR reset is set or not.
5608 * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST
5609 * @retval State of bit (1 or 0).
5610 */
LL_RCC_IsActiveFlag_BORRST(void)5611 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
5612 {
5613 return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == RCC_RSR_BORRSTF) ? 1UL : 0UL);
5614 }
5615
5616 /**
5617 * @brief Set RMVF bit to clear the reset flags.
5618 * @rmtoll RSR RMVF LL_RCC_ClearResetFlags
5619 * @retval None
5620 */
LL_RCC_ClearResetFlags(void)5621 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
5622 {
5623 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
5624 }
5625
5626 /**
5627 * @}
5628 */
5629
5630 /** @defgroup RCC_LL_EF_IT_Management IT Management
5631 * @{
5632 */
5633
5634 /**
5635 * @brief Enable LSI ready interrupt
5636 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
5637 * @retval None
5638 */
LL_RCC_EnableIT_LSIRDY(void)5639 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
5640 {
5641 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5642 }
5643
5644 /**
5645 * @brief Enable LSE ready interrupt
5646 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
5647 * @retval None
5648 */
LL_RCC_EnableIT_LSERDY(void)5649 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
5650 {
5651 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5652 }
5653
5654 /**
5655 * @brief Enable CSI ready interrupt
5656 * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY
5657 * @retval None
5658 */
LL_RCC_EnableIT_CSIRDY(void)5659 __STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
5660 {
5661 SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
5662 }
5663
5664 /**
5665 * @brief Enable HSI ready interrupt
5666 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
5667 * @retval None
5668 */
LL_RCC_EnableIT_HSIRDY(void)5669 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
5670 {
5671 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5672 }
5673
5674 /**
5675 * @brief Enable HSE ready interrupt
5676 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
5677 * @retval None
5678 */
LL_RCC_EnableIT_HSERDY(void)5679 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
5680 {
5681 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5682 }
5683
5684 /**
5685 * @brief Enable HSI48 ready interrupt
5686 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
5687 * @retval None
5688 */
LL_RCC_EnableIT_HSI48RDY(void)5689 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
5690 {
5691 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
5692 }
5693
5694 /**
5695 * @brief Enable PLL1 ready interrupt
5696 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
5697 * @retval None
5698 */
LL_RCC_EnableIT_PLL1RDY(void)5699 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
5700 {
5701 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
5702 }
5703
5704 /**
5705 * @brief Enable PLL2 ready interrupt
5706 * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
5707 * @retval None
5708 */
LL_RCC_EnableIT_PLL2RDY(void)5709 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
5710 {
5711 SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
5712 }
5713
5714 #if defined(RCC_CR_PLL3ON)
5715 /**
5716 * @brief Enable PLL3 ready interrupt
5717 * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY
5718 * @retval None
5719 */
LL_RCC_EnableIT_PLL3RDY(void)5720 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
5721 {
5722 SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
5723 }
5724 #endif /* PLL3 */
5725
5726 /**
5727 * @brief Disable LSI ready interrupt
5728 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
5729 * @retval None
5730 */
LL_RCC_DisableIT_LSIRDY(void)5731 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
5732 {
5733 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5734 }
5735
5736 /**
5737 * @brief Disable LSE ready interrupt
5738 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
5739 * @retval None
5740 */
LL_RCC_DisableIT_LSERDY(void)5741 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
5742 {
5743 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5744 }
5745
5746 /**
5747 * @brief Disable CSI ready interrupt
5748 * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY
5749 * @retval None
5750 */
LL_RCC_DisableIT_CSIRDY(void)5751 __STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
5752 {
5753 CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
5754 }
5755
5756 /**
5757 * @brief Disable HSI ready interrupt
5758 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
5759 * @retval None
5760 */
LL_RCC_DisableIT_HSIRDY(void)5761 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
5762 {
5763 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5764 }
5765
5766 /**
5767 * @brief Disable HSE ready interrupt
5768 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
5769 * @retval None
5770 */
LL_RCC_DisableIT_HSERDY(void)5771 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
5772 {
5773 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5774 }
5775
5776 /**
5777 * @brief Disable HSI48 ready interrupt
5778 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
5779 * @retval None
5780 */
LL_RCC_DisableIT_HSI48RDY(void)5781 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
5782 {
5783 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
5784 }
5785
5786 /**
5787 * @brief Disable PLL1 ready interrupt
5788 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
5789 * @retval None
5790 */
LL_RCC_DisableIT_PLL1RDY(void)5791 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
5792 {
5793 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
5794 }
5795
5796 /**
5797 * @brief Disable PLL2 ready interrupt
5798 * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
5799 * @retval None
5800 */
LL_RCC_DisableIT_PLL2RDY(void)5801 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
5802 {
5803 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
5804 }
5805
5806 #if defined(RCC_CR_PLL3ON)
5807 /**
5808 * @brief Disable PLL3 ready interrupt
5809 * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY
5810 * @retval None
5811 */
LL_RCC_DisableIT_PLL3RDY(void)5812 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
5813 {
5814 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
5815 }
5816 #endif /* PLL3 */
5817
5818 /**
5819 * @brief Checks if LSI ready interrupt source is enabled or disabled.
5820 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
5821 * @retval State of bit (1 or 0).
5822 */
LL_RCC_IsEnabledIT_LSIRDY(void)5823 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
5824 {
5825 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
5826 }
5827
5828 /**
5829 * @brief Checks if LSE ready interrupt source is enabled or disabled.
5830 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
5831 * @retval State of bit (1 or 0).
5832 */
LL_RCC_IsEnabledIT_LSERDY(void)5833 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
5834 {
5835 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
5836 }
5837
5838 /**
5839 * @brief Checks if CSI ready interrupt source is enabled or disabled.
5840 * @rmtoll CIER CSIRDYIE LL_RCC_IsEnabledIT_CSIRDY
5841 * @retval State of bit (1 or 0).
5842 */
LL_RCC_IsEnabledIT_CSIRDY(void)5843 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_CSIRDY(void)
5844 {
5845 return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL);
5846 }
5847
5848 /**
5849 * @brief Checks if HSI ready interrupt source is enabled or disabled.
5850 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
5851 * @retval State of bit (1 or 0).
5852 */
LL_RCC_IsEnabledIT_HSIRDY(void)5853 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
5854 {
5855 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
5856 }
5857
5858 /**
5859 * @brief Checks if HSE ready interrupt source is enabled or disabled.
5860 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
5861 * @retval State of bit (1 or 0).
5862 */
LL_RCC_IsEnabledIT_HSERDY(void)5863 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
5864 {
5865 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
5866 }
5867
5868 /**
5869 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
5870 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
5871 * @retval State of bit (1 or 0).
5872 */
LL_RCC_IsEnabledIT_HSI48RDY(void)5873 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
5874 {
5875 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
5876 }
5877 /**
5878 * @brief Checks if PLL1 ready interrupt source is enabled or disabled.
5879 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY
5880 * @retval State of bit (1 or 0).
5881 */
LL_RCC_IsEnabledIT_PLL1RDY(void)5882 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void)
5883 {
5884 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
5885 }
5886
5887 /**
5888 * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
5889 * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
5890 * @retval State of bit (1 or 0).
5891 */
LL_RCC_IsEnabledIT_PLL2RDY(void)5892 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
5893 {
5894 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL);
5895 }
5896
5897 #if defined(RCC_CR_PLL3ON)
5898 /**
5899 * @brief Checks if PLL3 ready interrupt source is enabled or disabled.
5900 * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnabledIT_PLL3RDY
5901 * @retval State of bit (1 or 0).
5902 */
LL_RCC_IsEnabledIT_PLL3RDY(void)5903 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void)
5904 {
5905 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL);
5906 }
5907 #endif /* PLL3 */
5908
5909 /**
5910 * @}
5911 */
5912
5913 /** @defgroup RCC_LL_EF_Security_Services Security Services
5914 * @{
5915 */
5916
5917 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
5918 /**
5919 * @brief Configure RCC resources security
5920 * @note Only available from secure state when system implements security (TZEN=1)
5921 * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n
5922 * SECCFGR HSESEC LL_RCC_ConfigSecure\n
5923 * SECCFGR CSISEC LL_RCC_ConfigSecure\n
5924 * SECCFGR LSISEC LL_RCC_ConfigSecure\n
5925 * SECCFGR LSESEC LL_RCC_ConfigSecure\n
5926 * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n
5927 * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n
5928 * SECCFGR PLL1SEC LL_RCC_ConfigSecure\n
5929 * SECCFGR PLL2SEC LL_RCC_ConfigSecure\n
5930 * SECCFGR PLL3SEC LL_RCC_ConfigSecure\n
5931 * SECCFGR HSI48SEC LL_RCC_ConfigSecure\n
5932 * SECCFGR RMVFSEC LL_RCC_ConfigSecure\n
5933 * SECCFGR CKPERSELSEC LL_RCC_ConfigSecure
5934 * @param Configuration This parameter shall be the full combination of the following values:
5935 * @arg @ref LL_RCC_ALL_SEC or LL_RCC_ALL_NSEC
5936 * @arg @ref LL_RCC_HSI_SEC or LL_RCC_HSI_NSEC
5937 * @arg @ref LL_RCC_HSE_SEC or LL_RCC_HSE_NSEC
5938 * @arg @ref LL_RCC_CSI_SEC or LL_RCC_CSI_NSEC
5939 * @arg @ref LL_RCC_LSE_SEC or LL_RCC_LSE_NSEC
5940 * @arg @ref LL_RCC_LSI_SEC or LL_RCC_LSI_NSEC
5941 * @arg @ref LL_RCC_SYSCLK_SEC or LL_RCC_SYSCLK_NSEC
5942 * @arg @ref LL_RCC_PRESCALERS_SEC or LL_RCC_PRESCALERS_NSEC
5943 * @arg @ref LL_RCC_PLL1_SEC or LL_RCC_PLL1_NSEC
5944 * @arg @ref LL_RCC_PLL2_SEC or LL_RCC_PLL2_NSEC
5945 * @arg @ref LL_RCC_PLL3_SEC or LL_RCC_PLL3_NSEC
5946 * @arg @ref LL_RCC_HSI48_SEC or LL_RCC_HSI48_NSEC
5947 * @arg @ref LL_RCC_RESET_FLAGS_SEC or LL_RCC_RESET_FLAGS_NSEC
5948 * @arg @ref LL_RCC_CKPER_SEC or LL_RCC_CKPER_NSEC
5949 * @retval None
5950 */
LL_RCC_ConfigSecure(uint32_t Configuration)5951 __STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t Configuration)
5952 {
5953 WRITE_REG(RCC->SECCFGR, Configuration);
5954 }
5955 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
5956
5957 #if defined(RCC_SECCFGR_HSISEC)
5958 /**
5959 * @brief Get RCC resources security status
5960 * @note Only available from secure state when system implements security (TZEN=1)
5961 * @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n
5962 * SECCFGR HSESEC LL_RCC_GetConfigSecure\n
5963 * SECCFGR CSISEC LL_RCC_GetConfigSecure\n
5964 * SECCFGR LSISEC LL_RCC_GetConfigSecure\n
5965 * SECCFGR LSESEC LL_RCC_GetConfigSecure\n
5966 * SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n
5967 * SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n
5968 * SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n
5969 * SECCFGR PLL2SEC LL_RCC_GetConfigSecure\n
5970 * SECCFGR PLL3SEC LL_RCC_GetConfigSecure\n
5971 * SECCFGR HSI48SEC LL_RCC_GetConfigSecure\n
5972 * SECCFGR RMVFSEC LL_RCC_GetConfigSecure\n
5973 * SECCFGR CKPERSELSEC LL_RCC_GetConfigSecure
5974 * @retval Returned value is the combination of the following values:
5975 * @arg @ref LL_RCC_ALL_SEC or LL_RCC_ALL_NSEC
5976 * @arg @ref LL_RCC_HSI_SEC or LL_RCC_HSI_NSEC
5977 * @arg @ref LL_RCC_HSE_SEC or LL_RCC_HSE_NSEC
5978 * @arg @ref LL_RCC_CSI_SEC or LL_RCC_CSI_NSEC
5979 * @arg @ref LL_RCC_LSE_SEC or LL_RCC_LSE_NSEC
5980 * @arg @ref LL_RCC_LSI_SEC or LL_RCC_LSI_NSEC
5981 * @arg @ref LL_RCC_SYSCLK_SEC or LL_RCC_SYSCLK_NSEC
5982 * @arg @ref LL_RCC_PRESCALERS_SEC or LL_RCC_PRESCALERS_NSEC
5983 * @arg @ref LL_RCC_PLL1_SEC or LL_RCC_PLL1_NSEC
5984 * @arg @ref LL_RCC_PLL2_SEC or LL_RCC_PLL2_NSEC
5985 * @arg @ref LL_RCC_PLL3_SEC or LL_RCC_PLL3_NSEC
5986 * @arg @ref LL_RCC_HSI48_SEC or LL_RCC_HSI48_NSEC
5987 * @arg @ref LL_RCC_RESET_FLAGS_SEC or LL_RCC_RESET_FLAGS_NSEC
5988 * @arg @ref LL_RCC_CKPER_SEC or LL_RCC_CKPER_NSEC
5989 * @retval None
5990 */
LL_RCC_GetConfigSecure(void)5991 __STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void)
5992 {
5993 return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK));
5994 }
5995 #endif /* RCC_SECCFGR_HSISEC */
5996
5997 /**
5998 * @}
5999 */
6000
6001 #if defined(USE_FULL_LL_DRIVER)
6002 /** @defgroup RCC_LL_EF_Init De-initialization function
6003 * @{
6004 */
6005 ErrorStatus LL_RCC_DeInit(void);
6006 /**
6007 * @}
6008 */
6009
6010 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
6011 * @{
6012 */
6013
6014 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
6015
6016 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks);
6017 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks);
6018 #if defined(RCC_CR_PLL3ON)
6019 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks);
6020 #endif /* PLL3 */
6021 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *pRCC_Clocks);
6022 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
6023 #if defined(UART4)
6024 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
6025 #endif /* UART4 */
6026 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
6027 uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource);
6028 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
6029 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
6030 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
6031 #if defined (SAI1)
6032 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
6033 #endif /* SAI1 */
6034 #if defined(SDMMC1)
6035 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
6036 #endif /* SDMMC1 */
6037 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
6038 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
6039 uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCDACxSource);
6040 uint32_t LL_RCC_GetDACLPClockFreq(uint32_t DACLPxSource);
6041 #if defined(OCTOSPI1)
6042 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
6043 #endif /* OCTOSPI1 */
6044 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
6045 #if defined(CEC)
6046 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
6047 #endif /* CEC */
6048 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
6049 /**
6050 * @}
6051 */
6052
6053 #endif /* USE_FULL_LL_DRIVER */
6054
6055 /**
6056 * @}
6057 */
6058
6059 /**
6060 * @}
6061 */
6062
6063 #endif /* defined(RCC) */
6064
6065 /**
6066 * @}
6067 */
6068
6069 #ifdef __cplusplus
6070 }
6071 #endif
6072
6073 #endif /* __STM32H5xx_LL_RCC_H */
6074