1 /**
2   ******************************************************************************
3   * @file    stm32mp1xx_ll_rcc.h
4   * @author  MCD Application Team
5   * @version $VERSION$
6   * @date    $DATE$
7   * @brief   Header file of RCC LL module.
8   ******************************************************************************
9   * @attention
10   *
11   * Copyright (c) 2019 STMicroelectronics.
12   * All rights reserved.
13   *
14   * This software is licensed under terms that can be found in the LICENSE file
15   * in the root directory of this software component.
16   * If no LICENSE file comes with this software, it is provided AS-IS.
17   *
18   ******************************************************************************
19   */
20 
21 /* Define to prevent recursive inclusion -------------------------------------*/
22 #ifndef STM32MP1xx_LL_RCC_H
23 #define STM32MP1xx_LL_RCC_H
24 
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32mp1xx.h"
32 
33 /** @addtogroup STM32MP1xx_LL_Driver
34   * @{
35   */
36 
37 #if defined(RCC)
38 
39 /** @defgroup RCC_LL RCC
40   * @{
41   */
42 
43 /* Private types -------------------------------------------------------------*/
44 /* Private variables ---------------------------------------------------------*/
45 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
46   * @{
47   */
48 
49 /**
50   * @}
51   */
52 
53 /* Private constants ---------------------------------------------------------*/
54 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
55   * @{
56   */
57 /* Defines used to perform offsets*/
58 
59 /* Clock source register offset Vs I2C46CKSELR register */
60 #define RCC_OFFSET_I2C46CKSELR     0x000UL
61 #define RCC_OFFSET_SPI6CKSELR      0x004UL
62 #define RCC_OFFSET_UART1CKSELR     0x008UL
63 #define RCC_OFFSET_RNG1CKSELR      0x00CUL
64 #define RCC_OFFSET_MCO1CFGR        0x740UL
65 #define RCC_OFFSET_MCO2CFGR        0x744UL
66 #define RCC_OFFSET_TIMG1PRER       0x768UL
67 #define RCC_OFFSET_TIMG2PRER       0x76CUL
68 #define RCC_OFFSET_I2C12CKSELR     0x800UL
69 #define RCC_OFFSET_I2C35CKSELR     0x804UL
70 #define RCC_OFFSET_SAI1CKSELR      0x808UL
71 #define RCC_OFFSET_SAI2CKSELR      0x80CUL
72 #define RCC_OFFSET_SAI3CKSELR      0x810UL
73 #define RCC_OFFSET_SAI4CKSELR      0x814UL
74 #define RCC_OFFSET_SPI2S1CKSELR    0x818UL
75 #define RCC_OFFSET_SPI2S23CKSELR   0x81CUL
76 #define RCC_OFFSET_SPI45CKSELR     0x820UL
77 #define RCC_OFFSET_UART6CKSELR     0x824UL
78 #define RCC_OFFSET_UART24CKSELR    0x828UL
79 #define RCC_OFFSET_UART35CKSELR    0x82CUL
80 #define RCC_OFFSET_UART78CKSELR    0x830UL
81 #define RCC_OFFSET_SDMMC12CKSELR   0x834UL
82 #define RCC_OFFSET_SDMMC3CKSELR    0x838UL
83 #define RCC_OFFSET_RNG2CKSELR      0x860UL
84 #define RCC_OFFSET_LPTIM45CKSELR   0x86CUL
85 #define RCC_OFFSET_LPTIM23CKSELR   0x870UL
86 #define RCC_OFFSET_LPTIM1CKSELR    0x874UL
87 
88 #define RCC_CONFIG_SHIFT  0U
89 #define RCC_MASK_SHIFT    8U
90 #define RCC_REG_SHIFT     16U
91 
92 
93 /* Define all reset flags mask */
94 #define LL_RCC_MC_RSTSCLRR_ALL  0x000007FFU
95 /**
96   * @}
97   */
98 
99 /* Private macros ------------------------------------------------------------*/
100 #if !defined (UNUSED)
101 #define UNUSED(x) ((void)(x))
102 #endif
103 
104 #if defined(USE_FULL_LL_DRIVER)
105 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
106   * @{
107   */
108 
109 /* 32     28     24           16            8             0
110    --------------------------------------------------------
111    | Free  |     Register      |    Mask    | ClkSource   |
112    |       |      Offset       |            | Config      |
113    --------------------------------------------------------*/
114 
115 #define LL_CLKSOURCE_MASK(__CLKSOURCE__) \
116           (((__CLKSOURCE__) >> RCC_MASK_SHIFT  ) & 0xFFUL)
117 
118 #define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) \
119           (((__CLKSOURCE__) >> RCC_CONFIG_SHIFT) & 0xFFUL)
120 
121 #define LL_CLKSOURCE_REG(__CLKSOURCE__) \
122           (((__CLKSOURCE__) >> RCC_REG_SHIFT   ) & 0xFFFUL)
123 
124 #define LL_CLKSOURCE(__REG__, __MSK__, __CLK__)      \
125           ((uint32_t)((((__REG__) ) << RCC_REG_SHIFT)  | \
126           (( __MSK__              ) << RCC_MASK_SHIFT) | \
127           (( __CLK__              ) << RCC_CONFIG_SHIFT)))
128 
129 /**
130   * @}
131   */
132 #endif /*USE_FULL_LL_DRIVER*/
133 
134 /* Exported types ------------------------------------------------------------*/
135 #if defined(USE_FULL_LL_DRIVER)
136 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
137   * @{
138   */
139 
140 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
141   * @{
142   */
143 
144 /**
145   * @brief  RCC Clocks Frequency Structure
146   */
147 typedef struct
148 {
149   uint32_t MPUSS_Frequency;   /*!< MPUSS clock frequency */
150   uint32_t AXISS_Frequency;   /*!< AXISS clock frequency */
151   uint32_t MCUSS_Frequency;   /*!< MCUSS clock frequency */
152   uint32_t ACLK_Frequency;    /*!< ACLK clock frequency */
153   uint32_t HCLK1_Frequency;   /*!< HCLK1 clock frequency */
154   uint32_t HCLK2_Frequency;   /*!< HCLK2 clock frequency */
155   uint32_t HCLK3_Frequency;   /*!< HCLK3 clock frequency */
156   uint32_t HCLK4_Frequency;   /*!< HCLK4 clock frequency */
157   uint32_t HCLK5_Frequency;   /*!< HCLK5 clock frequency */
158   uint32_t HCLK6_Frequency;   /*!< HCLK6 clock frequency */
159   uint32_t MCU_Frequency;     /*!< MCU clock frequency */
160   uint32_t MLHCLK_Frequency;  /*!< MLHCLK clock frequency */
161   uint32_t PCLK1_Frequency;   /*!< PCLK1 clock frequency */
162   uint32_t PCLK2_Frequency;   /*!< PCLK2 clock frequency */
163   uint32_t PCLK3_Frequency;   /*!< PCLK3 clock frequency */
164   uint32_t PCLK4_Frequency;   /*!< PCLK4 clock frequency */
165   uint32_t PCLK5_Frequency;   /*!< PCLK5 clock frequency */
166 } LL_RCC_ClocksTypeDef;
167 
168 /**
169   * @}
170   */
171 
172 /**
173   * @brief  PLL Clocks Frequency Structure
174   */
175 typedef struct
176 {
177   uint32_t PLL_P_Frequency;
178   uint32_t PLL_Q_Frequency;
179   uint32_t PLL_R_Frequency;
180 } LL_PLL_ClocksTypeDef;
181 
182 /**
183   * @}
184   */
185 #endif /* USE_FULL_LL_DRIVER */
186 
187 /* Exported constants --------------------------------------------------------*/
188 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
189   * @{
190   */
191 
192 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
193   * @brief    Defines used to adapt values of different oscillators
194   * @note     These values could be modified in the user environment according to
195   *           HW set-up.
196   * @{
197   */
198 #if !defined  (HSE_VALUE)
199 #define HSE_VALUE    24000000U   /*!< Value of the HSE oscillator in Hz */
200 #endif /* HSE_VALUE */
201 
202 #if !defined  (HSI_VALUE)
203 #define HSI_VALUE    64000000U  /*!< Value of the HSI oscillator in Hz */
204 #endif /* HSI_VALUE */
205 
206 #if !defined  (LSE_VALUE)
207 #define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
208 #endif /* LSE_VALUE */
209 
210 #if !defined  (LSI_VALUE)
211 #define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
212 #endif /* LSI_VALUE */
213 
214 #if !defined  (CSI_VALUE)
215 #define CSI_VALUE    4000000U     /*!< Value of the CSI oscillator in Hz */
216 #endif /* LSI_VALUE */
217 
218 #if !defined  (EXTERNAL_CLOCK_VALUE)
219 #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
220 #endif /* EXTERNAL_CLOCK_VALUE */
221 
222 #if !defined  (USBO_48M_VALUE)
223 #define USBO_48M_VALUE    48000000U /*!< Value of the rcc_ck_usbo_48m oscillator in Hz */
224 #endif /* USBO_48M_VALUE */
225 
226 /**
227   * @}
228   */
229 
230 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
231   * @brief    Flags defines which can be used with LL_RCC_WriteReg function
232   * @{
233   */
234 #define LL_RCC_CIFR_LSIRDYC      RCC_MC_CIFR_LSIRDYF /*!< LSI Ready Interrupt Clear */
235 #define LL_RCC_CIFR_LSERDYC      RCC_MC_CIFR_LSERDYF /*!< LSE Ready Interrupt Clear */
236 #define LL_RCC_CIFR_HSIRDYC      RCC_MC_CIFR_HSIRDYF /*!< HSI Ready Interrupt Clear */
237 #define LL_RCC_CIFR_HSERDYC      RCC_MC_CIFR_HSERDYF /*!< HSE Ready Interrupt Clear */
238 #define LL_RCC_CIFR_CSIRDYC      RCC_MC_CIFR_CSIRDYF /*!< CSI Ready Interrupt Clear */
239 #define LL_RCC_CIFR_PLL1RDYC     RCC_MC_CIFR_PLL1DYF /*!< PLL1 Ready Interrupt Clear */
240 #define LL_RCC_CIFR_PLL2RDYC     RCC_MC_CIFR_PLL2DYF /*!< PLL2 Ready Interrupt Clear */
241 #define LL_RCC_CIFR_PLL3RDYC     RCC_MC_CIFR_PLL3DYF /*!< PLL3 Ready Interrupt Clear */
242 #define LL_RCC_CIFR_PLL4RDYC     RCC_MC_CIFR_PLL4DYF /*!< PLL4 Ready Interrupt Clear */
243 #define LL_RCC_CIFR_LSECSSC      RCC_MC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt Clear */
244 #define LL_RCC_CIFR_WKUPC        RCC_MC_CIFR_WKUPF   /*!< Wake up from CStop Interrupt Clear */
245 /**
246   * @}
247   */
248 
249 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
250   * @brief    Flags defines which can be used with LL_RCC_ReadReg function
251   * @{
252   */
253 #define LL_RCC_CIFR_LSIRDYF      RCC_MC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
254 #define LL_RCC_CIFR_LSERDYF      RCC_MC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
255 #define LL_RCC_CIFR_HSIRDYF      RCC_MC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
256 #define LL_RCC_CIFR_HSERDYF      RCC_MC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
257 #define LL_RCC_CIFR_CSIRDYF      RCC_MC_CIFR_CSIRDYF /*!< CSI Ready Interrupt flag */
258 #define LL_RCC_CIFR_PLL1RDYF     RCC_MC_CIFR_PLL1DYF /*!< PLL1 Ready Interrupt flag */
259 #define LL_RCC_CIFR_PLL2RDYF     RCC_MC_CIFR_PLL2DYF /*!< PLL2 Ready Interrupt flag */
260 #define LL_RCC_CIFR_PLL3RDYF     RCC_MC_CIFR_PLL3DYF /*!< PLL3 Ready Interrupt flag */
261 #define LL_RCC_CIFR_PLL4RDYF     RCC_MC_CIFR_PLL4DYF /*!< PLL4 Ready Interrupt flag */
262 #define LL_RCC_CIFR_LSECSSF      RCC_MC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
263 #define LL_RCC_CIFR_WKUPF        RCC_MC_CIFR_WKUPF   /*!< Wake up from CStop Interrupt flag */
264 /**
265   * @}
266   */
267 
268 /** @defgroup RCC_LL_EC_IT IT Defines
269   * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
270   * @{
271   */
272 #define LL_RCC_CIER_LSIRDYIE      RCC_MC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
273 #define LL_RCC_CIER_LSERDYIE      RCC_MC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
274 #define LL_RCC_CIER_HSIRDYIE      RCC_MC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
275 #define LL_RCC_CIER_HSERDYIE      RCC_MC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
276 #define LL_RCC_CIER_CSIRDYIE      RCC_MC_CIER_CSIRDYIE /*!< CSI Ready Interrupt Enable */
277 #define LL_RCC_CIER_PLL1RDYIE     RCC_MC_CIER_PLL1DYIE /*!< PLL1 Ready Interrupt Enable */
278 #define LL_RCC_CIER_PLL2RDYIE     RCC_MC_CIER_PLL2DYIE /*!< PLL2 Ready Interrupt Enable */
279 #define LL_RCC_CIER_PLL3RDYIE     RCC_MC_CIER_PLL3DYIE /*!< PLL3 Ready Interrupt Enable */
280 #define LL_RCC_CIER_PLL4RDYIE     RCC_MC_CIER_PLL4DYIE /*!< PLL4 Ready Interrupt Enable */
281 #define LL_RCC_CIER_LSECSSIE      RCC_MC_CIER_LSECSSIE /*!< LSE Clock Security System Interrupt Enable */
282 #define LL_RCC_CIER_WKUPIE        RCC_MC_CIER_WKUPIE   /*!< Wake up from CStop Interrupt Enable */
283 /**
284   * @}
285   */
286 
287 /** @defgroup RCC_LL_EC_HSIDIV  HSI oscillator divider
288   * @{
289   */
290 #define LL_RCC_HSI_DIV_1                   0U
291 #define LL_RCC_HSI_DIV_2                   RCC_HSICFGR_HSIDIV_0
292 #define LL_RCC_HSI_DIV_4                   RCC_HSICFGR_HSIDIV_1
293 #define LL_RCC_HSI_DIV_8                   (RCC_HSICFGR_HSIDIV_0 | RCC_HSICFGR_HSIDIV_1)
294 /**
295   * @}
296   */
297 
298 /** @defgroup RCC_LL_EC_MCOxSOURCE  MCO SOURCE selection
299   * @{
300   */
301 #define LL_RCC_MCO1SOURCE_HSI      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, 0)
302 #define LL_RCC_MCO1SOURCE_HSE      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_0)
303 #define LL_RCC_MCO1SOURCE_CSI      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_1)
304 #define LL_RCC_MCO1SOURCE_LSI      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, (RCC_MCO1CFGR_MCO1SEL_0 | RCC_MCO1CFGR_MCO1SEL_1))
305 #define LL_RCC_MCO1SOURCE_LSE      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_2)
306 
307 #define LL_RCC_MCO2SOURCE_MPU      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, 0)
308 #define LL_RCC_MCO2SOURCE_AXI      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_0)
309 #define LL_RCC_MCO2SOURCE_MCU      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_1)
310 #define LL_RCC_MCO2SOURCE_PLL4     LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, (RCC_MCO2CFGR_MCO2SEL_1 | RCC_MCO2CFGR_MCO2SEL_0))
311 #define LL_RCC_MCO2SOURCE_HSE      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_2)
312 #define LL_RCC_MCO2SOURCE_HSI      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, (RCC_MCO2CFGR_MCO2SEL_2 | RCC_MCO2CFGR_MCO2SEL_0))
313 /**
314   * @}
315   */
316 
317 /** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
318   * @{
319   */
320 #define LL_RCC_MCO1_DIV_1                  0U                       /*!< MCO not divided */
321 #define LL_RCC_MCO1_DIV_2                  RCC_MCO1CFGR_MCO1DIV_0   /*!< MCO divided by 2 */
322 #define LL_RCC_MCO1_DIV_3                  RCC_MCO1CFGR_MCO1DIV_1   /*!< MCO divided by 3 */
323 #define LL_RCC_MCO1_DIV_4                  (RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0)   /*!< MCO divided by 4 */
324 #define LL_RCC_MCO1_DIV_5                  RCC_MCO1CFGR_MCO1DIV_2   /*!< MCO divided by 5 */
325 #define LL_RCC_MCO1_DIV_6                  (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0)   /*!< MCO divided by 6 */
326 #define LL_RCC_MCO1_DIV_7                  (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1)   /*!< MCO divided by 7 */
327 #define LL_RCC_MCO1_DIV_8                  (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1| RCC_MCO1CFGR_MCO1DIV_0)   /*!< MCO divided by 8 */
328 #define LL_RCC_MCO1_DIV_9                  RCC_MCO1CFGR_MCO1DIV_3   /*!< MCO divided by 9 */
329 #define LL_RCC_MCO1_DIV_10                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_0)   /*!< MCO divided by 10 */
330 #define LL_RCC_MCO1_DIV_11                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1)  /*!< MCO divided by 11 */
331 #define LL_RCC_MCO1_DIV_12                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0)  /*!< MCO divided by 12 */
332 #define LL_RCC_MCO1_DIV_13                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2)  /*!< MCO divided by 13 */
333 #define LL_RCC_MCO1_DIV_14                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0)  /*!< MCO divided by 14 */
334 #define LL_RCC_MCO1_DIV_15                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1)  /*!< MCO divided by 15 */
335 #define LL_RCC_MCO1_DIV_16                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0)  /*!< MCO divided by 16 */
336 /**
337   * @}
338   */
339 
340 /** @defgroup RCC_LL_EC_MCO2_DIV  MCO2 prescaler
341   * @{
342   */
343 #define LL_RCC_MCO2_DIV_1                  0U                       /*!< MCO not divided */
344 #define LL_RCC_MCO2_DIV_2                  RCC_MCO2CFGR_MCO2DIV_0   /*!< MCO divided by 2 */
345 #define LL_RCC_MCO2_DIV_3                  RCC_MCO2CFGR_MCO2DIV_1   /*!< MCO divided by 3 */
346 #define LL_RCC_MCO2_DIV_4                  (RCC_MCO2CFGR_MCO2DIV_1 | RCC_MCO2CFGR_MCO2DIV_0)   /*!< MCO divided by 4 */
347 #define LL_RCC_MCO2_DIV_5                  RCC_MCO2CFGR_MCO2DIV_2   /*!< MCO divided by 5 */
348 #define LL_RCC_MCO2_DIV_6                  (RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_0)   /*!< MCO divided by 6 */
349 #define LL_RCC_MCO2_DIV_7                  (RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_1)   /*!< MCO divided by 7 */
350 #define LL_RCC_MCO2_DIV_8                  (RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_1 | RCC_MCO2CFGR_MCO2DIV_0)   /*!< MCO divided by 8 */
351 #define LL_RCC_MCO2_DIV_9                  RCC_MCO2CFGR_MCO2DIV_3   /*!< MCO divided by 9 */
352 #define LL_RCC_MCO2_DIV_10                 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_0)   /*!< MCO divided by 10 */
353 #define LL_RCC_MCO2_DIV_11                 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_1)   /*!< MCO divided by 11 */
354 #define LL_RCC_MCO2_DIV_12                 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_1 | RCC_MCO2CFGR_MCO2DIV_0)   /*!< MCO divided by 12 */
355 #define LL_RCC_MCO2_DIV_13                 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_2)   /*!< MCO divided by 13 */
356 #define LL_RCC_MCO2_DIV_14                 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_0)  /*!< MCO divided by 14 */
357 #define LL_RCC_MCO2_DIV_15                 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_1)  /*!< MCO divided by 15 */
358 #define LL_RCC_MCO2_DIV_16                 (RCC_MCO2CFGR_MCO2DIV_3 | RCC_MCO2CFGR_MCO2DIV_2 | RCC_MCO2CFGR_MCO2DIV_1 | RCC_MCO2CFGR_MCO2DIV_0)  /*!< MCO divided by 16 */
359 /**
360   * @}
361   */
362 
363 /** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
364   * @{
365   */
366 #define LL_RCC_RTC_HSE_DIV_1                0U
367 #define LL_RCC_RTC_HSE_DIV_2                RCC_RTCDIVR_RTCDIV_0
368 #define LL_RCC_RTC_HSE_DIV_3                RCC_RTCDIVR_RTCDIV_1
369 #define LL_RCC_RTC_HSE_DIV_4                (RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
370 #define LL_RCC_RTC_HSE_DIV_5                RCC_RTCDIVR_RTCDIV_2
371 #define LL_RCC_RTC_HSE_DIV_6                (RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0)
372 #define LL_RCC_RTC_HSE_DIV_7                (RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1)
373 #define LL_RCC_RTC_HSE_DIV_8                (RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
374 #define LL_RCC_RTC_HSE_DIV_9                RCC_RTCDIVR_RTCDIV_3
375 #define LL_RCC_RTC_HSE_DIV_10               (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_0)
376 #define LL_RCC_RTC_HSE_DIV_11               (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1)
377 #define LL_RCC_RTC_HSE_DIV_12               (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
378 #define LL_RCC_RTC_HSE_DIV_13               (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2)
379 #define LL_RCC_RTC_HSE_DIV_14               (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0)
380 #define LL_RCC_RTC_HSE_DIV_15               (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1)
381 #define LL_RCC_RTC_HSE_DIV_16               (RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
382 #define LL_RCC_RTC_HSE_DIV_17               RCC_RTCDIVR_RTCDIV_4
383 #define LL_RCC_RTC_HSE_DIV_18               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_0)
384 #define LL_RCC_RTC_HSE_DIV_19               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_1)
385 #define LL_RCC_RTC_HSE_DIV_20               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
386 #define LL_RCC_RTC_HSE_DIV_21               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2)
387 #define LL_RCC_RTC_HSE_DIV_22               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0)
388 #define LL_RCC_RTC_HSE_DIV_23               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1)
389 #define LL_RCC_RTC_HSE_DIV_24               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
390 #define LL_RCC_RTC_HSE_DIV_25               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3)
391 #define LL_RCC_RTC_HSE_DIV_26               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_0)
392 #define LL_RCC_RTC_HSE_DIV_27               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1)
393 #define LL_RCC_RTC_HSE_DIV_28               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
394 #define LL_RCC_RTC_HSE_DIV_29               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2)
395 #define LL_RCC_RTC_HSE_DIV_30               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0)
396 #define LL_RCC_RTC_HSE_DIV_31               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1)
397 #define LL_RCC_RTC_HSE_DIV_32               (RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
398 #define LL_RCC_RTC_HSE_DIV_33               RCC_RTCDIVR_RTCDIV_5
399 #define LL_RCC_RTC_HSE_DIV_34               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_0)
400 #define LL_RCC_RTC_HSE_DIV_35               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_1)
401 #define LL_RCC_RTC_HSE_DIV_36               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
402 #define LL_RCC_RTC_HSE_DIV_37               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_2)
403 #define LL_RCC_RTC_HSE_DIV_38               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0)
404 #define LL_RCC_RTC_HSE_DIV_39               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1)
405 #define LL_RCC_RTC_HSE_DIV_40               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
406 #define LL_RCC_RTC_HSE_DIV_41               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3)
407 #define LL_RCC_RTC_HSE_DIV_42               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_0)
408 #define LL_RCC_RTC_HSE_DIV_43               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1)
409 #define LL_RCC_RTC_HSE_DIV_44               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
410 #define LL_RCC_RTC_HSE_DIV_45               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2)
411 #define LL_RCC_RTC_HSE_DIV_46               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0)
412 #define LL_RCC_RTC_HSE_DIV_47               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1)
413 #define LL_RCC_RTC_HSE_DIV_48               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
414 #define LL_RCC_RTC_HSE_DIV_49               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4)
415 #define LL_RCC_RTC_HSE_DIV_50               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_0)
416 #define LL_RCC_RTC_HSE_DIV_51               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_1)
417 #define LL_RCC_RTC_HSE_DIV_52               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
418 #define LL_RCC_RTC_HSE_DIV_53               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2)
419 #define LL_RCC_RTC_HSE_DIV_54               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0)
420 #define LL_RCC_RTC_HSE_DIV_55               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1)
421 #define LL_RCC_RTC_HSE_DIV_56               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
422 #define LL_RCC_RTC_HSE_DIV_57               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3)
423 #define LL_RCC_RTC_HSE_DIV_58               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_0)
424 #define LL_RCC_RTC_HSE_DIV_59               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1)
425 #define LL_RCC_RTC_HSE_DIV_60               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
426 #define LL_RCC_RTC_HSE_DIV_61               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2)
427 #define LL_RCC_RTC_HSE_DIV_62               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_0)
428 #define LL_RCC_RTC_HSE_DIV_63               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1)
429 #define LL_RCC_RTC_HSE_DIV_64               (RCC_RTCDIVR_RTCDIV_5 | RCC_RTCDIVR_RTCDIV_4 | RCC_RTCDIVR_RTCDIV_3 | RCC_RTCDIVR_RTCDIV_2 | RCC_RTCDIVR_RTCDIV_1 | RCC_RTCDIVR_RTCDIV_0)
430 /**
431   * @}
432   */
433 
434 /** @defgroup RCC_LL_EC_MPU_CLKSOURCE  MPU clock switch
435   * @{
436   */
437 #define LL_RCC_MPU_CLKSOURCE_HSI                0U                    /*!< HSI selection as MPU clock */
438 #define LL_RCC_MPU_CLKSOURCE_HSE                RCC_MPCKSELR_MPUSRC_0 /*!< HSE selection as MPU clock */
439 #define LL_RCC_MPU_CLKSOURCE_PLL1               RCC_MPCKSELR_MPUSRC_1 /*!< PLL1 selection as MPU clock */
440 #define LL_RCC_MPU_CLKSOURCE_MPUDIV             (RCC_MPCKSELR_MPUSRC_1 | RCC_MPCKSELR_MPUSRC_0) /*!< MPUDIV selection as MPU clock */
441 /**
442   * @}
443   */
444 
445 /** @defgroup RCC_LL_EC_MPU_CLKSOURCE_STATUS  MPU clock switch status
446   * @{
447   */
448 #define LL_RCC_MPU_CLKSOURCE_STATUS_HSI         0U                    /*!< HSI used as MPU clock */
449 #define LL_RCC_MPU_CLKSOURCE_STATUS_HSE         RCC_MPCKSELR_MPUSRC_0 /*!< HSE used as MPU clock */
450 #define LL_RCC_MPU_CLKSOURCE_STATUS_PLL1        RCC_MPCKSELR_MPUSRC_1 /*!< PLL1 used as MPU clock */
451 #define LL_RCC_MPU_CLKSOURCE_STATUS_MPUDIV      (RCC_MPCKSELR_MPUSRC_1 | RCC_MPCKSELR_MPUSRC_0) /*!< MPUDIV used as MPU clock */
452 /**
453   * @}
454   */
455 
456 /** @defgroup RCC_LL_EC_MPU_DIV  MPUDIV prescaler
457   * @{
458   */
459 #define LL_RCC_MPU_DIV_OFF                      0U                     /*!< MPU div is disabled, no clock generated */
460 #define LL_RCC_MPU_DIV_2                        RCC_MPCKDIVR_MPUDIV_0  /*!< MPUSS is equal to pll1_p_ck divided by 2 */
461 #define LL_RCC_MPU_DIV_4                        RCC_MPCKDIVR_MPUDIV_1  /*!< MPUSS is equal to pll1_p_ck divided by 4 */
462 #define LL_RCC_MPU_DIV_8                        (RCC_MPCKDIVR_MPUDIV_1 | RCC_MPCKDIVR_MPUDIV_0) /*!< MPUSS is equal to pll1_p_ck divided by 8 */
463 #define LL_RCC_MPU_DIV_16                       RCC_MPCKDIVR_MPUDIV_2  /*!< MPUSS is equal to pll1_p_ck divided by 16 */
464 /**
465   * @}
466   */
467 
468 /** @defgroup RCC_LL_EC_AXISS_CLKSOURCE  AXISS clock switch
469   * @{
470   */
471 #define LL_RCC_AXISS_CLKSOURCE_HSI              0U                      /*!< HSI selection as AXISS clock */
472 #define LL_RCC_AXISS_CLKSOURCE_HSE              RCC_ASSCKSELR_AXISSRC_0 /*!< HSE selection as AXISS clock */
473 #define LL_RCC_AXISS_CLKSOURCE_PLL2             RCC_ASSCKSELR_AXISSRC_1 /*!< PLL2 selection as AXISS clock */
474 #define LL_RCC_AXISS_CLKSOURCE_OFF              (RCC_ASSCKSELR_AXISSRC_1 | RCC_ASSCKSELR_AXISSRC_0) /*!< AXISS is gated */
475 /**
476   * @}
477   */
478 
479 /** @defgroup RCC_LL_EC_AXISS_CLKSOURCE_STATUS  AXISS clock switch status
480   * @{
481   */
482 #define LL_RCC_AXISS_CLKSOURCE_STATUS_HSI       0U                      /*!< HSI used as AXISS clock */
483 #define LL_RCC_AXISS_CLKSOURCE_STATUS_HSE       RCC_ASSCKSELR_AXISSRC_0 /*!< HSE used as AXISS clock */
484 #define LL_RCC_AXISS_CLKSOURCE_STATUS_PLL2      RCC_ASSCKSELR_AXISSRC_1 /*!< PLL2 used as AXISS clock */
485 #define LL_RCC_AXISS_CLKSOURCE_STATUS_OFF       (RCC_ASSCKSELR_AXISSRC_1 | RCC_ASSCKSELR_AXISSRC_0) /*!< AXISS is gated */
486 /**
487   * @}
488   */
489 
490 /** @defgroup RCC_LL_EC_AXI_DIV  AXI, AHB5 and AHB6 prescaler
491   * @{
492   */
493 #define LL_RCC_AXI_DIV_1                        0U  /*!< AXISS not divided */
494 #define LL_RCC_AXI_DIV_2                        RCC_AXIDIVR_AXIDIV_0  /*!< AXISS divided by 2 */
495 #define LL_RCC_AXI_DIV_3                        RCC_AXIDIVR_AXIDIV_1  /*!< AXISS divided by 3 */
496 #define LL_RCC_AXI_DIV_4                        RCC_AXIDIVR_AXIDIV_2  /*!< AXISS divided by 4 */
497 /**
498   * @}
499   */
500 
501 /** @defgroup RCC_LL_EC_MCUSS_CLKSOURCE  MCUSS clock switch
502   * @{
503   */
504 #define LL_RCC_MCUSS_CLKSOURCE_HSI              0U                      /*!< HSI selection as MCUSS clock */
505 #define LL_RCC_MCUSS_CLKSOURCE_HSE              RCC_MSSCKSELR_MCUSSRC_0 /*!< HSE selection as MCUSS clock */
506 #define LL_RCC_MCUSS_CLKSOURCE_CSI              RCC_MSSCKSELR_MCUSSRC_1 /*!< CSI selection as MCUSS clock */
507 #define LL_RCC_MCUSS_CLKSOURCE_PLL3             (RCC_MSSCKSELR_MCUSSRC_1 | RCC_MSSCKSELR_MCUSSRC_0) /*!< PLL3 selection as MCUSS clock */
508 /**
509   * @}
510   */
511 
512 /** @defgroup RCC_LL_EC_MCUSS_CLKSOURCE_STATUS  MCUSS clock switch status
513   * @{
514   */
515 #define LL_RCC_MCUSS_CLKSOURCE_STATUS_HSI       0U                      /*!< HSI used as MCUSS clock */
516 #define LL_RCC_MCUSS_CLKSOURCE_STATUS_HSE       RCC_MSSCKSELR_MCUSSRC_0 /*!< HSE used as MCUSS clock */
517 #define LL_RCC_MCUSS_CLKSOURCE_STATUS_CSI       RCC_MSSCKSELR_MCUSSRC_1 /*!< CSI used as MCUSS clock */
518 #define LL_RCC_MCUSS_CLKSOURCE_STATUS_PLL3      (RCC_MSSCKSELR_MCUSSRC_1 | RCC_MSSCKSELR_MCUSSRC_0) /*!< PLL3 used as MCUSS clock */
519 /**
520   * @}
521   */
522 
523 /** @defgroup RCC_LL_EC_MCU_DIV  MCUDIV prescaler
524   * @{
525   */
526 #define LL_RCC_MCU_DIV_1                        0U                                            /*!< MCUSS not divided */
527 #define LL_RCC_MCU_DIV_2                        RCC_MCUDIVR_MCUDIV_0                          /*!< MCUSS divided by 2 */
528 #define LL_RCC_MCU_DIV_4                        RCC_MCUDIVR_MCUDIV_1                          /*!< MCUSS divided by 4 */
529 #define LL_RCC_MCU_DIV_8                        (RCC_MCUDIVR_MCUDIV_1 | RCC_MCUDIVR_MCUDIV_0) /*!< MCUSS divided by 8 */
530 #define LL_RCC_MCU_DIV_16                       RCC_MCUDIVR_MCUDIV_2                          /*!< MCUSS divided by 16 */
531 #define LL_RCC_MCU_DIV_32                       (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_0) /*!< MCUSS divided by 32 */
532 #define LL_RCC_MCU_DIV_64                       (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_1) /*!< MCUSS divided by 64 */
533 #define LL_RCC_MCU_DIV_128                      (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_1 | RCC_MCUDIVR_MCUDIV_0) /*!< MCUSS divided by 128 */
534 #define LL_RCC_MCU_DIV_256                      RCC_MCUDIVR_MCUDIV_3                          /*!< MCUSS divided by 256 */
535 #define LL_RCC_MCU_DIV_512                      (RCC_MCUDIVR_MCUDIV_3 | RCC_MCUDIVR_MCUDIV_0) /*!< MCUSS divided by 512 */
536 /**
537   * @}
538   */
539 
540 /** @defgroup RCC_LL_EC_APB1_DIV  APB1 prescaler
541   * @{
542   */
543 #define LL_RCC_APB1_DIV_1                       0U                                                 /*!< mlhclk not divided (default after reset) */
544 #define LL_RCC_APB1_DIV_2                       RCC_APB1DIVR_APB1DIV_0                             /*!< mlhclk divided by 2 */
545 #define LL_RCC_APB1_DIV_4                       RCC_APB1DIVR_APB1DIV_1                             /*!< mlhclk divided by 4 */
546 #define LL_RCC_APB1_DIV_8                       (RCC_APB1DIVR_APB1DIV_1 | RCC_APB1DIVR_APB1DIV_0)  /*!< mlhclk divided by 8 */
547 #define LL_RCC_APB1_DIV_16                      RCC_APB1DIVR_APB1DIV_2                             /*!< mlhclk divided by 16 */
548 /**
549   * @}
550   */
551 
552 /** @defgroup RCC_LL_EC_APB2_DIV  APB2 prescaler
553   * @{
554   */
555 #define LL_RCC_APB2_DIV_1                       0U                                                 /*!< mlhclk not divided (default after reset) */
556 #define LL_RCC_APB2_DIV_2                       RCC_APB2DIVR_APB2DIV_0                             /*!< mlhclk divided by 2 */
557 #define LL_RCC_APB2_DIV_4                       RCC_APB2DIVR_APB2DIV_1                             /*!< mlhclk divided by 4 */
558 #define LL_RCC_APB2_DIV_8                       (RCC_APB2DIVR_APB2DIV_1 | RCC_APB2DIVR_APB2DIV_0)  /*!< mlhclk divided by 8 */
559 #define LL_RCC_APB2_DIV_16                      RCC_APB2DIVR_APB2DIV_2                             /*!< mlhclk divided by 16 */
560 /**
561   * @}
562   */
563 
564 /** @defgroup RCC_LL_EC_APB3_DIV  APB3 prescaler
565   * @{
566   */
567 #define LL_RCC_APB3_DIV_1                       0U                                                /*!< mlhclk not divided (default after reset) */
568 #define LL_RCC_APB3_DIV_2                       RCC_APB3DIVR_APB3DIV_0                            /*!< mlhclk divided by 2 */
569 #define LL_RCC_APB3_DIV_4                       RCC_APB3DIVR_APB3DIV_1                            /*!< mlhclk divided by 4 */
570 #define LL_RCC_APB3_DIV_8                       (RCC_APB3DIVR_APB3DIV_1| RCC_APB3DIVR_APB3DIV_0)  /*!< mlhclk divided by 8 */
571 #define LL_RCC_APB3_DIV_16                      RCC_APB3DIVR_APB3DIV_2                            /*!< mlhclk divided by 16 */
572 /**
573   * @}
574   */
575 
576 /** @defgroup RCC_LL_EC_APB4_DIV  APB4 prescaler
577   * @{
578   */
579 #define LL_RCC_APB4_DIV_1                       0U                                                 /*!< aclk not divided (default after reset) */
580 #define LL_RCC_APB4_DIV_2                       RCC_APB4DIVR_APB4DIV_0                             /*!< aclk divided by 2 */
581 #define LL_RCC_APB4_DIV_4                       RCC_APB4DIVR_APB4DIV_1                             /*!< aclk divided by 4 */
582 #define LL_RCC_APB4_DIV_8                       (RCC_APB4DIVR_APB4DIV_1 | RCC_APB4DIVR_APB4DIV_0)  /*!< aclk divided by 8 */
583 #define LL_RCC_APB4_DIV_16                      RCC_APB4DIVR_APB4DIV_2                             /*!< aclk divided by 16 */
584 /**
585   * @}
586   */
587 
588 /** @defgroup RCC_LL_EC_APB5_DIV  APB5 prescaler
589   * @{
590   */
591 #define LL_RCC_APB5_DIV_1                       0U                                                 /*!< aclk not divided (default after reset) */
592 #define LL_RCC_APB5_DIV_2                       RCC_APB5DIVR_APB5DIV_0                             /*!< aclk divided by 2 */
593 #define LL_RCC_APB5_DIV_4                       RCC_APB5DIVR_APB5DIV_1                             /*!< aclk divided by 4 */
594 #define LL_RCC_APB5_DIV_8                       (RCC_APB5DIVR_APB5DIV_1 | RCC_APB5DIVR_APB5DIV_0)  /*!< aclk divided by 8 */
595 #define LL_RCC_APB5_DIV_16                      RCC_APB5DIVR_APB5DIV_2                             /*!< aclk divided by 16 */
596 /**
597   * @}
598   */
599 
600 /** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
601   * @{
602   */
603 #define LL_RCC_LSEDRIVE_LOW                     0U                                        /*!< Xtal mode lower driving capability */
604 #define LL_RCC_LSEDRIVE_MEDIUMLOW               RCC_BDCR_LSEDRV_0                         /*!< Xtal mode medium low driving capability */
605 #define LL_RCC_LSEDRIVE_MEDIUMHIGH              RCC_BDCR_LSEDRV_1                         /*!< Xtal mode medium high driving capability */
606 #define LL_RCC_LSEDRIVE_HIGH                    (RCC_BDCR_LSEDRV_1 | RCC_BDCR_LSEDRV_0)   /*!< Xtal mode higher driving capability */
607 /**
608   * @}
609   */
610 
611 #if defined(USE_FULL_LL_DRIVER)
612 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
613   * @{
614   */
615 #define LL_RCC_PERIPH_FREQUENCY_NO              0x00000000U /*!< No clock enabled for the peripheral */
616 #define LL_RCC_PERIPH_FREQUENCY_NA              0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
617 /**
618   * @}
619   */
620 #endif /* USE_FULL_LL_DRIVER */
621 
622 
623 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
624   * @{
625   */
626 #define LL_RCC_I2C12_CLKSOURCE_PCLK1        LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, 0)
627 #define LL_RCC_I2C12_CLKSOURCE_PLL4R        LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_0)
628 #define LL_RCC_I2C12_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_1)
629 #define LL_RCC_I2C12_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, (RCC_I2C12CKSELR_I2C12SRC_1 | RCC_I2C12CKSELR_I2C12SRC_0))
630 
631 #define LL_RCC_I2C35_CLKSOURCE_PCLK1        LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, 0)
632 #define LL_RCC_I2C35_CLKSOURCE_PLL4R        LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_0)
633 #define LL_RCC_I2C35_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_1)
634 #define LL_RCC_I2C35_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, (RCC_I2C35CKSELR_I2C35SRC_1 | RCC_I2C35CKSELR_I2C35SRC_0))
635 
636 #define LL_RCC_I2C46_CLKSOURCE_PCLK5        LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, 0)
637 #define LL_RCC_I2C46_CLKSOURCE_PLL3Q        LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_0)
638 #define LL_RCC_I2C46_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_1)
639 #define LL_RCC_I2C46_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, (RCC_I2C46CKSELR_I2C46SRC_1 | RCC_I2C46CKSELR_I2C46SRC_0))
640 /**
641   * @}
642   */
643 
644 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
645   * @{
646   */
647 #define LL_RCC_SAI1_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, 0)
648 #define LL_RCC_SAI1_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_0)
649 #define LL_RCC_SAI1_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_1)
650 #define LL_RCC_SAI1_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, (RCC_SAI1CKSELR_SAI1SRC_1 | RCC_SAI1CKSELR_SAI1SRC_0))
651 #define LL_RCC_SAI1_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_2)
652 
653 #define LL_RCC_SAI2_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, 0)
654 #define LL_RCC_SAI2_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_0)
655 #define LL_RCC_SAI2_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_1)
656 #define LL_RCC_SAI2_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, (RCC_SAI2CKSELR_SAI2SRC_1 | RCC_SAI2CKSELR_SAI2SRC_0))
657 #define LL_RCC_SAI2_CLKSOURCE_SPDIF         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_2)
658 #define LL_RCC_SAI2_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, (RCC_SAI2CKSELR_SAI2SRC_2 | RCC_SAI2CKSELR_SAI2SRC_0))
659 
660 #define LL_RCC_SAI3_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, 0)
661 #define LL_RCC_SAI3_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_0)
662 #define LL_RCC_SAI3_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_1)
663 #define LL_RCC_SAI3_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, (RCC_SAI3CKSELR_SAI3SRC_1 | RCC_SAI3CKSELR_SAI3SRC_0))
664 #define LL_RCC_SAI3_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_2)
665 
666 #define LL_RCC_SAI4_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, 0)
667 #define LL_RCC_SAI4_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_0)
668 #define LL_RCC_SAI4_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_1)
669 #define LL_RCC_SAI4_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, (RCC_SAI4CKSELR_SAI4SRC_1 | RCC_SAI4CKSELR_SAI4SRC_0))
670 #define LL_RCC_SAI4_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_2)
671 /**
672   * @}
673   */
674 
675 /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI/I2S clock source selection
676   * @{
677   */
678 #define LL_RCC_SPI1_CLKSOURCE_PLL4P         LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, 0)
679 #define LL_RCC_SPI1_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_0)
680 #define LL_RCC_SPI1_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_1)
681 #define LL_RCC_SPI1_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, (RCC_SPI2S1CKSELR_SPI1SRC_1 | RCC_SPI2S1CKSELR_SPI1SRC_0))
682 #define LL_RCC_SPI1_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_2)
683 
684 #define LL_RCC_SPI23_CLKSOURCE_PLL4P        LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, 0)
685 #define LL_RCC_SPI23_CLKSOURCE_PLL3Q        LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_0)
686 #define LL_RCC_SPI23_CLKSOURCE_I2SCKIN      LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_1)
687 #define LL_RCC_SPI23_CLKSOURCE_PER          LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, (RCC_SPI2S23CKSELR_SPI23SRC_1 | RCC_SPI2S23CKSELR_SPI23SRC_0))
688 #define LL_RCC_SPI23_CLKSOURCE_PLL3R        LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_2)
689 
690 #define LL_RCC_SPI45_CLKSOURCE_PCLK2        LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, 0)
691 #define LL_RCC_SPI45_CLKSOURCE_PLL4Q        LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_0)
692 #define LL_RCC_SPI45_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_1)
693 #define LL_RCC_SPI45_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, (RCC_SPI45CKSELR_SPI45SRC_1 | RCC_SPI45CKSELR_SPI45SRC_0))
694 #define LL_RCC_SPI45_CLKSOURCE_HSE          LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_2)
695 
696 #define LL_RCC_SPI6_CLKSOURCE_PCLK5         LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, 0)
697 #define LL_RCC_SPI6_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_0)
698 #define LL_RCC_SPI6_CLKSOURCE_HSI           LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_1)
699 #define LL_RCC_SPI6_CLKSOURCE_CSI           LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, (RCC_SPI6CKSELR_SPI6SRC_1 | RCC_SPI6CKSELR_SPI6SRC_0))
700 #define LL_RCC_SPI6_CLKSOURCE_HSE           LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_2)
701 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, (RCC_SPI6CKSELR_SPI6SRC_2 | RCC_SPI6CKSELR_SPI6SRC_0))
702 /**
703   * @}
704   */
705 
706 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
707   * @{
708   */
709 #define LL_RCC_USART1_CLKSOURCE_PCLK5       LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, 0)
710 #define LL_RCC_USART1_CLKSOURCE_PLL3Q       LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_0)
711 #define LL_RCC_USART1_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_1)
712 #define LL_RCC_USART1_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, (RCC_UART1CKSELR_UART1SRC_1 | RCC_UART1CKSELR_UART1SRC_0))
713 #define LL_RCC_USART1_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_2)
714 #define LL_RCC_USART1_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, (RCC_UART1CKSELR_UART1SRC_2 | RCC_UART1CKSELR_UART1SRC_0))
715 
716 #define LL_RCC_UART24_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, 0)
717 #define LL_RCC_UART24_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_0)
718 #define LL_RCC_UART24_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_1)
719 #define LL_RCC_UART24_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, (RCC_UART24CKSELR_UART24SRC_1 | RCC_UART24CKSELR_UART24SRC_0))
720 #define LL_RCC_UART24_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_2)
721 
722 #define LL_RCC_UART35_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, 0)
723 #define LL_RCC_UART35_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_0)
724 #define LL_RCC_UART35_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_1)
725 #define LL_RCC_UART35_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, (RCC_UART35CKSELR_UART35SRC_1 | RCC_UART35CKSELR_UART35SRC_0))
726 #define LL_RCC_UART35_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_2)
727 
728 #define LL_RCC_USART6_CLKSOURCE_PCLK2       LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, 0)
729 #define LL_RCC_USART6_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_0)
730 #define LL_RCC_USART6_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_1)
731 #define LL_RCC_USART6_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, (RCC_UART6CKSELR_UART6SRC_1 | RCC_UART6CKSELR_UART6SRC_0))
732 #define LL_RCC_USART6_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_2)
733 
734 #define LL_RCC_UART78_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, 0)
735 #define LL_RCC_UART78_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_0)
736 #define LL_RCC_UART78_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_1)
737 #define LL_RCC_UART78_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, (RCC_UART78CKSELR_UART78SRC_1 | RCC_UART78CKSELR_UART78SRC_0))
738 #define LL_RCC_UART78_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_2)
739 /**
740   * @}
741   */
742 
743 /** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE  Peripheral SDMMC clock source selection
744   * @{
745   */
746 #define LL_RCC_SDMMC12_CLKSOURCE_HCLK6      LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, 0)
747 #define LL_RCC_SDMMC12_CLKSOURCE_PLL3R      LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_0)
748 #define LL_RCC_SDMMC12_CLKSOURCE_PLL4P      LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_1)
749 #define LL_RCC_SDMMC12_CLKSOURCE_HSI        LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, (RCC_SDMMC12CKSELR_SDMMC12SRC_1 | RCC_SDMMC12CKSELR_SDMMC12SRC_0))
750 
751 #define LL_RCC_SDMMC3_CLKSOURCE_HCLK2       LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, 0)
752 #define LL_RCC_SDMMC3_CLKSOURCE_PLL3R       LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_0)
753 #define LL_RCC_SDMMC3_CLKSOURCE_PLL4P       LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_1)
754 #define LL_RCC_SDMMC3_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, (RCC_SDMMC3CKSELR_SDMMC3SRC_1 | RCC_SDMMC3CKSELR_SDMMC3SRC_0))
755 /**
756   * @}
757   */
758 
759 /** @defgroup RCC_LL_EC_ETH_CLKSOURCE  Peripheral ETH clock source selection
760   * @{
761   */
762 #define LL_RCC_ETH_CLKSOURCE_PLL4P          0U
763 #define LL_RCC_ETH_CLKSOURCE_PLL3Q          RCC_ETHCKSELR_ETHSRC_0
764 #define LL_RCC_ETH_CLKSOURCE_OFF            RCC_ETHCKSELR_ETHSRC_1
765 /**
766   * @}
767   */
768 
769 /** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI clock source selection
770   * @{
771   */
772 #define LL_RCC_QSPI_CLKSOURCE_ACLK          0U
773 #define LL_RCC_QSPI_CLKSOURCE_PLL3R         RCC_QSPICKSELR_QSPISRC_0
774 #define LL_RCC_QSPI_CLKSOURCE_PLL4P         RCC_QSPICKSELR_QSPISRC_1
775 #define LL_RCC_QSPI_CLKSOURCE_PER           (RCC_QSPICKSELR_QSPISRC_1 | RCC_QSPICKSELR_QSPISRC_0)
776 /**
777   * @}
778   */
779 
780 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC clock source selection
781   * @{
782   */
783 #define LL_RCC_FMC_CLKSOURCE_ACLK           0U
784 #define LL_RCC_FMC_CLKSOURCE_PLL3R          RCC_FMCCKSELR_FMCSRC_0
785 #define LL_RCC_FMC_CLKSOURCE_PLL4P          RCC_FMCCKSELR_FMCSRC_1
786 #define LL_RCC_FMC_CLKSOURCE_PER            (RCC_FMCCKSELR_FMCSRC_1 | RCC_FMCCKSELR_FMCSRC_0)
787 /**
788   * @}
789   */
790 
791 #if defined(FDCAN1)
792 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection
793   * @{
794   */
795 #define LL_RCC_FDCAN_CLKSOURCE_HSE          0U
796 #define LL_RCC_FDCAN_CLKSOURCE_PLL3Q        RCC_FDCANCKSELR_FDCANSRC_0
797 #define LL_RCC_FDCAN_CLKSOURCE_PLL4Q        RCC_FDCANCKSELR_FDCANSRC_1
798 #define LL_RCC_FDCAN_CLKSOURCE_PLL4R        (RCC_FDCANCKSELR_FDCANSRC_1 | RCC_FDCANCKSELR_FDCANSRC_0)
799 /**
800   * @}
801   */
802 #endif /*FDCAN1*/
803 
804 /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE  Peripheral SPDIFRX clock source selection
805   * @{
806   */
807 #define LL_RCC_SPDIFRX_CLKSOURCE_PLL4P      0U
808 #define LL_RCC_SPDIFRX_CLKSOURCE_PLL3Q      RCC_SPDIFCKSELR_SPDIFSRC_0
809 #define LL_RCC_SPDIFRX_CLKSOURCE_HSI        RCC_SPDIFCKSELR_SPDIFSRC_1
810 /**
811   * @}
812   */
813 
814 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
815   * @{
816   */
817 #define LL_RCC_CEC_CLKSOURCE_LSE            0U
818 #define LL_RCC_CEC_CLKSOURCE_LSI            RCC_CECCKSELR_CECSRC_0
819 #define LL_RCC_CEC_CLKSOURCE_CSI122         RCC_CECCKSELR_CECSRC_1
820 /**
821   * @}
822   */
823 
824 /** @defgroup RCC_LL_EC_USBPHY_CLKSOURCE  Peripheral USBPHY clock source selection
825   * @{
826   */
827 #define LL_RCC_USBPHY_CLKSOURCE_HSE         0U
828 #define LL_RCC_USBPHY_CLKSOURCE_PLL4R       RCC_USBCKSELR_USBPHYSRC_0
829 #define LL_RCC_USBPHY_CLKSOURCE_HSE2        RCC_USBCKSELR_USBPHYSRC_1
830 /**
831   * @}
832   */
833 
834 /** @defgroup RCC_LL_EC_USBO_CLKSOURCE  Peripheral USBO clock source selection
835   * @{
836   */
837 #define LL_RCC_USBO_CLKSOURCE_PLL4R         0U
838 #define LL_RCC_USBO_CLKSOURCE_PHY           RCC_USBCKSELR_USBOSRC
839 /**
840   * @}
841   */
842 
843 /** @defgroup RCC_LL_EC_RNGx_CLKSOURCE  Peripheral RNG clock source selection
844   * @{
845   */
846 #define LL_RCC_RNG1_CLKSOURCE_CSI           LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, 0)
847 #define LL_RCC_RNG1_CLKSOURCE_PLL4R         LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_0)
848 #define LL_RCC_RNG1_CLKSOURCE_LSE           LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_1)
849 #define LL_RCC_RNG1_CLKSOURCE_LSI           LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, (RCC_RNG1CKSELR_RNG1SRC_1 | RCC_RNG1CKSELR_RNG1SRC_0))
850 
851 #define LL_RCC_RNG2_CLKSOURCE_CSI           LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, 0)
852 #define LL_RCC_RNG2_CLKSOURCE_PLL4R         LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_0)
853 #define LL_RCC_RNG2_CLKSOURCE_LSE           LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_1)
854 #define LL_RCC_RNG2_CLKSOURCE_LSI           LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, (RCC_RNG2CKSELR_RNG2SRC_1 | RCC_RNG2CKSELR_RNG2SRC_0))
855 /**
856   * @}
857   */
858 
859 /** @defgroup RCC_LL_EC_CKPER_CLKSOURCE  Peripheral CKPER clock source selection
860   * @{
861   */
862 #define LL_RCC_CKPER_CLKSOURCE_HSI          0U
863 #define LL_RCC_CKPER_CLKSOURCE_CSI          RCC_CPERCKSELR_CKPERSRC_0
864 #define LL_RCC_CKPER_CLKSOURCE_HSE          RCC_CPERCKSELR_CKPERSRC_1
865 #define LL_RCC_CKPER_CLKSOURCE_OFF          (RCC_CPERCKSELR_CKPERSRC_1 | RCC_CPERCKSELR_CKPERSRC_0) /*Clock disabled*/
866 /**
867   * @}
868   */
869 
870 /** @defgroup RCC_LL_EC_STGEN_CLKSOURCE  Peripheral STGEN clock source selection
871   * @{
872   */
873 #define LL_RCC_STGEN_CLKSOURCE_HSI          0U
874 #define LL_RCC_STGEN_CLKSOURCE_HSE          RCC_STGENCKSELR_STGENSRC_0
875 #define LL_RCC_STGEN_CLKSOURCE_OFF          RCC_STGENCKSELR_STGENSRC_1
876 /**
877   * @}
878   */
879 
880 #if defined(DSI)
881 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral  DSI clock source selection
882   * @{
883   */
884 #define LL_RCC_DSI_CLKSOURCE_PHY            0U
885 #define LL_RCC_DSI_CLKSOURCE_PLL4P          RCC_DSICKSELR_DSISRC
886 /**
887   * @}
888   */
889 #endif /*DSI*/
890 
891 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
892   * @{
893   */
894 #define LL_RCC_ADC_CLKSOURCE_PLL4R          0U
895 #define LL_RCC_ADC_CLKSOURCE_PER            RCC_ADCCKSELR_ADCSRC_0
896 #define LL_RCC_ADC_CLKSOURCE_PLL3Q          RCC_ADCCKSELR_ADCSRC_1
897 /**
898   * @}
899   */
900 
901 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM clock source selection
902   * @{
903   */
904 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, 0)
905 #define LL_RCC_LPTIM1_CLKSOURCE_PLL4P       LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_0)
906 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3Q       LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_1)
907 #define LL_RCC_LPTIM1_CLKSOURCE_LSE         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_1 | RCC_LPTIM1CKSELR_LPTIM1SRC_0))
908 #define LL_RCC_LPTIM1_CLKSOURCE_LSI         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_2)
909 #define LL_RCC_LPTIM1_CLKSOURCE_PER         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_0))
910 #define LL_RCC_LPTIM1_CLKSOURCE_OFF         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_1))
911 
912 #define LL_RCC_LPTIM23_CLKSOURCE_PCLK3      LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, 0)
913 #define LL_RCC_LPTIM23_CLKSOURCE_PLL4Q      LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_0)
914 #define LL_RCC_LPTIM23_CLKSOURCE_PER        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_1)
915 #define LL_RCC_LPTIM23_CLKSOURCE_LSE        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, (RCC_LPTIM23CKSELR_LPTIM23SRC_1 | RCC_LPTIM23CKSELR_LPTIM23SRC_0))
916 #define LL_RCC_LPTIM23_CLKSOURCE_LSI        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_2)
917 #define LL_RCC_LPTIM23_CLKSOURCE_OFF        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, (RCC_LPTIM23CKSELR_LPTIM23SRC_2 | RCC_LPTIM23CKSELR_LPTIM23SRC_0))
918 
919 #define LL_RCC_LPTIM45_CLKSOURCE_PCLK3      LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, 0)
920 #define LL_RCC_LPTIM45_CLKSOURCE_PLL4P      LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_0)
921 #define LL_RCC_LPTIM45_CLKSOURCE_PLL3Q      LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_1)
922 #define LL_RCC_LPTIM45_CLKSOURCE_LSE        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_1 | RCC_LPTIM45CKSELR_LPTIM45SRC_0))
923 #define LL_RCC_LPTIM45_CLKSOURCE_LSI        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_2)
924 #define LL_RCC_LPTIM45_CLKSOURCE_PER        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_0))
925 #define LL_RCC_LPTIM45_CLKSOURCE_OFF        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_1))
926 /**
927   * @}
928   */
929 
930 /** @defgroup RCC_LL_EC_TIMGx_Prescaler_Selection TIMG Prescaler selection
931   * @{
932   */
933 #define LL_RCC_TIMG1PRES_DEACTIVATED        LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, 0)
934 #define LL_RCC_TIMG1PRES_ACTIVATED          LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, RCC_TIMG1PRER_TIMG1PRE)
935 
936 #define LL_RCC_TIMG2PRES_DEACTIVATED        LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, 0)
937 #define LL_RCC_TIMG2PRES_ACTIVATED          LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, RCC_TIMG2PRER_TIMG2PRE)
938 /**
939   * @}
940   */
941 
942 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
943   * @{
944   */
945 #define LL_RCC_RTC_CLKSOURCE_NONE           0U                                       /*!< No clock used as RTC clock */
946 #define LL_RCC_RTC_CLKSOURCE_LSE            RCC_BDCR_RTCSRC_0                        /*!< LSE oscillator clock used as RTC clock */
947 #define LL_RCC_RTC_CLKSOURCE_LSI            RCC_BDCR_RTCSRC_1                        /*!< LSI oscillator clock used as RTC clock */
948 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV        (RCC_BDCR_RTCSRC_1 | RCC_BDCR_RTCSRC_0)  /*!< HSE oscillator clock divided by RTCDIV used as RTC clock */
949 /**
950   * @}
951   */
952 
953 /** @defgroup RCC_LL_EC_I2Cx  Peripheral I2C get clock source
954   * @{
955   */
956 #define LL_RCC_I2C12_CLKSOURCE        LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, 0x00000000U)
957 #define LL_RCC_I2C35_CLKSOURCE        LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, 0x00000000U)
958 #define LL_RCC_I2C46_CLKSOURCE        LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, 0x00000000U)
959 /**
960   * @}
961   */
962 
963 /** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source
964   * @{
965   */
966 #define LL_RCC_SAI1_CLKSOURCE         LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, 0x00000000U)
967 #define LL_RCC_SAI2_CLKSOURCE         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, 0x00000000U)
968 #define LL_RCC_SAI3_CLKSOURCE         LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, 0x00000000U)
969 #define LL_RCC_SAI4_CLKSOURCE         LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, 0x00000000U)
970 /**
971   * @}
972   */
973 
974 /** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
975   * @{
976   */
977 /* @note DFSDM and SA1 share the same kernel clock Muxer */
978 #define LL_RCC_DFSDM_CLKSOURCE        LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, 0x00000000U)
979 /**
980   * @}
981   */
982 
983 /** @defgroup RCC_LL_EC_SPIx  Peripheral SPI/I2S get clock source
984   * @{
985   */
986 #define LL_RCC_SPI1_CLKSOURCE         LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, 0x00000000U)
987 #define LL_RCC_SPI23_CLKSOURCE        LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, 0x00000000U)
988 #define LL_RCC_SPI45_CLKSOURCE        LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, 0x00000000U)
989 #define LL_RCC_SPI6_CLKSOURCE         LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, 0x00000000U)
990 /**
991   * @}
992   */
993 
994 /** @defgroup RCC_LL_EC_USARTx  Peripheral USART get clock source
995   * @{
996   */
997 #define LL_RCC_USART1_CLKSOURCE       LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, 0x00000000U)
998 #define LL_RCC_UART24_CLKSOURCE       LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, 0x00000000U)
999 #define LL_RCC_UART35_CLKSOURCE       LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, 0x00000000U)
1000 #define LL_RCC_USART6_CLKSOURCE       LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, 0x00000000U)
1001 #define LL_RCC_UART78_CLKSOURCE       LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, 0x00000000U)
1002 /**
1003   * @}
1004   */
1005 
1006 /** @defgroup RCC_LL_EC_SDMMCx  Peripheral SDMMC get clock source
1007   * @{
1008   */
1009 #define LL_RCC_SDMMC12_CLKSOURCE      LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, 0x00000000U)
1010 #define LL_RCC_SDMMC3_CLKSOURCE       LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, 0x00000000U)
1011 /**
1012   * @}
1013   */
1014 
1015 /** @defgroup RCC_LL_EC_ETH  Peripheral ETH get clock source
1016   * @{
1017   */
1018 #define LL_RCC_ETH_CLKSOURCE          RCC_ETHCKSELR_ETHSRC
1019 /**
1020   * @}
1021   */
1022 
1023 /** @defgroup RCC_LL_EC_QSPI  Peripheral QSPI get clock source
1024   * @{
1025   */
1026 #define LL_RCC_QSPI_CLKSOURCE         RCC_QSPICKSELR_QSPISRC
1027 /**
1028   * @}
1029   */
1030 
1031 /** @defgroup RCC_LL_EC_FMC  Peripheral FMC get clock source
1032   * @{
1033   */
1034 #define LL_RCC_FMC_CLKSOURCE          RCC_FMCCKSELR_FMCSRC
1035 /**
1036   * @}
1037   */
1038 
1039 #if defined(FDCAN1)
1040 /** @defgroup RCC_LL_EC_FDCAN  Peripheral FDCAN get clock source
1041   * @{
1042   */
1043 #define LL_RCC_FDCAN_CLKSOURCE        RCC_FDCANCKSELR_FDCANSRC
1044 /**
1045   * @}
1046   */
1047 #endif /*FDCAN1*/
1048 
1049 /** @defgroup RCC_LL_EC_SPDIFRX  Peripheral SPDIFRX get clock source
1050   * @{
1051   */
1052 #define LL_RCC_SPDIFRX_CLKSOURCE      RCC_SPDIFCKSELR_SPDIFSRC
1053 /**
1054   * @}
1055   */
1056 
1057 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
1058   * @{
1059   */
1060 #define LL_RCC_CEC_CLKSOURCE          RCC_CECCKSELR_CECSRC
1061 /**
1062   * @}
1063   */
1064 
1065 /** @defgroup RCC_LL_EC_USBPHY Peripheral USBPHY get clock source
1066   * @{
1067   */
1068 #define LL_RCC_USBPHY_CLKSOURCE       RCC_USBCKSELR_USBPHYSRC
1069 /**
1070   * @}
1071   */
1072 
1073 /** @defgroup RCC_LL_EC_USBO  Peripheral USBO get clock source
1074   * @{
1075   */
1076 #define LL_RCC_USBO_CLKSOURCE         RCC_USBCKSELR_USBOSRC
1077 /**
1078   * @}
1079   */
1080 
1081 /** @defgroup RCC_LL_EC_RNGx Peripheral RNG get clock source
1082   * @{
1083   */
1084 #define LL_RCC_RNG1_CLKSOURCE         LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, 0x00000000U)
1085 #define LL_RCC_RNG2_CLKSOURCE         LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, 0x00000000U)
1086 /**
1087   * @}
1088   */
1089 
1090 /** @defgroup RCC_LL_EC_CKPER Peripheral CKPER get clock source
1091   * @{
1092   */
1093 #define LL_RCC_CKPER_CLKSOURCE        RCC_CPERCKSELR_CKPERSRC
1094 /**
1095   * @}
1096   */
1097 
1098 /** @defgroup RCC_LL_EC_STGEN Peripheral STGEN get clock source
1099   * @{
1100   */
1101 #define LL_RCC_STGEN_CLKSOURCE        RCC_STGENCKSELR_STGENSRC
1102 /**
1103   * @}
1104   */
1105 
1106 #if defined(DSI)
1107 /** @defgroup RCC_LL_EC_DSI Peripheral  DSI get clock source
1108   * @{
1109   */
1110 #define LL_RCC_DSI_CLKSOURCE          RCC_DSICKSELR_DSISRC
1111 /**
1112   * @}
1113   */
1114 #endif /*DSI*/
1115 
1116 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
1117   * @{
1118   */
1119 #define LL_RCC_ADC_CLKSOURCE          RCC_ADCCKSELR_ADCSRC
1120 /**
1121   * @}
1122   */
1123 
1124 /** @defgroup RCC_LL_EC_LPTIMx Peripheral LPTIM get clock source
1125   * @{
1126   */
1127 #define LL_RCC_LPTIM1_CLKSOURCE       LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, 0x00000000U)
1128 #define LL_RCC_LPTIM23_CLKSOURCE      LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, 0x00000000U)
1129 #define LL_RCC_LPTIM45_CLKSOURCE      LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, 0x00000000U)
1130 /**
1131   * @}
1132   */
1133 
1134 /** @defgroup RCC_LL_EC_TIMGx_Prescaler TIMG get prescaler selection
1135   * @{
1136   */
1137 #define LL_RCC_TIMG1PRES              LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, 0x00000000U)
1138 #define LL_RCC_TIMG2PRES              LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, 0x00000000U)
1139 /**
1140   * @}
1141   */
1142 
1143 /** @defgroup RCC_LL_EC_PLL12SOURCE  PLL1 and PLL2 entry clock source
1144   * @{
1145   */
1146 #define LL_RCC_PLL12SOURCE_HSI        0U                        /*!< HSI clock selected as PLL12 entry clock source */
1147 #define LL_RCC_PLL12SOURCE_HSE        RCC_RCK12SELR_PLL12SRC_0  /*!< HSE clock selected as PLL12 entry clock source */
1148 #define LL_RCC_PLL12SOURCE_NONE       RCC_RCK12SELR_PLL12SRC_1  /*!< No clock */
1149 /**
1150   * @}
1151   */
1152 
1153 /** @defgroup RCC_LL_EC_PLL3SOURCE  PLL3 entry clock source
1154   * @{
1155   */
1156 #define LL_RCC_PLL3SOURCE_HSI         0U                                                 /*!< HSI clock selected as PLL3 entry clock source */
1157 #define LL_RCC_PLL3SOURCE_HSE         RCC_RCK3SELR_PLL3SRC_0                             /*!< HSE clock selected as PLL3 entry clock source */
1158 #define LL_RCC_PLL3SOURCE_CSI         RCC_RCK3SELR_PLL3SRC_1                             /*!< CSI clock selected as PLL3 entry clock source */
1159 #define LL_RCC_PLL3SOURCE_NONE        (RCC_RCK3SELR_PLL3SRC_1 | RCC_RCK3SELR_PLL3SRC_0)  /*!< No clock */
1160 /**
1161   * @}
1162   */
1163 
1164 /** @defgroup RCC_LL_EC_PLL4SOURCE  PLL4 entry clock source
1165   * @{
1166   */
1167 #define LL_RCC_PLL4SOURCE_HSI         0U                                                 /*!< HSI clock selected as PLL4 entry clock source */
1168 #define LL_RCC_PLL4SOURCE_HSE         RCC_RCK4SELR_PLL4SRC_0                             /*!< HSE clock selected as PLL4 entry clock source */
1169 #define LL_RCC_PLL4SOURCE_CSI         RCC_RCK4SELR_PLL4SRC_1                             /*!< CSI clock selected as PLL4 entry clock source */
1170 #define LL_RCC_PLL4SOURCE_I2SCKIN     (RCC_RCK4SELR_PLL4SRC_1 | RCC_RCK4SELR_PLL4SRC_0)  /*!< Signal I2S_CKIN selected as PLL4 entry clock source */
1171 /**
1172   * @}
1173   */
1174 
1175 /** @defgroup RCC_LL_PLL3_IF_Range RCC PLL3 Input Frequency Range
1176   * @{
1177   */
1178 #define LL_RCC_PLL3IFRANGE_0          RCC_PLL3CFGR1_IFRGE_0 /*!< The PLL3 input (ref3_ck) clock range frequency
1179                                                                  is between 4 and 8 MHz (default after reset) */
1180 #define LL_RCC_PLL3IFRANGE_1          RCC_PLL3CFGR1_IFRGE_1 /*!< The PLL3 input (ref3_ck) clock range frequency
1181                                                                  is between 8 and 16 MHz */
1182 /**
1183   * @}
1184   */
1185 
1186 /** @defgroup RCC_LL_PLL4_IF_Range RCC PLL4 Input Frequency Range
1187   * @{
1188   */
1189 #define LL_RCC_PLL4IFRANGE_0          RCC_PLL4CFGR1_IFRGE_0 /*!< The PLL4 input (ref4_ck) clock range frequency
1190                                                                  is between 4 and 8 MHz (default after reset) */
1191 #define LL_RCC_PLL4IFRANGE_1          RCC_PLL4CFGR1_IFRGE_1 /*!< The PLL4 input (ref4_ck) clock range frequency
1192                                                                  is between 8 and 16 MHz */
1193 /**
1194   * @}
1195   */
1196 
1197 /** @defgroup RCC_LL_EC_PLL1_SSCG_MODE  PLL1 Spread Spectrum Mode
1198   * @{
1199   */
1200 #define LL_RCC_PLL1SSCG_CENTER_SPREAD          0x00000000U            /*!< Center-spread modulation selected (default after reset) */
1201 #define LL_RCC_PLL1SSCG_DOWN_SPREAD            RCC_PLL1CSGR_SSCG_MODE /*!< Down-spread modulation selected */
1202 /**
1203   * @}
1204   */
1205 
1206 /** @defgroup RCC_LL_EC_PLL1_RPDFN_DIS  Dithering RPDF PLL1 noise control
1207   * @{
1208   */
1209 #define LL_RCC_PLL1RPDFN_DIS_ENABLED           0x00000000U            /*!< Dithering noise injection enabled (default after reset) */
1210 #define LL_RCC_PLL1RPDFN_DIS_DISABLED          RCC_PLL1CSGR_RPDFN_DIS /*!< Dithering noise injection disabled */
1211 /**
1212   * @}
1213   */
1214 
1215 /** @defgroup RCC_LL_EC_PLL1_TPDFN_DIS  Dithering TPDFN PLL1 noise control
1216   * @{
1217   */
1218 #define LL_RCC_PLL1TPDFN_DIS_ENABLED           0x00000000U            /*!< Dithering noise injection enabled (default after reset) */
1219 #define LL_RCC_PLL1TPDFN_DIS_DISABLED          RCC_PLL1CSGR_TPDFN_DIS /*!< Dithering noise injection disabled */
1220 /**
1221   * @}
1222   */
1223 
1224 /** @defgroup RCC_LL_EC_PLL2_SSCG_MODE  PLL2 Spread Spectrum Mode
1225   * @{
1226   */
1227 #define LL_RCC_PLL2SSCG_CENTER_SPREAD          0x00000000U            /*!< Center-spread modulation selected (default after reset) */
1228 #define LL_RCC_PLL2SSCG_DOWN_SPREAD            RCC_PLL2CSGR_SSCG_MODE /*!< Down-spread modulation selected */
1229 /**
1230   * @}
1231   */
1232 
1233 /** @defgroup RCC_LL_EC_PLL2_RPDFN_DIS  Dithering RPDF PLL2 noise control
1234   * @{
1235   */
1236 #define LL_RCC_PLL2RPDFN_DIS_ENABLED           0x00000000U            /*!< Dithering noise injection enabled (default after reset) */
1237 #define LL_RCC_PLL2RPDFN_DIS_DISABLED          RCC_PLL2CSGR_RPDFN_DIS /*!< Dithering noise injection disabled */
1238 /**
1239   * @}
1240   */
1241 
1242 /** @defgroup RCC_LL_EC_PLL2_TPDFN_DIS  Dithering TPDFN PLL2 noise control
1243   * @{
1244   */
1245 #define LL_RCC_PLL2TPDFN_DIS_ENABLED           0x00000000U            /*!< Dithering noise injection enabled (default after reset) */
1246 #define LL_RCC_PLL2TPDFN_DIS_DISABLED          RCC_PLL2CSGR_TPDFN_DIS /*!< Dithering noise injection disabled */
1247 /**
1248   * @}
1249   */
1250 
1251 /** @defgroup RCC_LL_EC_PLL3_SSCG_MODE  PLL3 Spread Spectrum Mode
1252   * @{
1253   */
1254 #define LL_RCC_PLL3SSCG_CENTER_SPREAD          0x00000000U            /*!< Center-spread modulation selected (default after reset) */
1255 #define LL_RCC_PLL3SSCG_DOWN_SPREAD            RCC_PLL3CSGR_SSCG_MODE /*!< Down-spread modulation selected */
1256 /**
1257   * @}
1258   */
1259 
1260 /** @defgroup RCC_LL_EC_PLL3_RPDFN_DIS  Dithering RPDF PLL3 noise control
1261   * @{
1262   */
1263 #define LL_RCC_PLL3RPDFN_DIS_ENABLED           0x00000000U            /*!< Dithering noise injection enabled (default after reset) */
1264 #define LL_RCC_PLL3RPDFN_DIS_DISABLED          RCC_PLL3CSGR_RPDFN_DIS /*!< Dithering noise injection disabled */
1265 /**
1266   * @}
1267   */
1268 
1269 /** @defgroup RCC_LL_EC_PLL3_TPDFN_DIS  Dithering TPDFN PLL3 noise control
1270   * @{
1271   */
1272 #define LL_RCC_PLL3TPDFN_DIS_ENABLED           0x00000000U            /*!< Dithering noise injection enabled (default after reset) */
1273 #define LL_RCC_PLL3TPDFN_DIS_DISABLED          RCC_PLL3CSGR_TPDFN_DIS /*!< Dithering noise injection disabled */
1274 /**
1275   * @}
1276   */
1277 
1278 /** @defgroup RCC_LL_EC_PLL4_SSCG_MODE  PLL4 Spread Spectrum Mode
1279   * @{
1280   */
1281 #define LL_RCC_PLL4SSCG_CENTER_SPREAD          0x00000000U            /*!< Center-spread modulation selected (default after reset) */
1282 #define LL_RCC_PLL4SSCG_DOWN_SPREAD            RCC_PLL4CSGR_SSCG_MODE /*!< Down-spread modulation selected */
1283 /**
1284   * @}
1285   */
1286 
1287 /** @defgroup RCC_LL_EC_PLL4_RPDFN_DIS  Dithering RPDF PLL4 noise control
1288   * @{
1289   */
1290 #define LL_RCC_PLL4RPDFN_DIS_ENABLED           0x00000000U            /*!< Dithering noise injection enabled (default after reset) */
1291 #define LL_RCC_PLL4RPDFN_DIS_DISABLED          RCC_PLL4CSGR_RPDFN_DIS /*!< Dithering noise injection disabled */
1292 /**
1293   * @}
1294   */
1295 
1296 /** @defgroup RCC_LL_EC_PLL4_TPDFN_DIS  Dithering TPDFN PLL4 noise control
1297   * @{
1298   */
1299 #define LL_RCC_PLL4TPDFN_DIS_ENABLED           0x00000000U            /*!< Dithering noise injection enabled (default after reset) */
1300 #define LL_RCC_PLL4TPDFN_DIS_DISABLED          RCC_PLL4CSGR_TPDFN_DIS /*!< Dithering noise injection disabled */
1301 /**
1302   * @}
1303   */
1304 
1305 /**
1306   * @}
1307   */
1308 
1309 /* Exported macro ------------------------------------------------------------*/
1310 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1311   * @{
1312   */
1313 
1314 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1315   * @{
1316   */
1317 
1318 /**
1319   * @brief  Write a value in RCC register
1320   * @param  __REG__ Register to be written
1321   * @param  __VALUE__ Value to be written in the register
1322   * @retval None
1323   */
1324 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1325 
1326 /**
1327   * @brief  Read a value in RCC register
1328   * @param  __REG__ Register to be read
1329   * @retval Register value
1330   */
1331 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1332 /**
1333   * @}
1334   */
1335 
1336 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1337   * @{
1338   */
1339 
1340 /**
1341   * @brief  Helper macro to calculate the MPUDIV frequency
1342   * @param  __PLL1PINPUTCLKFREQ__ Frequency of the input of mpudiv (based on PLL1P)
1343   * @param  __MPUDIVPRESCALER__ This parameter can be one of the following values:
1344   *         @arg @ref LL_RCC_MPU_DIV_2
1345   *         @arg @ref LL_RCC_MPU_DIV_4
1346   *         @arg @ref LL_RCC_MPU_DIV_8
1347   *         @arg @ref LL_RCC_MPU_DIV_16
1348   * @retval MPUDIV clock frequency (in Hz)
1349   */
1350 #define LL_RCC_CALC_MPUDIV_FREQ(__PLL1PINPUTCLKFREQ__, __MPUDIVPRESCALER__) ((__PLL1PINPUTCLKFREQ__) >> (__MPUDIVPRESCALER__))
1351 
1352 /**
1353   * @brief  Helper macro to calculate the ACLK, HCLK5 and HCLK6 frequencies
1354   * @param  __ACLKINPUTCLKFREQ__ Frequency of the input of aclk_ck (based on HSI/HSE/PLL2P)
1355   * @param  __AXIPRESCALER__ This parameter can be one of the following values:
1356   *         @arg @ref LL_RCC_AXI_DIV_1
1357   *         @arg @ref LL_RCC_AXI_DIV_2
1358   *         @arg @ref LL_RCC_AXI_DIV_3
1359   *         @arg @ref LL_RCC_AXI_DIV_4
1360   * @retval ACLK clock frequency (in Hz)
1361   */
1362 #define LL_RCC_CALC_ACLK_FREQ(__ACLKINPUTCLKFREQ__, __AXIPRESCALER__) ((__ACLKINPUTCLKFREQ__) / ((__AXIPRESCALER__) + 1U))
1363 
1364 /**
1365   * @brief  Helper macro to calculate the PCLK4 frequency (APB4)
1366   * @param  __ACLKFREQ__ ACLK frequency
1367   * @param  __APB4PRESCALER__ This parameter can be one of the following values:
1368   *         @arg @ref LL_RCC_APB4_DIV_1
1369   *         @arg @ref LL_RCC_APB4_DIV_2
1370   *         @arg @ref LL_RCC_APB4_DIV_4
1371   *         @arg @ref LL_RCC_APB4_DIV_8
1372   *         @arg @ref LL_RCC_APB4_DIV_16
1373   * @retval PCLK4 clock frequency (in Hz)
1374   */
1375 #define LL_RCC_CALC_PCLK4_FREQ(__ACLKFREQ__, __APB4PRESCALER__) ((__ACLKFREQ__) >> (__APB4PRESCALER__))
1376 
1377 /**
1378   * @brief  Helper macro to calculate the PCLK5 frequency (APB5)
1379   * @param  __ACLKFREQ__ ACLK frequency
1380   * @param  __APB5PRESCALER__ This parameter can be one of the following values:
1381   *         @arg @ref LL_RCC_APB5_DIV_1
1382   *         @arg @ref LL_RCC_APB5_DIV_2
1383   *         @arg @ref LL_RCC_APB5_DIV_4
1384   *         @arg @ref LL_RCC_APB5_DIV_8
1385   *         @arg @ref LL_RCC_APB5_DIV_16
1386   * @retval PCLK5 clock frequency (in Hz)
1387   */
1388 #define LL_RCC_CALC_PCLK5_FREQ(__ACLKFREQ__, __APB5PRESCALER__) ((__ACLKFREQ__) >> (__APB5PRESCALER__))
1389 
1390 /**
1391   * @brief  Helper macro to calculate the MLHCLK, MCU, FCLK, HCLK4, HCLK3, HCLK2 and HCLK1 frequencies
1392   * @param  __MLHCLKINPUTCLKFREQ__ Frequency of the input of mlhclk_ck (based on HSI/HSE/CSI/PLL3P)
1393   * @param  __MCUPRESCALER__ This parameter can be one of the following values:
1394   *         @arg @ref LL_RCC_MCU_DIV_1
1395   *         @arg @ref LL_RCC_MCU_DIV_2
1396   *         @arg @ref LL_RCC_MCU_DIV_4
1397   *         @arg @ref LL_RCC_MCU_DIV_8
1398   *         @arg @ref LL_RCC_MCU_DIV_16
1399   *         @arg @ref LL_RCC_MCU_DIV_32
1400   *         @arg @ref LL_RCC_MCU_DIV_64
1401   *         @arg @ref LL_RCC_MCU_DIV_128
1402   *         @arg @ref LL_RCC_MCU_DIV_256
1403   *         @arg @ref LL_RCC_MCU_DIV_512
1404   * @retval MLHCLK clock frequency (in Hz)
1405   */
1406 #define LL_RCC_CALC_MLHCLK_FREQ(__MLHCLKINPUTCLKFREQ__, __MCUPRESCALER__) ((__MLHCLKINPUTCLKFREQ__) >> (__MCUPRESCALER__))
1407 
1408 /**
1409   * @brief  Helper macro to calculate the PCLK1 frequency
1410   * @param  __MLHCLKFREQ__ MLHCLK frequency
1411   * @param  __APB1PRESCALER__ This parameter can be one of the following values:
1412   *         @arg @ref LL_RCC_APB1_DIV_1
1413   *         @arg @ref LL_RCC_APB1_DIV_2
1414   *         @arg @ref LL_RCC_APB1_DIV_4
1415   *         @arg @ref LL_RCC_APB1_DIV_8
1416   *         @arg @ref LL_RCC_APB1_DIV_16
1417   * @retval PCLK1 clock frequency (in Hz)
1418   */
1419 #define LL_RCC_CALC_PCLK1_FREQ(__MLHCLKFREQ__, __APB1PRESCALER__) ((__MLHCLKFREQ__) >> (__APB1PRESCALER__))
1420 
1421 /**
1422   * @brief  Helper macro to calculate the PCLK2 frequency
1423   * @param  __MLHCLKFREQ__ MLHCLK frequency
1424   * @param  __APB2PRESCALER__ This parameter can be one of the following values:
1425   *         @arg @ref LL_RCC_APB2_DIV_1
1426   *         @arg @ref LL_RCC_APB2_DIV_2
1427   *         @arg @ref LL_RCC_APB2_DIV_4
1428   *         @arg @ref LL_RCC_APB2_DIV_8
1429   *         @arg @ref LL_RCC_APB2_DIV_16
1430   * @retval PCLK2 clock frequency (in Hz)
1431   */
1432 #define LL_RCC_CALC_PCLK2_FREQ(__MLHCLKFREQ__, __APB2PRESCALER__) ((__MLHCLKFREQ__) >> (__APB2PRESCALER__))
1433 
1434 /**
1435   * @brief  Helper macro to calculate the PCLK3 frequency
1436   * @param  __MLHCLKFREQ__ MLHCLK frequency
1437   * @param  __APB3PRESCALER__ This parameter can be one of the following values:
1438   *         @arg @ref LL_RCC_APB3_DIV_1
1439   *         @arg @ref LL_RCC_APB3_DIV_2
1440   *         @arg @ref LL_RCC_APB3_DIV_4
1441   *         @arg @ref LL_RCC_APB3_DIV_8
1442   *         @arg @ref LL_RCC_APB3_DIV_16
1443   * @retval PCLK3 clock frequency (in Hz)
1444   */
1445 #define LL_RCC_CALC_PCLK3_FREQ(__MLHCLKFREQ__, __APB3PRESCALER__) ((__MLHCLKFREQ__) >> (__APB3PRESCALER__))
1446 
1447 /**
1448   * @}
1449   */
1450 
1451 /**
1452   * @}
1453   */
1454 
1455 /* Exported functions --------------------------------------------------------*/
1456 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1457   * @{
1458   */
1459 
1460 /** @defgroup RCC_LL_EF_HSE HSE
1461   * @{
1462   */
1463 
1464 /**
1465   * @brief  Enable the Clock Security System.
1466   * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
1467   *       a reset occurs or system enter in standby mode.
1468   * @rmtoll OCENSETR       HSECSSON         LL_RCC_HSE_EnableCSS
1469   * @retval None
1470   */
LL_RCC_HSE_EnableCSS(void)1471 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1472 {
1473   SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSECSSON);
1474 }
1475 
1476 
1477 /**
1478   * @brief  Enable HSE external digital oscillator (HSE Digital Bypass)
1479   * @rmtoll OCENSETR     DIGBYP       LL_RCC_HSE_EnableDigBypass
1480   * @retval None
1481   */
LL_RCC_HSE_EnableDigBypass(void)1482 __STATIC_INLINE void LL_RCC_HSE_EnableDigBypass(void)
1483 {
1484   WRITE_REG(RCC->OCENSETR, RCC_OCENSETR_DIGBYP);
1485   WRITE_REG(RCC->OCENSETR, RCC_OCENSETR_HSEBYP);
1486 }
1487 
1488 /**
1489   * @brief  Disable HSE external digital oscillator (HSE Digital Bypass)
1490   * @rmtoll OCENCLRR     DIGBYP       LL_RCC_HSE_DisableDigBypass
1491   * @retval None
1492   */
LL_RCC_HSE_DisableDigBypass(void)1493 __STATIC_INLINE void LL_RCC_HSE_DisableDigBypass(void)
1494 {
1495   WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_DIGBYP);
1496   WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEBYP);
1497 }
1498 
1499 /**
1500   * @brief  Enable HSE external oscillator (HSE Bypass)
1501   * @rmtoll OCENSETR     HSEBYP        LL_RCC_HSE_EnableBypass
1502   * @retval None
1503   */
LL_RCC_HSE_EnableBypass(void)1504 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1505 {
1506   WRITE_REG(RCC->OCENSETR, RCC_OCENSETR_HSEBYP);
1507 }
1508 
1509 /**
1510   * @brief  Disable HSE external oscillator (HSE Bypass)
1511   * @rmtoll OCENCLRR     HSEBYP        LL_RCC_HSE_DisableBypass
1512   * @retval None
1513   */
LL_RCC_HSE_DisableBypass(void)1514 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1515 {
1516   WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEBYP);
1517 }
1518 
1519 /**
1520   * @brief  Enable HSE crystal oscillator (HSE ON)
1521   * @rmtoll OCENCLRR      HSEON         LL_RCC_HSE_Enable
1522   * @retval None
1523   */
LL_RCC_HSE_Enable(void)1524 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1525 {
1526   WRITE_REG(RCC->OCENSETR, RCC_OCENSETR_HSEON);
1527 }
1528 
1529 /**
1530   * @brief  Disable HSE crystal oscillator (HSE ON)
1531   * @rmtoll OCENCLRR           HSEON         LL_RCC_HSE_Disable
1532   * @retval None
1533   */
LL_RCC_HSE_Disable(void)1534 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1535 {
1536   WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEON);
1537 }
1538 
1539 /**
1540   * @brief  Check if HSE oscillator is Ready
1541   * @rmtoll OCRDYR           HSERDY        LL_RCC_HSE_IsReady
1542   * @retval State of bit (1 or 0).
1543   */
LL_RCC_HSE_IsReady(void)1544 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1545 {
1546   return ((READ_BIT(RCC->OCRDYR, RCC_OCRDYR_HSERDY) == RCC_OCRDYR_HSERDY) ? 1UL : 0UL);
1547 }
1548 
1549 /**
1550   * @}
1551   */
1552 
1553 /** @defgroup RCC_LL_EF_HSI HSI
1554   * @{
1555   */
1556 
1557 /**
1558   * @brief  Enable HSI even in stop mode
1559   * @note HSI oscillator is forced ON even in Stop mode
1560   * @rmtoll OCENSETR     HSIKERON      LL_RCC_HSI_EnableInStopMode
1561   * @retval None
1562   */
LL_RCC_HSI_EnableInStopMode(void)1563 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1564 {
1565   WRITE_REG(RCC->OCENSETR, RCC_OCENSETR_HSIKERON);
1566 }
1567 
1568 /**
1569   * @brief  Disable HSI in stop mode
1570   * @rmtoll OCENCLRR     HSIKERON      LL_RCC_HSI_DisableInStopMode
1571   * @retval None
1572   */
LL_RCC_HSI_DisableInStopMode(void)1573 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1574 {
1575   WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSIKERON);
1576 }
1577 
1578 /**
1579   * @brief  Enable HSI oscillator
1580   * @rmtoll OCENSETR     HSION         LL_RCC_HSI_Enable
1581   * @retval None
1582   */
LL_RCC_HSI_Enable(void)1583 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1584 {
1585   WRITE_REG(RCC->OCENSETR, RCC_OCENSETR_HSION);
1586 }
1587 
1588 /**
1589   * @brief  Disable HSI oscillator
1590   * @rmtoll OCENCLRR     HSION         LL_RCC_HSI_Disable
1591   * @retval None
1592   */
LL_RCC_HSI_Disable(void)1593 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1594 {
1595   WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSION);
1596 }
1597 
1598 /**
1599   * @brief  Check if HSI clock is ready
1600   * @rmtoll OCRDYR       HSIRDY        LL_RCC_HSI_IsReady
1601   * @retval State of bit (1 or 0).
1602   */
LL_RCC_HSI_IsReady(void)1603 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1604 {
1605   return ((READ_BIT(RCC->OCRDYR, RCC_OCRDYR_HSIRDY) == RCC_OCRDYR_HSIRDY) ? 1UL : 0UL);
1606 }
1607 
1608 /**
1609   * @brief  Get HSI Calibration value
1610   * @note When HSITRIM is written, HSICAL is updated with the sum of
1611   *       HSITRIM and the factory trim value
1612   * @rmtoll HSICFGR        HSICAL        LL_RCC_HSI_GetCalibration
1613   * @retval Between Min_Data = 0x00 and Max_Data = 0xFFF
1614   */
LL_RCC_HSI_GetCalibration(void)1615 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1616 {
1617   return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
1618 }
1619 
1620 /**
1621   * @brief  Set HSI Calibration trimming
1622   * @note user-programmable trimming value that is added to the HSICAL
1623   * @note Default value is 0
1624   * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
1625   * @param  Value Between Min_Data = 0x0 and Max_Data = 0x7F
1626   * @retval None
1627   */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1628 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1629 {
1630   MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1631 }
1632 
1633 /**
1634   * @brief  Get HSI Calibration trimming
1635   * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
1636   * @retval Between Min_Data = 0 and Max_Data = 0x7F
1637   */
LL_RCC_HSI_GetCalibTrimming(void)1638 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1639 {
1640   return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1641 }
1642 
1643 /**
1644   * @brief  Set HSI divider
1645   * @rmtoll HSICFGR        HSIDIV       LL_RCC_HSI_SetDivider
1646   * @param  Divider This parameter can be one of the following values:
1647   *         @arg @ref LL_RCC_HSI_DIV_1
1648   *         @arg @ref LL_RCC_HSI_DIV_2
1649   *         @arg @ref LL_RCC_HSI_DIV_4
1650   *         @arg @ref LL_RCC_HSI_DIV_8
1651   * @retval None
1652   */
LL_RCC_HSI_SetDivider(uint32_t Divider)1653 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
1654 {
1655   MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSIDIV, Divider);
1656 }
1657 
1658 /**
1659   * @brief  Get HSI divider
1660   * @rmtoll HSICFGR        HSIDIV       LL_RCC_HSI_GetDivider
1661   * @retval It can be one of the following values:
1662   *         @arg @ref LL_RCC_HSI_DIV_1
1663   *         @arg @ref LL_RCC_HSI_DIV_2
1664   *         @arg @ref LL_RCC_HSI_DIV_4
1665   *         @arg @ref LL_RCC_HSI_DIV_8
1666   */
LL_RCC_HSI_GetDivider(void)1667 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
1668 {
1669   return (READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSIDIV));
1670 }
1671 
1672 /**
1673   * @brief  Check if HSI division is Ready
1674   * @rmtoll OCRDYR           HSIDIVRDY        LL_RCC_HSI_IsDividerReady
1675   * @retval State of bit (1 or 0).
1676   */
LL_RCC_HSI_IsDividerReady(void)1677 __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
1678 {
1679   return ((READ_BIT(RCC->OCRDYR, RCC_OCRDYR_HSIDIVRDY) == RCC_OCRDYR_HSIDIVRDY) ? 1UL : 0UL);
1680 }
1681 
1682 /**
1683   * @}
1684   */
1685 
1686 /** @defgroup RCC_LL_EF_CSI CSI
1687   * @{
1688   */
1689 
1690 /**
1691   * @brief  Enable CSI oscillator
1692   * @rmtoll OCENSETR           CSION         LL_RCC_CSI_Enable
1693   * @retval None
1694   */
LL_RCC_CSI_Enable(void)1695 __STATIC_INLINE void LL_RCC_CSI_Enable(void)
1696 {
1697   WRITE_REG(RCC->OCENSETR, RCC_OCENSETR_CSION);
1698 }
1699 
1700 /**
1701   * @brief  Disable CSI oscillator
1702   * @rmtoll OCENCLRR           CSION         LL_RCC_CSI_Disable
1703   * @retval None
1704   */
LL_RCC_CSI_Disable(void)1705 __STATIC_INLINE void LL_RCC_CSI_Disable(void)
1706 {
1707   WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_CSION);
1708 }
1709 
1710 /**
1711   * @brief  Check if CSI clock is ready
1712   * @rmtoll OCRDYR           CSIRDY        LL_RCC_CSI_IsReady
1713   * @retval State of bit (1 or 0).
1714   */
LL_RCC_CSI_IsReady(void)1715 __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
1716 {
1717   return ((READ_BIT(RCC->OCRDYR, RCC_OCRDYR_CSIRDY) == RCC_OCRDYR_CSIRDY) ? 1UL : 0UL);
1718 }
1719 
1720 /**
1721   * @brief  Enable CSI oscillator in Stop mode
1722   * @rmtoll OCENSETR           CSIKERON         LL_RCC_CSI_EnableInStopMode
1723   * @retval None
1724   */
LL_RCC_CSI_EnableInStopMode(void)1725 __STATIC_INLINE void LL_RCC_CSI_EnableInStopMode(void)
1726 {
1727   WRITE_REG(RCC->OCENSETR, RCC_OCENSETR_CSIKERON);
1728 }
1729 
1730 /**
1731   * @brief  Disable CSI oscillator in Stop mode
1732   * @rmtoll OCENCLRR           CSIKERON         LL_RCC_CSI_DisableInStopMode
1733   * @retval None
1734   */
LL_RCC_CSI_DisableInStopMode(void)1735 __STATIC_INLINE void LL_RCC_CSI_DisableInStopMode(void)
1736 {
1737   WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_CSIKERON);
1738 }
1739 
1740 /**
1741   * @brief  Get CSI Calibration value
1742   * @note When CSITRIM is written, CSICAL is updated with the sum of
1743   *       CSITRIM and the factory trim value
1744   * @rmtoll CSICFGR        CSICAL        LL_RCC_CSI_GetCalibration
1745   * @retval A value between 0 and 255 (0xFF)
1746   */
LL_RCC_CSI_GetCalibration(void)1747 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
1748 {
1749   return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
1750 }
1751 
1752 /**
1753   * @brief  Set CSI Calibration trimming
1754   * @note user-programmable trimming value that is added to the CSICAL
1755   * @note Default value is 16 (0x10) which, when added to the CSICAL value,
1756   *       should trim the CSI to 4 MHz
1757   * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_SetCalibTrimming
1758   * @param  Value can be a value between 0 and 31
1759   * @retval None
1760   */
LL_RCC_CSI_SetCalibTrimming(uint32_t Value)1761 __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
1762 {
1763   MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
1764 }
1765 
1766 /**
1767   * @brief  Get CSI Calibration trimming
1768   * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_GetCalibTrimming
1769   * @retval A value between 0 and 31
1770   */
LL_RCC_CSI_GetCalibTrimming(void)1771 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
1772 {
1773   return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1774 
1775 }
1776 
1777 /**
1778   * @}
1779   */
1780 
1781 /** @defgroup RCC_LL_EF_LSE LSE
1782   * @{
1783   */
1784 
1785 /**
1786   * @brief  Enable  Low Speed External (LSE) crystal.
1787   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
1788   * @retval None
1789   */
LL_RCC_LSE_Enable(void)1790 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1791 {
1792   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1793 }
1794 
1795 /**
1796   * @brief  Disable  Low Speed External (LSE) crystal.
1797   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
1798   * @retval None
1799   */
LL_RCC_LSE_Disable(void)1800 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1801 {
1802   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1803 }
1804 
1805 /**
1806   * @brief  Enable external clock source (LSE bypass).
1807   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
1808   * @retval None
1809   */
LL_RCC_LSE_EnableBypass(void)1810 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1811 {
1812   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1813 }
1814 
1815 /**
1816   * @brief  Disable external clock source (LSE bypass).
1817   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
1818   * @retval None
1819   */
LL_RCC_LSE_DisableBypass(void)1820 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1821 {
1822   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1823 }
1824 
1825 /**
1826   * @brief  Enable external digital clock source (LSE Digital Bypass).
1827   * @rmtoll BDCR         DIGBYP, LSEBYP    LL_RCC_LSE_EnableDigBypass
1828   * @retval None
1829   */
LL_RCC_LSE_EnableDigBypass(void)1830 __STATIC_INLINE void LL_RCC_LSE_EnableDigBypass(void)
1831 {
1832   SET_BIT(RCC->BDCR, RCC_BDCR_DIGBYP);
1833   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1834 }
1835 
1836 /**
1837   * @brief  Disable external digital clock source (LSE Digital Bypass).
1838   * @rmtoll BDCR         DIGBYP, LSEBYP     LL_RCC_LSE_DisableDigBypass
1839   * @retval None
1840   */
LL_RCC_LSE_DisableDigBypass(void)1841 __STATIC_INLINE void LL_RCC_LSE_DisableDigBypass(void)
1842 {
1843   CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEBYP | RCC_BDCR_DIGBYP));
1844 }
1845 
1846 /**
1847   * @brief  Set LSE oscillator drive capability
1848   * @note The oscillator is in Xtal mode when it is not in bypass mode.
1849   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
1850   * @param  LSEDrive This parameter can be one of the following values:
1851   *         @arg @ref LL_RCC_LSEDRIVE_LOW
1852   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1853   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1854   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
1855   * @retval None
1856   */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1857 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1858 {
1859   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1860 }
1861 
1862 /**
1863   * @brief  Get LSE oscillator drive capability
1864   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
1865   * @retval Returned value can be one of the following values:
1866   *         @arg @ref LL_RCC_LSEDRIVE_LOW
1867   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1868   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1869   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
1870   */
LL_RCC_LSE_GetDriveCapability(void)1871 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1872 {
1873   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1874 }
1875 
1876 /**
1877   * @brief  Enable Clock security system on LSE.
1878   * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_EnableCSS
1879   * @retval None
1880   */
LL_RCC_LSE_EnableCSS(void)1881 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1882 {
1883   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1884 }
1885 
1886 /**
1887   * @brief  Disable Clock security system on LSE.
1888   * @note Clock security system can be disabled only after a LSE
1889   *       failure detection. In that case it MUST be disabled by software.
1890   * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_DisableCSS
1891   * @retval None
1892   */
LL_RCC_LSE_DisableCSS(void)1893 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1894 {
1895   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1896 }
1897 
1898 /**
1899   * @brief  Check if LSE oscillator Ready
1900   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
1901   * @retval State of bit (1 or 0).
1902   */
LL_RCC_LSE_IsReady(void)1903 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1904 {
1905   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
1906 }
1907 
1908 /**
1909   * @brief  Check if CSS on LSE failure Detection
1910   * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsCSSDetected
1911   * @retval State of bit (1 or 0).
1912   */
LL_RCC_LSE_IsCSSDetected(void)1913 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1914 {
1915   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL);
1916 }
1917 
1918 /**
1919   * @}
1920   */
1921 
1922 /** @defgroup RCC_LL_EF_LSI LSI
1923   * @{
1924   */
1925 
1926 /**
1927   * @brief  Enable LSI Oscillator
1928   * @rmtoll RDLSICR          LSION         LL_RCC_LSI_Enable
1929   * @retval None
1930   */
LL_RCC_LSI_Enable(void)1931 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1932 {
1933   SET_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION);
1934 }
1935 
1936 /**
1937   * @brief  Disable LSI Oscillator
1938   * @rmtoll RDLSICR          LSION         LL_RCC_LSI_Disable
1939   * @retval None
1940   */
LL_RCC_LSI_Disable(void)1941 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1942 {
1943   CLEAR_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION);
1944 }
1945 
1946 /**
1947   * @brief  Check if LSI is Ready
1948   * @rmtoll RDLSICR          LSIRDY        LL_RCC_LSI_IsReady
1949   * @retval State of bit (1 or 0).
1950   */
LL_RCC_LSI_IsReady(void)1951 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1952 {
1953   return ((READ_BIT(RCC->RDLSICR, RCC_RDLSICR_LSIRDY) == RCC_RDLSICR_LSIRDY) ? 1UL : 0UL);
1954 }
1955 
1956 /**
1957   * @}
1958   */
1959 
1960 /** @defgroup RCC_LL_EF_System System
1961   * @{
1962   */
1963 
1964 /**
1965   * @brief  Configure the mpu clock source
1966   * @rmtoll MPCKSELR         MPUSRC            LL_RCC_SetMPUClkSource
1967   * @param  Source This parameter can be one of the following values:
1968   *         @arg @ref LL_RCC_MPU_CLKSOURCE_HSI
1969   *         @arg @ref LL_RCC_MPU_CLKSOURCE_HSE
1970   *         @arg @ref LL_RCC_MPU_CLKSOURCE_PLL1
1971   *         @arg @ref LL_RCC_MPU_CLKSOURCE_MPUDIV
1972   * @retval None
1973   */
LL_RCC_SetMPUClkSource(uint32_t Source)1974 __STATIC_INLINE void LL_RCC_SetMPUClkSource(uint32_t Source)
1975 {
1976   MODIFY_REG(RCC->MPCKSELR, RCC_MPCKSELR_MPUSRC, Source);
1977 }
1978 
1979 /**
1980   * @brief  Get the mpu clock source
1981   * @rmtoll MPCKSELR         MPUSRC           LL_RCC_GetMPUClkSource
1982   * @retval Returned value can be one of the following values:
1983   *         @arg @ref LL_RCC_MPU_CLKSOURCE_HSI
1984   *         @arg @ref LL_RCC_MPU_CLKSOURCE_HSE
1985   *         @arg @ref LL_RCC_MPU_CLKSOURCE_PLL1
1986   *         @arg @ref LL_RCC_MPU_CLKSOURCE_MPUDIV
1987   */
LL_RCC_GetMPUClkSource(void)1988 __STATIC_INLINE uint32_t LL_RCC_GetMPUClkSource(void)
1989 {
1990   return (uint32_t)(READ_BIT(RCC->MPCKSELR, RCC_MPCKSELR_MPUSRC));
1991 }
1992 
1993 /**
1994   * @brief  Configure the axiss clock source
1995   * @rmtoll ASSCKSELR         AXISSRC            LL_RCC_SetAXISSClkSource
1996   * @param  Source This parameter can be one of the following values:
1997   *         @arg @ref LL_RCC_AXISS_CLKSOURCE_HSI
1998   *         @arg @ref LL_RCC_AXISS_CLKSOURCE_HSE
1999   *         @arg @ref LL_RCC_AXISS_CLKSOURCE_PLL2
2000   *         @arg @ref LL_RCC_AXISS_CLKSOURCE_OFF
2001   * @retval None
2002   */
LL_RCC_SetAXISSClkSource(uint32_t Source)2003 __STATIC_INLINE void LL_RCC_SetAXISSClkSource(uint32_t Source)
2004 {
2005   MODIFY_REG(RCC->ASSCKSELR, RCC_ASSCKSELR_AXISSRC, Source);
2006 }
2007 
2008 /**
2009   * @brief  Get the axiss clock source
2010   * @rmtoll ASSCKSELR         AXISSRC           LL_RCC_GetAXISSClkSource
2011   * @retval Returned value can be one of the following values:
2012   *         @arg @ref LL_RCC_AXISS_CLKSOURCE_HSI
2013   *         @arg @ref LL_RCC_AXISS_CLKSOURCE_HSE
2014   *         @arg @ref LL_RCC_AXISS_CLKSOURCE_PLL2
2015   *         @arg @ref LL_RCC_AXISS_CLKSOURCE_OFF
2016   */
LL_RCC_GetAXISSClkSource(void)2017 __STATIC_INLINE uint32_t LL_RCC_GetAXISSClkSource(void)
2018 {
2019   return (uint32_t)(READ_BIT(RCC->ASSCKSELR, RCC_ASSCKSELR_AXISSRC));
2020 }
2021 
2022 /**
2023   * @brief  Configure the mcuss clock source
2024   * @rmtoll MSSCKSELR         MCUSSRC            LL_RCC_SetMCUClkSource
2025   * @param  Source This parameter can be one of the following values:
2026   *         @arg @ref LL_RCC_MCUSS_CLKSOURCE_HSI
2027   *         @arg @ref LL_RCC_MCUSS_CLKSOURCE_HSE
2028   *         @arg @ref LL_RCC_MCUSS_CLKSOURCE_CSI
2029   *         @arg @ref LL_RCC_MCUSS_CLKSOURCE_PLL3
2030   * @retval None
2031   */
LL_RCC_SetMCUSSClkSource(uint32_t Source)2032 __STATIC_INLINE void LL_RCC_SetMCUSSClkSource(uint32_t Source)
2033 {
2034   MODIFY_REG(RCC->MSSCKSELR, RCC_MSSCKSELR_MCUSSRC, Source);
2035 }
2036 
2037 /**
2038   * @brief  Get the mcuss clock source
2039   * @rmtoll MSSCKSELR         MCUSSRC           LL_RCC_GetMCUClkSource
2040   * @retval Returned value can be one of the following values:
2041   *         @arg @ref LL_RCC_MCUSS_CLKSOURCE_HSI
2042   *         @arg @ref LL_RCC_MCUSS_CLKSOURCE_HSE
2043   *         @arg @ref LL_RCC_MCUSS_CLKSOURCE_CSI
2044   *         @arg @ref LL_RCC_MCUSS_CLKSOURCE_PLL3
2045   */
LL_RCC_GetMCUSSClkSource(void)2046 __STATIC_INLINE uint32_t LL_RCC_GetMCUSSClkSource(void)
2047 {
2048   return (uint32_t)(READ_BIT(RCC->MSSCKSELR, RCC_MSSCKSELR_MCUSSRC));
2049 }
2050 
2051 /**
2052   * @brief  Set the MPUDIV prescaler
2053   * @rmtoll MPCKDIVR         MPUDIV            LL_RCC_SetMPUPrescaler
2054   * @param  Prescaler This parameter can be one of the following values:
2055   *         @arg @ref LL_RCC_MPU_DIV_OFF
2056   *         @arg @ref LL_RCC_MPU_DIV_2
2057   *         @arg @ref LL_RCC_MPU_DIV_4
2058   *         @arg @ref LL_RCC_MPU_DIV_8
2059   *         @arg @ref LL_RCC_MPU_DIV_16
2060   * @retval None
2061   */
LL_RCC_SetMPUPrescaler(uint32_t Prescaler)2062 __STATIC_INLINE void LL_RCC_SetMPUPrescaler(uint32_t Prescaler)
2063 {
2064   MODIFY_REG(RCC->MPCKDIVR, RCC_MPCKDIVR_MPUDIV, Prescaler);
2065 }
2066 
2067 /**
2068   * @brief  Set the ACLK (ACLK, HCLK5 and HCLK6) prescaler
2069   * @rmtoll AXIDIVR         ACLK            LL_RCC_SetACLKPrescaler
2070   * @param  Prescaler This parameter can be one of the following values:
2071   *         @arg @ref LL_RCC_AXI_DIV_1
2072   *         @arg @ref LL_RCC_AXI_DIV_2
2073   *         @arg @ref LL_RCC_AXI_DIV_3
2074   *         @arg @ref LL_RCC_AXI_DIV_4
2075   * @retval None
2076   */
LL_RCC_SetACLKPrescaler(uint32_t Prescaler)2077 __STATIC_INLINE void LL_RCC_SetACLKPrescaler(uint32_t Prescaler)
2078 {
2079   MODIFY_REG(RCC->AXIDIVR, RCC_AXIDIVR_AXIDIV, Prescaler);
2080 }
2081 
2082 /**
2083   * @brief  Set the APB4 prescaler
2084   * @rmtoll APB4DIVR         APB4            LL_RCC_SetAPB4Prescaler
2085   * @param  Prescaler This parameter can be one of the following values:
2086   *         @arg @ref LL_RCC_APB4_DIV_1
2087   *         @arg @ref LL_RCC_APB4_DIV_2
2088   *         @arg @ref LL_RCC_APB4_DIV_4
2089   *         @arg @ref LL_RCC_APB4_DIV_8
2090   *         @arg @ref LL_RCC_APB4_DIV_16
2091   * @retval None
2092   */
LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)2093 __STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
2094 {
2095   MODIFY_REG(RCC->APB4DIVR, RCC_APB4DIVR_APB4DIV, Prescaler);
2096 }
2097 
2098 /**
2099   * @brief  Set the APB5 prescaler
2100   * @rmtoll APB5DIVR         APB5            LL_RCC_SetAPB5Prescaler
2101   * @param  Prescaler This parameter can be one of the following values:
2102   *         @arg @ref LL_RCC_APB5_DIV_1
2103   *         @arg @ref LL_RCC_APB5_DIV_2
2104   *         @arg @ref LL_RCC_APB5_DIV_4
2105   *         @arg @ref LL_RCC_APB5_DIV_8
2106   *         @arg @ref LL_RCC_APB5_DIV_16
2107   * @retval None
2108   */
LL_RCC_SetAPB5Prescaler(uint32_t Prescaler)2109 __STATIC_INLINE void LL_RCC_SetAPB5Prescaler(uint32_t Prescaler)
2110 {
2111   MODIFY_REG(RCC->APB5DIVR, RCC_APB5DIVR_APB5DIV, Prescaler);
2112 }
2113 
2114 /**
2115   * @brief  Set the MLHCLK (MLHCLK, MCU, FCLK, HCLK4, HCLK3, HCLK2 and HCLK1) prescaler
2116   * @rmtoll MCUDIVR         MCUDIV            LL_RCC_SetMLHCLKPrescaler
2117   * @param  Prescaler This parameter can be one of the following values:
2118   *         @arg @ref LL_RCC_MCU_DIV_1
2119   *         @arg @ref LL_RCC_MCU_DIV_2
2120   *         @arg @ref LL_RCC_MCU_DIV_4
2121   *         @arg @ref LL_RCC_MCU_DIV_8
2122   *         @arg @ref LL_RCC_MCU_DIV_16
2123   *         @arg @ref LL_RCC_MCU_DIV_32
2124   *         @arg @ref LL_RCC_MCU_DIV_64
2125   *         @arg @ref LL_RCC_MCU_DIV_128
2126   *         @arg @ref LL_RCC_MCU_DIV_256
2127   *         @arg @ref LL_RCC_MCU_DIV_512
2128 
2129   * @retval None
2130   */
LL_RCC_SetMLHCLKPrescaler(uint32_t Prescaler)2131 __STATIC_INLINE void LL_RCC_SetMLHCLKPrescaler(uint32_t Prescaler)
2132 {
2133   MODIFY_REG(RCC->MCUDIVR, RCC_MCUDIVR_MCUDIV, Prescaler);
2134 }
2135 
2136 /**
2137   * @brief  Set the APB1 prescaler
2138   * @rmtoll APB1DIVR         APB1            LL_RCC_SetAPB1Prescaler
2139   * @param  Prescaler This parameter can be one of the following values:
2140   *         @arg @ref LL_RCC_APB1_DIV_1
2141   *         @arg @ref LL_RCC_APB1_DIV_2
2142   *         @arg @ref LL_RCC_APB1_DIV_4
2143   *         @arg @ref LL_RCC_APB1_DIV_8
2144   *         @arg @ref LL_RCC_APB1_DIV_16
2145   * @retval None
2146   */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2147 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2148 {
2149   MODIFY_REG(RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV, Prescaler);
2150 }
2151 
2152 /**
2153   * @brief  Set the APB2 prescaler
2154   * @rmtoll APB2DIVR         APB2            LL_RCC_SetAPB2Prescaler
2155   * @param  Prescaler This parameter can be one of the following values:
2156   *         @arg @ref LL_RCC_APB2_DIV_1
2157   *         @arg @ref LL_RCC_APB2_DIV_2
2158   *         @arg @ref LL_RCC_APB2_DIV_4
2159   *         @arg @ref LL_RCC_APB2_DIV_8
2160   *         @arg @ref LL_RCC_APB2_DIV_16
2161   * @retval None
2162   */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2163 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2164 {
2165   MODIFY_REG(RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV, Prescaler);
2166 }
2167 
2168 /**
2169   * @brief  Set the APB3 prescaler
2170   * @rmtoll APB3DIVR         APB3            LL_RCC_SetAPB3Prescaler
2171   * @param  Prescaler This parameter can be one of the following values:
2172   *         @arg @ref LL_RCC_APB3_DIV_1
2173   *         @arg @ref LL_RCC_APB3_DIV_2
2174   *         @arg @ref LL_RCC_APB3_DIV_4
2175   *         @arg @ref LL_RCC_APB3_DIV_8
2176   *         @arg @ref LL_RCC_APB3_DIV_16
2177   * @retval None
2178   */
LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)2179 __STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
2180 {
2181   MODIFY_REG(RCC->APB3DIVR, RCC_APB3DIVR_APB3DIV, Prescaler);
2182 }
2183 
2184 /**
2185   * @brief  Get the MPUDIV prescaler
2186   * @rmtoll MPCKDIVR         MPUDIV           LL_RCC_GetMPUPrescaler
2187   * @retval Returned value can be one of the following values:
2188   *         @arg @ref LL_RCC_MPU_DIV_OFF
2189   *         @arg @ref LL_RCC_MPU_DIV_2
2190   *         @arg @ref LL_RCC_MPU_DIV_4
2191   *         @arg @ref LL_RCC_MPU_DIV_8
2192   *         @arg @ref LL_RCC_MPU_DIV_16
2193   */
LL_RCC_GetMPUPrescaler(void)2194 __STATIC_INLINE uint32_t LL_RCC_GetMPUPrescaler(void)
2195 {
2196   return (uint32_t)(READ_BIT(RCC->MPCKDIVR, RCC_MPCKDIVR_MPUDIV));
2197 }
2198 
2199 /**
2200   * @brief  Get the ACLK (ACLK, HCLK5 and HCLK6) prescaler
2201   * @rmtoll AXIDIVR         ACLK           LL_RCC_GetACLKPrescaler
2202   * @retval Returned value can be one of the following values:
2203   *         @arg @ref LL_RCC_AXI_DIV_1
2204   *         @arg @ref LL_RCC_AXI_DIV_2
2205   *         @arg @ref LL_RCC_AXI_DIV_3
2206   *         @arg @ref LL_RCC_AXI_DIV_4
2207   */
LL_RCC_GetACLKPrescaler(void)2208 __STATIC_INLINE uint32_t LL_RCC_GetACLKPrescaler(void)
2209 {
2210   return (uint32_t)(READ_BIT(RCC->AXIDIVR, RCC_AXIDIVR_AXIDIV));
2211 }
2212 
2213 /**
2214   * @brief  Get the APB4 prescaler
2215   * @rmtoll APB4DIVR         APB4           LL_RCC_GetAPB4Prescaler
2216   * @retval Returned value can be one of the following values:
2217   *         @arg @ref LL_RCC_APB4_DIV_1
2218   *         @arg @ref LL_RCC_APB4_DIV_2
2219   *         @arg @ref LL_RCC_APB4_DIV_4
2220   *         @arg @ref LL_RCC_APB4_DIV_8
2221   *         @arg @ref LL_RCC_APB4_DIV_16
2222   */
LL_RCC_GetAPB4Prescaler(void)2223 __STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
2224 {
2225   return (uint32_t)(READ_BIT(RCC->APB4DIVR, RCC_APB4DIVR_APB4DIV));
2226 }
2227 
2228 /**
2229   * @brief  Get the APB5 prescaler
2230   * @rmtoll APB5DIVR         APB5           LL_RCC_GetAPB5Prescaler
2231   * @retval Returned value can be one of the following values:
2232   *         @arg @ref LL_RCC_APB5_DIV_1
2233   *         @arg @ref LL_RCC_APB5_DIV_2
2234   *         @arg @ref LL_RCC_APB5_DIV_4
2235   *         @arg @ref LL_RCC_APB5_DIV_8
2236   *         @arg @ref LL_RCC_APB5_DIV_16
2237   */
LL_RCC_GetAPB5Prescaler(void)2238 __STATIC_INLINE uint32_t LL_RCC_GetAPB5Prescaler(void)
2239 {
2240   return (uint32_t)(READ_BIT(RCC->APB5DIVR, RCC_APB5DIVR_APB5DIV));
2241 }
2242 
2243 /**
2244   * @brief  Get the MLHCLK (MLHCLK, MCU, FCLK, HCLK4, HCLK3, HCLK2 and HCLK1) prescaler
2245   * @rmtoll MCUDIVR         MCUDIV           LL_RCC_GetMLHCLKPrescaler
2246   * @retval Returned value can be one of the following values:
2247   *         @arg @ref LL_RCC_MCU_DIV_1
2248   *         @arg @ref LL_RCC_MCU_DIV_2
2249   *         @arg @ref LL_RCC_MCU_DIV_4
2250   *         @arg @ref LL_RCC_MCU_DIV_8
2251   *         @arg @ref LL_RCC_MCU_DIV_16
2252   *         @arg @ref LL_RCC_MCU_DIV_32
2253   *         @arg @ref LL_RCC_MCU_DIV_64
2254   *         @arg @ref LL_RCC_MCU_DIV_128
2255   *         @arg @ref LL_RCC_MCU_DIV_256
2256   *         @arg @ref LL_RCC_MCU_DIV_512
2257   */
LL_RCC_GetMLHCLKPrescaler(void)2258 __STATIC_INLINE uint32_t LL_RCC_GetMLHCLKPrescaler(void)
2259 {
2260   return (uint32_t)(READ_BIT(RCC->MCUDIVR, RCC_MCUDIVR_MCUDIV));
2261 }
2262 
2263 /**
2264   * @brief  Get the APB1 prescaler
2265   * @rmtoll APB1DIVR         APB1           LL_RCC_GetAPB1Prescaler
2266   * @retval Returned value can be one of the following values:
2267   *         @arg @ref LL_RCC_APB1_DIV_1
2268   *         @arg @ref LL_RCC_APB1_DIV_2
2269   *         @arg @ref LL_RCC_APB1_DIV_4
2270   *         @arg @ref LL_RCC_APB1_DIV_8
2271   *         @arg @ref LL_RCC_APB1_DIV_16
2272   */
LL_RCC_GetAPB1Prescaler(void)2273 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2274 {
2275   return (uint32_t)(READ_BIT(RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV));
2276 }
2277 
2278 /**
2279   * @brief  Get the APB2 prescaler
2280   * @rmtoll APB2DIVR         APB2           LL_RCC_GetAPB2Prescaler
2281   * @retval Returned value can be one of the following values:
2282   *         @arg @ref LL_RCC_APB2_DIV_1
2283   *         @arg @ref LL_RCC_APB2_DIV_2
2284   *         @arg @ref LL_RCC_APB2_DIV_4
2285   *         @arg @ref LL_RCC_APB2_DIV_8
2286   *         @arg @ref LL_RCC_APB2_DIV_16
2287   */
LL_RCC_GetAPB2Prescaler(void)2288 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2289 {
2290   return (uint32_t)(READ_BIT(RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV));
2291 }
2292 
2293 /**
2294   * @brief  Get the APB3 prescaler
2295   * @rmtoll APB3DIVR         APB3           LL_RCC_GetAPB3Prescaler
2296   * @retval Returned value can be one of the following values:
2297   *         @arg @ref LL_RCC_APB3_DIV_1
2298   *         @arg @ref LL_RCC_APB3_DIV_2
2299   *         @arg @ref LL_RCC_APB3_DIV_4
2300   *         @arg @ref LL_RCC_APB3_DIV_8
2301   *         @arg @ref LL_RCC_APB3_DIV_16
2302   */
LL_RCC_GetAPB3Prescaler(void)2303 __STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
2304 {
2305   return (uint32_t)(READ_BIT(RCC->APB3DIVR, RCC_APB3DIVR_APB3DIV));
2306 }
2307 
2308 /**
2309   * @}
2310   */
2311 
2312 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2313   * @{
2314   */
2315 
2316 /**
2317   * @brief  Configure peripheral clock source
2318   * @rmtoll I2C46CKSELR        *     LL_RCC_SetClockSource\n
2319   *         SPI6CKSELR         *     LL_RCC_SetClockSource\n
2320   *         UART1CKSELR        *     LL_RCC_SetClockSource\n
2321   *         RNG1CKSELR         *     LL_RCC_SetClockSource\n
2322   *         MCO1CFGR           *     LL_RCC_SetClockSource\n
2323   *         MCO2CFGR           *     LL_RCC_SetClockSource\n
2324   *         TIMG1PRER          *     LL_RCC_SetClockSource\n
2325   *         TIMG2PRER          *     LL_RCC_SetClockSource\n
2326   *         I2C12CKSELR        *     LL_RCC_SetClockSource\n
2327   *         I2C35CKSELR        *     LL_RCC_SetClockSource\n
2328   *         SAI1CKSELR         *     LL_RCC_SetClockSource\n
2329   *         SAI2CKSELR         *     LL_RCC_SetClockSource\n
2330   *         SAI3CKSELR         *     LL_RCC_SetClockSource\n
2331   *         SAI4CKSELR         *     LL_RCC_SetClockSource\n
2332   *         SPI2S1CKSELR       *     LL_RCC_SetClockSource\n
2333   *         SPI2S23CKSELR      *     LL_RCC_SetClockSource\n
2334   *         SPI45CKSELR        *     LL_RCC_SetClockSource\n
2335   *         UART6CKSELR        *     LL_RCC_SetClockSource\n
2336   *         UART24CKSELR       *     LL_RCC_SetClockSource\n
2337   *         UART35CKSELR       *     LL_RCC_SetClockSource\n
2338   *         UART78CKSELR       *     LL_RCC_SetClockSource\n
2339   *         SDMMC12CKSELR      *     LL_RCC_SetClockSource\n
2340   *         SDMMC3CKSELR       *     LL_RCC_SetClockSource\n
2341   *         RNG2CKSELR         *     LL_RCC_SetClockSource\n
2342   *         LPTIM45CKSELR      *     LL_RCC_SetClockSource\n
2343   *         LPTIM23CKSELR      *     LL_RCC_SetClockSource\n
2344   *         LPTIM1CKSELR       *     LL_RCC_SetClockSource
2345   * @param  ClkSource This parameter can be one of the following values:
2346   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_PCLK1
2347   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_PLL4R
2348   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_HSI
2349   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_CSI
2350   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_PCLK1
2351   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_PLL4R
2352   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_HSI
2353   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_CSI
2354   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_PCLK5
2355   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_PLL3Q
2356   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_HSI
2357   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_CSI
2358   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL4Q
2359   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3Q
2360   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2SCKIN
2361   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PER
2362   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3R
2363   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL4Q
2364   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3Q
2365   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_I2SCKIN
2366   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PER
2367   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIF
2368   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3R
2369   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL4Q
2370   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL3Q
2371   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_I2SCKIN
2372   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PER
2373   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL3R
2374   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL4Q
2375   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL3Q
2376   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_I2SCKIN
2377   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PER
2378   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL3R
2379   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL4P
2380   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3Q
2381   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_I2SCKIN
2382   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PER
2383   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3R
2384   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL4P
2385   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3Q
2386   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_I2SCKIN
2387   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PER
2388   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3R
2389   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
2390   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL4Q
2391   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
2392   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
2393   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
2394   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK5
2395   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL4Q
2396   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
2397   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
2398   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
2399   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
2400   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK5
2401   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q
2402   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2403   *         @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
2404   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PLL4Q
2405   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSE
2406   *         @arg @ref LL_RCC_UART24_CLKSOURCE_PCLK1
2407   *         @arg @ref LL_RCC_UART24_CLKSOURCE_PLL4Q
2408   *         @arg @ref LL_RCC_UART24_CLKSOURCE_HSI
2409   *         @arg @ref LL_RCC_UART24_CLKSOURCE_CSI
2410   *         @arg @ref LL_RCC_UART24_CLKSOURCE_HSE
2411   *         @arg @ref LL_RCC_UART35_CLKSOURCE_PCLK1
2412   *         @arg @ref LL_RCC_UART35_CLKSOURCE_PLL4Q
2413   *         @arg @ref LL_RCC_UART35_CLKSOURCE_HSI
2414   *         @arg @ref LL_RCC_UART35_CLKSOURCE_CSI
2415   *         @arg @ref LL_RCC_UART35_CLKSOURCE_HSE
2416   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
2417   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PLL4Q
2418   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
2419   *         @arg @ref LL_RCC_USART6_CLKSOURCE_CSI
2420   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSE
2421   *         @arg @ref LL_RCC_UART78_CLKSOURCE_PCLK1
2422   *         @arg @ref LL_RCC_UART78_CLKSOURCE_PLL4Q
2423   *         @arg @ref LL_RCC_UART78_CLKSOURCE_HSI
2424   *         @arg @ref LL_RCC_UART78_CLKSOURCE_CSI
2425   *         @arg @ref LL_RCC_UART78_CLKSOURCE_HSE
2426   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HCLK6
2427   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL3R
2428   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL4P
2429   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI
2430   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_HCLK2
2431   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_PLL3R
2432   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_PLL4P
2433   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_HSI
2434   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_CSI
2435   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_PLL4R
2436   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_LSE
2437   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_LSI
2438   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_CSI
2439   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_PLL4R
2440   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_LSE
2441   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_LSI
2442   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
2443   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
2444   *         @arg @ref LL_RCC_MCO1SOURCE_CSI
2445   *         @arg @ref LL_RCC_MCO1SOURCE_LSI
2446   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
2447   *         @arg @ref LL_RCC_MCO2SOURCE_MPU
2448   *         @arg @ref LL_RCC_MCO2SOURCE_AXI
2449   *         @arg @ref LL_RCC_MCO2SOURCE_MCU
2450   *         @arg @ref LL_RCC_MCO2SOURCE_PLL4
2451   *         @arg @ref LL_RCC_MCO2SOURCE_HSE
2452   *         @arg @ref LL_RCC_MCO2SOURCE_HSI
2453   *         @arg @ref LL_RCC_TIMG1PRES_DEACTIVATED
2454   *         @arg @ref LL_RCC_TIMG1PRES_ACTIVATED
2455   *         @arg @ref LL_RCC_TIMG2PRES_DEACTIVATED
2456   *         @arg @ref LL_RCC_TIMG2PRES_ACTIVATED
2457   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2458   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL4P
2459   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3Q
2460   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2461   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2462   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PER
2463   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_OFF
2464   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK3
2465   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL4Q
2466   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PER
2467   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE
2468   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI
2469   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_OFF
2470   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK3
2471   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL4P
2472   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3Q
2473   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE
2474   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI
2475   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PER
2476   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_OFF
2477   * @retval None
2478   */
LL_RCC_SetClockSource(uint32_t ClkSource)2479 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
2480 {
2481   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)&RCC->I2C46CKSELR + LL_CLKSOURCE_REG(ClkSource));
2482   MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
2483 }
2484 
2485 /**
2486   * @brief  Configure I2Cx clock source
2487   * @rmtoll I2C12CKSELR        I2C12SRC     LL_RCC_SetI2CClockSource\n
2488   *         I2C35CKSELR        I2C35SRC     LL_RCC_SetI2CClockSource\n
2489   *         I2C46CKSELR        I2C46SRC     LL_RCC_SetI2CClockSource
2490   * @param  ClkSource This parameter can be one of the following values:
2491   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_PCLK1
2492   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_PLL4R
2493   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_HSI
2494   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_CSI
2495   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_PCLK1
2496   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_PLL4R
2497   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_HSI
2498   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_CSI
2499   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_PCLK5
2500   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_PLL3Q
2501   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_HSI
2502   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_CSI
2503   * @retval None
2504   */
LL_RCC_SetI2CClockSource(uint32_t ClkSource)2505 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
2506 {
2507   LL_RCC_SetClockSource(ClkSource);
2508 }
2509 
2510 /**
2511   * @brief  Configure SAIx clock source
2512   * @rmtoll SAI1CKSELR        SAI1SRC     LL_RCC_SetSAIClockSource\n
2513   *         SAI2CKSELR        SAI2SRC     LL_RCC_SetSAIClockSource\n
2514   *         SAI3CKSELR        SAI3SRC     LL_RCC_SetSAIClockSource\n
2515   *         SAI4CKSELR        SAI4SRC     LL_RCC_SetSAIClockSource
2516   * @param  ClkSource This parameter can be one of the following values:
2517   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL4Q
2518   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3Q
2519   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2SCKIN
2520   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PER
2521   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3R
2522   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL4Q
2523   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3Q
2524   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_I2SCKIN
2525   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PER
2526   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIF
2527   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3R
2528   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL4Q
2529   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL3Q
2530   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_I2SCKIN
2531   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PER
2532   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL3R
2533   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL4Q
2534   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL3Q
2535   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_I2SCKIN
2536   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PER
2537   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL3R
2538 
2539   * @retval None
2540   */
LL_RCC_SetSAIClockSource(uint32_t ClkSource)2541 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
2542 {
2543   LL_RCC_SetClockSource(ClkSource);
2544 }
2545 
2546 
2547 /**
2548   * @brief  Configure SPI/I2S clock source
2549   * @rmtoll SPI2S1CKSELR        SPI1SRC     LL_RCC_SetSPIClockSource\n
2550   *         SPI2S23CKSELR       SPI23SRC    LL_RCC_SetSPIClockSource\n
2551   *         SPI45CKSELR         SPI45SRC    LL_RCC_SetSPIClockSource\n
2552   *         SPI6CKSELR          SPI6SRC     LL_RCC_SetSPIClockSource
2553   * @param  ClkSource This parameter can be one of the following values:
2554   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL4P
2555   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3Q
2556   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_I2SCKIN
2557   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PER
2558   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3R
2559   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL4P
2560   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3Q
2561   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_I2SCKIN
2562   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PER
2563   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3R
2564   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
2565   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL4Q
2566   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
2567   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
2568   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
2569   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK5
2570   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL4Q
2571   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
2572   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
2573   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
2574   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
2575   * @retval None
2576   */
LL_RCC_SetSPIClockSource(uint32_t ClkSource)2577 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
2578 {
2579   LL_RCC_SetClockSource(ClkSource);
2580 }
2581 
2582 /**
2583   * @brief  Configure U(S)ARTx clock source
2584   * @rmtoll UART1CKSELR        UART1SRC      LL_RCC_SetUARTClockSource\n
2585   *         UART24CKSELR       UART24SRC     LL_RCC_SetUARTClockSource\n
2586   *         UART35CKSELR       UART35SRC     LL_RCC_SetUARTClockSource\n
2587   *         UART6CKSELR        UART6SRC      LL_RCC_SetUARTClockSource\n
2588   *         UART78CKSELR       UART78SRC     LL_RCC_SetUARTClockSource
2589   * @param  ClkSource This parameter can be one of the following values:
2590   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK5
2591   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q
2592   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2593   *         @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
2594   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PLL4Q
2595   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSE
2596   *         @arg @ref LL_RCC_UART24_CLKSOURCE_PCLK1
2597   *         @arg @ref LL_RCC_UART24_CLKSOURCE_PLL4Q
2598   *         @arg @ref LL_RCC_UART24_CLKSOURCE_HSI
2599   *         @arg @ref LL_RCC_UART24_CLKSOURCE_CSI
2600   *         @arg @ref LL_RCC_UART24_CLKSOURCE_HSE
2601   *         @arg @ref LL_RCC_UART35_CLKSOURCE_PCLK1
2602   *         @arg @ref LL_RCC_UART35_CLKSOURCE_PLL4Q
2603   *         @arg @ref LL_RCC_UART35_CLKSOURCE_HSI
2604   *         @arg @ref LL_RCC_UART35_CLKSOURCE_CSI
2605   *         @arg @ref LL_RCC_UART35_CLKSOURCE_HSE
2606   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
2607   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PLL4Q
2608   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
2609   *         @arg @ref LL_RCC_USART6_CLKSOURCE_CSI
2610   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSE
2611   *         @arg @ref LL_RCC_UART78_CLKSOURCE_PCLK1
2612   *         @arg @ref LL_RCC_UART78_CLKSOURCE_PLL4Q
2613   *         @arg @ref LL_RCC_UART78_CLKSOURCE_HSI
2614   *         @arg @ref LL_RCC_UART78_CLKSOURCE_CSI
2615   *         @arg @ref LL_RCC_UART78_CLKSOURCE_HSE
2616   * @retval None
2617   */
LL_RCC_SetUARTClockSource(uint32_t ClkSource)2618 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t ClkSource)
2619 {
2620   LL_RCC_SetClockSource(ClkSource);
2621 }
2622 
2623 /**
2624   * @brief  Configure SDMMCx clock source
2625   * @rmtoll SDMMC12CKSELR      SDMMC12SRC      LL_RCC_SetSDMMCClockSource\n
2626   *         SDMMC3CKSELR       SDMMC3SRC       LL_RCC_SetSDMMCClockSource
2627   * @param  ClkSource This parameter can be one of the following values:
2628   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HCLK6
2629   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL3R
2630   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL4P
2631   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI
2632   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_HCLK2
2633   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_PLL3R
2634   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_PLL4P
2635   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_HSI
2636   * @retval None
2637   */
LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)2638 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
2639 {
2640   LL_RCC_SetClockSource(ClkSource);
2641 }
2642 
2643 /**
2644   * @brief  Configure ETH clock source
2645   * @rmtoll ETHCKSELR      ETHSRC      LL_RCC_SetETHClockSource
2646   * @param  ClkSource This parameter can be one of the following values:
2647   *         @arg @ref LL_RCC_ETH_CLKSOURCE_PLL4P
2648   *         @arg @ref LL_RCC_ETH_CLKSOURCE_PLL3Q
2649   *         @arg @ref LL_RCC_ETH_CLKSOURCE_OFF
2650   * @retval None
2651   */
LL_RCC_SetETHClockSource(uint32_t ClkSource)2652 __STATIC_INLINE void LL_RCC_SetETHClockSource(uint32_t ClkSource)
2653 {
2654   MODIFY_REG(RCC->ETHCKSELR, RCC_ETHCKSELR_ETHSRC, ClkSource);
2655 }
2656 
2657 /**
2658   * @brief  Configure QSPI clock source
2659   * @rmtoll QSPICKSELR      QSPISRC      LL_RCC_SetQSPIClockSource
2660   * @param  ClkSource This parameter can be one of the following values:
2661   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_ACLK
2662   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL3R
2663   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL4P
2664   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PER
2665   * @retval None
2666   */
LL_RCC_SetQSPIClockSource(uint32_t ClkSource)2667 __STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)
2668 {
2669   MODIFY_REG(RCC->QSPICKSELR, RCC_QSPICKSELR_QSPISRC, ClkSource);
2670 }
2671 
2672 /**
2673   * @brief  Configure FMC clock source
2674   * @rmtoll FMCCKSELR      FMCSRC      LL_RCC_SetFMCClockSource
2675   * @param  ClkSource This parameter can be one of the following values:
2676   *         @arg @ref LL_RCC_FMC_CLKSOURCE_ACLK
2677   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL3R
2678   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL4P
2679   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PER
2680   * @retval None
2681   */
LL_RCC_SetFMCClockSource(uint32_t ClkSource)2682 __STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
2683 {
2684   MODIFY_REG(RCC->FMCCKSELR, RCC_FMCCKSELR_FMCSRC, ClkSource);
2685 }
2686 
2687 #if defined(FDCAN1)
2688 /**
2689   * @brief  Configure FDCAN clock source
2690   * @rmtoll FDCANCKSELR      FDCANSRC      LL_RCC_SetFDCANClockSource
2691   * @param  ClkSource This parameter can be one of the following values:
2692   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
2693   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL3Q
2694   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL4Q
2695   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL4R
2696   * @retval None
2697   */
LL_RCC_SetFDCANClockSource(uint32_t ClkSource)2698 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
2699 {
2700   MODIFY_REG(RCC->FDCANCKSELR, RCC_FDCANCKSELR_FDCANSRC, ClkSource);
2701 }
2702 #endif /*FDCAN1*/
2703 
2704 /**
2705   * @brief  Configure SPDIFRX clock source
2706   * @rmtoll SPDIFCKSELR      SPDIFSRC      LL_RCC_SetSPDIFRXClockSource
2707   * @param  ClkSource This parameter can be one of the following values:
2708   *         @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL4P
2709   *         @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL3Q
2710   *         @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_HSI
2711   * @retval None
2712   */
LL_RCC_SetSPDIFRXClockSource(uint32_t ClkSource)2713 __STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t ClkSource)
2714 {
2715   MODIFY_REG(RCC->SPDIFCKSELR, RCC_SPDIFCKSELR_SPDIFSRC, ClkSource);
2716 }
2717 
2718 /**
2719   * @brief  Configure CEC clock source
2720   * @rmtoll CECCKSELR      CECSRC      LL_RCC_SetCECClockSource
2721   * @param  ClkSource This parameter can be one of the following values:
2722   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2723   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
2724   *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI122
2725   * @retval None
2726   */
LL_RCC_SetCECClockSource(uint32_t ClkSource)2727 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
2728 {
2729   MODIFY_REG(RCC->CECCKSELR, RCC_CECCKSELR_CECSRC, ClkSource);
2730 }
2731 
2732 /**
2733   * @brief  Configure USBPHY clock source
2734   * @rmtoll USBCKSELR      USBPHYSRC      LL_RCC_SetUSBPHYClockSource
2735   * @param  ClkSource This parameter can be one of the following values:
2736   *         @arg @ref LL_RCC_USBPHY_CLKSOURCE_HSE
2737   *         @arg @ref LL_RCC_USBPHY_CLKSOURCE_PLL4R
2738   *         @arg @ref LL_RCC_USBPHY_CLKSOURCE_HSE2
2739   * @retval None
2740   */
LL_RCC_SetUSBPHYClockSource(uint32_t ClkSource)2741 __STATIC_INLINE void LL_RCC_SetUSBPHYClockSource(uint32_t ClkSource)
2742 {
2743   MODIFY_REG(RCC->USBCKSELR, RCC_USBCKSELR_USBPHYSRC, ClkSource);
2744 }
2745 
2746 /**
2747   * @brief  Configure USBO clock source
2748   * @rmtoll USBCKSELR      USBOSRC      LL_RCC_SetUSBOClockSource
2749   * @param  ClkSource This parameter can be one of the following values:
2750   *         @arg @ref LL_RCC_USBO_CLKSOURCE_PLL4R
2751   *         @arg @ref LL_RCC_USBO_CLKSOURCE_PHY
2752   * @retval None
2753   */
LL_RCC_SetUSBOClockSource(uint32_t ClkSource)2754 __STATIC_INLINE void LL_RCC_SetUSBOClockSource(uint32_t ClkSource)
2755 {
2756   MODIFY_REG(RCC->USBCKSELR, RCC_USBCKSELR_USBOSRC, ClkSource);
2757 }
2758 
2759 /**
2760   * @brief  Configure RNGx clock source
2761   * @rmtoll RNG1CKSELR      RNG1SRC      LL_RCC_SetRNGClockSource\n
2762   *         RNG2CKSELR      RNG2SRC      LL_RCC_SetRNGClockSource
2763   * @param  ClkSource This parameter can be one of the following values:
2764   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_CSI
2765   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_PLL4R
2766   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_LSE
2767   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_LSI
2768   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_CSI
2769   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_PLL4R
2770   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_LSE
2771   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_LSI
2772   * @retval None
2773   */
LL_RCC_SetRNGClockSource(uint32_t ClkSource)2774 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)
2775 {
2776   LL_RCC_SetClockSource(ClkSource);
2777 }
2778 
2779 /**
2780   * @brief  Configure CKPER clock source
2781   * @rmtoll CPERCKSELR      CKPERSRC      LL_RCC_SetCKPERClockSource
2782   * @param  ClkSource This parameter can be one of the following values:
2783   *         @arg @ref LL_RCC_CKPER_CLKSOURCE_HSI
2784   *         @arg @ref LL_RCC_CKPER_CLKSOURCE_CSI
2785   *         @arg @ref LL_RCC_CKPER_CLKSOURCE_HSE
2786   *         @arg @ref LL_RCC_CKPER_CLKSOURCE_OFF
2787   * @retval None
2788   */
LL_RCC_SetCKPERClockSource(uint32_t ClkSource)2789 __STATIC_INLINE void LL_RCC_SetCKPERClockSource(uint32_t ClkSource)
2790 {
2791   MODIFY_REG(RCC->CPERCKSELR, RCC_CPERCKSELR_CKPERSRC, ClkSource);
2792 }
2793 
2794 /**
2795   * @brief  Configure STGEN clock source
2796   * @rmtoll STGENCKSELR      STGENSRC      LL_RCC_SetSTGENClockSource
2797   * @param  ClkSource This parameter can be one of the following values:
2798   *         @arg @ref LL_RCC_STGEN_CLKSOURCE_HSI
2799   *         @arg @ref LL_RCC_STGEN_CLKSOURCE_HSE
2800   *         @arg @ref LL_RCC_STGEN_CLKSOURCE_OFF
2801   * @retval None
2802   */
LL_RCC_SetSTGENClockSource(uint32_t ClkSource)2803 __STATIC_INLINE void LL_RCC_SetSTGENClockSource(uint32_t ClkSource)
2804 {
2805   MODIFY_REG(RCC->STGENCKSELR, RCC_STGENCKSELR_STGENSRC, ClkSource);
2806 }
2807 
2808 #if defined(DSI)
2809 /**
2810   * @brief  Configure DSI clock source
2811   * @rmtoll DSICKSELR      DSISRC      LL_RCC_SetDSIClockSource
2812   * @param  ClkSource This parameter can be one of the following values:
2813   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
2814   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL4P
2815   * @retval None
2816   */
LL_RCC_SetDSIClockSource(uint32_t ClkSource)2817 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)
2818 {
2819   MODIFY_REG(RCC->DSICKSELR, RCC_DSICKSELR_DSISRC, ClkSource);
2820 }
2821 #endif /*DSI*/
2822 
2823 /**
2824   * @brief  Configure ADC clock source
2825   * @rmtoll ADCCKSELR      ADCSRC      LL_RCC_SetADCClockSource
2826   * @param  ClkSource This parameter can be one of the following values:
2827   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL4R
2828   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PER
2829   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3Q
2830   * @retval None
2831   */
LL_RCC_SetADCClockSource(uint32_t ClkSource)2832 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
2833 {
2834   MODIFY_REG(RCC->ADCCKSELR, RCC_ADCCKSELR_ADCSRC, ClkSource);
2835 }
2836 
2837 /**
2838   * @brief  Configure LPTIMx clock source
2839   * @rmtoll LPTIM1CKSELR      LPTIM1SRC      LL_RCC_SetLPTIMClockSource\n
2840   *         LPTIM23CKSELR     LPTIM23SRC     LL_RCC_SetLPTIMClockSource\n
2841   *         LPTIM45CKSELR     LPTIM45SRC     LL_RCC_SetLPTIMClockSource
2842   * @param  ClkSource This parameter can be one of the following values:
2843   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2844   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL4P
2845   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3Q
2846   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2847   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2848   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PER
2849   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_OFF
2850   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK3
2851   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL4Q
2852   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PER
2853   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE
2854   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI
2855   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_OFF
2856   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK3
2857   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL4P
2858   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3Q
2859   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE
2860   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI
2861   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PER
2862   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_OFF
2863   * @retval None
2864   */
LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)2865 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
2866 {
2867   LL_RCC_SetClockSource(ClkSource);
2868 }
2869 
2870 /**
2871   * @brief  Get peripheral clock source
2872   * @rmtoll I2C46CKSELR        *     LL_RCC_GetClockSource\n
2873   *         SPI6CKSELR         *     LL_RCC_GetClockSource\n
2874   *         UART1CKSELR        *     LL_RCC_GetClockSource\n
2875   *         RNG1CKSELR         *     LL_RCC_GetClockSource\n
2876   *         TIMG1PRER          *     LL_RCC_GetClockSource\n
2877   *         TIMG2PRER          *     LL_RCC_GetClockSource\n
2878   *         I2C12CKSELR        *     LL_RCC_GetClockSource\n
2879   *         I2C35CKSELR        *     LL_RCC_GetClockSource\n
2880   *         SAI1CKSELR         *     LL_RCC_GetClockSource\n
2881   *         SAI2CKSELR         *     LL_RCC_GetClockSource\n
2882   *         SAI3CKSELR         *     LL_RCC_GetClockSource\n
2883   *         SAI4CKSELR         *     LL_RCC_GetClockSource\n
2884   *         SPI2S1CKSELR       *     LL_RCC_GetClockSource\n
2885   *         SPI2S23CKSELR      *     LL_RCC_GetClockSource\n
2886   *         SPI45CKSELR        *     LL_RCC_GetClockSource\n
2887   *         UART6CKSELR        *     LL_RCC_GetClockSource\n
2888   *         UART24CKSELR       *     LL_RCC_GetClockSource\n
2889   *         UART35CKSELR       *     LL_RCC_GetClockSource\n
2890   *         UART78CKSELR       *     LL_RCC_GetClockSource\n
2891   *         SDMMC12CKSELR      *     LL_RCC_GetClockSource\n
2892   *         SDMMC3CKSELR       *     LL_RCC_GetClockSource\n
2893   *         RNG2CKSELR         *     LL_RCC_GetClockSource\n
2894   *         LPTIM45CKSELR      *     LL_RCC_GetClockSource\n
2895   *         LPTIM23CKSELR      *     LL_RCC_GetClockSource\n
2896   *         LPTIM1CKSELR       *     LL_RCC_GetClockSource
2897   * @param  Periph This parameter can be one of the following values:
2898   *         @arg @ref LL_RCC_I2C12_CLKSOURCE
2899   *         @arg @ref LL_RCC_I2C35_CLKSOURCE
2900   *         @arg @ref LL_RCC_I2C46_CLKSOURCE
2901   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
2902   *         @arg @ref LL_RCC_SAI2_CLKSOURCE
2903   *         @arg @ref LL_RCC_SAI3_CLKSOURCE
2904   *         @arg @ref LL_RCC_SAI4_CLKSOURCE
2905   *         @arg @ref LL_RCC_SPI1_CLKSOURCE
2906   *         @arg @ref LL_RCC_SPI23_CLKSOURCE
2907   *         @arg @ref LL_RCC_SPI45_CLKSOURCE
2908   *         @arg @ref LL_RCC_SPI6_CLKSOURCE
2909   *         @arg @ref LL_RCC_USART1_CLKSOURCE
2910   *         @arg @ref LL_RCC_UART24_CLKSOURCE
2911   *         @arg @ref LL_RCC_UART35_CLKSOURCE
2912   *         @arg @ref LL_RCC_USART6_CLKSOURCE
2913   *         @arg @ref LL_RCC_UART78_CLKSOURCE
2914   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE
2915   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE
2916   *         @arg @ref LL_RCC_RNG1_CLKSOURCE
2917   *         @arg @ref LL_RCC_RNG2_CLKSOURCE
2918   *         @arg @ref LL_RCC_TIMG1PRES
2919   *         @arg @ref LL_RCC_TIMG2PRES
2920   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2921   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE
2922   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE
2923   * @retval Returned value can be one of the following values:
2924   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_PCLK1
2925   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_PLL4R
2926   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_HSI
2927   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_CSI
2928   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_PCLK1
2929   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_PLL4R
2930   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_HSI
2931   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_CSI
2932   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_PCLK5
2933   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_PLL3Q
2934   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_HSI
2935   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_CSI
2936   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL4Q
2937   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3Q
2938   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2SCKIN
2939   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PER
2940   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3R
2941   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL4Q
2942   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3Q
2943   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_I2SCKIN
2944   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PER
2945   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIF
2946   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3R
2947   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL4Q
2948   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL3Q
2949   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_I2SCKIN
2950   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PER
2951   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL3R
2952   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL4Q
2953   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL3Q
2954   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_I2SCKIN
2955   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PER
2956   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL3R
2957   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL4P
2958   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3Q
2959   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_I2SCKIN
2960   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PER
2961   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3R
2962   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL4P
2963   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3Q
2964   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_I2SCKIN
2965   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PER
2966   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3R
2967   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
2968   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL4Q
2969   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
2970   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
2971   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
2972   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK5
2973   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL4Q
2974   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
2975   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
2976   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
2977   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
2978   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK5
2979   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q
2980   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2981   *         @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
2982   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PLL4Q
2983   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSE
2984   *         @arg @ref LL_RCC_UART24_CLKSOURCE_PCLK1
2985   *         @arg @ref LL_RCC_UART24_CLKSOURCE_PLL4Q
2986   *         @arg @ref LL_RCC_UART24_CLKSOURCE_HSI
2987   *         @arg @ref LL_RCC_UART24_CLKSOURCE_CSI
2988   *         @arg @ref LL_RCC_UART24_CLKSOURCE_HSE
2989   *         @arg @ref LL_RCC_UART35_CLKSOURCE_PCLK1
2990   *         @arg @ref LL_RCC_UART35_CLKSOURCE_PLL4Q
2991   *         @arg @ref LL_RCC_UART35_CLKSOURCE_HSI
2992   *         @arg @ref LL_RCC_UART35_CLKSOURCE_CSI
2993   *         @arg @ref LL_RCC_UART35_CLKSOURCE_HSE
2994   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
2995   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PLL4Q
2996   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
2997   *         @arg @ref LL_RCC_USART6_CLKSOURCE_CSI
2998   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSE
2999   *         @arg @ref LL_RCC_UART78_CLKSOURCE_PCLK1
3000   *         @arg @ref LL_RCC_UART78_CLKSOURCE_PLL4Q
3001   *         @arg @ref LL_RCC_UART78_CLKSOURCE_HSI
3002   *         @arg @ref LL_RCC_UART78_CLKSOURCE_CSI
3003   *         @arg @ref LL_RCC_UART78_CLKSOURCE_HSE
3004   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HCLK6
3005   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL3R
3006   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL4P
3007   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI
3008   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_HCLK2
3009   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_PLL3R
3010   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_PLL4P
3011   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_HSI
3012   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_CSI
3013   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_PLL4R
3014   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_LSE
3015   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_LSI
3016   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_CSI
3017   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_PLL4R
3018   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_LSE
3019   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_LSI
3020   *         @arg @ref LL_RCC_TIMG1PRES_DEACTIVATED
3021   *         @arg @ref LL_RCC_TIMG1PRES_ACTIVATED
3022   *         @arg @ref LL_RCC_TIMG2PRES_DEACTIVATED
3023   *         @arg @ref LL_RCC_TIMG2PRES_ACTIVATED
3024   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3025   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL4P
3026   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3Q
3027   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3028   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3029   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PER
3030   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_OFF
3031   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK3
3032   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL4Q
3033   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PER
3034   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE
3035   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI
3036   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_OFF
3037   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK3
3038   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL4P
3039   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3Q
3040   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE
3041   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI
3042   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PER
3043   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_OFF
3044   */
LL_RCC_GetClockSource(uint32_t Periph)3045 __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
3046 {
3047   __IO const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->I2C46CKSELR) + LL_CLKSOURCE_REG(Periph)));
3048 
3049   return (uint32_t)(Periph | ((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) << RCC_CONFIG_SHIFT));
3050 }
3051 
3052 /**
3053   * @brief  Get I2Cx clock source
3054   * @rmtoll I2C12CKSELR        I2C12SRC     LL_RCC_GetI2CClockSource\n
3055   *         I2C35CKSELR        I2C35SRC     LL_RCC_GetI2CClockSource\n
3056   *         I2C46CKSELR        I2C46SRC     LL_RCC_GetI2CClockSource
3057   * @param  Periph This parameter can be one of the following values:
3058   *         @arg @ref LL_RCC_I2C12_CLKSOURCE
3059   *         @arg @ref LL_RCC_I2C35_CLKSOURCE
3060   *         @arg @ref LL_RCC_I2C46_CLKSOURCE
3061   * @retval Returned value can be one of the following values:
3062   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_PCLK1
3063   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_PLL4R
3064   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_HSI
3065   *         @arg @ref LL_RCC_I2C12_CLKSOURCE_CSI
3066   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_PCLK1
3067   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_PLL4R
3068   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_HSI
3069   *         @arg @ref LL_RCC_I2C35_CLKSOURCE_CSI
3070   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_PCLK5
3071   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_PLL3Q
3072   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_HSI
3073   *         @arg @ref LL_RCC_I2C46_CLKSOURCE_CSI
3074   */
LL_RCC_GetI2CClockSource(uint32_t Periph)3075 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
3076 {
3077   return LL_RCC_GetClockSource(Periph);
3078 }
3079 
3080 /**
3081   * @brief  Get SAIx clock source
3082   * @rmtoll SAI1CKSELR        SAI1SRC     LL_RCC_GetSAIClockSource\n
3083   *         SAI2CKSELR        SAI2SRC     LL_RCC_GetSAIClockSource\n
3084   *         SAI3CKSELR        SAI3SRC     LL_RCC_GetSAIClockSource\n
3085   *         SAI4CKSELR        SAI4SRC     LL_RCC_GetSAIClockSource
3086   * @param  Periph This parameter can be one of the following values:
3087   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
3088   *         @arg @ref LL_RCC_SAI2_CLKSOURCE
3089   *         @arg @ref LL_RCC_SAI3_CLKSOURCE
3090   *         @arg @ref LL_RCC_SAI4_CLKSOURCE
3091   * @retval Returned value can be one of the following values:
3092   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL4Q
3093   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3Q
3094   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2SCKIN
3095   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PER
3096   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3R
3097   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL4Q
3098   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3Q
3099   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_I2SCKIN
3100   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PER
3101   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIF
3102   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3R
3103   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL4Q
3104   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL3Q
3105   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_I2SCKIN
3106   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PER
3107   *         @arg @ref LL_RCC_SAI3_CLKSOURCE_PLL3R
3108   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL4Q
3109   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL3Q
3110   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_I2SCKIN
3111   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PER
3112   *         @arg @ref LL_RCC_SAI4_CLKSOURCE_PLL3R
3113   */
LL_RCC_GetSAIClockSource(uint32_t Periph)3114 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
3115 {
3116   return LL_RCC_GetClockSource(Periph);
3117 }
3118 
3119 
3120 /**
3121   * @brief  Get SPI/I2S clock source
3122   * @rmtoll SPI2S1CKSELR        SPI1SRC     LL_RCC_GetSPIClockSource\n
3123   *         SPI2S23CKSELR       SPI23SRC    LL_RCC_GetSPIClockSource\n
3124   *         SPI45CKSELR         SPI45SRC    LL_RCC_GetSPIClockSource\n
3125   *         SPI6CKSELR          SPI6SRC     LL_RCC_GetSPIClockSource
3126   * @param  Periph This parameter can be one of the following values:
3127   *         @arg @ref LL_RCC_SPI1_CLKSOURCE
3128   *         @arg @ref LL_RCC_SPI23_CLKSOURCE
3129   *         @arg @ref LL_RCC_SPI45_CLKSOURCE
3130   *         @arg @ref LL_RCC_SPI6_CLKSOURCE
3131   * @retval Returned value can be one of the following values:
3132   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL4P
3133   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3Q
3134   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_I2SCKIN
3135   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PER
3136   *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3R
3137   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL4P
3138   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3Q
3139   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_I2SCKIN
3140   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PER
3141   *         @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3R
3142   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3143   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL4Q
3144   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3145   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3146   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3147   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK5
3148   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL4Q
3149   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3150   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3151   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3152   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3153   */
LL_RCC_GetSPIClockSource(uint32_t Periph)3154 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
3155 {
3156   return LL_RCC_GetClockSource(Periph);
3157 }
3158 
3159 /**
3160   * @brief  Get U(S)ARTx clock source
3161   * @rmtoll UART1CKSELR        UART1SRC      LL_RCC_GetUARTClockSource\n
3162   *         UART24CKSELR       UART24SRC     LL_RCC_GetUARTClockSource\n
3163   *         UART35CKSELR       UART35SRC     LL_RCC_GetUARTClockSource\n
3164   *         UART6CKSELR        UART6SRC      LL_RCC_GetUARTClockSource\n
3165   *         UART78CKSELR       UART78SRC     LL_RCC_GetUARTClockSource
3166   * @param  Periph This parameter can be one of the following values:
3167   *         @arg @ref LL_RCC_USART1_CLKSOURCE
3168   *         @arg @ref LL_RCC_UART24_CLKSOURCE
3169   *         @arg @ref LL_RCC_UART35_CLKSOURCE
3170   *         @arg @ref LL_RCC_USART6_CLKSOURCE
3171   *         @arg @ref LL_RCC_UART78_CLKSOURCE
3172   * @retval Returned value can be one of the following values:
3173   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK5
3174   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q
3175   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
3176   *         @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
3177   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PLL4Q
3178   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSE
3179   *         @arg @ref LL_RCC_UART24_CLKSOURCE_PCLK1
3180   *         @arg @ref LL_RCC_UART24_CLKSOURCE_PLL4Q
3181   *         @arg @ref LL_RCC_UART24_CLKSOURCE_HSI
3182   *         @arg @ref LL_RCC_UART24_CLKSOURCE_CSI
3183   *         @arg @ref LL_RCC_UART24_CLKSOURCE_HSE
3184   *         @arg @ref LL_RCC_UART35_CLKSOURCE_PCLK1
3185   *         @arg @ref LL_RCC_UART35_CLKSOURCE_PLL4Q
3186   *         @arg @ref LL_RCC_UART35_CLKSOURCE_HSI
3187   *         @arg @ref LL_RCC_UART35_CLKSOURCE_CSI
3188   *         @arg @ref LL_RCC_UART35_CLKSOURCE_HSE
3189   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
3190   *         @arg @ref LL_RCC_USART6_CLKSOURCE_PLL4Q
3191   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
3192   *         @arg @ref LL_RCC_USART6_CLKSOURCE_CSI
3193   *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSE
3194   *         @arg @ref LL_RCC_UART78_CLKSOURCE_PCLK1
3195   *         @arg @ref LL_RCC_UART78_CLKSOURCE_PLL4Q
3196   *         @arg @ref LL_RCC_UART78_CLKSOURCE_HSI
3197   *         @arg @ref LL_RCC_UART78_CLKSOURCE_CSI
3198   *         @arg @ref LL_RCC_UART78_CLKSOURCE_HSE
3199   */
LL_RCC_GetUARTClockSource(uint32_t Periph)3200 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t Periph)
3201 {
3202   return LL_RCC_GetClockSource(Periph);
3203 }
3204 
3205 /**
3206   * @brief  Get SDMMCx clock source
3207   * @rmtoll SDMMC12CKSELR      SDMMC12SRC      LL_RCC_GetSDMMCClockSource\n
3208   *         SDMMC3CKSELR       SDMMC3SRC       LL_RCC_GetSDMMCClockSource
3209   * @param  Periph This parameter can be one of the following values:
3210   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE
3211   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE
3212   * @retval Returned value can be one of the following values:
3213   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HCLK6
3214   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL3R
3215   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL4P
3216   *         @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI
3217   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_HCLK2
3218   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_PLL3R
3219   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_PLL4P
3220   *         @arg @ref LL_RCC_SDMMC3_CLKSOURCE_HSI
3221   */
LL_RCC_GetSDMMCClockSource(uint32_t Periph)3222 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
3223 {
3224   return LL_RCC_GetClockSource(Periph);
3225 }
3226 
3227 /**
3228   * @brief  Get ETH clock source
3229   * @rmtoll ETHCKSELR      ETHSRC      LL_RCC_GetETHClockSource
3230   * @param  Periph This parameter can be one of the following values:
3231   *         @arg @ref LL_RCC_ETH_CLKSOURCE
3232   * @retval Returned value can be one of the following values:
3233   *         @arg @ref LL_RCC_ETH_CLKSOURCE_PLL4P
3234   *         @arg @ref LL_RCC_ETH_CLKSOURCE_PLL3Q
3235   *         @arg @ref LL_RCC_ETH_CLKSOURCE_OFF
3236   */
LL_RCC_GetETHClockSource(uint32_t Periph)3237 __STATIC_INLINE uint32_t LL_RCC_GetETHClockSource(uint32_t Periph)
3238 {
3239   /* Prevent unused argument compilation warning */
3240   UNUSED(Periph);
3241   return (uint32_t)(READ_BIT(RCC->ETHCKSELR, RCC_ETHCKSELR_ETHSRC));
3242 }
3243 
3244 /**
3245   * @brief  Get QSPI clock source
3246   * @rmtoll QSPICKSELR      QSPISRC      LL_RCC_GetQSPIClockSource
3247   * @param  Periph This parameter can be one of the following values:
3248   *         @arg @ref LL_RCC_QSPI_CLKSOURCE
3249   * @retval Returned value can be one of the following values:
3250   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_ACLK
3251   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL3R
3252   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL4P
3253   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PER
3254   */
LL_RCC_GetQSPIClockSource(uint32_t Periph)3255 __STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)
3256 {
3257   /* Prevent unused argument compilation warning */
3258   UNUSED(Periph);
3259   return (uint32_t)(READ_BIT(RCC->QSPICKSELR, RCC_QSPICKSELR_QSPISRC));
3260 }
3261 
3262 /**
3263   * @brief  Get FMC clock source
3264   * @rmtoll FMCCKSELR      FMCSRC      LL_RCC_GetFMCClockSource
3265   * @param  Periph This parameter can be one of the following values:
3266   *         @arg @ref LL_RCC_FMC_CLKSOURCE
3267   * @retval Returned value can be one of the following values:
3268   *         @arg @ref LL_RCC_FMC_CLKSOURCE_ACLK
3269   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL3R
3270   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL4P
3271   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PER
3272   */
LL_RCC_GetFMCClockSource(uint32_t Periph)3273 __STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
3274 {
3275   /* Prevent unused argument compilation warning */
3276   UNUSED(Periph);
3277   return (uint32_t)(READ_BIT(RCC->FMCCKSELR, RCC_FMCCKSELR_FMCSRC));
3278 }
3279 
3280 #if defined(FDCAN1)
3281 /**
3282   * @brief  Get FDCAN clock source
3283   * @rmtoll FDCANCKSELR      FDCANSRC      LL_RCC_GetFDCANClockSource
3284   * @param  Periph This parameter can be one of the following values:
3285   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
3286   * @retval Returned value can be one of the following values:
3287   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3288   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL3Q
3289   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL4Q
3290   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL4R
3291   */
LL_RCC_GetFDCANClockSource(uint32_t Periph)3292 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
3293 {
3294   /* Prevent unused argument compilation warning */
3295   UNUSED(Periph);
3296   return (uint32_t)(READ_BIT(RCC->FDCANCKSELR, RCC_FDCANCKSELR_FDCANSRC));
3297 }
3298 #endif /*FDCAN1*/
3299 
3300 /**
3301   * @brief  Get SPDIFRX clock source
3302   * @rmtoll SPDIFCKSELR      SPDIFSRC      LL_RCC_GetSPDIFRXClockSource
3303   * @param  Periph This parameter can be one of the following values:
3304   *         @arg @ref LL_RCC_SPDIFRX_CLKSOURCE
3305   * @retval Returned value can be one of the following values:
3306   *         @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL4P
3307   *         @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL3Q
3308   *         @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_HSI
3309   */
LL_RCC_GetSPDIFRXClockSource(uint32_t Periph)3310 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t Periph)
3311 {
3312   /* Prevent unused argument compilation warning */
3313   UNUSED(Periph);
3314   return (uint32_t)(READ_BIT(RCC->SPDIFCKSELR, RCC_SPDIFCKSELR_SPDIFSRC));
3315 }
3316 
3317 /**
3318   * @brief  Get CEC clock source
3319   * @rmtoll CECCKSELR      CECSRC      LL_RCC_GetCECClockSource
3320   * @param  Periph This parameter can be one of the following values:
3321   *         @arg @ref LL_RCC_CEC_CLKSOURCE
3322   * @retval Returned value can be one of the following values:
3323   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3324   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3325   *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI122
3326   */
LL_RCC_GetCECClockSource(uint32_t Periph)3327 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
3328 {
3329   /* Prevent unused argument compilation warning */
3330   UNUSED(Periph);
3331   return (uint32_t)(READ_BIT(RCC->CECCKSELR, RCC_CECCKSELR_CECSRC));
3332 }
3333 
3334 /**
3335   * @brief  Get USBPHY clock source
3336   * @rmtoll USBCKSELR      USBPHYSRC      LL_RCC_GetUSBPHYClockSource
3337   * @param  Periph This parameter can be one of the following values:
3338   *         @arg @ref LL_RCC_USBPHY_CLKSOURCE
3339   * @retval Returned value can be one of the following values:
3340   *         @arg @ref LL_RCC_USBPHY_CLKSOURCE_HSE
3341   *         @arg @ref LL_RCC_USBPHY_CLKSOURCE_PLL4R
3342   *         @arg @ref LL_RCC_USBPHY_CLKSOURCE_HSE2
3343   */
LL_RCC_GetUSBPHYClockSource(uint32_t Periph)3344 __STATIC_INLINE uint32_t LL_RCC_GetUSBPHYClockSource(uint32_t Periph)
3345 {
3346   /* Prevent unused argument compilation warning */
3347   UNUSED(Periph);
3348   return (uint32_t)(READ_BIT(RCC->USBCKSELR, RCC_USBCKSELR_USBPHYSRC));
3349 }
3350 
3351 /**
3352   * @brief  Get USBO clock source
3353   * @rmtoll USBCKSELR      USBOSRC      LL_RCC_GetUSBOClockSource
3354   * @param  Periph This parameter can be one of the following values:
3355   *         @arg @ref LL_RCC_USBO_CLKSOURCE
3356   * @retval Returned value can be one of the following values:
3357   *         @arg @ref LL_RCC_USBO_CLKSOURCE_PLL4R
3358   *         @arg @ref LL_RCC_USBO_CLKSOURCE_PHY
3359   */
LL_RCC_GetUSBOClockSource(uint32_t Periph)3360 __STATIC_INLINE uint32_t LL_RCC_GetUSBOClockSource(uint32_t Periph)
3361 {
3362   /* Prevent unused argument compilation warning */
3363   UNUSED(Periph);
3364   return (uint32_t)(READ_BIT(RCC->USBCKSELR, RCC_USBCKSELR_USBOSRC));
3365 }
3366 
3367 /**
3368   * @brief  Get RNGx clock source
3369   * @rmtoll RNG1CKSELR      RNG1SRC      LL_RCC_GetRNGClockSource\n
3370   *         RNG2CKSELR      RNG2SRC      LL_RCC_GetRNGClockSource
3371   * @param  Periph This parameter can be one of the following values:
3372   *         @arg @ref LL_RCC_RNG1_CLKSOURCE
3373   *         @arg @ref LL_RCC_RNG2_CLKSOURCE
3374   * @retval Returned value can be one of the following values:
3375   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_CSI
3376   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_PLL4R
3377   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_LSE
3378   *         @arg @ref LL_RCC_RNG1_CLKSOURCE_LSI
3379   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_CSI
3380   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_PLL4R
3381   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_LSE
3382   *         @arg @ref LL_RCC_RNG2_CLKSOURCE_LSI
3383   */
LL_RCC_GetRNGClockSource(uint32_t Periph)3384 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)
3385 {
3386   return LL_RCC_GetClockSource(Periph);
3387 }
3388 
3389 /**
3390   * @brief  Get CKPER clock source
3391   * @rmtoll CPERCKSELR      CKPERSRC      LL_RCC_GetCKPERClockSource
3392   * @param  Periph This parameter can be one of the following values:
3393   *         @arg @ref LL_RCC_CKPER_CLKSOURCE
3394   * @retval Returned value can be one of the following values:
3395   *         @arg @ref LL_RCC_CKPER_CLKSOURCE_HSI
3396   *         @arg @ref LL_RCC_CKPER_CLKSOURCE_CSI
3397   *         @arg @ref LL_RCC_CKPER_CLKSOURCE_HSE
3398   *         @arg @ref LL_RCC_CKPER_CLKSOURCE_OFF
3399   */
LL_RCC_GetCKPERClockSource(uint32_t Periph)3400 __STATIC_INLINE uint32_t LL_RCC_GetCKPERClockSource(uint32_t Periph)
3401 {
3402   /* Prevent unused argument compilation warning */
3403   UNUSED(Periph);
3404   return (uint32_t)(READ_BIT(RCC->CPERCKSELR, RCC_CPERCKSELR_CKPERSRC));
3405 }
3406 
3407 /**
3408   * @brief  Get STGEN clock source
3409   * @rmtoll STGENCKSELR      STGENSRC      LL_RCC_GetSTGENClockSource
3410   * @param  Periph This parameter can be one of the following values:
3411   *         @arg @ref LL_RCC_STGEN_CLKSOURCE
3412   * @retval Returned value can be one of the following values:
3413   *         @arg @ref LL_RCC_STGEN_CLKSOURCE_HSI
3414   *         @arg @ref LL_RCC_STGEN_CLKSOURCE_HSE
3415   *         @arg @ref LL_RCC_STGEN_CLKSOURCE_OFF
3416   */
LL_RCC_GetSTGENClockSource(uint32_t Periph)3417 __STATIC_INLINE uint32_t LL_RCC_GetSTGENClockSource(uint32_t Periph)
3418 {
3419   /* Prevent unused argument compilation warning */
3420   UNUSED(Periph);
3421   return (uint32_t)(READ_BIT(RCC->STGENCKSELR, RCC_STGENCKSELR_STGENSRC));
3422 }
3423 
3424 #if defined(DSI)
3425 /**
3426   * @brief  Get DSI clock source
3427   * @rmtoll DSICKSELR      DSISRC      LL_RCC_GetDSIClockSource
3428   * @param  Periph This parameter can be one of the following values:
3429   *         @arg @ref LL_RCC_DSI_CLKSOURCE
3430   * @retval Returned value can be one of the following values:
3431   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3432   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL4P
3433   */
LL_RCC_GetDSIClockSource(uint32_t Periph)3434 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)
3435 {
3436   /* Prevent unused argument compilation warning */
3437   UNUSED(Periph);
3438   return (uint32_t)(READ_BIT(RCC->DSICKSELR, RCC_DSICKSELR_DSISRC));
3439 }
3440 #endif /*DSI*/
3441 
3442 /**
3443   * @brief  Get ADC clock source
3444   * @rmtoll ADCCKSELR      ADCSRC      LL_RCC_GetADCClockSource
3445   * @param  Periph This parameter can be one of the following values:
3446   *         @arg @ref LL_RCC_ADC_CLKSOURCE
3447   * @retval Returned value can be one of the following values:
3448   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL4R
3449   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PER
3450   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3Q
3451   */
LL_RCC_GetADCClockSource(uint32_t Periph)3452 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
3453 {
3454   /* Prevent unused argument compilation warning */
3455   UNUSED(Periph);
3456   return (uint32_t)(READ_BIT(RCC->ADCCKSELR, RCC_ADCCKSELR_ADCSRC));
3457 }
3458 
3459 /**
3460   * @brief  Get LPTIMx clock source
3461   * @rmtoll LPTIM1CKSELR      LPTIM1SRC      LL_RCC_GetLPTIMClockSource\n
3462   *         LPTIM23CKSELR     LPTIM23SRC     LL_RCC_GetLPTIMClockSource\n
3463   *         LPTIM45CKSELR     LPTIM45SRC     LL_RCC_GetLPTIMClockSource
3464   * @param  Periph This parameter can be one of the following values:
3465   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3466   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE
3467   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE
3468   * @retval Returned value can be one of the following values:
3469   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3470   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL4P
3471   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3Q
3472   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3473   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3474   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PER
3475   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_OFF
3476   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK3
3477   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL4Q
3478   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PER
3479   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE
3480   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI
3481   *         @arg @ref LL_RCC_LPTIM23_CLKSOURCE_OFF
3482   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK3
3483   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL4P
3484   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3Q
3485   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE
3486   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI
3487   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PER
3488   *         @arg @ref LL_RCC_LPTIM45_CLKSOURCE_OFF
3489   */
LL_RCC_GetLPTIMClockSource(uint32_t Periph)3490 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
3491 {
3492   return LL_RCC_GetClockSource(Periph);
3493 }
3494 
3495 /**
3496   * @}
3497   */
3498 
3499 /** @defgroup RCC_LL_EF_RTC RTC
3500   * @{
3501   */
3502 
3503 /**
3504   * @brief  Set RTC Clock Source
3505   * @note   Once the RTC clock source has been selected, it cannot be changed
3506   *         anymore unless the Backup domain is reset, or unless a failure is
3507   *         detected on LSE (LSECSS is set). The VSWRST bit can be used to reset
3508   *         them.
3509   * @rmtoll BDCR         RTCSRC        LL_RCC_SetRTCClockSource
3510   * @param  Source This parameter can be one of the following values:
3511   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3512   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3513   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3514   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV
3515   * @retval None
3516   */
LL_RCC_SetRTCClockSource(uint32_t Source)3517 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3518 {
3519   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSRC, Source);
3520 }
3521 
3522 /**
3523   * @brief  Get RTC Clock Source
3524   * @rmtoll BDCR         RTCSRC        LL_RCC_GetRTCClockSource
3525   * @retval Returned value can be one of the following values:
3526   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3527   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3528   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3529   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV
3530   */
LL_RCC_GetRTCClockSource(void)3531 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
3532 {
3533   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSRC));
3534 }
3535 
3536 /**
3537   * @brief  Enable RTC
3538   * @rmtoll BDCR         RTCCKEN         LL_RCC_EnableRTC
3539   * @retval None
3540   */
LL_RCC_EnableRTC(void)3541 __STATIC_INLINE void LL_RCC_EnableRTC(void)
3542 {
3543   SET_BIT(RCC->BDCR, RCC_BDCR_RTCCKEN);
3544 }
3545 
3546 /**
3547   * @brief  Disable RTC
3548   * @rmtoll BDCR         RTCCKEN         LL_RCC_DisableRTC
3549   * @retval None
3550   */
LL_RCC_DisableRTC(void)3551 __STATIC_INLINE void LL_RCC_DisableRTC(void)
3552 {
3553   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCCKEN);
3554 }
3555 
3556 /**
3557   * @brief  Check if RTC has been enabled or not
3558   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
3559   * @retval State of bit (1 or 0).
3560   */
LL_RCC_IsEnabledRTC(void)3561 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
3562 {
3563   return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCCKEN) == RCC_BDCR_RTCCKEN) ? 1UL : 0UL);
3564 }
3565 
3566 /**
3567   * @brief  Force the Backup domain reset
3568   * @rmtoll BDCR         VSWRST         LL_RCC_ForceBackupDomainReset
3569   * @retval None
3570   */
LL_RCC_ForceBackupDomainReset(void)3571 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
3572 {
3573   SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
3574 }
3575 
3576 /**
3577   * @brief  Release the Backup domain reset
3578   * @rmtoll BDCR         VSWRST         LL_RCC_ReleaseBackupDomainReset
3579   * @retval None
3580   */
LL_RCC_ReleaseBackupDomainReset(void)3581 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
3582 {
3583   CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
3584 }
3585 
3586 /**
3587   * @brief  Set HSE Prescaler for RTC Clock
3588   * @rmtoll RTCDIVR         RTCDIV        LL_RCC_SetRTC_HSEPrescaler
3589   * @param  Prescaler This parameter can be one of the following values:
3590   *         @arg @ref LL_RCC_RTC_HSE_DIV_1
3591   *         @arg @ref LL_RCC_RTC_HSE_DIV_2
3592   *         @arg @ref LL_RCC_RTC_HSE_DIV_3
3593   *         @arg @ref LL_RCC_RTC_HSE_DIV_4
3594   *         @arg @ref LL_RCC_RTC_HSE_DIV_5
3595   *         @arg @ref LL_RCC_RTC_HSE_DIV_6
3596   *         @arg @ref LL_RCC_RTC_HSE_DIV_7
3597   *         @arg @ref LL_RCC_RTC_HSE_DIV_8
3598   *         @arg @ref LL_RCC_RTC_HSE_DIV_9
3599   *         @arg @ref LL_RCC_RTC_HSE_DIV_10
3600   *         @arg @ref LL_RCC_RTC_HSE_DIV_11
3601   *         @arg @ref LL_RCC_RTC_HSE_DIV_12
3602   *         @arg @ref LL_RCC_RTC_HSE_DIV_13
3603   *         @arg @ref LL_RCC_RTC_HSE_DIV_14
3604   *         @arg @ref LL_RCC_RTC_HSE_DIV_15
3605   *         @arg @ref LL_RCC_RTC_HSE_DIV_16
3606   *         @arg @ref LL_RCC_RTC_HSE_DIV_17
3607   *         @arg @ref LL_RCC_RTC_HSE_DIV_18
3608   *         @arg @ref LL_RCC_RTC_HSE_DIV_19
3609   *         @arg @ref LL_RCC_RTC_HSE_DIV_20
3610   *         @arg @ref LL_RCC_RTC_HSE_DIV_21
3611   *         @arg @ref LL_RCC_RTC_HSE_DIV_22
3612   *         @arg @ref LL_RCC_RTC_HSE_DIV_23
3613   *         @arg @ref LL_RCC_RTC_HSE_DIV_24
3614   *         @arg @ref LL_RCC_RTC_HSE_DIV_25
3615   *         @arg @ref LL_RCC_RTC_HSE_DIV_26
3616   *         @arg @ref LL_RCC_RTC_HSE_DIV_27
3617   *         @arg @ref LL_RCC_RTC_HSE_DIV_28
3618   *         @arg @ref LL_RCC_RTC_HSE_DIV_29
3619   *         @arg @ref LL_RCC_RTC_HSE_DIV_30
3620   *         @arg @ref LL_RCC_RTC_HSE_DIV_31
3621   *         @arg @ref LL_RCC_RTC_HSE_DIV_32
3622   *         @arg @ref LL_RCC_RTC_HSE_DIV_33
3623   *         @arg @ref LL_RCC_RTC_HSE_DIV_34
3624   *         @arg @ref LL_RCC_RTC_HSE_DIV_35
3625   *         @arg @ref LL_RCC_RTC_HSE_DIV_36
3626   *         @arg @ref LL_RCC_RTC_HSE_DIV_37
3627   *         @arg @ref LL_RCC_RTC_HSE_DIV_38
3628   *         @arg @ref LL_RCC_RTC_HSE_DIV_39
3629   *         @arg @ref LL_RCC_RTC_HSE_DIV_40
3630   *         @arg @ref LL_RCC_RTC_HSE_DIV_41
3631   *         @arg @ref LL_RCC_RTC_HSE_DIV_42
3632   *         @arg @ref LL_RCC_RTC_HSE_DIV_43
3633   *         @arg @ref LL_RCC_RTC_HSE_DIV_44
3634   *         @arg @ref LL_RCC_RTC_HSE_DIV_45
3635   *         @arg @ref LL_RCC_RTC_HSE_DIV_46
3636   *         @arg @ref LL_RCC_RTC_HSE_DIV_47
3637   *         @arg @ref LL_RCC_RTC_HSE_DIV_48
3638   *         @arg @ref LL_RCC_RTC_HSE_DIV_49
3639   *         @arg @ref LL_RCC_RTC_HSE_DIV_50
3640   *         @arg @ref LL_RCC_RTC_HSE_DIV_51
3641   *         @arg @ref LL_RCC_RTC_HSE_DIV_52
3642   *         @arg @ref LL_RCC_RTC_HSE_DIV_53
3643   *         @arg @ref LL_RCC_RTC_HSE_DIV_54
3644   *         @arg @ref LL_RCC_RTC_HSE_DIV_55
3645   *         @arg @ref LL_RCC_RTC_HSE_DIV_56
3646   *         @arg @ref LL_RCC_RTC_HSE_DIV_57
3647   *         @arg @ref LL_RCC_RTC_HSE_DIV_58
3648   *         @arg @ref LL_RCC_RTC_HSE_DIV_59
3649   *         @arg @ref LL_RCC_RTC_HSE_DIV_60
3650   *         @arg @ref LL_RCC_RTC_HSE_DIV_61
3651   *         @arg @ref LL_RCC_RTC_HSE_DIV_62
3652   *         @arg @ref LL_RCC_RTC_HSE_DIV_63
3653   *         @arg @ref LL_RCC_RTC_HSE_DIV_64
3654   * @retval None
3655   */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)3656 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
3657 {
3658   MODIFY_REG(RCC->RTCDIVR, RCC_RTCDIVR_RTCDIV, Prescaler);
3659 }
3660 
3661 /**
3662   * @brief  Get HSE Prescalers for RTC Clock
3663   * @rmtoll RTCDIVR         RTCDIV        LL_RCC_GetRTC_HSEPrescaler
3664   * @retval Returned value can be one of the following values:
3665   *         @arg @ref LL_RCC_RTC_HSE_DIV_1
3666   *         @arg @ref LL_RCC_RTC_HSE_DIV_2
3667   *         @arg @ref LL_RCC_RTC_HSE_DIV_3
3668   *         @arg @ref LL_RCC_RTC_HSE_DIV_4
3669   *         @arg @ref LL_RCC_RTC_HSE_DIV_5
3670   *         @arg @ref LL_RCC_RTC_HSE_DIV_6
3671   *         @arg @ref LL_RCC_RTC_HSE_DIV_7
3672   *         @arg @ref LL_RCC_RTC_HSE_DIV_8
3673   *         @arg @ref LL_RCC_RTC_HSE_DIV_9
3674   *         @arg @ref LL_RCC_RTC_HSE_DIV_10
3675   *         @arg @ref LL_RCC_RTC_HSE_DIV_11
3676   *         @arg @ref LL_RCC_RTC_HSE_DIV_12
3677   *         @arg @ref LL_RCC_RTC_HSE_DIV_13
3678   *         @arg @ref LL_RCC_RTC_HSE_DIV_14
3679   *         @arg @ref LL_RCC_RTC_HSE_DIV_15
3680   *         @arg @ref LL_RCC_RTC_HSE_DIV_16
3681   *         @arg @ref LL_RCC_RTC_HSE_DIV_17
3682   *         @arg @ref LL_RCC_RTC_HSE_DIV_18
3683   *         @arg @ref LL_RCC_RTC_HSE_DIV_19
3684   *         @arg @ref LL_RCC_RTC_HSE_DIV_20
3685   *         @arg @ref LL_RCC_RTC_HSE_DIV_21
3686   *         @arg @ref LL_RCC_RTC_HSE_DIV_22
3687   *         @arg @ref LL_RCC_RTC_HSE_DIV_23
3688   *         @arg @ref LL_RCC_RTC_HSE_DIV_24
3689   *         @arg @ref LL_RCC_RTC_HSE_DIV_25
3690   *         @arg @ref LL_RCC_RTC_HSE_DIV_26
3691   *         @arg @ref LL_RCC_RTC_HSE_DIV_27
3692   *         @arg @ref LL_RCC_RTC_HSE_DIV_28
3693   *         @arg @ref LL_RCC_RTC_HSE_DIV_29
3694   *         @arg @ref LL_RCC_RTC_HSE_DIV_30
3695   *         @arg @ref LL_RCC_RTC_HSE_DIV_31
3696   *         @arg @ref LL_RCC_RTC_HSE_DIV_32
3697   *         @arg @ref LL_RCC_RTC_HSE_DIV_33
3698   *         @arg @ref LL_RCC_RTC_HSE_DIV_34
3699   *         @arg @ref LL_RCC_RTC_HSE_DIV_35
3700   *         @arg @ref LL_RCC_RTC_HSE_DIV_36
3701   *         @arg @ref LL_RCC_RTC_HSE_DIV_37
3702   *         @arg @ref LL_RCC_RTC_HSE_DIV_38
3703   *         @arg @ref LL_RCC_RTC_HSE_DIV_39
3704   *         @arg @ref LL_RCC_RTC_HSE_DIV_40
3705   *         @arg @ref LL_RCC_RTC_HSE_DIV_41
3706   *         @arg @ref LL_RCC_RTC_HSE_DIV_42
3707   *         @arg @ref LL_RCC_RTC_HSE_DIV_43
3708   *         @arg @ref LL_RCC_RTC_HSE_DIV_44
3709   *         @arg @ref LL_RCC_RTC_HSE_DIV_45
3710   *         @arg @ref LL_RCC_RTC_HSE_DIV_46
3711   *         @arg @ref LL_RCC_RTC_HSE_DIV_47
3712   *         @arg @ref LL_RCC_RTC_HSE_DIV_48
3713   *         @arg @ref LL_RCC_RTC_HSE_DIV_49
3714   *         @arg @ref LL_RCC_RTC_HSE_DIV_50
3715   *         @arg @ref LL_RCC_RTC_HSE_DIV_51
3716   *         @arg @ref LL_RCC_RTC_HSE_DIV_52
3717   *         @arg @ref LL_RCC_RTC_HSE_DIV_53
3718   *         @arg @ref LL_RCC_RTC_HSE_DIV_54
3719   *         @arg @ref LL_RCC_RTC_HSE_DIV_55
3720   *         @arg @ref LL_RCC_RTC_HSE_DIV_56
3721   *         @arg @ref LL_RCC_RTC_HSE_DIV_57
3722   *         @arg @ref LL_RCC_RTC_HSE_DIV_58
3723   *         @arg @ref LL_RCC_RTC_HSE_DIV_59
3724   *         @arg @ref LL_RCC_RTC_HSE_DIV_60
3725   *         @arg @ref LL_RCC_RTC_HSE_DIV_61
3726   *         @arg @ref LL_RCC_RTC_HSE_DIV_62
3727   *         @arg @ref LL_RCC_RTC_HSE_DIV_63
3728   *         @arg @ref LL_RCC_RTC_HSE_DIV_64
3729   */
LL_RCC_GetRTC_HSEPrescaler(void)3730 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
3731 {
3732   return (uint32_t)(READ_BIT(RCC->RTCDIVR, RCC_RTCDIVR_RTCDIV));
3733 }
3734 
3735 /**
3736   * @}
3737   */
3738 
3739 /** @defgroup RCC_LL_EF_TIMGx_CLOCK_PRESCALER TIMGx
3740   * @{
3741   */
3742 
3743 /**
3744   * @brief  Configure TIMGx prescaler selection
3745   * @rmtoll TIMG1PRER      TIMG1PRE      LL_RCC_SetTIMGPrescaler\n
3746   *         TIMG2PRER      TIMG2PRE      LL_RCC_SetTIMGPrescaler
3747   * @param  PreSelection This parameter can be one of the following values:
3748   *         @arg @ref LL_RCC_TIMG1PRES_DEACTIVATED
3749   *         @arg @ref LL_RCC_TIMG1PRES_ACTIVATED
3750   *         @arg @ref LL_RCC_TIMG2PRES_DEACTIVATED
3751   *         @arg @ref LL_RCC_TIMG2PRES_ACTIVATED
3752   * @retval None
3753   */
LL_RCC_SetTIMGPrescaler(uint32_t PreSelection)3754 __STATIC_INLINE void LL_RCC_SetTIMGPrescaler(uint32_t PreSelection)
3755 {
3756   LL_RCC_SetClockSource(PreSelection);
3757 }
3758 
3759 /**
3760   * @brief  Get TIMGx prescaler selection
3761   * @rmtoll TIMG1PRER      TIMG1PRE      LL_RCC_GetTIMGPrescaler\n
3762   *         TIMG2PRER      TIMG2PRE      LL_RCC_GetTIMGPrescaler
3763   * @param  TIMGroup This parameter can be one of the following values:
3764   *         @arg @ref LL_RCC_TIMG1PRES
3765   *         @arg @ref LL_RCC_TIMG2PRES
3766   * @retval Returned value can be one of the following values:
3767   *         @arg @ref LL_RCC_TIMG1PRES_DEACTIVATED
3768   *         @arg @ref LL_RCC_TIMG1PRES_ACTIVATED
3769   *         @arg @ref LL_RCC_TIMG2PRES_DEACTIVATED
3770   *         @arg @ref LL_RCC_TIMG2PRES_ACTIVATED
3771   */
LL_RCC_GetTIMGPrescaler(uint32_t TIMGroup)3772 __STATIC_INLINE uint32_t LL_RCC_GetTIMGPrescaler(uint32_t TIMGroup)
3773 {
3774   return LL_RCC_GetClockSource(TIMGroup);
3775 }
3776 
3777 /**
3778   * @}
3779   */
3780 
3781 /** @defgroup RCC_LL_EF_MCO MCO
3782   * @{
3783   */
3784 
3785 /**
3786   * @brief  Configure MCOx
3787   * @rmtoll MCO1CFGR         MCO1SEL        LL_RCC_ConfigMCO\n
3788   *         MCO1CFGR         MCO1DIV        LL_RCC_ConfigMCO\n
3789   *         MCO2CFGR         MCO2SEL        LL_RCC_ConfigMCO\n
3790   *         MCO2CFGR         MCO2DIV        LL_RCC_ConfigMCO
3791   * @param  MCOxSource This parameter can be one of the following values:
3792   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
3793   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
3794   *         @arg @ref LL_RCC_MCO1SOURCE_CSI
3795   *         @arg @ref LL_RCC_MCO1SOURCE_LSI
3796   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
3797   *         @arg @ref LL_RCC_MCO2SOURCE_MPU
3798   *         @arg @ref LL_RCC_MCO2SOURCE_AXI
3799   *         @arg @ref LL_RCC_MCO2SOURCE_MCU
3800   *         @arg @ref LL_RCC_MCO2SOURCE_PLL4
3801   *         @arg @ref LL_RCC_MCO2SOURCE_HSE
3802   *         @arg @ref LL_RCC_MCO2SOURCE_HSI
3803   * @param  MCOxPrescaler This parameter can be one of the following values:
3804   *         @arg @ref LL_RCC_MCO1_DIV_1
3805   *         @arg @ref LL_RCC_MCO1_DIV_2
3806   *         @arg @ref LL_RCC_MCO1_DIV_3
3807   *         @arg @ref LL_RCC_MCO1_DIV_4
3808   *         @arg @ref LL_RCC_MCO1_DIV_5
3809   *         @arg @ref LL_RCC_MCO1_DIV_6
3810   *         @arg @ref LL_RCC_MCO1_DIV_7
3811   *         @arg @ref LL_RCC_MCO1_DIV_8
3812   *         @arg @ref LL_RCC_MCO1_DIV_9
3813   *         @arg @ref LL_RCC_MCO1_DIV_10
3814   *         @arg @ref LL_RCC_MCO1_DIV_11
3815   *         @arg @ref LL_RCC_MCO1_DIV_12
3816   *         @arg @ref LL_RCC_MCO1_DIV_13
3817   *         @arg @ref LL_RCC_MCO1_DIV_14
3818   *         @arg @ref LL_RCC_MCO1_DIV_15
3819   *         @arg @ref LL_RCC_MCO1_DIV_16
3820   *         @arg @ref LL_RCC_MCO2_DIV_1
3821   *         @arg @ref LL_RCC_MCO2_DIV_2
3822   *         @arg @ref LL_RCC_MCO2_DIV_3
3823   *         @arg @ref LL_RCC_MCO2_DIV_4
3824   *         @arg @ref LL_RCC_MCO2_DIV_5
3825   *         @arg @ref LL_RCC_MCO2_DIV_6
3826   *         @arg @ref LL_RCC_MCO2_DIV_7
3827   *         @arg @ref LL_RCC_MCO2_DIV_8
3828   *         @arg @ref LL_RCC_MCO2_DIV_9
3829   *         @arg @ref LL_RCC_MCO2_DIV_10
3830   *         @arg @ref LL_RCC_MCO2_DIV_11
3831   *         @arg @ref LL_RCC_MCO2_DIV_12
3832   *         @arg @ref LL_RCC_MCO2_DIV_13
3833   *         @arg @ref LL_RCC_MCO2_DIV_14
3834   *         @arg @ref LL_RCC_MCO2_DIV_15
3835   *         @arg @ref LL_RCC_MCO2_DIV_16
3836   * @retval None
3837   */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)3838 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
3839 {
3840   LL_RCC_SetClockSource(MCOxSource);
3841 
3842   /* Set MCOx prescaler */
3843   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)&RCC->I2C46CKSELR + LL_CLKSOURCE_REG(MCOxSource));
3844   /* RCC_MCO1CFGR_MCO1DIV and RCC_MCO2CFGR_MCO2DIV are the same value */
3845   MODIFY_REG(*pReg, RCC_MCO1CFGR_MCO1DIV, MCOxPrescaler);
3846 }
3847 
3848 /**
3849   * @}
3850   */
3851 
3852 /** @defgroup RCC_LL_EF_PLL PLL
3853   * @{
3854   */
3855 
3856 /**
3857   * @brief  Set the oscillator used as PLL1 and PLL2 clock source.
3858   * @note   PLLSRC can be written only when all PLL1 and PLL2 are disabled.
3859   * @rmtoll RCK12SELR      PLL12SRC        LL_RCC_PLL12_SetSource
3860   * @param  PLLSource parameter can be one of the following values:
3861   *         @arg @ref LL_RCC_PLL12SOURCE_HSI
3862   *         @arg @ref LL_RCC_PLL12SOURCE_HSE
3863   *         @arg @ref LL_RCC_PLL12SOURCE_NONE
3864   * @retval None
3865   */
LL_RCC_PLL12_SetSource(uint32_t PLLSource)3866 __STATIC_INLINE void LL_RCC_PLL12_SetSource(uint32_t PLLSource)
3867 {
3868   MODIFY_REG(RCC->RCK12SELR, RCC_RCK12SELR_PLL12SRC, PLLSource);
3869 }
3870 
3871 /**
3872   * @brief  Get the oscillator used as PLL1 and PLL2 clock source.
3873   * @rmtoll RCK12SELR      PLL12SRC        LL_RCC_PLL12_GetSource
3874   * @retval Returned value can be one of the following values:
3875   *         @arg @ref LL_RCC_PLL12SOURCE_HSI
3876   *         @arg @ref LL_RCC_PLL12SOURCE_HSE
3877   *         @arg @ref LL_RCC_PLL12SOURCE_NONE
3878   */
LL_RCC_PLL12_GetSource(void)3879 __STATIC_INLINE uint32_t LL_RCC_PLL12_GetSource(void)
3880 {
3881   return (uint32_t)(READ_BIT(RCC->RCK12SELR, RCC_RCK12SELR_PLL12SRC));
3882 }
3883 
3884 /**
3885   * @brief  Enable PLL1
3886   * @rmtoll PLL1CR           PLLON         LL_RCC_PLL1_Enable
3887   * @retval None
3888   */
LL_RCC_PLL1_Enable(void)3889 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
3890 {
3891   SET_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON);
3892 }
3893 
3894 /**
3895   * @brief  Disable PLL1
3896   * @note Cannot be disabled if the PLL clock is used as a system clock.
3897   *       This API shall be called only when PLL1 DIVPEN, DIVQEN and
3898   *       DIVREN are disabled.
3899   * @rmtoll PLL1CR           PLLON         LL_RCC_PLL1_Disable
3900   * @retval None
3901   */
LL_RCC_PLL1_Disable(void)3902 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
3903 {
3904   CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON);
3905 }
3906 
3907 /**
3908   * @brief  Check if PLL1 Ready
3909   * @rmtoll PLL1CR           PLL1RDY        LL_RCC_PLL1_IsReady
3910   * @retval State of bit (1 or 0).
3911   */
LL_RCC_PLL1_IsReady(void)3912 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
3913 {
3914   return ((READ_BIT(RCC->PLL1CR, RCC_PLL1CR_PLL1RDY) == RCC_PLL1CR_PLL1RDY) ? 1UL : 0UL);
3915 }
3916 
3917 /**
3918   * @brief  Enable PLL1P
3919   * @note   This API shall be called only when PLL1 is enabled and ready.
3920   * @rmtoll PLL1CR           DIVPEN         LL_RCC_PLL1P_Enable
3921   * @retval None
3922   */
LL_RCC_PLL1P_Enable(void)3923 __STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
3924 {
3925   SET_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
3926 }
3927 
3928 /**
3929   * @brief  Enable PLL1 FRACV
3930   * @rmtoll PLL1FRACR           FRACLE         LL_RCC_PLL1FRACV_Enable
3931   * @retval None
3932   */
LL_RCC_PLL1FRACV_Enable(void)3933 __STATIC_INLINE void LL_RCC_PLL1FRACV_Enable(void)
3934 {
3935   SET_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE);
3936 }
3937 
3938 /**
3939   * @brief  Enable PLL1 Clock Spreading Generator
3940   * @rmtoll PLL1CR           SSCG_CTRL         LL_RCC_PLL1CSG_Enable
3941   * @retval None
3942   */
LL_RCC_PLL1CSG_Enable(void)3943 __STATIC_INLINE void LL_RCC_PLL1CSG_Enable(void)
3944 {
3945   SET_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL);
3946 }
3947 
3948 /**
3949   * @brief  Check if PLL1 P is enabled
3950   * @rmtoll PLL1CR           DIVPEN         LL_RCC_PLL1P_IsEnabled
3951   * @retval State of bit (1 or 0).
3952   */
LL_RCC_PLL1P_IsEnabled(void)3953 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
3954 {
3955   return (uint32_t)((READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) == RCC_PLL1CR_DIVPEN) ? 1UL : 0UL);
3956 }
3957 
3958 /**
3959   * @brief  Check if PLL1 FRACV is enabled
3960   * @rmtoll PLL1FRACR           FRACLE         LL_RCC_PLL1FRACV_IsEnabled
3961   * @retval State of bit (1 or 0).
3962   */
LL_RCC_PLL1FRACV_IsEnabled(void)3963 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACV_IsEnabled(void)
3964 {
3965   return (uint32_t)((READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE) == RCC_PLL1FRACR_FRACLE) ? 1UL : 0UL);
3966 }
3967 
3968 /**
3969   * @brief  Check if PLL1 Clock Spreading Generator is enabled
3970   * @rmtoll PLL1CR           SSCG_CTRL         LL_RCC_PLL1CSG_IsEnabled
3971   * @retval None
3972   */
LL_RCC_PLL1CSG_IsEnabled(void)3973 __STATIC_INLINE uint32_t LL_RCC_PLL1CSG_IsEnabled(void)
3974 {
3975   return (uint32_t)((READ_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL) == RCC_PLL1CR_SSCG_CTRL) ? 1UL : 0UL);
3976 }
3977 
3978 /**
3979   * @brief  Disable PLL1P
3980   * @rmtoll PLL1CR           DIVPEN         LL_RCC_PLL1P_Disable
3981   * @retval None
3982   */
LL_RCC_PLL1P_Disable(void)3983 __STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
3984 {
3985   CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
3986 }
3987 
3988 /**
3989   * @brief  Disable PLL1 FRACV
3990   * @rmtoll PLL1FRACR           FRACLE         LL_RCC_PLL1FRACV_Disable
3991   * @retval None
3992   */
LL_RCC_PLL1FRACV_Disable(void)3993 __STATIC_INLINE void LL_RCC_PLL1FRACV_Disable(void)
3994 {
3995   CLEAR_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE);
3996 }
3997 
3998 /**
3999   * @brief  Disable PLL1 Clock Spreading Generator
4000   * @rmtoll PLL1CR           SSCG_CTRL         LL_RCC_PLL1CSG_Disable
4001   * @retval None
4002   */
LL_RCC_PLL1CSG_Disable(void)4003 __STATIC_INLINE void LL_RCC_PLL1CSG_Disable(void)
4004 {
4005   CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL);
4006 }
4007 
4008 /**
4009   * @brief  Get PLL1 N Coefficient
4010   * @rmtoll PLL1CFGR1        DIVN          LL_RCC_PLL1_GetN
4011   * @retval A value between 4 and 512
4012   */
LL_RCC_PLL1_GetN(void)4013 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
4014 {
4015   return (uint32_t)((READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_DIVN) >>  RCC_PLL1CFGR1_DIVN_Pos) + 1U);
4016 }
4017 
4018 /**
4019   * @brief  Get PLL1 M Coefficient
4020   * @rmtoll PLL1CFGR1       DIVM1          LL_RCC_PLL1_GetM
4021   * @retval A value between 1 and 64
4022   */
LL_RCC_PLL1_GetM(void)4023 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
4024 {
4025   return (uint32_t)((READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_DIVM1) >>  RCC_PLL1CFGR1_DIVM1_Pos) + 1U);
4026 }
4027 
4028 /**
4029   * @brief  Get PLL1 P Coefficient
4030   * @rmtoll PLL1CFGR2        DIVP          LL_RCC_PLL1_GetP
4031   * @retval A value between 1 and 128
4032   */
LL_RCC_PLL1_GetP(void)4033 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
4034 {
4035   return (uint32_t)((READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_DIVP) >>  RCC_PLL1CFGR2_DIVP_Pos) + 1U);
4036 }
4037 
4038 /**
4039   * @brief  Get PLL1 FRACV Coefficient
4040   * @rmtoll PLL1FRACR      FRACV          LL_RCC_PLL1_GetFRACV
4041   * @retval A value between 0 and 8191 (0x1FFF)
4042   */
LL_RCC_PLL1_GetFRACV(void)4043 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACV(void)
4044 {
4045   return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACV) >>  RCC_PLL1FRACR_FRACV_Pos);
4046 }
4047 
4048 /**
4049   * @brief  Set PLL1 N Coefficient
4050   * @note   This API shall be called only when PLL1 is disabled.
4051   * @rmtoll PLL1CFGR1        DIVN          LL_RCC_PLL1_SetN
4052   * @param  DIVN parameter can be a value between 4 and 512
4053   */
LL_RCC_PLL1_SetN(uint32_t DIVN)4054 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t DIVN)
4055 {
4056   MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_DIVN, (DIVN - 1U) << RCC_PLL1CFGR1_DIVN_Pos);
4057 }
4058 
4059 /**
4060   * @brief  Set PLL1 M Coefficient
4061   * @note   This API shall be called only when PLL1 is disabled.
4062   * @rmtoll PLL1CFGR1       DIVM1          LL_RCC_PLL1_SetM
4063   * @param  DIVM1 parameter can be a value between 1 and 64
4064   */
LL_RCC_PLL1_SetM(uint32_t DIVM1)4065 __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t DIVM1)
4066 {
4067   MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_DIVM1, (DIVM1 - 1U) << RCC_PLL1CFGR1_DIVM1_Pos);
4068 }
4069 
4070 /**
4071   * @brief  Set PLL1 P Coefficient
4072   * @rmtoll PLL1CFGR2        DIVP          LL_RCC_PLL1_SetP
4073   * @param  DIVP parameter can be a value between 1 and 128
4074   */
LL_RCC_PLL1_SetP(uint32_t DIVP)4075 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t DIVP)
4076 {
4077   MODIFY_REG(RCC->PLL1CFGR2, RCC_PLL1CFGR2_DIVP, (DIVP - 1U) << RCC_PLL1CFGR2_DIVP_Pos);
4078 }
4079 
4080 /**
4081   * @brief  Set PLL1 FRACV Coefficient
4082   * @rmtoll PLL1FRACR        FRACV          LL_RCC_PLL1_SetFRACV
4083   * @param  FRACV parameter can be a value between 0 and 8191 (0x1FFF)
4084   */
LL_RCC_PLL1_SetFRACV(uint32_t FRACV)4085 __STATIC_INLINE void LL_RCC_PLL1_SetFRACV(uint32_t FRACV)
4086 {
4087   MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACV, FRACV << RCC_PLL1FRACR_FRACV_Pos);
4088 }
4089 
4090 /** @brief  Configure the PLL1 Clock Spreading Generator
4091   * @rmtoll PLL1CSGR    MOD_PER, TPDFN_DIS, RPDFN_DIS, SSCG_MODE, INC_STEP  LL_RCC_PLL1_ConfigCSG
4092   *
4093   * @param  ModPeriod: Modulation Period Adjustment for PLL1
4094   *         This parameter must have a value between 1 and 8191
4095   *
4096   * @param  TPDFN
4097   *         This parameter can be one of the following values:
4098   *         @arg @ref LL_RCC_PLL1TPDFN_DIS_ENABLED
4099   *         @arg @ref LL_RCC_PLL1TPDFN_DIS_DISABLED
4100 
4101   * @param  RPDFN
4102   *         This parameter can be one of the following values:
4103   *         @arg @ref LL_RCC_PLL1RPDFN_DIS_ENABLED
4104   *         @arg @ref LL_RCC_PLL1RPDFN_DIS_DISABLED
4105   *
4106   * @param  SSCGMode
4107   *         This parameter can be one of the following values:
4108   *         @arg @ref LL_RCC_PLL1SSCG_CENTER_SPREAD
4109   *         @arg @ref LL_RCC_PLL1SSCG_DOWN_SPREAD
4110   *
4111   * @param  IncStep: Modulation Depth Adjustment for PLL1
4112   *         This parameter must have a value between 1 and 32767
4113   * @note   ModPeriod x IncStep shall not exceed (2^15)-1
4114   * @retval None
4115   */
LL_RCC_PLL1_ConfigCSG(uint32_t ModPeriod,uint32_t TPDFN,uint32_t RPDFN,uint32_t SSCGMode,uint32_t IncStep)4116 __STATIC_INLINE void LL_RCC_PLL1_ConfigCSG(uint32_t ModPeriod, uint32_t TPDFN, uint32_t RPDFN, uint32_t SSCGMode, uint32_t IncStep)
4117 {
4118   MODIFY_REG(RCC->PLL1CSGR, (RCC_PLL1CSGR_MOD_PER | RCC_PLL1CSGR_TPDFN_DIS | RCC_PLL1CSGR_RPDFN_DIS | \
4119                              RCC_PLL1CSGR_SSCG_MODE | RCC_PLL1CSGR_INC_STEP), \
4120              (ModPeriod | TPDFN | RPDFN | SSCGMode | (IncStep << RCC_PLL1CSGR_INC_STEP_Pos)));
4121 }
4122 
4123 /**
4124   * @brief  Enable PLL2
4125   * @rmtoll PLL2CR           PLLON         LL_RCC_PLL2_Enable
4126   * @retval None
4127   */
LL_RCC_PLL2_Enable(void)4128 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
4129 {
4130   SET_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON);
4131 }
4132 
4133 /**
4134   * @brief  Disable PLL2
4135   * @note Cannot be disabled if the PLL clock is used as a system clock.
4136   *       This API shall be called only when PLL1 DIVPEN, DIVQEN and DIVREN
4137   *       are disabled.
4138   * @rmtoll PLL2CR           PLLON         LL_RCC_PLL2_Disable
4139   * @retval None
4140   */
LL_RCC_PLL2_Disable(void)4141 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
4142 {
4143   CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON);
4144 }
4145 
4146 /**
4147   * @brief  Check if PLL2 Ready
4148   * @rmtoll PLL2CR           PLL2RDY        LL_RCC_PLL2_IsReady
4149   * @retval State of bit (1 or 0).
4150   */
LL_RCC_PLL2_IsReady(void)4151 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
4152 {
4153   return ((READ_BIT(RCC->PLL2CR, RCC_PLL2CR_PLL2RDY) == RCC_PLL2CR_PLL2RDY) ? 1UL : 0UL);
4154 }
4155 
4156 /**
4157   * @brief  Enable PLL2P
4158   * @note   This API shall be called only when PLL2 is enabled and ready.
4159   * @rmtoll PLL2CR           DIVPEN         LL_RCC_PLL2P_Enable
4160   * @retval None
4161   */
LL_RCC_PLL2P_Enable(void)4162 __STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
4163 {
4164   SET_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVPEN);
4165 }
4166 
4167 /**
4168   * @brief  Enable PLL2Q
4169   * @note   This API shall be called only when PLL2 is enabled and ready.
4170   * @rmtoll PLL2CR           DIVQEN         LL_RCC_PLL2Q_Enable
4171   * @retval None
4172   */
LL_RCC_PLL2Q_Enable(void)4173 __STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
4174 {
4175   SET_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVQEN);
4176 }
4177 
4178 /**
4179   * @brief  Enable PLL2R
4180   * @note   This API shall be called only when PLL2 is enabled and ready.
4181   * @rmtoll PLL2CR           DIVREN         LL_RCC_PLL2R_Enable
4182   * @retval None
4183   */
LL_RCC_PLL2R_Enable(void)4184 __STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
4185 {
4186   SET_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVREN);
4187 }
4188 
4189 /**
4190   * @brief  Enable PLL2 FRACV
4191   * @rmtoll PLL2FRACR           FRACLE         LL_RCC_PLL2FRACV_Enable
4192   * @retval None
4193   */
LL_RCC_PLL2FRACV_Enable(void)4194 __STATIC_INLINE void LL_RCC_PLL2FRACV_Enable(void)
4195 {
4196   SET_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACLE);
4197 }
4198 
4199 /**
4200   * @brief  Enable PLL2 Clock Spreading Generator
4201   * @rmtoll PLL2CR           SSCG_CTRL         LL_RCC_PLL2CSG_Enable
4202   * @retval None
4203   */
LL_RCC_PLL2CSG_Enable(void)4204 __STATIC_INLINE void LL_RCC_PLL2CSG_Enable(void)
4205 {
4206   SET_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL);
4207 }
4208 
4209 /**
4210   * @brief  Check if PLL2 P is enabled
4211   * @rmtoll PLL2CR           DIVPEN         LL_RCC_PLL2P_IsEnabled
4212   * @retval State of bit (1 or 0).
4213   */
LL_RCC_PLL2P_IsEnabled(void)4214 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
4215 {
4216   return (uint32_t)((READ_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVPEN) == RCC_PLL2CR_DIVPEN) ? 1UL : 0UL);
4217 }
4218 
4219 /**
4220   * @brief  Check if PLL2 Q is enabled
4221   * @rmtoll PLL2CR           DIVQEN         LL_RCC_PLL2Q_IsEnabled
4222   * @retval State of bit (1 or 0).
4223   */
LL_RCC_PLL2Q_IsEnabled(void)4224 __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
4225 {
4226   return (uint32_t)((READ_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVQEN) == RCC_PLL2CR_DIVQEN) ? 1UL : 0UL);
4227 }
4228 
4229 /**
4230   * @brief  Check if PLL2 R is enabled
4231   * @rmtoll PLL2CR           DIVREN         LL_RCC_PLL2R_IsEnabled
4232   * @retval State of bit (1 or 0).
4233   */
LL_RCC_PLL2R_IsEnabled(void)4234 __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
4235 {
4236   return (uint32_t)((READ_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVREN) == RCC_PLL2CR_DIVREN) ? 1UL : 0UL);
4237 }
4238 
4239 /**
4240   * @brief  Check if PLL2 FRACV is enabled
4241   * @rmtoll PLL2FRACR           FRACLE         LL_RCC_PLL2FRACV_IsEnabled
4242   * @retval State of bit (1 or 0).
4243   */
LL_RCC_PLL2FRACV_IsEnabled(void)4244 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACV_IsEnabled(void)
4245 {
4246   return (uint32_t)((READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACLE) == RCC_PLL2FRACR_FRACLE) ? 1UL : 0UL);
4247 }
4248 
4249 /**
4250   * @brief  Check if PLL2 Clock Spreading Generator is enabled
4251   * @rmtoll PLL2CR           SSCG_CTRL         LL_RCC_PLL2CSG_IsEnabled
4252   * @retval None
4253   */
LL_RCC_PLL2CSG_IsEnabled(void)4254 __STATIC_INLINE uint32_t LL_RCC_PLL2CSG_IsEnabled(void)
4255 {
4256   return (uint32_t)((READ_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL) == RCC_PLL2CR_SSCG_CTRL) ? 1UL : 0UL);
4257 }
4258 
4259 /**
4260   * @brief  Disable PLL2P
4261   * @rmtoll PLL2CR           DIVPEN         LL_RCC_PLL2P_Disable
4262   * @retval None
4263   */
LL_RCC_PLL2P_Disable(void)4264 __STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
4265 {
4266   CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVPEN);
4267 }
4268 
4269 /**
4270   * @brief  Disable PLL2Q
4271   * @rmtoll PLL2CR           DIVQEN         LL_RCC_PLL2Q_Disable
4272   * @retval None
4273   */
LL_RCC_PLL2Q_Disable(void)4274 __STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
4275 {
4276   CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVQEN);
4277 }
4278 
4279 /**
4280   * @brief  Disable PLL2R
4281   * @rmtoll PLL2CR           DIVREN         LL_RCC_PLL2R_Disable
4282   * @retval None
4283   */
LL_RCC_PLL2R_Disable(void)4284 __STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
4285 {
4286   CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVREN);
4287 }
4288 
4289 /**
4290   * @brief  Disable PLL2 FRACV
4291   * @rmtoll PLL2FRACR           FRACLE         LL_RCC_PLL2FRACV_Disable
4292   * @retval None
4293   */
LL_RCC_PLL2FRACV_Disable(void)4294 __STATIC_INLINE void LL_RCC_PLL2FRACV_Disable(void)
4295 {
4296   CLEAR_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACLE);
4297 }
4298 
4299 /**
4300   * @brief  Disable PLL2 Clock Spreading Generator
4301   * @rmtoll PLL2CR           SSCG_CTRL         LL_RCC_PLL2CSG_Disable
4302   * @retval None
4303   */
LL_RCC_PLL2CSG_Disable(void)4304 __STATIC_INLINE void LL_RCC_PLL2CSG_Disable(void)
4305 {
4306   CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL);
4307 }
4308 
4309 /**
4310   * @brief  Get PLL2 N Coefficient
4311   * @rmtoll PLL2CFGR1        DIVN          LL_RCC_PLL2_GetN
4312   * @retval A value between 4 and 512
4313   */
LL_RCC_PLL2_GetN(void)4314 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
4315 {
4316   return (uint32_t)((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_DIVN) >>  RCC_PLL2CFGR1_DIVN_Pos) + 1U);
4317 }
4318 
4319 /**
4320   * @brief  Get PLL2 M Coefficient
4321   * @rmtoll PLL2CFGR1       DIVM2          LL_RCC_PLL2_GetM
4322   * @retval A value between 1 and 64
4323   */
LL_RCC_PLL2_GetM(void)4324 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
4325 {
4326   return (uint32_t)((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_DIVM2) >>  RCC_PLL2CFGR1_DIVM2_Pos) + 1U);
4327 }
4328 
4329 /**
4330   * @brief  Get PLL2 P Coefficient
4331   * @rmtoll PLL2CFGR2        DIVP          LL_RCC_PLL2_GetP
4332   * @retval A value between 1 and 128
4333   */
LL_RCC_PLL2_GetP(void)4334 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
4335 {
4336   return (uint32_t)((READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_DIVP) >>  RCC_PLL2CFGR2_DIVP_Pos) + 1U);
4337 }
4338 
4339 /**
4340   * @brief  Get PLL2 Q Coefficient
4341   * @rmtoll PLL2CFGR2        DIVQ          LL_RCC_PLL2_GetQ
4342   * @retval A value between 1 and 128
4343   */
LL_RCC_PLL2_GetQ(void)4344 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
4345 {
4346   return (uint32_t)((READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_DIVQ) >>  RCC_PLL2CFGR2_DIVQ_Pos) + 1U);
4347 }
4348 
4349 /**
4350   * @brief  Get PLL2 R Coefficient
4351   * @rmtoll PLL2CFGR2        DIVR          LL_RCC_PLL2_GetR
4352   * @retval A value between 1 and 128
4353   */
LL_RCC_PLL2_GetR(void)4354 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
4355 {
4356   return (uint32_t)((READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_DIVR) >>  RCC_PLL2CFGR2_DIVR_Pos) + 1U);
4357 }
4358 
4359 /**
4360   * @brief  Get PLL2 FRACV Coefficient
4361   * @rmtoll PLL2FRACR      FRACV          LL_RCC_PLL2_GetFRACV
4362   * @retval A value between 0 and 8191 (0x1FFF)
4363   */
LL_RCC_PLL2_GetFRACV(void)4364 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACV(void)
4365 {
4366   return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACV) >>  RCC_PLL2FRACR_FRACV_Pos);
4367 }
4368 
4369 /**
4370   * @brief  Set PLL2 N Coefficient
4371   * @note   This API shall be called only when PLL2 is disabled.
4372   * @rmtoll PLL2CFGR1        DIVN          LL_RCC_PLL2_SetN
4373   * @param  DIVN parameter can be a value between 4 and 512
4374   */
LL_RCC_PLL2_SetN(uint32_t DIVN)4375 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t DIVN)
4376 {
4377   MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_DIVN, (DIVN - 1U) << RCC_PLL2CFGR1_DIVN_Pos);
4378 }
4379 
4380 /**
4381   * @brief  Set PLL2 M Coefficient
4382   * @note   This API shall be called only when PLL2 is disabled.
4383   * @rmtoll PLL2CFGR1       DIVM2          LL_RCC_PLL2_SetM
4384   * @param  DIVM2 parameter can be a value between 1 and 64
4385   */
LL_RCC_PLL2_SetM(uint32_t DIVM2)4386 __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t DIVM2)
4387 {
4388   MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_DIVM2, (DIVM2 - 1U) << RCC_PLL2CFGR1_DIVM2_Pos);
4389 }
4390 
4391 /**
4392   * @brief  Set PLL2 P Coefficient
4393   * @rmtoll PLL2CFGR2        DIVP          LL_RCC_PLL2_SetP
4394   * @param  DIVP parameter can be a value between 1 and 128
4395   */
LL_RCC_PLL2_SetP(uint32_t DIVP)4396 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t DIVP)
4397 {
4398   MODIFY_REG(RCC->PLL2CFGR2, RCC_PLL2CFGR2_DIVP, (DIVP - 1U) << RCC_PLL2CFGR2_DIVP_Pos);
4399 }
4400 
4401 /**
4402   * @brief  Set PLL2 Q Coefficient
4403   * @rmtoll PLL2CFGR2        DIVQ          LL_RCC_PLL2_SetQ
4404   * @param  DIVQ parameter can be a value between 1 and 128
4405   */
LL_RCC_PLL2_SetQ(uint32_t DIVQ)4406 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t DIVQ)
4407 {
4408   MODIFY_REG(RCC->PLL2CFGR2, RCC_PLL2CFGR2_DIVQ, (DIVQ - 1U) << RCC_PLL2CFGR2_DIVQ_Pos);
4409 }
4410 
4411 /**
4412   * @brief  Set PLL2 R Coefficient
4413   * @rmtoll PLL2CFGR2        DIVR          LL_RCC_PLL2_SetR
4414   * @param  DIVR parameter can be a value between 1 and 128
4415   */
LL_RCC_PLL2_SetR(uint32_t DIVR)4416 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t DIVR)
4417 {
4418   MODIFY_REG(RCC->PLL2CFGR2, RCC_PLL2CFGR2_DIVR, (DIVR - 1U) << RCC_PLL2CFGR2_DIVR_Pos);
4419 }
4420 
4421 /**
4422   * @brief  Set PLL2 FRACV Coefficient
4423   * @rmtoll PLL2FRACR        FRACV          LL_RCC_PLL2_SetFRACV
4424   * @param  FRACV parameter can be a value between 0 and 8191 (0x1FFF)
4425   */
LL_RCC_PLL2_SetFRACV(uint32_t FRACV)4426 __STATIC_INLINE void LL_RCC_PLL2_SetFRACV(uint32_t FRACV)
4427 {
4428   MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACV, FRACV << RCC_PLL2FRACR_FRACV_Pos);
4429 }
4430 
4431 /** @brief  Configure the PLL2 Clock Spreading Generator
4432   * @rmtoll PLL2CSGR    MOD_PER, TPDFN_DIS, RPDFN_DIS, SSCG_MODE, INC_STEP  LL_RCC_PLL2_ConfigCSG
4433   *
4434   * @param  ModPeriod: Modulation Period Adjustment for PLL2
4435   *         This parameter must have a value between 1 and 8191
4436   *
4437   * @param  TPDFN
4438   *         This parameter can be one of the following values:
4439   *         @arg @ref LL_RCC_PLL2TPDFN_DIS_ENABLED
4440   *         @arg @ref LL_RCC_PLL2TPDFN_DIS_DISABLED
4441 
4442   * @param  RPDFN
4443   *         This parameter can be one of the following values:
4444   *         @arg @ref LL_RCC_PLL2RPDFN_DIS_ENABLED
4445   *         @arg @ref LL_RCC_PLL2RPDFN_DIS_DISABLED
4446   *
4447   * @param  SSCGMode
4448   *         This parameter can be one of the following values:
4449   *         @arg @ref LL_RCC_PLL2SSCG_CENTER_SPREAD
4450   *         @arg @ref LL_RCC_PLL2SSCG_DOWN_SPREAD
4451   *
4452   * @param  IncStep: Modulation Depth Adjustment for PLL2
4453   *         This parameter must have a value between 1 and 32767
4454   * @note   ModPeriod x IncStep shall not exceed (2^15)-1
4455   * @retval None
4456   */
LL_RCC_PLL2_ConfigCSG(uint32_t ModPeriod,uint32_t TPDFN,uint32_t RPDFN,uint32_t SSCGMode,uint32_t IncStep)4457 __STATIC_INLINE void LL_RCC_PLL2_ConfigCSG(uint32_t ModPeriod, uint32_t TPDFN, uint32_t RPDFN, uint32_t SSCGMode, uint32_t IncStep)
4458 {
4459   MODIFY_REG(RCC->PLL2CSGR, (RCC_PLL2CSGR_MOD_PER | RCC_PLL2CSGR_TPDFN_DIS | RCC_PLL2CSGR_RPDFN_DIS | \
4460                              RCC_PLL2CSGR_SSCG_MODE | RCC_PLL2CSGR_INC_STEP), \
4461              (ModPeriod | TPDFN | RPDFN | SSCGMode | (IncStep << RCC_PLL2CSGR_INC_STEP_Pos)));
4462 }
4463 
4464 /**
4465   * @brief  Set the oscillator used as PLL3 clock source.
4466   * @note   PLLSRC can be written only when all PLL3 is disabled.
4467   * @rmtoll RCK3SELR      PLL3SRC        LL_RCC_PLL3_SetSource
4468   * @param  PLLSource parameter can be one of the following values:
4469   *         @arg @ref LL_RCC_PLL3SOURCE_HSI
4470   *         @arg @ref LL_RCC_PLL3SOURCE_HSE
4471   *         @arg @ref LL_RCC_PLL3SOURCE_CSI
4472   *         @arg @ref LL_RCC_PLL3SOURCE_NONE
4473   * @retval None
4474   */
LL_RCC_PLL3_SetSource(uint32_t PLLSource)4475 __STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource)
4476 {
4477   MODIFY_REG(RCC->RCK3SELR, RCC_RCK3SELR_PLL3SRC, PLLSource);
4478 }
4479 
4480 /**
4481   * @brief  Get the oscillator used as PLL3 clock source.
4482   * @rmtoll RCK3SELR      PLL3SRC        LL_RCC_PLL3_GetSource
4483   * @retval Returned value can be one of the following values:
4484   *         @arg @ref LL_RCC_PLL3SOURCE_HSI
4485   *         @arg @ref LL_RCC_PLL3SOURCE_HSE
4486   *         @arg @ref LL_RCC_PLL3SOURCE_CSI
4487   *         @arg @ref LL_RCC_PLL3SOURCE_NONE
4488   */
LL_RCC_PLL3_GetSource(void)4489 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void)
4490 {
4491   return (uint32_t)(READ_BIT(RCC->RCK3SELR, RCC_RCK3SELR_PLL3SRC));
4492 }
4493 
4494 /**
4495   * @brief  Enable PLL3
4496   * @rmtoll PLL3CR           PLLON         LL_RCC_PLL3_Enable
4497   * @retval None
4498   */
LL_RCC_PLL3_Enable(void)4499 __STATIC_INLINE void LL_RCC_PLL3_Enable(void)
4500 {
4501   SET_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON);
4502 }
4503 
4504 /**
4505   * @brief  Disable PLL3
4506   * @note Cannot be disabled if the PLL clock is used as a system clock.
4507   *       This API shall be called only when PLL1 DIVPEN, DIVQEN and DIVREN are
4508   *       disabled.
4509   * @rmtoll PLL3CR           PLLON         LL_RCC_PLL3_Disable
4510   * @retval None
4511   */
LL_RCC_PLL3_Disable(void)4512 __STATIC_INLINE void LL_RCC_PLL3_Disable(void)
4513 {
4514   CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON);
4515 }
4516 
4517 /**
4518   * @brief  Check if PLL3 Ready
4519   * @rmtoll PLL3CR           PLL3RDY        LL_RCC_PLL3_IsReady
4520   * @retval State of bit (1 or 0).
4521   */
LL_RCC_PLL3_IsReady(void)4522 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
4523 {
4524   return ((READ_BIT(RCC->PLL3CR, RCC_PLL3CR_PLL3RDY) == RCC_PLL3CR_PLL3RDY) ? 1UL : 0UL);
4525 }
4526 
4527 /**
4528   * @brief  Enable PLL3P
4529   * @note   This API shall be called only when PLL3 is enabled and ready.
4530   * @rmtoll PLL3CR           DIVPEN         LL_RCC_PLL3P_Enable
4531   * @retval None
4532   */
LL_RCC_PLL3P_Enable(void)4533 __STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
4534 {
4535   SET_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVPEN);
4536 }
4537 
4538 /**
4539   * @brief  Enable PLL3Q
4540   * @note   This API shall be called only when PLL3 is enabled and ready.
4541   * @rmtoll PLL3CR           DIVQEN         LL_RCC_PLL3Q_Enable
4542   * @retval None
4543   */
LL_RCC_PLL3Q_Enable(void)4544 __STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
4545 {
4546   SET_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVQEN);
4547 }
4548 
4549 /**
4550   * @brief  Enable PLL3R
4551   * @note   This API shall be called only when PLL3 is enabled and ready.
4552   * @rmtoll PLL3CR           DIVREN         LL_RCC_PLL3R_Enable
4553   * @retval None
4554   */
LL_RCC_PLL3R_Enable(void)4555 __STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
4556 {
4557   SET_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVREN);
4558 }
4559 
4560 /**
4561   * @brief  Enable PLL3 FRACV
4562   * @rmtoll PLL3FRACR           FRACLE         LL_RCC_PLL3FRACV_Enable
4563   * @retval None
4564   */
LL_RCC_PLL3FRACV_Enable(void)4565 __STATIC_INLINE void LL_RCC_PLL3FRACV_Enable(void)
4566 {
4567   SET_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACLE);
4568 }
4569 
4570 /**
4571   * @brief  Enable PLL3 Clock Spreading Generator
4572   * @rmtoll PLL3CR           SSCG_CTRL         LL_RCC_PLL3CSG_Enable
4573   * @retval None
4574   */
LL_RCC_PLL3CSG_Enable(void)4575 __STATIC_INLINE void LL_RCC_PLL3CSG_Enable(void)
4576 {
4577   SET_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL);
4578 }
4579 
4580 /**
4581   * @brief  Check if PLL3 P is enabled
4582   * @rmtoll PLL3CR           DIVPEN         LL_RCC_PLL3P_IsEnabled
4583   * @retval State of bit (1 or 0).
4584   */
LL_RCC_PLL3P_IsEnabled(void)4585 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
4586 {
4587   return (uint32_t)((READ_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVPEN) == RCC_PLL3CR_DIVPEN) ? 1UL : 0UL);
4588 }
4589 
4590 /**
4591   * @brief  Check if PLL3 Q is enabled
4592   * @rmtoll PLL3CR           DIVQEN         LL_RCC_PLL3Q_IsEnabled
4593   * @retval State of bit (1 or 0).
4594   */
LL_RCC_PLL3Q_IsEnabled(void)4595 __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
4596 {
4597   return (uint32_t)((READ_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVQEN) == RCC_PLL3CR_DIVQEN) ? 1UL : 0UL);
4598 }
4599 
4600 /**
4601   * @brief  Check if PLL3 R is enabled
4602   * @rmtoll PLL3CR           DIVREN         LL_RCC_PLL3R_IsEnabled
4603   * @retval State of bit (1 or 0).
4604   */
LL_RCC_PLL3R_IsEnabled(void)4605 __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
4606 {
4607   return (uint32_t)((READ_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVREN) == RCC_PLL3CR_DIVREN) ? 1UL : 0UL);
4608 }
4609 
4610 /**
4611   * @brief  Check if PLL3 FRACV is enabled
4612   * @rmtoll PLL3FRACR           FRACLE         LL_RCC_PLL3FRACV_IsEnabled
4613   * @retval State of bit (1 or 0).
4614   */
LL_RCC_PLL3FRACV_IsEnabled(void)4615 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACV_IsEnabled(void)
4616 {
4617   return (uint32_t)((READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACLE) == RCC_PLL3FRACR_FRACLE) ? 1UL : 0UL);
4618 }
4619 
4620 /**
4621   * @brief  Check if PLL3 Clock Spreading Generator is enabled
4622   * @rmtoll PLL3CR           SSCG_CTRL         LL_RCC_PLL3CSG_IsEnabled
4623   * @retval None
4624   */
LL_RCC_PLL3CSG_IsEnabled(void)4625 __STATIC_INLINE uint32_t LL_RCC_PLL3CSG_IsEnabled(void)
4626 {
4627   return (uint32_t)((READ_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL) == RCC_PLL3CR_SSCG_CTRL) ? 1UL : 0UL);
4628 }
4629 
4630 /**
4631   * @brief  Disable PLL3P
4632   * @rmtoll PLL3CR           DIVPEN         LL_RCC_PLL3P_Disable
4633   * @retval None
4634   */
LL_RCC_PLL3P_Disable(void)4635 __STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
4636 {
4637   CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVPEN);
4638 }
4639 
4640 /**
4641   * @brief  Disable PLL3Q
4642   * @rmtoll PLL3CR           DIVQEN         LL_RCC_PLL3Q_Disable
4643   * @retval None
4644   */
LL_RCC_PLL3Q_Disable(void)4645 __STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
4646 {
4647   CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVQEN);
4648 }
4649 
4650 /**
4651   * @brief  Disable PLL3R
4652   * @rmtoll PLL3CR           DIVREN         LL_RCC_PLL3R_Disable
4653   * @retval None
4654   */
LL_RCC_PLL3R_Disable(void)4655 __STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
4656 {
4657   CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVREN);
4658 }
4659 
4660 /**
4661   * @brief  Disable PLL3 FRACV
4662   * @rmtoll PLL3FRACR           FRACLE         LL_RCC_PLL3FRACV_Disable
4663   * @retval None
4664   */
LL_RCC_PLL3FRACV_Disable(void)4665 __STATIC_INLINE void LL_RCC_PLL3FRACV_Disable(void)
4666 {
4667   CLEAR_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACLE);
4668 }
4669 
4670 /**
4671   * @brief  Disable PLL3 Clock Spreading Generator
4672   * @rmtoll PLL3CR           SSCG_CTRL         LL_RCC_PLL3CSG_Disable
4673   * @retval None
4674   */
LL_RCC_PLL3CSG_Disable(void)4675 __STATIC_INLINE void LL_RCC_PLL3CSG_Disable(void)
4676 {
4677   CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL);
4678 }
4679 
4680 /**
4681   * @brief  Get PLL3 N Coefficient
4682   * @rmtoll PLL3CFGR1        DIVN          LL_RCC_PLL3_GetN
4683   * @retval A value between 4 and 512
4684   */
LL_RCC_PLL3_GetN(void)4685 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
4686 {
4687   return (uint32_t)((READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_DIVN) >>  RCC_PLL3CFGR1_DIVN_Pos) + 1U);
4688 }
4689 
4690 /**
4691   * @brief  Get PLL3 M Coefficient
4692   * @rmtoll PLL3CFGR1       DIVM3          LL_RCC_PLL3_GetM
4693   * @retval A value between 1 and 64
4694   */
LL_RCC_PLL3_GetM(void)4695 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
4696 {
4697   return (uint32_t)((READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_DIVM3) >>  RCC_PLL3CFGR1_DIVM3_Pos) + 1U);
4698 }
4699 
4700 /**
4701   * @brief  Get PLL3 input frequency range
4702   * @rmtoll PLL3CFGR1       IFRGE          LL_RCC_PLL3_GetIFRGE
4703   * @retval Returned value can be one of the following values:
4704   *         @arg @ref LL_RCC_PLL3IFRANGE_0
4705   *         @arg @ref LL_RCC_PLL3IFRANGE_1
4706   */
LL_RCC_PLL3_GetIFRGE(void)4707 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetIFRGE(void)
4708 {
4709   return (uint32_t)(READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_IFRGE));
4710 }
4711 
4712 /**
4713   * @brief  Get PLL3 P Coefficient
4714   * @rmtoll PLL3CFGR2        DIVP          LL_RCC_PLL3_GetP
4715   * @retval A value between 1 and 128
4716   */
LL_RCC_PLL3_GetP(void)4717 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
4718 {
4719   return (uint32_t)((READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_DIVP) >>  RCC_PLL3CFGR2_DIVP_Pos) + 1U);
4720 }
4721 
4722 /**
4723   * @brief  Get PLL3 Q Coefficient
4724   * @rmtoll PLL3CFGR2        DIVQ          LL_RCC_PLL3_GetQ
4725   * @retval A value between 1 and 128
4726   */
LL_RCC_PLL3_GetQ(void)4727 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
4728 {
4729   return (uint32_t)((READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_DIVQ) >>  RCC_PLL3CFGR2_DIVQ_Pos) + 1U);
4730 }
4731 
4732 /**
4733   * @brief  Get PLL3 R Coefficient
4734   * @rmtoll PLL3CFGR2        DIVR          LL_RCC_PLL3_GetR
4735   * @retval A value between 1 and 128
4736   */
LL_RCC_PLL3_GetR(void)4737 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
4738 {
4739   return (uint32_t)((READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_DIVR) >>  RCC_PLL3CFGR2_DIVR_Pos) + 1U);
4740 }
4741 
4742 /**
4743   * @brief  Get PLL3 FRACV Coefficient
4744   * @rmtoll PLL3FRACR      FRACV          LL_RCC_PLL3_GetFRACV
4745   * @retval A value between 0 and 8191 (0x1FFF)
4746   */
LL_RCC_PLL3_GetFRACV(void)4747 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACV(void)
4748 {
4749   return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACV) >>  RCC_PLL3FRACR_FRACV_Pos);
4750 }
4751 
4752 /**
4753   * @brief  Set PLL3 N Coefficient
4754   * @note   This API shall be called only when PLL3 is disabled.
4755   * @rmtoll PLL3CFGR1        DIVN          LL_RCC_PLL3_SetN
4756   * @param  DIVN parameter can be a value between 4 and 512
4757   */
LL_RCC_PLL3_SetN(uint32_t DIVN)4758 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t DIVN)
4759 {
4760   MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_DIVN, (DIVN - 1U) << RCC_PLL3CFGR1_DIVN_Pos);
4761 }
4762 
4763 /**
4764   * @brief  Set PLL3 M Coefficient
4765   * @note   This API shall be called only when PLL3 is disabled.
4766   * @rmtoll PLL3CFGR1       DIVM3          LL_RCC_PLL3_SetM
4767   * @param  DIVM3 parameter can be a value between 1 and 64
4768   */
LL_RCC_PLL3_SetM(uint32_t DIVM3)4769 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t DIVM3)
4770 {
4771   MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_DIVM3, (DIVM3 - 1U) << RCC_PLL3CFGR1_DIVM3_Pos);
4772 }
4773 
4774 /**
4775   * @brief  Set PLL3 input frequency range
4776   * @rmtoll PLL3CFGR1       IFRGE          LL_RCC_PLL3_SetIFRGE
4777   * @param  IFRange parameter can be one of the following values:
4778   *         @arg @ref LL_RCC_PLL3IFRANGE_0
4779   *         @arg @ref LL_RCC_PLL3IFRANGE_1
4780   * @note   If ref3_ck is equal to 8 MHz, it is recommended to set LL_RCC_PLL3IFRANGE_1
4781   * @retval None
4782   */
LL_RCC_PLL3_SetIFRGE(uint32_t IFRange)4783 __STATIC_INLINE void LL_RCC_PLL3_SetIFRGE(uint32_t IFRange)
4784 {
4785   MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_IFRGE, IFRange);
4786 }
4787 
4788 /**
4789   * @brief  Set PLL3 P Coefficient
4790   * @rmtoll PLL3CFGR2        DIVP          LL_RCC_PLL3_SetP
4791   * @param  DIVP parameter can be a value between 1 and 128
4792   */
LL_RCC_PLL3_SetP(uint32_t DIVP)4793 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t DIVP)
4794 {
4795   MODIFY_REG(RCC->PLL3CFGR2, RCC_PLL3CFGR2_DIVP, (DIVP - 1U) << RCC_PLL3CFGR2_DIVP_Pos);
4796 }
4797 
4798 /**
4799   * @brief  Set PLL3 Q Coefficient
4800   * @rmtoll PLL3CFGR2        DIVQ          LL_RCC_PLL3_SetQ
4801   * @param  DIVQ parameter can be a value between 1 and 128
4802   */
LL_RCC_PLL3_SetQ(uint32_t DIVQ)4803 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t DIVQ)
4804 {
4805   MODIFY_REG(RCC->PLL3CFGR2, RCC_PLL3CFGR2_DIVQ, (DIVQ - 1U) << RCC_PLL3CFGR2_DIVQ_Pos);
4806 }
4807 
4808 /**
4809   * @brief  Set PLL3 R Coefficient
4810   * @rmtoll PLL3CFGR2        DIVR          LL_RCC_PLL3_SetR
4811   * @param  DIVR parameter can be a value between 1 and 128
4812   */
LL_RCC_PLL3_SetR(uint32_t DIVR)4813 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t DIVR)
4814 {
4815   MODIFY_REG(RCC->PLL3CFGR2, RCC_PLL3CFGR2_DIVR, (DIVR - 1U) << RCC_PLL3CFGR2_DIVR_Pos);
4816 }
4817 
4818 /**
4819   * @brief  Set PLL3 FRACV Coefficient
4820   * @rmtoll PLL3FRACR        FRACV          LL_RCC_PLL3_SetFRACV
4821   * @param  FRACV parameter can be a value between 0 and 8191 (0x1FFF)
4822   */
LL_RCC_PLL3_SetFRACV(uint32_t FRACV)4823 __STATIC_INLINE void LL_RCC_PLL3_SetFRACV(uint32_t FRACV)
4824 {
4825   MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACV, FRACV << RCC_PLL3FRACR_FRACV_Pos);
4826 }
4827 
4828 /** @brief  Configure the PLL3 Clock Spreading Generator
4829   * @rmtoll PLL3CSGR    MOD_PER, TPDFN_DIS, RPDFN_DIS, SSCG_MODE, INC_STEP  LL_RCC_PLL3_ConfigCSG
4830   *
4831   * @param  ModPeriod: Modulation Period Adjustment for PLL3
4832   *         This parameter must have a value between 1 and 8191
4833   *
4834   * @param  TPDFN
4835   *         This parameter can be one of the following values:
4836   *         @arg @ref LL_RCC_PLL3TPDFN_DIS_ENABLED
4837   *         @arg @ref LL_RCC_PLL3TPDFN_DIS_DISABLED
4838 
4839   * @param  RPDFN
4840   *         This parameter can be one of the following values:
4841   *         @arg @ref LL_RCC_PLL3RPDFN_DIS_ENABLED
4842   *         @arg @ref LL_RCC_PLL3RPDFN_DIS_DISABLED
4843   *
4844   * @param  SSCGMode
4845   *         This parameter can be one of the following values:
4846   *         @arg @ref LL_RCC_PLL3SSCG_CENTER_SPREAD
4847   *         @arg @ref LL_RCC_PLL3SSCG_DOWN_SPREAD
4848   *
4849   * @param  IncStep: Modulation Depth Adjustment for PLL3
4850   *         This parameter must have a value between 1 and 32767
4851   * @note   ModPeriod x IncStep shall not exceed (2^15)-1
4852   * @retval None
4853   */
LL_RCC_PLL3_ConfigCSG(uint32_t ModPeriod,uint32_t TPDFN,uint32_t RPDFN,uint32_t SSCGMode,uint32_t IncStep)4854 __STATIC_INLINE void LL_RCC_PLL3_ConfigCSG(uint32_t ModPeriod, uint32_t TPDFN, uint32_t RPDFN, uint32_t SSCGMode, uint32_t IncStep)
4855 {
4856   MODIFY_REG(RCC->PLL3CSGR, (RCC_PLL3CSGR_MOD_PER | RCC_PLL3CSGR_TPDFN_DIS | RCC_PLL3CSGR_RPDFN_DIS | \
4857                              RCC_PLL3CSGR_SSCG_MODE | RCC_PLL3CSGR_INC_STEP), \
4858              (ModPeriod | TPDFN | RPDFN | SSCGMode | (IncStep << RCC_PLL3CSGR_INC_STEP_Pos)));
4859 }
4860 
4861 /**
4862   * @brief  Set the oscillator used as PLL4 clock source.
4863   * @note   PLLSRC can be written only when all PLL4 is disabled.
4864   * @rmtoll RCK4SELR      PLL4SRC        LL_RCC_PLL4_SetSource
4865   * @param  PLLSource parameter can be one of the following values:
4866   *         @arg @ref LL_RCC_PLL4SOURCE_HSI
4867   *         @arg @ref LL_RCC_PLL4SOURCE_HSE
4868   *         @arg @ref LL_RCC_PLL4SOURCE_CSI
4869   *         @arg @ref LL_RCC_PLL4SOURCE_I2SCKIN
4870   * @retval None
4871   */
LL_RCC_PLL4_SetSource(uint32_t PLLSource)4872 __STATIC_INLINE void LL_RCC_PLL4_SetSource(uint32_t PLLSource)
4873 {
4874   MODIFY_REG(RCC->RCK4SELR, RCC_RCK4SELR_PLL4SRC, PLLSource);
4875 }
4876 
4877 /**
4878   * @brief  Get the oscillator used as PLL4 clock source.
4879   * @rmtoll RCK4SELR      PLL4SRC        LL_RCC_PLL4_GetSource
4880   * @retval Returned value can be one of the following values:
4881   *         @arg @ref LL_RCC_PLL4SOURCE_HSI
4882   *         @arg @ref LL_RCC_PLL4SOURCE_HSE
4883   *         @arg @ref LL_RCC_PLL4SOURCE_CSI
4884   *         @arg @ref LL_RCC_PLL4SOURCE_I2SCKIN
4885   */
LL_RCC_PLL4_GetSource(void)4886 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetSource(void)
4887 {
4888   return (uint32_t)(READ_BIT(RCC->RCK4SELR, RCC_RCK4SELR_PLL4SRC));
4889 }
4890 
4891 /**
4892   * @brief  Enable PLL4
4893   * @rmtoll PLL4CR           PLLON         LL_RCC_PLL4_Enable
4894   * @retval None
4895   */
LL_RCC_PLL4_Enable(void)4896 __STATIC_INLINE void LL_RCC_PLL4_Enable(void)
4897 {
4898   SET_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON);
4899 }
4900 
4901 /**
4902   * @brief  Disable PLL4
4903   * @note Cannot be disabled if the PLL clock is used as a system clock.
4904   *       This API shall be called only when PLL1 DIVPEN, DIVQEN and DIVREN
4905   *       are disabled.
4906   * @rmtoll PLL4CR           PLLON         LL_RCC_PLL4_Disable
4907   * @retval None
4908   */
LL_RCC_PLL4_Disable(void)4909 __STATIC_INLINE void LL_RCC_PLL4_Disable(void)
4910 {
4911   CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON);
4912 }
4913 
4914 /**
4915   * @brief  Check if PLL4 Ready
4916   * @rmtoll PLL4CR           PLL4RDY        LL_RCC_PLL4_IsReady
4917   * @retval State of bit (1 or 0).
4918   */
LL_RCC_PLL4_IsReady(void)4919 __STATIC_INLINE uint32_t LL_RCC_PLL4_IsReady(void)
4920 {
4921   return ((READ_BIT(RCC->PLL4CR, RCC_PLL4CR_PLL4RDY) == RCC_PLL4CR_PLL4RDY) ? 1UL : 0UL);
4922 }
4923 
4924 /**
4925   * @brief  Enable PLL4P
4926   * @note   This API shall be called only when PLL4 is enabled and ready.
4927   * @rmtoll PLL4CR           DIVPEN         LL_RCC_PLL4P_Enable
4928   * @retval None
4929   */
LL_RCC_PLL4P_Enable(void)4930 __STATIC_INLINE void LL_RCC_PLL4P_Enable(void)
4931 {
4932   SET_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVPEN);
4933 }
4934 
4935 /**
4936   * @brief  Enable PLL4Q
4937   * @note   This API shall be called only when PLL4 is enabled and ready.
4938   * @rmtoll PLL4CR           DIVQEN         LL_RCC_PLL4Q_Enable
4939   * @retval None
4940   */
LL_RCC_PLL4Q_Enable(void)4941 __STATIC_INLINE void LL_RCC_PLL4Q_Enable(void)
4942 {
4943   SET_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVQEN);
4944 }
4945 
4946 /**
4947   * @brief  Enable PLL4R
4948   * @note   This API shall be called only when PLL4 is enabled and ready.
4949   * @rmtoll PLL4CR           DIVREN         LL_RCC_PLL4R_Enable
4950   * @retval None
4951   */
LL_RCC_PLL4R_Enable(void)4952 __STATIC_INLINE void LL_RCC_PLL4R_Enable(void)
4953 {
4954   SET_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVREN);
4955 }
4956 
4957 /**
4958   * @brief  Enable PLL4 FRACV
4959   * @rmtoll PLL4FRACR           FRACLE         LL_RCC_PLL4FRACV_Enable
4960   * @retval None
4961   */
LL_RCC_PLL4FRACV_Enable(void)4962 __STATIC_INLINE void LL_RCC_PLL4FRACV_Enable(void)
4963 {
4964   SET_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACLE);
4965 }
4966 
4967 /**
4968   * @brief  Enable PLL4 Clock Spreading Generator
4969   * @rmtoll PLL4CR           SSCG_CTRL         LL_RCC_PLL4CSG_Enable
4970   * @retval None
4971   */
LL_RCC_PLL4CSG_Enable(void)4972 __STATIC_INLINE void LL_RCC_PLL4CSG_Enable(void)
4973 {
4974   SET_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL);
4975 }
4976 
4977 /**
4978   * @brief  Check if PLL4 P is enabled
4979   * @rmtoll PLL4CR           DIVPEN         LL_RCC_PLL4P_IsEnabled
4980   * @retval State of bit (1 or 0).
4981   */
LL_RCC_PLL4P_IsEnabled(void)4982 __STATIC_INLINE uint32_t LL_RCC_PLL4P_IsEnabled(void)
4983 {
4984   return (uint32_t)((READ_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVPEN) == RCC_PLL4CR_DIVPEN) ? 1UL : 0UL);
4985 }
4986 
4987 /**
4988   * @brief  Check if PLL4 Q is enabled
4989   * @rmtoll PLL4CR           DIVQEN         LL_RCC_PLL4Q_IsEnabled
4990   * @retval State of bit (1 or 0).
4991   */
LL_RCC_PLL4Q_IsEnabled(void)4992 __STATIC_INLINE uint32_t LL_RCC_PLL4Q_IsEnabled(void)
4993 {
4994   return (uint32_t)((READ_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVQEN) == RCC_PLL4CR_DIVQEN) ? 1UL : 0UL);
4995 }
4996 
4997 /**
4998   * @brief  Check if PLL4 R is enabled
4999   * @rmtoll PLL4CR           DIVREN         LL_RCC_PLL4R_IsEnabled
5000   * @retval State of bit (1 or 0).
5001   */
LL_RCC_PLL4R_IsEnabled(void)5002 __STATIC_INLINE uint32_t LL_RCC_PLL4R_IsEnabled(void)
5003 {
5004   return (uint32_t)((READ_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVREN) == RCC_PLL4CR_DIVREN) ? 1UL : 0UL);
5005 }
5006 
5007 /**
5008   * @brief  Check if PLL4 FRACV is enabled
5009   * @rmtoll PLL4FRACR           FRACLE         LL_RCC_PLL4FRACV_IsEnabled
5010   * @retval State of bit (1 or 0).
5011   */
LL_RCC_PLL4FRACV_IsEnabled(void)5012 __STATIC_INLINE uint32_t LL_RCC_PLL4FRACV_IsEnabled(void)
5013 {
5014   return (uint32_t)((READ_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACLE) == RCC_PLL4FRACR_FRACLE) ? 1UL : 0UL);
5015 }
5016 
5017 /**
5018   * @brief  Check if PLL4 Clock Spreading Generator is enabled
5019   * @rmtoll PLL4CR           SSCG_CTRL         LL_RCC_PLL4CSG_IsEnabled
5020   * @retval None
5021   */
LL_RCC_PLL4CSG_IsEnabled(void)5022 __STATIC_INLINE uint32_t LL_RCC_PLL4CSG_IsEnabled(void)
5023 {
5024   return (uint32_t)((READ_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL) == RCC_PLL4CR_SSCG_CTRL) ? 1UL : 0UL);
5025 }
5026 
5027 /**
5028   * @brief  Disable PLL4P
5029   * @rmtoll PLL4CR           DIVPEN         LL_RCC_PLL4P_Disable
5030   * @retval None
5031   */
LL_RCC_PLL4P_Disable(void)5032 __STATIC_INLINE void LL_RCC_PLL4P_Disable(void)
5033 {
5034   CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVPEN);
5035 }
5036 
5037 /**
5038   * @brief  Disable PLL4Q
5039   * @rmtoll PLL4CR           DIVQEN         LL_RCC_PLL4Q_Disable
5040   * @retval None
5041   */
LL_RCC_PLL4Q_Disable(void)5042 __STATIC_INLINE void LL_RCC_PLL4Q_Disable(void)
5043 {
5044   CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVQEN);
5045 }
5046 
5047 /**
5048   * @brief  Disable PLL4R
5049   * @rmtoll PLL4CR           DIVREN         LL_RCC_PLL4R_Disable
5050   * @retval None
5051   */
LL_RCC_PLL4R_Disable(void)5052 __STATIC_INLINE void LL_RCC_PLL4R_Disable(void)
5053 {
5054   CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVREN);
5055 }
5056 
5057 /**
5058   * @brief  Disable PLL4 FRACV
5059   * @rmtoll PLL4FRACR           FRACLE         LL_RCC_PLL4FRACV_Disable
5060   * @retval None
5061   */
LL_RCC_PLL4FRACV_Disable(void)5062 __STATIC_INLINE void LL_RCC_PLL4FRACV_Disable(void)
5063 {
5064   CLEAR_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACLE);
5065 }
5066 
5067 /**
5068   * @brief  Disable PLL4 Clock Spreading Generator
5069   * @rmtoll PLL4CR           SSCG_CTRL         LL_RCC_PLL4CSG_Disable
5070   * @retval None
5071   */
LL_RCC_PLL4CSG_Disable(void)5072 __STATIC_INLINE void LL_RCC_PLL4CSG_Disable(void)
5073 {
5074   CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL);
5075 }
5076 
5077 /**
5078   * @brief  Get PLL4 N Coefficient
5079   * @rmtoll PLL4CFGR1        DIVN          LL_RCC_PLL4_GetN
5080   * @retval A value between 4 and 512
5081   */
LL_RCC_PLL4_GetN(void)5082 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetN(void)
5083 {
5084   return (uint32_t)((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_DIVN) >>  RCC_PLL4CFGR1_DIVN_Pos) + 1U);
5085 }
5086 
5087 /**
5088   * @brief  Get PLL4 M Coefficient
5089   * @rmtoll PLL4CFGR1       DIVM4          LL_RCC_PLL4_GetM
5090   * @retval A value between 1 and 64
5091   */
LL_RCC_PLL4_GetM(void)5092 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetM(void)
5093 {
5094   return (uint32_t)((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_DIVM4) >>  RCC_PLL4CFGR1_DIVM4_Pos) + 1U);
5095 }
5096 
5097 /**
5098   * @brief  Get PLL4 input frequency range
5099   * @rmtoll PLL4CFGR1       IFRGE          LL_RCC_PLL4_GetIFRGE
5100   * @retval Returned value can be one of the following values:
5101   *         @arg @ref LL_RCC_PLL4IFRANGE_0
5102   *         @arg @ref LL_RCC_PLL4IFRANGE_1
5103   */
LL_RCC_PLL4_GetIFRGE(void)5104 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetIFRGE(void)
5105 {
5106   return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_IFRGE));
5107 }
5108 
5109 /**
5110   * @brief  Get PLL4 P Coefficient
5111   * @rmtoll PLL4CFGR2        DIVP          LL_RCC_PLL4_GetP
5112   * @retval A value between 1 and 128
5113   */
LL_RCC_PLL4_GetP(void)5114 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetP(void)
5115 {
5116   return (uint32_t)((READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_DIVP) >>  RCC_PLL4CFGR2_DIVP_Pos) + 1U);
5117 }
5118 
5119 /**
5120   * @brief  Get PLL4 Q Coefficient
5121   * @rmtoll PLL4CFGR2        DIVQ          LL_RCC_PLL4_GetQ
5122   * @retval A value between 1 and 128
5123   */
LL_RCC_PLL4_GetQ(void)5124 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetQ(void)
5125 {
5126   return (uint32_t)((READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_DIVQ) >>  RCC_PLL4CFGR2_DIVQ_Pos) + 1U);
5127 }
5128 
5129 /**
5130   * @brief  Get PLL4 R Coefficient
5131   * @rmtoll PLL4CFGR2        DIVR          LL_RCC_PLL4_GetR
5132   * @retval A value between 1 and 128
5133   */
LL_RCC_PLL4_GetR(void)5134 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetR(void)
5135 {
5136   return (uint32_t)((READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_DIVR) >>  RCC_PLL4CFGR2_DIVR_Pos) + 1U);
5137 }
5138 
5139 /**
5140   * @brief  Get PLL4 FRACV Coefficient
5141   * @rmtoll PLL4FRACR      FRACV          LL_RCC_PLL4_GetFRACV
5142   * @retval A value between 0 and 8191 (0x1FFF)
5143   */
LL_RCC_PLL4_GetFRACV(void)5144 __STATIC_INLINE uint32_t LL_RCC_PLL4_GetFRACV(void)
5145 {
5146   return (uint32_t)(READ_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACV) >>  RCC_PLL4FRACR_FRACV_Pos);
5147 }
5148 
5149 /**
5150   * @brief  Set PLL4 N Coefficient
5151   * @note   This API shall be called only when PLL4 is disabled.
5152   * @rmtoll PLL4CFGR1        DIVN          LL_RCC_PLL4_SetN
5153   * @param  DIVN parameter can be a value between 4 and 512
5154   */
LL_RCC_PLL4_SetN(uint32_t DIVN)5155 __STATIC_INLINE void LL_RCC_PLL4_SetN(uint32_t DIVN)
5156 {
5157   MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_DIVN, (DIVN - 1U) << RCC_PLL4CFGR1_DIVN_Pos);
5158 }
5159 
5160 /**
5161   * @brief  Set PLL4 M Coefficient
5162   * @note   This API shall be called only when PLL4 is disabled.
5163   * @rmtoll PLL4CFGR1       DIVM4          LL_RCC_PLL4_SetM
5164   * @param  DIVM4 parameter can be a value between 1 and 64
5165   */
LL_RCC_PLL4_SetM(uint32_t DIVM4)5166 __STATIC_INLINE void LL_RCC_PLL4_SetM(uint32_t DIVM4)
5167 {
5168   MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_DIVM4, (DIVM4 - 1U) << RCC_PLL4CFGR1_DIVM4_Pos);
5169 }
5170 
5171 /**
5172   * @brief  Set PLL4 input frequency range
5173   * @rmtoll PLL4CFGR1       IFRGE          LL_RCC_PLL4_SetIFRGE
5174   * @param  IFRange parameter can be one of the following values:
5175   *         @arg @ref LL_RCC_PLL4IFRANGE_0
5176   *         @arg @ref LL_RCC_PLL4IFRANGE_1
5177   * @note   If ref4_ck is equal to 8 MHz, it is recommended to set LL_RCC_PLL4IFRANGE_1
5178   * @retval None
5179   */
LL_RCC_PLL4_SetIFRGE(uint32_t IFRange)5180 __STATIC_INLINE void LL_RCC_PLL4_SetIFRGE(uint32_t IFRange)
5181 {
5182   MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_IFRGE, IFRange);
5183 }
5184 
5185 /**
5186   * @brief  Set PLL4 P Coefficient
5187   * @rmtoll PLL4CFGR2        DIVP          LL_RCC_PLL4_SetP
5188   * @param  DIVP parameter can be a value between 1 and 128
5189   */
LL_RCC_PLL4_SetP(uint32_t DIVP)5190 __STATIC_INLINE void LL_RCC_PLL4_SetP(uint32_t DIVP)
5191 {
5192   MODIFY_REG(RCC->PLL4CFGR2, RCC_PLL4CFGR2_DIVP, (DIVP - 1U) << RCC_PLL4CFGR2_DIVP_Pos);
5193 }
5194 
5195 /**
5196   * @brief  Set PLL4 Q Coefficient
5197   * @rmtoll PLL4CFGR2        DIVQ          LL_RCC_PLL4_SetQ
5198   * @param  DIVQ parameter can be a value between 1 and 128
5199   */
LL_RCC_PLL4_SetQ(uint32_t DIVQ)5200 __STATIC_INLINE void LL_RCC_PLL4_SetQ(uint32_t DIVQ)
5201 {
5202   MODIFY_REG(RCC->PLL4CFGR2, RCC_PLL4CFGR2_DIVQ, (DIVQ - 1U) << RCC_PLL4CFGR2_DIVQ_Pos);
5203 }
5204 
5205 /**
5206   * @brief  Set PLL4 R Coefficient
5207   * @rmtoll PLL4CFGR2        DIVR          LL_RCC_PLL4_SetR
5208   * @param  DIVR parameter can be a value between 1 and 128
5209   */
LL_RCC_PLL4_SetR(uint32_t DIVR)5210 __STATIC_INLINE void LL_RCC_PLL4_SetR(uint32_t DIVR)
5211 {
5212   MODIFY_REG(RCC->PLL4CFGR2, RCC_PLL4CFGR2_DIVR, (DIVR - 1U) << RCC_PLL4CFGR2_DIVR_Pos);
5213 }
5214 
5215 /**
5216   * @brief  Set PLL4 FRACV Coefficient
5217   * @rmtoll PLL4FRACR        FRACV          LL_RCC_PLL4_SetFRACV
5218   * @param  FRACV parameter can be a value between 0 and 8191 (0x1FFF)
5219   */
LL_RCC_PLL4_SetFRACV(uint32_t FRACV)5220 __STATIC_INLINE void LL_RCC_PLL4_SetFRACV(uint32_t FRACV)
5221 {
5222   MODIFY_REG(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACV, FRACV << RCC_PLL4FRACR_FRACV_Pos);
5223 }
5224 
5225 /** @brief  Configure the PLL4 Clock Spreading Generator
5226   * @rmtoll PLL4CSGR    MOD_PER, TPDFN_DIS, RPDFN_DIS, SSCG_MODE, INC_STEP  LL_RCC_PLL4_ConfigCSG
5227   *
5228   * @param  ModPeriod: Modulation Period Adjustment for PLL4
5229   *         This parameter must have a value between 1 and 8191
5230   *
5231   * @param  TPDFN
5232   *         This parameter can be one of the following values:
5233   *         @arg @ref LL_RCC_PLL4TPDFN_DIS_ENABLED
5234   *         @arg @ref LL_RCC_PLL4TPDFN_DIS_DISABLED
5235 
5236   * @param  RPDFN
5237   *         This parameter can be one of the following values:
5238   *         @arg @ref LL_RCC_PLL4RPDFN_DIS_ENABLED
5239   *         @arg @ref LL_RCC_PLL4RPDFN_DIS_DISABLED
5240   *
5241   * @param  SSCGMode
5242   *         This parameter can be one of the following values:
5243   *         @arg @ref LL_RCC_PLL4SSCG_CENTER_SPREAD
5244   *         @arg @ref LL_RCC_PLL4SSCG_DOWN_SPREAD
5245   *
5246   * @param  IncStep: Modulation Depth Adjustment for PLL4
5247   *         This parameter must have a value between 1 and 32767
5248   * @note   ModPeriod x IncStep shall not exceed (2^15)-1
5249   * @retval None
5250   */
LL_RCC_PLL4_ConfigCSG(uint32_t ModPeriod,uint32_t TPDFN,uint32_t RPDFN,uint32_t SSCGMode,uint32_t IncStep)5251 __STATIC_INLINE void LL_RCC_PLL4_ConfigCSG(uint32_t ModPeriod, uint32_t TPDFN, uint32_t RPDFN, uint32_t SSCGMode, uint32_t IncStep)
5252 {
5253   MODIFY_REG(RCC->PLL4CSGR, (RCC_PLL4CSGR_MOD_PER | RCC_PLL4CSGR_TPDFN_DIS | RCC_PLL4CSGR_RPDFN_DIS | \
5254                              RCC_PLL4CSGR_SSCG_MODE | RCC_PLL4CSGR_INC_STEP), \
5255              (ModPeriod | TPDFN | RPDFN | SSCGMode | (IncStep << RCC_PLL4CSGR_INC_STEP_Pos)));
5256 }
5257 
5258 
5259 /**
5260   * @}
5261   */
5262 
5263 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
5264   * @{
5265   */
5266 
5267 /**
5268   * @brief  Clear LSI ready interrupt flag
5269   * @rmtoll MC_CIFR      LSIRDYF      LL_RCC_ClearFlag_LSIRDY
5270   * @retval None
5271   */
LL_RCC_ClearFlag_LSIRDY(void)5272 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
5273 {
5274   WRITE_REG(RCC->MC_CIFR, RCC_MC_CIFR_LSIRDYF);
5275 }
5276 
5277 /**
5278   * @brief  Clear LSE ready interrupt flag
5279   * @rmtoll MC_CIFR      LSERDYF       LL_RCC_ClearFlag_LSERDY
5280   * @retval None
5281   */
LL_RCC_ClearFlag_LSERDY(void)5282 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
5283 {
5284   WRITE_REG(RCC->MC_CIFR, RCC_MC_CIFR_LSERDYF);
5285 }
5286 
5287 /**
5288   * @brief  Clear HSI ready interrupt flag
5289   * @rmtoll MC_CIFR      HSIRDYF       LL_RCC_ClearFlag_HSIRDY
5290   * @retval None
5291   */
LL_RCC_ClearFlag_HSIRDY(void)5292 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
5293 {
5294   WRITE_REG(RCC->MC_CIFR, RCC_MC_CIFR_HSIRDYF);
5295 }
5296 
5297 /**
5298   * @brief  Clear HSE ready interrupt flag
5299   * @rmtoll CICR         HSERDYF       LL_RCC_ClearFlag_HSERDY
5300   * @retval None
5301   */
LL_RCC_ClearFlag_HSERDY(void)5302 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
5303 {
5304   WRITE_REG(RCC->MC_CIFR, RCC_MC_CIFR_HSERDYF);
5305 }
5306 
5307 /**
5308   * @brief  Clear CSI ready interrupt flag
5309   * @rmtoll MC_CIFR      CSIRDYF       LL_RCC_ClearFlag_CSIRDY
5310   * @retval None
5311   */
LL_RCC_ClearFlag_CSIRDY(void)5312 __STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
5313 {
5314   WRITE_REG(RCC->MC_CIFR, RCC_MC_CIFR_CSIRDYF);
5315 }
5316 
5317 /**
5318   * @brief  Clear PLL1 ready interrupt flag
5319   * @rmtoll MC_CIFR      PLL1DYF       LL_RCC_ClearFlag_PLL1RDY
5320   * @retval None
5321   */
LL_RCC_ClearFlag_PLL1RDY(void)5322 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
5323 {
5324   WRITE_REG(RCC->MC_CIFR, RCC_MC_CIFR_PLL1DYF);
5325 }
5326 
5327 /**
5328   * @brief  Clear PLL2 ready interrupt flag
5329   * @rmtoll MC_CIFR      PLL2DYF       LL_RCC_ClearFlag_PLL2RDY
5330   * @retval None
5331   */
LL_RCC_ClearFlag_PLL2RDY(void)5332 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
5333 {
5334   WRITE_REG(RCC->MC_CIFR, RCC_MC_CIFR_PLL2DYF);
5335 }
5336 
5337 /**
5338   * @brief  Clear PLL3 ready interrupt flag
5339   * @rmtoll MC_CIFR      PLL3DYF       LL_RCC_ClearFlag_PLL3RDY
5340   * @retval None
5341   */
LL_RCC_ClearFlag_PLL3RDY(void)5342 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
5343 {
5344   WRITE_REG(RCC->MC_CIFR, RCC_MC_CIFR_PLL3DYF);
5345 }
5346 
5347 /**
5348   * @brief  Clear PLL4 ready interrupt flag
5349   * @rmtoll MC_CIFR      PLL4DYF       LL_RCC_ClearFlag_PLL4RDY
5350   * @retval None
5351   */
LL_RCC_ClearFlag_PLL4RDY(void)5352 __STATIC_INLINE void LL_RCC_ClearFlag_PLL4RDY(void)
5353 {
5354   WRITE_REG(RCC->MC_CIFR, RCC_MC_CIFR_PLL4DYF);
5355 }
5356 
5357 /**
5358   * @brief  Clear LSE Clock security system interrupt flag
5359   * @rmtoll MC_CIFR      LSECSSF       LL_RCC_ClearFlag_LSECSS
5360   * @retval None
5361   */
LL_RCC_ClearFlag_LSECSS(void)5362 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
5363 {
5364   WRITE_REG(RCC->MC_CIFR, RCC_MC_CIFR_LSECSSF);
5365 }
5366 
5367 /**
5368   * @brief  Clear WKUP Wake up from CStop interrupt flag
5369   * @rmtoll MC_CIFR      WKUPF       LL_RCC_ClearFlag_WKUP
5370   * @retval None
5371   */
LL_RCC_ClearFlag_WKUP(void)5372 __STATIC_INLINE void LL_RCC_ClearFlag_WKUP(void)
5373 {
5374   WRITE_REG(RCC->MC_CIFR, RCC_MC_CIFR_WKUPF);
5375 }
5376 
5377 /**
5378   * @brief  Check if LSI ready interrupt occurred or not
5379   * @rmtoll MC_CIFR      LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
5380   * @retval State of bit (1 or 0).
5381   */
LL_RCC_IsActiveFlag_LSIRDY(void)5382 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
5383 {
5384   return (READ_BIT(RCC->MC_CIFR, RCC_MC_CIFR_LSIRDYF) == (RCC_MC_CIFR_LSIRDYF));
5385 }
5386 
5387 /**
5388   * @brief  Check if LSE ready interrupt occurred or not
5389   * @rmtoll MC_CIFR      LSERDYF       LL_RCC_IsActiveFlag_LSERDY
5390   * @retval State of bit (1 or 0).
5391   */
LL_RCC_IsActiveFlag_LSERDY(void)5392 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
5393 {
5394   return (READ_BIT(RCC->MC_CIFR, RCC_MC_CIFR_LSERDYF) == (RCC_MC_CIFR_LSERDYF));
5395 }
5396 
5397 /**
5398   * @brief  Check if HSI ready interrupt occurred or not
5399   * @rmtoll MC_CIFR      HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
5400   * @retval State of bit (1 or 0).
5401   */
LL_RCC_IsActiveFlag_HSIRDY(void)5402 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
5403 {
5404   return (READ_BIT(RCC->MC_CIFR, RCC_MC_CIFR_HSIRDYF) == (RCC_MC_CIFR_HSIRDYF));
5405 }
5406 
5407 /**
5408   * @brief  Check if HSE ready interrupt occurred or not
5409   * @rmtoll MC_CIFR      HSERDYF       LL_RCC_IsActiveFlag_HSERDY
5410   * @retval State of bit (1 or 0).
5411   */
LL_RCC_IsActiveFlag_HSERDY(void)5412 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
5413 {
5414   return (READ_BIT(RCC->MC_CIFR, RCC_MC_CIFR_HSERDYF) == (RCC_MC_CIFR_HSERDYF));
5415 }
5416 
5417 /**
5418   * @brief  Check if CSI ready interrupt occurred or not
5419   * @rmtoll MC_CIFR      CSIRDYF       LL_RCC_IsActiveFlag_CSIRDY
5420   * @retval State of bit (1 or 0).
5421   */
LL_RCC_IsActiveFlag_CSIRDY(void)5422 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
5423 {
5424   return (READ_BIT(RCC->MC_CIFR, RCC_MC_CIFR_CSIRDYF) == (RCC_MC_CIFR_CSIRDYF));
5425 }
5426 
5427 /**
5428   * @brief  Check if PLL1 ready interrupt occurred or not
5429   * @rmtoll MC_CIFR      PLL1DYF       LL_RCC_IsActiveFlag_PLL1RDY
5430   * @retval State of bit (1 or 0).
5431   */
LL_RCC_IsActiveFlag_PLL1RDY(void)5432 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
5433 {
5434   return (READ_BIT(RCC->MC_CIFR, RCC_MC_CIFR_PLL1DYF) == (RCC_MC_CIFR_PLL1DYF));
5435 }
5436 
5437 /**
5438   * @brief  Check if PLL2 ready interrupt occurred or not
5439   * @rmtoll MC_CIFR      PLL2DYF       LL_RCC_IsActiveFlag_PLL2RDY
5440   * @retval State of bit (1 or 0).
5441   */
LL_RCC_IsActiveFlag_PLL2RDY(void)5442 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
5443 {
5444   return (READ_BIT(RCC->MC_CIFR, RCC_MC_CIFR_PLL2DYF) == (RCC_MC_CIFR_PLL2DYF));
5445 }
5446 
5447 /**
5448   * @brief  Check if PLL3 ready interrupt occurred or not
5449   * @rmtoll MC_CIFR      PLL3DYF       LL_RCC_IsActiveFlag_PLL3RDY
5450   * @retval State of bit (1 or 0).
5451   */
LL_RCC_IsActiveFlag_PLL3RDY(void)5452 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
5453 {
5454   return (READ_BIT(RCC->MC_CIFR, RCC_MC_CIFR_PLL3DYF) == (RCC_MC_CIFR_PLL3DYF));
5455 }
5456 
5457 /**
5458   * @brief  Check if PLL4 ready interrupt occurred or not
5459   * @rmtoll MC_CIFR      PLL4DYF       LL_RCC_IsActiveFlag_PLL4RDY
5460   * @retval State of bit (1 or 0).
5461   */
LL_RCC_IsActiveFlag_PLL4RDY(void)5462 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL4RDY(void)
5463 {
5464   return (READ_BIT(RCC->MC_CIFR, RCC_MC_CIFR_PLL4DYF) == (RCC_MC_CIFR_PLL4DYF));
5465 }
5466 
5467 /**
5468   * @brief  Check if LSE Clock security system interrupt occurred or not
5469   * @rmtoll MC_CIFR      LSECSSF       LL_RCC_IsActiveFlag_LSECSS
5470   * @retval State of bit (1 or 0).
5471   */
LL_RCC_IsActiveFlag_LSECSS(void)5472 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
5473 {
5474   return (READ_BIT(RCC->MC_CIFR, RCC_MC_CIFR_LSECSSF) == (RCC_MC_CIFR_LSECSSF));
5475 }
5476 
5477 /**
5478   * @brief  Check if Wake up from CStop interrupt occurred or not
5479   * @rmtoll MC_CIFR      WKUPF       LL_RCC_IsActiveFlag_WKUP
5480   * @retval State of bit (1 or 0).
5481   */
LL_RCC_IsActiveFlag_WKUP(void)5482 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WKUP(void)
5483 {
5484   return (READ_BIT(RCC->MC_CIFR, RCC_MC_CIFR_WKUPF) == (RCC_MC_CIFR_WKUPF));
5485 }
5486 
5487 /**
5488   * @brief  Check if RCC flag Window Watchdog 1 reset is set or not.
5489   * @rmtoll MC_RSTSCLRR          WWDG1RSTF      LL_RCC_IsActiveFlag_WWDG1RST
5490   * @retval State of bit (1 or 0).
5491   */
LL_RCC_IsActiveFlag_WWDG1RST(void)5492 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
5493 {
5494   return (READ_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_WWDG1RSTF) == (RCC_MC_RSTSCLRR_WWDG1RSTF));
5495 }
5496 
5497 /**
5498   * @brief  Check if RCC flag Independent Watchdog 2 reset is set or not.
5499   * @rmtoll MC_RSTSCLRR   IWDG2RSTF      LL_RCC_IsActiveFlag_IWDG2RST
5500   * @retval State of bit (1 or 0).
5501   */
LL_RCC_IsActiveFlag_IWDG2RST(void)5502 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
5503 {
5504   return (READ_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_IWDG2RSTF) == (RCC_MC_RSTSCLRR_IWDG2RSTF));
5505 }
5506 
5507 /**
5508   * @brief  Check if RCC flag Independent Watchdog 1 reset is set or not.
5509   * @rmtoll MC_RSTSCLRR   IWDG1RSTF      LL_RCC_IsActiveFlag_IWDG1RST
5510   * @retval State of bit (1 or 0).
5511   */
LL_RCC_IsActiveFlag_IWDG1RST(void)5512 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
5513 {
5514   return (READ_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_IWDG1RSTF) == (RCC_MC_RSTSCLRR_IWDG1RSTF));
5515 }
5516 
5517 /**
5518   * @brief  Check if RCC flag MCU System reset is set or not.
5519   * @rmtoll MC_RSTSCLRR   MCSYSRSTF      LL_RCC_IsActiveFlag_MCSYSRST
5520   * @retval State of bit (1 or 0).
5521   */
LL_RCC_IsActiveFlag_MCSYSRST(void)5522 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCSYSRST(void)
5523 {
5524   return (READ_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_MCSYSRSTF) == (RCC_MC_RSTSCLRR_MCSYSRSTF));
5525 }
5526 
5527 /**
5528   * @brief  Check if RCC flag MPU System reset is set or not.
5529   * @rmtoll MC_RSTSCLRR   MPSYSRSTF      LL_RCC_IsActiveFlag_MPSYSRST
5530   * @retval State of bit (1 or 0).
5531   */
LL_RCC_IsActiveFlag_MPSYSRST(void)5532 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MPSYSRST(void)
5533 {
5534   return (READ_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_MPSYSRSTF) == (RCC_MC_RSTSCLRR_MPSYSRSTF));
5535 }
5536 
5537 /**
5538   * @brief  Check if RCC flag MCU reset is set or not.
5539   * @rmtoll MC_RSTSCLRR   MCURSTF      LL_RCC_IsActiveFlag_MCURST
5540   * @retval State of bit (1 or 0).
5541   */
LL_RCC_IsActiveFlag_MCURST(void)5542 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCURST(void)
5543 {
5544   return (READ_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_MCURSTF) == (RCC_MC_RSTSCLRR_MCURSTF));
5545 }
5546 
5547 /**
5548   * @brief  Check if RCC flag VDDCORE reset is set or not.
5549   * @rmtoll MC_RSTSCLRR   VCORERSTF      LL_RCC_IsActiveFlag_VCORERST
5550   * @retval State of bit (1 or 0).
5551   */
LL_RCC_IsActiveFlag_VCORERST(void)5552 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_VCORERST(void)
5553 {
5554   return (READ_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_VCORERSTF) == (RCC_MC_RSTSCLRR_VCORERSTF));
5555 }
5556 
5557 /**
5558   * @brief  Check if RCC flag HSE CSS reset is set or not.
5559   * @rmtoll MC_RSTSCLRR   HCSSRSTF      LL_RCC_IsActiveFlag_HCSSRST
5560   * @retval State of bit (1 or 0).
5561   */
LL_RCC_IsActiveFlag_HCSSRST(void)5562 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HCSSRST(void)
5563 {
5564   return (READ_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_HCSSRSTF) == (RCC_MC_RSTSCLRR_HCSSRSTF));
5565 }
5566 
5567 /**
5568   * @brief  Check if RCC flag NRST (PAD) reset is set or not.
5569   * @rmtoll MC_RSTSCLRR   PADRSTF      LL_RCC_IsActiveFlag_PADRSTF
5570   * @retval State of bit (1 or 0).
5571   */
LL_RCC_IsActiveFlag_PADRST(void)5572 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PADRST(void)
5573 {
5574   return (READ_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_PADRSTF) == (RCC_MC_RSTSCLRR_PADRSTF));
5575 }
5576 
5577 /**
5578   * @brief  Check if RCC flag BOR reset is set or not.
5579   * @rmtoll MC_RSTSCLRR   BORRSTF      LL_RCC_IsActiveFlag_BORRSTF
5580   * @retval State of bit (1 or 0).
5581   */
LL_RCC_IsActiveFlag_BORRST(void)5582 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
5583 {
5584   return (READ_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_BORRSTF) == (RCC_MC_RSTSCLRR_BORRSTF));
5585 }
5586 
5587 /**
5588   * @brief  Check if RCC flag POR/PDR reset is set or not.
5589   * @rmtoll MC_RSTSCLRR   PORRSTF      LL_RCC_IsActiveFlag_PORRST
5590   * @retval State of bit (1 or 0).
5591   */
LL_RCC_IsActiveFlag_PORRST(void)5592 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
5593 {
5594   return (READ_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_PORRSTF) == (RCC_MC_RSTSCLRR_PORRSTF));
5595 }
5596 
5597 /**
5598   * @brief  Set MC_RSTSCLRR bits to clear the reset flags.
5599   * @rmtoll MC_RSTSCLRR      LL_RCC_MC_RSTSCLRR_ALL       LL_RCC_ClearResetFlags
5600   * @retval None
5601   */
LL_RCC_ClearResetFlags(void)5602 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
5603 {
5604   WRITE_REG(RCC->MC_RSTSCLRR, LL_RCC_MC_RSTSCLRR_ALL);
5605 }
5606 
5607 /**
5608   * @}
5609   */
5610 
5611 /** @defgroup RCC_LL_EF_IT_Management IT Management
5612   * @{
5613   */
5614 
5615 /**
5616   * @brief  Enable LSI ready interrupt
5617   * @rmtoll MC_CIER      LSIRDYIE      LL_RCC_EnableIT_LSIRDY
5618   * @retval None
5619   */
LL_RCC_EnableIT_LSIRDY(void)5620 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
5621 {
5622   SET_BIT(RCC->MC_CIER, RCC_MC_CIER_LSIRDYIE);
5623 }
5624 
5625 /**
5626   * @brief  Enable LSE ready interrupt
5627   * @rmtoll MC_CIER      LSERDYIE      LL_RCC_EnableIT_LSERDY
5628   * @retval None
5629   */
LL_RCC_EnableIT_LSERDY(void)5630 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
5631 {
5632   SET_BIT(RCC->MC_CIER, RCC_MC_CIER_LSERDYIE);
5633 }
5634 
5635 /**
5636   * @brief  Enable HSI ready interrupt
5637   * @rmtoll MC_CIER      HSIRDYIE      LL_RCC_EnableIT_HSIRDY
5638   * @retval None
5639   */
LL_RCC_EnableIT_HSIRDY(void)5640 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
5641 {
5642   SET_BIT(RCC->MC_CIER, RCC_MC_CIER_HSIRDYIE);
5643 }
5644 
5645 /**
5646   * @brief  Enable HSE ready interrupt
5647   * @rmtoll MC_CIER      HSERDYIE      LL_RCC_EnableIT_HSERDY
5648   * @retval None
5649   */
LL_RCC_EnableIT_HSERDY(void)5650 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
5651 {
5652   SET_BIT(RCC->MC_CIER, RCC_MC_CIER_HSERDYIE);
5653 }
5654 
5655 /**
5656   * @brief  Enable CSI ready interrupt
5657   * @rmtoll MC_CIER      CSIRDYIE      LL_RCC_EnableIT_CSIRDY
5658   * @retval None
5659   */
LL_RCC_EnableIT_CSIRDY(void)5660 __STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
5661 {
5662   SET_BIT(RCC->MC_CIER, RCC_MC_CIER_CSIRDYIE);
5663 }
5664 
5665 /**
5666   * @brief  Enable PLL1 ready interrupt
5667   * @rmtoll MC_CIER      PLLR1DYIE      LL_RCC_EnableIT_PLL1RDY
5668   * @retval None
5669   */
LL_RCC_EnableIT_PLL1RDY(void)5670 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
5671 {
5672   SET_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL1DYIE);
5673 }
5674 
5675 /**
5676   * @brief  Enable PLL2 ready interrupt
5677   * @rmtoll MC_CIER      PLLR2DYIE      LL_RCC_EnableIT_PLL2RDY
5678   * @retval None
5679   */
LL_RCC_EnableIT_PLL2RDY(void)5680 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
5681 {
5682   SET_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL2DYIE);
5683 }
5684 
5685 /**
5686   * @brief  Enable PLL3 ready interrupt
5687   * @rmtoll MC_CIER      PLLR3DYIE      LL_RCC_EnableIT_PLL3RDY
5688   * @retval None
5689   */
LL_RCC_EnableIT_PLL3RDY(void)5690 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
5691 {
5692   SET_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL3DYIE);
5693 }
5694 
5695 /**
5696   * @brief  Enable PLL4 ready interrupt
5697   * @rmtoll MC_CIER      PLLR3DYIE      LL_RCC_EnableIT_PLL4RDY
5698   * @retval None
5699   */
LL_RCC_EnableIT_PLL4RDY(void)5700 __STATIC_INLINE void LL_RCC_EnableIT_PLL4RDY(void)
5701 {
5702   SET_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL4DYIE);
5703 }
5704 
5705 /**
5706   * @brief  Enable LSE clock security system interrupt
5707   * @rmtoll MC_CIER      LSECSSIE      LL_RCC_EnableIT_LSECSS
5708   * @retval None
5709   */
LL_RCC_EnableIT_LSECSS(void)5710 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
5711 {
5712   SET_BIT(RCC->MC_CIER, RCC_MC_CIER_LSECSSIE);
5713 }
5714 
5715 /**
5716   * @brief  Enable Wake up from CStop interrupt
5717   * @rmtoll MC_CIER      WKUPIE      LL_RCC_EnableIT_WKUP
5718   * @retval None
5719   */
LL_RCC_EnableIT_WKUP(void)5720 __STATIC_INLINE void LL_RCC_EnableIT_WKUP(void)
5721 {
5722   SET_BIT(RCC->MC_CIER, RCC_MC_CIER_WKUPIE);
5723 }
5724 
5725 /**
5726   * @brief  Disable LSI ready interrupt
5727   * @rmtoll MC_CIER      LSIRDYIE      LL_RCC_DisableIT_LSIRDY
5728   * @retval None
5729   */
LL_RCC_DisableIT_LSIRDY(void)5730 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
5731 {
5732   CLEAR_BIT(RCC->MC_CIER, RCC_MC_CIER_LSIRDYIE);
5733 }
5734 
5735 /**
5736   * @brief  Disable LSE ready interrupt
5737   * @rmtoll MC_CIER      LSERDYIE      LL_RCC_DisableIT_LSERDY
5738   * @retval None
5739   */
LL_RCC_DisableIT_LSERDY(void)5740 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
5741 {
5742   CLEAR_BIT(RCC->MC_CIER, RCC_MC_CIER_LSERDYIE);
5743 }
5744 
5745 /**
5746   * @brief  Disable HSI ready interrupt
5747   * @rmtoll MC_CIER      HSIRDYIE      LL_RCC_DisableIT_HSIRDY
5748   * @retval None
5749   */
LL_RCC_DisableIT_HSIRDY(void)5750 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
5751 {
5752   CLEAR_BIT(RCC->MC_CIER, RCC_MC_CIER_HSIRDYIE);
5753 }
5754 
5755 /**
5756   * @brief  Disable HSE ready interrupt
5757   * @rmtoll MC_CIER      HSERDYIE      LL_RCC_DisableIT_HSERDY
5758   * @retval None
5759   */
LL_RCC_DisableIT_HSERDY(void)5760 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
5761 {
5762   CLEAR_BIT(RCC->MC_CIER, RCC_MC_CIER_HSERDYIE);
5763 }
5764 
5765 /**
5766   * @brief  Disable CSI ready interrupt
5767   * @rmtoll MC_CIER      CSIRDYIE      LL_RCC_DisableIT_CSIRDY
5768   * @retval None
5769   */
LL_RCC_DisableIT_CSIRDY(void)5770 __STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
5771 {
5772   CLEAR_BIT(RCC->MC_CIER, RCC_MC_CIER_CSIRDYIE);
5773 }
5774 
5775 /**
5776   * @brief  Disable PLL1 ready interrupt
5777   * @rmtoll MC_CIER      PLLR1DYIE      LL_RCC_DisableIT_PLL1RDY
5778   * @retval None
5779   */
LL_RCC_DisableIT_PLL1RDY(void)5780 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
5781 {
5782   CLEAR_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL1DYIE);
5783 }
5784 
5785 /**
5786   * @brief  Disable PLL2 ready interrupt
5787   * @rmtoll MC_CIER      PLLR2DYIE      LL_RCC_DisableIT_PLL2RDY
5788   * @retval None
5789   */
LL_RCC_DisableIT_PLL2RDY(void)5790 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
5791 {
5792   CLEAR_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL2DYIE);
5793 }
5794 
5795 /**
5796   * @brief  Disable PLL3 ready interrupt
5797   * @rmtoll MC_CIER      PLLR3DYIE      LL_RCC_DisableIT_PLL3RDY
5798   * @retval None
5799   */
LL_RCC_DisableIT_PLL3RDY(void)5800 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
5801 {
5802   CLEAR_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL3DYIE);
5803 }
5804 
5805 /**
5806   * @brief  Disable PLL4 ready interrupt
5807   * @rmtoll MC_CIER      PLLR3DYIE      LL_RCC_DisableIT_PLL4RDY
5808   * @retval None
5809   */
LL_RCC_DisableIT_PLL4RDY(void)5810 __STATIC_INLINE void LL_RCC_DisableIT_PLL4RDY(void)
5811 {
5812   CLEAR_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL4DYIE);
5813 }
5814 
5815 /**
5816   * @brief  Disable LSE clock security system interrupt
5817   * @rmtoll MC_CIER      LSECSSIE      LL_RCC_DisableIT_LSECSS
5818   * @retval None
5819   */
LL_RCC_DisableIT_LSECSS(void)5820 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
5821 {
5822   CLEAR_BIT(RCC->MC_CIER, RCC_MC_CIER_LSECSSIE);
5823 }
5824 
5825 /**
5826   * @brief  Disable Wake up from CStop interrupt
5827   * @rmtoll MC_CIER      WKUPIE      LL_RCC_DisableIT_WKUP
5828   * @retval None
5829   */
LL_RCC_DisableIT_WKUP(void)5830 __STATIC_INLINE void LL_RCC_DisableIT_WKUP(void)
5831 {
5832   CLEAR_BIT(RCC->MC_CIER, RCC_MC_CIER_WKUPIE);
5833 }
5834 
5835 /**
5836   * @brief  Checks if LSI ready interrupt source is enabled or disabled.
5837   * @rmtoll MC_CIER      LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
5838   * @retval State of bit (1 or 0).
5839   */
LL_RCC_IsEnabledIT_LSIRDY(void)5840 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
5841 {
5842   return (READ_BIT(RCC->MC_CIER, RCC_MC_CIER_LSIRDYIE) == (RCC_MC_CIER_LSIRDYIE));
5843 }
5844 
5845 /**
5846   * @brief  Checks if LSE ready interrupt source is enabled or disabled.
5847   * @rmtoll MC_CIER      LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
5848   * @retval State of bit (1 or 0).
5849   */
LL_RCC_IsEnabledIT_LSERDY(void)5850 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
5851 {
5852   return (READ_BIT(RCC->MC_CIER, RCC_MC_CIER_LSERDYIE) == (RCC_MC_CIER_LSERDYIE));
5853 }
5854 
5855 /**
5856   * @brief  Checks if HSI ready interrupt source is enabled or disabled.
5857   * @rmtoll MC_CIER      HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
5858   * @retval State of bit (1 or 0).
5859   */
LL_RCC_IsEnabledIT_HSIRDY(void)5860 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
5861 {
5862   return (READ_BIT(RCC->MC_CIER, RCC_MC_CIER_HSIRDYIE) == (RCC_MC_CIER_HSIRDYIE));
5863 }
5864 
5865 /**
5866   * @brief  Checks if HSE ready interrupt source is enabled or disabled.
5867   * @rmtoll MC_CIER      HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
5868   * @retval State of bit (1 or 0).
5869   */
LL_RCC_IsEnabledIT_HSERDY(void)5870 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
5871 {
5872   return (READ_BIT(RCC->MC_CIER, RCC_MC_CIER_HSERDYIE) == (RCC_MC_CIER_HSERDYIE));
5873 }
5874 
5875 /**
5876   * @brief  Checks if CSI ready interrupt source is enabled or disabled.
5877   * @rmtoll MC_CIER      CSIRDYIE      LL_RCC_IsEnabledIT_CSIRDY
5878   * @retval State of bit (1 or 0).
5879   */
LL_RCC_IsEnabledIT_CSIRDY(void)5880 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_CSIRDY(void)
5881 {
5882   return (READ_BIT(RCC->MC_CIER, RCC_MC_CIER_CSIRDYIE) == (RCC_MC_CIER_CSIRDYIE));
5883 }
5884 
5885 /**
5886   * @brief  Checks if PLL1 ready interrupt source is enabled or disabled.
5887   * @rmtoll MC_CIER      PLL1DYIE      LL_RCC_IsEnabledIT_PLL1RDY
5888   * @retval State of bit (1 or 0).
5889   */
LL_RCC_IsEnabledIT_PLL1RDY(void)5890 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void)
5891 {
5892   return (READ_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL1DYIE) == (RCC_MC_CIER_PLL1DYIE));
5893 }
5894 
5895 /**
5896   * @brief  Checks if PLL2 ready interrupt source is enabled or disabled.
5897   * @rmtoll MC_CIER      PLL2DYIE      LL_RCC_IsEnabledIT_PLL2RDY
5898   * @retval State of bit (1 or 0).
5899   */
LL_RCC_IsEnabledIT_PLL2RDY(void)5900 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
5901 {
5902   return (READ_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL2DYIE) == (RCC_MC_CIER_PLL2DYIE));
5903 }
5904 
5905 /**
5906   * @brief  Checks if PLL3 ready interrupt source is enabled or disabled.
5907   * @rmtoll MC_CIER      PLL3DYIE      LL_RCC_IsEnabledIT_PLL3RDY
5908   * @retval State of bit (1 or 0).
5909   */
LL_RCC_IsEnabledIT_PLL3RDY(void)5910 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void)
5911 {
5912   return (READ_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL3DYIE) == (RCC_MC_CIER_PLL3DYIE));
5913 }
5914 
5915 /**
5916   * @brief  Checks if PLL4 ready interrupt source is enabled or disabled.
5917   * @rmtoll MC_CIER      PLL4DYIE      LL_RCC_IsEnabledIT_PLL4RDY
5918   * @retval State of bit (1 or 0).
5919   */
LL_RCC_IsEnabledIT_PLL4RDY(void)5920 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL4RDY(void)
5921 {
5922   return (READ_BIT(RCC->MC_CIER, RCC_MC_CIER_PLL4DYIE) == (RCC_MC_CIER_PLL4DYIE));
5923 }
5924 
5925 /**
5926   * @brief  Checks if LSECSS interrupt source is enabled or disabled.
5927   * @rmtoll MC_CIER      LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
5928   * @retval State of bit (1 or 0).
5929   */
LL_RCC_IsEnabledIT_LSECSS(void)5930 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
5931 {
5932   return (READ_BIT(RCC->MC_CIER, RCC_MC_CIER_LSECSSIE) == (RCC_MC_CIER_LSECSSIE));
5933 }
5934 
5935 /**
5936   * @brief  Checks if Wake up from CStop source is enabled or disabled.
5937   * @rmtoll MC_CIER      WKUPIE      LL_RCC_IsEnabledIT_LSECSS
5938   * @retval State of bit (1 or 0).
5939   */
LL_RCC_IsEnabledIT_WKUP(void)5940 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_WKUP(void)
5941 {
5942   return (READ_BIT(RCC->MC_CIER, RCC_MC_CIER_WKUPIE) == (RCC_MC_CIER_WKUPIE));
5943 }
5944 
5945 /**
5946   * @}
5947   */
5948 
5949 #if defined(USE_FULL_LL_DRIVER)
5950 /** @defgroup RCC_LL_EF_Init De-initialization function
5951   * @{
5952   */
5953 ErrorStatus LL_RCC_DeInit(void);
5954 /**
5955   * @}
5956   */
5957 
5958 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
5959   * @{
5960   */
5961 uint32_t    LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACV, uint32_t PQR);
5962 
5963 void        LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
5964 void        LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
5965 void        LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
5966 void        LL_RCC_GetPLL4ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
5967 void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
5968 
5969 uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
5970 uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
5971 uint32_t    LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
5972 uint32_t    LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
5973 uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
5974 uint32_t    LL_RCC_GetETHClockFreq(uint32_t ETHxSource);
5975 uint32_t    LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);
5976 uint32_t    LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
5977 #if defined(FDCAN1)
5978 uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
5979 #endif /*FDCAN1*/
5980 uint32_t    LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
5981 uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
5982 uint32_t    LL_RCC_GetUSBPHYClockFreq(uint32_t USBPHYxSource);
5983 uint32_t    LL_RCC_GetUSBOClockFreq(uint32_t USBOxSource);
5984 uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
5985 uint32_t    LL_RCC_GetCKPERClockFreq(uint32_t CKPERxSource);
5986 uint32_t    LL_RCC_GetSTGENClockFreq(uint32_t STGENxSource);
5987 #if defined(DSI)
5988 uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
5989 #endif /*DSI*/
5990 uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
5991 uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
5992 uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
5993 uint32_t    LL_RCC_GetLTDCClockFreq(void);
5994 uint32_t    LL_RCC_GetRTCClockFreq(void);
5995 uint32_t    LL_RCC_GetTIMGClockFreq(uint32_t TIMGxPrescaler);
5996 /**
5997   * @}
5998   */
5999 #endif /* USE_FULL_LL_DRIVER */
6000 
6001 /**
6002   * @}
6003   */
6004 /* End of RCC_LL_Exported_Functions */
6005 
6006 /**
6007   * @}
6008   */
6009 
6010 #endif /* defined(RCC) */
6011 
6012 /**
6013   * @}
6014   */
6015 
6016 #ifdef __cplusplus
6017 }
6018 #endif
6019 
6020 #endif /* STM32MP1xx_LL_RCC_H */
6021