1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef __STM32F4xx_LL_RCC_H
20 #define __STM32F4xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32f4xx.h"
28
29 /** @addtogroup STM32F4xx_LL_Driver
30 * @{
31 */
32
33 #if defined(RCC)
34
35 /** @defgroup RCC_LL RCC
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
42 * @{
43 */
44
45 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
46 static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
47 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
48
49 /**
50 * @}
51 */
52 /* Private constants ---------------------------------------------------------*/
53 /* Private macros ------------------------------------------------------------*/
54 #if defined(USE_FULL_LL_DRIVER)
55 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
56 * @{
57 */
58 /**
59 * @}
60 */
61 #endif /*USE_FULL_LL_DRIVER*/
62 /* Exported types ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
65 * @{
66 */
67
68 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
69 * @{
70 */
71
72 /**
73 * @brief RCC Clocks Frequency Structure
74 */
75 typedef struct
76 {
77 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
78 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
79 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
80 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
81 } LL_RCC_ClocksTypeDef;
82
83 /**
84 * @}
85 */
86
87 /**
88 * @}
89 */
90 #endif /* USE_FULL_LL_DRIVER */
91
92 /* Exported constants --------------------------------------------------------*/
93 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
94 * @{
95 */
96
97 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
98 * @brief Defines used to adapt values of different oscillators
99 * @note These values could be modified in the user environment according to
100 * HW set-up.
101 * @{
102 */
103 #if !defined (HSE_VALUE)
104 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
105 #endif /* HSE_VALUE */
106
107 #if !defined (HSI_VALUE)
108 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
109 #endif /* HSI_VALUE */
110
111 #if !defined (LSE_VALUE)
112 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
113 #endif /* LSE_VALUE */
114
115 #if !defined (LSI_VALUE)
116 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
117 #endif /* LSI_VALUE */
118
119 #if !defined (EXTERNAL_CLOCK_VALUE)
120 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
121 #endif /* EXTERNAL_CLOCK_VALUE */
122 /**
123 * @}
124 */
125
126 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
127 * @brief Flags defines which can be used with LL_RCC_WriteReg function
128 * @{
129 */
130 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
131 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
132 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
133 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
134 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
135 #if defined(RCC_PLLI2S_SUPPORT)
136 #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
137 #endif /* RCC_PLLI2S_SUPPORT */
138 #if defined(RCC_PLLSAI_SUPPORT)
139 #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */
140 #endif /* RCC_PLLSAI_SUPPORT */
141 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
142 /**
143 * @}
144 */
145
146 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
147 * @brief Flags defines which can be used with LL_RCC_ReadReg function
148 * @{
149 */
150 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
151 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
152 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
153 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
154 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
155 #if defined(RCC_PLLI2S_SUPPORT)
156 #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
157 #endif /* RCC_PLLI2S_SUPPORT */
158 #if defined(RCC_PLLSAI_SUPPORT)
159 #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */
160 #endif /* RCC_PLLSAI_SUPPORT */
161 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
162 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
163 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
164 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
165 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
166 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
167 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
168 #if defined(RCC_CSR_BORRSTF)
169 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
170 #endif /* RCC_CSR_BORRSTF */
171 /**
172 * @}
173 */
174
175 /** @defgroup RCC_LL_EC_IT IT Defines
176 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
177 * @{
178 */
179 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
180 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
181 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
182 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
183 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
184 #if defined(RCC_PLLI2S_SUPPORT)
185 #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
186 #endif /* RCC_PLLI2S_SUPPORT */
187 #if defined(RCC_PLLSAI_SUPPORT)
188 #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */
189 #endif /* RCC_PLLSAI_SUPPORT */
190 /**
191 * @}
192 */
193
194 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
195 * @{
196 */
197 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
198 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
199 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
200 #if defined(RCC_CFGR_SW_PLLR)
201 #define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */
202 #endif /* RCC_CFGR_SW_PLLR */
203 /**
204 * @}
205 */
206
207 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
208 * @{
209 */
210 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
211 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
212 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
213 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
214 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */
215 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
216 /**
217 * @}
218 */
219
220 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
221 * @{
222 */
223 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
224 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
225 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
226 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
227 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
228 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
229 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
230 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
231 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
232 /**
233 * @}
234 */
235
236 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
237 * @{
238 */
239 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
240 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
241 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
242 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
243 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
244 /**
245 * @}
246 */
247
248 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
249 * @{
250 */
251 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
252 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
253 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
254 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
255 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
256 /**
257 * @}
258 */
259
260 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
261 * @{
262 */
263 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
264 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
265 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
266 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
267 #if defined(RCC_CFGR_MCO2)
268 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
269 #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
270 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
271 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
272 #endif /* RCC_CFGR_MCO2 */
273 /**
274 * @}
275 */
276
277 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
278 * @{
279 */
280 #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
281 #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
282 #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
283 #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
284 #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
285 #if defined(RCC_CFGR_MCO2PRE)
286 #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
287 #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
288 #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
289 #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
290 #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
291 #endif /* RCC_CFGR_MCO2PRE */
292 /**
293 * @}
294 */
295
296 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
297 * @{
298 */
299 #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
300 #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
301 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
302 #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
303 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
304 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
305 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
306 #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
307 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
308 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
309 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
310 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
311 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
312 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
313 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
314 #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
315 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
316 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
317 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
318 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
319 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
320 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
321 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
322 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
323 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
324 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
325 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
326 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
327 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
328 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
329 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
330 /**
331 * @}
332 */
333
334 #if defined(USE_FULL_LL_DRIVER)
335 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
336 * @{
337 */
338 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
339 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
340 /**
341 * @}
342 */
343 #endif /* USE_FULL_LL_DRIVER */
344
345 #if defined(FMPI2C1)
346 /** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection
347 * @{
348 */
349 #define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */
350 #define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */
351 #define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */
352 /**
353 * @}
354 */
355 #endif /* FMPI2C1 */
356
357 #if defined(LPTIM1)
358 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
359 * @{
360 */
361 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */
362 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */
363 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */
364 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */
365 /**
366 * @}
367 */
368 #endif /* LPTIM1 */
369
370 #if defined(SAI1)
371 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
372 * @{
373 */
374 #if defined(RCC_DCKCFGR_SAI1SRC)
375 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */
376 #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */
377 #define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */
378 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */
379 #endif /* RCC_DCKCFGR_SAI1SRC */
380 #if defined(RCC_DCKCFGR_SAI2SRC)
381 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */
382 #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */
383 #define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */
384 #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */
385 #endif /* RCC_DCKCFGR_SAI2SRC */
386 #if defined(RCC_DCKCFGR_SAI1ASRC)
387 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
388 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */
389 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */
390 #define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */
391 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */
392 #else
393 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */
394 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */
395 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */
396 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
397 #endif /* RCC_DCKCFGR_SAI1ASRC */
398 #if defined(RCC_DCKCFGR_SAI1BSRC)
399 #if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
400 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */
401 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */
402 #define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */
403 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */
404 #else
405 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */
406 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */
407 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */
408 #endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
409 #endif /* RCC_DCKCFGR_SAI1BSRC */
410 /**
411 * @}
412 */
413 #endif /* SAI1 */
414
415 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
416 /** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection
417 * @{
418 */
419 #define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */
420 #if defined(RCC_DCKCFGR_SDIOSEL)
421 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */
422 #else
423 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */
424 #endif /* RCC_DCKCFGR_SDIOSEL */
425 /**
426 * @}
427 */
428 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
429
430 #if defined(DSI)
431 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
432 * @{
433 */
434 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
435 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */
436 /**
437 * @}
438 */
439 #endif /* DSI */
440
441 #if defined(CEC)
442 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
443 * @{
444 */
445 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */
446 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */
447 /**
448 * @}
449 */
450 #endif /* CEC */
451
452 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
453 * @{
454 */
455 #if defined(RCC_CFGR_I2SSRC)
456 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
457 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
458 #endif /* RCC_CFGR_I2SSRC */
459 #if defined(RCC_DCKCFGR_I2SSRC)
460 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */
461 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
462 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */
463 #endif /* RCC_DCKCFGR_I2SSRC */
464 #if defined(RCC_DCKCFGR_I2S1SRC)
465 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */
466 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
467 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */
468 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */
469 #endif /* RCC_DCKCFGR_I2S1SRC */
470 #if defined(RCC_DCKCFGR_I2S2SRC)
471 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */
472 #define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */
473 #define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */
474 #define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */
475 #endif /* RCC_DCKCFGR_I2S2SRC */
476 /**
477 * @}
478 */
479
480 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
481 /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
482 * @{
483 */
484 #if defined(RCC_DCKCFGR_CK48MSEL)
485 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
486 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
487 #endif /* RCC_DCKCFGR_CK48MSEL */
488 #if defined(RCC_DCKCFGR2_CK48MSEL)
489 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
490 #if defined(RCC_PLLSAI_SUPPORT)
491 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
492 #endif /* RCC_PLLSAI_SUPPORT */
493 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
494 #define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */
495 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
496 #endif /* RCC_DCKCFGR2_CK48MSEL */
497 /**
498 * @}
499 */
500
501 #if defined(RNG)
502 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
503 * @{
504 */
505 #define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */
506 #if defined(RCC_PLLSAI_SUPPORT)
507 #define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */
508 #endif /* RCC_PLLSAI_SUPPORT */
509 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
510 #define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */
511 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
512 /**
513 * @}
514 */
515 #endif /* RNG */
516
517 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
518 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
519 * @{
520 */
521 #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */
522 #if defined(RCC_PLLSAI_SUPPORT)
523 #define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */
524 #endif /* RCC_PLLSAI_SUPPORT */
525 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
526 #define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */
527 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
528 /**
529 * @}
530 */
531 #endif /* USB_OTG_FS || USB_OTG_HS */
532
533 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
534
535 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
536 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
537 * @{
538 */
539 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */
540 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */
541 #if defined(DFSDM2_Channel0)
542 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */
543 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */
544 #endif /* DFSDM2_Channel0 */
545 /**
546 * @}
547 */
548
549 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
550 * @{
551 */
552 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */
553 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */
554 #if defined(DFSDM2_Channel0)
555 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */
556 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */
557 #endif /* DFSDM2_Channel0 */
558 /**
559 * @}
560 */
561 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
562
563 #if defined(FMPI2C1)
564 /** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source
565 * @{
566 */
567 #define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */
568 /**
569 * @}
570 */
571 #endif /* FMPI2C1 */
572
573 #if defined(SPDIFRX)
574 /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
575 * @{
576 */
577 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */
578 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */
579 /**
580 * @}
581 */
582 #endif /* SPDIFRX */
583
584 #if defined(LPTIM1)
585 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
586 * @{
587 */
588 #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
589 /**
590 * @}
591 */
592 #endif /* LPTIM1 */
593
594 #if defined(SAI1)
595 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
596 * @{
597 */
598 #if defined(RCC_DCKCFGR_SAI1ASRC)
599 #define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */
600 #endif /* RCC_DCKCFGR_SAI1ASRC */
601 #if defined(RCC_DCKCFGR_SAI1BSRC)
602 #define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */
603 #endif /* RCC_DCKCFGR_SAI1BSRC */
604 #if defined(RCC_DCKCFGR_SAI1SRC)
605 #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */
606 #endif /* RCC_DCKCFGR_SAI1SRC */
607 #if defined(RCC_DCKCFGR_SAI2SRC)
608 #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */
609 #endif /* RCC_DCKCFGR_SAI2SRC */
610 /**
611 * @}
612 */
613 #endif /* SAI1 */
614
615 #if defined(SDIO)
616 /** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source
617 * @{
618 */
619 #if defined(RCC_DCKCFGR_SDIOSEL)
620 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */
621 #elif defined(RCC_DCKCFGR2_SDIOSEL)
622 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */
623 #else
624 #define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */
625 #endif /* RCC_DCKCFGR_SDIOSEL */
626 /**
627 * @}
628 */
629 #endif /* SDIO */
630
631 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
632 /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
633 * @{
634 */
635 #if defined(RCC_DCKCFGR_CK48MSEL)
636 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */
637 #endif /* RCC_DCKCFGR_CK48MSEL */
638 #if defined(RCC_DCKCFGR2_CK48MSEL)
639 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
640 #endif /* RCC_DCKCFGR_CK48MSEL */
641 /**
642 * @}
643 */
644 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
645
646 #if defined(RNG)
647 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
648 * @{
649 */
650 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
651 #define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */
652 #else
653 #define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */
654 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
655 /**
656 * @}
657 */
658 #endif /* RNG */
659
660 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
661 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
662 * @{
663 */
664 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
665 #define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */
666 #else
667 #define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */
668 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
669 /**
670 * @}
671 */
672 #endif /* USB_OTG_FS || USB_OTG_HS */
673
674 #if defined(CEC)
675 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
676 * @{
677 */
678 #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
679 /**
680 * @}
681 */
682 #endif /* CEC */
683
684 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
685 * @{
686 */
687 #if defined(RCC_CFGR_I2SSRC)
688 #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */
689 #endif /* RCC_CFGR_I2SSRC */
690 #if defined(RCC_DCKCFGR_I2SSRC)
691 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */
692 #endif /* RCC_DCKCFGR_I2SSRC */
693 #if defined(RCC_DCKCFGR_I2S1SRC)
694 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */
695 #endif /* RCC_DCKCFGR_I2S1SRC */
696 #if defined(RCC_DCKCFGR_I2S2SRC)
697 #define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */
698 #endif /* RCC_DCKCFGR_I2S2SRC */
699 /**
700 * @}
701 */
702
703 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
704 /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
705 * @{
706 */
707 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */
708 #if defined(DFSDM2_Channel0)
709 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */
710 #endif /* DFSDM2_Channel0 */
711 /**
712 * @}
713 */
714
715 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
716 * @{
717 */
718 #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */
719 #if defined(DFSDM2_Channel0)
720 #define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */
721 #endif /* DFSDM2_Channel0 */
722 /**
723 * @}
724 */
725 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
726
727 #if defined(SPDIFRX)
728 /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
729 * @{
730 */
731 #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */
732 /**
733 * @}
734 */
735 #endif /* SPDIFRX */
736
737 #if defined(DSI)
738 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
739 * @{
740 */
741 #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */
742 /**
743 * @}
744 */
745 #endif /* DSI */
746
747 #if defined(LTDC)
748 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
749 * @{
750 */
751 #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */
752 /**
753 * @}
754 */
755 #endif /* LTDC */
756
757
758 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
759 * @{
760 */
761 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
762 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
763 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
764 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
765 /**
766 * @}
767 */
768
769 #if defined(RCC_DCKCFGR_TIMPRE)
770 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
771 * @{
772 */
773 #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */
774 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */
775 /**
776 * @}
777 */
778 #endif /* RCC_DCKCFGR_TIMPRE */
779
780 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
781 * @{
782 */
783 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
784 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
785 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
786 #define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */
787 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
788 /**
789 * @}
790 */
791
792 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
793 * @{
794 */
795 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
796 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
797 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
798 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
799 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
800 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
801 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
802 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
803 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
804 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
805 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
806 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
807 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
808 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
809 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
810 #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
811 #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
812 #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
813 #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
814 #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
815 #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
816 #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
817 #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
818 #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
819 #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
820 #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
821 #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
822 #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
823 #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
824 #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
825 #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
826 #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
827 #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
828 #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
829 #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
830 #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
831 #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
832 #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
833 #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
834 #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
835 #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
836 #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
837 #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
838 #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
839 #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
840 #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
841 #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
842 #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
843 #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
844 #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
845 #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
846 #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
847 #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
848 #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
849 #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
850 #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
851 #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
852 #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
853 #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
854 #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
855 #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
856 #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
857 /**
858 * @}
859 */
860
861 #if defined(RCC_PLLCFGR_PLLR)
862 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
863 * @{
864 */
865 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
866 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
867 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
868 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
869 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
870 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
871 /**
872 * @}
873 */
874 #endif /* RCC_PLLCFGR_PLLR */
875
876 #if defined(RCC_DCKCFGR_PLLDIVR)
877 /** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR)
878 * @{
879 */
880 #define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */
881 #define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */
882 #define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */
883 #define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */
884 #define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */
885 #define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */
886 #define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */
887 #define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */
888 #define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */
889 #define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */
890 #define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */
891 #define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */
892 #define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */
893 #define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */
894 #define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */
895 #define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */
896 #define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */
897 #define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */
898 #define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */
899 #define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */
900 #define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */
901 #define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */
902 #define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */
903 #define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */
904 #define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */
905 #define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */
906 #define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */
907 #define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */
908 #define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */
909 #define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */
910 #define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */
911 /**
912 * @}
913 */
914 #endif /* RCC_DCKCFGR_PLLDIVR */
915
916 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
917 * @{
918 */
919 #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
920 #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
921 #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
922 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
923 /**
924 * @}
925 */
926
927 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
928 * @{
929 */
930 #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
931 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
932 #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
933 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
934 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
935 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
936 #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
937 #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
938 #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
939 #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
940 #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
941 #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
942 #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
943 #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
944 /**
945 * @}
946 */
947
948 /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
949 * @{
950 */
951 #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
952 #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
953 /**
954 * @}
955 */
956
957 #if defined(RCC_PLLI2S_SUPPORT)
958 /** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM)
959 * @{
960 */
961 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
962 #define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */
963 #define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */
964 #define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */
965 #define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */
966 #define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */
967 #define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */
968 #define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */
969 #define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */
970 #define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */
971 #define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */
972 #define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */
973 #define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */
974 #define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */
975 #define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */
976 #define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */
977 #define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */
978 #define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */
979 #define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */
980 #define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */
981 #define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */
982 #define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */
983 #define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */
984 #define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */
985 #define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */
986 #define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */
987 #define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */
988 #define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */
989 #define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */
990 #define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */
991 #define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */
992 #define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */
993 #define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */
994 #define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */
995 #define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */
996 #define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */
997 #define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */
998 #define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */
999 #define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */
1000 #define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */
1001 #define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */
1002 #define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */
1003 #define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */
1004 #define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */
1005 #define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */
1006 #define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */
1007 #define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */
1008 #define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */
1009 #define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */
1010 #define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */
1011 #define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */
1012 #define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */
1013 #define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */
1014 #define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */
1015 #define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */
1016 #define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */
1017 #define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */
1018 #define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */
1019 #define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */
1020 #define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */
1021 #define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */
1022 #define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */
1023 #define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */
1024 #else
1025 #define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */
1026 #define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */
1027 #define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */
1028 #define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */
1029 #define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */
1030 #define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */
1031 #define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */
1032 #define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */
1033 #define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */
1034 #define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */
1035 #define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */
1036 #define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */
1037 #define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */
1038 #define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */
1039 #define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */
1040 #define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */
1041 #define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */
1042 #define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */
1043 #define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */
1044 #define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */
1045 #define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */
1046 #define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */
1047 #define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */
1048 #define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */
1049 #define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */
1050 #define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */
1051 #define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */
1052 #define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */
1053 #define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */
1054 #define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */
1055 #define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */
1056 #define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */
1057 #define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */
1058 #define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */
1059 #define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */
1060 #define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */
1061 #define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */
1062 #define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */
1063 #define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */
1064 #define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */
1065 #define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */
1066 #define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */
1067 #define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */
1068 #define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */
1069 #define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */
1070 #define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */
1071 #define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */
1072 #define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */
1073 #define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */
1074 #define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */
1075 #define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */
1076 #define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */
1077 #define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */
1078 #define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */
1079 #define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */
1080 #define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */
1081 #define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */
1082 #define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */
1083 #define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */
1084 #define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */
1085 #define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */
1086 #define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */
1087 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
1088 /**
1089 * @}
1090 */
1091
1092 #if defined(RCC_PLLI2SCFGR_PLLI2SQ)
1093 /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
1094 * @{
1095 */
1096 #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */
1097 #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */
1098 #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */
1099 #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */
1100 #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */
1101 #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */
1102 #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */
1103 #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */
1104 #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */
1105 #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */
1106 #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */
1107 #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */
1108 #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */
1109 #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */
1110 /**
1111 * @}
1112 */
1113 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */
1114
1115 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
1116 /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
1117 * @{
1118 */
1119 #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
1120 #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
1121 #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
1122 #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
1123 #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
1124 #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
1125 #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
1126 #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
1127 #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
1128 #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
1129 #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
1130 #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
1131 #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
1132 #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
1133 #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
1134 #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
1135 #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
1136 #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
1137 #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
1138 #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
1139 #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
1140 #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
1141 #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
1142 #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
1143 #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
1144 #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
1145 #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
1146 #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
1147 #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
1148 #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
1149 #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
1150 #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
1151 /**
1152 * @}
1153 */
1154 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
1155
1156 #if defined(RCC_DCKCFGR_PLLI2SDIVR)
1157 /** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR)
1158 * @{
1159 */
1160 #define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */
1161 #define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */
1162 #define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */
1163 #define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */
1164 #define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */
1165 #define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */
1166 #define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */
1167 #define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */
1168 #define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */
1169 #define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */
1170 #define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */
1171 #define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */
1172 #define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */
1173 #define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */
1174 #define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */
1175 #define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */
1176 #define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */
1177 #define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */
1178 #define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */
1179 #define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */
1180 #define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */
1181 #define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */
1182 #define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */
1183 #define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */
1184 #define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */
1185 #define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */
1186 #define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */
1187 #define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */
1188 #define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */
1189 #define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */
1190 #define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */
1191 /**
1192 * @}
1193 */
1194 #endif /* RCC_DCKCFGR_PLLI2SDIVR */
1195
1196 /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
1197 * @{
1198 */
1199 #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
1200 #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
1201 #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
1202 #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
1203 #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
1204 #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
1205 /**
1206 * @}
1207 */
1208
1209 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
1210 /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
1211 * @{
1212 */
1213 #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */
1214 #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */
1215 #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */
1216 #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */
1217 /**
1218 * @}
1219 */
1220 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
1221 #endif /* RCC_PLLI2S_SUPPORT */
1222
1223 #if defined(RCC_PLLSAI_SUPPORT)
1224 /** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM)
1225 * @{
1226 */
1227 #if defined(RCC_PLLSAICFGR_PLLSAIM)
1228 #define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */
1229 #define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */
1230 #define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */
1231 #define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */
1232 #define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */
1233 #define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */
1234 #define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */
1235 #define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */
1236 #define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */
1237 #define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */
1238 #define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */
1239 #define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */
1240 #define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */
1241 #define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */
1242 #define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */
1243 #define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */
1244 #define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */
1245 #define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */
1246 #define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */
1247 #define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */
1248 #define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */
1249 #define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */
1250 #define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */
1251 #define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */
1252 #define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */
1253 #define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */
1254 #define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */
1255 #define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */
1256 #define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */
1257 #define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */
1258 #define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */
1259 #define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */
1260 #define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */
1261 #define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */
1262 #define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */
1263 #define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */
1264 #define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */
1265 #define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */
1266 #define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */
1267 #define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */
1268 #define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */
1269 #define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */
1270 #define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */
1271 #define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */
1272 #define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */
1273 #define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */
1274 #define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */
1275 #define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */
1276 #define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */
1277 #define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */
1278 #define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */
1279 #define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */
1280 #define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */
1281 #define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */
1282 #define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */
1283 #define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */
1284 #define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */
1285 #define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */
1286 #define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */
1287 #define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */
1288 #define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */
1289 #define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */
1290 #else
1291 #define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */
1292 #define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */
1293 #define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */
1294 #define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */
1295 #define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */
1296 #define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */
1297 #define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */
1298 #define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */
1299 #define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */
1300 #define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */
1301 #define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */
1302 #define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */
1303 #define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */
1304 #define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */
1305 #define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */
1306 #define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */
1307 #define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */
1308 #define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */
1309 #define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */
1310 #define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */
1311 #define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */
1312 #define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */
1313 #define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */
1314 #define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */
1315 #define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */
1316 #define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */
1317 #define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */
1318 #define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */
1319 #define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */
1320 #define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */
1321 #define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */
1322 #define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */
1323 #define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */
1324 #define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */
1325 #define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */
1326 #define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */
1327 #define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */
1328 #define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */
1329 #define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */
1330 #define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */
1331 #define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */
1332 #define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */
1333 #define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */
1334 #define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */
1335 #define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */
1336 #define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */
1337 #define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */
1338 #define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */
1339 #define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */
1340 #define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */
1341 #define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */
1342 #define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */
1343 #define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */
1344 #define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */
1345 #define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */
1346 #define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */
1347 #define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */
1348 #define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */
1349 #define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */
1350 #define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */
1351 #define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */
1352 #define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */
1353 #endif /* RCC_PLLSAICFGR_PLLSAIM */
1354 /**
1355 * @}
1356 */
1357
1358 /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
1359 * @{
1360 */
1361 #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */
1362 #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */
1363 #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */
1364 #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */
1365 #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */
1366 #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */
1367 #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */
1368 #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */
1369 #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */
1370 #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */
1371 #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */
1372 #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */
1373 #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */
1374 #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */
1375 /**
1376 * @}
1377 */
1378
1379 #if defined(RCC_DCKCFGR_PLLSAIDIVQ)
1380 /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
1381 * @{
1382 */
1383 #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
1384 #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
1385 #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
1386 #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
1387 #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
1388 #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
1389 #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
1390 #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
1391 #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
1392 #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
1393 #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
1394 #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
1395 #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
1396 #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
1397 #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
1398 #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
1399 #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
1400 #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
1401 #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
1402 #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
1403 #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
1404 #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
1405 #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
1406 #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
1407 #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
1408 #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
1409 #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
1410 #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
1411 #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
1412 #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
1413 #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
1414 #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
1415 /**
1416 * @}
1417 */
1418 #endif /* RCC_DCKCFGR_PLLSAIDIVQ */
1419
1420 #if defined(RCC_PLLSAICFGR_PLLSAIR)
1421 /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
1422 * @{
1423 */
1424 #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */
1425 #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */
1426 #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */
1427 #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */
1428 #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */
1429 #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */
1430 /**
1431 * @}
1432 */
1433 #endif /* RCC_PLLSAICFGR_PLLSAIR */
1434
1435 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
1436 /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
1437 * @{
1438 */
1439 #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
1440 #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
1441 #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
1442 #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
1443 /**
1444 * @}
1445 */
1446 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
1447
1448 #if defined(RCC_PLLSAICFGR_PLLSAIP)
1449 /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
1450 * @{
1451 */
1452 #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */
1453 #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */
1454 #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */
1455 #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */
1456 /**
1457 * @}
1458 */
1459 #endif /* RCC_PLLSAICFGR_PLLSAIP */
1460 #endif /* RCC_PLLSAI_SUPPORT */
1461 /**
1462 * @}
1463 */
1464
1465 /* Exported macro ------------------------------------------------------------*/
1466 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1467 * @{
1468 */
1469
1470 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1471 * @{
1472 */
1473
1474 /**
1475 * @brief Write a value in RCC register
1476 * @param __REG__ Register to be written
1477 * @param __VALUE__ Value to be written in the register
1478 * @retval None
1479 */
1480 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1481
1482 /**
1483 * @brief Read a value in RCC register
1484 * @param __REG__ Register to be read
1485 * @retval Register value
1486 */
1487 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1488 /**
1489 * @}
1490 */
1491
1492 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1493 * @{
1494 */
1495
1496 /**
1497 * @brief Helper macro to calculate the PLLCLK frequency on system domain
1498 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1499 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1500 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1501 * @param __PLLM__ This parameter can be one of the following values:
1502 * @arg @ref LL_RCC_PLLM_DIV_2
1503 * @arg @ref LL_RCC_PLLM_DIV_3
1504 * @arg @ref LL_RCC_PLLM_DIV_4
1505 * @arg @ref LL_RCC_PLLM_DIV_5
1506 * @arg @ref LL_RCC_PLLM_DIV_6
1507 * @arg @ref LL_RCC_PLLM_DIV_7
1508 * @arg @ref LL_RCC_PLLM_DIV_8
1509 * @arg @ref LL_RCC_PLLM_DIV_9
1510 * @arg @ref LL_RCC_PLLM_DIV_10
1511 * @arg @ref LL_RCC_PLLM_DIV_11
1512 * @arg @ref LL_RCC_PLLM_DIV_12
1513 * @arg @ref LL_RCC_PLLM_DIV_13
1514 * @arg @ref LL_RCC_PLLM_DIV_14
1515 * @arg @ref LL_RCC_PLLM_DIV_15
1516 * @arg @ref LL_RCC_PLLM_DIV_16
1517 * @arg @ref LL_RCC_PLLM_DIV_17
1518 * @arg @ref LL_RCC_PLLM_DIV_18
1519 * @arg @ref LL_RCC_PLLM_DIV_19
1520 * @arg @ref LL_RCC_PLLM_DIV_20
1521 * @arg @ref LL_RCC_PLLM_DIV_21
1522 * @arg @ref LL_RCC_PLLM_DIV_22
1523 * @arg @ref LL_RCC_PLLM_DIV_23
1524 * @arg @ref LL_RCC_PLLM_DIV_24
1525 * @arg @ref LL_RCC_PLLM_DIV_25
1526 * @arg @ref LL_RCC_PLLM_DIV_26
1527 * @arg @ref LL_RCC_PLLM_DIV_27
1528 * @arg @ref LL_RCC_PLLM_DIV_28
1529 * @arg @ref LL_RCC_PLLM_DIV_29
1530 * @arg @ref LL_RCC_PLLM_DIV_30
1531 * @arg @ref LL_RCC_PLLM_DIV_31
1532 * @arg @ref LL_RCC_PLLM_DIV_32
1533 * @arg @ref LL_RCC_PLLM_DIV_33
1534 * @arg @ref LL_RCC_PLLM_DIV_34
1535 * @arg @ref LL_RCC_PLLM_DIV_35
1536 * @arg @ref LL_RCC_PLLM_DIV_36
1537 * @arg @ref LL_RCC_PLLM_DIV_37
1538 * @arg @ref LL_RCC_PLLM_DIV_38
1539 * @arg @ref LL_RCC_PLLM_DIV_39
1540 * @arg @ref LL_RCC_PLLM_DIV_40
1541 * @arg @ref LL_RCC_PLLM_DIV_41
1542 * @arg @ref LL_RCC_PLLM_DIV_42
1543 * @arg @ref LL_RCC_PLLM_DIV_43
1544 * @arg @ref LL_RCC_PLLM_DIV_44
1545 * @arg @ref LL_RCC_PLLM_DIV_45
1546 * @arg @ref LL_RCC_PLLM_DIV_46
1547 * @arg @ref LL_RCC_PLLM_DIV_47
1548 * @arg @ref LL_RCC_PLLM_DIV_48
1549 * @arg @ref LL_RCC_PLLM_DIV_49
1550 * @arg @ref LL_RCC_PLLM_DIV_50
1551 * @arg @ref LL_RCC_PLLM_DIV_51
1552 * @arg @ref LL_RCC_PLLM_DIV_52
1553 * @arg @ref LL_RCC_PLLM_DIV_53
1554 * @arg @ref LL_RCC_PLLM_DIV_54
1555 * @arg @ref LL_RCC_PLLM_DIV_55
1556 * @arg @ref LL_RCC_PLLM_DIV_56
1557 * @arg @ref LL_RCC_PLLM_DIV_57
1558 * @arg @ref LL_RCC_PLLM_DIV_58
1559 * @arg @ref LL_RCC_PLLM_DIV_59
1560 * @arg @ref LL_RCC_PLLM_DIV_60
1561 * @arg @ref LL_RCC_PLLM_DIV_61
1562 * @arg @ref LL_RCC_PLLM_DIV_62
1563 * @arg @ref LL_RCC_PLLM_DIV_63
1564 * @param __PLLN__ Between 50/192(*) and 432
1565 *
1566 * (*) value not defined in all devices.
1567 * @param __PLLP__ This parameter can be one of the following values:
1568 * @arg @ref LL_RCC_PLLP_DIV_2
1569 * @arg @ref LL_RCC_PLLP_DIV_4
1570 * @arg @ref LL_RCC_PLLP_DIV_6
1571 * @arg @ref LL_RCC_PLLP_DIV_8
1572 * @retval PLL clock frequency (in Hz)
1573 */
1574 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1575 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
1576
1577 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1578 /**
1579 * @brief Helper macro to calculate the PLLRCLK frequency on system domain
1580 * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1581 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1582 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1583 * @param __PLLM__ This parameter can be one of the following values:
1584 * @arg @ref LL_RCC_PLLM_DIV_2
1585 * @arg @ref LL_RCC_PLLM_DIV_3
1586 * @arg @ref LL_RCC_PLLM_DIV_4
1587 * @arg @ref LL_RCC_PLLM_DIV_5
1588 * @arg @ref LL_RCC_PLLM_DIV_6
1589 * @arg @ref LL_RCC_PLLM_DIV_7
1590 * @arg @ref LL_RCC_PLLM_DIV_8
1591 * @arg @ref LL_RCC_PLLM_DIV_9
1592 * @arg @ref LL_RCC_PLLM_DIV_10
1593 * @arg @ref LL_RCC_PLLM_DIV_11
1594 * @arg @ref LL_RCC_PLLM_DIV_12
1595 * @arg @ref LL_RCC_PLLM_DIV_13
1596 * @arg @ref LL_RCC_PLLM_DIV_14
1597 * @arg @ref LL_RCC_PLLM_DIV_15
1598 * @arg @ref LL_RCC_PLLM_DIV_16
1599 * @arg @ref LL_RCC_PLLM_DIV_17
1600 * @arg @ref LL_RCC_PLLM_DIV_18
1601 * @arg @ref LL_RCC_PLLM_DIV_19
1602 * @arg @ref LL_RCC_PLLM_DIV_20
1603 * @arg @ref LL_RCC_PLLM_DIV_21
1604 * @arg @ref LL_RCC_PLLM_DIV_22
1605 * @arg @ref LL_RCC_PLLM_DIV_23
1606 * @arg @ref LL_RCC_PLLM_DIV_24
1607 * @arg @ref LL_RCC_PLLM_DIV_25
1608 * @arg @ref LL_RCC_PLLM_DIV_26
1609 * @arg @ref LL_RCC_PLLM_DIV_27
1610 * @arg @ref LL_RCC_PLLM_DIV_28
1611 * @arg @ref LL_RCC_PLLM_DIV_29
1612 * @arg @ref LL_RCC_PLLM_DIV_30
1613 * @arg @ref LL_RCC_PLLM_DIV_31
1614 * @arg @ref LL_RCC_PLLM_DIV_32
1615 * @arg @ref LL_RCC_PLLM_DIV_33
1616 * @arg @ref LL_RCC_PLLM_DIV_34
1617 * @arg @ref LL_RCC_PLLM_DIV_35
1618 * @arg @ref LL_RCC_PLLM_DIV_36
1619 * @arg @ref LL_RCC_PLLM_DIV_37
1620 * @arg @ref LL_RCC_PLLM_DIV_38
1621 * @arg @ref LL_RCC_PLLM_DIV_39
1622 * @arg @ref LL_RCC_PLLM_DIV_40
1623 * @arg @ref LL_RCC_PLLM_DIV_41
1624 * @arg @ref LL_RCC_PLLM_DIV_42
1625 * @arg @ref LL_RCC_PLLM_DIV_43
1626 * @arg @ref LL_RCC_PLLM_DIV_44
1627 * @arg @ref LL_RCC_PLLM_DIV_45
1628 * @arg @ref LL_RCC_PLLM_DIV_46
1629 * @arg @ref LL_RCC_PLLM_DIV_47
1630 * @arg @ref LL_RCC_PLLM_DIV_48
1631 * @arg @ref LL_RCC_PLLM_DIV_49
1632 * @arg @ref LL_RCC_PLLM_DIV_50
1633 * @arg @ref LL_RCC_PLLM_DIV_51
1634 * @arg @ref LL_RCC_PLLM_DIV_52
1635 * @arg @ref LL_RCC_PLLM_DIV_53
1636 * @arg @ref LL_RCC_PLLM_DIV_54
1637 * @arg @ref LL_RCC_PLLM_DIV_55
1638 * @arg @ref LL_RCC_PLLM_DIV_56
1639 * @arg @ref LL_RCC_PLLM_DIV_57
1640 * @arg @ref LL_RCC_PLLM_DIV_58
1641 * @arg @ref LL_RCC_PLLM_DIV_59
1642 * @arg @ref LL_RCC_PLLM_DIV_60
1643 * @arg @ref LL_RCC_PLLM_DIV_61
1644 * @arg @ref LL_RCC_PLLM_DIV_62
1645 * @arg @ref LL_RCC_PLLM_DIV_63
1646 * @param __PLLN__ Between 50 and 432
1647 * @param __PLLR__ This parameter can be one of the following values:
1648 * @arg @ref LL_RCC_PLLR_DIV_2
1649 * @arg @ref LL_RCC_PLLR_DIV_3
1650 * @arg @ref LL_RCC_PLLR_DIV_4
1651 * @arg @ref LL_RCC_PLLR_DIV_5
1652 * @arg @ref LL_RCC_PLLR_DIV_6
1653 * @arg @ref LL_RCC_PLLR_DIV_7
1654 * @retval PLL clock frequency (in Hz)
1655 */
1656 #define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1657 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1658
1659 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1660
1661 /**
1662 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
1663 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1664 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1665 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1666 * @param __PLLM__ This parameter can be one of the following values:
1667 * @arg @ref LL_RCC_PLLM_DIV_2
1668 * @arg @ref LL_RCC_PLLM_DIV_3
1669 * @arg @ref LL_RCC_PLLM_DIV_4
1670 * @arg @ref LL_RCC_PLLM_DIV_5
1671 * @arg @ref LL_RCC_PLLM_DIV_6
1672 * @arg @ref LL_RCC_PLLM_DIV_7
1673 * @arg @ref LL_RCC_PLLM_DIV_8
1674 * @arg @ref LL_RCC_PLLM_DIV_9
1675 * @arg @ref LL_RCC_PLLM_DIV_10
1676 * @arg @ref LL_RCC_PLLM_DIV_11
1677 * @arg @ref LL_RCC_PLLM_DIV_12
1678 * @arg @ref LL_RCC_PLLM_DIV_13
1679 * @arg @ref LL_RCC_PLLM_DIV_14
1680 * @arg @ref LL_RCC_PLLM_DIV_15
1681 * @arg @ref LL_RCC_PLLM_DIV_16
1682 * @arg @ref LL_RCC_PLLM_DIV_17
1683 * @arg @ref LL_RCC_PLLM_DIV_18
1684 * @arg @ref LL_RCC_PLLM_DIV_19
1685 * @arg @ref LL_RCC_PLLM_DIV_20
1686 * @arg @ref LL_RCC_PLLM_DIV_21
1687 * @arg @ref LL_RCC_PLLM_DIV_22
1688 * @arg @ref LL_RCC_PLLM_DIV_23
1689 * @arg @ref LL_RCC_PLLM_DIV_24
1690 * @arg @ref LL_RCC_PLLM_DIV_25
1691 * @arg @ref LL_RCC_PLLM_DIV_26
1692 * @arg @ref LL_RCC_PLLM_DIV_27
1693 * @arg @ref LL_RCC_PLLM_DIV_28
1694 * @arg @ref LL_RCC_PLLM_DIV_29
1695 * @arg @ref LL_RCC_PLLM_DIV_30
1696 * @arg @ref LL_RCC_PLLM_DIV_31
1697 * @arg @ref LL_RCC_PLLM_DIV_32
1698 * @arg @ref LL_RCC_PLLM_DIV_33
1699 * @arg @ref LL_RCC_PLLM_DIV_34
1700 * @arg @ref LL_RCC_PLLM_DIV_35
1701 * @arg @ref LL_RCC_PLLM_DIV_36
1702 * @arg @ref LL_RCC_PLLM_DIV_37
1703 * @arg @ref LL_RCC_PLLM_DIV_38
1704 * @arg @ref LL_RCC_PLLM_DIV_39
1705 * @arg @ref LL_RCC_PLLM_DIV_40
1706 * @arg @ref LL_RCC_PLLM_DIV_41
1707 * @arg @ref LL_RCC_PLLM_DIV_42
1708 * @arg @ref LL_RCC_PLLM_DIV_43
1709 * @arg @ref LL_RCC_PLLM_DIV_44
1710 * @arg @ref LL_RCC_PLLM_DIV_45
1711 * @arg @ref LL_RCC_PLLM_DIV_46
1712 * @arg @ref LL_RCC_PLLM_DIV_47
1713 * @arg @ref LL_RCC_PLLM_DIV_48
1714 * @arg @ref LL_RCC_PLLM_DIV_49
1715 * @arg @ref LL_RCC_PLLM_DIV_50
1716 * @arg @ref LL_RCC_PLLM_DIV_51
1717 * @arg @ref LL_RCC_PLLM_DIV_52
1718 * @arg @ref LL_RCC_PLLM_DIV_53
1719 * @arg @ref LL_RCC_PLLM_DIV_54
1720 * @arg @ref LL_RCC_PLLM_DIV_55
1721 * @arg @ref LL_RCC_PLLM_DIV_56
1722 * @arg @ref LL_RCC_PLLM_DIV_57
1723 * @arg @ref LL_RCC_PLLM_DIV_58
1724 * @arg @ref LL_RCC_PLLM_DIV_59
1725 * @arg @ref LL_RCC_PLLM_DIV_60
1726 * @arg @ref LL_RCC_PLLM_DIV_61
1727 * @arg @ref LL_RCC_PLLM_DIV_62
1728 * @arg @ref LL_RCC_PLLM_DIV_63
1729 * @param __PLLN__ Between 50/192(*) and 432
1730 *
1731 * (*) value not defined in all devices.
1732 * @param __PLLQ__ This parameter can be one of the following values:
1733 * @arg @ref LL_RCC_PLLQ_DIV_2
1734 * @arg @ref LL_RCC_PLLQ_DIV_3
1735 * @arg @ref LL_RCC_PLLQ_DIV_4
1736 * @arg @ref LL_RCC_PLLQ_DIV_5
1737 * @arg @ref LL_RCC_PLLQ_DIV_6
1738 * @arg @ref LL_RCC_PLLQ_DIV_7
1739 * @arg @ref LL_RCC_PLLQ_DIV_8
1740 * @arg @ref LL_RCC_PLLQ_DIV_9
1741 * @arg @ref LL_RCC_PLLQ_DIV_10
1742 * @arg @ref LL_RCC_PLLQ_DIV_11
1743 * @arg @ref LL_RCC_PLLQ_DIV_12
1744 * @arg @ref LL_RCC_PLLQ_DIV_13
1745 * @arg @ref LL_RCC_PLLQ_DIV_14
1746 * @arg @ref LL_RCC_PLLQ_DIV_15
1747 * @retval PLL clock frequency (in Hz)
1748 */
1749 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1750 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
1751
1752 #if defined(DSI)
1753 /**
1754 * @brief Helper macro to calculate the PLLCLK frequency used on DSI
1755 * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1756 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1757 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1758 * @param __PLLM__ This parameter can be one of the following values:
1759 * @arg @ref LL_RCC_PLLM_DIV_2
1760 * @arg @ref LL_RCC_PLLM_DIV_3
1761 * @arg @ref LL_RCC_PLLM_DIV_4
1762 * @arg @ref LL_RCC_PLLM_DIV_5
1763 * @arg @ref LL_RCC_PLLM_DIV_6
1764 * @arg @ref LL_RCC_PLLM_DIV_7
1765 * @arg @ref LL_RCC_PLLM_DIV_8
1766 * @arg @ref LL_RCC_PLLM_DIV_9
1767 * @arg @ref LL_RCC_PLLM_DIV_10
1768 * @arg @ref LL_RCC_PLLM_DIV_11
1769 * @arg @ref LL_RCC_PLLM_DIV_12
1770 * @arg @ref LL_RCC_PLLM_DIV_13
1771 * @arg @ref LL_RCC_PLLM_DIV_14
1772 * @arg @ref LL_RCC_PLLM_DIV_15
1773 * @arg @ref LL_RCC_PLLM_DIV_16
1774 * @arg @ref LL_RCC_PLLM_DIV_17
1775 * @arg @ref LL_RCC_PLLM_DIV_18
1776 * @arg @ref LL_RCC_PLLM_DIV_19
1777 * @arg @ref LL_RCC_PLLM_DIV_20
1778 * @arg @ref LL_RCC_PLLM_DIV_21
1779 * @arg @ref LL_RCC_PLLM_DIV_22
1780 * @arg @ref LL_RCC_PLLM_DIV_23
1781 * @arg @ref LL_RCC_PLLM_DIV_24
1782 * @arg @ref LL_RCC_PLLM_DIV_25
1783 * @arg @ref LL_RCC_PLLM_DIV_26
1784 * @arg @ref LL_RCC_PLLM_DIV_27
1785 * @arg @ref LL_RCC_PLLM_DIV_28
1786 * @arg @ref LL_RCC_PLLM_DIV_29
1787 * @arg @ref LL_RCC_PLLM_DIV_30
1788 * @arg @ref LL_RCC_PLLM_DIV_31
1789 * @arg @ref LL_RCC_PLLM_DIV_32
1790 * @arg @ref LL_RCC_PLLM_DIV_33
1791 * @arg @ref LL_RCC_PLLM_DIV_34
1792 * @arg @ref LL_RCC_PLLM_DIV_35
1793 * @arg @ref LL_RCC_PLLM_DIV_36
1794 * @arg @ref LL_RCC_PLLM_DIV_37
1795 * @arg @ref LL_RCC_PLLM_DIV_38
1796 * @arg @ref LL_RCC_PLLM_DIV_39
1797 * @arg @ref LL_RCC_PLLM_DIV_40
1798 * @arg @ref LL_RCC_PLLM_DIV_41
1799 * @arg @ref LL_RCC_PLLM_DIV_42
1800 * @arg @ref LL_RCC_PLLM_DIV_43
1801 * @arg @ref LL_RCC_PLLM_DIV_44
1802 * @arg @ref LL_RCC_PLLM_DIV_45
1803 * @arg @ref LL_RCC_PLLM_DIV_46
1804 * @arg @ref LL_RCC_PLLM_DIV_47
1805 * @arg @ref LL_RCC_PLLM_DIV_48
1806 * @arg @ref LL_RCC_PLLM_DIV_49
1807 * @arg @ref LL_RCC_PLLM_DIV_50
1808 * @arg @ref LL_RCC_PLLM_DIV_51
1809 * @arg @ref LL_RCC_PLLM_DIV_52
1810 * @arg @ref LL_RCC_PLLM_DIV_53
1811 * @arg @ref LL_RCC_PLLM_DIV_54
1812 * @arg @ref LL_RCC_PLLM_DIV_55
1813 * @arg @ref LL_RCC_PLLM_DIV_56
1814 * @arg @ref LL_RCC_PLLM_DIV_57
1815 * @arg @ref LL_RCC_PLLM_DIV_58
1816 * @arg @ref LL_RCC_PLLM_DIV_59
1817 * @arg @ref LL_RCC_PLLM_DIV_60
1818 * @arg @ref LL_RCC_PLLM_DIV_61
1819 * @arg @ref LL_RCC_PLLM_DIV_62
1820 * @arg @ref LL_RCC_PLLM_DIV_63
1821 * @param __PLLN__ Between 50 and 432
1822 * @param __PLLR__ This parameter can be one of the following values:
1823 * @arg @ref LL_RCC_PLLR_DIV_2
1824 * @arg @ref LL_RCC_PLLR_DIV_3
1825 * @arg @ref LL_RCC_PLLR_DIV_4
1826 * @arg @ref LL_RCC_PLLR_DIV_5
1827 * @arg @ref LL_RCC_PLLR_DIV_6
1828 * @arg @ref LL_RCC_PLLR_DIV_7
1829 * @retval PLL clock frequency (in Hz)
1830 */
1831 #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1832 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1833 #endif /* DSI */
1834
1835 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
1836 /**
1837 * @brief Helper macro to calculate the PLLCLK frequency used on I2S
1838 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1839 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1840 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1841 * @param __PLLM__ This parameter can be one of the following values:
1842 * @arg @ref LL_RCC_PLLM_DIV_2
1843 * @arg @ref LL_RCC_PLLM_DIV_3
1844 * @arg @ref LL_RCC_PLLM_DIV_4
1845 * @arg @ref LL_RCC_PLLM_DIV_5
1846 * @arg @ref LL_RCC_PLLM_DIV_6
1847 * @arg @ref LL_RCC_PLLM_DIV_7
1848 * @arg @ref LL_RCC_PLLM_DIV_8
1849 * @arg @ref LL_RCC_PLLM_DIV_9
1850 * @arg @ref LL_RCC_PLLM_DIV_10
1851 * @arg @ref LL_RCC_PLLM_DIV_11
1852 * @arg @ref LL_RCC_PLLM_DIV_12
1853 * @arg @ref LL_RCC_PLLM_DIV_13
1854 * @arg @ref LL_RCC_PLLM_DIV_14
1855 * @arg @ref LL_RCC_PLLM_DIV_15
1856 * @arg @ref LL_RCC_PLLM_DIV_16
1857 * @arg @ref LL_RCC_PLLM_DIV_17
1858 * @arg @ref LL_RCC_PLLM_DIV_18
1859 * @arg @ref LL_RCC_PLLM_DIV_19
1860 * @arg @ref LL_RCC_PLLM_DIV_20
1861 * @arg @ref LL_RCC_PLLM_DIV_21
1862 * @arg @ref LL_RCC_PLLM_DIV_22
1863 * @arg @ref LL_RCC_PLLM_DIV_23
1864 * @arg @ref LL_RCC_PLLM_DIV_24
1865 * @arg @ref LL_RCC_PLLM_DIV_25
1866 * @arg @ref LL_RCC_PLLM_DIV_26
1867 * @arg @ref LL_RCC_PLLM_DIV_27
1868 * @arg @ref LL_RCC_PLLM_DIV_28
1869 * @arg @ref LL_RCC_PLLM_DIV_29
1870 * @arg @ref LL_RCC_PLLM_DIV_30
1871 * @arg @ref LL_RCC_PLLM_DIV_31
1872 * @arg @ref LL_RCC_PLLM_DIV_32
1873 * @arg @ref LL_RCC_PLLM_DIV_33
1874 * @arg @ref LL_RCC_PLLM_DIV_34
1875 * @arg @ref LL_RCC_PLLM_DIV_35
1876 * @arg @ref LL_RCC_PLLM_DIV_36
1877 * @arg @ref LL_RCC_PLLM_DIV_37
1878 * @arg @ref LL_RCC_PLLM_DIV_38
1879 * @arg @ref LL_RCC_PLLM_DIV_39
1880 * @arg @ref LL_RCC_PLLM_DIV_40
1881 * @arg @ref LL_RCC_PLLM_DIV_41
1882 * @arg @ref LL_RCC_PLLM_DIV_42
1883 * @arg @ref LL_RCC_PLLM_DIV_43
1884 * @arg @ref LL_RCC_PLLM_DIV_44
1885 * @arg @ref LL_RCC_PLLM_DIV_45
1886 * @arg @ref LL_RCC_PLLM_DIV_46
1887 * @arg @ref LL_RCC_PLLM_DIV_47
1888 * @arg @ref LL_RCC_PLLM_DIV_48
1889 * @arg @ref LL_RCC_PLLM_DIV_49
1890 * @arg @ref LL_RCC_PLLM_DIV_50
1891 * @arg @ref LL_RCC_PLLM_DIV_51
1892 * @arg @ref LL_RCC_PLLM_DIV_52
1893 * @arg @ref LL_RCC_PLLM_DIV_53
1894 * @arg @ref LL_RCC_PLLM_DIV_54
1895 * @arg @ref LL_RCC_PLLM_DIV_55
1896 * @arg @ref LL_RCC_PLLM_DIV_56
1897 * @arg @ref LL_RCC_PLLM_DIV_57
1898 * @arg @ref LL_RCC_PLLM_DIV_58
1899 * @arg @ref LL_RCC_PLLM_DIV_59
1900 * @arg @ref LL_RCC_PLLM_DIV_60
1901 * @arg @ref LL_RCC_PLLM_DIV_61
1902 * @arg @ref LL_RCC_PLLM_DIV_62
1903 * @arg @ref LL_RCC_PLLM_DIV_63
1904 * @param __PLLN__ Between 50 and 432
1905 * @param __PLLR__ This parameter can be one of the following values:
1906 * @arg @ref LL_RCC_PLLR_DIV_2
1907 * @arg @ref LL_RCC_PLLR_DIV_3
1908 * @arg @ref LL_RCC_PLLR_DIV_4
1909 * @arg @ref LL_RCC_PLLR_DIV_5
1910 * @arg @ref LL_RCC_PLLR_DIV_6
1911 * @arg @ref LL_RCC_PLLR_DIV_7
1912 * @retval PLL clock frequency (in Hz)
1913 */
1914 #define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1915 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1916 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
1917
1918 #if defined(SPDIFRX)
1919 /**
1920 * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX
1921 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1922 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1923 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1924 * @param __PLLM__ This parameter can be one of the following values:
1925 * @arg @ref LL_RCC_PLLM_DIV_2
1926 * @arg @ref LL_RCC_PLLM_DIV_3
1927 * @arg @ref LL_RCC_PLLM_DIV_4
1928 * @arg @ref LL_RCC_PLLM_DIV_5
1929 * @arg @ref LL_RCC_PLLM_DIV_6
1930 * @arg @ref LL_RCC_PLLM_DIV_7
1931 * @arg @ref LL_RCC_PLLM_DIV_8
1932 * @arg @ref LL_RCC_PLLM_DIV_9
1933 * @arg @ref LL_RCC_PLLM_DIV_10
1934 * @arg @ref LL_RCC_PLLM_DIV_11
1935 * @arg @ref LL_RCC_PLLM_DIV_12
1936 * @arg @ref LL_RCC_PLLM_DIV_13
1937 * @arg @ref LL_RCC_PLLM_DIV_14
1938 * @arg @ref LL_RCC_PLLM_DIV_15
1939 * @arg @ref LL_RCC_PLLM_DIV_16
1940 * @arg @ref LL_RCC_PLLM_DIV_17
1941 * @arg @ref LL_RCC_PLLM_DIV_18
1942 * @arg @ref LL_RCC_PLLM_DIV_19
1943 * @arg @ref LL_RCC_PLLM_DIV_20
1944 * @arg @ref LL_RCC_PLLM_DIV_21
1945 * @arg @ref LL_RCC_PLLM_DIV_22
1946 * @arg @ref LL_RCC_PLLM_DIV_23
1947 * @arg @ref LL_RCC_PLLM_DIV_24
1948 * @arg @ref LL_RCC_PLLM_DIV_25
1949 * @arg @ref LL_RCC_PLLM_DIV_26
1950 * @arg @ref LL_RCC_PLLM_DIV_27
1951 * @arg @ref LL_RCC_PLLM_DIV_28
1952 * @arg @ref LL_RCC_PLLM_DIV_29
1953 * @arg @ref LL_RCC_PLLM_DIV_30
1954 * @arg @ref LL_RCC_PLLM_DIV_31
1955 * @arg @ref LL_RCC_PLLM_DIV_32
1956 * @arg @ref LL_RCC_PLLM_DIV_33
1957 * @arg @ref LL_RCC_PLLM_DIV_34
1958 * @arg @ref LL_RCC_PLLM_DIV_35
1959 * @arg @ref LL_RCC_PLLM_DIV_36
1960 * @arg @ref LL_RCC_PLLM_DIV_37
1961 * @arg @ref LL_RCC_PLLM_DIV_38
1962 * @arg @ref LL_RCC_PLLM_DIV_39
1963 * @arg @ref LL_RCC_PLLM_DIV_40
1964 * @arg @ref LL_RCC_PLLM_DIV_41
1965 * @arg @ref LL_RCC_PLLM_DIV_42
1966 * @arg @ref LL_RCC_PLLM_DIV_43
1967 * @arg @ref LL_RCC_PLLM_DIV_44
1968 * @arg @ref LL_RCC_PLLM_DIV_45
1969 * @arg @ref LL_RCC_PLLM_DIV_46
1970 * @arg @ref LL_RCC_PLLM_DIV_47
1971 * @arg @ref LL_RCC_PLLM_DIV_48
1972 * @arg @ref LL_RCC_PLLM_DIV_49
1973 * @arg @ref LL_RCC_PLLM_DIV_50
1974 * @arg @ref LL_RCC_PLLM_DIV_51
1975 * @arg @ref LL_RCC_PLLM_DIV_52
1976 * @arg @ref LL_RCC_PLLM_DIV_53
1977 * @arg @ref LL_RCC_PLLM_DIV_54
1978 * @arg @ref LL_RCC_PLLM_DIV_55
1979 * @arg @ref LL_RCC_PLLM_DIV_56
1980 * @arg @ref LL_RCC_PLLM_DIV_57
1981 * @arg @ref LL_RCC_PLLM_DIV_58
1982 * @arg @ref LL_RCC_PLLM_DIV_59
1983 * @arg @ref LL_RCC_PLLM_DIV_60
1984 * @arg @ref LL_RCC_PLLM_DIV_61
1985 * @arg @ref LL_RCC_PLLM_DIV_62
1986 * @arg @ref LL_RCC_PLLM_DIV_63
1987 * @param __PLLN__ Between 50 and 432
1988 * @param __PLLR__ This parameter can be one of the following values:
1989 * @arg @ref LL_RCC_PLLR_DIV_2
1990 * @arg @ref LL_RCC_PLLR_DIV_3
1991 * @arg @ref LL_RCC_PLLR_DIV_4
1992 * @arg @ref LL_RCC_PLLR_DIV_5
1993 * @arg @ref LL_RCC_PLLR_DIV_6
1994 * @arg @ref LL_RCC_PLLR_DIV_7
1995 * @retval PLL clock frequency (in Hz)
1996 */
1997 #define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1998 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1999 #endif /* SPDIFRX */
2000
2001 #if defined(RCC_PLLCFGR_PLLR)
2002 #if defined(SAI1)
2003 /**
2004 * @brief Helper macro to calculate the PLLCLK frequency used on SAI
2005 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
2006 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
2007 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2008 * @param __PLLM__ This parameter can be one of the following values:
2009 * @arg @ref LL_RCC_PLLM_DIV_2
2010 * @arg @ref LL_RCC_PLLM_DIV_3
2011 * @arg @ref LL_RCC_PLLM_DIV_4
2012 * @arg @ref LL_RCC_PLLM_DIV_5
2013 * @arg @ref LL_RCC_PLLM_DIV_6
2014 * @arg @ref LL_RCC_PLLM_DIV_7
2015 * @arg @ref LL_RCC_PLLM_DIV_8
2016 * @arg @ref LL_RCC_PLLM_DIV_9
2017 * @arg @ref LL_RCC_PLLM_DIV_10
2018 * @arg @ref LL_RCC_PLLM_DIV_11
2019 * @arg @ref LL_RCC_PLLM_DIV_12
2020 * @arg @ref LL_RCC_PLLM_DIV_13
2021 * @arg @ref LL_RCC_PLLM_DIV_14
2022 * @arg @ref LL_RCC_PLLM_DIV_15
2023 * @arg @ref LL_RCC_PLLM_DIV_16
2024 * @arg @ref LL_RCC_PLLM_DIV_17
2025 * @arg @ref LL_RCC_PLLM_DIV_18
2026 * @arg @ref LL_RCC_PLLM_DIV_19
2027 * @arg @ref LL_RCC_PLLM_DIV_20
2028 * @arg @ref LL_RCC_PLLM_DIV_21
2029 * @arg @ref LL_RCC_PLLM_DIV_22
2030 * @arg @ref LL_RCC_PLLM_DIV_23
2031 * @arg @ref LL_RCC_PLLM_DIV_24
2032 * @arg @ref LL_RCC_PLLM_DIV_25
2033 * @arg @ref LL_RCC_PLLM_DIV_26
2034 * @arg @ref LL_RCC_PLLM_DIV_27
2035 * @arg @ref LL_RCC_PLLM_DIV_28
2036 * @arg @ref LL_RCC_PLLM_DIV_29
2037 * @arg @ref LL_RCC_PLLM_DIV_30
2038 * @arg @ref LL_RCC_PLLM_DIV_31
2039 * @arg @ref LL_RCC_PLLM_DIV_32
2040 * @arg @ref LL_RCC_PLLM_DIV_33
2041 * @arg @ref LL_RCC_PLLM_DIV_34
2042 * @arg @ref LL_RCC_PLLM_DIV_35
2043 * @arg @ref LL_RCC_PLLM_DIV_36
2044 * @arg @ref LL_RCC_PLLM_DIV_37
2045 * @arg @ref LL_RCC_PLLM_DIV_38
2046 * @arg @ref LL_RCC_PLLM_DIV_39
2047 * @arg @ref LL_RCC_PLLM_DIV_40
2048 * @arg @ref LL_RCC_PLLM_DIV_41
2049 * @arg @ref LL_RCC_PLLM_DIV_42
2050 * @arg @ref LL_RCC_PLLM_DIV_43
2051 * @arg @ref LL_RCC_PLLM_DIV_44
2052 * @arg @ref LL_RCC_PLLM_DIV_45
2053 * @arg @ref LL_RCC_PLLM_DIV_46
2054 * @arg @ref LL_RCC_PLLM_DIV_47
2055 * @arg @ref LL_RCC_PLLM_DIV_48
2056 * @arg @ref LL_RCC_PLLM_DIV_49
2057 * @arg @ref LL_RCC_PLLM_DIV_50
2058 * @arg @ref LL_RCC_PLLM_DIV_51
2059 * @arg @ref LL_RCC_PLLM_DIV_52
2060 * @arg @ref LL_RCC_PLLM_DIV_53
2061 * @arg @ref LL_RCC_PLLM_DIV_54
2062 * @arg @ref LL_RCC_PLLM_DIV_55
2063 * @arg @ref LL_RCC_PLLM_DIV_56
2064 * @arg @ref LL_RCC_PLLM_DIV_57
2065 * @arg @ref LL_RCC_PLLM_DIV_58
2066 * @arg @ref LL_RCC_PLLM_DIV_59
2067 * @arg @ref LL_RCC_PLLM_DIV_60
2068 * @arg @ref LL_RCC_PLLM_DIV_61
2069 * @arg @ref LL_RCC_PLLM_DIV_62
2070 * @arg @ref LL_RCC_PLLM_DIV_63
2071 * @param __PLLN__ Between 50 and 432
2072 * @param __PLLR__ This parameter can be one of the following values:
2073 * @arg @ref LL_RCC_PLLR_DIV_2
2074 * @arg @ref LL_RCC_PLLR_DIV_3
2075 * @arg @ref LL_RCC_PLLR_DIV_4
2076 * @arg @ref LL_RCC_PLLR_DIV_5
2077 * @arg @ref LL_RCC_PLLR_DIV_6
2078 * @arg @ref LL_RCC_PLLR_DIV_7
2079 * @param __PLLDIVR__ This parameter can be one of the following values:
2080 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
2081 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
2082 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
2083 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
2084 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
2085 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
2086 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
2087 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
2088 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
2089 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
2090 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
2091 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
2092 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
2093 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
2094 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
2095 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
2096 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
2097 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
2098 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
2099 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
2100 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
2101 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
2102 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
2103 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
2104 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
2105 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
2106 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
2107 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
2108 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
2109 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
2110 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
2111 *
2112 * (*) value not defined in all devices.
2113 * @retval PLL clock frequency (in Hz)
2114 */
2115 #if defined(RCC_DCKCFGR_PLLDIVR)
2116 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2117 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
2118 #else
2119 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2120 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
2121 #endif /* RCC_DCKCFGR_PLLDIVR */
2122 #endif /* SAI1 */
2123 #endif /* RCC_PLLCFGR_PLLR */
2124
2125 #if defined(RCC_PLLSAI_SUPPORT)
2126 /**
2127 * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain
2128 * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2129 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
2130 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2131 * @param __PLLM__ This parameter can be one of the following values:
2132 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2133 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2134 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2135 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2136 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2137 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2138 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2139 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2140 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2141 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2142 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2143 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2144 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2145 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2146 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2147 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2148 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2149 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2150 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2151 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2152 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2153 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2154 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2155 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2156 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2157 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2158 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2159 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2160 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2161 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2162 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2163 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2164 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2165 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2166 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2167 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2168 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2169 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2170 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2171 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2172 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2173 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2174 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2175 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2176 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2177 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2178 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2179 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2180 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2181 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2182 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2183 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2184 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2185 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2186 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2187 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2188 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2189 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2190 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2191 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2192 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2193 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2194 * @param __PLLSAIN__ Between 49/50(*) and 432
2195 *
2196 * (*) value not defined in all devices.
2197 * @param __PLLSAIQ__ This parameter can be one of the following values:
2198 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
2199 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
2200 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
2201 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
2202 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
2203 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
2204 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
2205 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
2206 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
2207 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
2208 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
2209 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
2210 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
2211 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
2212 * @param __PLLSAIDIVQ__ This parameter can be one of the following values:
2213 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
2214 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
2215 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
2216 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
2217 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
2218 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
2219 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
2220 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
2221 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
2222 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
2223 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
2224 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
2225 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
2226 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
2227 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
2228 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
2229 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
2230 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
2231 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
2232 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
2233 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
2234 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
2235 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
2236 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
2237 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
2238 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
2239 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
2240 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
2241 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
2242 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
2243 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
2244 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
2245 * @retval PLLSAI clock frequency (in Hz)
2246 */
2247 #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2248 (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
2249
2250 #if defined(RCC_PLLSAICFGR_PLLSAIP)
2251 /**
2252 * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
2253 * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2254 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
2255 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2256 * @param __PLLM__ This parameter can be one of the following values:
2257 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2258 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2259 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2260 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2261 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2262 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2263 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2264 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2265 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2266 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2267 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2268 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2269 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2270 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2271 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2272 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2273 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2274 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2275 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2276 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2277 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2278 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2279 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2280 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2281 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2282 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2283 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2284 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2285 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2286 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2287 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2288 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2289 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2290 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2291 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2292 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2293 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2294 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2295 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2296 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2297 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2298 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2299 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2300 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2301 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2302 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2303 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2304 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2305 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2306 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2307 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2308 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2309 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2310 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2311 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2312 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2313 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2314 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2315 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2316 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2317 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2318 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2319 * @param __PLLSAIN__ Between 50 and 432
2320 * @param __PLLSAIP__ This parameter can be one of the following values:
2321 * @arg @ref LL_RCC_PLLSAIP_DIV_2
2322 * @arg @ref LL_RCC_PLLSAIP_DIV_4
2323 * @arg @ref LL_RCC_PLLSAIP_DIV_6
2324 * @arg @ref LL_RCC_PLLSAIP_DIV_8
2325 * @retval PLLSAI clock frequency (in Hz)
2326 */
2327 #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2328 ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
2329 #endif /* RCC_PLLSAICFGR_PLLSAIP */
2330
2331 #if defined(LTDC)
2332 /**
2333 * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
2334 * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2335 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
2336 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2337 * @param __PLLM__ This parameter can be one of the following values:
2338 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2339 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2340 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2341 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2342 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2343 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2344 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2345 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2346 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2347 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2348 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2349 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2350 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2351 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2352 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2353 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2354 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2355 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2356 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2357 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2358 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2359 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2360 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2361 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2362 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2363 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2364 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2365 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2366 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2367 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2368 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2369 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2370 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2371 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2372 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2373 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2374 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2375 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2376 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2377 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2378 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2379 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2380 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2381 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2382 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2383 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2384 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2385 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2386 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2387 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2388 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2389 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2390 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2391 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2392 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2393 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2394 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2395 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2396 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2397 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2398 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2399 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2400 * @param __PLLSAIN__ Between 49/50(*) and 432
2401 *
2402 * (*) value not defined in all devices.
2403 * @param __PLLSAIR__ This parameter can be one of the following values:
2404 * @arg @ref LL_RCC_PLLSAIR_DIV_2
2405 * @arg @ref LL_RCC_PLLSAIR_DIV_3
2406 * @arg @ref LL_RCC_PLLSAIR_DIV_4
2407 * @arg @ref LL_RCC_PLLSAIR_DIV_5
2408 * @arg @ref LL_RCC_PLLSAIR_DIV_6
2409 * @arg @ref LL_RCC_PLLSAIR_DIV_7
2410 * @param __PLLSAIDIVR__ This parameter can be one of the following values:
2411 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
2412 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
2413 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
2414 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
2415 * @retval PLLSAI clock frequency (in Hz)
2416 */
2417 #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2418 (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
2419 #endif /* LTDC */
2420 #endif /* RCC_PLLSAI_SUPPORT */
2421
2422 #if defined(RCC_PLLI2S_SUPPORT)
2423 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)
2424 /**
2425 * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain
2426 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2427 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
2428 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2429 * @param __PLLM__ This parameter can be one of the following values:
2430 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2431 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2432 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2433 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2434 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2435 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2436 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2437 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2438 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2439 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2440 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2441 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2442 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2443 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2444 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2445 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2446 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2447 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2448 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2449 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2450 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2451 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2452 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2453 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2454 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2455 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2456 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2457 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2458 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2459 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2460 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2461 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2462 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2463 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2464 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2465 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2466 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2467 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2468 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2469 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2470 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2471 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2472 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2473 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2474 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2475 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2476 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2477 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2478 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2479 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2480 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2481 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2482 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2483 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2484 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2485 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2486 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2487 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2488 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2489 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2490 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2491 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2492 * @param __PLLI2SN__ Between 50/192(*) and 432
2493 *
2494 * (*) value not defined in all devices.
2495 * @param __PLLI2SQ_R__ This parameter can be one of the following values:
2496 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
2497 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
2498 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
2499 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
2500 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
2501 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
2502 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
2503 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
2504 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
2505 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
2506 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
2507 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
2508 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
2509 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
2510 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
2511 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
2512 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
2513 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
2514 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
2515 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
2516 *
2517 * (*) value not defined in all devices.
2518 * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values:
2519 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
2520 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
2521 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
2522 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
2523 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
2524 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
2525 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
2526 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
2527 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
2528 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
2529 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
2530 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
2531 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
2532 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
2533 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
2534 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
2535 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
2536 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
2537 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
2538 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
2539 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
2540 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
2541 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
2542 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
2543 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
2544 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
2545 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
2546 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
2547 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
2548 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
2549 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
2550 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
2551 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
2552 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
2553 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
2554 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
2555 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
2556 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
2557 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
2558 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
2559 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
2560 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
2561 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
2562 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
2563 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
2564 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
2565 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
2566 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
2567 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
2568 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
2569 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
2570 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
2571 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
2572 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
2573 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
2574 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
2575 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
2576 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
2577 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
2578 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
2579 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
2580 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
2581 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
2582 *
2583 * (*) value not defined in all devices.
2584 * @retval PLLI2S clock frequency (in Hz)
2585 */
2586 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
2587 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2588 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
2589 #else
2590 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2591 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
2592
2593 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
2594 #endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */
2595
2596 #if defined(SPDIFRX)
2597 /**
2598 * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
2599 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2600 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
2601 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2602 * @param __PLLM__ This parameter can be one of the following values:
2603 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2604 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2605 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2606 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2607 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2608 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2609 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2610 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2611 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2612 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2613 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2614 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2615 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2616 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2617 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2618 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2619 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2620 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2621 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2622 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2623 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2624 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2625 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2626 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2627 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2628 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2629 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2630 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2631 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2632 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2633 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2634 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2635 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2636 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2637 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2638 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2639 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2640 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2641 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2642 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2643 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2644 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2645 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2646 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2647 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2648 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2649 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2650 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2651 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2652 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2653 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2654 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2655 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2656 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2657 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2658 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2659 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2660 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2661 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2662 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2663 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2664 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2665 * @param __PLLI2SN__ Between 50 and 432
2666 * @param __PLLI2SP__ This parameter can be one of the following values:
2667 * @arg @ref LL_RCC_PLLI2SP_DIV_2
2668 * @arg @ref LL_RCC_PLLI2SP_DIV_4
2669 * @arg @ref LL_RCC_PLLI2SP_DIV_6
2670 * @arg @ref LL_RCC_PLLI2SP_DIV_8
2671 * @retval PLLI2S clock frequency (in Hz)
2672 */
2673 #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2674 ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
2675
2676 #endif /* SPDIFRX */
2677
2678 /**
2679 * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
2680 * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2681 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
2682 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2683 * @param __PLLM__ This parameter can be one of the following values:
2684 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2685 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2686 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2687 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2688 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2689 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2690 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2691 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2692 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2693 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2694 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2695 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2696 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2697 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2698 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2699 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2700 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2701 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2702 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2703 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2704 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2705 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2706 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2707 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2708 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2709 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2710 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2711 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2712 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2713 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2714 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2715 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2716 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2717 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2718 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2719 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2720 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2721 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2722 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2723 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2724 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2725 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2726 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2727 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2728 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2729 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2730 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2731 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2732 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2733 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2734 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2735 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2736 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2737 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2738 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2739 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2740 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2741 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2742 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2743 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2744 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2745 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2746 * @param __PLLI2SN__ Between 50/192(*) and 432
2747 *
2748 * (*) value not defined in all devices.
2749 * @param __PLLI2SR__ This parameter can be one of the following values:
2750 * @arg @ref LL_RCC_PLLI2SR_DIV_2
2751 * @arg @ref LL_RCC_PLLI2SR_DIV_3
2752 * @arg @ref LL_RCC_PLLI2SR_DIV_4
2753 * @arg @ref LL_RCC_PLLI2SR_DIV_5
2754 * @arg @ref LL_RCC_PLLI2SR_DIV_6
2755 * @arg @ref LL_RCC_PLLI2SR_DIV_7
2756 * @retval PLLI2S clock frequency (in Hz)
2757 */
2758 #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2759 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
2760
2761 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
2762 /**
2763 * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
2764 * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2765 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
2766 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2767 * @param __PLLM__ This parameter can be one of the following values:
2768 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2769 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2770 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2771 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2772 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2773 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2774 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2775 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2776 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2777 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2778 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2779 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2780 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2781 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2782 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2783 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2784 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2785 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2786 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2787 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2788 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2789 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2790 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2791 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2792 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2793 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2794 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2795 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2796 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2797 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2798 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2799 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2800 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2801 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2802 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2803 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2804 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2805 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2806 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2807 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2808 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2809 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2810 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2811 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2812 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2813 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2814 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2815 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2816 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2817 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2818 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2819 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2820 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2821 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2822 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2823 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2824 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2825 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2826 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2827 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2828 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2829 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2830 * @param __PLLI2SN__ Between 50 and 432
2831 * @param __PLLI2SQ__ This parameter can be one of the following values:
2832 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
2833 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
2834 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
2835 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
2836 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
2837 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
2838 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
2839 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
2840 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
2841 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
2842 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
2843 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
2844 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
2845 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
2846 * @retval PLLI2S clock frequency (in Hz)
2847 */
2848 #define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2849 ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
2850
2851 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
2852 #endif /* RCC_PLLI2S_SUPPORT */
2853
2854 /**
2855 * @brief Helper macro to calculate the HCLK frequency
2856 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
2857 * @param __AHBPRESCALER__ This parameter can be one of the following values:
2858 * @arg @ref LL_RCC_SYSCLK_DIV_1
2859 * @arg @ref LL_RCC_SYSCLK_DIV_2
2860 * @arg @ref LL_RCC_SYSCLK_DIV_4
2861 * @arg @ref LL_RCC_SYSCLK_DIV_8
2862 * @arg @ref LL_RCC_SYSCLK_DIV_16
2863 * @arg @ref LL_RCC_SYSCLK_DIV_64
2864 * @arg @ref LL_RCC_SYSCLK_DIV_128
2865 * @arg @ref LL_RCC_SYSCLK_DIV_256
2866 * @arg @ref LL_RCC_SYSCLK_DIV_512
2867 * @retval HCLK clock frequency (in Hz)
2868 */
2869 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) &\
2870 RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
2871
2872 /**
2873 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
2874 * @param __HCLKFREQ__ HCLK frequency
2875 * @param __APB1PRESCALER__ This parameter can be one of the following values:
2876 * @arg @ref LL_RCC_APB1_DIV_1
2877 * @arg @ref LL_RCC_APB1_DIV_2
2878 * @arg @ref LL_RCC_APB1_DIV_4
2879 * @arg @ref LL_RCC_APB1_DIV_8
2880 * @arg @ref LL_RCC_APB1_DIV_16
2881 * @retval PCLK1 clock frequency (in Hz)
2882 */
2883 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
2884
2885 /**
2886 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
2887 * @param __HCLKFREQ__ HCLK frequency
2888 * @param __APB2PRESCALER__ This parameter can be one of the following values:
2889 * @arg @ref LL_RCC_APB2_DIV_1
2890 * @arg @ref LL_RCC_APB2_DIV_2
2891 * @arg @ref LL_RCC_APB2_DIV_4
2892 * @arg @ref LL_RCC_APB2_DIV_8
2893 * @arg @ref LL_RCC_APB2_DIV_16
2894 * @retval PCLK2 clock frequency (in Hz)
2895 */
2896 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
2897
2898 /**
2899 * @}
2900 */
2901
2902 /**
2903 * @}
2904 */
2905
2906 /* Exported functions --------------------------------------------------------*/
2907 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
2908 * @{
2909 */
2910
2911 /** @defgroup RCC_LL_EF_HSE HSE
2912 * @{
2913 */
2914
2915 /**
2916 * @brief Enable the Clock Security System.
2917 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
2918 * @retval None
2919 */
LL_RCC_HSE_EnableCSS(void)2920 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
2921 {
2922 SET_BIT(RCC->CR, RCC_CR_CSSON);
2923 }
2924
2925 /**
2926 * @brief Enable HSE external oscillator (HSE Bypass)
2927 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
2928 * @retval None
2929 */
LL_RCC_HSE_EnableBypass(void)2930 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
2931 {
2932 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
2933 }
2934
2935 /**
2936 * @brief Disable HSE external oscillator (HSE Bypass)
2937 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
2938 * @retval None
2939 */
LL_RCC_HSE_DisableBypass(void)2940 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
2941 {
2942 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
2943 }
2944
2945 /**
2946 * @brief Enable HSE crystal oscillator (HSE ON)
2947 * @rmtoll CR HSEON LL_RCC_HSE_Enable
2948 * @retval None
2949 */
LL_RCC_HSE_Enable(void)2950 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
2951 {
2952 SET_BIT(RCC->CR, RCC_CR_HSEON);
2953 }
2954
2955 /**
2956 * @brief Disable HSE crystal oscillator (HSE ON)
2957 * @rmtoll CR HSEON LL_RCC_HSE_Disable
2958 * @retval None
2959 */
LL_RCC_HSE_Disable(void)2960 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
2961 {
2962 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
2963 }
2964
2965 /**
2966 * @brief Check if HSE oscillator Ready
2967 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
2968 * @retval State of bit (1 or 0).
2969 */
LL_RCC_HSE_IsReady(void)2970 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
2971 {
2972 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
2973 }
2974
2975 /**
2976 * @}
2977 */
2978
2979 /** @defgroup RCC_LL_EF_HSI HSI
2980 * @{
2981 */
2982
2983 /**
2984 * @brief Enable HSI oscillator
2985 * @rmtoll CR HSION LL_RCC_HSI_Enable
2986 * @retval None
2987 */
LL_RCC_HSI_Enable(void)2988 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
2989 {
2990 SET_BIT(RCC->CR, RCC_CR_HSION);
2991 }
2992
2993 /**
2994 * @brief Disable HSI oscillator
2995 * @rmtoll CR HSION LL_RCC_HSI_Disable
2996 * @retval None
2997 */
LL_RCC_HSI_Disable(void)2998 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
2999 {
3000 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
3001 }
3002
3003 /**
3004 * @brief Check if HSI clock is ready
3005 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
3006 * @retval State of bit (1 or 0).
3007 */
LL_RCC_HSI_IsReady(void)3008 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
3009 {
3010 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
3011 }
3012
3013 /**
3014 * @brief Get HSI Calibration value
3015 * @note When HSITRIM is written, HSICAL is updated with the sum of
3016 * HSITRIM and the factory trim value
3017 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
3018 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
3019 */
LL_RCC_HSI_GetCalibration(void)3020 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
3021 {
3022 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
3023 }
3024
3025 /**
3026 * @brief Set HSI Calibration trimming
3027 * @note user-programmable trimming value that is added to the HSICAL
3028 * @note Default value is 16, which, when added to the HSICAL value,
3029 * should trim the HSI to 16 MHz +/- 1 %
3030 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
3031 * @param Value Between Min_Data = 0 and Max_Data = 31
3032 * @retval None
3033 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)3034 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
3035 {
3036 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
3037 }
3038
3039 /**
3040 * @brief Get HSI Calibration trimming
3041 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
3042 * @retval Between Min_Data = 0 and Max_Data = 31
3043 */
LL_RCC_HSI_GetCalibTrimming(void)3044 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
3045 {
3046 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
3047 }
3048
3049 /**
3050 * @}
3051 */
3052
3053 /** @defgroup RCC_LL_EF_LSE LSE
3054 * @{
3055 */
3056
3057 /**
3058 * @brief Enable Low Speed External (LSE) crystal.
3059 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
3060 * @retval None
3061 */
LL_RCC_LSE_Enable(void)3062 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
3063 {
3064 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3065 }
3066
3067 /**
3068 * @brief Disable Low Speed External (LSE) crystal.
3069 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
3070 * @retval None
3071 */
LL_RCC_LSE_Disable(void)3072 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
3073 {
3074 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3075 }
3076
3077 /**
3078 * @brief Enable external clock source (LSE bypass).
3079 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
3080 * @retval None
3081 */
LL_RCC_LSE_EnableBypass(void)3082 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
3083 {
3084 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3085 }
3086
3087 /**
3088 * @brief Disable external clock source (LSE bypass).
3089 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
3090 * @retval None
3091 */
LL_RCC_LSE_DisableBypass(void)3092 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
3093 {
3094 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3095 }
3096
3097 /**
3098 * @brief Check if LSE oscillator Ready
3099 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
3100 * @retval State of bit (1 or 0).
3101 */
LL_RCC_LSE_IsReady(void)3102 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
3103 {
3104 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
3105 }
3106
3107 #if defined(RCC_BDCR_LSEMOD)
3108 /**
3109 * @brief Enable LSE high drive mode.
3110 * @note LSE high drive mode can be enabled only when the LSE clock is disabled
3111 * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode
3112 * @retval None
3113 */
LL_RCC_LSE_EnableHighDriveMode(void)3114 __STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
3115 {
3116 SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3117 }
3118
3119 /**
3120 * @brief Disable LSE high drive mode.
3121 * @note LSE high drive mode can be disabled only when the LSE clock is disabled
3122 * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode
3123 * @retval None
3124 */
LL_RCC_LSE_DisableHighDriveMode(void)3125 __STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
3126 {
3127 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3128 }
3129 #endif /* RCC_BDCR_LSEMOD */
3130
3131 /**
3132 * @}
3133 */
3134
3135 /** @defgroup RCC_LL_EF_LSI LSI
3136 * @{
3137 */
3138
3139 /**
3140 * @brief Enable LSI Oscillator
3141 * @rmtoll CSR LSION LL_RCC_LSI_Enable
3142 * @retval None
3143 */
LL_RCC_LSI_Enable(void)3144 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
3145 {
3146 SET_BIT(RCC->CSR, RCC_CSR_LSION);
3147 }
3148
3149 /**
3150 * @brief Disable LSI Oscillator
3151 * @rmtoll CSR LSION LL_RCC_LSI_Disable
3152 * @retval None
3153 */
LL_RCC_LSI_Disable(void)3154 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
3155 {
3156 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
3157 }
3158
3159 /**
3160 * @brief Check if LSI is Ready
3161 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
3162 * @retval State of bit (1 or 0).
3163 */
LL_RCC_LSI_IsReady(void)3164 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
3165 {
3166 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
3167 }
3168
3169 /**
3170 * @}
3171 */
3172
3173 /** @defgroup RCC_LL_EF_System System
3174 * @{
3175 */
3176
3177 /**
3178 * @brief Configure the system clock source
3179 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
3180 * @param Source This parameter can be one of the following values:
3181 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
3182 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
3183 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
3184 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
3185 *
3186 * (*) value not defined in all devices.
3187 * @retval None
3188 */
LL_RCC_SetSysClkSource(uint32_t Source)3189 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
3190 {
3191 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
3192 }
3193
3194 /**
3195 * @brief Get the system clock source
3196 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
3197 * @retval Returned value can be one of the following values:
3198 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
3199 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
3200 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
3201 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
3202 *
3203 * (*) value not defined in all devices.
3204 */
LL_RCC_GetSysClkSource(void)3205 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
3206 {
3207 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
3208 }
3209
3210 /**
3211 * @brief Set AHB prescaler
3212 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
3213 * @param Prescaler This parameter can be one of the following values:
3214 * @arg @ref LL_RCC_SYSCLK_DIV_1
3215 * @arg @ref LL_RCC_SYSCLK_DIV_2
3216 * @arg @ref LL_RCC_SYSCLK_DIV_4
3217 * @arg @ref LL_RCC_SYSCLK_DIV_8
3218 * @arg @ref LL_RCC_SYSCLK_DIV_16
3219 * @arg @ref LL_RCC_SYSCLK_DIV_64
3220 * @arg @ref LL_RCC_SYSCLK_DIV_128
3221 * @arg @ref LL_RCC_SYSCLK_DIV_256
3222 * @arg @ref LL_RCC_SYSCLK_DIV_512
3223 * @retval None
3224 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)3225 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
3226 {
3227 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
3228 }
3229
3230 /**
3231 * @brief Set APB1 prescaler
3232 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
3233 * @param Prescaler This parameter can be one of the following values:
3234 * @arg @ref LL_RCC_APB1_DIV_1
3235 * @arg @ref LL_RCC_APB1_DIV_2
3236 * @arg @ref LL_RCC_APB1_DIV_4
3237 * @arg @ref LL_RCC_APB1_DIV_8
3238 * @arg @ref LL_RCC_APB1_DIV_16
3239 * @retval None
3240 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)3241 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
3242 {
3243 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
3244 }
3245
3246 /**
3247 * @brief Set APB2 prescaler
3248 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
3249 * @param Prescaler This parameter can be one of the following values:
3250 * @arg @ref LL_RCC_APB2_DIV_1
3251 * @arg @ref LL_RCC_APB2_DIV_2
3252 * @arg @ref LL_RCC_APB2_DIV_4
3253 * @arg @ref LL_RCC_APB2_DIV_8
3254 * @arg @ref LL_RCC_APB2_DIV_16
3255 * @retval None
3256 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)3257 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
3258 {
3259 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
3260 }
3261
3262 /**
3263 * @brief Get AHB prescaler
3264 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
3265 * @retval Returned value can be one of the following values:
3266 * @arg @ref LL_RCC_SYSCLK_DIV_1
3267 * @arg @ref LL_RCC_SYSCLK_DIV_2
3268 * @arg @ref LL_RCC_SYSCLK_DIV_4
3269 * @arg @ref LL_RCC_SYSCLK_DIV_8
3270 * @arg @ref LL_RCC_SYSCLK_DIV_16
3271 * @arg @ref LL_RCC_SYSCLK_DIV_64
3272 * @arg @ref LL_RCC_SYSCLK_DIV_128
3273 * @arg @ref LL_RCC_SYSCLK_DIV_256
3274 * @arg @ref LL_RCC_SYSCLK_DIV_512
3275 */
LL_RCC_GetAHBPrescaler(void)3276 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
3277 {
3278 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
3279 }
3280
3281 /**
3282 * @brief Get APB1 prescaler
3283 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
3284 * @retval Returned value can be one of the following values:
3285 * @arg @ref LL_RCC_APB1_DIV_1
3286 * @arg @ref LL_RCC_APB1_DIV_2
3287 * @arg @ref LL_RCC_APB1_DIV_4
3288 * @arg @ref LL_RCC_APB1_DIV_8
3289 * @arg @ref LL_RCC_APB1_DIV_16
3290 */
LL_RCC_GetAPB1Prescaler(void)3291 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
3292 {
3293 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
3294 }
3295
3296 /**
3297 * @brief Get APB2 prescaler
3298 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
3299 * @retval Returned value can be one of the following values:
3300 * @arg @ref LL_RCC_APB2_DIV_1
3301 * @arg @ref LL_RCC_APB2_DIV_2
3302 * @arg @ref LL_RCC_APB2_DIV_4
3303 * @arg @ref LL_RCC_APB2_DIV_8
3304 * @arg @ref LL_RCC_APB2_DIV_16
3305 */
LL_RCC_GetAPB2Prescaler(void)3306 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
3307 {
3308 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
3309 }
3310
3311 /**
3312 * @}
3313 */
3314
3315 /** @defgroup RCC_LL_EF_MCO MCO
3316 * @{
3317 */
3318
3319 #if defined(RCC_CFGR_MCO1EN)
3320 /**
3321 * @brief Enable MCO1 output
3322 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable
3323 * @retval None
3324 */
LL_RCC_MCO1_Enable(void)3325 __STATIC_INLINE void LL_RCC_MCO1_Enable(void)
3326 {
3327 SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3328 }
3329
3330 /**
3331 * @brief Disable MCO1 output
3332 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable
3333 * @retval None
3334 */
LL_RCC_MCO1_Disable(void)3335 __STATIC_INLINE void LL_RCC_MCO1_Disable(void)
3336 {
3337 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3338 }
3339 #endif /* RCC_CFGR_MCO1EN */
3340
3341 #if defined(RCC_CFGR_MCO2EN)
3342 /**
3343 * @brief Enable MCO2 output
3344 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable
3345 * @retval None
3346 */
LL_RCC_MCO2_Enable(void)3347 __STATIC_INLINE void LL_RCC_MCO2_Enable(void)
3348 {
3349 SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3350 }
3351
3352 /**
3353 * @brief Disable MCO2 output
3354 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable
3355 * @retval None
3356 */
LL_RCC_MCO2_Disable(void)3357 __STATIC_INLINE void LL_RCC_MCO2_Disable(void)
3358 {
3359 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3360 }
3361 #endif /* RCC_CFGR_MCO2EN */
3362
3363 /**
3364 * @brief Configure MCOx
3365 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
3366 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
3367 * CFGR MCO2 LL_RCC_ConfigMCO\n
3368 * CFGR MCO2PRE LL_RCC_ConfigMCO
3369 * @param MCOxSource This parameter can be one of the following values:
3370 * @arg @ref LL_RCC_MCO1SOURCE_HSI
3371 * @arg @ref LL_RCC_MCO1SOURCE_LSE
3372 * @arg @ref LL_RCC_MCO1SOURCE_HSE
3373 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
3374 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
3375 * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
3376 * @arg @ref LL_RCC_MCO2SOURCE_HSE
3377 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
3378 * @param MCOxPrescaler This parameter can be one of the following values:
3379 * @arg @ref LL_RCC_MCO1_DIV_1
3380 * @arg @ref LL_RCC_MCO1_DIV_2
3381 * @arg @ref LL_RCC_MCO1_DIV_3
3382 * @arg @ref LL_RCC_MCO1_DIV_4
3383 * @arg @ref LL_RCC_MCO1_DIV_5
3384 * @arg @ref LL_RCC_MCO2_DIV_1
3385 * @arg @ref LL_RCC_MCO2_DIV_2
3386 * @arg @ref LL_RCC_MCO2_DIV_3
3387 * @arg @ref LL_RCC_MCO2_DIV_4
3388 * @arg @ref LL_RCC_MCO2_DIV_5
3389 * @retval None
3390 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)3391 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
3392 {
3393 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
3394 }
3395
3396 /**
3397 * @}
3398 */
3399
3400 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
3401 * @{
3402 */
3403 #if defined(FMPI2C1)
3404 /**
3405 * @brief Configure FMPI2C clock source
3406 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource
3407 * @param FMPI2CxSource This parameter can be one of the following values:
3408 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
3409 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
3410 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
3411 * @retval None
3412 */
LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)3413 __STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
3414 {
3415 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
3416 }
3417 #endif /* FMPI2C1 */
3418
3419 #if defined(LPTIM1)
3420 /**
3421 * @brief Configure LPTIMx clock source
3422 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
3423 * @param LPTIMxSource This parameter can be one of the following values:
3424 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3425 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3426 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3427 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3428 * @retval None
3429 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)3430 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
3431 {
3432 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
3433 }
3434 #endif /* LPTIM1 */
3435
3436 #if defined(SAI1)
3437 /**
3438 * @brief Configure SAIx clock source
3439 * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n
3440 * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n
3441 * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n
3442 * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource
3443 * @param SAIxSource This parameter can be one of the following values:
3444 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
3445 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
3446 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
3447 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3448 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
3449 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
3450 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3451 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
3452 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
3453 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
3454 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
3455 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
3456 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
3457 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
3458 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
3459 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
3460 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
3461 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
3462 *
3463 * (*) value not defined in all devices.
3464 * @retval None
3465 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)3466 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
3467 {
3468 MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
3469 }
3470 #endif /* SAI1 */
3471
3472 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3473 /**
3474 * @brief Configure SDIO clock source
3475 * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n
3476 * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource
3477 * @param SDIOxSource This parameter can be one of the following values:
3478 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
3479 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
3480 * @retval None
3481 */
LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)3482 __STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
3483 {
3484 #if defined(RCC_DCKCFGR_SDIOSEL)
3485 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
3486 #else
3487 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
3488 #endif /* RCC_DCKCFGR_SDIOSEL */
3489 }
3490 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3491
3492 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3493 /**
3494 * @brief Configure 48Mhz domain clock source
3495 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n
3496 * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
3497 * @param CK48MxSource This parameter can be one of the following values:
3498 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
3499 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
3500 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
3501 *
3502 * (*) value not defined in all devices.
3503 * @retval None
3504 */
LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)3505 __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
3506 {
3507 #if defined(RCC_DCKCFGR_CK48MSEL)
3508 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
3509 #else
3510 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
3511 #endif /* RCC_DCKCFGR_CK48MSEL */
3512 }
3513
3514 #if defined(RNG)
3515 /**
3516 * @brief Configure RNG clock source
3517 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n
3518 * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
3519 * @param RNGxSource This parameter can be one of the following values:
3520 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3521 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
3522 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
3523 *
3524 * (*) value not defined in all devices.
3525 * @retval None
3526 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)3527 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
3528 {
3529 #if defined(RCC_DCKCFGR_CK48MSEL)
3530 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
3531 #else
3532 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
3533 #endif /* RCC_DCKCFGR_CK48MSEL */
3534 }
3535 #endif /* RNG */
3536
3537 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3538 /**
3539 * @brief Configure USB clock source
3540 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n
3541 * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
3542 * @param USBxSource This parameter can be one of the following values:
3543 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3544 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
3545 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
3546 *
3547 * (*) value not defined in all devices.
3548 * @retval None
3549 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)3550 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
3551 {
3552 #if defined(RCC_DCKCFGR_CK48MSEL)
3553 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
3554 #else
3555 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
3556 #endif /* RCC_DCKCFGR_CK48MSEL */
3557 }
3558 #endif /* USB_OTG_FS || USB_OTG_HS */
3559 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3560
3561 #if defined(CEC)
3562 /**
3563 * @brief Configure CEC clock source
3564 * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
3565 * @param Source This parameter can be one of the following values:
3566 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
3567 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3568 * @retval None
3569 */
LL_RCC_SetCECClockSource(uint32_t Source)3570 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
3571 {
3572 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
3573 }
3574 #endif /* CEC */
3575
3576 /**
3577 * @brief Configure I2S clock source
3578 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n
3579 * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n
3580 * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n
3581 * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource
3582 * @param Source This parameter can be one of the following values:
3583 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
3584 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
3585 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
3586 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
3587 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
3588 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
3589 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
3590 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
3591 *
3592 * (*) value not defined in all devices.
3593 * @retval None
3594 */
LL_RCC_SetI2SClockSource(uint32_t Source)3595 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
3596 {
3597 #if defined(RCC_CFGR_I2SSRC)
3598 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
3599 #else
3600 MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
3601 #endif /* RCC_CFGR_I2SSRC */
3602 }
3603
3604 #if defined(DSI)
3605 /**
3606 * @brief Configure DSI clock source
3607 * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource
3608 * @param Source This parameter can be one of the following values:
3609 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3610 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3611 * @retval None
3612 */
LL_RCC_SetDSIClockSource(uint32_t Source)3613 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
3614 {
3615 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
3616 }
3617 #endif /* DSI */
3618
3619 #if defined(DFSDM1_Channel0)
3620 /**
3621 * @brief Configure DFSDM Audio clock source
3622 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n
3623 * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource
3624 * @param Source This parameter can be one of the following values:
3625 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
3626 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
3627 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
3628 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
3629 *
3630 * (*) value not defined in all devices.
3631 * @retval None
3632 */
LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)3633 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
3634 {
3635 MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
3636 }
3637
3638 /**
3639 * @brief Configure DFSDM Kernel clock source
3640 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource
3641 * @param Source This parameter can be one of the following values:
3642 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3643 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3644 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
3645 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
3646 *
3647 * (*) value not defined in all devices.
3648 * @retval None
3649 */
LL_RCC_SetDFSDMClockSource(uint32_t Source)3650 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
3651 {
3652 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
3653 }
3654 #endif /* DFSDM1_Channel0 */
3655
3656 #if defined(SPDIFRX)
3657 /**
3658 * @brief Configure SPDIFRX clock source
3659 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource
3660 * @param SPDIFRXxSource This parameter can be one of the following values:
3661 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
3662 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
3663 *
3664 * (*) value not defined in all devices.
3665 * @retval None
3666 */
LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)3667 __STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
3668 {
3669 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
3670 }
3671 #endif /* SPDIFRX */
3672
3673 #if defined(FMPI2C1)
3674 /**
3675 * @brief Get FMPI2C clock source
3676 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource
3677 * @param FMPI2Cx This parameter can be one of the following values:
3678 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
3679 * @retval Returned value can be one of the following values:
3680 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
3681 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
3682 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
3683 */
LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)3684 __STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
3685 {
3686 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
3687 }
3688 #endif /* FMPI2C1 */
3689
3690 #if defined(LPTIM1)
3691 /**
3692 * @brief Get LPTIMx clock source
3693 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
3694 * @param LPTIMx This parameter can be one of the following values:
3695 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3696 * @retval Returned value can be one of the following values:
3697 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3698 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3699 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3700 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3701 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)3702 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
3703 {
3704 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
3705 }
3706 #endif /* LPTIM1 */
3707
3708 #if defined(SAI1)
3709 /**
3710 * @brief Get SAIx clock source
3711 * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n
3712 * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n
3713 * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n
3714 * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource
3715 * @param SAIx This parameter can be one of the following values:
3716 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
3717 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
3718 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
3719 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
3720 *
3721 * (*) value not defined in all devices.
3722 * @retval Returned value can be one of the following values:
3723 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
3724 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
3725 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
3726 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3727 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
3728 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
3729 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3730 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
3731 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
3732 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
3733 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
3734 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
3735 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
3736 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
3737 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
3738 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
3739 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
3740 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
3741 *
3742 * (*) value not defined in all devices.
3743 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)3744 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
3745 {
3746 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);
3747 }
3748 #endif /* SAI1 */
3749
3750 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3751 /**
3752 * @brief Get SDIOx clock source
3753 * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n
3754 * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource
3755 * @param SDIOx This parameter can be one of the following values:
3756 * @arg @ref LL_RCC_SDIO_CLKSOURCE
3757 * @retval Returned value can be one of the following values:
3758 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
3759 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
3760 */
LL_RCC_GetSDIOClockSource(uint32_t SDIOx)3761 __STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
3762 {
3763 #if defined(RCC_DCKCFGR_SDIOSEL)
3764 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
3765 #else
3766 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
3767 #endif /* RCC_DCKCFGR_SDIOSEL */
3768 }
3769 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3770
3771 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3772 /**
3773 * @brief Get 48Mhz domain clock source
3774 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n
3775 * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
3776 * @param CK48Mx This parameter can be one of the following values:
3777 * @arg @ref LL_RCC_CK48M_CLKSOURCE
3778 * @retval Returned value can be one of the following values:
3779 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
3780 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
3781 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
3782 *
3783 * (*) value not defined in all devices.
3784 */
LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)3785 __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
3786 {
3787 #if defined(RCC_DCKCFGR_CK48MSEL)
3788 return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
3789 #else
3790 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
3791 #endif /* RCC_DCKCFGR_CK48MSEL */
3792 }
3793
3794 #if defined(RNG)
3795 /**
3796 * @brief Get RNGx clock source
3797 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n
3798 * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
3799 * @param RNGx This parameter can be one of the following values:
3800 * @arg @ref LL_RCC_RNG_CLKSOURCE
3801 * @retval Returned value can be one of the following values:
3802 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3803 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
3804 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
3805 *
3806 * (*) value not defined in all devices.
3807 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)3808 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
3809 {
3810 #if defined(RCC_DCKCFGR_CK48MSEL)
3811 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
3812 #else
3813 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
3814 #endif /* RCC_DCKCFGR_CK48MSEL */
3815 }
3816 #endif /* RNG */
3817
3818 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3819 /**
3820 * @brief Get USBx clock source
3821 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n
3822 * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
3823 * @param USBx This parameter can be one of the following values:
3824 * @arg @ref LL_RCC_USB_CLKSOURCE
3825 * @retval Returned value can be one of the following values:
3826 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3827 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
3828 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
3829 *
3830 * (*) value not defined in all devices.
3831 */
LL_RCC_GetUSBClockSource(uint32_t USBx)3832 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
3833 {
3834 #if defined(RCC_DCKCFGR_CK48MSEL)
3835 return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
3836 #else
3837 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
3838 #endif /* RCC_DCKCFGR_CK48MSEL */
3839 }
3840 #endif /* USB_OTG_FS || USB_OTG_HS */
3841 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3842
3843 #if defined(CEC)
3844 /**
3845 * @brief Get CEC Clock Source
3846 * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
3847 * @param CECx This parameter can be one of the following values:
3848 * @arg @ref LL_RCC_CEC_CLKSOURCE
3849 * @retval Returned value can be one of the following values:
3850 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
3851 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3852 */
LL_RCC_GetCECClockSource(uint32_t CECx)3853 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
3854 {
3855 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
3856 }
3857 #endif /* CEC */
3858
3859 /**
3860 * @brief Get I2S Clock Source
3861 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n
3862 * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n
3863 * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n
3864 * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource
3865 * @param I2Sx This parameter can be one of the following values:
3866 * @arg @ref LL_RCC_I2S1_CLKSOURCE
3867 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
3868 * @retval Returned value can be one of the following values:
3869 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
3870 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
3871 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
3872 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
3873 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
3874 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
3875 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
3876 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
3877 *
3878 * (*) value not defined in all devices.
3879 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)3880 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
3881 {
3882 #if defined(RCC_CFGR_I2SSRC)
3883 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
3884 #else
3885 return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);
3886 #endif /* RCC_CFGR_I2SSRC */
3887 }
3888
3889 #if defined(DFSDM1_Channel0)
3890 /**
3891 * @brief Get DFSDM Audio Clock Source
3892 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n
3893 * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource
3894 * @param DFSDMx This parameter can be one of the following values:
3895 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
3896 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
3897 * @retval Returned value can be one of the following values:
3898 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
3899 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
3900 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
3901 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
3902 *
3903 * (*) value not defined in all devices.
3904 */
LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)3905 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
3906 {
3907 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);
3908 }
3909
3910 /**
3911 * @brief Get DFSDM Audio Clock Source
3912 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource
3913 * @param DFSDMx This parameter can be one of the following values:
3914 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
3915 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
3916 * @retval Returned value can be one of the following values:
3917 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3918 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3919 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
3920 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
3921 *
3922 * (*) value not defined in all devices.
3923 */
LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)3924 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
3925 {
3926 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
3927 }
3928 #endif /* DFSDM1_Channel0 */
3929
3930 #if defined(SPDIFRX)
3931 /**
3932 * @brief Get SPDIFRX clock source
3933 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource
3934 * @param SPDIFRXx This parameter can be one of the following values:
3935 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
3936 * @retval Returned value can be one of the following values:
3937 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
3938 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
3939 *
3940 * (*) value not defined in all devices.
3941 */
LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)3942 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
3943 {
3944 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
3945 }
3946 #endif /* SPDIFRX */
3947
3948 #if defined(DSI)
3949 /**
3950 * @brief Get DSI Clock Source
3951 * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource
3952 * @param DSIx This parameter can be one of the following values:
3953 * @arg @ref LL_RCC_DSI_CLKSOURCE
3954 * @retval Returned value can be one of the following values:
3955 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3956 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3957 */
LL_RCC_GetDSIClockSource(uint32_t DSIx)3958 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
3959 {
3960 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
3961 }
3962 #endif /* DSI */
3963
3964 /**
3965 * @}
3966 */
3967
3968 /** @defgroup RCC_LL_EF_RTC RTC
3969 * @{
3970 */
3971
3972 /**
3973 * @brief Set RTC Clock Source
3974 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3975 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3976 * set). The BDRST bit can be used to reset them.
3977 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3978 * @param Source This parameter can be one of the following values:
3979 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3980 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3981 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3982 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3983 * @retval None
3984 */
LL_RCC_SetRTCClockSource(uint32_t Source)3985 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3986 {
3987 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3988 }
3989
3990 /**
3991 * @brief Get RTC Clock Source
3992 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
3993 * @retval Returned value can be one of the following values:
3994 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3995 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3996 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3997 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3998 */
LL_RCC_GetRTCClockSource(void)3999 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
4000 {
4001 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
4002 }
4003
4004 /**
4005 * @brief Enable RTC
4006 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
4007 * @retval None
4008 */
LL_RCC_EnableRTC(void)4009 __STATIC_INLINE void LL_RCC_EnableRTC(void)
4010 {
4011 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4012 }
4013
4014 /**
4015 * @brief Disable RTC
4016 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
4017 * @retval None
4018 */
LL_RCC_DisableRTC(void)4019 __STATIC_INLINE void LL_RCC_DisableRTC(void)
4020 {
4021 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4022 }
4023
4024 /**
4025 * @brief Check if RTC has been enabled or not
4026 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
4027 * @retval State of bit (1 or 0).
4028 */
LL_RCC_IsEnabledRTC(void)4029 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
4030 {
4031 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
4032 }
4033
4034 /**
4035 * @brief Force the Backup domain reset
4036 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
4037 * @retval None
4038 */
LL_RCC_ForceBackupDomainReset(void)4039 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
4040 {
4041 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4042 }
4043
4044 /**
4045 * @brief Release the Backup domain reset
4046 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
4047 * @retval None
4048 */
LL_RCC_ReleaseBackupDomainReset(void)4049 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
4050 {
4051 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4052 }
4053
4054 /**
4055 * @brief Set HSE Prescalers for RTC Clock
4056 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
4057 * @param Prescaler This parameter can be one of the following values:
4058 * @arg @ref LL_RCC_RTC_NOCLOCK
4059 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4060 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4061 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4062 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4063 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4064 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4065 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4066 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4067 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4068 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4069 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4070 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4071 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4072 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4073 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4074 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4075 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4076 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4077 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4078 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4079 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4080 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4081 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4082 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4083 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4084 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4085 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4086 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4087 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4088 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4089 * @retval None
4090 */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)4091 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4092 {
4093 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
4094 }
4095
4096 /**
4097 * @brief Get HSE Prescalers for RTC Clock
4098 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
4099 * @retval Returned value can be one of the following values:
4100 * @arg @ref LL_RCC_RTC_NOCLOCK
4101 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4102 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4103 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4104 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4105 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4106 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4107 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4108 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4109 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4110 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4111 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4112 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4113 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4114 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4115 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4116 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4117 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4118 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4119 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4120 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4121 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4122 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4123 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4124 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4125 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4126 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4127 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4128 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4129 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4130 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4131 */
LL_RCC_GetRTC_HSEPrescaler(void)4132 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4133 {
4134 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
4135 }
4136
4137 /**
4138 * @}
4139 */
4140
4141 #if defined(RCC_DCKCFGR_TIMPRE)
4142 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4143 * @{
4144 */
4145
4146 /**
4147 * @brief Set Timers Clock Prescalers
4148 * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler
4149 * @param Prescaler This parameter can be one of the following values:
4150 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4151 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4152 * @retval None
4153 */
LL_RCC_SetTIMPrescaler(uint32_t Prescaler)4154 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4155 {
4156 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
4157 }
4158
4159 /**
4160 * @brief Get Timers Clock Prescalers
4161 * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler
4162 * @retval Returned value can be one of the following values:
4163 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4164 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4165 */
LL_RCC_GetTIMPrescaler(void)4166 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4167 {
4168 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
4169 }
4170
4171 /**
4172 * @}
4173 */
4174 #endif /* RCC_DCKCFGR_TIMPRE */
4175
4176 /** @defgroup RCC_LL_EF_PLL PLL
4177 * @{
4178 */
4179
4180 /**
4181 * @brief Enable PLL
4182 * @rmtoll CR PLLON LL_RCC_PLL_Enable
4183 * @retval None
4184 */
LL_RCC_PLL_Enable(void)4185 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
4186 {
4187 SET_BIT(RCC->CR, RCC_CR_PLLON);
4188 }
4189
4190 /**
4191 * @brief Disable PLL
4192 * @note Cannot be disabled if the PLL clock is used as the system clock
4193 * @rmtoll CR PLLON LL_RCC_PLL_Disable
4194 * @retval None
4195 */
LL_RCC_PLL_Disable(void)4196 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
4197 {
4198 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
4199 }
4200
4201 /**
4202 * @brief Check if PLL Ready
4203 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
4204 * @retval State of bit (1 or 0).
4205 */
LL_RCC_PLL_IsReady(void)4206 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
4207 {
4208 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
4209 }
4210
4211 /**
4212 * @brief Configure PLL used for SYSCLK Domain
4213 * @note PLL Source and PLLM Divider can be written only when PLL,
4214 * PLLI2S and PLLSAI(*) are disabled
4215 * @note PLLN/PLLP can be written only when PLL is disabled
4216 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
4217 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
4218 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
4219 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n
4220 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
4221 * @param Source This parameter can be one of the following values:
4222 * @arg @ref LL_RCC_PLLSOURCE_HSI
4223 * @arg @ref LL_RCC_PLLSOURCE_HSE
4224 * @param PLLM This parameter can be one of the following values:
4225 * @arg @ref LL_RCC_PLLM_DIV_2
4226 * @arg @ref LL_RCC_PLLM_DIV_3
4227 * @arg @ref LL_RCC_PLLM_DIV_4
4228 * @arg @ref LL_RCC_PLLM_DIV_5
4229 * @arg @ref LL_RCC_PLLM_DIV_6
4230 * @arg @ref LL_RCC_PLLM_DIV_7
4231 * @arg @ref LL_RCC_PLLM_DIV_8
4232 * @arg @ref LL_RCC_PLLM_DIV_9
4233 * @arg @ref LL_RCC_PLLM_DIV_10
4234 * @arg @ref LL_RCC_PLLM_DIV_11
4235 * @arg @ref LL_RCC_PLLM_DIV_12
4236 * @arg @ref LL_RCC_PLLM_DIV_13
4237 * @arg @ref LL_RCC_PLLM_DIV_14
4238 * @arg @ref LL_RCC_PLLM_DIV_15
4239 * @arg @ref LL_RCC_PLLM_DIV_16
4240 * @arg @ref LL_RCC_PLLM_DIV_17
4241 * @arg @ref LL_RCC_PLLM_DIV_18
4242 * @arg @ref LL_RCC_PLLM_DIV_19
4243 * @arg @ref LL_RCC_PLLM_DIV_20
4244 * @arg @ref LL_RCC_PLLM_DIV_21
4245 * @arg @ref LL_RCC_PLLM_DIV_22
4246 * @arg @ref LL_RCC_PLLM_DIV_23
4247 * @arg @ref LL_RCC_PLLM_DIV_24
4248 * @arg @ref LL_RCC_PLLM_DIV_25
4249 * @arg @ref LL_RCC_PLLM_DIV_26
4250 * @arg @ref LL_RCC_PLLM_DIV_27
4251 * @arg @ref LL_RCC_PLLM_DIV_28
4252 * @arg @ref LL_RCC_PLLM_DIV_29
4253 * @arg @ref LL_RCC_PLLM_DIV_30
4254 * @arg @ref LL_RCC_PLLM_DIV_31
4255 * @arg @ref LL_RCC_PLLM_DIV_32
4256 * @arg @ref LL_RCC_PLLM_DIV_33
4257 * @arg @ref LL_RCC_PLLM_DIV_34
4258 * @arg @ref LL_RCC_PLLM_DIV_35
4259 * @arg @ref LL_RCC_PLLM_DIV_36
4260 * @arg @ref LL_RCC_PLLM_DIV_37
4261 * @arg @ref LL_RCC_PLLM_DIV_38
4262 * @arg @ref LL_RCC_PLLM_DIV_39
4263 * @arg @ref LL_RCC_PLLM_DIV_40
4264 * @arg @ref LL_RCC_PLLM_DIV_41
4265 * @arg @ref LL_RCC_PLLM_DIV_42
4266 * @arg @ref LL_RCC_PLLM_DIV_43
4267 * @arg @ref LL_RCC_PLLM_DIV_44
4268 * @arg @ref LL_RCC_PLLM_DIV_45
4269 * @arg @ref LL_RCC_PLLM_DIV_46
4270 * @arg @ref LL_RCC_PLLM_DIV_47
4271 * @arg @ref LL_RCC_PLLM_DIV_48
4272 * @arg @ref LL_RCC_PLLM_DIV_49
4273 * @arg @ref LL_RCC_PLLM_DIV_50
4274 * @arg @ref LL_RCC_PLLM_DIV_51
4275 * @arg @ref LL_RCC_PLLM_DIV_52
4276 * @arg @ref LL_RCC_PLLM_DIV_53
4277 * @arg @ref LL_RCC_PLLM_DIV_54
4278 * @arg @ref LL_RCC_PLLM_DIV_55
4279 * @arg @ref LL_RCC_PLLM_DIV_56
4280 * @arg @ref LL_RCC_PLLM_DIV_57
4281 * @arg @ref LL_RCC_PLLM_DIV_58
4282 * @arg @ref LL_RCC_PLLM_DIV_59
4283 * @arg @ref LL_RCC_PLLM_DIV_60
4284 * @arg @ref LL_RCC_PLLM_DIV_61
4285 * @arg @ref LL_RCC_PLLM_DIV_62
4286 * @arg @ref LL_RCC_PLLM_DIV_63
4287 * @param PLLN Between 50/192(*) and 432
4288 *
4289 * (*) value not defined in all devices.
4290 * @param PLLP_R This parameter can be one of the following values:
4291 * @arg @ref LL_RCC_PLLP_DIV_2
4292 * @arg @ref LL_RCC_PLLP_DIV_4
4293 * @arg @ref LL_RCC_PLLP_DIV_6
4294 * @arg @ref LL_RCC_PLLP_DIV_8
4295 * @arg @ref LL_RCC_PLLR_DIV_2 (*)
4296 * @arg @ref LL_RCC_PLLR_DIV_3 (*)
4297 * @arg @ref LL_RCC_PLLR_DIV_4 (*)
4298 * @arg @ref LL_RCC_PLLR_DIV_5 (*)
4299 * @arg @ref LL_RCC_PLLR_DIV_6 (*)
4300 * @arg @ref LL_RCC_PLLR_DIV_7 (*)
4301 *
4302 * (*) value not defined in all devices.
4303 * @retval None
4304 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP_R)4305 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
4306 {
4307 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,
4308 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);
4309 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
4310 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
4311 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
4312 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
4313 }
4314
4315 /**
4316 * @brief Configure PLL used for 48Mhz domain clock
4317 * @note PLL Source and PLLM Divider can be written only when PLL,
4318 * PLLI2S and PLLSAI(*) are disabled
4319 * @note PLLN/PLLQ can be written only when PLL is disabled
4320 * @note This can be selected for USB, RNG, SDIO
4321 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
4322 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
4323 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
4324 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
4325 * @param Source This parameter can be one of the following values:
4326 * @arg @ref LL_RCC_PLLSOURCE_HSI
4327 * @arg @ref LL_RCC_PLLSOURCE_HSE
4328 * @param PLLM This parameter can be one of the following values:
4329 * @arg @ref LL_RCC_PLLM_DIV_2
4330 * @arg @ref LL_RCC_PLLM_DIV_3
4331 * @arg @ref LL_RCC_PLLM_DIV_4
4332 * @arg @ref LL_RCC_PLLM_DIV_5
4333 * @arg @ref LL_RCC_PLLM_DIV_6
4334 * @arg @ref LL_RCC_PLLM_DIV_7
4335 * @arg @ref LL_RCC_PLLM_DIV_8
4336 * @arg @ref LL_RCC_PLLM_DIV_9
4337 * @arg @ref LL_RCC_PLLM_DIV_10
4338 * @arg @ref LL_RCC_PLLM_DIV_11
4339 * @arg @ref LL_RCC_PLLM_DIV_12
4340 * @arg @ref LL_RCC_PLLM_DIV_13
4341 * @arg @ref LL_RCC_PLLM_DIV_14
4342 * @arg @ref LL_RCC_PLLM_DIV_15
4343 * @arg @ref LL_RCC_PLLM_DIV_16
4344 * @arg @ref LL_RCC_PLLM_DIV_17
4345 * @arg @ref LL_RCC_PLLM_DIV_18
4346 * @arg @ref LL_RCC_PLLM_DIV_19
4347 * @arg @ref LL_RCC_PLLM_DIV_20
4348 * @arg @ref LL_RCC_PLLM_DIV_21
4349 * @arg @ref LL_RCC_PLLM_DIV_22
4350 * @arg @ref LL_RCC_PLLM_DIV_23
4351 * @arg @ref LL_RCC_PLLM_DIV_24
4352 * @arg @ref LL_RCC_PLLM_DIV_25
4353 * @arg @ref LL_RCC_PLLM_DIV_26
4354 * @arg @ref LL_RCC_PLLM_DIV_27
4355 * @arg @ref LL_RCC_PLLM_DIV_28
4356 * @arg @ref LL_RCC_PLLM_DIV_29
4357 * @arg @ref LL_RCC_PLLM_DIV_30
4358 * @arg @ref LL_RCC_PLLM_DIV_31
4359 * @arg @ref LL_RCC_PLLM_DIV_32
4360 * @arg @ref LL_RCC_PLLM_DIV_33
4361 * @arg @ref LL_RCC_PLLM_DIV_34
4362 * @arg @ref LL_RCC_PLLM_DIV_35
4363 * @arg @ref LL_RCC_PLLM_DIV_36
4364 * @arg @ref LL_RCC_PLLM_DIV_37
4365 * @arg @ref LL_RCC_PLLM_DIV_38
4366 * @arg @ref LL_RCC_PLLM_DIV_39
4367 * @arg @ref LL_RCC_PLLM_DIV_40
4368 * @arg @ref LL_RCC_PLLM_DIV_41
4369 * @arg @ref LL_RCC_PLLM_DIV_42
4370 * @arg @ref LL_RCC_PLLM_DIV_43
4371 * @arg @ref LL_RCC_PLLM_DIV_44
4372 * @arg @ref LL_RCC_PLLM_DIV_45
4373 * @arg @ref LL_RCC_PLLM_DIV_46
4374 * @arg @ref LL_RCC_PLLM_DIV_47
4375 * @arg @ref LL_RCC_PLLM_DIV_48
4376 * @arg @ref LL_RCC_PLLM_DIV_49
4377 * @arg @ref LL_RCC_PLLM_DIV_50
4378 * @arg @ref LL_RCC_PLLM_DIV_51
4379 * @arg @ref LL_RCC_PLLM_DIV_52
4380 * @arg @ref LL_RCC_PLLM_DIV_53
4381 * @arg @ref LL_RCC_PLLM_DIV_54
4382 * @arg @ref LL_RCC_PLLM_DIV_55
4383 * @arg @ref LL_RCC_PLLM_DIV_56
4384 * @arg @ref LL_RCC_PLLM_DIV_57
4385 * @arg @ref LL_RCC_PLLM_DIV_58
4386 * @arg @ref LL_RCC_PLLM_DIV_59
4387 * @arg @ref LL_RCC_PLLM_DIV_60
4388 * @arg @ref LL_RCC_PLLM_DIV_61
4389 * @arg @ref LL_RCC_PLLM_DIV_62
4390 * @arg @ref LL_RCC_PLLM_DIV_63
4391 * @param PLLN Between 50/192(*) and 432
4392 *
4393 * (*) value not defined in all devices.
4394 * @param PLLQ This parameter can be one of the following values:
4395 * @arg @ref LL_RCC_PLLQ_DIV_2
4396 * @arg @ref LL_RCC_PLLQ_DIV_3
4397 * @arg @ref LL_RCC_PLLQ_DIV_4
4398 * @arg @ref LL_RCC_PLLQ_DIV_5
4399 * @arg @ref LL_RCC_PLLQ_DIV_6
4400 * @arg @ref LL_RCC_PLLQ_DIV_7
4401 * @arg @ref LL_RCC_PLLQ_DIV_8
4402 * @arg @ref LL_RCC_PLLQ_DIV_9
4403 * @arg @ref LL_RCC_PLLQ_DIV_10
4404 * @arg @ref LL_RCC_PLLQ_DIV_11
4405 * @arg @ref LL_RCC_PLLQ_DIV_12
4406 * @arg @ref LL_RCC_PLLQ_DIV_13
4407 * @arg @ref LL_RCC_PLLQ_DIV_14
4408 * @arg @ref LL_RCC_PLLQ_DIV_15
4409 * @retval None
4410 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)4411 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4412 {
4413 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
4414 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
4415 }
4416
4417 #if defined(DSI)
4418 /**
4419 * @brief Configure PLL used for DSI clock
4420 * @note PLL Source and PLLM Divider can be written only when PLL,
4421 * PLLI2S and PLLSAI are disabled
4422 * @note PLLN/PLLR can be written only when PLL is disabled
4423 * @note This can be selected for DSI
4424 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
4425 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
4426 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
4427 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
4428 * @param Source This parameter can be one of the following values:
4429 * @arg @ref LL_RCC_PLLSOURCE_HSI
4430 * @arg @ref LL_RCC_PLLSOURCE_HSE
4431 * @param PLLM This parameter can be one of the following values:
4432 * @arg @ref LL_RCC_PLLM_DIV_2
4433 * @arg @ref LL_RCC_PLLM_DIV_3
4434 * @arg @ref LL_RCC_PLLM_DIV_4
4435 * @arg @ref LL_RCC_PLLM_DIV_5
4436 * @arg @ref LL_RCC_PLLM_DIV_6
4437 * @arg @ref LL_RCC_PLLM_DIV_7
4438 * @arg @ref LL_RCC_PLLM_DIV_8
4439 * @arg @ref LL_RCC_PLLM_DIV_9
4440 * @arg @ref LL_RCC_PLLM_DIV_10
4441 * @arg @ref LL_RCC_PLLM_DIV_11
4442 * @arg @ref LL_RCC_PLLM_DIV_12
4443 * @arg @ref LL_RCC_PLLM_DIV_13
4444 * @arg @ref LL_RCC_PLLM_DIV_14
4445 * @arg @ref LL_RCC_PLLM_DIV_15
4446 * @arg @ref LL_RCC_PLLM_DIV_16
4447 * @arg @ref LL_RCC_PLLM_DIV_17
4448 * @arg @ref LL_RCC_PLLM_DIV_18
4449 * @arg @ref LL_RCC_PLLM_DIV_19
4450 * @arg @ref LL_RCC_PLLM_DIV_20
4451 * @arg @ref LL_RCC_PLLM_DIV_21
4452 * @arg @ref LL_RCC_PLLM_DIV_22
4453 * @arg @ref LL_RCC_PLLM_DIV_23
4454 * @arg @ref LL_RCC_PLLM_DIV_24
4455 * @arg @ref LL_RCC_PLLM_DIV_25
4456 * @arg @ref LL_RCC_PLLM_DIV_26
4457 * @arg @ref LL_RCC_PLLM_DIV_27
4458 * @arg @ref LL_RCC_PLLM_DIV_28
4459 * @arg @ref LL_RCC_PLLM_DIV_29
4460 * @arg @ref LL_RCC_PLLM_DIV_30
4461 * @arg @ref LL_RCC_PLLM_DIV_31
4462 * @arg @ref LL_RCC_PLLM_DIV_32
4463 * @arg @ref LL_RCC_PLLM_DIV_33
4464 * @arg @ref LL_RCC_PLLM_DIV_34
4465 * @arg @ref LL_RCC_PLLM_DIV_35
4466 * @arg @ref LL_RCC_PLLM_DIV_36
4467 * @arg @ref LL_RCC_PLLM_DIV_37
4468 * @arg @ref LL_RCC_PLLM_DIV_38
4469 * @arg @ref LL_RCC_PLLM_DIV_39
4470 * @arg @ref LL_RCC_PLLM_DIV_40
4471 * @arg @ref LL_RCC_PLLM_DIV_41
4472 * @arg @ref LL_RCC_PLLM_DIV_42
4473 * @arg @ref LL_RCC_PLLM_DIV_43
4474 * @arg @ref LL_RCC_PLLM_DIV_44
4475 * @arg @ref LL_RCC_PLLM_DIV_45
4476 * @arg @ref LL_RCC_PLLM_DIV_46
4477 * @arg @ref LL_RCC_PLLM_DIV_47
4478 * @arg @ref LL_RCC_PLLM_DIV_48
4479 * @arg @ref LL_RCC_PLLM_DIV_49
4480 * @arg @ref LL_RCC_PLLM_DIV_50
4481 * @arg @ref LL_RCC_PLLM_DIV_51
4482 * @arg @ref LL_RCC_PLLM_DIV_52
4483 * @arg @ref LL_RCC_PLLM_DIV_53
4484 * @arg @ref LL_RCC_PLLM_DIV_54
4485 * @arg @ref LL_RCC_PLLM_DIV_55
4486 * @arg @ref LL_RCC_PLLM_DIV_56
4487 * @arg @ref LL_RCC_PLLM_DIV_57
4488 * @arg @ref LL_RCC_PLLM_DIV_58
4489 * @arg @ref LL_RCC_PLLM_DIV_59
4490 * @arg @ref LL_RCC_PLLM_DIV_60
4491 * @arg @ref LL_RCC_PLLM_DIV_61
4492 * @arg @ref LL_RCC_PLLM_DIV_62
4493 * @arg @ref LL_RCC_PLLM_DIV_63
4494 * @param PLLN Between 50 and 432
4495 * @param PLLR This parameter can be one of the following values:
4496 * @arg @ref LL_RCC_PLLR_DIV_2
4497 * @arg @ref LL_RCC_PLLR_DIV_3
4498 * @arg @ref LL_RCC_PLLR_DIV_4
4499 * @arg @ref LL_RCC_PLLR_DIV_5
4500 * @arg @ref LL_RCC_PLLR_DIV_6
4501 * @arg @ref LL_RCC_PLLR_DIV_7
4502 * @retval None
4503 */
LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4504 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4505 {
4506 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4507 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4508 }
4509 #endif /* DSI */
4510
4511 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
4512 /**
4513 * @brief Configure PLL used for I2S clock
4514 * @note PLL Source and PLLM Divider can be written only when PLL,
4515 * PLLI2S and PLLSAI are disabled
4516 * @note PLLN/PLLR can be written only when PLL is disabled
4517 * @note This can be selected for I2S
4518 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n
4519 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n
4520 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n
4521 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S
4522 * @param Source This parameter can be one of the following values:
4523 * @arg @ref LL_RCC_PLLSOURCE_HSI
4524 * @arg @ref LL_RCC_PLLSOURCE_HSE
4525 * @param PLLM This parameter can be one of the following values:
4526 * @arg @ref LL_RCC_PLLM_DIV_2
4527 * @arg @ref LL_RCC_PLLM_DIV_3
4528 * @arg @ref LL_RCC_PLLM_DIV_4
4529 * @arg @ref LL_RCC_PLLM_DIV_5
4530 * @arg @ref LL_RCC_PLLM_DIV_6
4531 * @arg @ref LL_RCC_PLLM_DIV_7
4532 * @arg @ref LL_RCC_PLLM_DIV_8
4533 * @arg @ref LL_RCC_PLLM_DIV_9
4534 * @arg @ref LL_RCC_PLLM_DIV_10
4535 * @arg @ref LL_RCC_PLLM_DIV_11
4536 * @arg @ref LL_RCC_PLLM_DIV_12
4537 * @arg @ref LL_RCC_PLLM_DIV_13
4538 * @arg @ref LL_RCC_PLLM_DIV_14
4539 * @arg @ref LL_RCC_PLLM_DIV_15
4540 * @arg @ref LL_RCC_PLLM_DIV_16
4541 * @arg @ref LL_RCC_PLLM_DIV_17
4542 * @arg @ref LL_RCC_PLLM_DIV_18
4543 * @arg @ref LL_RCC_PLLM_DIV_19
4544 * @arg @ref LL_RCC_PLLM_DIV_20
4545 * @arg @ref LL_RCC_PLLM_DIV_21
4546 * @arg @ref LL_RCC_PLLM_DIV_22
4547 * @arg @ref LL_RCC_PLLM_DIV_23
4548 * @arg @ref LL_RCC_PLLM_DIV_24
4549 * @arg @ref LL_RCC_PLLM_DIV_25
4550 * @arg @ref LL_RCC_PLLM_DIV_26
4551 * @arg @ref LL_RCC_PLLM_DIV_27
4552 * @arg @ref LL_RCC_PLLM_DIV_28
4553 * @arg @ref LL_RCC_PLLM_DIV_29
4554 * @arg @ref LL_RCC_PLLM_DIV_30
4555 * @arg @ref LL_RCC_PLLM_DIV_31
4556 * @arg @ref LL_RCC_PLLM_DIV_32
4557 * @arg @ref LL_RCC_PLLM_DIV_33
4558 * @arg @ref LL_RCC_PLLM_DIV_34
4559 * @arg @ref LL_RCC_PLLM_DIV_35
4560 * @arg @ref LL_RCC_PLLM_DIV_36
4561 * @arg @ref LL_RCC_PLLM_DIV_37
4562 * @arg @ref LL_RCC_PLLM_DIV_38
4563 * @arg @ref LL_RCC_PLLM_DIV_39
4564 * @arg @ref LL_RCC_PLLM_DIV_40
4565 * @arg @ref LL_RCC_PLLM_DIV_41
4566 * @arg @ref LL_RCC_PLLM_DIV_42
4567 * @arg @ref LL_RCC_PLLM_DIV_43
4568 * @arg @ref LL_RCC_PLLM_DIV_44
4569 * @arg @ref LL_RCC_PLLM_DIV_45
4570 * @arg @ref LL_RCC_PLLM_DIV_46
4571 * @arg @ref LL_RCC_PLLM_DIV_47
4572 * @arg @ref LL_RCC_PLLM_DIV_48
4573 * @arg @ref LL_RCC_PLLM_DIV_49
4574 * @arg @ref LL_RCC_PLLM_DIV_50
4575 * @arg @ref LL_RCC_PLLM_DIV_51
4576 * @arg @ref LL_RCC_PLLM_DIV_52
4577 * @arg @ref LL_RCC_PLLM_DIV_53
4578 * @arg @ref LL_RCC_PLLM_DIV_54
4579 * @arg @ref LL_RCC_PLLM_DIV_55
4580 * @arg @ref LL_RCC_PLLM_DIV_56
4581 * @arg @ref LL_RCC_PLLM_DIV_57
4582 * @arg @ref LL_RCC_PLLM_DIV_58
4583 * @arg @ref LL_RCC_PLLM_DIV_59
4584 * @arg @ref LL_RCC_PLLM_DIV_60
4585 * @arg @ref LL_RCC_PLLM_DIV_61
4586 * @arg @ref LL_RCC_PLLM_DIV_62
4587 * @arg @ref LL_RCC_PLLM_DIV_63
4588 * @param PLLN Between 50 and 432
4589 * @param PLLR This parameter can be one of the following values:
4590 * @arg @ref LL_RCC_PLLR_DIV_2
4591 * @arg @ref LL_RCC_PLLR_DIV_3
4592 * @arg @ref LL_RCC_PLLR_DIV_4
4593 * @arg @ref LL_RCC_PLLR_DIV_5
4594 * @arg @ref LL_RCC_PLLR_DIV_6
4595 * @arg @ref LL_RCC_PLLR_DIV_7
4596 * @retval None
4597 */
LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4598 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4599 {
4600 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4601 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4602 }
4603 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
4604
4605 #if defined(SPDIFRX)
4606 /**
4607 * @brief Configure PLL used for SPDIFRX clock
4608 * @note PLL Source and PLLM Divider can be written only when PLL,
4609 * PLLI2S and PLLSAI are disabled
4610 * @note PLLN/PLLR can be written only when PLL is disabled
4611 * @note This can be selected for SPDIFRX
4612 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4613 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4614 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4615 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX
4616 * @param Source This parameter can be one of the following values:
4617 * @arg @ref LL_RCC_PLLSOURCE_HSI
4618 * @arg @ref LL_RCC_PLLSOURCE_HSE
4619 * @param PLLM This parameter can be one of the following values:
4620 * @arg @ref LL_RCC_PLLM_DIV_2
4621 * @arg @ref LL_RCC_PLLM_DIV_3
4622 * @arg @ref LL_RCC_PLLM_DIV_4
4623 * @arg @ref LL_RCC_PLLM_DIV_5
4624 * @arg @ref LL_RCC_PLLM_DIV_6
4625 * @arg @ref LL_RCC_PLLM_DIV_7
4626 * @arg @ref LL_RCC_PLLM_DIV_8
4627 * @arg @ref LL_RCC_PLLM_DIV_9
4628 * @arg @ref LL_RCC_PLLM_DIV_10
4629 * @arg @ref LL_RCC_PLLM_DIV_11
4630 * @arg @ref LL_RCC_PLLM_DIV_12
4631 * @arg @ref LL_RCC_PLLM_DIV_13
4632 * @arg @ref LL_RCC_PLLM_DIV_14
4633 * @arg @ref LL_RCC_PLLM_DIV_15
4634 * @arg @ref LL_RCC_PLLM_DIV_16
4635 * @arg @ref LL_RCC_PLLM_DIV_17
4636 * @arg @ref LL_RCC_PLLM_DIV_18
4637 * @arg @ref LL_RCC_PLLM_DIV_19
4638 * @arg @ref LL_RCC_PLLM_DIV_20
4639 * @arg @ref LL_RCC_PLLM_DIV_21
4640 * @arg @ref LL_RCC_PLLM_DIV_22
4641 * @arg @ref LL_RCC_PLLM_DIV_23
4642 * @arg @ref LL_RCC_PLLM_DIV_24
4643 * @arg @ref LL_RCC_PLLM_DIV_25
4644 * @arg @ref LL_RCC_PLLM_DIV_26
4645 * @arg @ref LL_RCC_PLLM_DIV_27
4646 * @arg @ref LL_RCC_PLLM_DIV_28
4647 * @arg @ref LL_RCC_PLLM_DIV_29
4648 * @arg @ref LL_RCC_PLLM_DIV_30
4649 * @arg @ref LL_RCC_PLLM_DIV_31
4650 * @arg @ref LL_RCC_PLLM_DIV_32
4651 * @arg @ref LL_RCC_PLLM_DIV_33
4652 * @arg @ref LL_RCC_PLLM_DIV_34
4653 * @arg @ref LL_RCC_PLLM_DIV_35
4654 * @arg @ref LL_RCC_PLLM_DIV_36
4655 * @arg @ref LL_RCC_PLLM_DIV_37
4656 * @arg @ref LL_RCC_PLLM_DIV_38
4657 * @arg @ref LL_RCC_PLLM_DIV_39
4658 * @arg @ref LL_RCC_PLLM_DIV_40
4659 * @arg @ref LL_RCC_PLLM_DIV_41
4660 * @arg @ref LL_RCC_PLLM_DIV_42
4661 * @arg @ref LL_RCC_PLLM_DIV_43
4662 * @arg @ref LL_RCC_PLLM_DIV_44
4663 * @arg @ref LL_RCC_PLLM_DIV_45
4664 * @arg @ref LL_RCC_PLLM_DIV_46
4665 * @arg @ref LL_RCC_PLLM_DIV_47
4666 * @arg @ref LL_RCC_PLLM_DIV_48
4667 * @arg @ref LL_RCC_PLLM_DIV_49
4668 * @arg @ref LL_RCC_PLLM_DIV_50
4669 * @arg @ref LL_RCC_PLLM_DIV_51
4670 * @arg @ref LL_RCC_PLLM_DIV_52
4671 * @arg @ref LL_RCC_PLLM_DIV_53
4672 * @arg @ref LL_RCC_PLLM_DIV_54
4673 * @arg @ref LL_RCC_PLLM_DIV_55
4674 * @arg @ref LL_RCC_PLLM_DIV_56
4675 * @arg @ref LL_RCC_PLLM_DIV_57
4676 * @arg @ref LL_RCC_PLLM_DIV_58
4677 * @arg @ref LL_RCC_PLLM_DIV_59
4678 * @arg @ref LL_RCC_PLLM_DIV_60
4679 * @arg @ref LL_RCC_PLLM_DIV_61
4680 * @arg @ref LL_RCC_PLLM_DIV_62
4681 * @arg @ref LL_RCC_PLLM_DIV_63
4682 * @param PLLN Between 50 and 432
4683 * @param PLLR This parameter can be one of the following values:
4684 * @arg @ref LL_RCC_PLLR_DIV_2
4685 * @arg @ref LL_RCC_PLLR_DIV_3
4686 * @arg @ref LL_RCC_PLLR_DIV_4
4687 * @arg @ref LL_RCC_PLLR_DIV_5
4688 * @arg @ref LL_RCC_PLLR_DIV_6
4689 * @arg @ref LL_RCC_PLLR_DIV_7
4690 * @retval None
4691 */
LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4692 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4693 {
4694 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4695 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4696 }
4697 #endif /* SPDIFRX */
4698
4699 #if defined(RCC_PLLCFGR_PLLR)
4700 #if defined(SAI1)
4701 /**
4702 * @brief Configure PLL used for SAI clock
4703 * @note PLL Source and PLLM Divider can be written only when PLL,
4704 * PLLI2S and PLLSAI are disabled
4705 * @note PLLN/PLLR can be written only when PLL is disabled
4706 * @note This can be selected for SAI
4707 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
4708 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
4709 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
4710 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n
4711 * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI
4712 * @param Source This parameter can be one of the following values:
4713 * @arg @ref LL_RCC_PLLSOURCE_HSI
4714 * @arg @ref LL_RCC_PLLSOURCE_HSE
4715 * @param PLLM This parameter can be one of the following values:
4716 * @arg @ref LL_RCC_PLLM_DIV_2
4717 * @arg @ref LL_RCC_PLLM_DIV_3
4718 * @arg @ref LL_RCC_PLLM_DIV_4
4719 * @arg @ref LL_RCC_PLLM_DIV_5
4720 * @arg @ref LL_RCC_PLLM_DIV_6
4721 * @arg @ref LL_RCC_PLLM_DIV_7
4722 * @arg @ref LL_RCC_PLLM_DIV_8
4723 * @arg @ref LL_RCC_PLLM_DIV_9
4724 * @arg @ref LL_RCC_PLLM_DIV_10
4725 * @arg @ref LL_RCC_PLLM_DIV_11
4726 * @arg @ref LL_RCC_PLLM_DIV_12
4727 * @arg @ref LL_RCC_PLLM_DIV_13
4728 * @arg @ref LL_RCC_PLLM_DIV_14
4729 * @arg @ref LL_RCC_PLLM_DIV_15
4730 * @arg @ref LL_RCC_PLLM_DIV_16
4731 * @arg @ref LL_RCC_PLLM_DIV_17
4732 * @arg @ref LL_RCC_PLLM_DIV_18
4733 * @arg @ref LL_RCC_PLLM_DIV_19
4734 * @arg @ref LL_RCC_PLLM_DIV_20
4735 * @arg @ref LL_RCC_PLLM_DIV_21
4736 * @arg @ref LL_RCC_PLLM_DIV_22
4737 * @arg @ref LL_RCC_PLLM_DIV_23
4738 * @arg @ref LL_RCC_PLLM_DIV_24
4739 * @arg @ref LL_RCC_PLLM_DIV_25
4740 * @arg @ref LL_RCC_PLLM_DIV_26
4741 * @arg @ref LL_RCC_PLLM_DIV_27
4742 * @arg @ref LL_RCC_PLLM_DIV_28
4743 * @arg @ref LL_RCC_PLLM_DIV_29
4744 * @arg @ref LL_RCC_PLLM_DIV_30
4745 * @arg @ref LL_RCC_PLLM_DIV_31
4746 * @arg @ref LL_RCC_PLLM_DIV_32
4747 * @arg @ref LL_RCC_PLLM_DIV_33
4748 * @arg @ref LL_RCC_PLLM_DIV_34
4749 * @arg @ref LL_RCC_PLLM_DIV_35
4750 * @arg @ref LL_RCC_PLLM_DIV_36
4751 * @arg @ref LL_RCC_PLLM_DIV_37
4752 * @arg @ref LL_RCC_PLLM_DIV_38
4753 * @arg @ref LL_RCC_PLLM_DIV_39
4754 * @arg @ref LL_RCC_PLLM_DIV_40
4755 * @arg @ref LL_RCC_PLLM_DIV_41
4756 * @arg @ref LL_RCC_PLLM_DIV_42
4757 * @arg @ref LL_RCC_PLLM_DIV_43
4758 * @arg @ref LL_RCC_PLLM_DIV_44
4759 * @arg @ref LL_RCC_PLLM_DIV_45
4760 * @arg @ref LL_RCC_PLLM_DIV_46
4761 * @arg @ref LL_RCC_PLLM_DIV_47
4762 * @arg @ref LL_RCC_PLLM_DIV_48
4763 * @arg @ref LL_RCC_PLLM_DIV_49
4764 * @arg @ref LL_RCC_PLLM_DIV_50
4765 * @arg @ref LL_RCC_PLLM_DIV_51
4766 * @arg @ref LL_RCC_PLLM_DIV_52
4767 * @arg @ref LL_RCC_PLLM_DIV_53
4768 * @arg @ref LL_RCC_PLLM_DIV_54
4769 * @arg @ref LL_RCC_PLLM_DIV_55
4770 * @arg @ref LL_RCC_PLLM_DIV_56
4771 * @arg @ref LL_RCC_PLLM_DIV_57
4772 * @arg @ref LL_RCC_PLLM_DIV_58
4773 * @arg @ref LL_RCC_PLLM_DIV_59
4774 * @arg @ref LL_RCC_PLLM_DIV_60
4775 * @arg @ref LL_RCC_PLLM_DIV_61
4776 * @arg @ref LL_RCC_PLLM_DIV_62
4777 * @arg @ref LL_RCC_PLLM_DIV_63
4778 * @param PLLN Between 50 and 432
4779 * @param PLLR This parameter can be one of the following values:
4780 * @arg @ref LL_RCC_PLLR_DIV_2
4781 * @arg @ref LL_RCC_PLLR_DIV_3
4782 * @arg @ref LL_RCC_PLLR_DIV_4
4783 * @arg @ref LL_RCC_PLLR_DIV_5
4784 * @arg @ref LL_RCC_PLLR_DIV_6
4785 * @arg @ref LL_RCC_PLLR_DIV_7
4786 * @param PLLDIVR This parameter can be one of the following values:
4787 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
4788 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
4789 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
4790 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
4791 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
4792 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
4793 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
4794 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
4795 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
4796 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
4797 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
4798 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
4799 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
4800 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
4801 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
4802 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
4803 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
4804 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
4805 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
4806 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
4807 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
4808 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
4809 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
4810 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
4811 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
4812 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
4813 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
4814 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
4815 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
4816 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
4817 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
4818 *
4819 * (*) value not defined in all devices.
4820 * @retval None
4821 */
4822 #if defined(RCC_DCKCFGR_PLLDIVR)
LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR,uint32_t PLLDIVR)4823 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR,
4824 uint32_t PLLDIVR)
4825 #else
4826 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4827 #endif /* RCC_DCKCFGR_PLLDIVR */
4828 {
4829 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4830 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4831 #if defined(RCC_DCKCFGR_PLLDIVR)
4832 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
4833 #endif /* RCC_DCKCFGR_PLLDIVR */
4834 }
4835 #endif /* SAI1 */
4836 #endif /* RCC_PLLCFGR_PLLR */
4837
4838 /**
4839 * @brief Configure PLL clock source
4840 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
4841 * @param PLLSource This parameter can be one of the following values:
4842 * @arg @ref LL_RCC_PLLSOURCE_HSI
4843 * @arg @ref LL_RCC_PLLSOURCE_HSE
4844 * @retval None
4845 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)4846 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
4847 {
4848 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
4849 }
4850
4851 /**
4852 * @brief Get the oscillator used as PLL clock source.
4853 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
4854 * @retval Returned value can be one of the following values:
4855 * @arg @ref LL_RCC_PLLSOURCE_HSI
4856 * @arg @ref LL_RCC_PLLSOURCE_HSE
4857 */
LL_RCC_PLL_GetMainSource(void)4858 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
4859 {
4860 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
4861 }
4862
4863 /**
4864 * @brief Get Main PLL multiplication factor for VCO
4865 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
4866 * @retval Between 50/192(*) and 432
4867 *
4868 * (*) value not defined in all devices.
4869 */
LL_RCC_PLL_GetN(void)4870 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
4871 {
4872 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
4873 }
4874
4875 /**
4876 * @brief Get Main PLL division factor for PLLP
4877 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
4878 * @retval Returned value can be one of the following values:
4879 * @arg @ref LL_RCC_PLLP_DIV_2
4880 * @arg @ref LL_RCC_PLLP_DIV_4
4881 * @arg @ref LL_RCC_PLLP_DIV_6
4882 * @arg @ref LL_RCC_PLLP_DIV_8
4883 */
LL_RCC_PLL_GetP(void)4884 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4885 {
4886 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
4887 }
4888
4889 /**
4890 * @brief Get Main PLL division factor for PLLQ
4891 * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
4892 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
4893 * @retval Returned value can be one of the following values:
4894 * @arg @ref LL_RCC_PLLQ_DIV_2
4895 * @arg @ref LL_RCC_PLLQ_DIV_3
4896 * @arg @ref LL_RCC_PLLQ_DIV_4
4897 * @arg @ref LL_RCC_PLLQ_DIV_5
4898 * @arg @ref LL_RCC_PLLQ_DIV_6
4899 * @arg @ref LL_RCC_PLLQ_DIV_7
4900 * @arg @ref LL_RCC_PLLQ_DIV_8
4901 * @arg @ref LL_RCC_PLLQ_DIV_9
4902 * @arg @ref LL_RCC_PLLQ_DIV_10
4903 * @arg @ref LL_RCC_PLLQ_DIV_11
4904 * @arg @ref LL_RCC_PLLQ_DIV_12
4905 * @arg @ref LL_RCC_PLLQ_DIV_13
4906 * @arg @ref LL_RCC_PLLQ_DIV_14
4907 * @arg @ref LL_RCC_PLLQ_DIV_15
4908 */
LL_RCC_PLL_GetQ(void)4909 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
4910 {
4911 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
4912 }
4913
4914 #if defined(RCC_PLLCFGR_PLLR)
4915 /**
4916 * @brief Get Main PLL division factor for PLLR
4917 * @note used for PLLCLK (system clock)
4918 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
4919 * @retval Returned value can be one of the following values:
4920 * @arg @ref LL_RCC_PLLR_DIV_2
4921 * @arg @ref LL_RCC_PLLR_DIV_3
4922 * @arg @ref LL_RCC_PLLR_DIV_4
4923 * @arg @ref LL_RCC_PLLR_DIV_5
4924 * @arg @ref LL_RCC_PLLR_DIV_6
4925 * @arg @ref LL_RCC_PLLR_DIV_7
4926 */
LL_RCC_PLL_GetR(void)4927 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
4928 {
4929 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
4930 }
4931 #endif /* RCC_PLLCFGR_PLLR */
4932
4933 #if defined(RCC_DCKCFGR_PLLDIVR)
4934 /**
4935 * @brief Get Main PLL division factor for PLLDIVR
4936 * @note used for PLLSAICLK (SAI1 and SAI2 clock)
4937 * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR
4938 * @retval Returned value can be one of the following values:
4939 * @arg @ref LL_RCC_PLLDIVR_DIV_1
4940 * @arg @ref LL_RCC_PLLDIVR_DIV_2
4941 * @arg @ref LL_RCC_PLLDIVR_DIV_3
4942 * @arg @ref LL_RCC_PLLDIVR_DIV_4
4943 * @arg @ref LL_RCC_PLLDIVR_DIV_5
4944 * @arg @ref LL_RCC_PLLDIVR_DIV_6
4945 * @arg @ref LL_RCC_PLLDIVR_DIV_7
4946 * @arg @ref LL_RCC_PLLDIVR_DIV_8
4947 * @arg @ref LL_RCC_PLLDIVR_DIV_9
4948 * @arg @ref LL_RCC_PLLDIVR_DIV_10
4949 * @arg @ref LL_RCC_PLLDIVR_DIV_11
4950 * @arg @ref LL_RCC_PLLDIVR_DIV_12
4951 * @arg @ref LL_RCC_PLLDIVR_DIV_13
4952 * @arg @ref LL_RCC_PLLDIVR_DIV_14
4953 * @arg @ref LL_RCC_PLLDIVR_DIV_15
4954 * @arg @ref LL_RCC_PLLDIVR_DIV_16
4955 * @arg @ref LL_RCC_PLLDIVR_DIV_17
4956 * @arg @ref LL_RCC_PLLDIVR_DIV_18
4957 * @arg @ref LL_RCC_PLLDIVR_DIV_19
4958 * @arg @ref LL_RCC_PLLDIVR_DIV_20
4959 * @arg @ref LL_RCC_PLLDIVR_DIV_21
4960 * @arg @ref LL_RCC_PLLDIVR_DIV_22
4961 * @arg @ref LL_RCC_PLLDIVR_DIV_23
4962 * @arg @ref LL_RCC_PLLDIVR_DIV_24
4963 * @arg @ref LL_RCC_PLLDIVR_DIV_25
4964 * @arg @ref LL_RCC_PLLDIVR_DIV_26
4965 * @arg @ref LL_RCC_PLLDIVR_DIV_27
4966 * @arg @ref LL_RCC_PLLDIVR_DIV_28
4967 * @arg @ref LL_RCC_PLLDIVR_DIV_29
4968 * @arg @ref LL_RCC_PLLDIVR_DIV_30
4969 * @arg @ref LL_RCC_PLLDIVR_DIV_31
4970 */
LL_RCC_PLL_GetDIVR(void)4971 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
4972 {
4973 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
4974 }
4975 #endif /* RCC_DCKCFGR_PLLDIVR */
4976
4977 /**
4978 * @brief Get Division factor for the main PLL and other PLL
4979 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
4980 * @retval Returned value can be one of the following values:
4981 * @arg @ref LL_RCC_PLLM_DIV_2
4982 * @arg @ref LL_RCC_PLLM_DIV_3
4983 * @arg @ref LL_RCC_PLLM_DIV_4
4984 * @arg @ref LL_RCC_PLLM_DIV_5
4985 * @arg @ref LL_RCC_PLLM_DIV_6
4986 * @arg @ref LL_RCC_PLLM_DIV_7
4987 * @arg @ref LL_RCC_PLLM_DIV_8
4988 * @arg @ref LL_RCC_PLLM_DIV_9
4989 * @arg @ref LL_RCC_PLLM_DIV_10
4990 * @arg @ref LL_RCC_PLLM_DIV_11
4991 * @arg @ref LL_RCC_PLLM_DIV_12
4992 * @arg @ref LL_RCC_PLLM_DIV_13
4993 * @arg @ref LL_RCC_PLLM_DIV_14
4994 * @arg @ref LL_RCC_PLLM_DIV_15
4995 * @arg @ref LL_RCC_PLLM_DIV_16
4996 * @arg @ref LL_RCC_PLLM_DIV_17
4997 * @arg @ref LL_RCC_PLLM_DIV_18
4998 * @arg @ref LL_RCC_PLLM_DIV_19
4999 * @arg @ref LL_RCC_PLLM_DIV_20
5000 * @arg @ref LL_RCC_PLLM_DIV_21
5001 * @arg @ref LL_RCC_PLLM_DIV_22
5002 * @arg @ref LL_RCC_PLLM_DIV_23
5003 * @arg @ref LL_RCC_PLLM_DIV_24
5004 * @arg @ref LL_RCC_PLLM_DIV_25
5005 * @arg @ref LL_RCC_PLLM_DIV_26
5006 * @arg @ref LL_RCC_PLLM_DIV_27
5007 * @arg @ref LL_RCC_PLLM_DIV_28
5008 * @arg @ref LL_RCC_PLLM_DIV_29
5009 * @arg @ref LL_RCC_PLLM_DIV_30
5010 * @arg @ref LL_RCC_PLLM_DIV_31
5011 * @arg @ref LL_RCC_PLLM_DIV_32
5012 * @arg @ref LL_RCC_PLLM_DIV_33
5013 * @arg @ref LL_RCC_PLLM_DIV_34
5014 * @arg @ref LL_RCC_PLLM_DIV_35
5015 * @arg @ref LL_RCC_PLLM_DIV_36
5016 * @arg @ref LL_RCC_PLLM_DIV_37
5017 * @arg @ref LL_RCC_PLLM_DIV_38
5018 * @arg @ref LL_RCC_PLLM_DIV_39
5019 * @arg @ref LL_RCC_PLLM_DIV_40
5020 * @arg @ref LL_RCC_PLLM_DIV_41
5021 * @arg @ref LL_RCC_PLLM_DIV_42
5022 * @arg @ref LL_RCC_PLLM_DIV_43
5023 * @arg @ref LL_RCC_PLLM_DIV_44
5024 * @arg @ref LL_RCC_PLLM_DIV_45
5025 * @arg @ref LL_RCC_PLLM_DIV_46
5026 * @arg @ref LL_RCC_PLLM_DIV_47
5027 * @arg @ref LL_RCC_PLLM_DIV_48
5028 * @arg @ref LL_RCC_PLLM_DIV_49
5029 * @arg @ref LL_RCC_PLLM_DIV_50
5030 * @arg @ref LL_RCC_PLLM_DIV_51
5031 * @arg @ref LL_RCC_PLLM_DIV_52
5032 * @arg @ref LL_RCC_PLLM_DIV_53
5033 * @arg @ref LL_RCC_PLLM_DIV_54
5034 * @arg @ref LL_RCC_PLLM_DIV_55
5035 * @arg @ref LL_RCC_PLLM_DIV_56
5036 * @arg @ref LL_RCC_PLLM_DIV_57
5037 * @arg @ref LL_RCC_PLLM_DIV_58
5038 * @arg @ref LL_RCC_PLLM_DIV_59
5039 * @arg @ref LL_RCC_PLLM_DIV_60
5040 * @arg @ref LL_RCC_PLLM_DIV_61
5041 * @arg @ref LL_RCC_PLLM_DIV_62
5042 * @arg @ref LL_RCC_PLLM_DIV_63
5043 */
LL_RCC_PLL_GetDivider(void)5044 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
5045 {
5046 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5047 }
5048
5049 /**
5050 * @brief Configure Spread Spectrum used for PLL
5051 * @note These bits must be written before enabling PLL
5052 * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
5053 * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
5054 * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
5055 * @param Mod Between Min_Data=0 and Max_Data=8191
5056 * @param Inc Between Min_Data=0 and Max_Data=32767
5057 * @param Sel This parameter can be one of the following values:
5058 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
5059 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
5060 * @retval None
5061 */
LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod,uint32_t Inc,uint32_t Sel)5062 __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
5063 {
5064 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
5065 }
5066
5067 /**
5068 * @brief Get Spread Spectrum Modulation Period for PLL
5069 * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
5070 * @retval Between Min_Data=0 and Max_Data=8191
5071 */
LL_RCC_PLL_GetPeriodModulation(void)5072 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
5073 {
5074 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
5075 }
5076
5077 /**
5078 * @brief Get Spread Spectrum Incrementation Step for PLL
5079 * @note Must be written before enabling PLL
5080 * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
5081 * @retval Between Min_Data=0 and Max_Data=32767
5082 */
LL_RCC_PLL_GetStepIncrementation(void)5083 __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
5084 {
5085 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
5086 }
5087
5088 /**
5089 * @brief Get Spread Spectrum Selection for PLL
5090 * @note Must be written before enabling PLL
5091 * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
5092 * @retval Returned value can be one of the following values:
5093 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
5094 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
5095 */
LL_RCC_PLL_GetSpreadSelection(void)5096 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
5097 {
5098 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
5099 }
5100
5101 /**
5102 * @brief Enable Spread Spectrum for PLL.
5103 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
5104 * @retval None
5105 */
LL_RCC_PLL_SpreadSpectrum_Enable(void)5106 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
5107 {
5108 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5109 }
5110
5111 /**
5112 * @brief Disable Spread Spectrum for PLL.
5113 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
5114 * @retval None
5115 */
LL_RCC_PLL_SpreadSpectrum_Disable(void)5116 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
5117 {
5118 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5119 }
5120
5121 /**
5122 * @}
5123 */
5124
5125 #if defined(RCC_PLLI2S_SUPPORT)
5126 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
5127 * @{
5128 */
5129
5130 /**
5131 * @brief Enable PLLI2S
5132 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
5133 * @retval None
5134 */
LL_RCC_PLLI2S_Enable(void)5135 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
5136 {
5137 SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
5138 }
5139
5140 /**
5141 * @brief Disable PLLI2S
5142 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
5143 * @retval None
5144 */
LL_RCC_PLLI2S_Disable(void)5145 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
5146 {
5147 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
5148 }
5149
5150 /**
5151 * @brief Check if PLLI2S Ready
5152 * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
5153 * @retval State of bit (1 or 0).
5154 */
LL_RCC_PLLI2S_IsReady(void)5155 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
5156 {
5157 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
5158 }
5159
5160 #if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))
5161 /**
5162 * @brief Configure PLLI2S used for SAI domain clock
5163 * @note PLL Source and PLLM Divider can be written only when PLL,
5164 * PLLI2S and PLLSAI(*) are disabled
5165 * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
5166 * @note This can be selected for SAI
5167 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
5168 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
5169 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
5170 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n
5171 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
5172 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
5173 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n
5174 * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
5175 * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI
5176 * @param Source This parameter can be one of the following values:
5177 * @arg @ref LL_RCC_PLLSOURCE_HSI
5178 * @arg @ref LL_RCC_PLLSOURCE_HSE
5179 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5180 *
5181 * (*) value not defined in all devices.
5182 * @param PLLM This parameter can be one of the following values:
5183 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5184 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5185 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5186 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5187 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5188 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5189 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5190 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5191 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5192 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5193 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5194 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5195 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5196 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5197 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5198 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5199 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5200 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5201 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5202 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5203 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5204 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5205 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5206 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5207 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5208 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5209 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5210 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5211 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5212 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5213 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5214 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5215 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5216 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5217 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5218 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5219 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5220 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5221 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5222 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5223 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5224 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5225 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5226 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5227 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5228 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5229 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5230 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5231 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5232 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5233 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5234 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5235 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5236 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5237 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5238 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5239 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5240 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5241 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5242 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5243 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5244 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5245 * @param PLLN Between 50/192(*) and 432
5246 *
5247 * (*) value not defined in all devices.
5248 * @param PLLQ_R This parameter can be one of the following values:
5249 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
5250 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
5251 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
5252 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
5253 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
5254 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
5255 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
5256 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
5257 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
5258 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
5259 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
5260 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
5261 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
5262 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
5263 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
5264 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
5265 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
5266 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
5267 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
5268 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
5269 *
5270 * (*) value not defined in all devices.
5271 * @param PLLDIVQ_R This parameter can be one of the following values:
5272 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
5273 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
5274 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
5275 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
5276 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
5277 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
5278 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
5279 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
5280 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
5281 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
5282 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
5283 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
5284 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
5285 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
5286 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
5287 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
5288 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
5289 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
5290 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
5291 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
5292 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
5293 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
5294 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
5295 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
5296 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
5297 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
5298 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
5299 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
5300 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
5301 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
5302 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
5303 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
5304 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
5305 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
5306 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
5307 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
5308 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
5309 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
5310 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
5311 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
5312 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
5313 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
5314 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
5315 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
5316 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
5317 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
5318 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
5319 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
5320 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
5321 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
5322 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
5323 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
5324 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
5325 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
5326 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
5327 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
5328 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
5329 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
5330 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
5331 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
5332 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
5333 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
5334 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
5335 *
5336 * (*) value not defined in all devices.
5337 * @retval None
5338 */
LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ_R,uint32_t PLLDIVQ_R)5339 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R,
5340 uint32_t PLLDIVQ_R)
5341 {
5342 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5343 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5344 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5345 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5346 #else
5347 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5348 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5349 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
5350 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5351 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
5352 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
5353 #else
5354 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
5355 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
5356 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5357 }
5358 #endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
5359
5360 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
5361 /**
5362 * @brief Configure PLLI2S used for 48Mhz domain clock
5363 * @note PLL Source and PLLM Divider can be written only when PLL,
5364 * PLLI2S and PLLSAI(*) are disabled
5365 * @note PLLN/PLLQ can be written only when PLLI2S is disabled
5366 * @note This can be selected for RNG, USB, SDIO
5367 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
5368 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
5369 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n
5370 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n
5371 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n
5372 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M
5373 * @param Source This parameter can be one of the following values:
5374 * @arg @ref LL_RCC_PLLSOURCE_HSI
5375 * @arg @ref LL_RCC_PLLSOURCE_HSE
5376 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5377 *
5378 * (*) value not defined in all devices.
5379 * @param PLLM This parameter can be one of the following values:
5380 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5381 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5382 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5383 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5384 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5385 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5386 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5387 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5388 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5389 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5390 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5391 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5392 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5393 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5394 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5395 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5396 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5397 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5398 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5399 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5400 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5401 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5402 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5403 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5404 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5405 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5406 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5407 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5408 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5409 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5410 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5411 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5412 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5413 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5414 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5415 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5416 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5417 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5418 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5419 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5420 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5421 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5422 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5423 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5424 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5425 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5426 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5427 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5428 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5429 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5430 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5431 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5432 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5433 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5434 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5435 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5436 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5437 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5438 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5439 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5440 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5441 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5442 * @param PLLN Between 50 and 432
5443 * @param PLLQ This parameter can be one of the following values:
5444 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
5445 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
5446 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
5447 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
5448 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
5449 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
5450 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
5451 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
5452 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
5453 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
5454 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
5455 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
5456 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
5457 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
5458 * @retval None
5459 */
LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)5460 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
5461 {
5462 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5463 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5464 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5465 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5466 #else
5467 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5468 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5469 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
5470 }
5471 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
5472
5473 #if defined(SPDIFRX)
5474 /**
5475 * @brief Configure PLLI2S used for SPDIFRX domain clock
5476 * @note PLL Source and PLLM Divider can be written only when PLL,
5477 * PLLI2S and PLLSAI(*) are disabled
5478 * @note PLLN/PLLP can be written only when PLLI2S is disabled
5479 * @note This can be selected for SPDIFRX
5480 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5481 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5482 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5483 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5484 * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
5485 * @param Source This parameter can be one of the following values:
5486 * @arg @ref LL_RCC_PLLSOURCE_HSI
5487 * @arg @ref LL_RCC_PLLSOURCE_HSE
5488 * @param PLLM This parameter can be one of the following values:
5489 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5490 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5491 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5492 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5493 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5494 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5495 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5496 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5497 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5498 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5499 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5500 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5501 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5502 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5503 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5504 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5505 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5506 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5507 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5508 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5509 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5510 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5511 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5512 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5513 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5514 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5515 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5516 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5517 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5518 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5519 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5520 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5521 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5522 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5523 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5524 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5525 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5526 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5527 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5528 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5529 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5530 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5531 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5532 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5533 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5534 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5535 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5536 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5537 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5538 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5539 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5540 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5541 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5542 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5543 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5544 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5545 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5546 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5547 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5548 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5549 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5550 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5551 * @param PLLN Between 50 and 432
5552 * @param PLLP This parameter can be one of the following values:
5553 * @arg @ref LL_RCC_PLLI2SP_DIV_2
5554 * @arg @ref LL_RCC_PLLI2SP_DIV_4
5555 * @arg @ref LL_RCC_PLLI2SP_DIV_6
5556 * @arg @ref LL_RCC_PLLI2SP_DIV_8
5557 * @retval None
5558 */
LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)5559 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
5560 {
5561 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5562 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5563 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5564 #else
5565 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5566 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5567 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
5568 }
5569 #endif /* SPDIFRX */
5570
5571 /**
5572 * @brief Configure PLLI2S used for I2S1 domain clock
5573 * @note PLL Source and PLLM Divider can be written only when PLL,
5574 * PLLI2S and PLLSAI(*) are disabled
5575 * @note PLLN/PLLR can be written only when PLLI2S is disabled
5576 * @note This can be selected for I2S
5577 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
5578 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
5579 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
5580 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n
5581 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
5582 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
5583 * @param Source This parameter can be one of the following values:
5584 * @arg @ref LL_RCC_PLLSOURCE_HSI
5585 * @arg @ref LL_RCC_PLLSOURCE_HSE
5586 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5587 *
5588 * (*) value not defined in all devices.
5589 * @param PLLM This parameter can be one of the following values:
5590 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5591 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5592 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5593 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5594 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5595 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5596 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5597 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5598 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5599 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5600 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5601 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5602 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5603 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5604 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5605 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5606 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5607 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5608 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5609 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5610 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5611 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5612 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5613 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5614 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5615 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5616 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5617 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5618 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5619 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5620 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5621 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5622 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5623 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5624 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5625 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5626 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5627 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5628 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5629 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5630 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5631 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5632 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5633 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5634 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5635 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5636 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5637 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5638 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5639 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5640 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5641 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5642 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5643 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5644 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5645 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5646 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5647 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5648 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5649 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5650 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5651 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5652 * @param PLLN Between 50/192(*) and 432
5653 *
5654 * (*) value not defined in all devices.
5655 * @param PLLR This parameter can be one of the following values:
5656 * @arg @ref LL_RCC_PLLI2SR_DIV_2
5657 * @arg @ref LL_RCC_PLLI2SR_DIV_3
5658 * @arg @ref LL_RCC_PLLI2SR_DIV_4
5659 * @arg @ref LL_RCC_PLLI2SR_DIV_5
5660 * @arg @ref LL_RCC_PLLI2SR_DIV_6
5661 * @arg @ref LL_RCC_PLLI2SR_DIV_7
5662 * @retval None
5663 */
LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)5664 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
5665 {
5666 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5667 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5668 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5669 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5670 #else
5671 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5672 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5673 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
5674 }
5675
5676 /**
5677 * @brief Get I2SPLL multiplication factor for VCO
5678 * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
5679 * @retval Between 50/192(*) and 432
5680 *
5681 * (*) value not defined in all devices.
5682 */
LL_RCC_PLLI2S_GetN(void)5683 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
5684 {
5685 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
5686 }
5687
5688 #if defined(RCC_PLLI2SCFGR_PLLI2SQ)
5689 /**
5690 * @brief Get I2SPLL division factor for PLLI2SQ
5691 * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
5692 * @retval Returned value can be one of the following values:
5693 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
5694 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
5695 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
5696 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
5697 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
5698 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
5699 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
5700 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
5701 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
5702 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
5703 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
5704 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
5705 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
5706 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
5707 */
LL_RCC_PLLI2S_GetQ(void)5708 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
5709 {
5710 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
5711 }
5712 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */
5713
5714 /**
5715 * @brief Get I2SPLL division factor for PLLI2SR
5716 * @note used for PLLI2SCLK (I2S clock)
5717 * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
5718 * @retval Returned value can be one of the following values:
5719 * @arg @ref LL_RCC_PLLI2SR_DIV_2
5720 * @arg @ref LL_RCC_PLLI2SR_DIV_3
5721 * @arg @ref LL_RCC_PLLI2SR_DIV_4
5722 * @arg @ref LL_RCC_PLLI2SR_DIV_5
5723 * @arg @ref LL_RCC_PLLI2SR_DIV_6
5724 * @arg @ref LL_RCC_PLLI2SR_DIV_7
5725 */
LL_RCC_PLLI2S_GetR(void)5726 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
5727 {
5728 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
5729 }
5730
5731 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
5732 /**
5733 * @brief Get I2SPLL division factor for PLLI2SP
5734 * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
5735 * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
5736 * @retval Returned value can be one of the following values:
5737 * @arg @ref LL_RCC_PLLI2SP_DIV_2
5738 * @arg @ref LL_RCC_PLLI2SP_DIV_4
5739 * @arg @ref LL_RCC_PLLI2SP_DIV_6
5740 * @arg @ref LL_RCC_PLLI2SP_DIV_8
5741 */
LL_RCC_PLLI2S_GetP(void)5742 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
5743 {
5744 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
5745 }
5746 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
5747
5748 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5749 /**
5750 * @brief Get I2SPLL division factor for PLLI2SDIVQ
5751 * @note used PLLSAICLK selected (SAI clock)
5752 * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
5753 * @retval Returned value can be one of the following values:
5754 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
5755 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
5756 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
5757 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
5758 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
5759 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
5760 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
5761 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
5762 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
5763 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
5764 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
5765 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
5766 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
5767 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
5768 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
5769 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
5770 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
5771 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
5772 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
5773 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
5774 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
5775 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
5776 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
5777 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
5778 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
5779 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
5780 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
5781 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
5782 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
5783 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
5784 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
5785 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
5786 */
LL_RCC_PLLI2S_GetDIVQ(void)5787 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
5788 {
5789 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
5790 }
5791 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5792
5793 #if defined(RCC_DCKCFGR_PLLI2SDIVR)
5794 /**
5795 * @brief Get I2SPLL division factor for PLLI2SDIVR
5796 * @note used PLLSAICLK selected (SAI clock)
5797 * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR
5798 * @retval Returned value can be one of the following values:
5799 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
5800 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
5801 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
5802 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
5803 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
5804 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
5805 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
5806 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
5807 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
5808 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
5809 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
5810 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
5811 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
5812 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
5813 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
5814 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
5815 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
5816 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
5817 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
5818 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
5819 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
5820 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
5821 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
5822 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
5823 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
5824 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
5825 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
5826 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
5827 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
5828 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
5829 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
5830 */
LL_RCC_PLLI2S_GetDIVR(void)5831 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
5832 {
5833 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
5834 }
5835 #endif /* RCC_DCKCFGR_PLLI2SDIVR */
5836
5837 /**
5838 * @brief Get division factor for PLLI2S input clock
5839 * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n
5840 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider
5841 * @retval Returned value can be one of the following values:
5842 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5843 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5844 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5845 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5846 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5847 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5848 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5849 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5850 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5851 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5852 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5853 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5854 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5855 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5856 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5857 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5858 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5859 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5860 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5861 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5862 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5863 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5864 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5865 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5866 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5867 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5868 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5869 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5870 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5871 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5872 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5873 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5874 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5875 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5876 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5877 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5878 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5879 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5880 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5881 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5882 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5883 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5884 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5885 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5886 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5887 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5888 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5889 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5890 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5891 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5892 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5893 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5894 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5895 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5896 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5897 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5898 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5899 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5900 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5901 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5902 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5903 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5904 */
LL_RCC_PLLI2S_GetDivider(void)5905 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
5906 {
5907 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5908 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
5909 #else
5910 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5911 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5912 }
5913
5914 /**
5915 * @brief Get the oscillator used as PLL clock source.
5916 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n
5917 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource
5918 * @retval Returned value can be one of the following values:
5919 * @arg @ref LL_RCC_PLLSOURCE_HSI
5920 * @arg @ref LL_RCC_PLLSOURCE_HSE
5921 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5922 *
5923 * (*) value not defined in all devices.
5924 */
LL_RCC_PLLI2S_GetMainSource(void)5925 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
5926 {
5927 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
5928 uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
5929 uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
5930 uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
5931 return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
5932 #else
5933 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
5934 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
5935 }
5936
5937 /**
5938 * @}
5939 */
5940 #endif /* RCC_PLLI2S_SUPPORT */
5941
5942 #if defined(RCC_PLLSAI_SUPPORT)
5943 /** @defgroup RCC_LL_EF_PLLSAI PLLSAI
5944 * @{
5945 */
5946
5947 /**
5948 * @brief Enable PLLSAI
5949 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
5950 * @retval None
5951 */
LL_RCC_PLLSAI_Enable(void)5952 __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
5953 {
5954 SET_BIT(RCC->CR, RCC_CR_PLLSAION);
5955 }
5956
5957 /**
5958 * @brief Disable PLLSAI
5959 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
5960 * @retval None
5961 */
LL_RCC_PLLSAI_Disable(void)5962 __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
5963 {
5964 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
5965 }
5966
5967 /**
5968 * @brief Check if PLLSAI Ready
5969 * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
5970 * @retval State of bit (1 or 0).
5971 */
LL_RCC_PLLSAI_IsReady(void)5972 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
5973 {
5974 return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
5975 }
5976
5977 /**
5978 * @brief Configure PLLSAI used for SAI domain clock
5979 * @note PLL Source and PLLM Divider can be written only when PLL,
5980 * PLLI2S and PLLSAI(*) are disabled
5981 * @note PLLN/PLLQ can be written only when PLLSAI is disabled
5982 * @note This can be selected for SAI
5983 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
5984 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
5985 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n
5986 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
5987 * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
5988 * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
5989 * @param Source This parameter can be one of the following values:
5990 * @arg @ref LL_RCC_PLLSOURCE_HSI
5991 * @arg @ref LL_RCC_PLLSOURCE_HSE
5992 * @param PLLM This parameter can be one of the following values:
5993 * @arg @ref LL_RCC_PLLSAIM_DIV_2
5994 * @arg @ref LL_RCC_PLLSAIM_DIV_3
5995 * @arg @ref LL_RCC_PLLSAIM_DIV_4
5996 * @arg @ref LL_RCC_PLLSAIM_DIV_5
5997 * @arg @ref LL_RCC_PLLSAIM_DIV_6
5998 * @arg @ref LL_RCC_PLLSAIM_DIV_7
5999 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6000 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6001 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6002 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6003 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6004 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6005 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6006 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6007 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6008 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6009 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6010 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6011 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6012 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6013 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6014 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6015 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6016 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6017 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6018 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6019 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6020 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6021 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6022 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6023 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6024 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6025 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6026 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6027 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6028 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6029 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6030 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6031 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6032 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6033 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6034 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6035 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6036 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6037 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6038 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6039 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6040 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6041 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6042 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6043 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6044 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6045 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6046 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6047 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6048 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6049 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6050 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6051 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6052 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6053 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6054 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6055 * @param PLLN Between 49/50(*) and 432
6056 *
6057 * (*) value not defined in all devices.
6058 * @param PLLQ This parameter can be one of the following values:
6059 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
6060 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
6061 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
6062 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
6063 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
6064 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
6065 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
6066 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
6067 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
6068 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
6069 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
6070 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
6071 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
6072 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
6073 * @param PLLDIVQ This parameter can be one of the following values:
6074 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
6075 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
6076 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
6077 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
6078 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
6079 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
6080 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
6081 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
6082 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
6083 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
6084 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
6085 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
6086 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
6087 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
6088 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
6089 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
6090 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
6091 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
6092 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
6093 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
6094 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
6095 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
6096 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
6097 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
6098 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
6099 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
6100 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
6101 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
6102 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
6103 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
6104 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
6105 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
6106 * @retval None
6107 */
LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ,uint32_t PLLDIVQ)6108 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ,
6109 uint32_t PLLDIVQ)
6110 {
6111 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6112 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6113 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6114 #else
6115 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6116 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6117 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
6118 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
6119 }
6120
6121 #if defined(RCC_PLLSAICFGR_PLLSAIP)
6122 /**
6123 * @brief Configure PLLSAI used for 48Mhz domain clock
6124 * @note PLL Source and PLLM Divider can be written only when PLL,
6125 * PLLI2S and PLLSAI(*) are disabled
6126 * @note PLLN/PLLP can be written only when PLLSAI is disabled
6127 * @note This can be selected for USB, RNG, SDIO
6128 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
6129 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
6130 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n
6131 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
6132 * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
6133 * @param Source This parameter can be one of the following values:
6134 * @arg @ref LL_RCC_PLLSOURCE_HSI
6135 * @arg @ref LL_RCC_PLLSOURCE_HSE
6136 * @param PLLM This parameter can be one of the following values:
6137 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6138 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6139 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6140 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6141 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6142 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6143 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6144 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6145 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6146 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6147 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6148 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6149 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6150 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6151 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6152 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6153 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6154 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6155 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6156 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6157 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6158 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6159 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6160 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6161 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6162 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6163 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6164 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6165 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6166 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6167 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6168 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6169 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6170 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6171 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6172 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6173 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6174 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6175 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6176 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6177 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6178 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6179 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6180 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6181 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6182 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6183 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6184 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6185 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6186 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6187 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6188 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6189 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6190 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6191 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6192 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6193 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6194 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6195 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6196 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6197 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6198 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6199 * @param PLLN Between 50 and 432
6200 * @param PLLP This parameter can be one of the following values:
6201 * @arg @ref LL_RCC_PLLSAIP_DIV_2
6202 * @arg @ref LL_RCC_PLLSAIP_DIV_4
6203 * @arg @ref LL_RCC_PLLSAIP_DIV_6
6204 * @arg @ref LL_RCC_PLLSAIP_DIV_8
6205 * @retval None
6206 */
LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)6207 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
6208 {
6209 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6210 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6211 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6212 #else
6213 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6214 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6215 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
6216 }
6217 #endif /* RCC_PLLSAICFGR_PLLSAIP */
6218
6219 #if defined(LTDC)
6220 /**
6221 * @brief Configure PLLSAI used for LTDC domain clock
6222 * @note PLL Source and PLLM Divider can be written only when PLL,
6223 * PLLI2S and PLLSAI(*) are disabled
6224 * @note PLLN/PLLR can be written only when PLLSAI is disabled
6225 * @note This can be selected for LTDC
6226 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6227 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6228 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6229 * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6230 * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
6231 * @param Source This parameter can be one of the following values:
6232 * @arg @ref LL_RCC_PLLSOURCE_HSI
6233 * @arg @ref LL_RCC_PLLSOURCE_HSE
6234 * @param PLLM This parameter can be one of the following values:
6235 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6236 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6237 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6238 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6239 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6240 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6241 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6242 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6243 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6244 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6245 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6246 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6247 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6248 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6249 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6250 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6251 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6252 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6253 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6254 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6255 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6256 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6257 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6258 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6259 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6260 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6261 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6262 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6263 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6264 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6265 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6266 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6267 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6268 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6269 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6270 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6271 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6272 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6273 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6274 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6275 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6276 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6277 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6278 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6279 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6280 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6281 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6282 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6283 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6284 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6285 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6286 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6287 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6288 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6289 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6290 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6291 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6292 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6293 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6294 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6295 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6296 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6297 * @param PLLN Between 49/50(*) and 432
6298 *
6299 * (*) value not defined in all devices.
6300 * @param PLLR This parameter can be one of the following values:
6301 * @arg @ref LL_RCC_PLLSAIR_DIV_2
6302 * @arg @ref LL_RCC_PLLSAIR_DIV_3
6303 * @arg @ref LL_RCC_PLLSAIR_DIV_4
6304 * @arg @ref LL_RCC_PLLSAIR_DIV_5
6305 * @arg @ref LL_RCC_PLLSAIR_DIV_6
6306 * @arg @ref LL_RCC_PLLSAIR_DIV_7
6307 * @param PLLDIVR This parameter can be one of the following values:
6308 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
6309 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
6310 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
6311 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
6312 * @retval None
6313 */
LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR,uint32_t PLLDIVR)6314 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR,
6315 uint32_t PLLDIVR)
6316 {
6317 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
6318 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
6319 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
6320 }
6321 #endif /* LTDC */
6322
6323 /**
6324 * @brief Get division factor for PLLSAI input clock
6325 * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n
6326 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider
6327 * @retval Returned value can be one of the following values:
6328 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6329 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6330 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6331 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6332 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6333 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6334 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6335 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6336 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6337 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6338 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6339 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6340 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6341 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6342 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6343 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6344 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6345 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6346 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6347 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6348 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6349 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6350 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6351 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6352 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6353 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6354 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6355 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6356 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6357 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6358 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6359 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6360 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6361 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6362 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6363 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6364 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6365 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6366 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6367 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6368 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6369 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6370 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6371 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6372 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6373 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6374 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6375 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6376 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6377 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6378 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6379 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6380 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6381 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6382 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6383 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6384 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6385 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6386 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6387 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6388 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6389 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6390 */
LL_RCC_PLLSAI_GetDivider(void)6391 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
6392 {
6393 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6394 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
6395 #else
6396 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
6397 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6398 }
6399
6400 /**
6401 * @brief Get SAIPLL multiplication factor for VCO
6402 * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
6403 * @retval Between 49/50(*) and 432
6404 *
6405 * (*) value not defined in all devices.
6406 */
LL_RCC_PLLSAI_GetN(void)6407 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
6408 {
6409 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
6410 }
6411
6412 /**
6413 * @brief Get SAIPLL division factor for PLLSAIQ
6414 * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
6415 * @retval Returned value can be one of the following values:
6416 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
6417 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
6418 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
6419 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
6420 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
6421 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
6422 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
6423 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
6424 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
6425 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
6426 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
6427 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
6428 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
6429 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
6430 */
LL_RCC_PLLSAI_GetQ(void)6431 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
6432 {
6433 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
6434 }
6435
6436 #if defined(RCC_PLLSAICFGR_PLLSAIR)
6437 /**
6438 * @brief Get SAIPLL division factor for PLLSAIR
6439 * @note used for PLLSAICLK (SAI clock)
6440 * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
6441 * @retval Returned value can be one of the following values:
6442 * @arg @ref LL_RCC_PLLSAIR_DIV_2
6443 * @arg @ref LL_RCC_PLLSAIR_DIV_3
6444 * @arg @ref LL_RCC_PLLSAIR_DIV_4
6445 * @arg @ref LL_RCC_PLLSAIR_DIV_5
6446 * @arg @ref LL_RCC_PLLSAIR_DIV_6
6447 * @arg @ref LL_RCC_PLLSAIR_DIV_7
6448 */
LL_RCC_PLLSAI_GetR(void)6449 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
6450 {
6451 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
6452 }
6453 #endif /* RCC_PLLSAICFGR_PLLSAIR */
6454
6455 #if defined(RCC_PLLSAICFGR_PLLSAIP)
6456 /**
6457 * @brief Get SAIPLL division factor for PLLSAIP
6458 * @note used for PLL48MCLK (48M domain clock)
6459 * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
6460 * @retval Returned value can be one of the following values:
6461 * @arg @ref LL_RCC_PLLSAIP_DIV_2
6462 * @arg @ref LL_RCC_PLLSAIP_DIV_4
6463 * @arg @ref LL_RCC_PLLSAIP_DIV_6
6464 * @arg @ref LL_RCC_PLLSAIP_DIV_8
6465 */
LL_RCC_PLLSAI_GetP(void)6466 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
6467 {
6468 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
6469 }
6470 #endif /* RCC_PLLSAICFGR_PLLSAIP */
6471
6472 /**
6473 * @brief Get SAIPLL division factor for PLLSAIDIVQ
6474 * @note used PLLSAICLK selected (SAI clock)
6475 * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
6476 * @retval Returned value can be one of the following values:
6477 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
6478 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
6479 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
6480 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
6481 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
6482 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
6483 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
6484 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
6485 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
6486 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
6487 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
6488 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
6489 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
6490 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
6491 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
6492 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
6493 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
6494 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
6495 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
6496 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
6497 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
6498 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
6499 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
6500 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
6501 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
6502 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
6503 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
6504 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
6505 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
6506 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
6507 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
6508 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
6509 */
LL_RCC_PLLSAI_GetDIVQ(void)6510 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
6511 {
6512 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
6513 }
6514
6515 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
6516 /**
6517 * @brief Get SAIPLL division factor for PLLSAIDIVR
6518 * @note used for LTDC domain clock
6519 * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
6520 * @retval Returned value can be one of the following values:
6521 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
6522 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
6523 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
6524 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
6525 */
LL_RCC_PLLSAI_GetDIVR(void)6526 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
6527 {
6528 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
6529 }
6530 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
6531
6532 /**
6533 * @}
6534 */
6535 #endif /* RCC_PLLSAI_SUPPORT */
6536
6537 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
6538 * @{
6539 */
6540
6541 /**
6542 * @brief Clear LSI ready interrupt flag
6543 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
6544 * @retval None
6545 */
LL_RCC_ClearFlag_LSIRDY(void)6546 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
6547 {
6548 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
6549 }
6550
6551 /**
6552 * @brief Clear LSE ready interrupt flag
6553 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
6554 * @retval None
6555 */
LL_RCC_ClearFlag_LSERDY(void)6556 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
6557 {
6558 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
6559 }
6560
6561 /**
6562 * @brief Clear HSI ready interrupt flag
6563 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
6564 * @retval None
6565 */
LL_RCC_ClearFlag_HSIRDY(void)6566 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
6567 {
6568 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
6569 }
6570
6571 /**
6572 * @brief Clear HSE ready interrupt flag
6573 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
6574 * @retval None
6575 */
LL_RCC_ClearFlag_HSERDY(void)6576 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
6577 {
6578 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
6579 }
6580
6581 /**
6582 * @brief Clear PLL ready interrupt flag
6583 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
6584 * @retval None
6585 */
LL_RCC_ClearFlag_PLLRDY(void)6586 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
6587 {
6588 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
6589 }
6590
6591 #if defined(RCC_PLLI2S_SUPPORT)
6592 /**
6593 * @brief Clear PLLI2S ready interrupt flag
6594 * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
6595 * @retval None
6596 */
LL_RCC_ClearFlag_PLLI2SRDY(void)6597 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
6598 {
6599 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
6600 }
6601
6602 #endif /* RCC_PLLI2S_SUPPORT */
6603
6604 #if defined(RCC_PLLSAI_SUPPORT)
6605 /**
6606 * @brief Clear PLLSAI ready interrupt flag
6607 * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
6608 * @retval None
6609 */
LL_RCC_ClearFlag_PLLSAIRDY(void)6610 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
6611 {
6612 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
6613 }
6614
6615 #endif /* RCC_PLLSAI_SUPPORT */
6616
6617 /**
6618 * @brief Clear Clock security system interrupt flag
6619 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
6620 * @retval None
6621 */
LL_RCC_ClearFlag_HSECSS(void)6622 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
6623 {
6624 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
6625 }
6626
6627 /**
6628 * @brief Check if LSI ready interrupt occurred or not
6629 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
6630 * @retval State of bit (1 or 0).
6631 */
LL_RCC_IsActiveFlag_LSIRDY(void)6632 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
6633 {
6634 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
6635 }
6636
6637 /**
6638 * @brief Check if LSE ready interrupt occurred or not
6639 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
6640 * @retval State of bit (1 or 0).
6641 */
LL_RCC_IsActiveFlag_LSERDY(void)6642 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
6643 {
6644 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
6645 }
6646
6647 /**
6648 * @brief Check if HSI ready interrupt occurred or not
6649 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
6650 * @retval State of bit (1 or 0).
6651 */
LL_RCC_IsActiveFlag_HSIRDY(void)6652 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
6653 {
6654 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
6655 }
6656
6657 /**
6658 * @brief Check if HSE ready interrupt occurred or not
6659 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
6660 * @retval State of bit (1 or 0).
6661 */
LL_RCC_IsActiveFlag_HSERDY(void)6662 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
6663 {
6664 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
6665 }
6666
6667 /**
6668 * @brief Check if PLL ready interrupt occurred or not
6669 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
6670 * @retval State of bit (1 or 0).
6671 */
LL_RCC_IsActiveFlag_PLLRDY(void)6672 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
6673 {
6674 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
6675 }
6676
6677 #if defined(RCC_PLLI2S_SUPPORT)
6678 /**
6679 * @brief Check if PLLI2S ready interrupt occurred or not
6680 * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
6681 * @retval State of bit (1 or 0).
6682 */
LL_RCC_IsActiveFlag_PLLI2SRDY(void)6683 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
6684 {
6685 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
6686 }
6687 #endif /* RCC_PLLI2S_SUPPORT */
6688
6689 #if defined(RCC_PLLSAI_SUPPORT)
6690 /**
6691 * @brief Check if PLLSAI ready interrupt occurred or not
6692 * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
6693 * @retval State of bit (1 or 0).
6694 */
LL_RCC_IsActiveFlag_PLLSAIRDY(void)6695 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
6696 {
6697 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
6698 }
6699 #endif /* RCC_PLLSAI_SUPPORT */
6700
6701 /**
6702 * @brief Check if Clock security system interrupt occurred or not
6703 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
6704 * @retval State of bit (1 or 0).
6705 */
LL_RCC_IsActiveFlag_HSECSS(void)6706 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
6707 {
6708 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
6709 }
6710
6711 /**
6712 * @brief Check if RCC flag Independent Watchdog reset is set or not.
6713 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
6714 * @retval State of bit (1 or 0).
6715 */
LL_RCC_IsActiveFlag_IWDGRST(void)6716 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
6717 {
6718 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
6719 }
6720
6721 /**
6722 * @brief Check if RCC flag Low Power reset is set or not.
6723 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
6724 * @retval State of bit (1 or 0).
6725 */
LL_RCC_IsActiveFlag_LPWRRST(void)6726 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
6727 {
6728 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
6729 }
6730
6731 /**
6732 * @brief Check if RCC flag Pin reset is set or not.
6733 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
6734 * @retval State of bit (1 or 0).
6735 */
LL_RCC_IsActiveFlag_PINRST(void)6736 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
6737 {
6738 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
6739 }
6740
6741 /**
6742 * @brief Check if RCC flag POR/PDR reset is set or not.
6743 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
6744 * @retval State of bit (1 or 0).
6745 */
LL_RCC_IsActiveFlag_PORRST(void)6746 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
6747 {
6748 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
6749 }
6750
6751 /**
6752 * @brief Check if RCC flag Software reset is set or not.
6753 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
6754 * @retval State of bit (1 or 0).
6755 */
LL_RCC_IsActiveFlag_SFTRST(void)6756 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
6757 {
6758 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
6759 }
6760
6761 /**
6762 * @brief Check if RCC flag Window Watchdog reset is set or not.
6763 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
6764 * @retval State of bit (1 or 0).
6765 */
LL_RCC_IsActiveFlag_WWDGRST(void)6766 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
6767 {
6768 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
6769 }
6770
6771 #if defined(RCC_CSR_BORRSTF)
6772 /**
6773 * @brief Check if RCC flag BOR reset is set or not.
6774 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
6775 * @retval State of bit (1 or 0).
6776 */
LL_RCC_IsActiveFlag_BORRST(void)6777 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
6778 {
6779 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
6780 }
6781 #endif /* RCC_CSR_BORRSTF */
6782
6783 /**
6784 * @brief Set RMVF bit to clear the reset flags.
6785 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
6786 * @retval None
6787 */
LL_RCC_ClearResetFlags(void)6788 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
6789 {
6790 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
6791 }
6792
6793 /**
6794 * @}
6795 */
6796
6797 /** @defgroup RCC_LL_EF_IT_Management IT Management
6798 * @{
6799 */
6800
6801 /**
6802 * @brief Enable LSI ready interrupt
6803 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
6804 * @retval None
6805 */
LL_RCC_EnableIT_LSIRDY(void)6806 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
6807 {
6808 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6809 }
6810
6811 /**
6812 * @brief Enable LSE ready interrupt
6813 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
6814 * @retval None
6815 */
LL_RCC_EnableIT_LSERDY(void)6816 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
6817 {
6818 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6819 }
6820
6821 /**
6822 * @brief Enable HSI ready interrupt
6823 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
6824 * @retval None
6825 */
LL_RCC_EnableIT_HSIRDY(void)6826 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
6827 {
6828 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6829 }
6830
6831 /**
6832 * @brief Enable HSE ready interrupt
6833 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
6834 * @retval None
6835 */
LL_RCC_EnableIT_HSERDY(void)6836 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
6837 {
6838 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6839 }
6840
6841 /**
6842 * @brief Enable PLL ready interrupt
6843 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
6844 * @retval None
6845 */
LL_RCC_EnableIT_PLLRDY(void)6846 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
6847 {
6848 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6849 }
6850
6851 #if defined(RCC_PLLI2S_SUPPORT)
6852 /**
6853 * @brief Enable PLLI2S ready interrupt
6854 * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
6855 * @retval None
6856 */
LL_RCC_EnableIT_PLLI2SRDY(void)6857 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
6858 {
6859 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6860 }
6861 #endif /* RCC_PLLI2S_SUPPORT */
6862
6863 #if defined(RCC_PLLSAI_SUPPORT)
6864 /**
6865 * @brief Enable PLLSAI ready interrupt
6866 * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
6867 * @retval None
6868 */
LL_RCC_EnableIT_PLLSAIRDY(void)6869 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
6870 {
6871 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6872 }
6873 #endif /* RCC_PLLSAI_SUPPORT */
6874
6875 /**
6876 * @brief Disable LSI ready interrupt
6877 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
6878 * @retval None
6879 */
LL_RCC_DisableIT_LSIRDY(void)6880 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
6881 {
6882 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6883 }
6884
6885 /**
6886 * @brief Disable LSE ready interrupt
6887 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
6888 * @retval None
6889 */
LL_RCC_DisableIT_LSERDY(void)6890 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
6891 {
6892 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6893 }
6894
6895 /**
6896 * @brief Disable HSI ready interrupt
6897 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
6898 * @retval None
6899 */
LL_RCC_DisableIT_HSIRDY(void)6900 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
6901 {
6902 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6903 }
6904
6905 /**
6906 * @brief Disable HSE ready interrupt
6907 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
6908 * @retval None
6909 */
LL_RCC_DisableIT_HSERDY(void)6910 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
6911 {
6912 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6913 }
6914
6915 /**
6916 * @brief Disable PLL ready interrupt
6917 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
6918 * @retval None
6919 */
LL_RCC_DisableIT_PLLRDY(void)6920 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
6921 {
6922 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6923 }
6924
6925 #if defined(RCC_PLLI2S_SUPPORT)
6926 /**
6927 * @brief Disable PLLI2S ready interrupt
6928 * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
6929 * @retval None
6930 */
LL_RCC_DisableIT_PLLI2SRDY(void)6931 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
6932 {
6933 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6934 }
6935
6936 #endif /* RCC_PLLI2S_SUPPORT */
6937
6938 #if defined(RCC_PLLSAI_SUPPORT)
6939 /**
6940 * @brief Disable PLLSAI ready interrupt
6941 * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
6942 * @retval None
6943 */
LL_RCC_DisableIT_PLLSAIRDY(void)6944 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
6945 {
6946 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6947 }
6948 #endif /* RCC_PLLSAI_SUPPORT */
6949
6950 /**
6951 * @brief Checks if LSI ready interrupt source is enabled or disabled.
6952 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
6953 * @retval State of bit (1 or 0).
6954 */
LL_RCC_IsEnabledIT_LSIRDY(void)6955 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
6956 {
6957 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
6958 }
6959
6960 /**
6961 * @brief Checks if LSE ready interrupt source is enabled or disabled.
6962 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
6963 * @retval State of bit (1 or 0).
6964 */
LL_RCC_IsEnabledIT_LSERDY(void)6965 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
6966 {
6967 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
6968 }
6969
6970 /**
6971 * @brief Checks if HSI ready interrupt source is enabled or disabled.
6972 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
6973 * @retval State of bit (1 or 0).
6974 */
LL_RCC_IsEnabledIT_HSIRDY(void)6975 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
6976 {
6977 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
6978 }
6979
6980 /**
6981 * @brief Checks if HSE ready interrupt source is enabled or disabled.
6982 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
6983 * @retval State of bit (1 or 0).
6984 */
LL_RCC_IsEnabledIT_HSERDY(void)6985 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
6986 {
6987 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
6988 }
6989
6990 /**
6991 * @brief Checks if PLL ready interrupt source is enabled or disabled.
6992 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
6993 * @retval State of bit (1 or 0).
6994 */
LL_RCC_IsEnabledIT_PLLRDY(void)6995 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
6996 {
6997 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
6998 }
6999
7000 #if defined(RCC_PLLI2S_SUPPORT)
7001 /**
7002 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
7003 * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
7004 * @retval State of bit (1 or 0).
7005 */
LL_RCC_IsEnabledIT_PLLI2SRDY(void)7006 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
7007 {
7008 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
7009 }
7010
7011 #endif /* RCC_PLLI2S_SUPPORT */
7012
7013 #if defined(RCC_PLLSAI_SUPPORT)
7014 /**
7015 * @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
7016 * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
7017 * @retval State of bit (1 or 0).
7018 */
LL_RCC_IsEnabledIT_PLLSAIRDY(void)7019 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
7020 {
7021 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
7022 }
7023 #endif /* RCC_PLLSAI_SUPPORT */
7024
7025 /**
7026 * @}
7027 */
7028
7029 #if defined(USE_FULL_LL_DRIVER)
7030 /** @defgroup RCC_LL_EF_Init De-initialization function
7031 * @{
7032 */
7033 ErrorStatus LL_RCC_DeInit(void);
7034 /**
7035 * @}
7036 */
7037
7038 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
7039 * @{
7040 */
7041 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
7042 #if defined(FMPI2C1)
7043 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
7044 #endif /* FMPI2C1 */
7045 #if defined(LPTIM1)
7046 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
7047 #endif /* LPTIM1 */
7048 #if defined(SAI1)
7049 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
7050 #endif /* SAI1 */
7051 #if defined(SDIO)
7052 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
7053 #endif /* SDIO */
7054 #if defined(RNG)
7055 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
7056 #endif /* RNG */
7057 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
7058 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
7059 #endif /* USB_OTG_FS || USB_OTG_HS */
7060 #if defined(DFSDM1_Channel0)
7061 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
7062 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
7063 #endif /* DFSDM1_Channel0 */
7064 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
7065 #if defined(CEC)
7066 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
7067 #endif /* CEC */
7068 #if defined(LTDC)
7069 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
7070 #endif /* LTDC */
7071 #if defined(SPDIFRX)
7072 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
7073 #endif /* SPDIFRX */
7074 #if defined(DSI)
7075 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
7076 #endif /* DSI */
7077 /**
7078 * @}
7079 */
7080 #endif /* USE_FULL_LL_DRIVER */
7081
7082 /**
7083 * @}
7084 */
7085
7086 /**
7087 * @}
7088 */
7089
7090 #endif /* defined(RCC) */
7091
7092 /**
7093 * @}
7094 */
7095
7096 #ifdef __cplusplus
7097 }
7098 #endif
7099
7100 #endif /* __STM32F4xx_LL_RCC_H */
7101
7102
