1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32WBxx_LL_RCC_H
22 #define STM32WBxx_LL_RCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32wbxx.h"
30
31 /** @addtogroup STM32WBxx_LL_Driver
32 * @{
33 */
34
35 #if defined(RCC)
36
37 /** @defgroup RCC_LL RCC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
44 * @{
45 */
46
47 #define HSE_CONTROL_UNLOCK_KEY 0xCAFECAFEU
48
49 /**
50 * @}
51 */
52
53 /* Private constants ---------------------------------------------------------*/
54 /* Private macros ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
57 * @{
58 */
59 /**
60 * @}
61 */
62 #endif /*USE_FULL_LL_DRIVER*/
63
64 /* Exported types ------------------------------------------------------------*/
65 #if defined(USE_FULL_LL_DRIVER)
66 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
67 * @{
68 */
69
70 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
71 * @{
72 */
73
74 /**
75 * @brief RCC Clocks Frequency Structure
76 */
77 typedef struct
78 {
79 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
80 uint32_t HCLK1_Frequency; /*!< HCLK1 clock frequency */
81 uint32_t HCLK2_Frequency; /*!< HCLK2 clock frequency */
82 uint32_t HCLK4_Frequency; /*!< HCLK4 clock frequency */
83 uint32_t HCLK5_Frequency; /*!< HCLK5 clock frequency */
84 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
85 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
86 } LL_RCC_ClocksTypeDef;
87
88 /**
89 * @}
90 */
91
92 /**
93 * @}
94 */
95 #endif /* USE_FULL_LL_DRIVER */
96
97 /* Exported constants --------------------------------------------------------*/
98 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
99 * @{
100 */
101
102 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
103 * @brief Defines used to adapt values of different oscillators
104 * @note These values could be modified in the user environment according to
105 * HW set-up.
106 * @{
107 */
108 #if !defined (HSE_VALUE)
109 #define HSE_VALUE 32000000U /*!< Value of the HSE oscillator in Hz */
110 #endif /* HSE_VALUE */
111
112 #if !defined (HSI_VALUE)
113 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
114 #endif /* HSI_VALUE */
115
116 #if !defined (LSE_VALUE)
117 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
118 #endif /* LSE_VALUE */
119
120 #if !defined (LSI_VALUE)
121 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
122 #endif /* LSI_VALUE */
123
124 #if defined(RCC_HSI48_SUPPORT)
125 #if !defined (HSI48_VALUE)
126 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
127 #endif /* HSI48_VALUE */
128 #endif
129
130 /**
131 * @}
132 */
133
134 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
135 * @brief Flags defines which can be used with LL_RCC_WriteReg function
136 * @{
137 */
138 #define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC /*!< LSI1 Ready Interrupt Clear */
139 #define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC /*!< LSI1 Ready Interrupt Clear */
140 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
141 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
142 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
143 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
144 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
145 #if defined(RCC_HSI48_SUPPORT)
146 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
147 #endif
148 #if defined(SAI1)
149 #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
150 #endif
151 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
152 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
153 /**
154 * @}
155 */
156
157 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
158 * @brief Flags defines which can be used with LL_RCC_ReadReg function
159 * @{
160 */
161 #define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */
162 #define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */
163 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
164 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
165 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
166 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
167 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
168 #if defined(RCC_HSI48_SUPPORT)
169 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
170 #endif
171 #if defined(SAI1)
172 #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
173 #endif
174 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
175 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
176 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
177 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
178 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
179 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
180 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
181 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
182 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
183 /**
184 * @}
185 */
186
187 /** @defgroup RCC_LL_EC_IT IT Defines
188 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
189 * @{
190 */
191 #define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE /*!< LSI1 Ready Interrupt Enable */
192 #define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE /*!< LSI Ready Interrupt Enable */
193 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
194 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
195 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
196 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
197 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
198 #if defined(RCC_HSI48_SUPPORT)
199 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
200 #endif
201 #if defined(SAI1)
202 #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */
203 #endif
204 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
205 /**
206 * @}
207 */
208
209 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
210 * @{
211 */
212 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
213 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
214 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
215 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
216 /**
217 * @}
218 */
219
220 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
221 * @{
222 */
223 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
224 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
225 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
226 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
227 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
228 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
229 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
230 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
231 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
232 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
233 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
234 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
235 /**
236 * @}
237 */
238
239
240 /** @defgroup RCC_LL_EC_HSE_CURRENT_CONTROL HSE current control max limits
241 * @{
242 */
243 #define LL_RCC_HSE_CURRENTMAX_0 0x000000000U /*!< HSE current control max limit = 0.18 ma/V*/
244 #define LL_RCC_HSE_CURRENTMAX_1 RCC_HSECR_HSEGMC0 /*!< HSE current control max limit = 0.57 ma/V*/
245 #define LL_RCC_HSE_CURRENTMAX_2 RCC_HSECR_HSEGMC1 /*!< HSE current control max limit = 0.78 ma/V*/
246 #define LL_RCC_HSE_CURRENTMAX_3 (RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.13 ma/V*/
247 #define LL_RCC_HSE_CURRENTMAX_4 RCC_HSECR_HSEGMC2 /*!< HSE current control max limit = 0.61 ma/V*/
248 #define LL_RCC_HSE_CURRENTMAX_5 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.65 ma/V*/
249 #define LL_RCC_HSE_CURRENTMAX_6 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1) /*!< HSE current control max limit = 2.12 ma/V*/
250 #define LL_RCC_HSE_CURRENTMAX_7 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 2.84 ma/V*/
251 /**
252 * @}
253 */
254
255 /** @defgroup RCC_LL_EC_HSE_SENSE_AMPLIFIER HSE sense amplifier threshold
256 * @{
257 */
258 #define LL_RCC_HSEAMPTHRESHOLD_1_2 (0x000000000U) /*!< HSE sense amplifier bias current factor = 1/2*/
259 #define LL_RCC_HSEAMPTHRESHOLD_3_4 RCC_HSECR_HSES /*!< HSE sense amplifier bias current factor = 3/4*/
260 /**
261 * @}
262 */
263
264 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
265 * @{
266 */
267 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
268 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
269 /**
270 * @}
271 */
272
273 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
274 * @{
275 */
276 #define LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */
277 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */
278 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */
279 #define LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL selection as system clock */
280 /**
281 * @}
282 */
283
284 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
285 * @{
286 */
287 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */
288 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */
289 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */
290 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL used as system clock */
291 /**
292 * @}
293 */
294
295 /** @defgroup RCC_LL_EC_RF_CLKSOURCE_STATUS RF system clock switch status
296 * @{
297 */
298 #define LL_RCC_RF_CLKSOURCE_HSI 0x00000000U /*!< HSI used as RF system clock */
299 #define LL_RCC_RF_CLKSOURCE_HSE_DIV2 RCC_EXTCFGR_RFCSS /*!< HSE divided by 2 used as RF system clock */
300 /**
301 * @}
302 */
303
304 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
305 * @{
306 */
307 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
308 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
309 #define LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0 /*!< SYSCLK divided by 3 */
310 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
311 #define LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1 /*!< SYSCLK divided by 5 */
312 #define LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 6 */
313 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
314 #define LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 10 */
315 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
316 #define LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 32 */
317 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
318 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
319 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
320 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
321 /**
322 * @}
323 */
324
325 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
326 * @{
327 */
328 #define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK1 not divided */
329 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2 /*!< HCLK1 divided by 2 */
330 #define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 4 */
331 #define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK1 divided by 8 */
332 #define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 16 */
333 /**
334 * @}
335 */
336
337 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
338 * @{
339 */
340 #define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK1 not divided */
341 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2 /*!< HCLK1 divided by 2 */
342 #define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 4 */
343 #define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1) /*!< HCLK1 divided by 8 */
344 #define LL_RCC_APB2_DIV_16 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 16 */
345 /**
346 * @}
347 */
348
349 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
350 * @{
351 */
352 #define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
353 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
354 /**
355 * @}
356 */
357
358 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
359 * @{
360 */
361 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
362 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
363 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
364 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
365 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE after stabilization selection as MCO1 source */
366 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
367 #define LL_RCC_MCO1SOURCE_LSI1 (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI1 selection as MCO1 source */
368 #define LL_RCC_MCO1SOURCE_LSI2 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI2 selection as MCO1 source */
369 #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3 /*!< LSE selection as MCO1 source */
370 #if defined(RCC_HSI48_SUPPORT)
371 #define LL_RCC_MCO1SOURCE_HSI48 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3) /*!< HSI48 selection as MCO1 source */
372 #endif
373 #define LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< HSE before stabilization selection as MCO1 source */
374 /**
375 * @}
376 */
377
378 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
379 * @{
380 */
381 #define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */
382 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */
383 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */
384 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */
385 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */
386 /**
387 * @}
388 */
389
390 #if defined(RCC_SMPS_SUPPORT)
391 /** @defgroup RCC_LL_EC_SMPS_CLKSOURCE SMPS clock switch
392 * @{
393 */
394 #define LL_RCC_SMPS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as SMPS clock */
395 #define LL_RCC_SMPS_CLKSOURCE_MSI RCC_SMPSCR_SMPSSEL_0 /*!< MSI selection as SMPS clock */
396 #define LL_RCC_SMPS_CLKSOURCE_HSE RCC_SMPSCR_SMPSSEL_1 /*!< HSE selection as SMPS clock */
397 /**
398 * @}
399 */
400
401 /** @defgroup RCC_LL_EC_SMPS_CLKSOURCE_STATUS SMPS clock switch status
402 * @{
403 */
404 #define LL_RCC_SMPS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as SMPS clock */
405 #define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0 /*!< MSI used as SMPS clock */
406 #define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1 /*!< HSE used as SMPS clock */
407 #define LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1) /*!< No Clock used as SMPS clock */
408 /**
409 * @}
410 */
411
412 /** @defgroup RCC_LL_EC_SMPS_DIV SMPS prescaler
413 * @{
414 */
415 #define LL_RCC_SMPS_DIV_0 (0x00000000U) /*!< SMPS clock division 0 */
416 #define LL_RCC_SMPS_DIV_1 RCC_SMPSCR_SMPSDIV_0 /*!< SMPS clock division 1 */
417 #define LL_RCC_SMPS_DIV_2 RCC_SMPSCR_SMPSDIV_1 /*!< SMPS clock division 2 */
418 #define LL_RCC_SMPS_DIV_3 (RCC_SMPSCR_SMPSDIV_0|RCC_SMPSCR_SMPSDIV_1) /*!< SMPS clock division 3 */
419 /**
420 * @}
421 */
422 #endif
423
424 #if defined(USE_FULL_LL_DRIVER)
425 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
426 * @{
427 */
428 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
429 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
430 /**
431 * @}
432 */
433 #endif /* USE_FULL_LL_DRIVER */
434
435 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE USART1 CLKSOURCE
436 * @{
437 */
438 #define LL_RCC_USART1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 selected as USART1 clock */
439 #define LL_RCC_USART1_CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 /*!< SYSCLK selected as USART1 clock */
440 #define LL_RCC_USART1_CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 /*!< HSI selected as USART1 clock */
441 #define LL_RCC_USART1_CLKSOURCE_LSE RCC_CCIPR_USART1SEL /*!< LSE selected as USART1 clock */
442 /**
443 * @}
444 */
445
446 #if defined(LPUART1)
447 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE LPUART1 CLKSOURCE
448 * @{
449 */
450 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as LPUART1 clock */
451 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYCLK selected as LPUART1 clock */
452 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */
453 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock */
454 /**
455 * @}
456 */
457 #endif
458
459 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE
460 * @{
461 */
462 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C1 clock */
463 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK selected as I2C1 clock */
464 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI selected as I2C1 clock */
465 #if defined(I2C3)
466 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C3 clock */
467 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK selected as I2C3 clock */
468 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */
469 #endif
470 /**
471 * @}
472 */
473
474 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE LPTIMx CLKSOURCE
475 * @{
476 */
477 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM1 clock */
478 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI selected as LPTIM1 clock */
479 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI selected as LPTIM1 clock */
480 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16)) /*!< LSE selected as LPTIM1 clock */
481 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM2 clock */
482 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI selected as LPTIM2 clock */
483 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI selected as LPTIM2 clock */
484 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16)) /*!< LSE selected as LPTIM2 clock */
485 /**
486 * @}
487 */
488
489 #if defined(SAI1)
490 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE SAI1 CLKSOURCE
491 * @{
492 */
493 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 0x00000000U /*!< PLLSAI1 selected as SAI1 clock */
494 #define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 /*!< PLL selected as SAI1 clock */
495 #define LL_RCC_SAI1_CLKSOURCE_HSI RCC_CCIPR_SAI1SEL_1 /*!< HSI selected as SAI1 clock */
496 #define LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL /*!< External input selected as SAI1 clock */
497 /**
498 * @}
499 */
500 #endif
501
502 /** @defgroup RCC_LL_EC_CLK48_CLKSOURCE CLK48 CLKSOURCE
503 * @{
504 */
505 #if defined(RCC_HSI48_SUPPORT)
506 #define LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 selected as CLK48 clock */
507 #endif
508 #if defined(SAI1)
509 #define LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 selected as CLK48 clock */
510 #endif
511 #define LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL selected as CLK48 clock */
512 #define LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI selected as CLK48 clock */
513 /**
514 * @}
515 */
516
517 /** @defgroup RCC_LL_EC_USB_CLKSOURCE USB CLKSOURCE
518 * @{
519 */
520 #if defined(RCC_HSI48_SUPPORT)
521 #define LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48 /*!< HSI48 selected as USB clock */
522 #endif
523 #if defined(SAI1)
524 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 selected as USB clock */
525 #endif
526 #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL /*!< PLL selected as USB clock */
527 #define LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI /*!< MSI selected as USB clock */
528 /**
529 * @}
530 */
531
532 /** @defgroup RCC_LL_EC_ADC_CLKSRC ADC CLKSRC
533 * @{
534 */
535 #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock*/
536 #if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
537 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 selected as ADC clock*/
538 #elif defined (STM32WB15xx)
539 #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock */
540 #endif
541 #define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock */
542 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock */
543 /**
544 * @}
545 */
546
547 /** @defgroup RCC_LL_EC_RNG_CLKSRC RNG CLKSRC
548 * @{
549 */
550 #define LL_RCC_RNG_CLKSOURCE_CLK48 0x00000000U /*!< CLK48 divided by 3 selected as RNG Clock */
551 #define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as ADC clock */
552 #define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as ADC clock */
553 /**
554 * @}
555 */
556
557
558 /** @defgroup RCC_LL_EC_USART1 USART1
559 * @{
560 */
561 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 clock source selection bits */
562 /**
563 * @}
564 */
565
566 #if defined(LPUART1)
567 /** @defgroup RCC_LL_EC_LPUART1 LPUART1
568 * @{
569 */
570 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 clock source selection bits */
571 /**
572 * @}
573 */
574 #endif
575
576 /** @defgroup RCC_LL_EC_I2C1 I2C1
577 * @{
578 */
579 #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 clock source selection bits */
580 #define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 clock source selection bits */
581 /**
582 * @}
583 */
584
585 /** @defgroup RCC_LL_EC_LPTIM1 LPTIM1
586 * @{
587 */
588 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 clock source selection bits */
589 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 clock source selection bits */
590 /**
591 * @}
592 */
593
594 #if defined(SAI1)
595 /** @defgroup RCC_LL_EC_SAI1 SAI1
596 * @{
597 */
598 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 clock source selection bits */
599 /**
600 * @}
601 */
602 #endif
603
604 /** @defgroup RCC_LL_EC_CLK48 CLK48
605 * @{
606 */
607 #define LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< CLK48 clock source selection bits */
608 /**
609 * @}
610 */
611
612 /** @defgroup RCC_LL_EC_USB USB
613 * @{
614 */
615 #define LL_RCC_USB_CLKSOURCE LL_RCC_CLK48_CLKSOURCE /*!< USB clock source selection bits */
616 /**
617 * @}
618 */
619
620 /** @defgroup RCC_LL_EC_RNG RNG
621 * @{
622 */
623 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL /*!< RNG clock source selection bits */
624 /**
625 * @}
626 */
627
628 /** @defgroup RCC_LL_EC_ADC ADC
629 * @{
630 */
631 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC clock source selection bits */
632 /**
633 * @}
634 */
635
636
637 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
638 * @{
639 */
640 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
641 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
642 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
643 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
644
645 /**
646 * @}
647 */
648
649 /** @defgroup RCC_LL_EC_RFWKP_CLKSOURCE RF Wakeup clock source selection
650 * @{
651 */
652 #define LL_RCC_RFWKP_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RF Wakeup clock */
653 #define LL_RCC_RFWKP_CLKSOURCE_LSE RCC_CSR_RFWKPSEL_0 /*!< LSE oscillator clock used as RF Wakeup clock */
654 #define LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 RCC_CSR_RFWKPSEL /*!< HSE oscillator clock divided by 1024 used as RF Wakeup clock */
655
656 /**
657 * @}
658 */
659
660
661 /** @defgroup RCC_LL_EC_PLLSOURCE PLL and PLLSAI1 entry clock source
662 * @{
663 */
664 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
665 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */
666 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */
667 #define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */
668 /**
669 * @}
670 */
671
672 /** @defgroup RCC_LL_EC_PLLM_DIV PLL and PLLSAI1 division factor
673 * @{
674 */
675 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL and PLLSAI1 division factor by 1 */
676 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLSAI1 division factor by 2 */
677 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLSAI1 division factor by 3 */
678 #define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL and PLLSAI1 division factor by 4 */
679 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLSAI1 division factor by 5 */
680 #define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL and PLLSAI1 division factor by 6 */
681 #define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL and PLLSAI1 division factor by 7 */
682 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL and PLLSAI1 division factor by 8 */
683 /**
684 * @}
685 */
686
687 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
688 * @{
689 */
690 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
691 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
692 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
693 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
694 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
695 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
696 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
697 /**
698 * @}
699 */
700
701 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
702 * @{
703 */
704 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
705 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
706 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
707 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
708 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
709 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
710 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */
711 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
712 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
713 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
714 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */
715 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
716 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */
717 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */
718 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 16 */
719 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
720 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
721 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
722 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */
723 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
724 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */
725 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */
726 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 24 */
727 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
728 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */
729 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27 */
730 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 28 */
731 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */
732 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 30 */
733 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 31 */
734 #define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 32 */
735 /**
736 * @}
737 */
738
739 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
740 * @{
741 */
742 #define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 2 */
743 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 3 */
744 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
745 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 5 */
746 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */
747 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */
748 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
749 /**
750 * @}
751 */
752
753
754 #if defined(SAI1)
755 /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLQ)
756 * @{
757 */
758 #define LL_RCC_PLLSAI1Q_DIV_2 (RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
759 #define LL_RCC_PLLSAI1Q_DIV_3 (RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 3 */
760 #define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
761 #define LL_RCC_PLLSAI1Q_DIV_5 (RCC_PLLSAI1CFGR_PLLQ_2) /*!< PLLSAI1 division factor for PLLSAI1Q output by 5 */
762 #define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
763 #define LL_RCC_PLLSAI1Q_DIV_7 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 7 */
764 #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
765 /**
766 * @}
767 */
768
769 /** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLP)
770 * @{
771 */
772 #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
773 #define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
774 #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
775 #define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
776 #define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
777 #define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
778 #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */
779 #define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
780 #define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
781 #define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
782 #define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */
783 #define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
784 #define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */
785 #define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */
786 #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 16 */
787 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
788 #define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
789 #define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
790 #define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */
791 #define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
792 #define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */
793 #define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */
794 #define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 24 */
795 #define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
796 #define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */
797 #define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/
798 #define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 28 */
799 #define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */
800 #define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 30 */
801 #define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 31 */
802 #define LL_RCC_PLLSAI1P_DIV_32 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 32 */
803 /**
804 * @}
805 */
806
807 /** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLR)
808 * @{
809 */
810 #define LL_RCC_PLLSAI1R_DIV_2 (RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
811 #define LL_RCC_PLLSAI1R_DIV_3 (RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 3 */
812 #define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
813 #define LL_RCC_PLLSAI1R_DIV_5 (RCC_PLLSAI1CFGR_PLLR_2) /*!< PLLSAI1 division factor for PLLSAI1R output by 5 */
814 #define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
815 #define LL_RCC_PLLSAI1R_DIV_7 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 7 */
816 #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
817 /**
818 * @}
819 */
820 #endif
821
822 /**
823 * @}
824 */
825
826 /* Exported macro ------------------------------------------------------------*/
827 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
828 * @{
829 */
830
831 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
832 * @{
833 */
834
835 /**
836 * @brief Write a value in RCC register
837 * @param __REG__ Register to be written
838 * @param __VALUE__ Value to be written in the register
839 * @retval None
840 */
841 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
842
843 /**
844 * @brief Read a value in RCC register
845 * @param __REG__ Register to be read
846 * @retval Register value
847 */
848 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
849 /**
850 * @}
851 */
852
853 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
854 * @{
855 */
856
857 /**
858 * @brief Helper macro to calculate the PLLRCLK frequency on system domain
859 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
860 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
861 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
862 * @param __PLLM__ This parameter can be one of the following values:
863 * @arg @ref LL_RCC_PLLM_DIV_1
864 * @arg @ref LL_RCC_PLLM_DIV_2
865 * @arg @ref LL_RCC_PLLM_DIV_3
866 * @arg @ref LL_RCC_PLLM_DIV_4
867 * @arg @ref LL_RCC_PLLM_DIV_5
868 * @arg @ref LL_RCC_PLLM_DIV_6
869 * @arg @ref LL_RCC_PLLM_DIV_7
870 * @arg @ref LL_RCC_PLLM_DIV_8
871 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
872 * @param __PLLR__ This parameter can be one of the following values:
873 * @arg @ref LL_RCC_PLLR_DIV_2
874 * @arg @ref LL_RCC_PLLR_DIV_3
875 * @arg @ref LL_RCC_PLLR_DIV_4
876 * @arg @ref LL_RCC_PLLR_DIV_5
877 * @arg @ref LL_RCC_PLLR_DIV_6
878 * @arg @ref LL_RCC_PLLR_DIV_7
879 * @arg @ref LL_RCC_PLLR_DIV_8
880 * @retval PLL clock frequency (in Hz)
881 */
882 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
883 (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U))
884
885 #if defined(SAI1)
886 /**
887 * @brief Helper macro to calculate the PLLPCLK frequency used on SAI domain
888 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
889 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
890 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
891 * @param __PLLM__ This parameter can be one of the following values:
892 * @arg @ref LL_RCC_PLLM_DIV_1
893 * @arg @ref LL_RCC_PLLM_DIV_2
894 * @arg @ref LL_RCC_PLLM_DIV_3
895 * @arg @ref LL_RCC_PLLM_DIV_4
896 * @arg @ref LL_RCC_PLLM_DIV_5
897 * @arg @ref LL_RCC_PLLM_DIV_6
898 * @arg @ref LL_RCC_PLLM_DIV_7
899 * @arg @ref LL_RCC_PLLM_DIV_8
900 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
901 * @param __PLLP__ This parameter can be one of the following values:
902 * @arg @ref LL_RCC_PLLP_DIV_2
903 * @arg @ref LL_RCC_PLLP_DIV_3
904 * @arg @ref LL_RCC_PLLP_DIV_4
905 * @arg @ref LL_RCC_PLLP_DIV_5
906 * @arg @ref LL_RCC_PLLP_DIV_6
907 * @arg @ref LL_RCC_PLLP_DIV_7
908 * @arg @ref LL_RCC_PLLP_DIV_8
909 * @arg @ref LL_RCC_PLLP_DIV_9
910 * @arg @ref LL_RCC_PLLP_DIV_10
911 * @arg @ref LL_RCC_PLLP_DIV_11
912 * @arg @ref LL_RCC_PLLP_DIV_12
913 * @arg @ref LL_RCC_PLLP_DIV_13
914 * @arg @ref LL_RCC_PLLP_DIV_14
915 * @arg @ref LL_RCC_PLLP_DIV_15
916 * @arg @ref LL_RCC_PLLP_DIV_16
917 * @arg @ref LL_RCC_PLLP_DIV_17
918 * @arg @ref LL_RCC_PLLP_DIV_18
919 * @arg @ref LL_RCC_PLLP_DIV_19
920 * @arg @ref LL_RCC_PLLP_DIV_20
921 * @arg @ref LL_RCC_PLLP_DIV_21
922 * @arg @ref LL_RCC_PLLP_DIV_22
923 * @arg @ref LL_RCC_PLLP_DIV_23
924 * @arg @ref LL_RCC_PLLP_DIV_24
925 * @arg @ref LL_RCC_PLLP_DIV_25
926 * @arg @ref LL_RCC_PLLP_DIV_26
927 * @arg @ref LL_RCC_PLLP_DIV_27
928 * @arg @ref LL_RCC_PLLP_DIV_28
929 * @arg @ref LL_RCC_PLLP_DIV_29
930 * @arg @ref LL_RCC_PLLP_DIV_30
931 * @arg @ref LL_RCC_PLLP_DIV_31
932 * @retval PLL clock frequency (in Hz)
933 */
934 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U))/ \
935 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
936 #endif
937
938 /**
939 * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain
940 * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
941 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
942 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
943 * @param __PLLM__ This parameter can be one of the following values:
944 * @arg @ref LL_RCC_PLLM_DIV_1
945 * @arg @ref LL_RCC_PLLM_DIV_2
946 * @arg @ref LL_RCC_PLLM_DIV_3
947 * @arg @ref LL_RCC_PLLM_DIV_4
948 * @arg @ref LL_RCC_PLLM_DIV_5
949 * @arg @ref LL_RCC_PLLM_DIV_6
950 * @arg @ref LL_RCC_PLLM_DIV_7
951 * @arg @ref LL_RCC_PLLM_DIV_8
952 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
953 * @param __PLLP__ This parameter can be one of the following values:
954 * @arg @ref LL_RCC_PLLP_DIV_2
955 * @arg @ref LL_RCC_PLLP_DIV_3
956 * @arg @ref LL_RCC_PLLP_DIV_4
957 * @arg @ref LL_RCC_PLLP_DIV_5
958 * @arg @ref LL_RCC_PLLP_DIV_6
959 * @arg @ref LL_RCC_PLLP_DIV_7
960 * @arg @ref LL_RCC_PLLP_DIV_8
961 * @arg @ref LL_RCC_PLLP_DIV_9
962 * @arg @ref LL_RCC_PLLP_DIV_10
963 * @arg @ref LL_RCC_PLLP_DIV_11
964 * @arg @ref LL_RCC_PLLP_DIV_12
965 * @arg @ref LL_RCC_PLLP_DIV_13
966 * @arg @ref LL_RCC_PLLP_DIV_14
967 * @arg @ref LL_RCC_PLLP_DIV_15
968 * @arg @ref LL_RCC_PLLP_DIV_16
969 * @arg @ref LL_RCC_PLLP_DIV_17
970 * @arg @ref LL_RCC_PLLP_DIV_18
971 * @arg @ref LL_RCC_PLLP_DIV_19
972 * @arg @ref LL_RCC_PLLP_DIV_20
973 * @arg @ref LL_RCC_PLLP_DIV_21
974 * @arg @ref LL_RCC_PLLP_DIV_22
975 * @arg @ref LL_RCC_PLLP_DIV_23
976 * @arg @ref LL_RCC_PLLP_DIV_24
977 * @arg @ref LL_RCC_PLLP_DIV_25
978 * @arg @ref LL_RCC_PLLP_DIV_26
979 * @arg @ref LL_RCC_PLLP_DIV_27
980 * @arg @ref LL_RCC_PLLP_DIV_28
981 * @arg @ref LL_RCC_PLLP_DIV_29
982 * @arg @ref LL_RCC_PLLP_DIV_30
983 * @arg @ref LL_RCC_PLLP_DIV_31
984 * @arg @ref LL_RCC_PLLP_DIV_32
985 * @retval PLL clock frequency (in Hz)
986 */
987 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
988 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
989
990
991 /**
992 * @brief Helper macro to calculate the PLLQCLK frequency used on 48M domain
993 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
994 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
995 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
996 * @param __PLLM__ This parameter can be one of the following values:
997 * @arg @ref LL_RCC_PLLM_DIV_1
998 * @arg @ref LL_RCC_PLLM_DIV_2
999 * @arg @ref LL_RCC_PLLM_DIV_3
1000 * @arg @ref LL_RCC_PLLM_DIV_4
1001 * @arg @ref LL_RCC_PLLM_DIV_5
1002 * @arg @ref LL_RCC_PLLM_DIV_6
1003 * @arg @ref LL_RCC_PLLM_DIV_7
1004 * @arg @ref LL_RCC_PLLM_DIV_8
1005 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
1006 * @param __PLLQ__ This parameter can be one of the following values:
1007 * @arg @ref LL_RCC_PLLQ_DIV_2
1008 * @arg @ref LL_RCC_PLLQ_DIV_3
1009 * @arg @ref LL_RCC_PLLQ_DIV_4
1010 * @arg @ref LL_RCC_PLLQ_DIV_5
1011 * @arg @ref LL_RCC_PLLQ_DIV_6
1012 * @arg @ref LL_RCC_PLLQ_DIV_7
1013 * @arg @ref LL_RCC_PLLQ_DIV_8
1014 * @retval PLL clock frequency (in Hz)
1015 */
1016 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1017 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
1018
1019 #if defined(SAI1)
1020 /**
1021 * @brief Helper macro to calculate the PLLSAI1PCLK frequency used for SAI domain
1022 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1023 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
1024 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1025 * @param __PLLM__ This parameter can be one of the following values:
1026 * @arg @ref LL_RCC_PLLM_DIV_1
1027 * @arg @ref LL_RCC_PLLM_DIV_2
1028 * @arg @ref LL_RCC_PLLM_DIV_3
1029 * @arg @ref LL_RCC_PLLM_DIV_4
1030 * @arg @ref LL_RCC_PLLM_DIV_5
1031 * @arg @ref LL_RCC_PLLM_DIV_6
1032 * @arg @ref LL_RCC_PLLM_DIV_7
1033 * @arg @ref LL_RCC_PLLM_DIV_8
1034 * @param __PLLSAI1N__ Between 6 and 127
1035 * @param __PLLSAI1P__ This parameter can be one of the following values:
1036 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
1037 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
1038 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
1039 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
1040 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
1041 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
1042 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
1043 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
1044 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
1045 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
1046 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
1047 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
1048 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
1049 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
1050 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
1051 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
1052 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
1053 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
1054 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
1055 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
1056 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
1057 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
1058 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
1059 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
1060 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
1061 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
1062 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
1063 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
1064 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
1065 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
1066 * @arg @ref LL_RCC_PLLSAI1P_DIV_32
1067 * @retval PLLSAI1 clock frequency (in Hz)
1068 */
1069 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
1070 ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1071 (((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLP_Pos) + 1U))
1072
1073 /**
1074 * @brief Helper macro to calculate the PLLSAI1QCLK frequency used on 48M domain
1075 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1076 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
1077 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1078 * @param __PLLM__ This parameter can be one of the following values:
1079 * @arg @ref LL_RCC_PLLM_DIV_1
1080 * @arg @ref LL_RCC_PLLM_DIV_2
1081 * @arg @ref LL_RCC_PLLM_DIV_3
1082 * @arg @ref LL_RCC_PLLM_DIV_4
1083 * @arg @ref LL_RCC_PLLM_DIV_5
1084 * @arg @ref LL_RCC_PLLM_DIV_6
1085 * @arg @ref LL_RCC_PLLM_DIV_7
1086 * @arg @ref LL_RCC_PLLM_DIV_8
1087 * @param __PLLSAI1N__ Between 6 and 127
1088 * @param __PLLSAI1Q__ This parameter can be one of the following values:
1089 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
1090 * @arg @ref LL_RCC_PLLSAI1Q_DIV_3
1091 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
1092 * @arg @ref LL_RCC_PLLSAI1Q_DIV_5
1093 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
1094 * @arg @ref LL_RCC_PLLSAI1Q_DIV_7
1095 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
1096 * @retval PLLSAI1 clock frequency (in Hz)
1097 */
1098 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
1099 ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1100 (((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLQ_Pos) + 1U))
1101
1102 /**
1103 * @brief Helper macro to calculate the PLLSAI1RCLK frequency used on ADC domain
1104 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1105 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
1106 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1107 * @param __PLLM__ This parameter can be one of the following values:
1108 * @arg @ref LL_RCC_PLLM_DIV_1
1109 * @arg @ref LL_RCC_PLLM_DIV_2
1110 * @arg @ref LL_RCC_PLLM_DIV_3
1111 * @arg @ref LL_RCC_PLLM_DIV_4
1112 * @arg @ref LL_RCC_PLLM_DIV_5
1113 * @arg @ref LL_RCC_PLLM_DIV_6
1114 * @arg @ref LL_RCC_PLLM_DIV_7
1115 * @arg @ref LL_RCC_PLLM_DIV_8
1116 * @param __PLLSAI1N__ Between 6 and 127
1117 * @param __PLLSAI1R__ This parameter can be one of the following values:
1118 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
1119 * @arg @ref LL_RCC_PLLSAI1R_DIV_3
1120 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
1121 * @arg @ref LL_RCC_PLLSAI1R_DIV_5
1122 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
1123 * @arg @ref LL_RCC_PLLSAI1R_DIV_7
1124 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
1125 * @retval PLLSAI1 clock frequency (in Hz)
1126 */
1127 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
1128 ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1129 (((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLR_Pos) + 1U))
1130 #endif
1131
1132 /**
1133 * @brief Helper macro to calculate the HCLK1 frequency
1134 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1135 * @param __CPU1PRESCALER__ This parameter can be one of the following values:
1136 * @arg @ref LL_RCC_SYSCLK_DIV_1
1137 * @arg @ref LL_RCC_SYSCLK_DIV_2
1138 * @arg @ref LL_RCC_SYSCLK_DIV_3
1139 * @arg @ref LL_RCC_SYSCLK_DIV_4
1140 * @arg @ref LL_RCC_SYSCLK_DIV_5
1141 * @arg @ref LL_RCC_SYSCLK_DIV_6
1142 * @arg @ref LL_RCC_SYSCLK_DIV_8
1143 * @arg @ref LL_RCC_SYSCLK_DIV_10
1144 * @arg @ref LL_RCC_SYSCLK_DIV_16
1145 * @arg @ref LL_RCC_SYSCLK_DIV_32
1146 * @arg @ref LL_RCC_SYSCLK_DIV_64
1147 * @arg @ref LL_RCC_SYSCLK_DIV_128
1148 * @arg @ref LL_RCC_SYSCLK_DIV_256
1149 * @arg @ref LL_RCC_SYSCLK_DIV_512
1150 * @retval HCLK1 clock frequency (in Hz)
1151 */
1152 #define __LL_RCC_CALC_HCLK1_FREQ(__SYSCLKFREQ__,__CPU1PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU1PRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
1153
1154 /**
1155 * @brief Helper macro to calculate the HCLK2 frequency
1156 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1157 * @param __CPU2PRESCALER__ This parameter can be one of the following values:
1158 * @arg @ref LL_RCC_SYSCLK_DIV_1
1159 * @arg @ref LL_RCC_SYSCLK_DIV_2
1160 * @arg @ref LL_RCC_SYSCLK_DIV_3
1161 * @arg @ref LL_RCC_SYSCLK_DIV_4
1162 * @arg @ref LL_RCC_SYSCLK_DIV_5
1163 * @arg @ref LL_RCC_SYSCLK_DIV_6
1164 * @arg @ref LL_RCC_SYSCLK_DIV_8
1165 * @arg @ref LL_RCC_SYSCLK_DIV_10
1166 * @arg @ref LL_RCC_SYSCLK_DIV_16
1167 * @arg @ref LL_RCC_SYSCLK_DIV_32
1168 * @arg @ref LL_RCC_SYSCLK_DIV_64
1169 * @arg @ref LL_RCC_SYSCLK_DIV_128
1170 * @arg @ref LL_RCC_SYSCLK_DIV_256
1171 * @arg @ref LL_RCC_SYSCLK_DIV_512
1172 * @retval HCLK2 clock frequency (in Hz)
1173 */
1174 #define __LL_RCC_CALC_HCLK2_FREQ(__SYSCLKFREQ__, __CPU2PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU2PRESCALER__) & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos])
1175
1176 /**
1177 * @brief Helper macro to calculate the HCLK4 frequency
1178 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1179 * @param __AHB4PRESCALER__ This parameter can be one of the following values:
1180 * @arg @ref LL_RCC_SYSCLK_DIV_1
1181 * @arg @ref LL_RCC_SYSCLK_DIV_2
1182 * @arg @ref LL_RCC_SYSCLK_DIV_3
1183 * @arg @ref LL_RCC_SYSCLK_DIV_4
1184 * @arg @ref LL_RCC_SYSCLK_DIV_5
1185 * @arg @ref LL_RCC_SYSCLK_DIV_6
1186 * @arg @ref LL_RCC_SYSCLK_DIV_8
1187 * @arg @ref LL_RCC_SYSCLK_DIV_10
1188 * @arg @ref LL_RCC_SYSCLK_DIV_16
1189 * @arg @ref LL_RCC_SYSCLK_DIV_32
1190 * @arg @ref LL_RCC_SYSCLK_DIV_64
1191 * @arg @ref LL_RCC_SYSCLK_DIV_128
1192 * @arg @ref LL_RCC_SYSCLK_DIV_256
1193 * @arg @ref LL_RCC_SYSCLK_DIV_512
1194 * @retval HCLK4 clock frequency (in Hz)
1195 */
1196 #define __LL_RCC_CALC_HCLK4_FREQ(__SYSCLKFREQ__, __AHB4PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[(((__AHB4PRESCALER__) >> 4U) & RCC_EXTCFGR_SHDHPRE) >> RCC_EXTCFGR_SHDHPRE_Pos])
1197
1198
1199 /**
1200 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1201 * @param __HCLKFREQ__ HCLK frequency
1202 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1203 * @arg @ref LL_RCC_APB1_DIV_1
1204 * @arg @ref LL_RCC_APB1_DIV_2
1205 * @arg @ref LL_RCC_APB1_DIV_4
1206 * @arg @ref LL_RCC_APB1_DIV_8
1207 * @arg @ref LL_RCC_APB1_DIV_16
1208 * @retval PCLK1 clock frequency (in Hz)
1209 */
1210 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB1PRESCALER__) & RCC_CFGR_PPRE1_Msk) >> RCC_CFGR_PPRE1_Pos)] & 31U))
1211
1212 /**
1213 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1214 * @param __HCLKFREQ__ HCLK frequency
1215 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1216 * @arg @ref LL_RCC_APB2_DIV_1
1217 * @arg @ref LL_RCC_APB2_DIV_2
1218 * @arg @ref LL_RCC_APB2_DIV_4
1219 * @arg @ref LL_RCC_APB2_DIV_8
1220 * @arg @ref LL_RCC_APB2_DIV_16
1221 * @retval PCLK2 clock frequency (in Hz)
1222 */
1223 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB2PRESCALER__) & RCC_CFGR_PPRE2_Msk) >> RCC_CFGR_PPRE2_Pos)] & 31U))
1224
1225 /**
1226 * @brief Helper macro to calculate the MSI frequency (in Hz)
1227 * @note __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange()
1228 * @param __MSIRANGE__ This parameter can be one of the following values:
1229 * @arg @ref LL_RCC_MSIRANGE_0
1230 * @arg @ref LL_RCC_MSIRANGE_1
1231 * @arg @ref LL_RCC_MSIRANGE_2
1232 * @arg @ref LL_RCC_MSIRANGE_3
1233 * @arg @ref LL_RCC_MSIRANGE_4
1234 * @arg @ref LL_RCC_MSIRANGE_5
1235 * @arg @ref LL_RCC_MSIRANGE_6
1236 * @arg @ref LL_RCC_MSIRANGE_7
1237 * @arg @ref LL_RCC_MSIRANGE_8
1238 * @arg @ref LL_RCC_MSIRANGE_9
1239 * @arg @ref LL_RCC_MSIRANGE_10
1240 * @arg @ref LL_RCC_MSIRANGE_11
1241 * @retval MSI clock frequency (in Hz)
1242 */
1243 #define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) MSIRangeTable[((__MSIRANGE__) & RCC_CR_MSIRANGE_Msk) >> RCC_CR_MSIRANGE_Pos]
1244 /**
1245 * @}
1246 */
1247
1248 /**
1249 * @}
1250 */
1251
1252 /* Exported functions --------------------------------------------------------*/
1253 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1254 * @{
1255 */
1256
1257 /** @defgroup RCC_LL_EF_HSE HSE
1258 * @{
1259 */
1260
1261 /**
1262 * @brief Enable HSE sysclk and pll prescaler division by 2
1263 * @rmtoll CR HSEPRE LL_RCC_HSE_EnableDiv2
1264 * @retval None
1265 */
LL_RCC_HSE_EnableDiv2(void)1266 __STATIC_INLINE void LL_RCC_HSE_EnableDiv2(void)
1267 {
1268 SET_BIT(RCC->CR, RCC_CR_HSEPRE);
1269 }
1270
1271 /**
1272 * @brief Disable HSE sysclk and pll prescaler
1273 * @rmtoll CR HSEPRE LL_RCC_HSE_DisableDiv2
1274 * @retval None
1275 */
LL_RCC_HSE_DisableDiv2(void)1276 __STATIC_INLINE void LL_RCC_HSE_DisableDiv2(void)
1277 {
1278 CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE);
1279 }
1280
1281 /**
1282 * @brief Get HSE sysclk and pll prescaler
1283 * @rmtoll CR HSEPRE LL_RCC_HSE_IsEnabledDiv2
1284 * @retval None
1285 */
LL_RCC_HSE_IsEnabledDiv2(void)1286 __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledDiv2(void)
1287 {
1288 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL);
1289 }
1290
1291 /**
1292 * @brief Enable the Clock Security System.
1293 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1294 * @retval None
1295 */
LL_RCC_HSE_EnableCSS(void)1296 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1297 {
1298 SET_BIT(RCC->CR, RCC_CR_CSSON);
1299 }
1300
1301 /**
1302 * @brief Enable HSE crystal oscillator (HSE ON)
1303 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1304 * @retval None
1305 */
LL_RCC_HSE_Enable(void)1306 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1307 {
1308 SET_BIT(RCC->CR, RCC_CR_HSEON);
1309 }
1310
1311 /**
1312 * @brief Disable HSE crystal oscillator (HSE ON)
1313 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1314 * @retval None
1315 */
LL_RCC_HSE_Disable(void)1316 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1317 {
1318 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1319 }
1320
1321 /**
1322 * @brief Check if HSE oscillator Ready
1323 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1324 * @retval State of bit (1 or 0).
1325 */
LL_RCC_HSE_IsReady(void)1326 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1327 {
1328 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
1329 }
1330
1331 /**
1332 * @brief Check if HSE clock control register is locked or not
1333 * @rmtoll HSECR UNLOCKED LL_RCC_HSE_IsClockControlLocked
1334 * @retval State of bit (1 or 0).
1335 */
LL_RCC_HSE_IsClockControlLocked(void)1336 __STATIC_INLINE uint32_t LL_RCC_HSE_IsClockControlLocked(void)
1337 {
1338 return ((READ_BIT(RCC->HSECR, RCC_HSECR_UNLOCKED) != (RCC_HSECR_UNLOCKED)) ? 1UL : 0UL);
1339 }
1340
1341 /**
1342 * @brief Set HSE capacitor tuning
1343 * @rmtoll HSECR HSETUNE LL_RCC_HSE_SetCapacitorTuning
1344 * @param Value Between Min_Data = 0 and Max_Data = 63
1345 * @retval None
1346 */
LL_RCC_HSE_SetCapacitorTuning(uint32_t Value)1347 __STATIC_INLINE void LL_RCC_HSE_SetCapacitorTuning(uint32_t Value)
1348 {
1349 WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
1350 MODIFY_REG(RCC->HSECR, RCC_HSECR_HSETUNE, Value << RCC_HSECR_HSETUNE_Pos);
1351 }
1352
1353 /**
1354 * @brief Get HSE capacitor tuning
1355 * @rmtoll HSECR HSETUNE LL_RCC_HSE_GetCapacitorTuning
1356 * @retval Between Min_Data = 0 and Max_Data = 63
1357 */
LL_RCC_HSE_GetCapacitorTuning(void)1358 __STATIC_INLINE uint32_t LL_RCC_HSE_GetCapacitorTuning(void)
1359 {
1360 return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSETUNE) >> RCC_HSECR_HSETUNE_Pos);
1361 }
1362
1363 /**
1364 * @brief Set HSE current control
1365 * @rmtoll HSECR HSEGMC LL_RCC_HSE_SetCurrentControl
1366 * @param CurrentMax This parameter can be one of the following values:
1367 * @arg @ref LL_RCC_HSE_CURRENTMAX_0
1368 * @arg @ref LL_RCC_HSE_CURRENTMAX_1
1369 * @arg @ref LL_RCC_HSE_CURRENTMAX_2
1370 * @arg @ref LL_RCC_HSE_CURRENTMAX_3
1371 * @arg @ref LL_RCC_HSE_CURRENTMAX_4
1372 * @arg @ref LL_RCC_HSE_CURRENTMAX_5
1373 * @arg @ref LL_RCC_HSE_CURRENTMAX_6
1374 * @arg @ref LL_RCC_HSE_CURRENTMAX_7
1375 */
LL_RCC_HSE_SetCurrentControl(uint32_t CurrentMax)1376 __STATIC_INLINE void LL_RCC_HSE_SetCurrentControl(uint32_t CurrentMax)
1377 {
1378 WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
1379 MODIFY_REG(RCC->HSECR, RCC_HSECR_HSEGMC, CurrentMax);
1380 }
1381
1382 /**
1383 * @brief Get HSE current control
1384 * @rmtoll HSECR HSEGMC LL_RCC_HSE_GetCurrentControl
1385 * @retval Returned value can be one of the following values:
1386 * @arg @ref LL_RCC_HSE_CURRENTMAX_0
1387 * @arg @ref LL_RCC_HSE_CURRENTMAX_1
1388 * @arg @ref LL_RCC_HSE_CURRENTMAX_2
1389 * @arg @ref LL_RCC_HSE_CURRENTMAX_3
1390 * @arg @ref LL_RCC_HSE_CURRENTMAX_4
1391 * @arg @ref LL_RCC_HSE_CURRENTMAX_5
1392 * @arg @ref LL_RCC_HSE_CURRENTMAX_6
1393 * @arg @ref LL_RCC_HSE_CURRENTMAX_7
1394 */
LL_RCC_HSE_GetCurrentControl(void)1395 __STATIC_INLINE uint32_t LL_RCC_HSE_GetCurrentControl(void)
1396 {
1397 return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSEGMC));
1398 }
1399
1400 /**
1401 * @brief Set HSE sense amplifier threshold
1402 * @rmtoll HSECR HSES LL_RCC_HSE_SetSenseAmplifier
1403 * @param SenseAmplifier This parameter can be one of the following values:
1404 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_1_2
1405 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_3_4
1406 */
LL_RCC_HSE_SetSenseAmplifier(uint32_t SenseAmplifier)1407 __STATIC_INLINE void LL_RCC_HSE_SetSenseAmplifier(uint32_t SenseAmplifier)
1408 {
1409 WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
1410 MODIFY_REG(RCC->HSECR, RCC_HSECR_HSES, SenseAmplifier);
1411 }
1412
1413 /**
1414 * @brief Get HSE current control
1415 * @rmtoll HSECR HSES LL_RCC_HSE_GetSenseAmplifier
1416 * @retval Returned value can be one of the following values:
1417 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_1_2
1418 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_3_4
1419 */
LL_RCC_HSE_GetSenseAmplifier(void)1420 __STATIC_INLINE uint32_t LL_RCC_HSE_GetSenseAmplifier(void)
1421 {
1422 return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSES));
1423 }
1424 /**
1425 * @}
1426 */
1427
1428 /** @defgroup RCC_LL_EF_HSI HSI
1429 * @{
1430 */
1431
1432 /**
1433 * @brief Enable HSI even in stop mode
1434 * @note HSI oscillator is forced ON even in Stop mode
1435 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
1436 * @retval None
1437 */
LL_RCC_HSI_EnableInStopMode(void)1438 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1439 {
1440 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1441 }
1442
1443 /**
1444 * @brief Disable HSI in stop mode
1445 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
1446 * @retval None
1447 */
LL_RCC_HSI_DisableInStopMode(void)1448 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1449 {
1450 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1451 }
1452
1453 /**
1454 * @brief Check if HSI in stop mode is ready
1455 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
1456 * @retval State of bit (1 or 0).
1457 */
LL_RCC_HSI_IsEnabledInStopMode(void)1458 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
1459 {
1460 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
1461 }
1462
1463 /**
1464 * @brief Enable HSI oscillator
1465 * @rmtoll CR HSION LL_RCC_HSI_Enable
1466 * @retval None
1467 */
LL_RCC_HSI_Enable(void)1468 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1469 {
1470 SET_BIT(RCC->CR, RCC_CR_HSION);
1471 }
1472
1473 /**
1474 * @brief Disable HSI oscillator
1475 * @rmtoll CR HSION LL_RCC_HSI_Disable
1476 * @retval None
1477 */
LL_RCC_HSI_Disable(void)1478 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1479 {
1480 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1481 }
1482
1483 /**
1484 * @brief Check if HSI clock is ready
1485 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1486 * @retval State of bit (1 or 0).
1487 */
LL_RCC_HSI_IsReady(void)1488 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1489 {
1490 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
1491 }
1492
1493 /**
1494 * @brief Enable HSI Automatic from stop mode
1495 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
1496 * @retval None
1497 */
LL_RCC_HSI_EnableAutoFromStop(void)1498 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
1499 {
1500 SET_BIT(RCC->CR, RCC_CR_HSIASFS);
1501 }
1502
1503 /**
1504 * @brief Disable HSI Automatic from stop mode
1505 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
1506 * @retval None
1507 */
LL_RCC_HSI_DisableAutoFromStop(void)1508 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
1509 {
1510 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
1511 }
1512 /**
1513 * @brief Get HSI Calibration value
1514 * @note When HSITRIM is written, HSICAL is updated with the sum of
1515 * HSITRIM and the factory trim value
1516 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
1517 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1518 */
LL_RCC_HSI_GetCalibration(void)1519 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1520 {
1521 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
1522 }
1523
1524 /**
1525 * @brief Set HSI Calibration trimming
1526 * @note user-programmable trimming value that is added to the HSICAL
1527 * @note Default value is 64, which, when added to the HSICAL value,
1528 * should trim the HSI to 16 MHz +/- 1 %
1529 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
1530 * @param Value Between Min_Data = 0 and Max_Data = 127
1531 * @retval None
1532 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1533 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1534 {
1535 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
1536 }
1537
1538 /**
1539 * @brief Get HSI Calibration trimming
1540 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
1541 * @retval Between Min_Data = 0 and Max_Data = 127
1542 */
LL_RCC_HSI_GetCalibTrimming(void)1543 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1544 {
1545 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
1546 }
1547
1548 /**
1549 * @}
1550 */
1551
1552 #if defined(RCC_HSI48_SUPPORT)
1553 /** @defgroup RCC_LL_EF_HSI48 HSI48
1554 * @{
1555 */
1556
1557 /**
1558 * @brief Enable HSI48
1559 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
1560 * @retval None
1561 */
LL_RCC_HSI48_Enable(void)1562 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1563 {
1564 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1565 }
1566
1567 /**
1568 * @brief Disable HSI48
1569 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
1570 * @retval None
1571 */
LL_RCC_HSI48_Disable(void)1572 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1573 {
1574 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1575 }
1576
1577 /**
1578 * @brief Check if HSI48 oscillator Ready
1579 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
1580 * @retval State of bit (1 or 0).
1581 */
LL_RCC_HSI48_IsReady(void)1582 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1583 {
1584 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
1585 }
1586
1587 /**
1588 * @brief Get HSI48 Calibration value
1589 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1590 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
1591 */
LL_RCC_HSI48_GetCalibration(void)1592 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1593 {
1594 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1595 }
1596
1597 /**
1598 * @}
1599 */
1600 #endif
1601
1602 /** @defgroup RCC_LL_EF_LSE LSE
1603 * @{
1604 */
1605
1606 /**
1607 * @brief Enable Low Speed External (LSE) crystal.
1608 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1609 * @retval None
1610 */
LL_RCC_LSE_Enable(void)1611 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1612 {
1613 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1614 }
1615
1616 /**
1617 * @brief Disable Low Speed External (LSE) crystal.
1618 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1619 * @retval None
1620 */
LL_RCC_LSE_Disable(void)1621 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1622 {
1623 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1624 }
1625
1626 /**
1627 * @brief Check if Low Speed External (LSE) crystal has been enabled or not
1628 * @rmtoll BDCR LSEON LL_RCC_LSE_IsEnabled
1629 * @retval State of bit (1 or 0).
1630 */
LL_RCC_LSE_IsEnabled(void)1631 __STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabled(void)
1632 {
1633 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL);
1634 }
1635
1636 /**
1637 * @brief Enable external clock source (LSE bypass).
1638 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1639 * @retval None
1640 */
LL_RCC_LSE_EnableBypass(void)1641 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1642 {
1643 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1644 }
1645
1646 /**
1647 * @brief Disable external clock source (LSE bypass).
1648 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1649 * @retval None
1650 */
LL_RCC_LSE_DisableBypass(void)1651 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1652 {
1653 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1654 }
1655
1656 /**
1657 * @brief Set LSE oscillator drive capability
1658 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1659 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1660 * @param LSEDrive This parameter can be one of the following values:
1661 * @arg @ref LL_RCC_LSEDRIVE_LOW
1662 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1663 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1664 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1665 * @retval None
1666 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1667 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1668 {
1669 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1670 }
1671
1672 /**
1673 * @brief Get LSE oscillator drive capability
1674 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1675 * @retval Returned value can be one of the following values:
1676 * @arg @ref LL_RCC_LSEDRIVE_LOW
1677 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1678 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1679 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1680 */
LL_RCC_LSE_GetDriveCapability(void)1681 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1682 {
1683 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1684 }
1685
1686 /**
1687 * @brief Enable Clock security system on LSE.
1688 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1689 * @retval None
1690 */
LL_RCC_LSE_EnableCSS(void)1691 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1692 {
1693 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1694 }
1695
1696 /**
1697 * @brief Disable Clock security system on LSE.
1698 * @note Clock security system can be disabled only after a LSE
1699 * failure detection. In that case it MUST be disabled by software.
1700 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1701 * @retval None
1702 */
LL_RCC_LSE_DisableCSS(void)1703 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1704 {
1705 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1706 }
1707
1708 /**
1709 * @brief Check if LSE oscillator Ready
1710 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1711 * @retval State of bit (1 or 0).
1712 */
LL_RCC_LSE_IsReady(void)1713 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1714 {
1715 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
1716 }
1717
1718 /**
1719 * @brief Check if CSS on LSE failure Detection
1720 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
1721 * @retval State of bit (1 or 0).
1722 */
LL_RCC_LSE_IsCSSDetected(void)1723 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1724 {
1725 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
1726 }
1727
1728 /**
1729 * @}
1730 */
1731
1732 /** @defgroup RCC_LL_EF_LSI1 LSI1
1733 * @{
1734 */
1735
1736 /**
1737 * @brief Enable LSI1 Oscillator
1738 * @rmtoll CSR LSI1ON LL_RCC_LSI1_Enable
1739 * @retval None
1740 */
LL_RCC_LSI1_Enable(void)1741 __STATIC_INLINE void LL_RCC_LSI1_Enable(void)
1742 {
1743 SET_BIT(RCC->CSR, RCC_CSR_LSI1ON);
1744 }
1745
1746 /**
1747 * @brief Disable LSI1 Oscillator
1748 * @rmtoll CSR LSI1ON LL_RCC_LSI1_Disable
1749 * @retval None
1750 */
LL_RCC_LSI1_Disable(void)1751 __STATIC_INLINE void LL_RCC_LSI1_Disable(void)
1752 {
1753 CLEAR_BIT(RCC->CSR, RCC_CSR_LSI1ON);
1754 }
1755
1756 /**
1757 * @brief Check if LSI1 is Ready
1758 * @rmtoll CSR LSI1RDY LL_RCC_LSI1_IsReady
1759 * @retval State of bit (1 or 0).
1760 */
LL_RCC_LSI1_IsReady(void)1761 __STATIC_INLINE uint32_t LL_RCC_LSI1_IsReady(void)
1762 {
1763 return ((READ_BIT(RCC->CSR, RCC_CSR_LSI1RDY) == (RCC_CSR_LSI1RDY)) ? 1UL : 0UL);
1764 }
1765
1766 /**
1767 * @}
1768 */
1769
1770 /** @defgroup RCC_LL_EF_LSI2 LSI2
1771 * @{
1772 */
1773
1774 /**
1775 * @brief Enable LSI2 Oscillator
1776 * @rmtoll CSR LSI2ON LL_RCC_LSI2_Enable
1777 * @retval None
1778 */
LL_RCC_LSI2_Enable(void)1779 __STATIC_INLINE void LL_RCC_LSI2_Enable(void)
1780 {
1781 SET_BIT(RCC->CSR, RCC_CSR_LSI2ON);
1782 }
1783
1784 /**
1785 * @brief Disable LSI2 Oscillator
1786 * @rmtoll CSR LSI2ON LL_RCC_LSI2_Disable
1787 * @retval None
1788 */
LL_RCC_LSI2_Disable(void)1789 __STATIC_INLINE void LL_RCC_LSI2_Disable(void)
1790 {
1791 CLEAR_BIT(RCC->CSR, RCC_CSR_LSI2ON);
1792 }
1793
1794 /**
1795 * @brief Check if LSI2 is Ready
1796 * @rmtoll CSR LSI2RDY LL_RCC_LSI2_IsReady
1797 * @retval State of bit (1 or 0).
1798 */
LL_RCC_LSI2_IsReady(void)1799 __STATIC_INLINE uint32_t LL_RCC_LSI2_IsReady(void)
1800 {
1801 return ((READ_BIT(RCC->CSR, RCC_CSR_LSI2RDY) == (RCC_CSR_LSI2RDY)) ? 1UL : 0UL);
1802 }
1803
1804 /**
1805 * @brief Set LSI2 trimming value
1806 * @rmtoll CSR LSI2TRIM LL_RCC_LSI2_SetTrimming
1807 * @param Value Between Min_Data = 0 and Max_Data = 15
1808 * @retval None
1809 */
LL_RCC_LSI2_SetTrimming(uint32_t Value)1810 __STATIC_INLINE void LL_RCC_LSI2_SetTrimming(uint32_t Value)
1811 {
1812 MODIFY_REG(RCC->CSR, RCC_CSR_LSI2TRIM, Value << RCC_CSR_LSI2TRIM_Pos);
1813 }
1814
1815 /**
1816 * @brief Get LSI2 trimming value
1817 * @rmtoll CSR LSI2TRIM LL_RCC_LSI2_GetTrimming
1818 * @retval Between Min_Data = 0 and Max_Data = 12
1819 */
LL_RCC_LSI2_GetTrimming(void)1820 __STATIC_INLINE uint32_t LL_RCC_LSI2_GetTrimming(void)
1821 {
1822 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSI2TRIM) >> RCC_CSR_LSI2TRIM_Pos);
1823 }
1824
1825 /**
1826 * @}
1827 */
1828
1829 /** @defgroup RCC_LL_EF_MSI MSI
1830 * @{
1831 */
1832
1833 /**
1834 * @brief Enable MSI oscillator
1835 * @rmtoll CR MSION LL_RCC_MSI_Enable
1836 * @retval None
1837 */
LL_RCC_MSI_Enable(void)1838 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
1839 {
1840 SET_BIT(RCC->CR, RCC_CR_MSION);
1841 }
1842
1843 /**
1844 * @brief Disable MSI oscillator
1845 * @rmtoll CR MSION LL_RCC_MSI_Disable
1846 * @retval None
1847 */
LL_RCC_MSI_Disable(void)1848 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
1849 {
1850 CLEAR_BIT(RCC->CR, RCC_CR_MSION);
1851 }
1852
1853 /**
1854 * @brief Check if MSI oscillator Ready
1855 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
1856 * @retval State of bit (1 or 0).
1857 */
LL_RCC_MSI_IsReady(void)1858 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
1859 {
1860 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL);
1861 }
1862
1863 /**
1864 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
1865 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
1866 * and ready (LSERDY set by hardware)
1867 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
1868 * ready
1869 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
1870 * @retval None
1871 */
LL_RCC_MSI_EnablePLLMode(void)1872 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
1873 {
1874 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1875 }
1876
1877 /**
1878 * @brief Disable MSI-PLL mode
1879 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
1880 * the Clock Security System on LSE detects a LSE failure
1881 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
1882 * @retval None
1883 */
LL_RCC_MSI_DisablePLLMode(void)1884 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
1885 {
1886 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1887 }
1888
1889
1890 /**
1891 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
1892 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
1893 * @param Range This parameter can be one of the following values:
1894 * @arg @ref LL_RCC_MSIRANGE_0
1895 * @arg @ref LL_RCC_MSIRANGE_1
1896 * @arg @ref LL_RCC_MSIRANGE_2
1897 * @arg @ref LL_RCC_MSIRANGE_3
1898 * @arg @ref LL_RCC_MSIRANGE_4
1899 * @arg @ref LL_RCC_MSIRANGE_5
1900 * @arg @ref LL_RCC_MSIRANGE_6
1901 * @arg @ref LL_RCC_MSIRANGE_7
1902 * @arg @ref LL_RCC_MSIRANGE_8
1903 * @arg @ref LL_RCC_MSIRANGE_9
1904 * @arg @ref LL_RCC_MSIRANGE_10
1905 * @arg @ref LL_RCC_MSIRANGE_11
1906 * @retval None
1907 */
LL_RCC_MSI_SetRange(uint32_t Range)1908 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
1909 {
1910 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
1911 }
1912
1913 /**
1914 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
1915 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
1916 * @retval Returned value can be one of the following values:
1917 * @arg @ref LL_RCC_MSIRANGE_0
1918 * @arg @ref LL_RCC_MSIRANGE_1
1919 * @arg @ref LL_RCC_MSIRANGE_2
1920 * @arg @ref LL_RCC_MSIRANGE_3
1921 * @arg @ref LL_RCC_MSIRANGE_4
1922 * @arg @ref LL_RCC_MSIRANGE_5
1923 * @arg @ref LL_RCC_MSIRANGE_6
1924 * @arg @ref LL_RCC_MSIRANGE_7
1925 * @arg @ref LL_RCC_MSIRANGE_8
1926 * @arg @ref LL_RCC_MSIRANGE_9
1927 * @arg @ref LL_RCC_MSIRANGE_10
1928 * @arg @ref LL_RCC_MSIRANGE_11
1929 */
LL_RCC_MSI_GetRange(void)1930 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
1931 {
1932 uint32_t msiRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE);
1933 if (msiRange > LL_RCC_MSIRANGE_11)
1934 {
1935 msiRange = LL_RCC_MSIRANGE_11;
1936 }
1937 return msiRange;
1938 }
1939
1940
1941 /**
1942 * @brief Get MSI Calibration value
1943 * @note When MSITRIM is written, MSICAL is updated with the sum of
1944 * MSITRIM and the factory trim value
1945 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
1946 * @retval Between Min_Data = 0 and Max_Data = 255
1947 */
LL_RCC_MSI_GetCalibration(void)1948 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
1949 {
1950 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
1951 }
1952
1953 /**
1954 * @brief Set MSI Calibration trimming
1955 * @note user-programmable trimming value that is added to the MSICAL
1956 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
1957 * @param Value Between Min_Data = 0 and Max_Data = 255
1958 * @retval None
1959 */
LL_RCC_MSI_SetCalibTrimming(uint32_t Value)1960 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
1961 {
1962 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
1963 }
1964
1965 /**
1966 * @brief Get MSI Calibration trimming
1967 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
1968 * @retval Between 0 and 255
1969 */
LL_RCC_MSI_GetCalibTrimming(void)1970 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
1971 {
1972 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
1973 }
1974
1975 /**
1976 * @}
1977 */
1978
1979 /** @defgroup RCC_LL_EF_LSCO LSCO
1980 * @{
1981 */
1982
1983 /**
1984 * @brief Enable Low speed clock
1985 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
1986 * @retval None
1987 */
LL_RCC_LSCO_Enable(void)1988 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1989 {
1990 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1991 }
1992
1993 /**
1994 * @brief Disable Low speed clock
1995 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
1996 * @retval None
1997 */
LL_RCC_LSCO_Disable(void)1998 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1999 {
2000 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2001 }
2002
2003 /**
2004 * @brief Configure Low speed clock selection
2005 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
2006 * @param Source This parameter can be one of the following values:
2007 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2008 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2009 * @retval None
2010 */
LL_RCC_LSCO_SetSource(uint32_t Source)2011 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
2012 {
2013 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
2014 }
2015
2016 /**
2017 * @brief Get Low speed clock selection
2018 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
2019 * @retval Returned value can be one of the following values:
2020 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2021 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2022 */
LL_RCC_LSCO_GetSource(void)2023 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
2024 {
2025 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
2026 }
2027
2028 /**
2029 * @}
2030 */
2031
2032 /** @defgroup RCC_LL_EF_System System
2033 * @{
2034 */
2035
2036 /**
2037 * @brief Configure the system clock source
2038 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2039 * @param Source This parameter can be one of the following values:
2040 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
2041 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2042 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2043 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
2044 * @retval None
2045 */
LL_RCC_SetSysClkSource(uint32_t Source)2046 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2047 {
2048 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2049 }
2050
2051 /**
2052 * @brief Get the system clock source
2053 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2054 * @retval Returned value can be one of the following values:
2055 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
2056 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2057 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2058 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
2059 */
LL_RCC_GetSysClkSource(void)2060 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2061 {
2062 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2063 }
2064
2065 /**
2066 * @brief Get the RF clock source
2067 * @rmtoll EXTCFGR RFCSS LL_RCC_GetRFClockSource
2068 * @retval Returned value can be one of the following values:
2069 * @arg @ref LL_RCC_RF_CLKSOURCE_HSI
2070 * @arg @ref LL_RCC_RF_CLKSOURCE_HSE_DIV2
2071 */
LL_RCC_GetRFClockSource(void)2072 __STATIC_INLINE uint32_t LL_RCC_GetRFClockSource(void)
2073 {
2074 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_RFCSS));
2075 }
2076
2077 /**
2078 * @brief Set RF Wakeup Clock Source
2079 * @rmtoll CSR RFWKPSEL LL_RCC_SetRFWKPClockSource
2080 * @param Source This parameter can be one of the following values:
2081 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE
2082 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE
2083 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
2084 * @retval None
2085 */
LL_RCC_SetRFWKPClockSource(uint32_t Source)2086 __STATIC_INLINE void LL_RCC_SetRFWKPClockSource(uint32_t Source)
2087 {
2088 MODIFY_REG(RCC->CSR, RCC_CSR_RFWKPSEL, Source);
2089 }
2090
2091 /**
2092 * @brief Get RF Wakeup Clock Source
2093 * @rmtoll CSR RFWKPSEL LL_RCC_GetRFWKPClockSource
2094 * @retval Returned value can be one of the following values:
2095 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE
2096 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE
2097 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
2098 */
LL_RCC_GetRFWKPClockSource(void)2099 __STATIC_INLINE uint32_t LL_RCC_GetRFWKPClockSource(void)
2100 {
2101 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RFWKPSEL));
2102 }
2103
2104 /**
2105 * @brief Check if Radio System is reset.
2106 * @rmtoll CSR RFRSTS LL_RCC_IsRFUnderReset
2107 * @retval State of bit (1 or 0).
2108 */
LL_RCC_IsRFUnderReset(void)2109 __STATIC_INLINE uint32_t LL_RCC_IsRFUnderReset(void)
2110 {
2111 return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTS) == (RCC_CSR_RFRSTS)) ? 1UL : 0UL);
2112 }
2113
2114 /**
2115 * @brief Set AHB prescaler
2116 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
2117 * @param Prescaler This parameter can be one of the following values:
2118 * @arg @ref LL_RCC_SYSCLK_DIV_1
2119 * @arg @ref LL_RCC_SYSCLK_DIV_2
2120 * @arg @ref LL_RCC_SYSCLK_DIV_3
2121 * @arg @ref LL_RCC_SYSCLK_DIV_4
2122 * @arg @ref LL_RCC_SYSCLK_DIV_5
2123 * @arg @ref LL_RCC_SYSCLK_DIV_6
2124 * @arg @ref LL_RCC_SYSCLK_DIV_8
2125 * @arg @ref LL_RCC_SYSCLK_DIV_10
2126 * @arg @ref LL_RCC_SYSCLK_DIV_16
2127 * @arg @ref LL_RCC_SYSCLK_DIV_32
2128 * @arg @ref LL_RCC_SYSCLK_DIV_64
2129 * @arg @ref LL_RCC_SYSCLK_DIV_128
2130 * @arg @ref LL_RCC_SYSCLK_DIV_256
2131 * @arg @ref LL_RCC_SYSCLK_DIV_512
2132 * @retval None
2133 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2134 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2135 {
2136 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
2137 }
2138
2139 /**
2140 * @brief Set CPU2 AHB prescaler
2141 * @rmtoll EXTCFGR C2HPRE LL_C2_RCC_SetAHBPrescaler
2142 * @param Prescaler This parameter can be one of the following values:
2143 * @arg @ref LL_RCC_SYSCLK_DIV_1
2144 * @arg @ref LL_RCC_SYSCLK_DIV_2
2145 * @arg @ref LL_RCC_SYSCLK_DIV_3
2146 * @arg @ref LL_RCC_SYSCLK_DIV_4
2147 * @arg @ref LL_RCC_SYSCLK_DIV_5
2148 * @arg @ref LL_RCC_SYSCLK_DIV_6
2149 * @arg @ref LL_RCC_SYSCLK_DIV_8
2150 * @arg @ref LL_RCC_SYSCLK_DIV_10
2151 * @arg @ref LL_RCC_SYSCLK_DIV_16
2152 * @arg @ref LL_RCC_SYSCLK_DIV_32
2153 * @arg @ref LL_RCC_SYSCLK_DIV_64
2154 * @arg @ref LL_RCC_SYSCLK_DIV_128
2155 * @arg @ref LL_RCC_SYSCLK_DIV_256
2156 * @arg @ref LL_RCC_SYSCLK_DIV_512
2157 * @retval None
2158 */
LL_C2_RCC_SetAHBPrescaler(uint32_t Prescaler)2159 __STATIC_INLINE void LL_C2_RCC_SetAHBPrescaler(uint32_t Prescaler)
2160 {
2161 MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler);
2162 }
2163
2164 /**
2165 * @brief Set AHB4 prescaler
2166 * @rmtoll EXTCFGR SHDHPRE LL_RCC_SetAHB4Prescaler
2167 * @param Prescaler This parameter can be one of the following values:
2168 * @arg @ref LL_RCC_SYSCLK_DIV_1
2169 * @arg @ref LL_RCC_SYSCLK_DIV_2
2170 * @arg @ref LL_RCC_SYSCLK_DIV_3
2171 * @arg @ref LL_RCC_SYSCLK_DIV_4
2172 * @arg @ref LL_RCC_SYSCLK_DIV_5
2173 * @arg @ref LL_RCC_SYSCLK_DIV_6
2174 * @arg @ref LL_RCC_SYSCLK_DIV_8
2175 * @arg @ref LL_RCC_SYSCLK_DIV_10
2176 * @arg @ref LL_RCC_SYSCLK_DIV_16
2177 * @arg @ref LL_RCC_SYSCLK_DIV_32
2178 * @arg @ref LL_RCC_SYSCLK_DIV_64
2179 * @arg @ref LL_RCC_SYSCLK_DIV_128
2180 * @arg @ref LL_RCC_SYSCLK_DIV_256
2181 * @arg @ref LL_RCC_SYSCLK_DIV_512
2182 * @retval None
2183 */
LL_RCC_SetAHB4Prescaler(uint32_t Prescaler)2184 __STATIC_INLINE void LL_RCC_SetAHB4Prescaler(uint32_t Prescaler)
2185 {
2186 MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4);
2187 }
2188
2189 /**
2190 * @brief Set APB1 prescaler
2191 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
2192 * @param Prescaler This parameter can be one of the following values:
2193 * @arg @ref LL_RCC_APB1_DIV_1
2194 * @arg @ref LL_RCC_APB1_DIV_2
2195 * @arg @ref LL_RCC_APB1_DIV_4
2196 * @arg @ref LL_RCC_APB1_DIV_8
2197 * @arg @ref LL_RCC_APB1_DIV_16
2198 * @retval None
2199 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2200 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2201 {
2202 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
2203 }
2204
2205 /**
2206 * @brief Set APB2 prescaler
2207 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
2208 * @param Prescaler This parameter can be one of the following values:
2209 * @arg @ref LL_RCC_APB2_DIV_1
2210 * @arg @ref LL_RCC_APB2_DIV_2
2211 * @arg @ref LL_RCC_APB2_DIV_4
2212 * @arg @ref LL_RCC_APB2_DIV_8
2213 * @arg @ref LL_RCC_APB2_DIV_16
2214 * @retval None
2215 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2216 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2217 {
2218 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
2219 }
2220
2221 /**
2222 * @brief Get AHB prescaler
2223 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
2224 * @retval Returned value can be one of the following values:
2225 * @arg @ref LL_RCC_SYSCLK_DIV_1
2226 * @arg @ref LL_RCC_SYSCLK_DIV_2
2227 * @arg @ref LL_RCC_SYSCLK_DIV_3
2228 * @arg @ref LL_RCC_SYSCLK_DIV_4
2229 * @arg @ref LL_RCC_SYSCLK_DIV_5
2230 * @arg @ref LL_RCC_SYSCLK_DIV_6
2231 * @arg @ref LL_RCC_SYSCLK_DIV_8
2232 * @arg @ref LL_RCC_SYSCLK_DIV_10
2233 * @arg @ref LL_RCC_SYSCLK_DIV_16
2234 * @arg @ref LL_RCC_SYSCLK_DIV_32
2235 * @arg @ref LL_RCC_SYSCLK_DIV_64
2236 * @arg @ref LL_RCC_SYSCLK_DIV_128
2237 * @arg @ref LL_RCC_SYSCLK_DIV_256
2238 * @arg @ref LL_RCC_SYSCLK_DIV_512
2239 */
LL_RCC_GetAHBPrescaler(void)2240 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2241 {
2242 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
2243 }
2244
2245 /**
2246 * @brief Get C2 AHB prescaler
2247 * @rmtoll EXTCFGR C2HPRE LL_C2_RCC_GetAHBPrescaler
2248 * @retval Returned value can be one of the following values:
2249 * @arg @ref LL_RCC_SYSCLK_DIV_1
2250 * @arg @ref LL_RCC_SYSCLK_DIV_2
2251 * @arg @ref LL_RCC_SYSCLK_DIV_3
2252 * @arg @ref LL_RCC_SYSCLK_DIV_4
2253 * @arg @ref LL_RCC_SYSCLK_DIV_5
2254 * @arg @ref LL_RCC_SYSCLK_DIV_6
2255 * @arg @ref LL_RCC_SYSCLK_DIV_8
2256 * @arg @ref LL_RCC_SYSCLK_DIV_10
2257 * @arg @ref LL_RCC_SYSCLK_DIV_16
2258 * @arg @ref LL_RCC_SYSCLK_DIV_32
2259 * @arg @ref LL_RCC_SYSCLK_DIV_64
2260 * @arg @ref LL_RCC_SYSCLK_DIV_128
2261 * @arg @ref LL_RCC_SYSCLK_DIV_256
2262 * @arg @ref LL_RCC_SYSCLK_DIV_512
2263 */
LL_C2_RCC_GetAHBPrescaler(void)2264 __STATIC_INLINE uint32_t LL_C2_RCC_GetAHBPrescaler(void)
2265 {
2266 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE));
2267 }
2268
2269 /**
2270 * @brief Get AHB4 prescaler
2271 * @rmtoll EXTCFGR SHDHPRE LL_RCC_GetAHB4Prescaler
2272 * @retval Returned value can be one of the following values:
2273 * @arg @ref LL_RCC_SYSCLK_DIV_1
2274 * @arg @ref LL_RCC_SYSCLK_DIV_2
2275 * @arg @ref LL_RCC_SYSCLK_DIV_3
2276 * @arg @ref LL_RCC_SYSCLK_DIV_4
2277 * @arg @ref LL_RCC_SYSCLK_DIV_5
2278 * @arg @ref LL_RCC_SYSCLK_DIV_6
2279 * @arg @ref LL_RCC_SYSCLK_DIV_8
2280 * @arg @ref LL_RCC_SYSCLK_DIV_10
2281 * @arg @ref LL_RCC_SYSCLK_DIV_16
2282 * @arg @ref LL_RCC_SYSCLK_DIV_32
2283 * @arg @ref LL_RCC_SYSCLK_DIV_64
2284 * @arg @ref LL_RCC_SYSCLK_DIV_128
2285 * @arg @ref LL_RCC_SYSCLK_DIV_256
2286 * @arg @ref LL_RCC_SYSCLK_DIV_512
2287 */
LL_RCC_GetAHB4Prescaler(void)2288 __STATIC_INLINE uint32_t LL_RCC_GetAHB4Prescaler(void)
2289 {
2290 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4);
2291 }
2292
2293 /**
2294 * @brief Get APB1 prescaler
2295 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
2296 * @retval Returned value can be one of the following values:
2297 * @arg @ref LL_RCC_APB1_DIV_1
2298 * @arg @ref LL_RCC_APB1_DIV_2
2299 * @arg @ref LL_RCC_APB1_DIV_4
2300 * @arg @ref LL_RCC_APB1_DIV_8
2301 * @arg @ref LL_RCC_APB1_DIV_16
2302 */
LL_RCC_GetAPB1Prescaler(void)2303 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2304 {
2305 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
2306 }
2307
2308 /**
2309 * @brief Get APB2 prescaler
2310 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
2311 * @retval Returned value can be one of the following values:
2312 * @arg @ref LL_RCC_APB2_DIV_1
2313 * @arg @ref LL_RCC_APB2_DIV_2
2314 * @arg @ref LL_RCC_APB2_DIV_4
2315 * @arg @ref LL_RCC_APB2_DIV_8
2316 * @arg @ref LL_RCC_APB2_DIV_16
2317 */
LL_RCC_GetAPB2Prescaler(void)2318 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2319 {
2320 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
2321 }
2322
2323 /**
2324 * @brief Set Clock After Wake-Up From Stop mode
2325 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
2326 * @param Clock This parameter can be one of the following values:
2327 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2328 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2329 * @retval None
2330 */
LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)2331 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
2332 {
2333 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
2334 }
2335
2336 /**
2337 * @brief Get Clock After Wake-Up From Stop mode
2338 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
2339 * @retval Returned value can be one of the following values:
2340 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2341 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2342 */
LL_RCC_GetClkAfterWakeFromStop(void)2343 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
2344 {
2345 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2346 }
2347
2348 /**
2349 * @}
2350 */
2351
2352 #if defined(RCC_SMPS_SUPPORT)
2353 /** @defgroup RCC_LL_EF_SMPS SMPS
2354 * @{
2355 */
2356 /**
2357 * @brief Configure SMPS step down converter clock source
2358 * @rmtoll SMPSCR SMPSSEL LL_RCC_SetSMPSClockSource
2359 * @param SMPSSource This parameter can be one of the following values:
2360 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSI
2361 * @arg @ref LL_RCC_SMPS_CLKSOURCE_MSI (*)
2362 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSE
2363 * @note The system must always be configured so as to get a SMPS Step Down
2364 * converter clock frequency between 2 MHz and 8 MHz
2365 * @note (*) The MSI shall only be selected as SMPS Step Down converter
2366 * clock source when a supported SMPS Step Down converter clock
2367 * MSIRANGE is set (LL_RCC_MSIRANGE_8 to LL_RCC_MSIRANGE_11)
2368 * @retval None
2369 */
LL_RCC_SetSMPSClockSource(uint32_t SMPSSource)2370 __STATIC_INLINE void LL_RCC_SetSMPSClockSource(uint32_t SMPSSource)
2371 {
2372 MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL, SMPSSource);
2373 }
2374
2375 /**
2376 * @brief Get the SMPS clock source selection
2377 * @rmtoll SMPSCR SMPSSEL LL_RCC_GetSMPSClockSelection
2378 * @retval Returned value can be one of the following values:
2379 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSI
2380 * @arg @ref LL_RCC_SMPS_CLKSOURCE_MSI
2381 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSE
2382 */
LL_RCC_GetSMPSClockSelection(void)2383 __STATIC_INLINE uint32_t LL_RCC_GetSMPSClockSelection(void)
2384 {
2385 return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL));
2386 }
2387
2388
2389 /**
2390 * @brief Get the SMPS clock source
2391 * @rmtoll SMPSCR SMPSSWS LL_RCC_GetSMPSClockSource
2392 * @retval Returned value can be one of the following values:
2393 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_HSI
2394 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_MSI
2395 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_HSE
2396 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK
2397 */
LL_RCC_GetSMPSClockSource(void)2398 __STATIC_INLINE uint32_t LL_RCC_GetSMPSClockSource(void)
2399 {
2400 return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSSWS));
2401 }
2402
2403 /**
2404 * @brief Set SMPS prescaler
2405 * @rmtoll SMPSCR SMPSDIV LL_RCC_SetSMPSPrescaler
2406 * @param Prescaler This parameter can be one of the following values:
2407 * @arg @ref LL_RCC_SMPS_DIV_0
2408 * @arg @ref LL_RCC_SMPS_DIV_1
2409 * @arg @ref LL_RCC_SMPS_DIV_2
2410 * @arg @ref LL_RCC_SMPS_DIV_3
2411 * @retval None
2412 */
LL_RCC_SetSMPSPrescaler(uint32_t Prescaler)2413 __STATIC_INLINE void LL_RCC_SetSMPSPrescaler(uint32_t Prescaler)
2414 {
2415 MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV, Prescaler);
2416 }
2417
2418 /**
2419 * @brief Get SMPS prescaler
2420 * @rmtoll SMPSCR SMPSDIV LL_RCC_GetSMPSPrescaler
2421 * @retval Returned value can be one of the following values:
2422 * @arg @ref LL_RCC_SMPS_DIV_0
2423 * @arg @ref LL_RCC_SMPS_DIV_1
2424 * @arg @ref LL_RCC_SMPS_DIV_2
2425 * @arg @ref LL_RCC_SMPS_DIV_3
2426 */
LL_RCC_GetSMPSPrescaler(void)2427 __STATIC_INLINE uint32_t LL_RCC_GetSMPSPrescaler(void)
2428 {
2429 return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV));
2430 }
2431
2432 /**
2433 * @}
2434 */
2435 #endif
2436
2437 /** @defgroup RCC_LL_EF_MCO MCO
2438 * @{
2439 */
2440
2441 /**
2442 * @brief Configure MCOx
2443 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
2444 * CFGR MCOPRE LL_RCC_ConfigMCO
2445 * @param MCOxSource This parameter can be one of the following values:
2446 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
2447 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
2448 * @arg @ref LL_RCC_MCO1SOURCE_MSI
2449 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2450 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2451 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
2452 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
2453 * @arg @ref LL_RCC_MCO1SOURCE_LSI1
2454 * @arg @ref LL_RCC_MCO1SOURCE_LSI2
2455 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2456 * @arg @ref LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB
2457 * @param MCOxPrescaler This parameter can be one of the following values:
2458 * @arg @ref LL_RCC_MCO1_DIV_1
2459 * @arg @ref LL_RCC_MCO1_DIV_2
2460 * @arg @ref LL_RCC_MCO1_DIV_4
2461 * @arg @ref LL_RCC_MCO1_DIV_8
2462 * @arg @ref LL_RCC_MCO1_DIV_16
2463 * @note (*) Value not defined for all devices
2464 * @retval None
2465 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2466 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2467 {
2468 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
2469 }
2470
2471 /**
2472 * @}
2473 */
2474
2475 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2476 * @{
2477 */
2478
2479 /**
2480 * @brief Configure USARTx clock source
2481 * @rmtoll CCIPR USART1SEL LL_RCC_SetUSARTClockSource
2482 * @param USARTxSource This parameter can be one of the following values:
2483 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2484 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2485 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2486 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2487 * @retval None
2488 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)2489 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2490 {
2491 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, USARTxSource);
2492 }
2493
2494 #if defined(LPUART1)
2495 /**
2496 * @brief Configure LPUART1x clock source
2497 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
2498 * @param LPUARTxSource This parameter can be one of the following values:
2499 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2500 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2501 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2502 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2503 * @retval None
2504 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)2505 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
2506 {
2507 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
2508 }
2509 #endif
2510
2511 /**
2512 * @brief Configure I2Cx clock source
2513 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
2514 * @param I2CxSource This parameter can be one of the following values:
2515 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2516 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2517 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2518 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
2519 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
2520 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
2521 * @note (*) Value not defined for all devices
2522 * @retval None
2523 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)2524 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
2525 {
2526 MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U));
2527 }
2528
2529 /**
2530 * @brief Configure LPTIMx clock source
2531 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
2532 * @param LPTIMxSource This parameter can be one of the following values:
2533 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2534 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2535 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2536 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2537 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2538 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2539 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2540 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2541 * @retval None
2542 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)2543 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2544 {
2545 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16));
2546 }
2547
2548 #if defined(SAI1)
2549 /**
2550 * @brief Configure SAIx clock source
2551 * @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource
2552 * @param SAIxSource This parameter can be one of the following values:
2553 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
2554 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
2555 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
2556 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2557 * @retval None
2558 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)2559 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
2560 {
2561 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
2562 }
2563 #endif
2564
2565 /**
2566 * @brief Configure RNG clock source
2567 * @note In case of CLK48 clock selected, it must be configured first thanks to LL_RCC_SetCLK48ClockSource
2568 * @rmtoll CCIPR RNGSEL LL_RCC_SetRNGClockSource
2569 * @param RNGxSource This parameter can be one of the following values:
2570 * @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
2571 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2572 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2573 * @retval None
2574 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)2575 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
2576 {
2577 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
2578 }
2579
2580 /**
2581 * @brief Configure CLK48 clock source
2582 * @rmtoll CCIPR CLK48SEL LL_RCC_SetCLK48ClockSource
2583 * @param CLK48xSource This parameter can be one of the following values:
2584 * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*)
2585 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
2586 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
2587 * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
2588 * @note (*) Value not defined for all devices
2589 * @retval None
2590 */
LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource)2591 __STATIC_INLINE void LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource)
2592 {
2593 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource);
2594 }
2595
2596 #if defined(USB)
2597 /**
2598 * @brief Configure USB clock source
2599 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
2600 * @param USBxSource This parameter can be one of the following values:
2601 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2602 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
2603 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2604 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
2605 * @retval None
2606 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)2607 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
2608 {
2609 LL_RCC_SetCLK48ClockSource(USBxSource);
2610 }
2611 #endif
2612
2613 /**
2614 * @brief Configure RNG clock source
2615 * @note Allow to configure the overall RNG Clock source, if CLK48 is selected as RNG
2616 Clock source, the CLK48xSource has to be configured
2617 * @rmtoll CCIPR RNGSEL LL_RCC_ConfigRNGClockSource
2618 * @rmtoll CCIPR CLK48SEL LL_RCC_ConfigRNGClockSource
2619 * @param RNGxSource This parameter can be one of the following values:
2620 * @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
2621 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2622 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2623 * @param CLK48xSource This parameter can be one of the following values:
2624 * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*)
2625 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
2626 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
2627 * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
2628 * @note (*) Value not defined for all devices
2629 * @retval None
2630 */
LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource,uint32_t CLK48xSource)2631 __STATIC_INLINE void LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource, uint32_t CLK48xSource)
2632 {
2633 if (RNGxSource == LL_RCC_RNG_CLKSOURCE_CLK48)
2634 {
2635 LL_RCC_SetCLK48ClockSource(CLK48xSource);
2636 }
2637 LL_RCC_SetRNGClockSource(RNGxSource);
2638 }
2639
2640
2641 /**
2642 * @brief Configure ADC clock source
2643 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
2644 * @param ADCxSource This parameter can be one of the following values:
2645 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2646 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
2647 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2648 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2649 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*)
2650 * @note (*) Value not defined for all devices
2651 * @retval None
2652 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)2653 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
2654 {
2655 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
2656 }
2657
2658
2659 /**
2660 * @brief Get USARTx clock source
2661 * @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource
2662 * @param USARTx This parameter can be one of the following values:
2663 * @arg @ref LL_RCC_USART1_CLKSOURCE
2664 * @retval Returned value can be one of the following values:
2665 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2666 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2667 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2668 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2669 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)2670 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
2671 {
2672 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx));
2673 }
2674
2675 #if defined(LPUART1)
2676 /**
2677 * @brief Get LPUARTx clock source
2678 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
2679 * @param LPUARTx This parameter can be one of the following values:
2680 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
2681 * @retval Returned value can be one of the following values:
2682 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2683 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2684 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2685 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2686 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)2687 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
2688 {
2689 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
2690 }
2691 #endif
2692
2693 /**
2694 * @brief Get I2Cx clock source
2695 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
2696 * @param I2Cx This parameter can be one of the following values:
2697 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2698 * @arg @ref LL_RCC_I2C3_CLKSOURCE
2699 * @retval Returned value can be one of the following values:
2700 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2701 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2702 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2703 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
2704 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
2705 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
2706 * @note (*) Value not defined for all devices
2707 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)2708 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2709 {
2710 return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) | (I2Cx << 4));
2711 }
2712
2713 /**
2714 * @brief Get LPTIMx clock source
2715 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
2716 * @param LPTIMx This parameter can be one of the following values:
2717 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2718 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2719 * @retval Returned value can be one of the following values:
2720 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2721 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2722 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2723 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2724 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2725 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2726 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2727 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2728 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2729 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2730 {
2731 return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16) | LPTIMx);
2732 }
2733
2734 #if defined(SAI1)
2735 /**
2736 * @brief Get SAIx clock source
2737 * @rmtoll CCIPR SAI1SEL LL_RCC_GetSAIClockSource
2738 * @param SAIx This parameter can be one of the following values:
2739 * @arg @ref LL_RCC_SAI1_CLKSOURCE
2740 * @retval Returned value can be one of the following values:
2741 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
2742 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
2743 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
2744 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2745 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)2746 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
2747 {
2748 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
2749 }
2750 #endif
2751
2752 /**
2753 * @brief Get RNGx clock source
2754 * @rmtoll CCIPR RNGSEL LL_RCC_GetRNGClockSource
2755 * @param RNGx This parameter can be one of the following values:
2756 * @arg @ref LL_RCC_RNG_CLKSOURCE
2757 * @retval Returned value can be one of the following values:
2758 * @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
2759 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2760 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2761 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2762 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2763 {
2764 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
2765 }
2766
2767 /**
2768 * @brief Get CLK48x clock source
2769 * @rmtoll CCIPR CLK48SEL LL_RCC_GetCLK48ClockSource
2770 * @param CLK48x This parameter can be one of the following values:
2771 * @arg @ref LL_RCC_CLK48_CLKSOURCE
2772 * @retval Returned value can be one of the following values:
2773 * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48 (*)
2774 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
2775 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
2776 * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
2777 * @note (*) Value not defined for all devices
2778 */
LL_RCC_GetCLK48ClockSource(uint32_t CLK48x)2779 __STATIC_INLINE uint32_t LL_RCC_GetCLK48ClockSource(uint32_t CLK48x)
2780 {
2781 return (uint32_t)(READ_BIT(RCC->CCIPR, CLK48x));
2782 }
2783
2784 #if defined(USB)
2785 /**
2786 * @brief Get USBx clock source
2787 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
2788 * @param USBx This parameter can be one of the following values:
2789 * @arg @ref LL_RCC_USB_CLKSOURCE
2790 * @retval Returned value can be one of the following values:
2791 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2792 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
2793 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2794 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
2795 */
LL_RCC_GetUSBClockSource(uint32_t USBx)2796 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
2797 {
2798 return LL_RCC_GetCLK48ClockSource(USBx);
2799 }
2800 #endif
2801
2802 /**
2803 * @brief Get ADCx clock source
2804 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
2805 * @param ADCx This parameter can be one of the following values:
2806 * @arg @ref LL_RCC_ADC_CLKSOURCE
2807 * @retval Returned value can be one of the following values:
2808 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2809 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
2810 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2811 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2812 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*)
2813 * @note (*) Value not defined for all devices
2814 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2815 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2816 {
2817 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
2818 }
2819
2820 /**
2821 * @}
2822 */
2823
2824 /** @defgroup RCC_LL_EF_RTC RTC
2825 * @{
2826 */
2827
2828 /**
2829 * @brief Set RTC Clock Source
2830 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2831 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2832 * set). The BDRST bit can be used to reset them.
2833 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2834 * @param Source This parameter can be one of the following values:
2835 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2836 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2837 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2838 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2839 * @retval None
2840 */
LL_RCC_SetRTCClockSource(uint32_t Source)2841 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2842 {
2843 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2844 }
2845
2846 /**
2847 * @brief Get RTC Clock Source
2848 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2849 * @retval Returned value can be one of the following values:
2850 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2851 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2852 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2853 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2854 */
LL_RCC_GetRTCClockSource(void)2855 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2856 {
2857 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2858 }
2859
2860 /**
2861 * @brief Enable RTC
2862 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2863 * @retval None
2864 */
LL_RCC_EnableRTC(void)2865 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2866 {
2867 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2868 }
2869
2870 /**
2871 * @brief Disable RTC
2872 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2873 * @retval None
2874 */
LL_RCC_DisableRTC(void)2875 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2876 {
2877 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2878 }
2879
2880 /**
2881 * @brief Check if RTC has been enabled or not
2882 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2883 * @retval State of bit (1 or 0).
2884 */
LL_RCC_IsEnabledRTC(void)2885 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2886 {
2887 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
2888 }
2889
2890 /**
2891 * @brief Force the Backup domain reset
2892 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2893 * @retval None
2894 */
LL_RCC_ForceBackupDomainReset(void)2895 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2896 {
2897 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2898 }
2899
2900 /**
2901 * @brief Release the Backup domain reset
2902 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2903 * @retval None
2904 */
LL_RCC_ReleaseBackupDomainReset(void)2905 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2906 {
2907 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2908 }
2909
2910 /**
2911 * @}
2912 */
2913
2914
2915 /** @defgroup RCC_LL_EF_PLL PLL
2916 * @{
2917 */
2918
2919 /**
2920 * @brief Enable PLL
2921 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2922 * @retval None
2923 */
LL_RCC_PLL_Enable(void)2924 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2925 {
2926 SET_BIT(RCC->CR, RCC_CR_PLLON);
2927 }
2928
2929 /**
2930 * @brief Disable PLL
2931 * @note Cannot be disabled if the PLL clock is used as the system clock
2932 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2933 * @retval None
2934 */
LL_RCC_PLL_Disable(void)2935 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2936 {
2937 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2938 }
2939
2940 /**
2941 * @brief Check if PLL Ready
2942 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2943 * @retval State of bit (1 or 0).
2944 */
LL_RCC_PLL_IsReady(void)2945 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2946 {
2947 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
2948 }
2949
2950 /**
2951 * @brief Configure PLL used for SYSCLK Domain
2952 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2953 * PLLSAI1 are disabled
2954 * @note PLLN/PLLR can be written only when PLL is disabled
2955 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2956 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
2957 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
2958 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
2959 * @param Source This parameter can be one of the following values:
2960 * @arg @ref LL_RCC_PLLSOURCE_NONE
2961 * @arg @ref LL_RCC_PLLSOURCE_MSI
2962 * @arg @ref LL_RCC_PLLSOURCE_HSI
2963 * @arg @ref LL_RCC_PLLSOURCE_HSE
2964 * @param PLLM This parameter can be one of the following values:
2965 * @arg @ref LL_RCC_PLLM_DIV_1
2966 * @arg @ref LL_RCC_PLLM_DIV_2
2967 * @arg @ref LL_RCC_PLLM_DIV_3
2968 * @arg @ref LL_RCC_PLLM_DIV_4
2969 * @arg @ref LL_RCC_PLLM_DIV_5
2970 * @arg @ref LL_RCC_PLLM_DIV_6
2971 * @arg @ref LL_RCC_PLLM_DIV_7
2972 * @arg @ref LL_RCC_PLLM_DIV_8
2973 * @param PLLN Between 6 and 127
2974 * @param PLLR This parameter can be one of the following values:
2975 * @arg @ref LL_RCC_PLLR_DIV_2
2976 * @arg @ref LL_RCC_PLLR_DIV_4
2977 * @arg @ref LL_RCC_PLLR_DIV_6
2978 * @arg @ref LL_RCC_PLLR_DIV_8
2979 * @retval None
2980 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2981 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2982 {
2983 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
2984 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
2985 }
2986
2987 #if defined(SAI1)
2988 /**
2989 * @brief Configure PLL used for SAI domain clock
2990 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2991 * PLLSAI1 are disabled
2992 * @note PLLN/PLLP can be written only when PLL is disabled
2993 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
2994 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
2995 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
2996 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
2997 * @param Source This parameter can be one of the following values:
2998 * @arg @ref LL_RCC_PLLSOURCE_NONE
2999 * @arg @ref LL_RCC_PLLSOURCE_MSI
3000 * @arg @ref LL_RCC_PLLSOURCE_HSI
3001 * @arg @ref LL_RCC_PLLSOURCE_HSE
3002 * @param PLLM This parameter can be one of the following values:
3003 * @arg @ref LL_RCC_PLLM_DIV_1
3004 * @arg @ref LL_RCC_PLLM_DIV_2
3005 * @arg @ref LL_RCC_PLLM_DIV_3
3006 * @arg @ref LL_RCC_PLLM_DIV_4
3007 * @arg @ref LL_RCC_PLLM_DIV_5
3008 * @arg @ref LL_RCC_PLLM_DIV_6
3009 * @arg @ref LL_RCC_PLLM_DIV_7
3010 * @arg @ref LL_RCC_PLLM_DIV_8
3011 * @param PLLN Between 6 and 127
3012 * @param PLLP This parameter can be one of the following values:
3013 * @arg @ref LL_RCC_PLLP_DIV_2
3014 * @arg @ref LL_RCC_PLLP_DIV_3
3015 * @arg @ref LL_RCC_PLLP_DIV_4
3016 * @arg @ref LL_RCC_PLLP_DIV_5
3017 * @arg @ref LL_RCC_PLLP_DIV_6
3018 * @arg @ref LL_RCC_PLLP_DIV_7
3019 * @arg @ref LL_RCC_PLLP_DIV_8
3020 * @arg @ref LL_RCC_PLLP_DIV_9
3021 * @arg @ref LL_RCC_PLLP_DIV_10
3022 * @arg @ref LL_RCC_PLLP_DIV_11
3023 * @arg @ref LL_RCC_PLLP_DIV_12
3024 * @arg @ref LL_RCC_PLLP_DIV_13
3025 * @arg @ref LL_RCC_PLLP_DIV_14
3026 * @arg @ref LL_RCC_PLLP_DIV_15
3027 * @arg @ref LL_RCC_PLLP_DIV_16
3028 * @arg @ref LL_RCC_PLLP_DIV_17
3029 * @arg @ref LL_RCC_PLLP_DIV_18
3030 * @arg @ref LL_RCC_PLLP_DIV_19
3031 * @arg @ref LL_RCC_PLLP_DIV_20
3032 * @arg @ref LL_RCC_PLLP_DIV_21
3033 * @arg @ref LL_RCC_PLLP_DIV_22
3034 * @arg @ref LL_RCC_PLLP_DIV_23
3035 * @arg @ref LL_RCC_PLLP_DIV_24
3036 * @arg @ref LL_RCC_PLLP_DIV_25
3037 * @arg @ref LL_RCC_PLLP_DIV_26
3038 * @arg @ref LL_RCC_PLLP_DIV_27
3039 * @arg @ref LL_RCC_PLLP_DIV_28
3040 * @arg @ref LL_RCC_PLLP_DIV_29
3041 * @arg @ref LL_RCC_PLLP_DIV_30
3042 * @arg @ref LL_RCC_PLLP_DIV_31
3043 * @arg @ref LL_RCC_PLLP_DIV_32
3044 * @retval None
3045 */
LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3046 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3047 {
3048 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3049 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3050 }
3051 #endif
3052
3053 /**
3054 * @brief Configure PLL used for ADC domain clock
3055 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3056 * PLLSAI1 are disabled
3057 * @note PLLN/PLLP can be written only when PLL is disabled
3058 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
3059 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
3060 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
3061 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_ADC
3062 * @param Source This parameter can be one of the following values:
3063 * @arg @ref LL_RCC_PLLSOURCE_NONE
3064 * @arg @ref LL_RCC_PLLSOURCE_MSI
3065 * @arg @ref LL_RCC_PLLSOURCE_HSI
3066 * @arg @ref LL_RCC_PLLSOURCE_HSE
3067 * @param PLLM This parameter can be one of the following values:
3068 * @arg @ref LL_RCC_PLLM_DIV_1
3069 * @arg @ref LL_RCC_PLLM_DIV_2
3070 * @arg @ref LL_RCC_PLLM_DIV_3
3071 * @arg @ref LL_RCC_PLLM_DIV_4
3072 * @arg @ref LL_RCC_PLLM_DIV_5
3073 * @arg @ref LL_RCC_PLLM_DIV_6
3074 * @arg @ref LL_RCC_PLLM_DIV_7
3075 * @arg @ref LL_RCC_PLLM_DIV_8
3076 * @param PLLN Between 6 and 127
3077 * @param PLLP This parameter can be one of the following values:
3078 * @arg @ref LL_RCC_PLLP_DIV_2
3079 * @arg @ref LL_RCC_PLLP_DIV_3
3080 * @arg @ref LL_RCC_PLLP_DIV_4
3081 * @arg @ref LL_RCC_PLLP_DIV_5
3082 * @arg @ref LL_RCC_PLLP_DIV_6
3083 * @arg @ref LL_RCC_PLLP_DIV_7
3084 * @arg @ref LL_RCC_PLLP_DIV_8
3085 * @arg @ref LL_RCC_PLLP_DIV_9
3086 * @arg @ref LL_RCC_PLLP_DIV_10
3087 * @arg @ref LL_RCC_PLLP_DIV_11
3088 * @arg @ref LL_RCC_PLLP_DIV_12
3089 * @arg @ref LL_RCC_PLLP_DIV_13
3090 * @arg @ref LL_RCC_PLLP_DIV_14
3091 * @arg @ref LL_RCC_PLLP_DIV_15
3092 * @arg @ref LL_RCC_PLLP_DIV_16
3093 * @arg @ref LL_RCC_PLLP_DIV_17
3094 * @arg @ref LL_RCC_PLLP_DIV_18
3095 * @arg @ref LL_RCC_PLLP_DIV_19
3096 * @arg @ref LL_RCC_PLLP_DIV_20
3097 * @arg @ref LL_RCC_PLLP_DIV_21
3098 * @arg @ref LL_RCC_PLLP_DIV_22
3099 * @arg @ref LL_RCC_PLLP_DIV_23
3100 * @arg @ref LL_RCC_PLLP_DIV_24
3101 * @arg @ref LL_RCC_PLLP_DIV_25
3102 * @arg @ref LL_RCC_PLLP_DIV_26
3103 * @arg @ref LL_RCC_PLLP_DIV_27
3104 * @arg @ref LL_RCC_PLLP_DIV_28
3105 * @arg @ref LL_RCC_PLLP_DIV_29
3106 * @arg @ref LL_RCC_PLLP_DIV_30
3107 * @arg @ref LL_RCC_PLLP_DIV_31
3108 * @arg @ref LL_RCC_PLLP_DIV_32
3109 * @retval None
3110 */
LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3111 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3112 {
3113 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3114 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3115 }
3116
3117 /**
3118 * @brief Configure PLL used for 48Mhz domain clock
3119 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3120 * PLLSAI1 are disabled
3121 * @note PLLN/PLLQ can be written only when PLL is disabled
3122 * @note This can be selected for USB, RNG
3123 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
3124 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
3125 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
3126 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
3127 * @param Source This parameter can be one of the following values:
3128 * @arg @ref LL_RCC_PLLSOURCE_NONE
3129 * @arg @ref LL_RCC_PLLSOURCE_MSI
3130 * @arg @ref LL_RCC_PLLSOURCE_HSI
3131 * @arg @ref LL_RCC_PLLSOURCE_HSE
3132 * @param PLLM This parameter can be one of the following values:
3133 * @arg @ref LL_RCC_PLLM_DIV_1
3134 * @arg @ref LL_RCC_PLLM_DIV_2
3135 * @arg @ref LL_RCC_PLLM_DIV_3
3136 * @arg @ref LL_RCC_PLLM_DIV_4
3137 * @arg @ref LL_RCC_PLLM_DIV_5
3138 * @arg @ref LL_RCC_PLLM_DIV_6
3139 * @arg @ref LL_RCC_PLLM_DIV_7
3140 * @arg @ref LL_RCC_PLLM_DIV_8
3141 * @param PLLN Between 6 and 127
3142 * @param PLLQ This parameter can be one of the following values:
3143 * @arg @ref LL_RCC_PLLQ_DIV_2
3144 * @arg @ref LL_RCC_PLLQ_DIV_3
3145 * @arg @ref LL_RCC_PLLQ_DIV_4
3146 * @arg @ref LL_RCC_PLLQ_DIV_5
3147 * @arg @ref LL_RCC_PLLQ_DIV_6
3148 * @arg @ref LL_RCC_PLLQ_DIV_7
3149 * @arg @ref LL_RCC_PLLQ_DIV_8
3150 * @retval None
3151 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3152 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3153 {
3154 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
3155 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
3156 }
3157
3158 /**
3159 * @brief Get Main PLL multiplication factor for VCO
3160 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
3161 * @retval Between 6 and 127
3162 */
LL_RCC_PLL_GetN(void)3163 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
3164 {
3165 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
3166 }
3167
3168 /**
3169 * @brief Get Main PLL division factor for PLLP
3170 * @note used for PLLSAI1CLK (SAI1 clock)
3171 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
3172 * @retval Returned value can be one of the following values:
3173 * @arg @ref LL_RCC_PLLP_DIV_2
3174 * @arg @ref LL_RCC_PLLP_DIV_3
3175 * @arg @ref LL_RCC_PLLP_DIV_4
3176 * @arg @ref LL_RCC_PLLP_DIV_5
3177 * @arg @ref LL_RCC_PLLP_DIV_6
3178 * @arg @ref LL_RCC_PLLP_DIV_7
3179 * @arg @ref LL_RCC_PLLP_DIV_8
3180 * @arg @ref LL_RCC_PLLP_DIV_9
3181 * @arg @ref LL_RCC_PLLP_DIV_10
3182 * @arg @ref LL_RCC_PLLP_DIV_11
3183 * @arg @ref LL_RCC_PLLP_DIV_12
3184 * @arg @ref LL_RCC_PLLP_DIV_13
3185 * @arg @ref LL_RCC_PLLP_DIV_14
3186 * @arg @ref LL_RCC_PLLP_DIV_15
3187 * @arg @ref LL_RCC_PLLP_DIV_16
3188 * @arg @ref LL_RCC_PLLP_DIV_17
3189 * @arg @ref LL_RCC_PLLP_DIV_18
3190 * @arg @ref LL_RCC_PLLP_DIV_19
3191 * @arg @ref LL_RCC_PLLP_DIV_20
3192 * @arg @ref LL_RCC_PLLP_DIV_21
3193 * @arg @ref LL_RCC_PLLP_DIV_22
3194 * @arg @ref LL_RCC_PLLP_DIV_23
3195 * @arg @ref LL_RCC_PLLP_DIV_24
3196 * @arg @ref LL_RCC_PLLP_DIV_25
3197 * @arg @ref LL_RCC_PLLP_DIV_26
3198 * @arg @ref LL_RCC_PLLP_DIV_27
3199 * @arg @ref LL_RCC_PLLP_DIV_28
3200 * @arg @ref LL_RCC_PLLP_DIV_29
3201 * @arg @ref LL_RCC_PLLP_DIV_30
3202 * @arg @ref LL_RCC_PLLP_DIV_31
3203 * @arg @ref LL_RCC_PLLP_DIV_32
3204 */
LL_RCC_PLL_GetP(void)3205 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
3206 {
3207 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
3208 }
3209
3210 /**
3211 * @brief Get Main PLL division factor for PLLQ
3212 * @note used for PLL48MCLK selected for USB, RNG (48 MHz clock)
3213 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
3214 * @retval Returned value can be one of the following values:
3215 * @arg @ref LL_RCC_PLLQ_DIV_2
3216 * @arg @ref LL_RCC_PLLQ_DIV_3
3217 * @arg @ref LL_RCC_PLLQ_DIV_4
3218 * @arg @ref LL_RCC_PLLQ_DIV_5
3219 * @arg @ref LL_RCC_PLLQ_DIV_6
3220 * @arg @ref LL_RCC_PLLQ_DIV_7
3221 * @arg @ref LL_RCC_PLLQ_DIV_8
3222 */
LL_RCC_PLL_GetQ(void)3223 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
3224 {
3225 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
3226 }
3227
3228 /**
3229 * @brief Get Main PLL division factor for PLLR
3230 * @note used for PLLCLK (system clock)
3231 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
3232 * @retval Returned value can be one of the following values:
3233 * @arg @ref LL_RCC_PLLR_DIV_2
3234 * @arg @ref LL_RCC_PLLR_DIV_3
3235 * @arg @ref LL_RCC_PLLR_DIV_4
3236 * @arg @ref LL_RCC_PLLR_DIV_5
3237 * @arg @ref LL_RCC_PLLR_DIV_6
3238 * @arg @ref LL_RCC_PLLR_DIV_7
3239 * @arg @ref LL_RCC_PLLR_DIV_8
3240 */
LL_RCC_PLL_GetR(void)3241 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
3242 {
3243 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
3244 }
3245
3246 /**
3247 * @brief Get Division factor for the main PLL and other PLL
3248 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
3249 * @retval Returned value can be one of the following values:
3250 * @arg @ref LL_RCC_PLLM_DIV_1
3251 * @arg @ref LL_RCC_PLLM_DIV_2
3252 * @arg @ref LL_RCC_PLLM_DIV_3
3253 * @arg @ref LL_RCC_PLLM_DIV_4
3254 * @arg @ref LL_RCC_PLLM_DIV_5
3255 * @arg @ref LL_RCC_PLLM_DIV_6
3256 * @arg @ref LL_RCC_PLLM_DIV_7
3257 * @arg @ref LL_RCC_PLLM_DIV_8
3258 */
LL_RCC_PLL_GetDivider(void)3259 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
3260 {
3261 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
3262 }
3263
3264 #if defined(SAI1)
3265 /**
3266 * @brief Enable PLL output mapped on SAI domain clock
3267 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
3268 * @retval None
3269 */
LL_RCC_PLL_EnableDomain_SAI(void)3270 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
3271 {
3272 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3273 }
3274
3275 /**
3276 * @brief Disable PLL output mapped on SAI domain clock
3277 * @note In order to save power, when the PLLCLK of the PLL is
3278 * not used, should be 0
3279 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
3280 * @retval None
3281 */
LL_RCC_PLL_DisableDomain_SAI(void)3282 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
3283 {
3284 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3285 }
3286 #endif
3287
3288 /**
3289 * @brief Enable PLL output mapped on ADC domain clock
3290 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
3291 * @retval None
3292 */
LL_RCC_PLL_EnableDomain_ADC(void)3293 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
3294 {
3295 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3296 }
3297
3298 /**
3299 * @brief Disable PLL output mapped on ADC domain clock
3300 * @note In order to save power, when the PLLCLK of the PLL is
3301 * not used, should be 0
3302 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
3303 * @retval None
3304 */
LL_RCC_PLL_DisableDomain_ADC(void)3305 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
3306 {
3307 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3308 }
3309
3310
3311 /**
3312 * @brief Enable PLL output mapped on 48MHz domain clock
3313 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
3314 * @retval None
3315 */
LL_RCC_PLL_EnableDomain_48M(void)3316 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
3317 {
3318 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3319 }
3320
3321 /**
3322 * @brief Disable PLL output mapped on 48MHz domain clock
3323 * @note In order to save power, when the PLLCLK of the PLL is
3324 * not used, should be 0
3325 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
3326 * @retval None
3327 */
LL_RCC_PLL_DisableDomain_48M(void)3328 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
3329 {
3330 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3331 }
3332
3333 /**
3334 * @brief Enable PLL output mapped on SYSCLK domain
3335 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
3336 * @retval None
3337 */
LL_RCC_PLL_EnableDomain_SYS(void)3338 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
3339 {
3340 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3341 }
3342
3343 /**
3344 * @brief Disable PLL output mapped on SYSCLK domain
3345 * @note Cannot be disabled if the PLL clock is used as the system clock
3346 * @note In order to save power, when the PLLCLK of the PLL is
3347 * not used, Main PLL should be 0
3348 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
3349 * @retval None
3350 */
LL_RCC_PLL_DisableDomain_SYS(void)3351 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
3352 {
3353 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3354 }
3355
3356 /**
3357 * @}
3358 */
3359
3360 #if defined(SAI1)
3361 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
3362 * @{
3363 */
3364
3365 /**
3366 * @brief Enable PLLSAI1
3367 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
3368 * @retval None
3369 */
LL_RCC_PLLSAI1_Enable(void)3370 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
3371 {
3372 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
3373 }
3374
3375 /**
3376 * @brief Disable PLLSAI1
3377 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
3378 * @retval None
3379 */
LL_RCC_PLLSAI1_Disable(void)3380 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
3381 {
3382 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
3383 }
3384
3385 /**
3386 * @brief Check if PLLSAI1 Ready
3387 * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
3388 * @retval State of bit (1 or 0).
3389 */
LL_RCC_PLLSAI1_IsReady(void)3390 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
3391 {
3392 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) ? 1UL : 0UL);
3393 }
3394
3395 /**
3396 * @brief Configure PLLSAI1 used for 48Mhz domain clock
3397 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3398 * PLLSAI1 are disabled
3399 * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
3400 * @note This can be selected for USB, RNG
3401 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
3402 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
3403 * PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_48M\n
3404 * PLLSAI1CFGR PLLQ LL_RCC_PLLSAI1_ConfigDomain_48M
3405 * @param Source This parameter can be one of the following values:
3406 * @arg @ref LL_RCC_PLLSOURCE_NONE
3407 * @arg @ref LL_RCC_PLLSOURCE_MSI
3408 * @arg @ref LL_RCC_PLLSOURCE_HSI
3409 * @arg @ref LL_RCC_PLLSOURCE_HSE
3410 * @param PLLM This parameter can be one of the following values:
3411 * @arg @ref LL_RCC_PLLM_DIV_1
3412 * @arg @ref LL_RCC_PLLM_DIV_2
3413 * @arg @ref LL_RCC_PLLM_DIV_3
3414 * @arg @ref LL_RCC_PLLM_DIV_4
3415 * @arg @ref LL_RCC_PLLM_DIV_5
3416 * @arg @ref LL_RCC_PLLM_DIV_6
3417 * @arg @ref LL_RCC_PLLM_DIV_7
3418 * @arg @ref LL_RCC_PLLM_DIV_8
3419 * @param PLLN Between 6 and 127
3420 * @param PLLQ This parameter can be one of the following values:
3421 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
3422 * @arg @ref LL_RCC_PLLSAI1Q_DIV_3
3423 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
3424 * @arg @ref LL_RCC_PLLSAI1Q_DIV_5
3425 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
3426 * @arg @ref LL_RCC_PLLSAI1Q_DIV_7
3427 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
3428 * @retval None
3429 */
LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3430 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3431 {
3432 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3433 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLQ, (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLQ);
3434 }
3435
3436 /**
3437 * @brief Configure PLLSAI1 used for SAI domain clock
3438 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3439 * PLLSAI1 are disabled
3440 * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
3441 * @note This can be selected for SAI1 or SAI2 (*)
3442 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3443 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3444 * PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3445 * PLLSAI1CFGR PLLP LL_RCC_PLLSAI1_ConfigDomain_SAI
3446 * @param Source This parameter can be one of the following values:
3447 * @arg @ref LL_RCC_PLLSOURCE_NONE
3448 * @arg @ref LL_RCC_PLLSOURCE_MSI
3449 * @arg @ref LL_RCC_PLLSOURCE_HSI
3450 * @arg @ref LL_RCC_PLLSOURCE_HSE
3451 * @param PLLM This parameter can be one of the following values:
3452 * @arg @ref LL_RCC_PLLM_DIV_1
3453 * @arg @ref LL_RCC_PLLM_DIV_2
3454 * @arg @ref LL_RCC_PLLM_DIV_3
3455 * @arg @ref LL_RCC_PLLM_DIV_4
3456 * @arg @ref LL_RCC_PLLM_DIV_5
3457 * @arg @ref LL_RCC_PLLM_DIV_6
3458 * @arg @ref LL_RCC_PLLM_DIV_7
3459 * @arg @ref LL_RCC_PLLM_DIV_8
3460 * @param PLLN Between 6 and 127
3461 * @param PLLP This parameter can be one of the following values:
3462 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
3463 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
3464 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
3465 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
3466 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
3467 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
3468 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
3469 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
3470 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
3471 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
3472 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
3473 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
3474 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
3475 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
3476 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
3477 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
3478 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
3479 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
3480 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
3481 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
3482 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
3483 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
3484 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
3485 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
3486 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
3487 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
3488 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
3489 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
3490 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
3491 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
3492 * @arg @ref LL_RCC_PLLSAI1P_DIV_32
3493 * @retval None
3494 */
LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3495 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3496 {
3497 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3498 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLP,
3499 (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLP);
3500 }
3501
3502 /**
3503 * @brief Configure PLLSAI1 used for ADC domain clock
3504 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3505 * PLLSAI1 are disabled
3506 * @note PLLN/PLLR can be written only when PLLSAI1 is disabled
3507 * @note This can be selected for ADC
3508 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3509 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3510 * PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3511 * PLLSAI1CFGR PLLR LL_RCC_PLLSAI1_ConfigDomain_ADC
3512 * @param Source This parameter can be one of the following values:
3513 * @arg @ref LL_RCC_PLLSOURCE_NONE
3514 * @arg @ref LL_RCC_PLLSOURCE_MSI
3515 * @arg @ref LL_RCC_PLLSOURCE_HSI
3516 * @arg @ref LL_RCC_PLLSOURCE_HSE
3517 * @param PLLM This parameter can be one of the following values:
3518 * @arg @ref LL_RCC_PLLM_DIV_1
3519 * @arg @ref LL_RCC_PLLM_DIV_2
3520 * @arg @ref LL_RCC_PLLM_DIV_3
3521 * @arg @ref LL_RCC_PLLM_DIV_4
3522 * @arg @ref LL_RCC_PLLM_DIV_5
3523 * @arg @ref LL_RCC_PLLM_DIV_6
3524 * @arg @ref LL_RCC_PLLM_DIV_7
3525 * @arg @ref LL_RCC_PLLM_DIV_8
3526 * @param PLLN Between 6 and 127
3527 * @param PLLR This parameter can be one of the following values:
3528 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
3529 * @arg @ref LL_RCC_PLLSAI1R_DIV_3
3530 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
3531 * @arg @ref LL_RCC_PLLSAI1R_DIV_5
3532 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
3533 * @arg @ref LL_RCC_PLLSAI1R_DIV_7
3534 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
3535 * @retval None
3536 */
LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)3537 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3538 {
3539 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3540 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLR, (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLR);
3541 }
3542
3543 /**
3544 * @brief Get SAI1PLL multiplication factor for VCO
3545 * @rmtoll PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_GetN
3546 * @retval Between 6 and 127
3547 */
LL_RCC_PLLSAI1_GetN(void)3548 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
3549 {
3550 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN) >> RCC_PLLSAI1CFGR_PLLN_Pos);
3551 }
3552
3553 /**
3554 * @brief Get SAI1PLL division factor for PLLSAI1P
3555 * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
3556 * @rmtoll PLLSAI1CFGR PLLP LL_RCC_PLLSAI1_GetP
3557 * @retval Returned value can be one of the following values:
3558 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
3559 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
3560 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
3561 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
3562 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
3563 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
3564 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
3565 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
3566 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
3567 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
3568 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
3569 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
3570 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
3571 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
3572 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
3573 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
3574 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
3575 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
3576 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
3577 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
3578 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
3579 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
3580 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
3581 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
3582 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
3583 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
3584 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
3585 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
3586 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
3587 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
3588 * @arg @ref LL_RCC_PLLSAI1P_DIV_32
3589 */
LL_RCC_PLLSAI1_GetP(void)3590 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
3591 {
3592 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLP));
3593 }
3594
3595 /**
3596 * @brief Get SAI1PLL division factor for PLLQ
3597 * @note used PLL48M2CLK selected for USB, RNG (48 MHz clock)
3598 * @rmtoll PLLSAI1CFGR PLLQ LL_RCC_PLLSAI1_GetQ
3599 * @retval Returned value can be one of the following values:
3600 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
3601 * @arg @ref LL_RCC_PLLSAI1Q_DIV_3
3602 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
3603 * @arg @ref LL_RCC_PLLSAI1Q_DIV_5
3604 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
3605 * @arg @ref LL_RCC_PLLSAI1Q_DIV_7
3606 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
3607 */
LL_RCC_PLLSAI1_GetQ(void)3608 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
3609 {
3610 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQ));
3611 }
3612
3613 /**
3614 * @brief Get PLLSAI1 division factor for PLLSAIR
3615 * @note used for PLLADC1CLK (ADC clock)
3616 * @rmtoll PLLSAI1CFGR PLLR LL_RCC_PLLSAI1_GetR
3617 * @retval Returned value can be one of the following values:
3618 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
3619 * @arg @ref LL_RCC_PLLSAI1R_DIV_3
3620 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
3621 * @arg @ref LL_RCC_PLLSAI1R_DIV_5
3622 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
3623 * @arg @ref LL_RCC_PLLSAI1R_DIV_7
3624 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
3625 */
LL_RCC_PLLSAI1_GetR(void)3626 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
3627 {
3628 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR));
3629 }
3630
3631
3632 /**
3633 * @brief Enable PLLSAI1 output mapped on SAI domain clock
3634 * @rmtoll PLLSAI1CFGR PLLPEN LL_RCC_PLLSAI1_EnableDomain_SAI
3635 * @retval None
3636 */
LL_RCC_PLLSAI1_EnableDomain_SAI(void)3637 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
3638 {
3639 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLPEN);
3640 }
3641
3642 /**
3643 * @brief Disable PLLSAI1 output mapped on SAI domain clock
3644 * @note In order to save power, when of the PLLSAI1 is
3645 * not used, should be 0
3646 * @rmtoll PLLSAI1CFGR PLLPEN LL_RCC_PLLSAI1_DisableDomain_SAI
3647 * @retval None
3648 */
LL_RCC_PLLSAI1_DisableDomain_SAI(void)3649 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
3650 {
3651 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLPEN);
3652 }
3653
3654 /**
3655 * @brief Enable PLLSAI1 output mapped on 48MHz domain clock
3656 * @rmtoll PLLSAI1CFGR PLLQEN LL_RCC_PLLSAI1_EnableDomain_48M
3657 * @retval None
3658 */
LL_RCC_PLLSAI1_EnableDomain_48M(void)3659 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
3660 {
3661 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQEN);
3662 }
3663
3664 /**
3665 * @brief Disable PLLSAI1 output mapped on 48MHz domain clock
3666 * @note In order to save power, when of the PLLSAI1 is
3667 * not used, should be 0
3668 * @rmtoll PLLSAI1CFGR PLLQEN LL_RCC_PLLSAI1_DisableDomain_48M
3669 * @retval None
3670 */
LL_RCC_PLLSAI1_DisableDomain_48M(void)3671 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
3672 {
3673 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQEN);
3674 }
3675
3676 /**
3677 * @brief Enable PLLSAI1 output mapped on ADC domain clock
3678 * @rmtoll PLLSAI1CFGR PLLREN LL_RCC_PLLSAI1_EnableDomain_ADC
3679 * @retval None
3680 */
LL_RCC_PLLSAI1_EnableDomain_ADC(void)3681 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
3682 {
3683 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLREN);
3684 }
3685
3686 /**
3687 * @brief Disable PLLSAI1 output mapped on ADC domain clock
3688 * @note In order to save power, when of the PLLSAI1 is
3689 * not used, Main PLLSAI1 should be 0
3690 * @rmtoll PLLSAI1CFGR PLLREN LL_RCC_PLLSAI1_DisableDomain_ADC
3691 * @retval None
3692 */
LL_RCC_PLLSAI1_DisableDomain_ADC(void)3693 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
3694 {
3695 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLREN);
3696 }
3697 #endif
3698
3699 /**
3700 * @}
3701 */
3702
3703
3704
3705 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
3706 * @{
3707 */
3708
3709 /**
3710 * @brief Clear LSI1 ready interrupt flag
3711 * @rmtoll CICR LSI1RDYC LL_RCC_ClearFlag_LSI1RDY
3712 * @retval None
3713 */
LL_RCC_ClearFlag_LSI1RDY(void)3714 __STATIC_INLINE void LL_RCC_ClearFlag_LSI1RDY(void)
3715 {
3716 SET_BIT(RCC->CICR, RCC_CICR_LSI1RDYC);
3717 }
3718
3719 /**
3720 * @brief Clear LSI2 ready interrupt flag
3721 * @rmtoll CICR LSI2RDYC LL_RCC_ClearFlag_LSI2RDY
3722 * @retval None
3723 */
LL_RCC_ClearFlag_LSI2RDY(void)3724 __STATIC_INLINE void LL_RCC_ClearFlag_LSI2RDY(void)
3725 {
3726 SET_BIT(RCC->CICR, RCC_CICR_LSI2RDYC);
3727 }
3728
3729 /**
3730 * @brief Clear LSE ready interrupt flag
3731 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
3732 * @retval None
3733 */
LL_RCC_ClearFlag_LSERDY(void)3734 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
3735 {
3736 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
3737 }
3738
3739 /**
3740 * @brief Clear MSI ready interrupt flag
3741 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
3742 * @retval None
3743 */
LL_RCC_ClearFlag_MSIRDY(void)3744 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
3745 {
3746 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
3747 }
3748
3749 /**
3750 * @brief Clear HSI ready interrupt flag
3751 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
3752 * @retval None
3753 */
LL_RCC_ClearFlag_HSIRDY(void)3754 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
3755 {
3756 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
3757 }
3758
3759 /**
3760 * @brief Clear HSE ready interrupt flag
3761 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
3762 * @retval None
3763 */
LL_RCC_ClearFlag_HSERDY(void)3764 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
3765 {
3766 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
3767 }
3768
3769 /**
3770 * @brief Configure PLL clock source
3771 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
3772 * @param PLLSource This parameter can be one of the following values:
3773 * @arg @ref LL_RCC_PLLSOURCE_MSI
3774 * @arg @ref LL_RCC_PLLSOURCE_HSI
3775 * @arg @ref LL_RCC_PLLSOURCE_HSE
3776 * @retval None
3777 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)3778 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
3779 {
3780 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
3781 }
3782
3783 /**
3784 * @brief Get the oscillator used as PLL clock source.
3785 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
3786 * @retval Returned value can be one of the following values:
3787 * @arg @ref LL_RCC_PLLSOURCE_NONE
3788 * @arg @ref LL_RCC_PLLSOURCE_MSI
3789 * @arg @ref LL_RCC_PLLSOURCE_HSI
3790 * @arg @ref LL_RCC_PLLSOURCE_HSE
3791 */
LL_RCC_PLL_GetMainSource(void)3792 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3793 {
3794 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3795 }
3796
3797 /**
3798 * @brief Clear PLL ready interrupt flag
3799 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
3800 * @retval None
3801 */
LL_RCC_ClearFlag_PLLRDY(void)3802 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
3803 {
3804 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
3805 }
3806
3807 #if defined(RCC_HSI48_SUPPORT)
3808 /**
3809 * @brief Clear HSI48 ready interrupt flag
3810 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
3811 * @retval None
3812 */
LL_RCC_ClearFlag_HSI48RDY(void)3813 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
3814 {
3815 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
3816 }
3817 #endif
3818
3819 #if defined(SAI1)
3820 /**
3821 * @brief Clear PLLSAI1 ready interrupt flag
3822 * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
3823 * @retval None
3824 */
LL_RCC_ClearFlag_PLLSAI1RDY(void)3825 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
3826 {
3827 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
3828 }
3829 #endif
3830
3831 /**
3832 * @brief Clear Clock security system interrupt flag
3833 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
3834 * @retval None
3835 */
LL_RCC_ClearFlag_HSECSS(void)3836 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
3837 {
3838 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
3839 }
3840
3841 /**
3842 * @brief Clear LSE Clock security system interrupt flag
3843 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
3844 * @retval None
3845 */
LL_RCC_ClearFlag_LSECSS(void)3846 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
3847 {
3848 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
3849 }
3850
3851 /**
3852 * @brief Check if LSI1 ready interrupt occurred or not
3853 * @rmtoll CIFR LSI1RDYF LL_RCC_IsActiveFlag_LSI1RDY
3854 * @retval State of bit (1 or 0).
3855 */
LL_RCC_IsActiveFlag_LSI1RDY(void)3856 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI1RDY(void)
3857 {
3858 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI1RDYF) == (RCC_CIFR_LSI1RDYF)) ? 1UL : 0UL);
3859 }
3860
3861 /**
3862 * @brief Check if LSI2 ready interrupt occurred or not
3863 * @rmtoll CIFR LSI2RDYF LL_RCC_IsActiveFlag_LSI2RDY
3864 * @retval State of bit (1 or 0).
3865 */
LL_RCC_IsActiveFlag_LSI2RDY(void)3866 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI2RDY(void)
3867 {
3868 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI2RDYF) == (RCC_CIFR_LSI2RDYF)) ? 1UL : 0UL);
3869 }
3870
3871 /**
3872 * @brief Check if LSE ready interrupt occurred or not
3873 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
3874 * @retval State of bit (1 or 0).
3875 */
LL_RCC_IsActiveFlag_LSERDY(void)3876 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
3877 {
3878 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
3879 }
3880
3881 /**
3882 * @brief Check if MSI ready interrupt occurred or not
3883 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
3884 * @retval State of bit (1 or 0).
3885 */
LL_RCC_IsActiveFlag_MSIRDY(void)3886 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
3887 {
3888 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)) ? 1UL : 0UL);
3889 }
3890
3891 /**
3892 * @brief Check if HSI ready interrupt occurred or not
3893 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
3894 * @retval State of bit (1 or 0).
3895 */
LL_RCC_IsActiveFlag_HSIRDY(void)3896 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
3897 {
3898 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
3899 }
3900
3901 /**
3902 * @brief Check if HSE ready interrupt occurred or not
3903 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
3904 * @retval State of bit (1 or 0).
3905 */
LL_RCC_IsActiveFlag_HSERDY(void)3906 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
3907 {
3908 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
3909 }
3910
3911 /**
3912 * @brief Check if PLL ready interrupt occurred or not
3913 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
3914 * @retval State of bit (1 or 0).
3915 */
LL_RCC_IsActiveFlag_PLLRDY(void)3916 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
3917 {
3918 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
3919 }
3920
3921 #if defined(RCC_HSI48_SUPPORT)
3922 /**
3923 * @brief Check if HSI48 ready interrupt occurred or not
3924 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
3925 * @retval State of bit (1 or 0).
3926 */
LL_RCC_IsActiveFlag_HSI48RDY(void)3927 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
3928 {
3929 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
3930 }
3931 #endif
3932
3933 #if defined(SAI1)
3934 /**
3935 * @brief Check if PLLSAI1 ready interrupt occurred or not
3936 * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
3937 * @retval State of bit (1 or 0).
3938 */
LL_RCC_IsActiveFlag_PLLSAI1RDY(void)3939 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
3940 {
3941 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF)) ? 1UL : 0UL);
3942 }
3943 #endif
3944
3945 /**
3946 * @brief Check if Clock security system interrupt occurred or not
3947 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
3948 * @retval State of bit (1 or 0).
3949 */
LL_RCC_IsActiveFlag_HSECSS(void)3950 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
3951 {
3952 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
3953 }
3954
3955 /**
3956 * @brief Check if LSE Clock security system interrupt occurred or not
3957 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
3958 * @retval State of bit (1 or 0).
3959 */
LL_RCC_IsActiveFlag_LSECSS(void)3960 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
3961 {
3962 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
3963 }
3964
3965 /**
3966 * @brief Check if HCLK1 prescaler flag value has been applied or not
3967 * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE
3968 * @retval State of bit (1 or 0).
3969 */
LL_RCC_IsActiveFlag_HPRE(void)3970 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void)
3971 {
3972 return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL);
3973 }
3974
3975 /**
3976 * @brief Check if HCLK2 prescaler flag value has been applied or not
3977 * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE
3978 * @retval State of bit (1 or 0).
3979 */
LL_RCC_IsActiveFlag_C2HPRE(void)3980 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void)
3981 {
3982 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL);
3983 }
3984
3985 /**
3986 * @brief Check if HCLK4 prescaler flag value has been applied or not
3987 * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE
3988 * @retval State of bit (1 or 0).
3989 */
LL_RCC_IsActiveFlag_SHDHPRE(void)3990 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void)
3991 {
3992 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL);
3993 }
3994
3995
3996 /**
3997 * @brief Check if PLCK1 prescaler flag value has been applied or not
3998 * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1
3999 * @retval State of bit (1 or 0).
4000 */
LL_RCC_IsActiveFlag_PPRE1(void)4001 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void)
4002 {
4003 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL);
4004 }
4005
4006 /**
4007 * @brief Check if PLCK2 prescaler flag value has been applied or not
4008 * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2
4009 * @retval State of bit (1 or 0).
4010 */
LL_RCC_IsActiveFlag_PPRE2(void)4011 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void)
4012 {
4013 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL);
4014 }
4015
4016 /**
4017 * @brief Check if RCC flag Independent Watchdog reset is set or not.
4018 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
4019 * @retval State of bit (1 or 0).
4020 */
LL_RCC_IsActiveFlag_IWDGRST(void)4021 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
4022 {
4023 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
4024 }
4025
4026 /**
4027 * @brief Check if RCC flag Low Power reset is set or not.
4028 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
4029 * @retval State of bit (1 or 0).
4030 */
LL_RCC_IsActiveFlag_LPWRRST(void)4031 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
4032 {
4033 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
4034 }
4035
4036 /**
4037 * @brief Check if RCC flag Option byte reset is set or not.
4038 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
4039 * @retval State of bit (1 or 0).
4040 */
LL_RCC_IsActiveFlag_OBLRST(void)4041 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
4042 {
4043 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
4044 }
4045
4046 /**
4047 * @brief Check if RCC flag Pin reset is set or not.
4048 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
4049 * @retval State of bit (1 or 0).
4050 */
LL_RCC_IsActiveFlag_PINRST(void)4051 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
4052 {
4053 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
4054 }
4055
4056 /**
4057 * @brief Check if RCC flag Software reset is set or not.
4058 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
4059 * @retval State of bit (1 or 0).
4060 */
LL_RCC_IsActiveFlag_SFTRST(void)4061 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
4062 {
4063 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
4064 }
4065
4066 /**
4067 * @brief Check if RCC flag Window Watchdog reset is set or not.
4068 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
4069 * @retval State of bit (1 or 0).
4070 */
LL_RCC_IsActiveFlag_WWDGRST(void)4071 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
4072 {
4073 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
4074 }
4075
4076 /**
4077 * @brief Check if RCC flag BOR reset is set or not.
4078 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
4079 * @retval State of bit (1 or 0).
4080 */
LL_RCC_IsActiveFlag_BORRST(void)4081 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
4082 {
4083 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL);
4084 }
4085
4086 /**
4087 * @brief Set RMVF bit to clear the reset flags.
4088 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
4089 * @retval None
4090 */
LL_RCC_ClearResetFlags(void)4091 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
4092 {
4093 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
4094 }
4095
4096 /**
4097 * @}
4098 */
4099
4100 /** @defgroup RCC_LL_EF_IT_Management IT Management
4101 * @{
4102 */
4103
4104 /**
4105 * @brief Enable LSI1 ready interrupt
4106 * @rmtoll CIER LSI1RDYIE LL_RCC_EnableIT_LSI1RDY
4107 * @retval None
4108 */
LL_RCC_EnableIT_LSI1RDY(void)4109 __STATIC_INLINE void LL_RCC_EnableIT_LSI1RDY(void)
4110 {
4111 SET_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
4112 }
4113
4114 /**
4115 * @brief Enable LSI2 ready interrupt
4116 * @rmtoll CIER LSI2RDYIE LL_RCC_EnableIT_LSI2RDY
4117 * @retval None
4118 */
LL_RCC_EnableIT_LSI2RDY(void)4119 __STATIC_INLINE void LL_RCC_EnableIT_LSI2RDY(void)
4120 {
4121 SET_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
4122 }
4123 /**
4124 * @brief Enable LSE ready interrupt
4125 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
4126 * @retval None
4127 */
LL_RCC_EnableIT_LSERDY(void)4128 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
4129 {
4130 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
4131 }
4132
4133 /**
4134 * @brief Enable MSI ready interrupt
4135 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
4136 * @retval None
4137 */
LL_RCC_EnableIT_MSIRDY(void)4138 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
4139 {
4140 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
4141 }
4142
4143 /**
4144 * @brief Enable HSI ready interrupt
4145 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
4146 * @retval None
4147 */
LL_RCC_EnableIT_HSIRDY(void)4148 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
4149 {
4150 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
4151 }
4152
4153 /**
4154 * @brief Enable HSE ready interrupt
4155 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
4156 * @retval None
4157 */
LL_RCC_EnableIT_HSERDY(void)4158 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
4159 {
4160 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
4161 }
4162
4163 /**
4164 * @brief Enable PLL ready interrupt
4165 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
4166 * @retval None
4167 */
LL_RCC_EnableIT_PLLRDY(void)4168 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
4169 {
4170 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
4171 }
4172
4173 #if defined(RCC_HSI48_SUPPORT)
4174 /**
4175 * @brief Enable HSI48 ready interrupt
4176 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
4177 * @retval None
4178 */
LL_RCC_EnableIT_HSI48RDY(void)4179 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
4180 {
4181 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
4182 }
4183 #endif
4184
4185 #if defined(SAI1)
4186 /**
4187 * @brief Enable PLLSAI1 ready interrupt
4188 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
4189 * @retval None
4190 */
LL_RCC_EnableIT_PLLSAI1RDY(void)4191 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
4192 {
4193 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
4194 }
4195 #endif
4196
4197 /**
4198 * @brief Enable LSE clock security system interrupt
4199 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
4200 * @retval None
4201 */
LL_RCC_EnableIT_LSECSS(void)4202 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
4203 {
4204 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
4205 }
4206
4207 /**
4208 * @brief Disable LSI1 ready interrupt
4209 * @rmtoll CIER LSI1RDYIE LL_RCC_DisableIT_LSI1RDY
4210 * @retval None
4211 */
LL_RCC_DisableIT_LSI1RDY(void)4212 __STATIC_INLINE void LL_RCC_DisableIT_LSI1RDY(void)
4213 {
4214 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
4215 }
4216
4217 /**
4218 * @brief Disable LSI2 ready interrupt
4219 * @rmtoll CIER LSI2RDYIE LL_RCC_DisableIT_LSI2RDY
4220 * @retval None
4221 */
LL_RCC_DisableIT_LSI2RDY(void)4222 __STATIC_INLINE void LL_RCC_DisableIT_LSI2RDY(void)
4223 {
4224 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
4225 }
4226 /**
4227 * @brief Disable LSE ready interrupt
4228 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
4229 * @retval None
4230 */
LL_RCC_DisableIT_LSERDY(void)4231 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
4232 {
4233 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
4234 }
4235
4236 /**
4237 * @brief Disable MSI ready interrupt
4238 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
4239 * @retval None
4240 */
LL_RCC_DisableIT_MSIRDY(void)4241 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
4242 {
4243 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
4244 }
4245
4246 /**
4247 * @brief Disable HSI ready interrupt
4248 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
4249 * @retval None
4250 */
LL_RCC_DisableIT_HSIRDY(void)4251 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
4252 {
4253 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
4254 }
4255
4256 /**
4257 * @brief Disable HSE ready interrupt
4258 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
4259 * @retval None
4260 */
LL_RCC_DisableIT_HSERDY(void)4261 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
4262 {
4263 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
4264 }
4265
4266 /**
4267 * @brief Disable PLL ready interrupt
4268 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
4269 * @retval None
4270 */
LL_RCC_DisableIT_PLLRDY(void)4271 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
4272 {
4273 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
4274 }
4275
4276 #if defined(RCC_HSI48_SUPPORT)
4277 /**
4278 * @brief Disable HSI48 ready interrupt
4279 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
4280 * @retval None
4281 */
LL_RCC_DisableIT_HSI48RDY(void)4282 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
4283 {
4284 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
4285 }
4286 #endif
4287
4288 #if defined(SAI1)
4289 /**
4290 * @brief Disable PLLSAI1 ready interrupt
4291 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
4292 * @retval None
4293 */
LL_RCC_DisableIT_PLLSAI1RDY(void)4294 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
4295 {
4296 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
4297 }
4298 #endif
4299
4300 /**
4301 * @brief Disable LSE clock security system interrupt
4302 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
4303 * @retval None
4304 */
LL_RCC_DisableIT_LSECSS(void)4305 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
4306 {
4307 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
4308 }
4309
4310 /**
4311 * @brief Checks if LSI1 ready interrupt source is enabled or disabled.
4312 * @rmtoll CIER LSI1RDYIE LL_RCC_IsEnabledIT_LSI1RDY
4313 * @retval State of bit (1 or 0).
4314 */
LL_RCC_IsEnabledIT_LSI1RDY(void)4315 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI1RDY(void)
4316 {
4317 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE) == (RCC_CIER_LSI1RDYIE)) ? 1UL : 0UL);
4318 }
4319
4320 /**
4321 * @brief Checks if LSI2 ready interrupt source is enabled or disabled.
4322 * @rmtoll CIER LSI2RDYIE LL_RCC_IsEnabledIT_LSI2RDY
4323 * @retval State of bit (1 or 0).
4324 */
LL_RCC_IsEnabledIT_LSI2RDY(void)4325 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI2RDY(void)
4326 {
4327 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE) == (RCC_CIER_LSI2RDYIE)) ? 1UL : 0UL);
4328 }
4329 /**
4330 * @brief Checks if LSE ready interrupt source is enabled or disabled.
4331 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
4332 * @retval State of bit (1 or 0).
4333 */
LL_RCC_IsEnabledIT_LSERDY(void)4334 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
4335 {
4336 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
4337 }
4338
4339 /**
4340 * @brief Checks if MSI ready interrupt source is enabled or disabled.
4341 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
4342 * @retval State of bit (1 or 0).
4343 */
LL_RCC_IsEnabledIT_MSIRDY(void)4344 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
4345 {
4346 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)) ? 1UL : 0UL);
4347 }
4348
4349 /**
4350 * @brief Checks if HSI ready interrupt source is enabled or disabled.
4351 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
4352 * @retval State of bit (1 or 0).
4353 */
LL_RCC_IsEnabledIT_HSIRDY(void)4354 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
4355 {
4356 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
4357 }
4358
4359 /**
4360 * @brief Checks if HSE ready interrupt source is enabled or disabled.
4361 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
4362 * @retval State of bit (1 or 0).
4363 */
LL_RCC_IsEnabledIT_HSERDY(void)4364 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
4365 {
4366 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
4367 }
4368
4369 /**
4370 * @brief Checks if PLL ready interrupt source is enabled or disabled.
4371 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
4372 * @retval State of bit (1 or 0).
4373 */
LL_RCC_IsEnabledIT_PLLRDY(void)4374 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
4375 {
4376 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
4377 }
4378
4379 #if defined(RCC_HSI48_SUPPORT)
4380 /**
4381 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
4382 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
4383 * @retval State of bit (1 or 0).
4384 */
LL_RCC_IsEnabledIT_HSI48RDY(void)4385 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
4386 {
4387 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
4388 }
4389 #endif
4390
4391 #if defined(SAI1)
4392 /**
4393 * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
4394 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
4395 * @retval State of bit (1 or 0).
4396 */
LL_RCC_IsEnabledIT_PLLSAI1RDY(void)4397 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
4398 {
4399 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE)) ? 1UL : 0UL);
4400 }
4401 #endif
4402
4403 /**
4404 * @brief Checks if LSECSS interrupt source is enabled or disabled.
4405 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
4406 * @retval State of bit (1 or 0).
4407 */
LL_RCC_IsEnabledIT_LSECSS(void)4408 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
4409 {
4410 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
4411 }
4412
4413 /**
4414 * @}
4415 */
4416
4417 #if defined(USE_FULL_LL_DRIVER)
4418 /** @defgroup RCC_LL_EF_Init De-initialization function
4419 * @{
4420 */
4421 ErrorStatus LL_RCC_DeInit(void);
4422 /**
4423 * @}
4424 */
4425
4426 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
4427 * @{
4428 */
4429 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
4430 #if defined(RCC_SMPS_SUPPORT)
4431 uint32_t LL_RCC_GetSMPSClockFreq(void);
4432 #endif
4433 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
4434 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
4435 #if defined(LPUART1)
4436 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
4437 #endif
4438 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
4439 #if defined(SAI1)
4440 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
4441 #endif
4442 uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource);
4443 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
4444 #if defined(USB)
4445 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
4446 #endif
4447 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
4448 uint32_t LL_RCC_GetRTCClockFreq(void);
4449 uint32_t LL_RCC_GetRFWKPClockFreq(void);
4450 /**
4451 * @}
4452 */
4453 #endif /* USE_FULL_LL_DRIVER */
4454
4455 /**
4456 * @}
4457 */
4458
4459 /**
4460 * @}
4461 */
4462
4463 #endif /* defined(RCC) */
4464
4465 /**
4466 * @}
4467 */
4468
4469 #ifdef __cplusplus
4470 }
4471 #endif
4472
4473 #endif /* STM32WBxx_LL_RCC_H */
4474
4475 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4476
