1 /**
2 ******************************************************************************
3 * @file stm32wb0x_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WB0x_LL_RCC_H
21 #define STM32WB0x_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif /* __cplusplus */
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wb0x.h"
29
30 /** @addtogroup STM32WB0x_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
43 * @{
44 */
45
46 /**
47 * @}
48 */
49
50 /* Private constants ---------------------------------------------------------*/
51 /* Private macros ------------------------------------------------------------*/
52 #if defined(USE_FULL_LL_DRIVER)
53 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
54 * @{
55 */
56 /**
57 * @}
58 */
59 #endif /*USE_FULL_LL_DRIVER*/
60
61 /* Exported types ------------------------------------------------------------*/
62 #if defined(USE_FULL_LL_DRIVER)
63 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
64 * @{
65 */
66
67 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
68 * @{
69 */
70
71 /**
72 * @brief RCC Clocks Frequency Structure
73 */
74 typedef struct
75 {
76 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
77 } LL_RCC_ClocksTypeDef;
78
79 /**
80 * @}
81 */
82
83 /**
84 * @}
85 */
86 #endif /* USE_FULL_LL_DRIVER */
87
88 /* Exported constants --------------------------------------------------------*/
89 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
90 * @{
91 */
92
93 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
94 * @brief Defines used to adapt values of different oscillators
95 * @note These values could be modified in the user environment according to
96 * HW set-up.
97 * @{
98 */
99 #if !defined (HSE_VALUE)
100 #define HSE_VALUE 32000000U /*!< Value of the HSE oscillator in Hz */
101 #endif /* HSE_VALUE */
102
103 #if !defined (HSI_VALUE)
104 #define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */
105 #endif /* HSI_VALUE */
106
107 #if !defined (RC64MPLL_VALUE)
108 #define RC64MPLL_VALUE 64000000U /*!< Value of the RC 64 MHz PLL clock in Hz */
109 #endif /* HSI_VALUE */
110
111 #if !defined (LSE_VALUE)
112 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
113 #endif /* LSE_VALUE */
114
115 #if !defined (LSI_VALUE)
116 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
117 #endif /* LSI_VALUE */
118
119 /**
120 * @}
121 */
122
123 /** @defgroup RCC_LL_EC_GET_CLEAR_FLAG Ready Interrupt Flags Defines
124 * @brief Flags defines which can be used with LL_RCC_ReadReg LL_RCC_WriteReg function
125 * @{
126 */
127 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt Flag/Clear */
128 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt Flag/Clear */
129 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt Flag/Clear */
130 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt Flag/Clear */
131 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_HSIPLLRDYF /*!< PLL Ready Interrupt Flag/Clear */
132 #define LL_RCC_CIFR_PLLUNLOCKDETF RCC_CIFR_HSIPLLUNLOCKDETF /*!< PLL Unlock Interrupt Flag/Clear */
133 #define LL_RCC_CIFR_RTCRSTRELF RCC_CIFR_RTCRSTF /*!< RTC Reset Release Interrupt Flag/Clear */
134 #define LL_RCC_CIFR_WDGRSTRELF RCC_CIFR_WDGRSTF /*!< WDG Reset Release Interrupt Flag/Clear */
135 #if defined(RCC_CIFR_LPURSTF)
136 #define LL_RCC_CIFR_LPURSTRELF RCC_CIFR_LPURSTF /*!< LPUART Reset Release Interrupt Flag/Clear */
137 #endif
138
139 /**
140 * @}
141 */
142
143 /** @defgroup RCC_LL_EC_GET_FLAG Reset Flags Defines
144 * @brief Flags defines which can be used with LL_RCC_ReadReg function
145 * @{
146 */
147 #define LL_RCC_CSR_LOCKUPRSTF RCC_CSR_LOCKUPRSTF /*!< CPU lockup reset flag */
148 #define LL_RCC_CSR_WDGRSTF RCC_CSR_WDGRSTF /*!< Watchdog reset flag */
149 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software reset flag */
150 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< Power-On or BOR reset flag */
151 #define LL_RCC_CSR_PADRSTF RCC_CSR_PADRSTF /*!< NRSTn pad reset flag */
152 /**
153 * @}
154 */
155
156 /** @defgroup RCC_LL_EC_IT IT Enable Defines
157 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
158 * @{
159 */
160 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_HSIPLLRDYIE /*!< PLL ready interrupt enable */
161 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE ready interrupt enable */
162 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI ready interrupt enable */
163 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE ready interrupt enable */
164 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI ready interrupt enable */
165 /**
166 * @}
167 */
168
169 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
170 * @{
171 */
172 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
173 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_CSSWCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
174 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_CSSWCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
175 #define LL_RCC_LSEDRIVE_HIGH RCC_CSSWCR_LSEDRV /*!< Xtal mode higher driving capability */
176 /**
177 * @}
178 */
179
180 /** @defgroup RCC_LL_EC_HSE_CURRENT_CONTROL HSE current control max limits
181 * @{
182 */
183 #define LL_RCC_HSE_CURRENTMAX_0 0x000000000U /*!< HSE current control max limit = 0.18 mA/V*/
184 #define LL_RCC_HSE_CURRENTMAX_1 RCC_RFSWHSECR_GMC_0 /*!< HSE current control max limit = 0.57 mA/V*/
185 #define LL_RCC_HSE_CURRENTMAX_2 RCC_RFSWHSECR_GMC_1 /*!< HSE current control max limit = 0.78 mA/V*/
186 #define LL_RCC_HSE_CURRENTMAX_3 (RCC_RFSWHSECR_GMC_1| RCC_RFSWHSECR_GMC_0) /*!< HSE current control max limit = 1.13 mA/V*/
187 #define LL_RCC_HSE_CURRENTMAX_4 RCC_RFSWHSECR_GMC_2 /*!< HSE current control max limit = 0.61 mA/V*/
188 #define LL_RCC_HSE_CURRENTMAX_5 (RCC_RFSWHSECR_GMC_2|RCC_RFSWHSECR_GMC_0) /*!< HSE current control max limit = 1.65 mA/V*/
189 #define LL_RCC_HSE_CURRENTMAX_6 (RCC_RFSWHSECR_GMC_2|RCC_RFSWHSECR_GMC_1) /*!< HSE current control max limit = 2.12 mA/V*/
190 #define LL_RCC_HSE_CURRENTMAX_7 RCC_RFSWHSECR_GMC /*!< HSE current control max limit = 2.84 mA/V*/
191 /**
192 * @}
193 */
194
195 #if defined(RCC_RFSWHSECR_SATRG)
196 /** @defgroup RCC_LL_EC_HSE_SENSE_AMPLIFIER HSE sense amplifier threshold
197 * @{
198 */
199 #define LL_RCC_HSEAMPTHRESHOLD_1_2 (0x000000000U) /*!< HSE sense amplifier bias current factor = 1/2*/
200 #define LL_RCC_HSEAMPTHRESHOLD_3_4 RCC_RFSWHSECR_SATRG /*!< HSE sense amplifier bias current factor = 3/4*/
201 /**
202 * @}
203 */
204 #endif
205
206 /** @defgroup RCC_LL_EC_LOCKDET_NSTOP LOCKDET_NSTOP time selection
207 * @{
208 */
209 #define LL_RCC_LOCKDET_NSTOP_0 0x00000000U
210 #define LL_RCC_LOCKDET_NSTOP_1 RCC_LOCKDET_NSTOP_0
211 #define LL_RCC_LOCKDET_NSTOP_2 RCC_LOCKDET_NSTOP_1
212 #define LL_RCC_LOCKDET_NSTOP_3 RCC_LOCKDET_NSTOP_1 | RCC_LOCKDET_NSTOP_0
213 #define LL_RCC_LOCKDET_NSTOP_4 RCC_LOCKDET_NSTOP_2
214 #define LL_RCC_LOCKDET_NSTOP_5 RCC_LOCKDET_NSTOP_2 | RCC_LOCKDET_NSTOP_0
215 #define LL_RCC_LOCKDET_NSTOP_6 RCC_LOCKDET_NSTOP_2 | RCC_LOCKDET_NSTOP_1
216 #define LL_RCC_LOCKDET_NSTOP_7 RCC_LOCKDET_NSTOP_2 | RCC_LOCKDET_NSTOP_1 | RCC_LOCKDET_NSTOP_0
217 /**
218 * @}
219 */
220
221 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Source Selection
222 * @{
223 */
224 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_CFGR_CLKSLOWSEL_0 /*!< LSE selection for low speed clock */
225 #define LL_RCC_LSCO_CLKSOURCE_LSI RCC_CFGR_CLKSLOWSEL_1 /*!< Enable the LSI selection for low speed clock */
226 #define LL_RCC_LSCO_CLKSOURCE_HSI64M_DIV2048 RCC_CFGR_CLKSLOWSEL /*!< HSI_64M divided by 2048 selection for low speed clock */
227 /**
228 * @}
229 */
230
231 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE_ENABLE Enable LSCO Clock Source
232 * @{
233 */
234 #define LL_RCC_LSCO_LSI RCC_CR_LSION /*!< Enable LSI selection for low speed clock */
235 #define LL_RCC_LSCO_LSE RCC_CR_LSEON /*!< Enable LSE selection for low speed clock */
236 #define LL_RCC_LSCO_LSEBYP RCC_CR_LSEBYP /*!< Enable LSE clock bypass selection for low speed clock */
237 /**
238 * @}
239 */
240
241 /** @defgroup RCC_LL_HSEPLLBUFON Enable the External high speed clock buffer for PLL
242 * @{
243 */
244 #define LL_RCC_HSEPLLBUF_OFF 0x00000000U /*!< Disable the External high speed clock buffer for PLL */
245 #define LL_RCC_HSEPLLBUF_ON RCC_CR_HSEPLLBUFON /*!< Enable the External high speed clock buffer for PLL. Always enabled when the radio is used */
246 /**
247 * @}
248 */
249
250
251 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE Enable HS clock Source
252 * @{
253 */
254 #define LL_RCC_SYS_HSI 0x00000000U /*!< Enable HSI system clock */
255 #define LL_RCC_SYS_HSE RCC_CR_HSEON /*!< Enable HSE system clock */
256 /**
257 * @}
258 */
259
260 /** @defgroup RCC_LL_EC_RF_CLKSOURCE RF system clock
261 * @{
262 */
263 #if defined(RCC_APB2ENR_CLKBLEDIV_0)
264 #define LL_RCC_RF_CLK_32M RCC_APB2ENR_CLKBLEDIV_0 /*!< Radio system clock 32 MHz*/
265 #else
266 #define LL_RCC_RF_CLK_32M 0x00000000U /*!< Radio system clock 32 MHz*/
267 #endif
268 #if defined(RCC_APB2ENR_CLKBLEDIV_1)
269 #define LL_RCC_RF_CLK_16M RCC_APB2ENR_CLKBLEDIV_1 /*!< Radio system clock 16 MHz*/
270 #else
271 #define LL_RCC_RF_CLK_16M RCC_APB2ENR_CLKBLEDIV /*!< Radio system clock 16 MHz*/
272 #endif
273 /**
274 * @}
275 */
276
277 /** @defgroup RCC_DIRECT_HSE_Clock_Divider DIRECT HSE Clock Divider
278 * @{
279 */
280 #define LL_RCC_DIRECT_HSE_DIV_1 RCC_CFGR_CLKSYSDIV_0 /*!< DIRECT HSE division factor = 1 */
281 #define LL_RCC_DIRECT_HSE_DIV_2 RCC_CFGR_CLKSYSDIV_1 /*!< DIRECT HSE division factor = 2 */
282 #define LL_RCC_DIRECT_HSE_DIV_4 (RCC_CFGR_CLKSYSDIV_1 | RCC_CFGR_CLKSYSDIV_0) /*!< DIRECT HSE division factor = 4 */
283 #define LL_RCC_DIRECT_HSE_DIV_8 RCC_CFGR_CLKSYSDIV_2 /*!< DIRECT HSE division factor = 8 */
284 #define LL_RCC_DIRECT_HSE_DIV_16 (RCC_CFGR_CLKSYSDIV_2 | RCC_CFGR_CLKSYSDIV_0) /*!< DIRECT HSE division factor = 16 */
285 #define LL_RCC_DIRECT_HSE_DIV_32 (RCC_CFGR_CLKSYSDIV_2 | RCC_CFGR_CLKSYSDIV_1) /*!< DIRECT HSE division factor = 32 */
286 /**
287 * @}
288 */
289
290 /** @defgroup RCC_LL_EC_SYSCLK_DIV RC64MPLL divider factor to have the System clock
291 * @{
292 */
293 #define LL_RCC_RC64MPLL_DIV_1 0x00000000U /*!< RC64MPLL not divided as SYSCLK */
294 #define LL_RCC_RC64MPLL_DIV_2 RCC_CFGR_CLKSYSDIV_0 /*!< RC64MPLL divided by 2 as SYSCLK */
295 #define LL_RCC_RC64MPLL_DIV_4 RCC_CFGR_CLKSYSDIV_1 /*!< RC64MPLL divided by 4 as SYSCLK */
296 #define LL_RCC_RC64MPLL_DIV_8 (RCC_CFGR_CLKSYSDIV_1 | RCC_CFGR_CLKSYSDIV_0) /*!< RC64MPLL divided by 8 as SYSCLK */
297 #define LL_RCC_RC64MPLL_DIV_16 RCC_CFGR_CLKSYSDIV_2 /*!< RC64MPLL divided by 16 as SYSCLK */
298 #define LL_RCC_RC64MPLL_DIV_32 (RCC_CFGR_CLKSYSDIV_2 | RCC_CFGR_CLKSYSDIV_0) /*!< RC64MPLL divided by 32 as SYSCLK */
299 #define LL_RCC_RC64MPLL_DIV_64 (RCC_CFGR_CLKSYSDIV_2 | RCC_CFGR_CLKSYSDIV_1) /*!< RC64MPLL divided by 64 as SYSCLK */
300 /**
301 * @}
302 */
303
304 /** @defgroup RCC_LL_EC_SYSCLK_SWITCH_DIV RC64MPLL divider factor to switch the System clock with MR_BLE enabled
305 * @{
306 */
307 #define LL_RCC_RC64MPLL_SWITCH_DIV_1 0x00000000U /*!< RC64MPLL not divided as SYSCLK */
308 #define LL_RCC_RC64MPLL_SWITCH_DIV_2 RCC_CSCMDR_CLKSYSDIV_REQ_0 /*!< RC64MPLL divided by 2 as SYSCLK */
309 #define LL_RCC_RC64MPLL_SWITCH_DIV_4 RCC_CSCMDR_CLKSYSDIV_REQ_1 /*!< RC64MPLL divided by 4 as SYSCLK */
310 /**
311 * @}
312 */
313
314 /** @defgroup RCC_LL_EC_SYSCLK_SWITCH_STATUS Status of the RC64MPLL clock switch with MR_BLE enabled
315 * @{
316 */
317 #define LL_RCC_RC64MPLL_SWITCH_STATUS_IDLE 0x00000000U /*!< RC64MPLL Clock Switch Status IDLE */
318 #define LL_RCC_RC64MPLL_SWITCH_STATUS_ONGOING RCC_CSCMDR_STATUS_0 /*!< RC64MPLL Clock Switch Status ONGOING */
319 #define LL_RCC_RC64MPLL_SWITCH_STATUS_DONE RCC_CSCMDR_STATUS_1 /*!< RC64MPLL Clock Switch Status DONE */
320 /**
321 * @}
322 */
323
324 /** @defgroup RCC_LL_EC_MCOSOURCE MCO SOURCE selection
325 * @{
326 */
327 #define LL_RCC_MCOSOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
328 #define LL_RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO source */
329 #define LL_RCC_MCOSOURCE_HSI (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO source */
330 #define LL_RCC_MCOSOURCE_RC64MPLL (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1) /*!< RC64MPLL selection as MCO source */
331 #define LL_RCC_MCOSOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE after stabilization selection as MCO source */
332 #define LL_RCC_MCOSOURCE_HSI64M_DIV2048 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< HSI_64M divided by 2048 seelction as MCO source */
333 #define LL_RCC_MCOSOURCE_SMPS (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< SMPS selection as MCO source */
334 #define LL_RCC_MCOSOURCE_ADC RCC_CFGR_MCOSEL /*!< ADC selection as MCO source */
335 /**
336 * @}
337 */
338
339 /** @defgroup RCC_LL_EC_MCO_DIV MCO prescaler
340 * @{
341 */
342 #define LL_RCC_MCO_DIV_1 0x00000000U /*!< MCO not divided */
343 #define LL_RCC_MCO_DIV_2 RCC_CFGR_CCOPRE_0 /*!< MCO divided by 2 */
344 #define LL_RCC_MCO_DIV_4 RCC_CFGR_CCOPRE_1 /*!< MCO divided by 4 */
345 #define LL_RCC_MCO_DIV_8 (RCC_CFGR_CCOPRE_1 | RCC_CFGR_CCOPRE_0) /*!< MCO divided by 8 */
346 #define LL_RCC_MCO_DIV_16 RCC_CFGR_CCOPRE_2 /*!< MCO divided by 16 */
347 #define LL_RCC_MCO_DIV_32 (RCC_CFGR_CCOPRE_2 | RCC_CFGR_CCOPRE_0) /*!< MCO divided by 32 */
348 /**
349 * @}
350 */
351
352 /** @defgroup RCC_LL_EC_LSCOSOURCE LCO SOURCE selection
353 * @{
354 */
355 #define LL_RCC_LSCOSOURCE_NOCLOCK 0x00000000U /*!< LSCO output disabled, no clock on LSCO */
356 #define LL_RCC_LSCOSOURCE_LSI RCC_CFGR_LCOSEL_1 /*!< LSI selection as LSCO source */
357 #define LL_RCC_LSCOSOURCE_LSE (RCC_CFGR_LCOSEL_0|RCC_CFGR_LCOSEL_1) /*!< LSE selection as LSCO source */
358 /**
359 * @}
360 */
361
362 /** @defgroup RCC_LL_EC_SMPS_DIV SMPS prescaler
363 * @{
364 */
365 #define LL_RCC_SMPS_DIV_2 (0x00000000U) /*!< SMPS clock division 2 (SMPS clock is 8 MHz)*/
366 #define LL_RCC_SMPS_DIV_4 RCC_CFGR_SMPSDIV /*!< SMPS clock division 4 (SMPS clock is 4 MHz)*/
367 /**
368 * @}
369 */
370
371 #if defined(RCC_CFGR_LPUCLKSEL)
372 /** @defgroup RCC_LL_CFGR_LPU_CLK LPUART clock selection
373 * @{
374 */
375 #define LL_RCC_LPUCLKSEL_CLK16M (0x00000000U) /*!< LPUART Clock Selection 16 MHz */
376 #define LL_RCC_LPUCLKSEL_CLKLSE RCC_CFGR_LPUCLKSEL /*!< LPUART Clock Selection LSE source */
377 /**
378 * @}
379 */
380 #endif /* RCC_CFGR_LPUCLKSEL */
381
382 #if defined(USE_FULL_LL_DRIVER)
383 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
384 * @{
385 */
386 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
387 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
388 /**
389 * @}
390 */
391 #endif /* USE_FULL_LL_DRIVER */
392
393 #if defined(SPI2)
394 /** @defgroup RCC_LL_EC_SPI2_I2S SPI2_I2S
395 * @{
396 */
397 #define LL_RCC_SPI2_I2S_CLK16M 0x00000000U /*!< SPI2 I2S 16 MHz clock source selection bits */
398 #define LL_RCC_SPI2_I2S_CLK32M RCC_CFGR_SPI2I2SCLKSEL /*!< SPI2 I2S 32 MHz clock source selection bits */
399 /**
400 * @}
401 */
402 #endif
403
404 /** @defgroup RCC_LL_EC_SPI3_I2S SPI3_I2S
405 * @{
406 */
407 #define LL_RCC_SPI3_I2S_CLK16M 0x00000000U /*!< SPI3 I2S 16 MHz clock source selection bits */
408 #if !defined(RCC_CFGR_SPI3I2SCLKSEL_0)
409 #define LL_RCC_SPI3_I2S_CLK32M RCC_CFGR_SPI3I2SCLKSEL /*!< SPI3 I2S 32 MHz clock source selection bits */
410 #endif
411 #if defined(RCC_CFGR_SPI3I2SCLKSEL_0)
412 #define LL_RCC_SPI3_I2S_CLK32M RCC_CFGR_SPI3I2SCLKSEL_0 /*!< SPI3 I2S 32 MHz clock source selection bits */
413 #define LL_RCC_SPI3_I2S_CLK64M RCC_CFGR_SPI3I2SCLKSEL_1 /*!< SPI3 I2S 64 MHz clock source selection bits */
414 #endif
415 /**
416 * @}
417 */
418
419 #if defined(RCC_CFGR_LPUCLKSEL)
420 /** @defgroup RCC_LL_EC_LPUART1 LPUART1
421 * @{
422 */
423 #define LL_RCC_LPUART1_CLKSOURCE 0x00000000U /*!< LPUART1 clock source */
424 /**
425 * @}
426 */
427 #endif /* RCC_CFGR_LPUCLKSEL */
428
429 /**
430 * @}
431 */
432
433 /* Exported macro ------------------------------------------------------------*/
434 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
435 * @{
436 */
437
438 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
439 * @{
440 */
441
442 /**
443 * @brief Write a value in RCC register
444 * @param __REG__ Register to be written
445 * @param __VALUE__ Value to be written in the register
446 * @retval None
447 */
448 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
449
450 /**
451 * @brief Read a value in RCC register
452 * @param __REG__ Register to be read
453 * @retval Register value
454 */
455 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
456 /**
457 * @}
458 */
459
460 /**
461 * @}
462 */
463
464 /* Exported functions --------------------------------------------------------*/
465 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
466 * @{
467 */
468
469 /** @defgroup RCC_LL_EF_HSE HSE
470 * @{
471 */
472
473 /**
474 * @brief Enable HSE crystal oscillator (HSE ON)
475 * @rmtoll CR HSEON LL_RCC_HSE_Enable
476 * @retval None
477 */
LL_RCC_HSE_Enable(void)478 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
479 {
480 SET_BIT(RCC->CR, RCC_CR_HSEON);
481 }
482
483 /**
484 * @brief Disable HSE crystal oscillator (HSE ON)
485 * @rmtoll CR HSEON LL_RCC_HSE_Disable
486 * @retval None
487 */
LL_RCC_HSE_Disable(void)488 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
489 {
490 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
491 }
492
493 /**
494 * @brief Check if HSE crystal oscillator is enabled.
495 * @rmtoll CR HSEON LL_RCC_HSE_IsEnabled
496 * @retval State of bit (1 or 0).
497 */
LL_RCC_HSE_IsEnabled(void)498 __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabled(void)
499 {
500 return ((READ_BIT(RCC->CR, RCC_CR_HSEON) == (RCC_CR_HSEON)) ? 1UL : 0UL);
501 }
502
503 /**
504 * @brief Check if HSE oscillator Ready
505 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
506 * @retval State of bit (1 or 0).
507 */
LL_RCC_HSE_IsReady(void)508 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
509 {
510 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
511 }
512
513 /**
514 * @brief Set HSE capacitor tuning
515 * @rmtoll RFSWHSECR SWXOTUNE LL_RCC_HSE_SetCapacitorTuning
516 * @param Value Between Min_Data = 0 and Max_Data = 63
517 * @retval None
518 */
LL_RCC_HSE_SetCapacitorTuning(uint32_t Value)519 __STATIC_INLINE void LL_RCC_HSE_SetCapacitorTuning(uint32_t Value)
520 {
521 MODIFY_REG(RCC->RFSWHSECR, RCC_RFSWHSECR_SWXOTUNE, Value << RCC_RFSWHSECR_SWXOTUNE_Pos);
522 SET_BIT(RCC->RFSWHSECR, RCC_RFSWHSECR_SWXOTUNEEN);
523 }
524
525 /**
526 * @brief Get HSE capacitor tuning
527 * @rmtoll RFSWHSECR SWXOTUNE LL_RCC_HSE_GetCapacitorTuning
528 * @retval Between Min_Data = 0 and Max_Data = 63
529 */
LL_RCC_HSE_GetCapacitorTuning(void)530 __STATIC_INLINE uint32_t LL_RCC_HSE_GetCapacitorTuning(void)
531 {
532 return (uint32_t)(READ_BIT(RCC->RFSWHSECR, RCC_RFSWHSECR_SWXOTUNE) >> RCC_RFSWHSECR_SWXOTUNE_Pos);
533 }
534
535 /**
536 * @brief Set HSE current control
537 * @rmtoll RFSWHSECR GMC LL_RCC_HSE_SetCurrentControl
538 * @param CurrentMax This parameter can be one of the following values:
539 * @arg @ref LL_RCC_HSE_CURRENTMAX_0
540 * @arg @ref LL_RCC_HSE_CURRENTMAX_1
541 * @arg @ref LL_RCC_HSE_CURRENTMAX_2
542 * @arg @ref LL_RCC_HSE_CURRENTMAX_3
543 * @arg @ref LL_RCC_HSE_CURRENTMAX_4
544 * @arg @ref LL_RCC_HSE_CURRENTMAX_5
545 * @arg @ref LL_RCC_HSE_CURRENTMAX_6
546 * @arg @ref LL_RCC_HSE_CURRENTMAX_7
547 */
LL_RCC_HSE_SetCurrentControl(uint32_t CurrentMax)548 __STATIC_INLINE void LL_RCC_HSE_SetCurrentControl(uint32_t CurrentMax)
549 {
550 MODIFY_REG(RCC->RFSWHSECR, RCC_RFSWHSECR_GMC, CurrentMax);
551 }
552
553 /**
554 * @brief Get HSE current control
555 * @rmtoll RFSWHSECR GMC LL_RCC_HSE_GetCurrentControl
556 * @retval Returned value can be one of the following values:
557 * @arg @ref LL_RCC_HSE_CURRENTMAX_0
558 * @arg @ref LL_RCC_HSE_CURRENTMAX_1
559 * @arg @ref LL_RCC_HSE_CURRENTMAX_2
560 * @arg @ref LL_RCC_HSE_CURRENTMAX_3
561 * @arg @ref LL_RCC_HSE_CURRENTMAX_4
562 * @arg @ref LL_RCC_HSE_CURRENTMAX_5
563 * @arg @ref LL_RCC_HSE_CURRENTMAX_6
564 * @arg @ref LL_RCC_HSE_CURRENTMAX_7
565 */
LL_RCC_HSE_GetCurrentControl(void)566 __STATIC_INLINE uint32_t LL_RCC_HSE_GetCurrentControl(void)
567 {
568 return (uint32_t)(READ_BIT(RCC->RFSWHSECR, RCC_RFSWHSECR_GMC));
569 }
570
571 #if defined(RCC_RFSWHSECR_SATRG)
572 /**
573 * @brief Set HSE sense amplifier threshold
574 * @rmtoll RFSWHSECR SATRG LL_RCC_HSE_SetSenseAmplifier
575 * @param SenseAmplifier This parameter can be one of the following values:
576 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_1_2
577 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_3_4
578 */
LL_RCC_HSE_SetSenseAmplifier(uint32_t SenseAmplifier)579 __STATIC_INLINE void LL_RCC_HSE_SetSenseAmplifier(uint32_t SenseAmplifier)
580 {
581 MODIFY_REG(RCC->RFSWHSECR, RCC_RFSWHSECR_SATRG, SenseAmplifier);
582 }
583
584 /**
585 * @brief Get HSE current control
586 * @rmtoll RFSWHSECR SATRG LL_RCC_HSE_GetSenseAmplifier
587 * @retval Returned value can be one of the following values:
588 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_1_2
589 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_3_4
590 */
LL_RCC_HSE_GetSenseAmplifier(void)591 __STATIC_INLINE uint32_t LL_RCC_HSE_GetSenseAmplifier(void)
592 {
593 return (uint32_t)(READ_BIT(RCC->RFSWHSECR, RCC_RFSWHSECR_SATRG));
594 }
595 #endif
596
597 #if defined(RCC_RFSWHSECR_ISTARTUP)
598 /**
599 * @brief Set HSE startup current
600 * @rmtoll RFSWHSECR ISTARTUP LL_RCC_HSE_SetStartupCurrent
601 * @param StartupCurrent HSE startup current
602 */
LL_RCC_HSE_SetStartupCurrent(uint32_t StartupCurrent)603 __STATIC_INLINE void LL_RCC_HSE_SetStartupCurrent(uint32_t StartupCurrent)
604 {
605 MODIFY_REG_FIELD(RCC->RFSWHSECR, RCC_RFSWHSECR_ISTARTUP, StartupCurrent);
606 }
607
608 /**
609 * @brief Get HSE startup current
610 * @rmtoll RFSWHSECR ISTARTUP LL_RCC_HSE_GetStartupCurrent
611 * @retval Startup Current value
612 */
LL_RCC_HSE_GetStartupCurrent(void)613 __STATIC_INLINE uint32_t LL_RCC_HSE_GetStartupCurrent(void)
614 {
615 return (uint32_t)(READ_REG_FIELD(RCC->RFSWHSECR, RCC_RFSWHSECR_ISTARTUP));
616 }
617 #endif
618 #if defined(RCC_RFSWHSECR_AMPLTHRESH)
619 /**
620 * @brief Set HSE Amplitude Control threshold
621 * @rmtoll RFSWHSECR AMPLTHRESH LL_RCC_HSE_SetAmplitudeThreshold
622 * @param AmplThr HSE Amplitude Control threshold
623 */
LL_RCC_HSE_SetAmplitudeThreshold(uint32_t AmplThr)624 __STATIC_INLINE void LL_RCC_HSE_SetAmplitudeThreshold(uint32_t AmplThr)
625 {
626 MODIFY_REG_FIELD(RCC->RFSWHSECR, RCC_RFSWHSECR_AMPLTHRESH, AmplThr);
627 }
628
629 /**
630 * @brief Get HSE Amplitude Control threshold
631 * @rmtoll RFSWHSECR AMPLTHRESH LL_RCC_HSE_GetAmplitudeThreshold
632 * @retval HSE Amplitude Control threshold
633 */
LL_RCC_HSE_GetAmplitudeThreshold(void)634 __STATIC_INLINE uint32_t LL_RCC_HSE_GetAmplitudeThreshold(void)
635 {
636 return (uint32_t)(READ_REG_FIELD(RCC->RFSWHSECR, RCC_RFSWHSECR_AMPLTHRESH));
637 }
638 #endif
639 /**
640 * @}
641 */
642
643 /** @defgroup RCC_LL_EF_HSI HSI
644 * @{
645 */
646
647 /**
648 * @brief Enable HSI
649 * @rmtoll CFGR STOPHSI LL_RCC_HSI_Enable
650 * @retval None
651 */
LL_RCC_HSI_Enable(void)652 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
653 {
654 CLEAR_BIT(RCC->CFGR, RCC_CFGR_STOPHSI);
655 CLEAR_BIT(RCC->CFGR, RCC_CFGR_HSESEL);
656 }
657
658 /**
659 * @brief Disable HSI
660 * @rmtoll CFGR STOPHSI LL_RCC_HSI_Disable
661 * @retval None
662 */
LL_RCC_HSI_Disable(void)663 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
664 {
665 SET_BIT(RCC->CFGR, RCC_CFGR_HSESEL);
666 SET_BIT(RCC->CFGR, RCC_CFGR_STOPHSI);
667 }
668
669 /**
670 * @brief Check if HSI clock is ready
671 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
672 * @retval State of bit (1 or 0).
673 */
LL_RCC_HSI_IsReady(void)674 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
675 {
676 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
677 }
678
679 /**
680 * @brief Set HSI Calibration trimming
681 * @note user-programmable trimming value
682 * @note Default value is loaded by HW at reset as soon as the flash controller achieves the reading of the
683 * information in Flash memory (reg. ICSCR).
684 * @rmtoll CSSWCR HSITRIM LL_RCC_HSI_SetCalibTrimming
685 * @param Value Between Min_Data = 0 and Max_Data = 127
686 * @retval None
687 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)688 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
689 {
690 MODIFY_REG(RCC->CSSWCR, RCC_CSSWCR_HSITRIMSW, Value << RCC_CSSWCR_HSITRIMSW_Pos);
691 SET_BIT(RCC->CSSWCR, RCC_CSSWCR_HSISWTRIMEN);
692 }
693
694 /**
695 * @brief Get HSI Calibration trimming
696 * @rmtoll ICSCR/CSSWCR HSITRIM LL_RCC_HSI_GetCalibTrimming
697 * @retval Between Min_Data = 0 and Max_Data = 127
698 */
LL_RCC_HSI_GetCalibTrimming(void)699 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
700 {
701 if ((uint32_t)(READ_BIT(RCC->CSSWCR, RCC_CSSWCR_HSISWTRIMEN)))
702 {
703 return (uint32_t)(READ_BIT(RCC->CSSWCR, RCC_CSSWCR_HSITRIMSW) >> RCC_CSSWCR_HSITRIMSW_Pos);
704 }
705 else
706 {
707 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
708 }
709 }
710 /**
711 * @}
712 */
713
714 /** @defgroup RCC_LL_EF_DIRECT_HSE DIRECT_HSE
715 * @{
716 */
717 /**
718 * @brief Enable DIRECT_HSE mode
719 * @rmtoll CFGR HSESEL/STOPHSI LL_RCC_HSE_Enable
720 * @retval None
721 */
LL_RCC_DIRECT_HSE_Enable(void)722 __STATIC_INLINE void LL_RCC_DIRECT_HSE_Enable(void)
723 {
724 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0);
725 SET_BIT(RCC->CFGR, RCC_CFGR_HSESEL);
726 for (volatile int i = 0; i < 6; i++)
727 {
728 __asm("NOP");
729 }
730 SET_BIT(RCC->CFGR, RCC_CFGR_STOPHSI);
731 }
732
733 /**
734 * @brief Disable DIRECT_HSE
735 * @rmtoll CFGR HSESEL/STOPHSI LL_RCC_HSE_Disable
736 * @retval None
737 */
LL_RCC_DIRECT_HSE_Disable(void)738 __STATIC_INLINE void LL_RCC_DIRECT_HSE_Disable(void)
739 {
740 CLEAR_BIT(RCC->CFGR, RCC_CFGR_STOPHSI);
741 while (LL_RCC_HSI_IsReady() == 0);
742 CLEAR_BIT(RCC->CFGR, RCC_CFGR_HSESEL);
743 }
744
745 /**
746 * @brief Check if DIRECT_HSE mode is ready
747 * @rmtoll CFGR HSESEL/STOPHSI LL_RCC_DIRECT_HSE_IsEnabled
748 * @retval State of bit (1 or 0).
749 */
LL_RCC_DIRECT_HSE_IsEnabled(void)750 __STATIC_INLINE uint32_t LL_RCC_DIRECT_HSE_IsEnabled(void)
751 {
752 #if defined(RCC_CFGR_HSESEL_STATUS)
753 return ((READ_BIT(RCC->CFGR, RCC_CFGR_HSESEL_STATUS) == (RCC_CFGR_HSESEL_STATUS)) ? 1UL : 0UL);
754 #else
755 return (((READ_BIT(RCC->CFGR, RCC_CFGR_HSESEL) == (RCC_CFGR_HSESEL)) && (READ_BIT(RCC->CFGR, RCC_CFGR_STOPHSI) == (RCC_CFGR_STOPHSI))) ? 1UL : 0UL);
756 #endif
757 }
758
759 #if defined(RCC_CFGR_HSESEL_STATUS)
760 /**
761 * @brief Get the DIRECT HSE Selection Status
762 * @rmtoll CFGR HSESEL_STATUS LL_RCC_Get_DIRECT_HSESEL_Status
763 * @retval State of bit (1 or 0).
764 */
LL_RCC_Get_DIRECT_HSESEL_Status(void)765 __STATIC_INLINE uint32_t LL_RCC_Get_DIRECT_HSESEL_Status(void)
766 {
767 return ((READ_BIT(RCC->CFGR, RCC_CFGR_HSESEL_STATUS) == (RCC_CFGR_HSESEL_STATUS)) ? 1UL : 0UL);
768 }
769 #endif
770
771 /**
772 * @}
773 */
774
775 /** @defgroup RCC_LL_EF_LOCKDET_NSTOP LOCKDET_NSTOP
776 * @{
777 */
778
779 /**
780 * @brief Set LOCKDET_NSTOP time
781 * @rmtoll CR LOCKDET_NSTOP LL_RCC_LOCKDET_NSTOP_SetTime
782 * @param time This parameter can be one of the following values:
783 * @arg @ref LL_RCC_LOCKDET_NSTOP_0
784 * @arg @ref LL_RCC_LOCKDET_NSTOP_1
785 * @arg @ref LL_RCC_LOCKDET_NSTOP_2
786 * @arg @ref LL_RCC_LOCKDET_NSTOP_3
787 * @arg @ref LL_RCC_LOCKDET_NSTOP_4
788 * @arg @ref LL_RCC_LOCKDET_NSTOP_5
789 * @arg @ref LL_RCC_LOCKDET_NSTOP_6
790 * @arg @ref LL_RCC_LOCKDET_NSTOP_7
791 * @retval None
792 */
LL_RCC_LOCKDET_NSTOP_SetTime(uint32_t time)793 __STATIC_INLINE void LL_RCC_LOCKDET_NSTOP_SetTime(uint32_t time)
794 {
795 MODIFY_REG(RCC->CR, RCC_CR_LOCKDET_NSTOP, time);
796 }
797
798 /**
799 * @brief Get LOCKDET_NSTOP time
800 * @rmtoll CR LOCKDET_NSTOP LL_RCC_LOCKDET_NSTOP_GetTime
801 * @retval Returned value can be one of the following values:
802 * @arg @ref LL_RCC_LOCKDET_NSTOP_0
803 * @arg @ref LL_RCC_LOCKDET_NSTOP_1
804 * @arg @ref LL_RCC_LOCKDET_NSTOP_2
805 * @arg @ref LL_RCC_LOCKDET_NSTOP_3
806 * @arg @ref LL_RCC_LOCKDET_NSTOP_4
807 * @arg @ref LL_RCC_LOCKDET_NSTOP_5
808 * @arg @ref LL_RCC_LOCKDET_NSTOP_6
809 * @arg @ref LL_RCC_LOCKDET_NSTOP_7
810 */
LL_RCC_LOCKDET_NSTOP_GetTime(void)811 __STATIC_INLINE uint32_t LL_RCC_LOCKDET_NSTOP_GetTime(void)
812 {
813 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_LOCKDET_NSTOP));
814 }
815
816 /**
817 * @}
818 */
819
820 /** @defgroup RCC_LL_EF_LSCO LSCO
821 * @{
822 */
823
824 /**
825 * @brief Configure Low speed clock selection
826 * @rmtoll CFGR CLKSLOWSEL LL_RCC_LSCO_SetSource
827 * @param Source This parameter can be one of the following values:
828 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
829 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
830 * @arg @ref LL_RCC_LSCO_CLKSOURCE_HSI64M_DIV2048
831 * @retval None
832 */
LL_RCC_LSCO_SetSource(uint32_t Source)833 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
834 {
835 MODIFY_REG(RCC->CFGR, RCC_CFGR_CLKSLOWSEL, Source);
836 }
837
838 /**
839 * @brief Get Low speed clock selection
840 * @rmtoll CFGR CLKSLOWSEL LL_RCC_LSCO_GetSource
841 * @retval Returned value can be one of the following values:
842 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
843 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
844 * @arg @ref LL_RCC_LSCO_CLKSOURCE_HSI64M_DIV2048
845 */
LL_RCC_LSCO_GetSource(void)846 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
847 {
848 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_CLKSLOWSEL));
849 }
850
851 /**
852 * @}
853 */
854
855 /** @defgroup RCC_LL_EF_LSE LSE
856 * @{
857 */
858
859 /**
860 * @brief Enable Low Speed External (LSE) crystal.
861 * @rmtoll CR LSEON LL_RCC_LSE_Enable
862 * @retval None
863 */
LL_RCC_LSE_Enable(void)864 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
865 {
866 SET_BIT(RCC->CR, RCC_CR_LSEON);
867 }
868
869 /**
870 * @brief Disable Low Speed External (LSE) crystal.
871 * @rmtoll CR LSEON LL_RCC_LSE_Disable
872 * @retval None
873 */
LL_RCC_LSE_Disable(void)874 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
875 {
876 CLEAR_BIT(RCC->CR, RCC_CR_LSEON);
877 }
878
879 /**
880 * @brief Check if Low Speed External (LSE) crystal has been enabled or not
881 * @rmtoll CR LSEON LL_RCC_LSE_IsEnabled
882 * @retval State of bit (1 or 0).
883 */
LL_RCC_LSE_IsEnabled(void)884 __STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabled(void)
885 {
886 return ((READ_BIT(RCC->CR, RCC_CR_LSEON) == (RCC_CR_LSEON)) ? 1UL : 0UL);
887 }
888
889 /**
890 * @brief Check if LSE oscillator Ready
891 * @rmtoll CR LSERDY LL_RCC_LSE_IsReady
892 * @retval State of bit (1 or 0).
893 */
LL_RCC_LSE_IsReady(void)894 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
895 {
896 return ((READ_BIT(RCC->CR, RCC_CR_LSERDY) == (RCC_CR_LSERDY)) ? 1UL : 0UL);
897 }
898
899 /**
900 * @brief Enable external clock source (LSE bypass).
901 * @rmtoll CR LSEBYP LL_RCC_LSE_EnableBypass
902 * @retval None
903 */
LL_RCC_LSE_EnableBypass(void)904 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
905 {
906 SET_BIT(RCC->CR, RCC_CR_LSEBYP);
907 }
908
909 /**
910 * @brief Disable external clock source (LSE bypass).
911 * @rmtoll CR LSEBYP LL_RCC_LSE_DisableBypass
912 * @retval None
913 */
LL_RCC_LSE_DisableBypass(void)914 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
915 {
916 CLEAR_BIT(RCC->CR, RCC_CR_LSEBYP);
917 }
918
919 /**
920 * @brief Check if LSE bypass configuration is enabled.
921 * @rmtoll CR LSEBYP LL_RCC_LSE_IsBypassEnabled
922 * @retval State of bit (1 or 0).
923 */
LL_RCC_LSE_IsBypassEnabled(void)924 __STATIC_INLINE uint32_t LL_RCC_LSE_IsBypassEnabled(void)
925 {
926 return ((READ_BIT(RCC->CR, RCC_CR_LSEBYP) == (RCC_CR_LSEBYP)) ? 1UL : 0UL);
927 }
928
929 /**
930 * @brief Set LSE oscillator drive capability
931 * @note The oscillator is in Xtal mode when it is not in bypass mode.
932 * @rmtoll CSSWCR LSEDRV LL_RCC_LSE_SetDriveCapability
933 * @param LSEDrive This parameter can be one of the following values:
934 * @arg @ref LL_RCC_LSEDRIVE_LOW
935 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
936 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
937 * @arg @ref LL_RCC_LSEDRIVE_HIGH
938 * @retval None
939 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)940 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
941 {
942 MODIFY_REG(RCC->CSSWCR, RCC_CSSWCR_LSEDRV, LSEDrive);
943 }
944
945 /**
946 * @brief Get LSE oscillator drive capability
947 * @rmtoll CSSWCR LSEDRV LL_RCC_LSE_GetDriveCapability
948 * @retval Returned value can be one of the following values:
949 * @arg @ref LL_RCC_LSEDRIVE_LOW
950 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
951 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
952 * @arg @ref LL_RCC_LSEDRIVE_HIGH
953 */
LL_RCC_LSE_GetDriveCapability(void)954 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
955 {
956 return (uint32_t)(READ_BIT(RCC->CSSWCR, RCC_CSSWCR_LSEDRV));
957 }
958
959 /**
960 * @}
961 */
962
963 /** @defgroup RCC_LL_EF_LSI LSI
964 * @{
965 */
966
967 /**
968 * @brief Enable LSI Oscillator
969 * @rmtoll CR LSION LL_RCC_LSI_Enable
970 * @retval None
971 */
LL_RCC_LSI_Enable(void)972 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
973 {
974 SET_BIT(RCC->CR, RCC_CR_LSION);
975 }
976
977 /**
978 * @brief Disable LSI Oscillator
979 * @rmtoll CR LSION LL_RCC_LSI_Disable
980 * @retval None
981 */
LL_RCC_LSI_Disable(void)982 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
983 {
984 CLEAR_BIT(RCC->CR, RCC_CR_LSION);
985 }
986
987 /**
988 * @brief Check if LSI crystal oscillator is enabled.
989 * @rmtoll CR LSION LL_RCC_LSI_IsEnabled
990 * @retval State of bit (1 or 0).
991 */
LL_RCC_LSI_IsEnabled(void)992 __STATIC_INLINE uint32_t LL_RCC_LSI_IsEnabled(void)
993 {
994 return ((READ_BIT(RCC->CR, RCC_CR_LSION) == (RCC_CR_LSION)) ? 1UL : 0UL);
995 }
996
997 /**
998 * @brief Check if LSI is Ready
999 * @rmtoll CR LSIRDY LL_RCC_LSI_IsReady
1000 * @retval State of bit (1 or 0).
1001 */
LL_RCC_LSI_IsReady(void)1002 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1003 {
1004 return ((READ_BIT(RCC->CR, RCC_CR_LSIRDY) == (RCC_CR_LSIRDY)) ? 1UL : 0UL);
1005 }
1006
1007 /**
1008 * @brief Enable LSI trimming procedure
1009 * @rmtoll ICSCR LSITRIMEN LL_RCC_LSI_EnableTrimming
1010 * @retval None
1011 */
LL_RCC_LSI_EnableTrimming(void)1012 __STATIC_INLINE void LL_RCC_LSI_EnableTrimming(void)
1013 {
1014 SET_BIT(RCC->ICSCR, RCC_ICSCR_LSITRIMEN);
1015 }
1016
1017 /**
1018 * @brief Disable LSI trimming procedure
1019 * @rmtoll ICSCR LSITRIMEN LL_RCC_LSI_DisableTrimming
1020 * @retval None
1021 */
LL_RCC_LSI_DisableTrimming(void)1022 __STATIC_INLINE void LL_RCC_LSI_DisableTrimming(void)
1023 {
1024 CLEAR_BIT(RCC->ICSCR, RCC_ICSCR_LSITRIMEN);
1025 }
1026
1027 /**
1028 * @brief Check if LSI trimming procedure is enabled
1029 * @rmtoll ICSCR LSITRIMEN LL_RCC_LSI_IsTrimmingEnabled
1030 * @retval State of bit (1 or 0).
1031 */
LL_RCC_LSI_IsTrimmingEnabled(void)1032 __STATIC_INLINE uint32_t LL_RCC_LSI_IsTrimmingEnabled(void)
1033 {
1034 return ((READ_BIT(RCC->ICSCR, RCC_ICSCR_LSITRIMEN) == (RCC_ICSCR_LSITRIMEN)) ? 1UL : 0UL);
1035 }
1036
1037 /**
1038 * @brief Set LSI trimming value
1039 * @note After enabling the LSI oscillator and the LSI trimming procedure
1040 * the LSI trimming value is decreased from 15 to 0, till LSITRIMOK raised
1041 * @rmtoll CSSWCR LSISWBW LL_RCC_LSI_SetTrimming
1042 * @param Value Between Min_Data = 0 and Max_Data = 15
1043 * @retval None
1044 */
LL_RCC_LSI_SetTrimming(uint32_t Value)1045 __STATIC_INLINE void LL_RCC_LSI_SetTrimming(uint32_t Value)
1046 {
1047 MODIFY_REG(RCC->CSSWCR, RCC_CSSWCR_LSISWBW, Value << RCC_CSSWCR_LSISWBW_Pos);
1048 SET_BIT(RCC->CSSWCR, RCC_CSSWCR_LSISWTRIMEN);
1049 }
1050
1051 /**
1052 * @brief Get LSI trimming value
1053 * @rmtoll CSSWCR/ICSCR LSITRIM LL_RCC_LSI_GetTrimming
1054 * @retval Between Min_Data = 0 and Max_Data = 15
1055 */
LL_RCC_LSI_GetTrimming(void)1056 __STATIC_INLINE uint32_t LL_RCC_LSI_GetTrimming(void)
1057 {
1058 if (READ_BIT(RCC->CSSWCR, RCC_CSSWCR_LSISWTRIMEN))
1059 {
1060 return (uint32_t)(READ_BIT(RCC->CSSWCR, RCC_CSSWCR_LSISWBW) >> RCC_CSSWCR_LSISWBW_Pos);
1061 }
1062 else
1063 {
1064 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_LSIBW) >> RCC_ICSCR_LSIBW_Pos);
1065 }
1066 }
1067
1068 #if defined(RCC_ICSCR_LSITRIMOK)
1069 /**
1070 * @brief Check if LSI oscillator trimming is OK
1071 * @rmtoll ICSCR LSITRIMOK LL_RCC_LSI_IsTrimmed
1072 * @retval State of bit (1 or 0).
1073 */
LL_RCC_LSI_IsTrimmed(void)1074 __STATIC_INLINE uint32_t LL_RCC_LSI_IsTrimmed(void)
1075 {
1076 return ((READ_BIT(RCC->ICSCR, RCC_ICSCR_LSITRIMOK) == (RCC_ICSCR_LSITRIMOK)) ? 1UL : 0UL);
1077 }
1078 #endif
1079
1080 /**
1081 * @}
1082 */
1083
1084
1085 /** @defgroup RCC_LL_EF_System System Clock
1086 * @{
1087 */
1088
1089 /**
1090 * @brief Configure the system clock source
1091 * @rmtoll CR HSEON LL_RCC_SetSysClkSource
1092 * @param Source This parameter can be one of the following values:
1093 * @arg @ref LL_RCC_SYS_HSI
1094 * @arg @ref LL_RCC_SYS_HSE
1095 * @retval None
1096 */
LL_RCC_SetSysClkSource(uint32_t Source)1097 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1098 {
1099 if (Source == LL_RCC_SYS_HSI)
1100 {
1101 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1102 }
1103 if (Source == LL_RCC_SYS_HSE)
1104 {
1105 SET_BIT(RCC->CR, RCC_CR_HSEON);
1106 }
1107 }
1108
1109 /**
1110 * @brief Get the system clock source
1111 * @rmtoll CR HSEON LL_RCC_GetSysClkSource
1112 * @retval Returned value can be one of the following values:
1113 * @arg @ref LL_RCC_SYS_HSI
1114 * @arg @ref LL_RCC_SYS_HSE
1115 */
LL_RCC_GetSysClkSource(void)1116 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1117 {
1118 if (READ_BIT(RCC->CR, RCC_CR_HSEON))
1119 {
1120 return LL_RCC_SYS_HSE;
1121 }
1122
1123 return LL_RCC_SYS_HSI;
1124 }
1125
1126 #if defined(RCC_APB2ENR_CLKBLEDIV)
1127 /**
1128 * @brief Set the RF clock frequency
1129 * @rmtoll APB2ENR CLKBLEDIV LL_RCC_SetRFClockSource
1130 * @param Source This parameter can be one of the following values:
1131 * @arg @ref LL_RCC_RF_CLK_16M
1132 * @arg @ref LL_RCC_RF_CLK_32M
1133 * @retval None
1134 */
LL_RCC_SetRFClock(uint32_t Source)1135 __STATIC_INLINE void LL_RCC_SetRFClock(uint32_t Source)
1136 {
1137 MODIFY_REG(RCC->APB2ENR, RCC_APB2ENR_CLKBLEDIV, Source);
1138 }
1139
1140 /**
1141 * @brief Get the RF clock frequency
1142 * @rmtoll APB2ENR CLKBLEDIV LL_RCC_GetRFClockSource
1143 * @retval Returned value can be one of the following values:
1144 * @arg @ref LL_RCC_RF_CLK_16M
1145 * @arg @ref LL_RCC_RF_CLK_32M
1146 */
LL_RCC_GetRFClock(void)1147 __STATIC_INLINE uint32_t LL_RCC_GetRFClock(void)
1148 {
1149 return (uint32_t)(READ_BIT(RCC->APB2ENR, RCC_APB2ENR_CLKBLEDIV));
1150 }
1151 #endif
1152
1153 #if defined(RCC_APB2RSTR_MRBLERST)
1154 /**
1155 * @brief Check if Radio System is reset.
1156 * @rmtoll APB2RSTR MRBLERST LL_RCC_IsRFUnderReset
1157 * @retval State of bit (1 or 0).
1158 */
LL_RCC_IsRFUnderReset(void)1159 __STATIC_INLINE uint32_t LL_RCC_IsRFUnderReset(void)
1160 {
1161 return ((READ_BIT(RCC->APB2RSTR, RCC_APB2RSTR_MRBLERST) == (RCC_APB2RSTR_MRBLERST)) ? 1UL : 0UL);
1162 }
1163 #endif
1164 /**
1165 * @}
1166 */
1167
1168 /** @defgroup RCC_LL_EF_SMPS SMPS
1169 * @{
1170 */
1171
1172 /**
1173 * @brief Set SMPS prescaler
1174 * @rmtoll CFGR SMPSDIV LL_RCC_SetSMPSPrescaler
1175 * @param Prescaler This parameter can be one of the following values:
1176 * @arg @ref LL_RCC_SMPS_DIV_2
1177 * @arg @ref LL_RCC_SMPS_DIV_4
1178 * @retval None
1179 */
LL_RCC_SetSMPSPrescaler(uint32_t Prescaler)1180 __STATIC_INLINE void LL_RCC_SetSMPSPrescaler(uint32_t Prescaler)
1181 {
1182 MODIFY_REG(RCC->CFGR, RCC_CFGR_SMPSDIV, Prescaler);
1183 }
1184
1185 /**
1186 * @brief Get SMPS prescaler
1187 * @rmtoll CFGR SMPSDIV LL_RCC_GetSMPSPrescaler
1188 * @retval Returned value can be one of the following values:
1189 * @arg @ref LL_RCC_SMPS_DIV_2
1190 * @arg @ref LL_RCC_SMPS_DIV_4
1191 */
LL_RCC_GetSMPSPrescaler(void)1192 __STATIC_INLINE uint32_t LL_RCC_GetSMPSPrescaler(void)
1193 {
1194 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SMPSDIV));
1195 }
1196
1197 /**
1198 * @}
1199 */
1200
1201 #if defined(RCC_CFGR_LPUCLKSEL)
1202 /** @defgroup RCC_LL_CFGR_LPUCLK_SEL LPUART Clock Selection
1203 * @{
1204 */
1205
1206 /**
1207 * @brief Set LPUART Clock source
1208 * @rmtoll CFGR LPUCLKSEL LL_RCC_SetLPUARTClockSource
1209 * @param Source this parameter can be one of the following values:
1210 * @arg @ref LL_RCC_LPUCLKSEL_CLK16M
1211 * @arg @ref LL_RCC_LPUCLKSEL_CLKLSE
1212 * @retval None
1213 */
LL_RCC_SetLPUARTClockSource(uint32_t Source)1214 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t Source)
1215 {
1216 MODIFY_REG(RCC->CFGR, RCC_CFGR_LPUCLKSEL, Source);
1217 }
1218
1219 /**
1220 * @brief Get LPUART Clock source
1221 * @rmtoll CFGR LPUCLKSEL LL_RCC_GetLPUARTClockSource
1222 * @retval Returned value can be one of the following values:
1223 * @arg @ref LL_RCC_LPUCLKSEL_CLK16M
1224 * @arg @ref LL_RCC_LPUCLKSEL_CLKLSE
1225 */
LL_RCC_GetLPUARTClockSource(void)1226 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(void)
1227 {
1228 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_LPUCLKSEL));
1229 }
1230
1231 /**
1232 * @}
1233 */
1234 #endif /* RCC_CFGR_LPUCLKSEL */
1235
1236 /** @defgroup RCC_LL_EF_MCO_LSCO MCO/LSCO configuration
1237 * @{
1238 */
1239
1240 /**
1241 * @brief Configure MCOx
1242 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
1243 * CFGR CCOPRE LL_RCC_ConfigMCO
1244 * @param MCOSource This parameter can be one of the following values:
1245 * @arg @ref LL_RCC_MCOSOURCE_NOCLOCK
1246 * @arg @ref LL_RCC_MCOSOURCE_SYSCLK
1247 * @arg @ref LL_RCC_MCOSOURCE_HSI
1248 * @arg @ref LL_RCC_MCOSOURCE_RC64MPLL
1249 * @arg @ref LL_RCC_MCOSOURCE_HSE
1250 * @arg @ref LL_RCC_MCOSOURCE_HSI64M_DIV2048
1251 * @arg @ref LL_RCC_MCOSOURCE_SMPS
1252 * @arg @ref LL_RCC_MCOSOURCE_ADC
1253 * @param MCOPrescaler This parameter can be one of the following values:
1254 * @arg @ref LL_RCC_MCO_DIV_1
1255 * @arg @ref LL_RCC_MCO_DIV_2
1256 * @arg @ref LL_RCC_MCO_DIV_4
1257 * @arg @ref LL_RCC_MCO_DIV_8
1258 * @arg @ref LL_RCC_MCO_DIV_16
1259 * @arg @ref LL_RCC_MCO_DIV_32
1260 * @retval None
1261 */
LL_RCC_ConfigMCO(uint32_t MCOSource,uint32_t MCOPrescaler)1262 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOSource, uint32_t MCOPrescaler)
1263 {
1264 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_CCOPRE, MCOSource | MCOPrescaler);
1265 }
1266
1267 /**
1268 * @brief Configure LSCOx
1269 * @rmtoll CFGR LCOSEL LL_RCC_ConfigLSCO
1270 * @param LSCOSource This parameter can be one of the following values:
1271 * @arg @ref LL_RCC_LSCOSOURCE_NOCLOCK
1272 * @arg @ref LL_RCC_LSCOSOURCE_LSI
1273 * @arg @ref LL_RCC_LSCOSOURCE_LSE
1274 * @retval None
1275 */
LL_RCC_ConfigLSCO(uint32_t LSCOSource)1276 __STATIC_INLINE void LL_RCC_ConfigLSCO(uint32_t LSCOSource)
1277 {
1278 MODIFY_REG(RCC->CFGR, RCC_CFGR_LCOSEL, LSCOSource);
1279 }
1280
1281 #if defined(RCC_CFGR_LCOEN)
1282 /**
1283 * @brief LCO enabled on GPIA_Pin_10 also in deepstop
1284 * @rmtoll CFGR LCOEN LL_RCC_LSCOinDeepStop_Enable
1285 * @retval None
1286 */
LL_RCC_LSCOinDeepStop_Enable(void)1287 __STATIC_INLINE void LL_RCC_LSCOinDeepStop_Enable(void)
1288 {
1289 SET_BIT(RCC->CFGR, RCC_CFGR_LCOEN);
1290 }
1291
1292 /**
1293 * @brief LCO disabled on GPIA_Pin_10 also in deepstop
1294 * @rmtoll CFGR LCOEN LL_RCC_LSCOinDeepStop_Disable
1295 * @retval None
1296 */
LL_RCC_LSCOinDeepStop_Disable(void)1297 __STATIC_INLINE void LL_RCC_LSCOinDeepStop_Disable(void)
1298 {
1299 CLEAR_BIT(RCC->CFGR, RCC_CFGR_LCOEN);
1300 }
1301
1302 /**
1303 * @brief Check if the LCO is enabled on PA10 in deepstop
1304 * @rmtoll CFGR LCOEN LL_RCC_LSCOinDeepStop_IsEnabled
1305 * @retval State of bit (1 or 0).
1306 */
LL_RCC_LSCOinDeepStop_IsEnabled(void)1307 __STATIC_INLINE uint32_t LL_RCC_LSCOinDeepStop_IsEnabled(void)
1308 {
1309 return ((READ_BIT(RCC->CFGR, RCC_CFGR_LCOEN) == (RCC_CFGR_LCOEN)) ? 1UL : 0UL);
1310 }
1311 #endif
1312 /**
1313 * @}
1314 */
1315
1316
1317 #if defined( RCC_CFGR_IOBOOSTEN)
1318 /** @defgroup RCC_LL_EF_IOBOOST IOBOOSTER configuration
1319 * @{
1320 */
1321 /**
1322 * @brief IO BOOSTER enable
1323 * @rmtoll CFGR IOBOOSTEN LL_RCC_IOBOOST_Enable
1324 * @retval None
1325 */
LL_RCC_IOBOOST_Enable(void)1326 __STATIC_INLINE void LL_RCC_IOBOOST_Enable(void)
1327 {
1328 SET_BIT(RCC->CFGR, RCC_CFGR_IOBOOSTEN);
1329 }
1330
1331 /**
1332 * @brief IO BOOSTER disable
1333 * @rmtoll CFGR IOBOOSTEN LL_RCC_IOBOOST_Disable
1334 * @retval None
1335 */
LL_RCC_IOBOOST_Disable(void)1336 __STATIC_INLINE void LL_RCC_IOBOOST_Disable(void)
1337 {
1338 CLEAR_BIT(RCC->CFGR, RCC_CFGR_IOBOOSTEN);
1339 }
1340
1341 /**
1342 * @brief Check if the IO BOOSTER is enabled
1343 * @rmtoll CFGR IOBOOSTEN LL_RCC_IOBOOST_IsEnabled
1344 * @retval State of bit (1 or 0).
1345 */
LL_RCC_IOBOOST_IsEnabled(void)1346 __STATIC_INLINE uint32_t LL_RCC_IOBOOST_IsEnabled(void)
1347 {
1348 return ((READ_BIT(RCC->CFGR, RCC_CFGR_IOBOOSTEN) == (RCC_CFGR_IOBOOSTEN)) ? 1UL : 0UL);
1349 }
1350
1351 /**
1352 * @}
1353 */
1354 #endif
1355
1356 #if defined( RCC_CFGR_IOBOOSTCLKEN)
1357 /** @defgroup RCC_LL_EF_IOBOOSTCLK IOBOOSTER Clock configuration
1358 * @{
1359 */
1360
1361 /**
1362 * @brief IO BOOSTER clock enable
1363 * @rmtoll CFGR IOBOOSTCLKEN LL_RCC_IOBOOSTCLK_Enable
1364 * @retval None
1365 */
LL_RCC_IOBOOSTCLK_Enable(void)1366 __STATIC_INLINE void LL_RCC_IOBOOSTCLK_Enable(void)
1367 {
1368 SET_BIT(RCC->CFGR, RCC_CFGR_IOBOOSTCLKEN);
1369 }
1370
1371 /**
1372 * @brief IO BOOSTER clock disable
1373 * @rmtoll CFGR IOBOOSTCLKEN LL_RCC_IOBOOSTCLK_Disable
1374 * @retval None
1375 */
LL_RCC_IOBOOSTCLK_Disable(void)1376 __STATIC_INLINE void LL_RCC_IOBOOSTCLK_Disable(void)
1377 {
1378 CLEAR_BIT(RCC->CFGR, RCC_CFGR_IOBOOSTCLKEN);
1379 }
1380
1381 /**
1382 * @brief Check if the IO BOOSTER clock is enabled
1383 * @rmtoll CFGR IOBOOSTCLKEN LL_RCC_IOBOOSTCLK_IsEnabled
1384 * @retval State of bit (1 or 0).
1385 */
LL_RCC_IOBOOSTCLK_IsEnabled(void)1386 __STATIC_INLINE uint32_t LL_RCC_IOBOOSTCLK_IsEnabled(void)
1387 {
1388 return ((READ_BIT(RCC->CFGR, RCC_CFGR_IOBOOSTCLKEN) == (RCC_CFGR_IOBOOSTCLKEN)) ? 1UL : 0UL);
1389 }
1390
1391 /**
1392 * @}
1393 */
1394 #endif
1395
1396 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1397 * @{
1398 */
1399
1400 #if defined(SPI2)
1401 /**
1402 * @brief Configure SPI2I2S clock source
1403 * @rmtoll CFGR SPI2I2SCLKSEL LL_RCC_SetSPI2I2SClockSource
1404 * @param Source This parameter can be one of the following values:
1405 * @arg @ref LL_RCC_SPI2_I2S_CLK16M
1406 * @arg @ref LL_RCC_SPI2_I2S_CLK32M
1407 * @retval None
1408 */
LL_RCC_SetSPI2I2SClockSource(uint32_t Source)1409 __STATIC_INLINE void LL_RCC_SetSPI2I2SClockSource(uint32_t Source)
1410 {
1411 MODIFY_REG(RCC->CFGR, RCC_CFGR_SPI2I2SCLKSEL, Source);
1412 }
1413 #endif
1414
1415 /**
1416 * @brief Configure SPI3I2S clock source
1417 * @rmtoll CFGR SPI3I2SCLKSEL LL_RCC_SetSPI3I2SClockSource
1418 * @param Source This parameter can be one of the following values:
1419 * @arg @ref LL_RCC_SPI3_I2S_CLK16M
1420 * @arg @ref LL_RCC_SPI3_I2S_CLK32M
1421 * @arg @ref LL_RCC_SPI3_I2S_CLK64M
1422 * @retval None
1423 * @note The LL_RCC_SPI3_I2S_CLK64M is valid for STM32WB05 and STM32WB09 family
1424 */
LL_RCC_SetSPI3I2SClockSource(uint32_t Source)1425 __STATIC_INLINE void LL_RCC_SetSPI3I2SClockSource(uint32_t Source)
1426 {
1427 MODIFY_REG(RCC->CFGR, RCC_CFGR_SPI3I2SCLKSEL, Source);
1428 }
1429
1430 #if defined(SPI2)
1431 /**
1432 * @brief Get SPI2I2S clock source
1433 * @rmtoll CFGR SPI2I2SCLKSEL LL_RCC_GetSPI2I2SClockSource
1434 * @retval Returned value can be one of the following values:
1435 * @arg @ref LL_RCC_SPI2_I2S_CLK16M
1436 * @arg @ref LL_RCC_SPI2_I2S_CLK32M
1437 */
LL_RCC_GetSPI2I2SClockSource(void)1438 __STATIC_INLINE uint32_t LL_RCC_GetSPI2I2SClockSource(void)
1439 {
1440 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SPI2I2SCLKSEL));
1441 }
1442 #endif
1443
1444 /**
1445 * @brief Get SPI3I2S clock source
1446 * @rmtoll CFGR SPI3I2SCLKSEL LL_RCC_GetSPI3I2SClockSource
1447 * @retval Returned value can be one of the following values:
1448 * @arg @ref LL_RCC_SPI3_I2S_CLK16M
1449 * @arg @ref LL_RCC_SPI3_I2S_CLK32M
1450 * @arg @ref LL_RCC_SPI3_I2S_CLK64M
1451 * @note The LL_RCC_SPI3_I2S_CLK64M is valid for STM32WB05 and STM32WB09 family
1452 */
LL_RCC_GetSPI3I2SClockSource(void)1453 __STATIC_INLINE uint32_t LL_RCC_GetSPI3I2SClockSource(void)
1454 {
1455 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SPI3I2SCLKSEL));
1456 }
1457
1458 /**
1459 * @}
1460 */
1461
1462
1463 /** @defgroup RCC_LL_EF_PLL PLL
1464 * @{
1465 */
1466
1467 /**
1468 * @brief Enable RC64MPLL
1469 * @rmtoll CR HSIPLLON LL_RCC_RC64MPLL_Enable
1470 * @retval None
1471 */
LL_RCC_RC64MPLL_Enable(void)1472 __STATIC_INLINE void LL_RCC_RC64MPLL_Enable(void)
1473 {
1474 SET_BIT(RCC->CR, RCC_CR_HSIPLLON);
1475 }
1476
1477 /**
1478 * @brief Disable RC64MPLL
1479 * @note Cannot be disabled if the RC64MPLL clock is used as the system clock
1480 * @rmtoll CR HSIPLLON LL_RCC_RC64MPLL_Disable
1481 * @retval None
1482 */
LL_RCC_RC64MPLL_Disable(void)1483 __STATIC_INLINE void LL_RCC_RC64MPLL_Disable(void)
1484 {
1485 CLEAR_BIT(RCC->CR, RCC_CR_HSIPLLON);
1486 }
1487
1488 /**
1489 * @brief Check if RC64MPLL is Ready
1490 * @rmtoll CR HSIPLLRDY LL_RCC_RC64MPLL_IsReady
1491 * @retval State of bit (1 or 0).
1492 */
LL_RCC_RC64MPLL_IsReady(void)1493 __STATIC_INLINE uint32_t LL_RCC_RC64MPLL_IsReady(void)
1494 {
1495 return ((READ_BIT(RCC->CR, RCC_CR_HSIPLLRDY) == (RCC_CR_HSIPLLRDY)) ? 1UL : 0UL);
1496 }
1497
1498 /**
1499 * @brief Set RC64MPLL prescaler
1500 * @rmtoll CFGR CLKSYSDIV LL_RCC_SetRC64MPLLPrescaler
1501 * @param Prescaler This parameter can be one of the following values:
1502 * @arg @ref LL_RCC_RC64MPLL_DIV_1
1503 * @arg @ref LL_RCC_RC64MPLL_DIV_2
1504 * @arg @ref LL_RCC_RC64MPLL_DIV_4
1505 * @arg @ref LL_RCC_RC64MPLL_DIV_8
1506 * @arg @ref LL_RCC_RC64MPLL_DIV_16
1507 * @arg @ref LL_RCC_RC64MPLL_DIV_32
1508 * @arg @ref LL_RCC_RC64MPLL_DIV_64
1509 * @retval None
1510 */
LL_RCC_SetRC64MPLLPrescaler(uint32_t Prescaler)1511 __STATIC_INLINE void LL_RCC_SetRC64MPLLPrescaler(uint32_t Prescaler)
1512 {
1513 MODIFY_REG(RCC->CFGR, RCC_CFGR_CLKSYSDIV, Prescaler);
1514 }
1515
1516 /**
1517 * @brief Get RC64MPLL prescaler
1518 * @rmtoll CFGR CLKSYSDIV LL_RCC_GetRC64MPLLPrescaler
1519 * @retval Returned value can be one of the following values:
1520 * @arg @ref LL_RCC_RC64MPLL_DIV_1
1521 * @arg @ref LL_RCC_RC64MPLL_DIV_2
1522 * @arg @ref LL_RCC_RC64MPLL_DIV_4
1523 * @arg @ref LL_RCC_RC64MPLL_DIV_8
1524 * @arg @ref LL_RCC_RC64MPLL_DIV_16
1525 * @arg @ref LL_RCC_RC64MPLL_DIV_32
1526 * @arg @ref LL_RCC_RC64MPLL_DIV_64
1527 */
LL_RCC_GetRC64MPLLPrescaler(void)1528 __STATIC_INLINE uint32_t LL_RCC_GetRC64MPLLPrescaler(void)
1529 {
1530 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_CLKSYSDIV));
1531 }
1532
1533 #if defined(RCC_CFGR_CLKSYSDIV_STATUS)
1534 /**
1535 * @brief Get System Clock Prescaler Status
1536 * @rmtoll CFGR CLKSYSDIV_STATUS LL_RCC_GetCLKSYSPrescalerStatus
1537 * @retval Returned value can be one of the following values:
1538 * @arg @ref LL_RCC_RC64MPLL_DIV_1
1539 * @arg @ref LL_RCC_RC64MPLL_DIV_2
1540 * @arg @ref LL_RCC_RC64MPLL_DIV_4
1541 * @arg @ref LL_RCC_RC64MPLL_DIV_8
1542 * @arg @ref LL_RCC_RC64MPLL_DIV_16
1543 * @arg @ref LL_RCC_RC64MPLL_DIV_32
1544 * @arg @ref LL_RCC_RC64MPLL_DIV_64
1545 * @arg @ref LL_RCC_DIRECT_HSE_DIV_1
1546 * @arg @ref LL_RCC_DIRECT_HSE_DIV_2
1547 * @arg @ref LL_RCC_DIRECT_HSE_DIV_4
1548 * @arg @ref LL_RCC_DIRECT_HSE_DIV_8
1549 * @arg @ref LL_RCC_DIRECT_HSE_DIV_16
1550 * @arg @ref LL_RCC_DIRECT_HSE_DIV_32
1551 */
LL_RCC_GetCLKSYSPrescalerStatus(void)1552 __STATIC_INLINE uint32_t LL_RCC_GetCLKSYSPrescalerStatus(void)
1553 {
1554 return (uint32_t)((READ_BIT(RCC->CFGR, RCC_CFGR_CLKSYSDIV_STATUS) >> RCC_CFGR_CLKSYSDIV_STATUS_Pos) << RCC_CFGR_CLKSYSDIV_Pos);
1555 }
1556 #endif
1557
1558 /**
1559 * @brief Set DIRECT_HSE prescaler
1560 * @rmtoll CFGR CLKSYSDIV LL_RCC_SetDirectHSEPrescaler
1561 * @param Prescaler This parameter can be one of the following values:
1562 * @arg @ref LL_RCC_DIRECT_HSE_DIV_1
1563 * @arg @ref LL_RCC_DIRECT_HSE_DIV_2
1564 * @arg @ref LL_RCC_DIRECT_HSE_DIV_4
1565 * @arg @ref LL_RCC_DIRECT_HSE_DIV_8
1566 * @arg @ref LL_RCC_DIRECT_HSE_DIV_16
1567 * @arg @ref LL_RCC_DIRECT_HSE_DIV_32
1568 * @retval None
1569 */
LL_RCC_SetDirectHSEPrescaler(uint32_t Prescaler)1570 __STATIC_INLINE void LL_RCC_SetDirectHSEPrescaler(uint32_t Prescaler)
1571 {
1572 MODIFY_REG(RCC->CFGR, RCC_CFGR_CLKSYSDIV, Prescaler);
1573 }
1574
1575 /**
1576 * @brief Get DIRECT_HSE prescaler
1577 * @rmtoll CFGR CLKSYSDIV LL_RCC_GetDirectHSEPrescaler
1578 * @retval Returned value can be one of the following values:
1579 * @arg @ref LL_RCC_DIRECT_HSE_DIV_1
1580 * @arg @ref LL_RCC_DIRECT_HSE_DIV_2
1581 * @arg @ref LL_RCC_DIRECT_HSE_DIV_4
1582 * @arg @ref LL_RCC_DIRECT_HSE_DIV_8
1583 * @arg @ref LL_RCC_DIRECT_HSE_DIV_16
1584 * @arg @ref LL_RCC_DIRECT_HSE_DIV_32
1585 */
LL_RCC_GetDirectHSEPrescaler(void)1586 __STATIC_INLINE uint32_t LL_RCC_GetDirectHSEPrescaler(void)
1587 {
1588 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_CLKSYSDIV));
1589 }
1590 /**
1591 * @}
1592 */
1593
1594 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
1595 * @{
1596 */
1597
1598 /**
1599 * @brief Clear LSI ready interrupt flag
1600 * @rmtoll CIFR LSIRDYF LL_RCC_ClearFlag_LSIRDY
1601 * @retval None
1602 */
LL_RCC_ClearFlag_LSIRDY(void)1603 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
1604 {
1605 WRITE_REG(RCC->CIFR, RCC_CIFR_LSIRDYF);
1606 }
1607
1608 /**
1609 * @brief Clear LSE ready interrupt flag
1610 * @rmtoll CIFR LSERDYF LL_RCC_ClearFlag_LSERDY
1611 * @retval None
1612 */
LL_RCC_ClearFlag_LSERDY(void)1613 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
1614 {
1615 WRITE_REG(RCC->CIFR, RCC_CIFR_LSERDYF);
1616 }
1617
1618 /**
1619 * @brief Clear HSI ready interrupt flag
1620 * @rmtoll CIFR HSIRDYF LL_RCC_ClearFlag_HSIRDY
1621 * @retval None
1622 */
LL_RCC_ClearFlag_HSIRDY(void)1623 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
1624 {
1625 WRITE_REG(RCC->CIFR, RCC_CIFR_HSIRDYF);
1626 }
1627
1628 /**
1629 * @brief Clear HSE ready interrupt flag
1630 * @rmtoll CIFR HSERDYF LL_RCC_ClearFlag_HSERDY
1631 * @retval None
1632 */
LL_RCC_ClearFlag_HSERDY(void)1633 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
1634 {
1635 WRITE_REG(RCC->CIFR, RCC_CIFR_HSERDYF);
1636 }
1637
1638 /**
1639 * @brief Clear RC64MPLL ready interrupt flag
1640 * @rmtoll CIFR HSIPLLRDYF LL_RCC_ClearFlag_RC64MPLLRDY
1641 * @retval None
1642 */
LL_RCC_ClearFlag_RC64MPLLRDY(void)1643 __STATIC_INLINE void LL_RCC_ClearFlag_RC64MPLLRDY(void)
1644 {
1645 WRITE_REG(RCC->CIFR, RCC_CIFR_HSIPLLRDYF);
1646 }
1647
1648 /**
1649 * @brief Clear RC64MPLL Unlock Detection interrupt flag
1650 * @rmtoll CIFR HSIPLLUNLOCKDETF LL_RCC_ClearFlag_RC64MPLLUNLOCKDET
1651 * @retval None
1652 */
LL_RCC_ClearFlag_RC64MPLLUNLOCKDET(void)1653 __STATIC_INLINE void LL_RCC_ClearFlag_RC64MPLLUNLOCKDET(void)
1654 {
1655 WRITE_REG(RCC->CIFR, RCC_CIFR_HSIPLLUNLOCKDETF);
1656 }
1657
1658 /**
1659 * @brief Clear RTC Reset Release interrupt flag
1660 * @rmtoll CIFR RTCRSTF LL_RCC_ClearFlag_RTCRRSTREL
1661 * @retval None
1662 */
LL_RCC_ClearFlag_RTCRSTREL(void)1663 __STATIC_INLINE void LL_RCC_ClearFlag_RTCRSTREL(void)
1664 {
1665 WRITE_REG(RCC->CIFR, RCC_CIFR_RTCRSTF);
1666 }
1667
1668 /**
1669 * @brief Clear Watchdog Reset Release interrupt flag
1670 * @rmtoll CIFR WDGRSTF LL_RCC_ClearFlag_WDGRSTREL
1671 * @retval None
1672 */
LL_RCC_ClearFlag_WDGRSTREL(void)1673 __STATIC_INLINE void LL_RCC_ClearFlag_WDGRSTREL(void)
1674 {
1675 WRITE_REG(RCC->CIFR, RCC_CIFR_WDGRSTF);
1676 }
1677
1678 #if defined(RCC_CIFR_LPURSTF)
1679 /**
1680 * @brief Clear LPUART Reset Release interrupt flag
1681 * @rmtoll CIFR LPURSTF LL_RCC_ClearFlag_LPURSTREL
1682 * @retval None
1683 */
LL_RCC_ClearFlag_LPURSTREL(void)1684 __STATIC_INLINE void LL_RCC_ClearFlag_LPURSTREL(void)
1685 {
1686 WRITE_REG(RCC->CIFR, RCC_CIFR_LPURSTF);
1687 }
1688 #endif
1689
1690 /**
1691 * @brief Check if LSI ready interrupt occurred or not
1692 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
1693 * @retval State of bit (1 or 0).
1694 */
LL_RCC_IsActiveFlag_LSIRDY(void)1695 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
1696 {
1697 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
1698 }
1699
1700 /**
1701 * @brief Check if LSE ready interrupt occurred or not
1702 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
1703 * @retval State of bit (1 or 0).
1704 */
LL_RCC_IsActiveFlag_LSERDY(void)1705 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
1706 {
1707 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
1708 }
1709
1710 /**
1711 * @brief Check if HSI ready interrupt occurred or not
1712 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
1713 * @retval State of bit (1 or 0).
1714 */
LL_RCC_IsActiveFlag_HSIRDY(void)1715 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
1716 {
1717 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
1718 }
1719
1720 /**
1721 * @brief Check if HSE ready interrupt occurred or not
1722 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
1723 * @retval State of bit (1 or 0).
1724 */
LL_RCC_IsActiveFlag_HSERDY(void)1725 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
1726 {
1727 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
1728 }
1729
1730 /**
1731 * @brief Check if RC64MPLL ready interrupt occurred or not
1732 * @rmtoll CIFR HSIPLLRDYF LL_RCC_IsActiveFlag_RC64MPLLRDY
1733 * @retval State of bit (1 or 0).
1734 */
LL_RCC_IsActiveFlag_RC64MPLLRDY(void)1735 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_RC64MPLLRDY(void)
1736 {
1737 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIPLLRDYF) == (RCC_CIFR_HSIPLLRDYF)) ? 1UL : 0UL);
1738 }
1739
1740 /**
1741 * @brief Check if RC64MPLL Unlock Detection flag interrupt occurred or not
1742 * @rmtoll CIFR HSIPLLUNLOCKDETF LL_RCC_IsActiveFlag_RC64MPLLUNLOCKDET
1743 * @retval State of bit (1 or 0).
1744 */
LL_RCC_IsActiveFlag_RC64MPLLUNLOCKDET(void)1745 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_RC64MPLLUNLOCKDET(void)
1746 {
1747 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIPLLUNLOCKDETF) == (RCC_CIFR_HSIPLLUNLOCKDETF)) ? 1UL : 0UL);
1748 }
1749
1750 /**
1751 * @brief Check if RTC Reset Release flag interrupt occurred or not
1752 * @rmtoll CIFR RTCRSTF LL_RCC_IsActiveFlag_RTCRSTREL
1753 * @retval State of bit (1 or 0).
1754 */
LL_RCC_IsActiveFlag_RTCRSTREL(void)1755 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_RTCRSTREL(void)
1756 {
1757 return ((READ_BIT(RCC->CIFR, RCC_CIFR_RTCRSTF) == (RCC_CIFR_RTCRSTF)) ? 1UL : 0UL);
1758 }
1759
1760 /**
1761 * @brief Check if WDG Reset Release flag interrupt occurred or not
1762 * @rmtoll CIFR WDGRSTF LL_RCC_IsActiveFlag_WDGRSTREL
1763 * @retval State of bit (1 or 0).
1764 */
LL_RCC_IsActiveFlag_WDGRSTREL(void)1765 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WDGRSTREL(void)
1766 {
1767 return ((READ_BIT(RCC->CIFR, RCC_CIFR_WDGRSTF) == (RCC_CIFR_WDGRSTF)) ? 1UL : 0UL);
1768 }
1769
1770 #if defined(RCC_CIFR_LPURSTF)
1771 /**
1772 * @brief Check if LPUART Reset Release flag interrupt occurred or not
1773 * @rmtoll CIFR LPURSTF LL_RCC_IsActiveFlag_LPURSTREL
1774 * @retval State of bit (1 or 0).
1775 */
LL_RCC_IsActiveFlag_LPURSTREL(void)1776 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPURSTREL(void)
1777 {
1778 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LPURSTF) == (RCC_CIFR_LPURSTF)) ? 1UL : 0UL);
1779 }
1780 #endif
1781
1782
1783 /**
1784 * @brief Check if RCC flag CPU lockup reset is set or not.
1785 * @rmtoll CSR LOCKUPRSTF LL_RCC_IsActiveFlag_LOCKUPRST
1786 * @retval State of bit (1 or 0).
1787 */
LL_RCC_IsActiveFlag_LOCKUPRST(void)1788 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LOCKUPRST(void)
1789 {
1790 return ((READ_BIT(RCC->CSR, RCC_CSR_LOCKUPRSTF) == (RCC_CSR_LOCKUPRSTF)) ? 1UL : 0UL);
1791 }
1792
1793 /**
1794 * @brief Check if RCC flag Watchdog reset is set or not.
1795 * @rmtoll CSR WDGRSTF LL_RCC_IsActiveFlag_WDGRST
1796 * @retval State of bit (1 or 0).
1797 */
LL_RCC_IsActiveFlag_WDGRST(void)1798 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WDGRST(void)
1799 {
1800 return ((READ_BIT(RCC->CSR, RCC_CSR_WDGRSTF) == (RCC_CSR_WDGRSTF)) ? 1UL : 0UL);
1801 }
1802
1803 /**
1804 * @brief Check if RCC flag Software reset is set or not.
1805 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
1806 * @retval State of bit (1 or 0).
1807 */
LL_RCC_IsActiveFlag_SFTRST(void)1808 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
1809 {
1810 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
1811 }
1812
1813 /**
1814 * @brief Check if RCC flag Power-On reset is set or not.
1815 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
1816 * @retval State of bit (1 or 0).
1817 */
LL_RCC_IsActiveFlag_PORRST(void)1818 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
1819 {
1820 return ((READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)) ? 1UL : 0UL);
1821 }
1822
1823 /**
1824 * @brief Check if RCC flag NRSTn pad reset is set or not.
1825 * @rmtoll CSR PADRSTF LL_RCC_IsActiveFlag_PADRST
1826 * @retval State of bit (1 or 0).
1827 */
LL_RCC_IsActiveFlag_PADRST(void)1828 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PADRST(void)
1829 {
1830 return ((READ_BIT(RCC->CSR, RCC_CSR_PADRSTF) == (RCC_CSR_PADRSTF)) ? 1UL : 0UL);
1831 }
1832
1833 /**
1834 * @brief Set RMVF bit to clear the reset flags.
1835 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
1836 * @retval None
1837 */
LL_RCC_ClearResetFlags(void)1838 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
1839 {
1840 WRITE_REG(RCC->CSR, RCC_CSR_RMVF);
1841 }
1842
1843 /**
1844 * @}
1845 */
1846
1847 /** @defgroup RCC_LL_EF_CLK_SWITCH_Management Clock Switch Management
1848 * @{
1849 */
1850
1851 /**
1852 * @brief Set RC64MPLL prescaler to switch the clock when the MR_BLE is enabled
1853 * @rmtoll CSCMDR CLKSYSDIV_REQ LL_RCC_SwitchRC64MPLLPrescaler
1854 * @param Prescaler This parameter can be one of the following values:
1855 * @arg @ref LL_RCC_RC64MPLL_SWITCH_DIV_1
1856 * @arg @ref LL_RCC_RC64MPLL_SWITCH_DIV_2
1857 * @arg @ref LL_RCC_RC64MPLL_SWITCH_DIV_4
1858 * @retval None
1859 */
LL_RCC_SwitchRC64MPLLPrescaler(uint32_t Prescaler)1860 __STATIC_INLINE void LL_RCC_SwitchRC64MPLLPrescaler(uint32_t Prescaler)
1861 {
1862 MODIFY_REG(RCC->CSCMDR, RCC_CSCMDR_CLKSYSDIV_REQ, Prescaler);
1863 }
1864
1865 /**
1866 * @brief Request the RC64MPLL prescaler to switch the clock when the MR_BLE is enabled
1867 * @rmtoll CSCMDR REQUEST LL_RCC_RequestSwitchRC64MPLLClock
1868 * @retval None
1869 */
LL_RCC_RequestSwitchRC64MPLLClock(void)1870 __STATIC_INLINE void LL_RCC_RequestSwitchRC64MPLLClock(void)
1871 {
1872 SET_BIT(RCC->CSCMDR, RCC_CSCMDR_REQUEST);
1873 }
1874
1875 /**
1876 * @brief Get RC64MPLL clock switch status
1877 * @rmtoll CSCMDR STATUS LL_RCC_HSE_GetCapacitorTuning
1878 * @retval The Clock switch status. Possible values are:
1879 * @arg @ref LL_RCC_RC64MPLL_SWITCH_STATUS_IDLE
1880 * @arg @ref LL_RCC_RC64MPLL_SWITCH_STATUS_ONGOING
1881 * @arg @ref LL_RCC_RC64MPLL_SWITCH_STATUS_DONE
1882 */
LL_RCC_GetRC64MPLLSwitchStatus(void)1883 __STATIC_INLINE uint32_t LL_RCC_GetRC64MPLLSwitchStatus(void)
1884 {
1885 return (uint32_t)(READ_BIT(RCC->CSCMDR, RCC_CSCMDR_STATUS));
1886 }
1887
1888 /**
1889 * @brief Enable End of Switch Sequence interrupt
1890 * @rmtoll CSCMDR EOFSEQ_IE LL_RCC_EnableIT_EOFSEQ
1891 * @retval None
1892 */
LL_RCC_EnableIT_EOFSEQ(void)1893 __STATIC_INLINE void LL_RCC_EnableIT_EOFSEQ(void)
1894 {
1895 SET_BIT(RCC->CSCMDR, RCC_CSCMDR_EOFSEQ_IE);
1896 }
1897
1898 /**
1899 * @brief Disable End of Switch Sequence interrupt
1900 * @rmtoll CSCMDR EOFSEQ_IE LL_RCC_DisableIT_EOFSEQ
1901 * @retval None
1902 */
LL_RCC_DisableIT_EOFSEQ(void)1903 __STATIC_INLINE void LL_RCC_DisableIT_EOFSEQ(void)
1904 {
1905 CLEAR_BIT(RCC->CSCMDR, RCC_CSCMDR_EOFSEQ_IE);
1906 }
1907
1908 /**
1909 * @brief Checks if End of Switch Sequence interrupt source is enabled or disabled.
1910 * @rmtoll CSCMDR EOFSEQ_IE LL_RCC_IsEnabledIT_EOFSEQ
1911 * @retval State of bit (1 or 0).
1912 */
LL_RCC_IsEnabledIT_EOFSEQ(void)1913 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_EOFSEQ(void)
1914 {
1915 return ((READ_BIT(RCC->CSCMDR, RCC_CSCMDR_EOFSEQ_IE) == (RCC_CSCMDR_EOFSEQ_IE)) ? 1UL : 0UL);
1916 }
1917
1918 /**
1919 * @brief Clear End of Sequence interrupt flag
1920 * @rmtoll CSCMDR EOFSEQ_IRQ LL_RCC_ClearFlag_EOFSEQ
1921 * @retval None
1922 */
LL_RCC_ClearFlag_EOFSEQ(void)1923 __STATIC_INLINE void LL_RCC_ClearFlag_EOFSEQ(void)
1924 {
1925 WRITE_REG(RCC->CSCMDR, RCC_CSCMDR_EOFSEQ_IRQ);
1926 }
1927
1928 /**
1929 * @brief Check if End of Sequence interrupt occurred or not
1930 * @rmtoll CSCMDR EOFSEQ_IRQ LL_RCC_IsActiveFlag_EOFSEQ
1931 * @retval State of bit (1 or 0).
1932 */
LL_RCC_IsActiveFlag_EOFSEQ(void)1933 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_EOFSEQ(void)
1934 {
1935 return ((READ_BIT(RCC->CSCMDR, RCC_CSCMDR_EOFSEQ_IRQ) == (RCC_CSCMDR_EOFSEQ_IRQ)) ? 1UL : 0UL);
1936 }
1937 /**
1938 * @}
1939 */
1940
1941 /** @defgroup RCC_LL_EF_IT_Management IT Management
1942 * @{
1943 */
1944
1945 /**
1946 * @brief Enable LSI ready interrupt
1947 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
1948 * @retval None
1949 */
LL_RCC_EnableIT_LSIRDY(void)1950 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
1951 {
1952 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
1953 }
1954
1955 /**
1956 * @brief Enable LSE ready interrupt
1957 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
1958 * @retval None
1959 */
LL_RCC_EnableIT_LSERDY(void)1960 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
1961 {
1962 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
1963 }
1964
1965 /**
1966 * @brief Enable HSI ready interrupt
1967 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
1968 * @retval None
1969 */
LL_RCC_EnableIT_HSIRDY(void)1970 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
1971 {
1972 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
1973 }
1974
1975 /**
1976 * @brief Enable HSE ready interrupt
1977 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
1978 * @retval None
1979 */
LL_RCC_EnableIT_HSERDY(void)1980 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
1981 {
1982 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
1983 }
1984
1985 /**
1986 * @brief Enable RC64MPLL ready interrupt
1987 * @rmtoll CIER HSIPLLRDYIE LL_RCC_EnableIT_RC64MPLLRDY
1988 * @retval None
1989 */
LL_RCC_EnableIT_RC64MPLLRDY(void)1990 __STATIC_INLINE void LL_RCC_EnableIT_RC64MPLLRDY(void)
1991 {
1992 SET_BIT(RCC->CIER, RCC_CIER_HSIPLLRDYIE);
1993 }
1994
1995 /**
1996 * @brief Enable RC64MPLL Unlock Detection interrupt
1997 * @rmtoll CIER RCC_CIER_HSIPLLUNLOCKDETIE LL_RCC_EnableIT_RC64MPLLUNLOCKDET
1998 * @retval None
1999 */
LL_RCC_EnableIT_RC64MPLLUNLOCKDET(void)2000 __STATIC_INLINE void LL_RCC_EnableIT_RC64MPLLUNLOCKDET(void)
2001 {
2002 SET_BIT(RCC->CIER, RCC_CIER_HSIPLLUNLOCKDETIE);
2003 }
2004
2005 /**
2006 * @brief Enable RTC Reset Release interrupt
2007 * @rmtoll CIER RCC_CIER_RTCRSTIE LL_RCC_EnableIT_RTCRSTREL
2008 * @retval None
2009 */
LL_RCC_EnableIT_RTCRSTREL(void)2010 __STATIC_INLINE void LL_RCC_EnableIT_RTCRSTREL(void)
2011 {
2012 SET_BIT(RCC->CIER, RCC_CIER_RTCRSTIE);
2013 }
2014
2015 /**
2016 * @brief Enable Watchdog Reset Release interrupt
2017 * @rmtoll CIER RCC_CIER_WDGRSTIE LL_RCC_EnableIT_WDGRSTREL
2018 * @retval None
2019 */
LL_RCC_EnableIT_WDGRSTREL(void)2020 __STATIC_INLINE void LL_RCC_EnableIT_WDGRSTREL(void)
2021 {
2022 SET_BIT(RCC->CIER, RCC_CIER_WDGRSTIE);
2023 }
2024
2025 #if defined(RCC_CIER_LPURSTIE)
2026 /**
2027 * @brief Enable LPUART Reset Release interrupt
2028 * @rmtoll CIER RCC_CIER_LPURSTIE LL_RCC_EnableIT_LPURSTREL
2029 * @retval None
2030 */
LL_RCC_EnableIT_LPURSTREL(void)2031 __STATIC_INLINE void LL_RCC_EnableIT_LPURSTREL(void)
2032 {
2033 SET_BIT(RCC->CIER, RCC_CIER_LPURSTIE);
2034 }
2035 #endif
2036
2037 /**
2038 * @brief Disable LSI ready interrupt
2039 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
2040 * @retval None
2041 */
LL_RCC_DisableIT_LSIRDY(void)2042 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
2043 {
2044 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
2045 }
2046
2047 /**
2048 * @brief Disable LSE ready interrupt
2049 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
2050 * @retval None
2051 */
LL_RCC_DisableIT_LSERDY(void)2052 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
2053 {
2054 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
2055 }
2056
2057 /**
2058 * @brief Disable HSI ready interrupt
2059 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
2060 * @retval None
2061 */
LL_RCC_DisableIT_HSIRDY(void)2062 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
2063 {
2064 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
2065 }
2066
2067 /**
2068 * @brief Disable HSE ready interrupt
2069 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
2070 * @retval None
2071 */
LL_RCC_DisableIT_HSERDY(void)2072 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
2073 {
2074 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
2075 }
2076
2077 /**
2078 * @brief Disable RC64MPLL ready interrupt
2079 * @rmtoll CIER HSIPLLRDYIE LL_RCC_DisableIT_RC64MPLLRDY
2080 * @retval None
2081 */
LL_RCC_DisableIT_RC64MPLLRDY(void)2082 __STATIC_INLINE void LL_RCC_DisableIT_RC64MPLLRDY(void)
2083 {
2084 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIPLLRDYIE);
2085 }
2086
2087 /**
2088 * @brief Disable RC64MPLL Unlock Detection interrupt
2089 * @rmtoll CIER RCC_CIER_HSIPLLUNLOCKDETIE LL_RCC_DisableIT_RC64MPLLUNLOCKDET
2090 * @retval None
2091 */
LL_RCC_DisableIT_RC64MPLLUNLOCKDET(void)2092 __STATIC_INLINE void LL_RCC_DisableIT_RC64MPLLUNLOCKDET(void)
2093 {
2094 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIPLLUNLOCKDETIE);
2095 }
2096
2097 /**
2098 * @brief Disable RTC Reset Release interrupt
2099 * @rmtoll CIER RCC_CIER_RTCRSTIE LL_RCC_DisableIT_RTCRSTREL
2100 * @retval None
2101 */
LL_RCC_DisableIT_RTCRSTREL(void)2102 __STATIC_INLINE void LL_RCC_DisableIT_RTCRSTREL(void)
2103 {
2104 CLEAR_BIT(RCC->CIER, RCC_CIER_RTCRSTIE);
2105 }
2106
2107 /**
2108 * @brief Disable Watchdog Reset Release interrupt
2109 * @rmtoll CIER RCC_CIER_WDGRSTIE LL_RCC_DisableIT_WDGRSTREL
2110 * @retval None
2111 */
LL_RCC_DisableIT_WDGRSTREL(void)2112 __STATIC_INLINE void LL_RCC_DisableIT_WDGRSTREL(void)
2113 {
2114 CLEAR_BIT(RCC->CIER, RCC_CIER_WDGRSTIE);
2115 }
2116
2117 #if defined(RCC_CIER_LPURSTIE)
2118 /**
2119 * @brief Disable LPUART Reset Release interrupt
2120 * @rmtoll CIER RCC_CIER_LPURSTIE LL_RCC_DisableIT_LPURSTREL
2121 * @retval None
2122 */
LL_RCC_DisableIT_LPURSTREL(void)2123 __STATIC_INLINE void LL_RCC_DisableIT_LPURSTREL(void)
2124 {
2125 CLEAR_BIT(RCC->CIER, RCC_CIER_LPURSTIE);
2126 }
2127 #endif
2128
2129 /**
2130 * @brief Checks if LSI ready interrupt source is enabled or disabled.
2131 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
2132 * @retval State of bit (1 or 0).
2133 */
LL_RCC_IsEnabledIT_LSIRDY(void)2134 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
2135 {
2136 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
2137 }
2138
2139 /**
2140 * @brief Checks if LSE ready interrupt source is enabled or disabled.
2141 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
2142 * @retval State of bit (1 or 0).
2143 */
LL_RCC_IsEnabledIT_LSERDY(void)2144 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
2145 {
2146 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
2147 }
2148
2149 /**
2150 * @brief Checks if HSI ready interrupt source is enabled or disabled.
2151 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
2152 * @retval State of bit (1 or 0).
2153 */
LL_RCC_IsEnabledIT_HSIRDY(void)2154 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
2155 {
2156 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
2157 }
2158
2159 /**
2160 * @brief Checks if HSE ready interrupt source is enabled or disabled.
2161 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
2162 * @retval State of bit (1 or 0).
2163 */
LL_RCC_IsEnabledIT_HSERDY(void)2164 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
2165 {
2166 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
2167 }
2168
2169 /**
2170 * @brief Checks if RC64MPLL ready interrupt source is enabled or disabled.
2171 * @rmtoll CIER HSIPLLRDYIE LL_RCC_IsEnabledIT_RC64MPLLRDY
2172 * @retval State of bit (1 or 0).
2173 */
LL_RCC_IsEnabledIT_RC64MPLLRDY(void)2174 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_RC64MPLLRDY(void)
2175 {
2176 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIPLLRDYIE) == (RCC_CIER_HSIPLLRDYIE)) ? 1UL : 0UL);
2177 }
2178
2179 /**
2180 * @brief Checks if RC64MPLL Unlock Detection interrupt source is enabled or disabled.
2181 * @rmtoll CIER RCC_CIER_HSIPLLUNLOCKDETIE LL_RCC_IsEnabledIT_RC64MPLLUNLOCKDET
2182 * @retval None
2183 */
LL_RCC_IsEnabledIT_RC64MPLLUNLOCKDET(void)2184 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_RC64MPLLUNLOCKDET(void)
2185 {
2186 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIPLLUNLOCKDETIE) == (RCC_CIER_HSIPLLUNLOCKDETIE)) ? 1UL : 0UL);
2187 }
2188
2189 /**
2190 * @brief Checks if RTC Reset Release interrupt source is enabled or disabled.
2191 * @rmtoll CIER RCC_CIER_RTCRSTIE LL_RCC_IsEnabledIT_RTCRSTREL
2192 * @retval None
2193 */
LL_RCC_IsEnabledIT_RTCRSTREL(void)2194 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_RTCRSTREL(void)
2195 {
2196 return ((READ_BIT(RCC->CIER, RCC_CIER_RTCRSTIE) == (RCC_CIER_RTCRSTIE)) ? 1UL : 0UL);
2197 }
2198
2199 /**
2200 * @brief Checks if Watchdog Reset Release interrupt source is enabled or disabled.
2201 * @rmtoll CIER RCC_CIER_WDGRSTIE LL_RCC_IsEnabledIT_WDGRSTREL
2202 * @retval None
2203 */
LL_RCC_IsEnabledIT_WDGRSTREL(void)2204 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_WDGRSTREL(void)
2205 {
2206 return ((READ_BIT(RCC->CIER, RCC_CIER_WDGRSTIE) == (RCC_CIER_WDGRSTIE)) ? 1UL : 0UL);
2207 }
2208
2209 #if defined(RCC_CIER_LPURSTIE)
2210 /**
2211 * @brief Checks if LPUART Reset Release interrupt source is enabled or disabled.
2212 * @rmtoll CIER RCC_CIER_LPURSTIE LL_RCC_IsEnabledIT_LPURSTREL
2213 * @retval None
2214 */
LL_RCC_IsEnabledIT_LPURSTREL(void)2215 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LPURSTREL(void)
2216 {
2217 return ((READ_BIT(RCC->CIER, RCC_CIER_LPURSTIE) == (RCC_CIER_LPURSTIE)) ? 1UL : 0UL);
2218 }
2219 #endif
2220
2221
2222 /**
2223 * @}
2224 */
2225
2226 /** @defgroup RCC_LL_HSEPLL_BUFFER_RF External high speed clock buffer for PLL RF2G4
2227 * @{
2228 */
2229
2230 /**
2231 * @brief Enable high speed clock buffer for PLL RF2G4
2232 * @rmtoll CR HSEPLLBUFON LL_RCC_HSEPLLBUFON_Enable
2233 * @retval None
2234 */
LL_RCC_HSEPLLBUFON_Enable(void)2235 __STATIC_INLINE void LL_RCC_HSEPLLBUFON_Enable(void)
2236 {
2237 SET_BIT(RCC->CR, RCC_CR_HSEPLLBUFON);
2238 }
2239
2240 /**
2241 * @brief Disable high speed clock buffer for PLL RF2G4
2242 * @rmtoll CR HSEPLLBUFON LL_RCC_HSEPLLBUFON_Disable
2243 * @retval None
2244 */
LL_RCC_HSEPLLBUFON_Disable(void)2245 __STATIC_INLINE void LL_RCC_HSEPLLBUFON_Disable(void)
2246 {
2247 CLEAR_BIT(RCC->CR, RCC_CR_HSEPLLBUFON);
2248 }
2249
2250 /**
2251 * @brief Check if the high speed clock buffer for PLL RF2G4 is enabled.
2252 * @rmtoll CR HSEPLLBUFON LL_RCC_HSEPLLBUFON_IsEnabled
2253 * @retval State of bit (1 or 0).
2254 */
LL_RCC_HSEPLLBUFON_IsEnabled(void)2255 __STATIC_INLINE uint32_t LL_RCC_HSEPLLBUFON_IsEnabled(void)
2256 {
2257 return ((READ_BIT(RCC->CR, RCC_CR_HSEPLLBUFON) == (RCC_CR_HSEPLLBUFON)) ? 1UL : 0UL);
2258 }
2259 /**
2260 * @}
2261 */
2262
2263 #if defined(USE_FULL_LL_DRIVER)
2264 /** @defgroup RCC_LL_EF_Init De-initialization function
2265 * @{
2266 */
2267 ErrorStatus LL_RCC_DeInit(void);
2268 /**
2269 * @}
2270 */
2271
2272 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
2273 * @{
2274 */
2275 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2276 uint32_t LL_RCC_GetSMPSClockFreq(void);
2277 #if defined(RCC_CFGR_LPUCLKSEL)
2278 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
2279 #endif /* RCC_CFGR_LPUCLKSEL */
2280
2281 /**
2282 * @}
2283 */
2284 #endif /* USE_FULL_LL_DRIVER */
2285
2286 /**
2287 * @}
2288 */
2289
2290 /**
2291 * @}
2292 */
2293
2294 #endif /* defined(RCC) */
2295
2296 /**
2297 * @}
2298 */
2299
2300 #ifdef __cplusplus
2301 }
2302 #endif /* __cplusplus */
2303
2304 #endif /* STM32WB0x_LL_RCC_H */
2305
