1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32C0xx_LL_RCC_H
21 #define STM32C0xx_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32c0xx.h"
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
43 * @{
44 */
45 /**
46 * @}
47 */
48
49 /* Private constants ---------------------------------------------------------*/
50 /* Private macros ------------------------------------------------------------*/
51 #if defined(USE_FULL_LL_DRIVER)
52 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
53 * @{
54 */
55 /**
56 * @}
57 */
58 #endif /*USE_FULL_LL_DRIVER*/
59
60 /* Exported types ------------------------------------------------------------*/
61 #if defined(USE_FULL_LL_DRIVER)
62 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
63 * @{
64 */
65
66 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
67 * @{
68 */
69
70 /**
71 * @brief RCC Clocks Frequency Structure
72 */
73 typedef struct
74 {
75 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
76 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
77 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
78 } LL_RCC_ClocksTypeDef;
79
80 /**
81 * @}
82 */
83
84 /**
85 * @}
86 */
87 #endif /* USE_FULL_LL_DRIVER */
88
89 /* Exported constants --------------------------------------------------------*/
90 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
91 * @{
92 */
93
94 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
95 * @brief Defines used to adapt values of different oscillators
96 * @note These values could be modified in the user environment according to
97 * HW set-up.
98 * @{
99 */
100 #if !defined (HSE_VALUE)
101 #define HSE_VALUE 48000000U /*!< Value of the HSE oscillator in Hz */
102 #endif /* HSE_VALUE */
103
104 #if !defined (HSI_VALUE)
105 #define HSI_VALUE 48000000U /*!< Value of the HSI oscillator in Hz */
106 #endif /* HSI_VALUE */
107
108 #if !defined (LSE_VALUE)
109 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
110 #endif /* LSE_VALUE */
111
112 #if !defined (LSI_VALUE)
113 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
114 #endif /* LSI_VALUE */
115 #if !defined (EXTERNAL_CLOCK_VALUE)
116 #define EXTERNAL_CLOCK_VALUE 48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */
117 #endif /* EXTERNAL_CLOCK_VALUE */
118
119 #if defined(RCC_HSI48_SUPPORT)
120 #if !defined (HSI48_VALUE)
121 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
122 #endif /* HSI48_VALUE */
123 #endif /* RCC_HSI48_SUPPORT */
124 /**
125 * @}
126 */
127
128 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
129 * @brief Flags defines which can be used with LL_RCC_WriteReg function
130 * @{
131 */
132 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
133 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
134 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
135 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
136 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
137 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
138 #if defined(RCC_HSI48_SUPPORT)
139 #define LL_RCC_CICR_HSI48CSSC RCC_CICR_HSIUSB48RDYC /*!< HSI48 Ready Interrupt Clear */
140 #endif /* RCC_HSI48_SUPPORT */
141 /**
142 * @}
143 */
144
145 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
146 * @brief Flags defines which can be used with LL_RCC_ReadReg function
147 * @{
148 */
149 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
150 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
151 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
152 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
153 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
154 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
155 #if defined(RCC_HSI48_SUPPORT)
156 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSIUSB48RDYF /*!< HSI48 Ready Interrupt flag */
157 #endif /* RCC_HSI48_SUPPORT */
158 #define LL_RCC_CSR_LPWRRSTF RCC_CSR2_LPWRRSTF /*!< Low-Power reset flag */
159 #define LL_RCC_CSR_OBLRSTF RCC_CSR2_OBLRSTF /*!< OBL reset flag */
160 #define LL_RCC_CSR_PINRSTF RCC_CSR2_PINRSTF /*!< PIN reset flag */
161 #define LL_RCC_CSR_SFTRSTF RCC_CSR2_SFTRSTF /*!< Software Reset flag */
162 #define LL_RCC_CSR_IWDGRSTF RCC_CSR2_IWDGRSTF /*!< Independent Watchdog reset flag */
163 #define LL_RCC_CSR_WWDGRSTF RCC_CSR2_WWDGRSTF /*!< Window watchdog reset flag */
164 #define LL_RCC_CSR_PWRRSTF RCC_CSR2_PWRRSTF /*!< BOR or POR/PDR reset flag */
165 /**
166 * @}
167 */
168
169 /** @defgroup RCC_LL_EC_IT IT Defines
170 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
171 * @{
172 */
173 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
174 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
175 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
176 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
177 /**
178 * @}
179 */
180
181 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
182 * @{
183 */
184 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
185 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_CSR1_LSEDRV_0 /*!< Xtal mode medium low driving capability */
186 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR1_LSEDRV_1 /*!< Xtal mode medium high driving capability */
187 #define LL_RCC_LSEDRIVE_HIGH RCC_CSR1_LSEDRV /*!< Xtal mode higher driving capability */
188 /**
189 * @}
190 */
191
192 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
193 * @{
194 */
195 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
196 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_CSR1_LSCOSEL /*!< LSE selection for low speed clock */
197 /**
198 * @}
199 */
200
201 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
202 * @{
203 */
204 #define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */
205 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */
206 #if defined(RCC_HSI48_SUPPORT)
207 #define LL_RCC_SYS_CLKSOURCE_HSIUSB48 RCC_CFGR_SW_1 /*!< HSIUSB48 selection used as system clock */
208 #endif /* RCC_HSI48_SUPPORT */
209 #define LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection used as system clock */
210 #define LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection used as system clock */
211 /**
212 * @}
213 */
214
215 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
216 * @{
217 */
218 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */
219 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */
220 #if defined(RCC_HSI48_SUPPORT)
221 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSIUSB48 RCC_CFGR_SWS_1 /*!< HSIUSB48 used as system clock */
222 #endif /* RCC_HSI48_SUPPORT */
223 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */
224 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */
225 /**
226 * @}
227 */
228
229 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
230 * @{
231 */
232 #if defined(RCC_CR_SYSDIV)
233 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
234 #define LL_RCC_SYSCLK_DIV_2 RCC_CR_SYSDIV_0 /*!< SYSCLK divided by 2 */
235 #define LL_RCC_SYSCLK_DIV_3 RCC_CR_SYSDIV_1 /*!< SYSCLK divided by 3 */
236 #define LL_RCC_SYSCLK_DIV_4 (RCC_CR_SYSDIV_1 | RCC_CR_SYSDIV_0) /*!< SYSCLK divided by 4 */
237 #define LL_RCC_SYSCLK_DIV_5 RCC_CR_SYSDIV_2 /*!< SYSCLK divided by 5 */
238 #define LL_RCC_SYSCLK_DIV_6 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_0) /*!< SYSCLK divided by 6 */
239 #define LL_RCC_SYSCLK_DIV_7 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_1) /*!< SYSCLK divided by 7 */
240 #define LL_RCC_SYSCLK_DIV_8 (RCC_CR_SYSDIV_2 | RCC_CR_SYSDIV_1 | RCC_CR_SYSDIV_0) /*!< SYSCLK divided by 8 */
241 #else
242 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
243 #endif /* RCC_CR_SYSDIV */
244 /**
245 * @}
246 */
247
248 /** @defgroup RCC_HCLK_Clock_Source RCC HCLK Clock Source
249 * @{
250 */
251 #define LL_RCC_HCLK_DIV_1 0x00000000U /*!< HCLK not divided */
252 #define LL_RCC_HCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< HCLK divided by 2 */
253 #define LL_RCC_HCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 4 */
254 #define LL_RCC_HCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 8 */
255 #define LL_RCC_HCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 16 */
256 #define LL_RCC_HCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< HCLK divided by 64 */
257 #define LL_RCC_HCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 128 */
258 #define LL_RCC_HCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 256 */
259 #define LL_RCC_HCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 512 */
260 /**
261 * @}
262 */
263
264 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
265 * @{
266 */
267 #define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */
268 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */
269 #define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */
270 #define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */
271 #define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */
272 /**
273 * @}
274 */
275
276 /** @defgroup RCC_LL_EC_HSI_DIV HSI division factor
277 * @{
278 */
279 #define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI not divided */
280 #define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI divided by 2 */
281 #define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI divided by 4 */
282 #define LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0) /*!< HSI divided by 8 */
283 #define LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2 /*!< HSI divided by 16 */
284 #define LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0) /*!< HSI divided by 32 */
285 #define LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1) /*!< HSI divided by 64 */
286 #define LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV /*!< HSI divided by 128 */
287 /**
288 * @}
289 */
290
291 /** @defgroup RCC_LL_EC_HSIKER_DIV HSI Kernel division factor
292 * @{
293 */
294 #define LL_RCC_HSIKER_DIV_1 0x00000000U /*!< HSI kernel not divided */
295 #define LL_RCC_HSIKER_DIV_2 RCC_CR_HSIKERDIV_0 /*!< HSI kernel divided by 2 */
296 #define LL_RCC_HSIKER_DIV_3 RCC_CR_HSIKERDIV_1 /*!< HSI kernel divided by 3 */
297 #define LL_RCC_HSIKER_DIV_4 (RCC_CR_HSIKERDIV_1 | RCC_CR_HSIKERDIV_0) /*!< HSI kernel divided by 4 */
298 #define LL_RCC_HSIKER_DIV_5 RCC_CR_HSIKERDIV_2 /*!< HSI kernel divided by 5 */
299 #define LL_RCC_HSIKER_DIV_6 (RCC_CR_HSIKERDIV_2 | RCC_CR_HSIKERDIV_0) /*!< HSI kernel divided by 6 */
300 #define LL_RCC_HSIKER_DIV_7 (RCC_CR_HSIKERDIV_2 | RCC_CR_HSIKERDIV_1) /*!< HSI kernel divided by 7 */
301 #define LL_RCC_HSIKER_DIV_8 RCC_CR_HSIKERDIV /*!< HSI kernel divided by 8 */
302 /**
303 * @}
304 */
305
306 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
307 * @{
308 */
309 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
310 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
311 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
312 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
313 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
314 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
315 #if defined(RCC_HSI48_SUPPORT)
316 #define LL_RCC_MCO1SOURCE_HSIUSB48 RCC_CFGR_MCOSEL_3 /*!< HSIUSB48 selection as MCO1 source */
317 #endif /* RCC_HSI48_SUPPORT */
318 /**
319 * @}
320 */
321
322 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
323 * @{
324 */
325 #define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO1 not divided */
326 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO1 divided by 2 */
327 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO1 divided by 4 */
328 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 8 */
329 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO1 divided by 16 */
330 #define LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 32 */
331 #define LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO1 divided by 64 */
332 #define LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 128 */
333 #if defined(RCC_CFGR_MCOPRE_3)
334 #define LL_RCC_MCO1_DIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO1 divided by 256 */
335 #define LL_RCC_MCO1_DIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 512 */
336 #define LL_RCC_MCO1_DIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO1 divided by 1024 */
337 #endif /* RCC_CFGR_MCOPRE_3 */
338 /**
339 * @}
340 */
341
342 /** @defgroup RCC_LL_EC_MCO2SOURCE MCO2 SOURCE selection
343 * @{
344 */
345 #define LL_RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO2 output disabled, no clock on MCO2 */
346 #define LL_RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */
347 #define LL_RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_0| RCC_CFGR_MCO2SEL_1) /*!< HSI16 selection as MCO2 source */
348 #define LL_RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */
349 #define LL_RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSI selection as MCO2 source */
350 #define LL_RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_0|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSE selection as MCO2 source */
351 #if defined(RCC_HSI48_SUPPORT)
352 #define LL_RCC_MCO2SOURCE_HSIUSB48 RCC_CFGR_MCO2SEL_3 /*!< HSIUSB48 selection as MCO2 source */
353 #endif /* RCC_HSI48_SUPPORT */
354 /**
355 * @}
356 */
357
358 /** @defgroup RCC_LL_EC_MCO2_DIV MCO2 prescaler
359 * @{
360 */
361 #define LL_RCC_MCO2_DIV_1 0x00000000U /*!< MCO2 not divided */
362 #define LL_RCC_MCO2_DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO2 divided by 2 */
363 #define LL_RCC_MCO2_DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO2 divided by 4 */
364 #define LL_RCC_MCO2_DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 8 */
365 #define LL_RCC_MCO2_DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO2 divided by 16 */
366 #define LL_RCC_MCO2_DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 32 */
367 #define LL_RCC_MCO2_DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 64 */
368 #define LL_RCC_MCO2_DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */
369 #if defined(RCC_CFGR_MCO2PRE_3)
370 #define LL_RCC_MCO2_DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO1 divided by 256 */
371 #define LL_RCC_MCO2_DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO1 divided by 512 */
372 #define LL_RCC_MCO2_DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO1 divided by 1024 */
373 #endif /* RCC_CFGR_MCO2PRE_3 */
374 /**
375 * @}
376 */
377 #if defined(USE_FULL_LL_DRIVER)
378 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
379 * @{
380 */
381 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
382 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
383 /**
384 * @}
385 */
386 #endif /* USE_FULL_LL_DRIVER */
387
388 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
389 * @{
390 */
391 #define LL_RCC_USART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART1 clock source */
392 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
393 #define LL_RCC_USART1_CLKSOURCE_HSIKER ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSIKER clock used as USART1 clock source */
394 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
395
396 /**
397 * @}
398 */
399
400
401 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
402 * @{
403 */
404 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as I2C1 clock source */
405 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 /*!< SYSCLK clock used as I2C1 clock source */
406 #define LL_RCC_I2C1_CLKSOURCE_HSIKER RCC_CCIPR_I2C1SEL_1 /*!< HSIKER clock used as I2C1 clock source */
407 #if defined(I2C2)
408 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as I2C2 clock source */
409 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 /*!< SYSCLK clock used as I2C2 clock source */
410 #define LL_RCC_I2C2_CLKSOURCE_HSIKER RCC_CCIPR_I2C1SEL_1 /*!< HSIKER clock used as I2C2 clock source */
411 #endif /* I2C2 */
412 /**
413 * @}
414 */
415
416 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
417 * @{
418 */
419 #define LL_RCC_I2S1_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as I2S1 clock source */
420 #define LL_RCC_I2S1_CLKSOURCE_HSIKER RCC_CCIPR_I2S1SEL_1 /*!< HSIKER clock used as I2S1 clock source */
421 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CCIPR_I2S1SEL /*!< External clock used as I2S1 clock source */
422 /**
423 * @}
424 */
425
426 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
427 * @{
428 */
429 #define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */
430 #define LL_RCC_ADC_CLKSOURCE_HSIKER RCC_CCIPR_ADCSEL_1 /*!< HSIKER kernel used as ADC clock */
431 /**
432 * @}
433 */
434
435 /** @defgroup RCC_LL_EC_USARTx Peripheral USARTx get clock source
436 * @{
437 */
438 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
439 /**
440 * @}
441 */
442
443 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
444 * @{
445 */
446 #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */
447 #if defined(I2C2)
448 #define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C2 Clock source selection */
449 #endif /* I2C2 */
450 /**
451 * @}
452 */
453
454 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
455 * @{
456 */
457 #define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR_I2S1SEL /*!< I2S1 Clock source selection */
458 /**
459 * @}
460 */
461
462 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
463 * @{
464 */
465 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */
466 /**
467 * @}
468 */
469
470 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
471 * @{
472 */
473 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
474 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
475 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR1_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
476 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_CSR1_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
477 /**
478 * @}
479 */
480 #if defined(USB_DRD_FS)
481 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
482 * @{
483 */
484 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
485 #define LL_RCC_USB_CLKSOURCE_HSE RCC_CCIPR2_USBSEL /*!< HSE clock used as USB clock source */
486 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
487 * @{
488 */
489 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR2_USBSEL /*!< USB Clock source selection */
490 /**
491 * @}
492 */
493
494 /**
495 * @}
496 */
497 #endif /* USB_DRD_FS */
498 /**
499 * @}
500 */
501
502 /* Exported macro ------------------------------------------------------------*/
503 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
504 * @{
505 */
506
507 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
508 * @{
509 */
510
511 /**
512 * @brief Write a value in RCC register
513 * @param __REG__ Register to be written
514 * @param __VALUE__ Value to be written in the register
515 * @retval None
516 */
517 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__))
518
519 /**
520 * @brief Read a value in RCC register
521 * @param __REG__ Register to be read
522 * @retval Register value
523 */
524 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
525 /**
526 * @}
527 */
528
529 /**
530 * @brief Helper macro to calculate the HCLK frequency
531 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/LSE/LSI)
532 * @param __AHBPRESCALER__ This parameter can be one of the following values:
533 * @arg @ref LL_RCC_HCLK_DIV_1
534 * @arg @ref LL_RCC_HCLK_DIV_2
535 * @arg @ref LL_RCC_HCLK_DIV_4
536 * @arg @ref LL_RCC_HCLK_DIV_8
537 * @arg @ref LL_RCC_HCLK_DIV_16
538 * @arg @ref LL_RCC_HCLK_DIV_64
539 * @arg @ref LL_RCC_HCLK_DIV_128
540 * @arg @ref LL_RCC_HCLK_DIV_256
541 * @arg @ref LL_RCC_HCLK_DIV_512
542 * @retval HCLK clock frequency (in Hz)
543 */
544 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) \
545 ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__)\
546 & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
547
548 /**
549 * @brief Helper macro to calculate the PCLK1 frequency (APB1)
550 * @param __HCLKFREQ__ HCLK frequency
551 * @param __APB1PRESCALER__ This parameter can be one of the following values:
552 * @arg @ref LL_RCC_APB1_DIV_1
553 * @arg @ref LL_RCC_APB1_DIV_2
554 * @arg @ref LL_RCC_APB1_DIV_4
555 * @arg @ref LL_RCC_APB1_DIV_8
556 * @arg @ref LL_RCC_APB1_DIV_16
557 * @retval PCLK1 clock frequency (in Hz)
558 */
559 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \
560 ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos]\
561 & 0x1FU))
562
563 /**
564 * @brief Helper macro to calculate the HSISYS frequency
565 * @param __HSIDIV__ This parameter can be one of the following values:
566 * @arg @ref LL_RCC_HSI_DIV_1
567 * @arg @ref LL_RCC_HSI_DIV_2
568 * @arg @ref LL_RCC_HSI_DIV_4
569 * @arg @ref LL_RCC_HSI_DIV_8
570 * @arg @ref LL_RCC_HSI_DIV_16
571 * @arg @ref LL_RCC_HSI_DIV_32
572 * @arg @ref LL_RCC_HSI_DIV_64
573 * @arg @ref LL_RCC_HSI_DIV_128
574 * @retval HSISYS clock frequency (in Hz)
575 */
576 #define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos)))
577
578 /**
579 * @brief Helper macro to calculate the HSI Kernel frequency
580 * @param __HSIKERDIV__ This parameter can be one of the following values:
581 * @arg @ref LL_RCC_HSIKER_DIV_1
582 * @arg @ref LL_RCC_HSIKER_DIV_2
583 * @arg @ref LL_RCC_HSIKER_DIV_3
584 * @arg @ref LL_RCC_HSIKER_DIV_4
585 * @arg @ref LL_RCC_HSIKER_DIV_5
586 * @arg @ref LL_RCC_HSIKER_DIV_6
587 * @arg @ref LL_RCC_HSIKER_DIV_7
588 * @arg @ref LL_RCC_HSIKER_DIV_8
589 * @retval HSIKER clock frequency (in Hz)
590 */
591 #define __LL_RCC_CALC_HSIKER_FREQ(__HSIKERDIV__) (HSI_VALUE / (((__HSIKERDIV__)>> RCC_CR_HSIKERDIV_Pos) +1U))
592 /**
593 * @}
594 */
595
596
597 /* Exported functions --------------------------------------------------------*/
598 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
599 * @{
600 */
601
602 /** @defgroup RCC_LL_EF_HSE HSE
603 * @{
604 */
605
606 /**
607 * @brief Enable the Clock Security System.
608 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
609 * @retval None
610 */
LL_RCC_HSE_EnableCSS(void)611 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
612 {
613 SET_BIT(RCC->CR, RCC_CR_CSSON);
614 }
615
616 /**
617 * @brief Enable HSE external oscillator (HSE Bypass)
618 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
619 * @retval None
620 */
LL_RCC_HSE_EnableBypass(void)621 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
622 {
623 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
624 }
625
626 /**
627 * @brief Disable HSE external oscillator (HSE Bypass)
628 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
629 * @retval None
630 */
LL_RCC_HSE_DisableBypass(void)631 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
632 {
633 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
634 }
635
636 /**
637 * @brief Enable HSE crystal oscillator (HSE ON)
638 * @rmtoll CR HSEON LL_RCC_HSE_Enable
639 * @retval None
640 */
LL_RCC_HSE_Enable(void)641 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
642 {
643 SET_BIT(RCC->CR, RCC_CR_HSEON);
644 }
645
646 /**
647 * @brief Disable HSE crystal oscillator (HSE ON)
648 * @rmtoll CR HSEON LL_RCC_HSE_Disable
649 * @retval None
650 */
LL_RCC_HSE_Disable(void)651 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
652 {
653 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
654 }
655
656 /**
657 * @brief Check if HSE oscillator Ready
658 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
659 * @retval State of bit (1 or 0).
660 */
LL_RCC_HSE_IsReady(void)661 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
662 {
663 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
664 }
665
666 /**
667 * @}
668 */
669
670 /** @defgroup RCC_LL_EF_HSI HSI
671 * @{
672 */
673
674 /**
675 * @brief Enable HSI even in stop mode
676 * @note HSI oscillator is forced ON even in Stop mode
677 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
678 * @retval None
679 */
LL_RCC_HSI_EnableInStopMode(void)680 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
681 {
682 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
683 }
684
685 /**
686 * @brief Disable HSI in stop mode
687 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
688 * @retval None
689 */
LL_RCC_HSI_DisableInStopMode(void)690 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
691 {
692 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
693 }
694
695 /**
696 * @brief Check if HSI in stop mode is enabled
697 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
698 * @retval State of bit (1 or 0).
699 */
LL_RCC_HSI_IsEnabledInStopMode(void)700 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
701 {
702 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
703 }
704
705 /**
706 * @brief Set HSIKER divider
707 * @rmtoll CR HSIKERDIV LL_RCC_HSIKER_SetDivider
708 * @param Divider This parameter can be one of the following values:
709 * @arg @ref LL_RCC_HSIKER_DIV_1
710 * @arg @ref LL_RCC_HSIKER_DIV_2
711 * @arg @ref LL_RCC_HSIKER_DIV_3
712 * @arg @ref LL_RCC_HSIKER_DIV_4
713 * @arg @ref LL_RCC_HSIKER_DIV_5
714 * @arg @ref LL_RCC_HSIKER_DIV_6
715 * @arg @ref LL_RCC_HSIKER_DIV_7
716 * @arg @ref LL_RCC_HSIKER_DIV_8
717 * @retval None.
718 */
LL_RCC_HSIKER_SetDivider(uint32_t Divider)719 __STATIC_INLINE void LL_RCC_HSIKER_SetDivider(uint32_t Divider)
720 {
721 MODIFY_REG(RCC->CR, RCC_CR_HSIKERDIV, Divider);
722 }
723
724 /**
725 * @brief Get HSIKER divider
726 * @rmtoll CR HSIKERDIV LL_RCC_HSIKER_GetDivider
727 * @retval can be one of the following values:
728 * @arg @ref LL_RCC_HSIKER_DIV_1
729 * @arg @ref LL_RCC_HSIKER_DIV_2
730 * @arg @ref LL_RCC_HSIKER_DIV_3
731 * @arg @ref LL_RCC_HSIKER_DIV_4
732 * @arg @ref LL_RCC_HSIKER_DIV_5
733 * @arg @ref LL_RCC_HSIKER_DIV_6
734 * @arg @ref LL_RCC_HSIKER_DIV_7
735 * @arg @ref LL_RCC_HSIKER_DIV_8
736 */
LL_RCC_HSIKER_GetDivider(void)737 __STATIC_INLINE uint32_t LL_RCC_HSIKER_GetDivider(void)
738 {
739 return (READ_BIT(RCC->CR, RCC_CR_HSIKERDIV));
740 }
741
742 /**
743 * @brief Enable HSI oscillator
744 * @rmtoll CR HSION LL_RCC_HSI_Enable
745 * @retval None
746 */
LL_RCC_HSI_Enable(void)747 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
748 {
749 SET_BIT(RCC->CR, RCC_CR_HSION);
750 }
751
752
753 /**
754 * @brief Set HSI divider
755 * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider
756 * @param Divider This parameter can be one of the following values:
757 * @arg @ref LL_RCC_HSI_DIV_1
758 * @arg @ref LL_RCC_HSI_DIV_2
759 * @arg @ref LL_RCC_HSI_DIV_4
760 * @arg @ref LL_RCC_HSI_DIV_8
761 * @arg @ref LL_RCC_HSI_DIV_16
762 * @arg @ref LL_RCC_HSI_DIV_32
763 * @arg @ref LL_RCC_HSI_DIV_64
764 * @arg @ref LL_RCC_HSI_DIV_128
765 * @retval None.
766 */
LL_RCC_HSI_SetDivider(uint32_t Divider)767 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
768 {
769 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
770 }
771
772 /**
773 * @brief Get HSI divider
774 * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider
775 * @retval can be one of the following values:
776 * @arg @ref LL_RCC_HSI_DIV_1
777 * @arg @ref LL_RCC_HSI_DIV_2
778 * @arg @ref LL_RCC_HSI_DIV_4
779 * @arg @ref LL_RCC_HSI_DIV_8
780 * @arg @ref LL_RCC_HSI_DIV_16
781 * @arg @ref LL_RCC_HSI_DIV_32
782 * @arg @ref LL_RCC_HSI_DIV_64
783 * @arg @ref LL_RCC_HSI_DIV_128
784 */
LL_RCC_HSI_GetDivider(void)785 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
786 {
787 return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
788 }
789
790 /**
791 * @brief Disable HSI oscillator
792 * @rmtoll CR HSION LL_RCC_HSI_Disable
793 * @retval None
794 */
LL_RCC_HSI_Disable(void)795 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
796 {
797 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
798 }
799
800 /**
801 * @brief Check if HSI clock is ready
802 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
803 * @retval State of bit (1 or 0).
804 */
LL_RCC_HSI_IsReady(void)805 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
806 {
807 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
808 }
809
810 /**
811 * @brief Get HSI Calibration value
812 * @note When HSITRIM is written, HSICAL is updated with the sum of
813 * HSITRIM and the factory trim value
814 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
815 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
816 */
LL_RCC_HSI_GetCalibration(void)817 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
818 {
819 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
820 }
821
822 /**
823 * @brief Set HSI Calibration trimming
824 * @note user-programmable trimming value that is added to the HSICAL
825 * @note Default value is 64, which, when added to the HSICAL value,
826 * should trim the HSI to 16 MHz +/- 1 %
827 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
828 * @param Value Between Min_Data = 0 and Max_Data = 127
829 * @retval None
830 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)831 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
832 {
833 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
834 }
835
836 /**
837 * @brief Get HSI Calibration trimming
838 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
839 * @retval Between Min_Data = 0 and Max_Data = 127
840 */
LL_RCC_HSI_GetCalibTrimming(void)841 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
842 {
843 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
844 }
845
846 /**
847 * @}
848 */
849
850 #if defined(RCC_HSI48_SUPPORT)
851 /** @defgroup RCC_LL_EF_HSI48 HSI48
852 * @{
853 */
854
855 /**
856 * @brief Enable HSI48
857 * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
858 * @retval None
859 */
LL_RCC_HSI48_Enable(void)860 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
861 {
862 SET_BIT(RCC->CR, RCC_CR_HSIUSB48ON);
863 }
864
865 /**
866 * @brief Disable HSI48
867 * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
868 * @retval None
869 */
LL_RCC_HSI48_Disable(void)870 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
871 {
872 CLEAR_BIT(RCC->CR, RCC_CR_HSIUSB48ON);
873 }
874
875 /**
876 * @brief Check if HSI48 oscillator Ready
877 * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
878 * @retval State of bit (1 or 0).
879 */
LL_RCC_HSI48_IsReady(void)880 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
881 {
882 return ((READ_BIT(RCC->CR, RCC_CR_HSIUSB48RDY) == RCC_CR_HSIUSB48RDY) ? 1UL : 0UL);
883 }
884
885 /**
886 * @}
887 */
888 #endif /* RCC_HSI48_SUPPORT */
889
890 /** @defgroup RCC_LL_EF_LSE LSE
891 * @{
892 */
893
894 /**
895 * @brief Enable Low Speed External (LSE) crystal.
896 * @rmtoll CSR1 LSEON LL_RCC_LSE_Enable
897 * @retval None
898 */
LL_RCC_LSE_Enable(void)899 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
900 {
901 SET_BIT(RCC->CSR1, RCC_CSR1_LSEON);
902 }
903
904 /**
905 * @brief Disable Low Speed External (LSE) crystal.
906 * @rmtoll CSR1 LSEON LL_RCC_LSE_Disable
907 * @retval None
908 */
LL_RCC_LSE_Disable(void)909 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
910 {
911 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEON);
912 }
913
914 /**
915 * @brief Enable external clock source (LSE bypass).
916 * @rmtoll CSR1 LSEBYP LL_RCC_LSE_EnableBypass
917 * @retval None
918 */
LL_RCC_LSE_EnableBypass(void)919 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
920 {
921 SET_BIT(RCC->CSR1, RCC_CSR1_LSEBYP);
922 }
923
924 /**
925 * @brief Disable external clock source (LSE bypass).
926 * @rmtoll CSR1 LSEBYP LL_RCC_LSE_DisableBypass
927 * @retval None
928 */
LL_RCC_LSE_DisableBypass(void)929 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
930 {
931 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEBYP);
932 }
933
934 /**
935 * @brief Set LSE oscillator drive capability
936 * @note The oscillator is in Xtal mode when it is not in bypass mode.
937 * @rmtoll CSR1 LSEDRV LL_RCC_LSE_SetDriveCapability
938 * @param LSEDrive This parameter can be one of the following values:
939 * @arg @ref LL_RCC_LSEDRIVE_LOW
940 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
941 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
942 * @arg @ref LL_RCC_LSEDRIVE_HIGH
943 * @retval None
944 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)945 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
946 {
947 MODIFY_REG(RCC->CSR1, RCC_CSR1_LSEDRV, LSEDrive);
948 }
949
950 /**
951 * @brief Get LSE oscillator drive capability
952 * @rmtoll CSR1 LSEDRV LL_RCC_LSE_GetDriveCapability
953 * @retval Returned value can be one of the following values:
954 * @arg @ref LL_RCC_LSEDRIVE_LOW
955 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
956 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
957 * @arg @ref LL_RCC_LSEDRIVE_HIGH
958 */
LL_RCC_LSE_GetDriveCapability(void)959 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
960 {
961 return (uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_LSEDRV));
962 }
963
964 /**
965 * @brief Enable Clock security system on LSE.
966 * @rmtoll CSR1 LSECSSON LL_RCC_LSE_EnableCSS
967 * @retval None
968 */
LL_RCC_LSE_EnableCSS(void)969 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
970 {
971 SET_BIT(RCC->CSR1, RCC_CSR1_LSECSSON);
972 }
973
974 /**
975 * @brief Disable Clock security system on LSE.
976 * @note Clock security system can be disabled only after a LSE
977 * failure detection. In that case it MUST be disabled by software.
978 * @rmtoll CSR1 LSECSSON LL_RCC_LSE_DisableCSS
979 * @retval None
980 */
LL_RCC_LSE_DisableCSS(void)981 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
982 {
983 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSECSSON);
984 }
985
986 /**
987 * @brief Check if LSE oscillator Ready
988 * @rmtoll CSR1 LSERDY LL_RCC_LSE_IsReady
989 * @retval State of bit (1 or 0).
990 */
LL_RCC_LSE_IsReady(void)991 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
992 {
993 return ((READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == (RCC_CSR1_LSERDY)) ? 1UL : 0UL);
994 }
995
996 /**
997 * @brief Check if CSS on LSE failure Detection
998 * @rmtoll CSR1 LSECSSD LL_RCC_LSE_IsCSSDetected
999 * @retval State of bit (1 or 0).
1000 */
LL_RCC_LSE_IsCSSDetected(void)1001 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1002 {
1003 return ((READ_BIT(RCC->CSR1, RCC_CSR1_LSECSSD) == (RCC_CSR1_LSECSSD)) ? 1UL : 0UL);
1004 }
1005
1006 /**
1007 * @}
1008 */
1009
1010 /** @defgroup RCC_LL_EF_LSI LSI
1011 * @{
1012 */
1013
1014 /**
1015 * @brief Enable LSI Oscillator
1016 * @rmtoll CSR2 LSION LL_RCC_LSI_Enable
1017 * @retval None
1018 */
LL_RCC_LSI_Enable(void)1019 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1020 {
1021 SET_BIT(RCC->CSR2, RCC_CSR2_LSION);
1022 }
1023
1024 /**
1025 * @brief Disable LSI Oscillator
1026 * @rmtoll CSR2 LSION LL_RCC_LSI_Disable
1027 * @retval None
1028 */
LL_RCC_LSI_Disable(void)1029 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1030 {
1031 CLEAR_BIT(RCC->CSR2, RCC_CSR2_LSION);
1032 }
1033
1034 /**
1035 * @brief Check if LSI is Ready
1036 * @rmtoll CSR2 LSIRDY LL_RCC_LSI_IsReady
1037 * @retval State of bit (1 or 0).
1038 */
LL_RCC_LSI_IsReady(void)1039 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1040 {
1041 return ((READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == (RCC_CSR2_LSIRDY)) ? 1UL : 0UL);
1042 }
1043
1044 /**
1045 * @}
1046 */
1047
1048 /** @defgroup RCC_LL_EF_LSCO LSCO
1049 * @{
1050 */
1051
1052 /**
1053 * @brief Enable Low speed clock
1054 * @rmtoll CSR1 LSCOEN LL_RCC_LSCO_Enable
1055 * @retval None
1056 */
LL_RCC_LSCO_Enable(void)1057 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1058 {
1059 SET_BIT(RCC->CSR1, RCC_CSR1_LSCOEN);
1060 }
1061
1062 /**
1063 * @brief Disable Low speed clock
1064 * @rmtoll CSR1 LSCOEN LL_RCC_LSCO_Disable
1065 * @retval None
1066 */
LL_RCC_LSCO_Disable(void)1067 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1068 {
1069 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSCOEN);
1070 }
1071
1072 /**
1073 * @brief Configure Low speed clock selection
1074 * @rmtoll CSR1 LSCOSEL LL_RCC_LSCO_SetSource
1075 * @param Source This parameter can be one of the following values:
1076 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1077 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1078 * @retval None
1079 */
LL_RCC_LSCO_SetSource(uint32_t Source)1080 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
1081 {
1082 MODIFY_REG(RCC->CSR1, RCC_CSR1_LSCOSEL, Source);
1083 }
1084
1085 /**
1086 * @brief Get Low speed clock selection
1087 * @rmtoll CSR1 LSCOSEL LL_RCC_LSCO_GetSource
1088 * @retval Returned value can be one of the following values:
1089 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1090 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1091 */
LL_RCC_LSCO_GetSource(void)1092 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
1093 {
1094 return (uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_LSCOSEL));
1095 }
1096
1097 /**
1098 * @}
1099 */
1100
1101 /** @defgroup RCC_LL_EF_System System
1102 * @{
1103 */
1104
1105 /**
1106 * @brief Configure the system clock source
1107 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1108 * @param Source This parameter can be one of the following values:
1109 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1110 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1111 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSIUSB48 (*)
1112 * @arg @ref LL_RCC_SYS_CLKSOURCE_LSI
1113 * @arg @ref LL_RCC_SYS_CLKSOURCE_LSE
1114 * @note (*) peripheral not available on all devices
1115 * @retval None
1116 */
LL_RCC_SetSysClkSource(uint32_t Source)1117 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1118 {
1119 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1120 }
1121
1122 /**
1123 * @brief Get the system clock source
1124 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1125 * @retval Returned value can be one of the following values:
1126 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1127 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1128 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSIUSB48 (*)
1129 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI
1130 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE
1131 * @note (*) peripheral not available on all devices
1132 */
LL_RCC_GetSysClkSource(void)1133 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1134 {
1135 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1136 }
1137
1138 #if defined(RCC_CR_SYSDIV)
1139 /**
1140 * @brief Set SYS DIV
1141 * @rmtoll CR SYSDIV LL_RCC_SetSYSDivider
1142 * @param Divider This parameter can be one of the following values:
1143 * @arg @ref LL_RCC_SYSCLK_DIV_1
1144 * @arg @ref LL_RCC_SYSCLK_DIV_2
1145 * @arg @ref LL_RCC_SYSCLK_DIV_3
1146 * @arg @ref LL_RCC_SYSCLK_DIV_4
1147 * @arg @ref LL_RCC_SYSCLK_DIV_5
1148 * @arg @ref LL_RCC_SYSCLK_DIV_6
1149 * @arg @ref LL_RCC_SYSCLK_DIV_7
1150 * @arg @ref LL_RCC_SYSCLK_DIV_8
1151 * @retval None
1152 */
LL_RCC_SetSYSDivider(uint32_t Divider)1153 __STATIC_INLINE void LL_RCC_SetSYSDivider(uint32_t Divider)
1154 {
1155 MODIFY_REG(RCC->CR, RCC_CR_SYSDIV, Divider);
1156 }
1157 #endif /* RCC_CR_SYSDIV */
1158
1159 /**
1160 * @brief Set AHB prescaler
1161 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1162 * @param Prescaler This parameter can be one of the following values:
1163 * @arg @ref LL_RCC_SYSCLK_DIV_1
1164 * @arg @ref LL_RCC_SYSCLK_DIV_2
1165 * @arg @ref LL_RCC_SYSCLK_DIV_4
1166 * @arg @ref LL_RCC_SYSCLK_DIV_8
1167 * @arg @ref LL_RCC_SYSCLK_DIV_16
1168 * @arg @ref LL_RCC_SYSCLK_DIV_64
1169 * @arg @ref LL_RCC_SYSCLK_DIV_128
1170 * @arg @ref LL_RCC_SYSCLK_DIV_256
1171 * @arg @ref LL_RCC_SYSCLK_DIV_512
1172 * @retval None
1173 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1174 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1175 {
1176 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1177 }
1178
1179 /**
1180 * @brief Set APB1 prescaler
1181 * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler
1182 * @param Prescaler This parameter can be one of the following values:
1183 * @arg @ref LL_RCC_APB1_DIV_1
1184 * @arg @ref LL_RCC_APB1_DIV_2
1185 * @arg @ref LL_RCC_APB1_DIV_4
1186 * @arg @ref LL_RCC_APB1_DIV_8
1187 * @arg @ref LL_RCC_APB1_DIV_16
1188 * @retval None
1189 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1190 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1191 {
1192 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
1193 }
1194
1195 /**
1196 * @brief Set HSI48 division factor
1197 * @rmtoll CR HSIDIV LL_RCC_SetHSIDiv
1198 * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
1199 * system clock source.
1200 * @param HSIDiv This parameter can be one of the following values:
1201 * @arg @ref LL_RCC_HSI_DIV_1
1202 * @arg @ref LL_RCC_HSI_DIV_2
1203 * @arg @ref LL_RCC_HSI_DIV_4
1204 * @arg @ref LL_RCC_HSI_DIV_8
1205 * @arg @ref LL_RCC_HSI_DIV_16
1206 * @arg @ref LL_RCC_HSI_DIV_32
1207 * @arg @ref LL_RCC_HSI_DIV_64
1208 * @arg @ref LL_RCC_HSI_DIV_128
1209 * @retval None
1210 */
LL_RCC_SetHSIDiv(uint32_t HSIDiv)1211 __STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv)
1212 {
1213 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv);
1214 }
1215
1216 /**
1217 * @brief Set HSIKER division factor
1218 * @rmtoll CR HSIKERDIV LL_RCC_SetHSIKERDiv
1219 * @param HSIKERDiv This parameter can be one of the following values:
1220 * @arg @ref LL_RCC_HSIKER_DIV_1
1221 * @arg @ref LL_RCC_HSIKER_DIV_2
1222 * @arg @ref LL_RCC_HSIKER_DIV_3
1223 * @arg @ref LL_RCC_HSIKER_DIV_4
1224 * @arg @ref LL_RCC_HSIKER_DIV_5
1225 * @arg @ref LL_RCC_HSIKER_DIV_6
1226 * @arg @ref LL_RCC_HSIKER_DIV_7
1227 * @arg @ref LL_RCC_HSIKER_DIV_8
1228 * @retval None
1229 */
LL_RCC_SetHSIKERDiv(uint32_t HSIKERDiv)1230 __STATIC_INLINE void LL_RCC_SetHSIKERDiv(uint32_t HSIKERDiv)
1231 {
1232 MODIFY_REG(RCC->CR, RCC_CR_HSIKERDIV, HSIKERDiv);
1233 }
1234
1235 #if defined(RCC_CR_SYSDIV)
1236 /**
1237 * @brief Get SYS divider
1238 * @rmtoll CR SYSDIV LL_RCC_GetSYSDivider
1239 * @retval Returned value can be one of the following values:
1240 * @arg @ref LL_RCC_SYSCLK_DIV_1
1241 * @arg @ref LL_RCC_SYSCLK_DIV_2
1242 * @arg @ref LL_RCC_SYSCLK_DIV_3
1243 * @arg @ref LL_RCC_SYSCLK_DIV_4
1244 * @arg @ref LL_RCC_SYSCLK_DIV_5
1245 * @arg @ref LL_RCC_SYSCLK_DIV_6
1246 * @arg @ref LL_RCC_SYSCLK_DIV_7
1247 * @arg @ref LL_RCC_SYSCLK_DIV_8
1248 */
LL_RCC_GetSYSDivider(void)1249 __STATIC_INLINE uint32_t LL_RCC_GetSYSDivider(void)
1250 {
1251 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_SYSDIV));
1252 }
1253 #endif /* RCC_CR_SYSDIV */
1254
1255 /**
1256 * @brief Get AHB prescaler
1257 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1258 * @retval Returned value can be one of the following values:
1259 * @arg @ref LL_RCC_SYSCLK_DIV_1
1260 * @arg @ref LL_RCC_SYSCLK_DIV_2
1261 * @arg @ref LL_RCC_SYSCLK_DIV_4
1262 * @arg @ref LL_RCC_SYSCLK_DIV_8
1263 * @arg @ref LL_RCC_SYSCLK_DIV_16
1264 * @arg @ref LL_RCC_SYSCLK_DIV_64
1265 * @arg @ref LL_RCC_SYSCLK_DIV_128
1266 * @arg @ref LL_RCC_SYSCLK_DIV_256
1267 * @arg @ref LL_RCC_SYSCLK_DIV_512
1268 */
LL_RCC_GetAHBPrescaler(void)1269 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1270 {
1271 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1272 }
1273
1274 /**
1275 * @brief Get APB1 prescaler
1276 * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler
1277 * @retval Returned value can be one of the following values:
1278 * @arg @ref LL_RCC_APB1_DIV_1
1279 * @arg @ref LL_RCC_APB1_DIV_2
1280 * @arg @ref LL_RCC_APB1_DIV_4
1281 * @arg @ref LL_RCC_APB1_DIV_8
1282 * @arg @ref LL_RCC_APB1_DIV_16
1283 */
LL_RCC_GetAPB1Prescaler(void)1284 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1285 {
1286 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
1287 }
1288
1289 /**
1290 * @brief Get HSI48 Division factor
1291 * @rmtoll CR HSIDIV LL_RCC_GetHSIDiv
1292 * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
1293 * system clock source.
1294 * @retval Returned value can be one of the following values:
1295 * @arg @ref LL_RCC_HSI_DIV_1
1296 * @arg @ref LL_RCC_HSI_DIV_2
1297 * @arg @ref LL_RCC_HSI_DIV_4
1298 * @arg @ref LL_RCC_HSI_DIV_8
1299 * @arg @ref LL_RCC_HSI_DIV_16
1300 * @arg @ref LL_RCC_HSI_DIV_32
1301 * @arg @ref LL_RCC_HSI_DIV_64
1302 * @arg @ref LL_RCC_HSI_DIV_128
1303 */
LL_RCC_GetHSIDiv(void)1304 __STATIC_INLINE uint32_t LL_RCC_GetHSIDiv(void)
1305 {
1306 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV));
1307 }
1308 /**
1309 * @}
1310 */
1311
1312 /** @defgroup RCC_LL_EF_MCO MCO
1313 * @{
1314 */
1315
1316 /**
1317 * @brief Configure MCOx
1318 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
1319 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
1320 * CFGR MCO2 LL_RCC_ConfigMCO\n
1321 * CFGR MCO2PRE LL_RCC_ConfigMCO
1322 * @param MCOxSource This parameter can be one of the following values:
1323 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1324 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1325 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1326 * @arg @ref LL_RCC_MCO1SOURCE_HSIUSB48 (*)
1327 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1328 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1329 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1330 * @param MCOxPrescaler This parameter can be one of the following values:
1331 * @arg @ref LL_RCC_MCO1_DIV_1
1332 * @arg @ref LL_RCC_MCO1_DIV_2
1333 * @arg @ref LL_RCC_MCO1_DIV_4
1334 * @arg @ref LL_RCC_MCO1_DIV_8
1335 * @arg @ref LL_RCC_MCO1_DIV_16
1336 * @arg @ref LL_RCC_MCO1_DIV_32
1337 * @arg @ref LL_RCC_MCO1_DIV_64
1338 * @arg @ref LL_RCC_MCO1_DIV_128
1339 * @arg @ref LL_RCC_MCO1_DIV_256 (*)
1340 * @arg @ref LL_RCC_MCO1_DIV_512 (*)
1341 * @arg @ref LL_RCC_MCO1_DIV_1024 (*)
1342 * @note (*) not available on all devices
1343 * @retval None
1344 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1345 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1346 {
1347 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1348 }
1349
1350 /**
1351 * @}
1352 */
1353
1354 /** @defgroup RCC_LL_EF_MCO2 MCO2
1355 * @{
1356 */
1357
1358 /**
1359 * @brief Configure MCO2
1360 * @rmtoll CFGR MCO2SEL LL_RCC_ConfigMCO2\n
1361 * CFGR MCO2PRE LL_RCC_ConfigMCO2
1362 * @note feature not available in all devices.
1363 * @param MCOxSource This parameter can be one of the following values:
1364 * @arg @ref LL_RCC_MCO2SOURCE_NOCLOCK
1365 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
1366 * @arg @ref LL_RCC_MCO2SOURCE_HSI
1367 * @arg @ref LL_RCC_MCO2SOURCE_HSIUSB48 (*)
1368 * @arg @ref LL_RCC_MCO2SOURCE_HSE
1369 * @arg @ref LL_RCC_MCO2SOURCE_LSI
1370 * @arg @ref LL_RCC_MCO2SOURCE_LSE
1371 * @param MCOxPrescaler This parameter can be one of the following values:
1372 * @arg @ref LL_RCC_MCO2_DIV_1
1373 * @arg @ref LL_RCC_MCO2_DIV_2
1374 * @arg @ref LL_RCC_MCO2_DIV_4
1375 * @arg @ref LL_RCC_MCO2_DIV_8
1376 * @arg @ref LL_RCC_MCO2_DIV_16
1377 * @arg @ref LL_RCC_MCO2_DIV_32
1378 * @arg @ref LL_RCC_MCO2_DIV_64
1379 * @arg @ref LL_RCC_MCO2_DIV_128
1380 * @arg @ref LL_RCC_MCO2_DIV_256 (*)
1381 * @arg @ref LL_RCC_MCO2_DIV_512 (*)
1382 * @arg @ref LL_RCC_MCO2_DIV_1024 (*)
1383 * @note (*) not available on all devices
1384 * @retval None
1385 */
LL_RCC_ConfigMCO2(uint32_t MCOxSource,uint32_t MCOxPrescaler)1386 __STATIC_INLINE void LL_RCC_ConfigMCO2(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1387 {
1388 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE, MCOxSource | MCOxPrescaler);
1389 }
1390
1391 /**
1392 * @}
1393 */
1394 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1395 * @{
1396 */
1397
1398 /**
1399 * @brief Configure USARTx clock source
1400 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
1401 * @param USARTxSource This parameter can be one of the following values:
1402 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
1403 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1404 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSIKER
1405 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1406 * @retval None
1407 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1408 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1409 {
1410 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
1411 }
1412
1413 /**
1414 * @brief Configure I2Cx clock source
1415 * @rmtoll CCIPR I2C1SEL LL_RCC_SetI2CClockSource
1416 * @param I2CxSource This parameter can be one of the following values:
1417 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1418 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1419 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSIKER
1420 * @retval None
1421 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1422 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1423 {
1424 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, I2CxSource);
1425 }
1426
1427 /**
1428 * @brief Configure ADC clock source
1429 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
1430 * @param ADCxSource This parameter can be one of the following values:
1431 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
1432 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSIKER
1433 * @retval None
1434 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)1435 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1436 {
1437 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
1438 }
1439
1440 /**
1441 * @brief Configure I2Sx clock source
1442 * @rmtoll CCIPR I2S1SEL LL_RCC_SetI2SClockSource
1443 * @param I2SxSource This parameter can be one of the following values:
1444 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
1445 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
1446 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSIKER
1447 * @retval None
1448 */
LL_RCC_SetI2SClockSource(uint32_t I2SxSource)1449 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
1450 {
1451 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, I2SxSource);
1452 }
1453
1454 #if defined (USB_DRD_FS)
1455 /**
1456 * @brief Configure USB clock source
1457 * @rmtoll CCIPR2 CK48MSEL LL_RCC_SetUSBClockSource
1458 * @param USBxSource This parameter can be one of the following values:
1459 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
1460 * @arg @ref LL_RCC_USB_CLKSOURCE_HSE
1461 *
1462 * (*) value not defined in all devices.
1463 * @retval None
1464 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)1465 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
1466 {
1467 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, USBxSource);
1468 }
1469 #endif /* USB_DRD_FS */
1470
1471 /**
1472 * @brief Get USARTx clock source
1473 * @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource
1474 * @param USARTx This parameter can be one of the following values:
1475 * @arg @ref LL_RCC_USART1_CLKSOURCE
1476 * @retval Returned value can be one of the following values:
1477 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
1478 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1479 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSIKER
1480 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1481 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)1482 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1483 {
1484 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
1485 }
1486
1487 /**
1488 * @brief Get I2Cx clock source
1489 * @rmtoll CCIPR I2C1SEL LL_RCC_GetI2CClockSource
1490 * @param I2Cx This parameter can be one of the following values:
1491 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1492 * @retval Returned value can be one of the following values:
1493 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1494 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1495 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSIKER
1496 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)1497 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
1498 {
1499 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Cx));
1500 }
1501
1502 /**
1503 * @brief Get ADCx clock source
1504 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
1505 * @param ADCx This parameter can be one of the following values:
1506 * @arg @ref LL_RCC_ADC_CLKSOURCE
1507 * @retval Returned value can be one of the following values:
1508 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSIKER
1509 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
1510 */
LL_RCC_GetADCClockSource(uint32_t ADCx)1511 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1512 {
1513 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
1514 }
1515
1516 /**
1517 * @brief Get I2Sx clock source
1518 * @rmtoll CCIPR I2S LL_RCC_GetI2SClockSource
1519 * @param I2Sx This parameter can be one of the following values:
1520 * @arg @ref LL_RCC_I2S1_CLKSOURCE
1521 * @retval Returned value can be one of the following values:
1522 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
1523 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
1524 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSIKER
1525 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)1526 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
1527 {
1528 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
1529 }
1530
1531 #if defined (USB_DRD_FS)
1532 /**
1533 * @brief Get USBx clock source
1534 * @rmtoll CCIPR2 CK48MSEL LL_RCC_GetUSBClockSource
1535 * @param USBx This parameter can be one of the following values:
1536 * @arg @ref LL_RCC_USB_CLKSOURCE
1537 * @retval Returned value can be one of the following values:
1538 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
1539 */
LL_RCC_GetUSBClockSource(uint32_t USBx)1540 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
1541 {
1542 return (uint32_t)(READ_BIT(RCC->CCIPR2, USBx));
1543 }
1544 #endif /* USB_DRD_FS */
1545
1546 /**
1547 * @}
1548 */
1549
1550 /** @defgroup RCC_LL_EF_RTC RTC
1551 * @{
1552 */
1553
1554 /**
1555 * @brief Set RTC Clock Source
1556 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
1557 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
1558 * set). The BDRST bit can be used to reset them.
1559 * @rmtoll CSR1 RTCSEL LL_RCC_SetRTCClockSource
1560 * @param Source This parameter can be one of the following values:
1561 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1562 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1563 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1564 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
1565 * @retval None
1566 */
LL_RCC_SetRTCClockSource(uint32_t Source)1567 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
1568 {
1569 MODIFY_REG(RCC->CSR1, RCC_CSR1_RTCSEL, Source);
1570 }
1571
1572 /**
1573 * @brief Get RTC Clock Source
1574 * @rmtoll CSR1 RTCSEL LL_RCC_GetRTCClockSource
1575 * @retval Returned value can be one of the following values:
1576 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1577 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1578 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1579 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
1580 */
LL_RCC_GetRTCClockSource(void)1581 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
1582 {
1583 return (uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL));
1584 }
1585
1586 /**
1587 * @brief Enable RTC
1588 * @rmtoll CSR1 RTCEN LL_RCC_EnableRTC
1589 * @retval None
1590 */
LL_RCC_EnableRTC(void)1591 __STATIC_INLINE void LL_RCC_EnableRTC(void)
1592 {
1593 SET_BIT(RCC->CSR1, RCC_CSR1_RTCEN);
1594 }
1595
1596 /**
1597 * @brief Disable RTC
1598 * @rmtoll CSR1 RTCEN LL_RCC_DisableRTC
1599 * @retval None
1600 */
LL_RCC_DisableRTC(void)1601 __STATIC_INLINE void LL_RCC_DisableRTC(void)
1602 {
1603 CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCEN);
1604 }
1605
1606 /**
1607 * @brief Check if RTC has been enabled or not
1608 * @rmtoll CSR1 RTCEN LL_RCC_IsEnabledRTC
1609 * @retval State of bit (1 or 0).
1610 */
LL_RCC_IsEnabledRTC(void)1611 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
1612 {
1613 return ((READ_BIT(RCC->CSR1, RCC_CSR1_RTCEN) == (RCC_CSR1_RTCEN)) ? 1UL : 0UL);
1614 }
1615
1616 /**
1617 * @brief Force the Backup domain reset
1618 * @rmtoll CSR1 RTCRST LL_RCC_ForceBackupDomainReset
1619 * @retval None
1620 */
LL_RCC_ForceBackupDomainReset(void)1621 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
1622 {
1623 SET_BIT(RCC->CSR1, RCC_CSR1_RTCRST);
1624 }
1625
1626 /**
1627 * @brief Release the Backup domain reset
1628 * @rmtoll CSR1 RTCRST LL_RCC_ReleaseBackupDomainReset
1629 * @retval None
1630 */
LL_RCC_ReleaseBackupDomainReset(void)1631 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
1632 {
1633 CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCRST);
1634 }
1635
1636 /**
1637 * @}
1638 */
1639
1640 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
1641 * @{
1642 */
1643
1644 /**
1645 * @brief Clear LSI ready interrupt flag
1646 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
1647 * @retval None
1648 */
LL_RCC_ClearFlag_LSIRDY(void)1649 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
1650 {
1651 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
1652 }
1653
1654 /**
1655 * @brief Clear LSE ready interrupt flag
1656 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
1657 * @retval None
1658 */
LL_RCC_ClearFlag_LSERDY(void)1659 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
1660 {
1661 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
1662 }
1663
1664 #if defined(RCC_HSI48_SUPPORT)
1665 /**
1666 * @brief Clear HSI48 ready interrupt flag
1667 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
1668 * @retval None
1669 */
LL_RCC_ClearFlag_HSI48RDY(void)1670 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
1671 {
1672 SET_BIT(RCC->CICR, RCC_CICR_HSIUSB48RDYC);
1673 }
1674 #endif /* RCC_HSI48_SUPPORT */
1675
1676 /**
1677 * @brief Clear HSI ready interrupt flag
1678 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
1679 * @retval None
1680 */
LL_RCC_ClearFlag_HSIRDY(void)1681 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
1682 {
1683 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
1684 }
1685
1686 /**
1687 * @brief Clear HSE ready interrupt flag
1688 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
1689 * @retval None
1690 */
LL_RCC_ClearFlag_HSERDY(void)1691 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
1692 {
1693 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
1694 }
1695
1696 /**
1697 * @brief Clear Clock security system interrupt flag
1698 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
1699 * @retval None
1700 */
LL_RCC_ClearFlag_HSECSS(void)1701 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
1702 {
1703 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
1704 }
1705
1706 /**
1707 * @brief Clear LSE Clock security system interrupt flag
1708 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
1709 * @retval None
1710 */
LL_RCC_ClearFlag_LSECSS(void)1711 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
1712 {
1713 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
1714 }
1715
1716 /**
1717 * @brief Check if LSI ready interrupt occurred or not
1718 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
1719 * @retval State of bit (1 or 0).
1720 */
LL_RCC_IsActiveFlag_LSIRDY(void)1721 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
1722 {
1723 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
1724 }
1725
1726 /**
1727 * @brief Check if LSE ready interrupt occurred or not
1728 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
1729 * @retval State of bit (1 or 0).
1730 */
LL_RCC_IsActiveFlag_LSERDY(void)1731 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
1732 {
1733 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
1734 }
1735
1736 #if defined(RCC_HSI48_SUPPORT)
1737 /**
1738 * @brief Check if HSI48 ready interrupt occurred or not
1739 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
1740 * @retval State of bit (1 or 0).
1741 */
LL_RCC_IsActiveFlag_HSI48RDY(void)1742 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
1743 {
1744 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIUSB48RDYF) == (RCC_CIFR_HSIUSB48RDYF)) ? 1UL : 0UL);
1745 }
1746 #endif /* RCC_HSI48_SUPPORT */
1747
1748 /**
1749 * @brief Check if HSI ready interrupt occurred or not
1750 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
1751 * @retval State of bit (1 or 0).
1752 */
LL_RCC_IsActiveFlag_HSIRDY(void)1753 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
1754 {
1755 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
1756 }
1757
1758 /**
1759 * @brief Check if HSE ready interrupt occurred or not
1760 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
1761 * @retval State of bit (1 or 0).
1762 */
LL_RCC_IsActiveFlag_HSERDY(void)1763 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
1764 {
1765 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
1766 }
1767
1768 /**
1769 * @brief Check if Clock security system interrupt occurred or not
1770 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
1771 * @retval State of bit (1 or 0).
1772 */
LL_RCC_IsActiveFlag_HSECSS(void)1773 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
1774 {
1775 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
1776 }
1777
1778 /**
1779 * @brief Check if LSE Clock security system interrupt occurred or not
1780 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
1781 * @retval State of bit (1 or 0).
1782 */
LL_RCC_IsActiveFlag_LSECSS(void)1783 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
1784 {
1785 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
1786 }
1787
1788 /**
1789 * @brief Check if RCC flag Independent Watchdog reset is set or not.
1790 * @rmtoll CSR2 IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
1791 * @retval State of bit (1 or 0).
1792 */
LL_RCC_IsActiveFlag_IWDGRST(void)1793 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
1794 {
1795 return ((READ_BIT(RCC->CSR2, RCC_CSR2_IWDGRSTF) == (RCC_CSR2_IWDGRSTF)) ? 1UL : 0UL);
1796 }
1797
1798 /**
1799 * @brief Check if RCC flag Low Power reset is set or not.
1800 * @rmtoll CSR2 LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
1801 * @retval State of bit (1 or 0).
1802 */
LL_RCC_IsActiveFlag_LPWRRST(void)1803 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
1804 {
1805 return ((READ_BIT(RCC->CSR2, RCC_CSR2_LPWRRSTF) == (RCC_CSR2_LPWRRSTF)) ? 1UL : 0UL);
1806 }
1807
1808 /**
1809 * @brief Check if RCC flag Option byte reset is set or not.
1810 * @rmtoll CSR2 OBLRSTF LL_RCC_IsActiveFlag_OBLRST
1811 * @retval State of bit (1 or 0).
1812 */
LL_RCC_IsActiveFlag_OBLRST(void)1813 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
1814 {
1815 return ((READ_BIT(RCC->CSR2, RCC_CSR2_OBLRSTF) == (RCC_CSR2_OBLRSTF)) ? 1UL : 0UL);
1816 }
1817
1818 /**
1819 * @brief Check if RCC flag Pin reset is set or not.
1820 * @rmtoll CSR2 PINRSTF LL_RCC_IsActiveFlag_PINRST
1821 * @retval State of bit (1 or 0).
1822 */
LL_RCC_IsActiveFlag_PINRST(void)1823 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
1824 {
1825 return ((READ_BIT(RCC->CSR2, RCC_CSR2_PINRSTF) == (RCC_CSR2_PINRSTF)) ? 1UL : 0UL);
1826 }
1827
1828 /**
1829 * @brief Check if RCC flag Software reset is set or not.
1830 * @rmtoll CSR2 SFTRSTF LL_RCC_IsActiveFlag_SFTRST
1831 * @retval State of bit (1 or 0).
1832 */
LL_RCC_IsActiveFlag_SFTRST(void)1833 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
1834 {
1835 return ((READ_BIT(RCC->CSR2, RCC_CSR2_SFTRSTF) == (RCC_CSR2_SFTRSTF)) ? 1UL : 0UL);
1836 }
1837
1838 /**
1839 * @brief Check if RCC flag Window Watchdog reset is set or not.
1840 * @rmtoll CSR2 WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
1841 * @retval State of bit (1 or 0).
1842 */
LL_RCC_IsActiveFlag_WWDGRST(void)1843 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
1844 {
1845 return ((READ_BIT(RCC->CSR2, RCC_CSR2_WWDGRSTF) == (RCC_CSR2_WWDGRSTF)) ? 1UL : 0UL);
1846 }
1847
1848 /**
1849 * @brief Check if RCC flag BOR or POR/PDR reset is set or not.
1850 * @rmtoll CSR2 PWRRSTF LL_RCC_IsActiveFlag_PWRRST
1851 * @retval State of bit (1 or 0).
1852 */
LL_RCC_IsActiveFlag_PWRRST(void)1853 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void)
1854 {
1855 return ((READ_BIT(RCC->CSR2, RCC_CSR2_PWRRSTF) == (RCC_CSR2_PWRRSTF)) ? 1UL : 0UL);
1856 }
1857
1858 /**
1859 * @brief Set RMVF bit to clear the reset flags.
1860 * @rmtoll CSR2 RMVF LL_RCC_ClearResetFlags
1861 * @retval None
1862 */
LL_RCC_ClearResetFlags(void)1863 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
1864 {
1865 SET_BIT(RCC->CSR2, RCC_CSR2_RMVF);
1866 }
1867
1868 /**
1869 * @}
1870 */
1871
1872 /** @defgroup RCC_LL_EF_IT_Management IT Management
1873 * @{
1874 */
1875
1876 /**
1877 * @brief Enable LSI ready interrupt
1878 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
1879 * @retval None
1880 */
LL_RCC_EnableIT_LSIRDY(void)1881 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
1882 {
1883 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
1884 }
1885
1886 /**
1887 * @brief Enable LSE ready interrupt
1888 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
1889 * @retval None
1890 */
LL_RCC_EnableIT_LSERDY(void)1891 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
1892 {
1893 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
1894 }
1895
1896 #if defined(RCC_HSI48_SUPPORT)
1897 /**
1898 * @brief Enable HSI48 ready interrupt
1899 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
1900 * @retval None
1901 */
LL_RCC_EnableIT_HSI48RDY(void)1902 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
1903 {
1904 SET_BIT(RCC->CIER, RCC_CIER_HSIUSB48RDYIE);
1905 }
1906 #endif /* RCC_HSI48_SUPPORT */
1907
1908 /**
1909 * @brief Enable HSI ready interrupt
1910 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
1911 * @retval None
1912 */
LL_RCC_EnableIT_HSIRDY(void)1913 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
1914 {
1915 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
1916 }
1917
1918 /**
1919 * @brief Enable HSE ready interrupt
1920 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
1921 * @retval None
1922 */
LL_RCC_EnableIT_HSERDY(void)1923 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
1924 {
1925 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
1926 }
1927
1928 /**
1929 * @brief Disable LSI ready interrupt
1930 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
1931 * @retval None
1932 */
LL_RCC_DisableIT_LSIRDY(void)1933 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
1934 {
1935 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
1936 }
1937
1938 /**
1939 * @brief Disable LSE ready interrupt
1940 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
1941 * @retval None
1942 */
LL_RCC_DisableIT_LSERDY(void)1943 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
1944 {
1945 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
1946 }
1947
1948 #if defined(RCC_HSI48_SUPPORT)
1949 /**
1950 * @brief Disable HSI48 ready interrupt
1951 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
1952 * @retval None
1953 */
LL_RCC_DisableIT_HSI48RDY(void)1954 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
1955 {
1956 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIUSB48RDYIE);
1957 }
1958 #endif /* RCC_HSI48_SUPPORT */
1959
1960 /**
1961 * @brief Disable HSI ready interrupt
1962 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
1963 * @retval None
1964 */
LL_RCC_DisableIT_HSIRDY(void)1965 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
1966 {
1967 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
1968 }
1969
1970 /**
1971 * @brief Disable HSE ready interrupt
1972 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
1973 * @retval None
1974 */
LL_RCC_DisableIT_HSERDY(void)1975 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
1976 {
1977 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
1978 }
1979
1980
1981 /**
1982 * @brief Checks if LSI ready interrupt source is enabled or disabled.
1983 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
1984 * @retval State of bit (1 or 0).
1985 */
LL_RCC_IsEnabledIT_LSIRDY(void)1986 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
1987 {
1988 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
1989 }
1990
1991 /**
1992 * @brief Checks if LSE ready interrupt source is enabled or disabled.
1993 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
1994 * @retval State of bit (1 or 0).
1995 */
LL_RCC_IsEnabledIT_LSERDY(void)1996 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
1997 {
1998 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
1999 }
2000
2001 #if defined(RCC_HSI48_SUPPORT)
2002 /**
2003 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
2004 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
2005 * @retval State of bit (1 or 0).
2006 */
LL_RCC_IsEnabledIT_HSI48RDY(void)2007 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
2008 {
2009 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIUSB48RDYIE) == (RCC_CIER_HSIUSB48RDYIE)) ? 1UL : 0UL);
2010 }
2011 #endif /* RCC_HSI48_SUPPORT */
2012
2013 /**
2014 * @brief Checks if HSI ready interrupt source is enabled or disabled.
2015 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
2016 * @retval State of bit (1 or 0).
2017 */
LL_RCC_IsEnabledIT_HSIRDY(void)2018 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
2019 {
2020 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
2021 }
2022
2023 /**
2024 * @brief Checks if HSE ready interrupt source is enabled or disabled.
2025 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
2026 * @retval State of bit (1 or 0).
2027 */
LL_RCC_IsEnabledIT_HSERDY(void)2028 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
2029 {
2030 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
2031 }
2032
2033 /**
2034 * @}
2035 */
2036
2037 #if defined(USE_FULL_LL_DRIVER)
2038 /** @defgroup RCC_LL_EF_Init De-initialization function
2039 * @{
2040 */
2041 ErrorStatus LL_RCC_DeInit(void);
2042 /**
2043 * @}
2044 */
2045
2046 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
2047 * @{
2048 */
2049 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2050 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
2051 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
2052 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
2053 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
2054 uint32_t LL_RCC_GetRTCClockFreq(void);
2055 #if defined(USB_DRD_FS)
2056 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
2057 #endif /* USB_DRD_FS */
2058 /**
2059 * @}
2060 */
2061 #endif /* USE_FULL_LL_DRIVER */
2062
2063 /**
2064 * @}
2065 */
2066
2067 /**
2068 * @}
2069 */
2070
2071 #endif /* defined(RCC) */
2072
2073 /**
2074 * @}
2075 */
2076
2077 #ifdef __cplusplus
2078 }
2079 #endif
2080
2081 #endif /* STM32C0xx_LL_RCC_H */
2082
