1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32C0xx_LL_RCC_H
21 #define STM32C0xx_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32c0xx.h"
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
43 * @{
44 */
45
46
47 /**
48 * @}
49 */
50
51 /* Private constants ---------------------------------------------------------*/
52 /* Private macros ------------------------------------------------------------*/
53 #if defined(USE_FULL_LL_DRIVER)
54 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
55 * @{
56 */
57 /**
58 * @}
59 */
60 #endif /*USE_FULL_LL_DRIVER*/
61
62 /* Exported types ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
65 * @{
66 */
67
68 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
69 * @{
70 */
71
72 /**
73 * @brief RCC Clocks Frequency Structure
74 */
75 typedef struct
76 {
77 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
78 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
79 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
80 } LL_RCC_ClocksTypeDef;
81
82 /**
83 * @}
84 */
85
86 /**
87 * @}
88 */
89 #endif /* USE_FULL_LL_DRIVER */
90
91 /* Exported constants --------------------------------------------------------*/
92 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
93 * @{
94 */
95
96 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
97 * @brief Defines used to adapt values of different oscillators
98 * @note These values could be modified in the user environment according to
99 * HW set-up.
100 * @{
101 */
102 #if !defined (HSE_VALUE)
103 #define HSE_VALUE 48000000U /*!< Value of the HSE oscillator in Hz */
104 #endif /* HSE_VALUE */
105
106 #if !defined (HSI_VALUE)
107 #define HSI_VALUE 48000000U /*!< Value of the HSI oscillator in Hz */
108 #endif /* HSI_VALUE */
109
110 #if !defined (LSE_VALUE)
111 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
112 #endif /* LSE_VALUE */
113
114 #if !defined (LSI_VALUE)
115 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
116 #endif /* LSI_VALUE */
117 #if !defined (EXTERNAL_CLOCK_VALUE)
118 #define EXTERNAL_CLOCK_VALUE 48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */
119 #endif /* EXTERNAL_CLOCK_VALUE */
120 /**
121 * @}
122 */
123
124 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
125 * @brief Flags defines which can be used with LL_RCC_WriteReg function
126 * @{
127 */
128 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
129 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
130 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
131 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
132 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
133 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
134 /**
135 * @}
136 */
137
138 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
139 * @brief Flags defines which can be used with LL_RCC_ReadReg function
140 * @{
141 */
142 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
143 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
144 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
145 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
146 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
147 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
148 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
149 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
150 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
151 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
152 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
153 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
154 #define LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */
155 /**
156 * @}
157 */
158
159 /** @defgroup RCC_LL_EC_IT IT Defines
160 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
161 * @{
162 */
163 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
164 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
165 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
166 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
167 /**
168 * @}
169 */
170
171 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
172 * @{
173 */
174 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
175 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_CSR1_LSEDRV_0 /*!< Xtal mode medium low driving capability */
176 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR1_LSEDRV_1 /*!< Xtal mode medium high driving capability */
177 #define LL_RCC_LSEDRIVE_HIGH RCC_CSR1_LSEDRV /*!< Xtal mode higher driving capability */
178 /**
179 * @}
180 */
181
182 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
183 * @{
184 */
185 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
186 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_CSR1_LSCOSEL /*!< LSE selection for low speed clock */
187 /**
188 * @}
189 */
190
191 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
192 * @{
193 */
194 #define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */
195 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */
196 #define LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection used as system clock */
197 #define LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection used as system clock */
198 /**
199 * @}
200 */
201
202 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
203 * @{
204 */
205 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */
206 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */
207 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */
208 #define LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */
209 /**
210 * @}
211 */
212
213 /** @defgroup RCC_HCLK_Clock_Source RCC HCLK Clock Source
214 * @{
215 */
216 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< HCLK not divided */
217 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< HCLK divided by 2 */
218 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 4 */
219 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 8 */
220 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 16 */
221 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< HCLK divided by 64 */
222 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 128 */
223 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 256 */
224 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 512 */
225 /**
226 * @}
227 */
228
229 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
230 * @{
231 */
232 #define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */
233 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */
234 #define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */
235 #define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */
236 #define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */
237 /**
238 * @}
239 */
240
241 /** @defgroup RCC_LL_EC_HSI_DIV HSI division factor
242 * @{
243 */
244 #define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI not divided */
245 #define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI divided by 2 */
246 #define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI divided by 4 */
247 #define LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0) /*!< HSI divided by 8 */
248 #define LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2 /*!< HSI divided by 16 */
249 #define LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0) /*!< HSI divided by 32 */
250 #define LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1) /*!< HSI divided by 64 */
251 #define LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV /*!< HSI divided by 128 */
252 /**
253 * @}
254 */
255
256 /** @defgroup RCC_LL_EC_HSIKER_DIV HSI Kernel division factor
257 * @{
258 */
259 #define LL_RCC_HSIKER_DIV_1 0x00000000U /*!< HSI kernel not divided */
260 #define LL_RCC_HSIKER_DIV_2 RCC_CR_HSIKERDIV_0 /*!< HSI kernel divided by 2 */
261 #define LL_RCC_HSIKER_DIV_3 RCC_CR_HSIKERDIV_1 /*!< HSI kernel divided by 3 */
262 #define LL_RCC_HSIKER_DIV_4 (RCC_CR_HSIKERDIV_1 | RCC_CR_HSIKERDIV_0) /*!< HSI kernel divided by 4 */
263 #define LL_RCC_HSIKER_DIV_5 RCC_CR_HSIKERDIV_2 /*!< HSI kernel divided by 5 */
264 #define LL_RCC_HSIKER_DIV_6 (RCC_CR_HSIKERDIV_2 | RCC_CR_HSIKERDIV_0) /*!< HSI kernel divided by 6 */
265 #define LL_RCC_HSIKER_DIV_7 (RCC_CR_HSIKERDIV_2 | RCC_CR_HSIKERDIV_1) /*!< HSI kernel divided by 7 */
266 #define LL_RCC_HSIKER_DIV_8 RCC_CR_HSIKERDIV /*!< HSI kernel divided by 8 */
267 /**
268 * @}
269 */
270
271 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
272 * @{
273 */
274 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
275 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
276 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
277 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
278 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
279 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
280 /**
281 * @}
282 */
283
284 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
285 * @{
286 */
287 #define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO1 not divided */
288 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO1 divided by 2 */
289 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO1 divided by 4 */
290 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 8 */
291 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO1 divided by 16 */
292 #define LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 32 */
293 #define LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO1 divided by 64 */
294 #define LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 128 */
295 /**
296 * @}
297 */
298
299 /** @defgroup RCC_LL_EC_MCO2SOURCE MCO2 SOURCE selection
300 * @{
301 */
302 #define LL_RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO2 output disabled, no clock on MCO2 */
303 #define LL_RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */
304 #define LL_RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_0| RCC_CFGR_MCO2SEL_1) /*!< HSI16 selection as MCO2 source */
305 #define LL_RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */
306 #define LL_RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSI selection as MCO2 source */
307 #define LL_RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_0|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSE selection as MCO2 source */
308 /**
309 * @}
310 */
311
312 /** @defgroup RCC_LL_EC_MCO2_DIV MCO2 prescaler
313 * @{
314 */
315 #define LL_RCC_MCO2_DIV_1 0x00000000U /*!< MCO2 not divided */
316 #define LL_RCC_MCO2_DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO2 divided by 2 */
317 #define LL_RCC_MCO2_DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO2 divided by 4 */
318 #define LL_RCC_MCO2_DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 8 */
319 #define LL_RCC_MCO2_DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO2 divided by 16 */
320 #define LL_RCC_MCO2_DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 32 */
321 #define LL_RCC_MCO2_DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 64 */
322 #define LL_RCC_MCO2_DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */
323 /**
324 * @}
325 */
326 #if defined(USE_FULL_LL_DRIVER)
327 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
328 * @{
329 */
330 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
331 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
332 /**
333 * @}
334 */
335 #endif /* USE_FULL_LL_DRIVER */
336
337 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
338 * @{
339 */
340 #define LL_RCC_USART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART1 clock source */
341 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
342 #define LL_RCC_USART1_CLKSOURCE_HSIKER ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSIKER clock used as USART1 clock source */
343 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
344
345 /**
346 * @}
347 */
348
349
350 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
351 * @{
352 */
353 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as I2C1 clock source */
354 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 /*!< SYSCLK clock used as I2C1 clock source */
355 #define LL_RCC_I2C1_CLKSOURCE_HSIKER RCC_CCIPR_I2C1SEL_1 /*!< HSIKER clock used as I2C1 clock source */
356 /**
357 * @}
358 */
359
360 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
361 * @{
362 */
363 #define LL_RCC_I2S1_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as I2S1 clock source */
364 #define LL_RCC_I2S1_CLKSOURCE_HSIKER RCC_CCIPR_I2S1SEL_1 /*!< HSIKER clock used as I2S1 clock source */
365 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CCIPR_I2S1SEL /*!< External clock used as I2S1 clock source */
366 /**
367 * @}
368 */
369
370 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
371 * @{
372 */
373 #define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */
374 #define LL_RCC_ADC_CLKSOURCE_HSIKER RCC_CCIPR_ADCSEL_1 /*!< HSIKER kernel used as ADC clock */
375 /**
376 * @}
377 */
378
379 /** @defgroup RCC_LL_EC_USARTx Peripheral USARTx get clock source
380 * @{
381 */
382 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
383 /**
384 * @}
385 */
386
387 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
388 * @{
389 */
390 #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */
391 /**
392 * @}
393 */
394
395 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
396 * @{
397 */
398 #define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR_I2S1SEL /*!< I2S1 Clock source selection */
399 /**
400 * @}
401 */
402
403 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
404 * @{
405 */
406 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */
407 /**
408 * @}
409 */
410
411 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
412 * @{
413 */
414 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
415 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
416 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR1_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
417 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_CSR1_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
418 /**
419 * @}
420 */
421
422 /**
423 * @}
424 */
425
426 /* Exported macro ------------------------------------------------------------*/
427 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
428 * @{
429 */
430
431 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
432 * @{
433 */
434
435 /**
436 * @brief Write a value in RCC register
437 * @param __REG__ Register to be written
438 * @param __VALUE__ Value to be written in the register
439 * @retval None
440 */
441 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__))
442
443 /**
444 * @brief Read a value in RCC register
445 * @param __REG__ Register to be read
446 * @retval Register value
447 */
448 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
449 /**
450 * @}
451 */
452
453 /**
454 * @brief Helper macro to calculate the HCLK frequency
455 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
456 * @param __AHBPRESCALER__ This parameter can be one of the following values:
457 * @arg @ref LL_RCC_SYSCLK_DIV_1
458 * @arg @ref LL_RCC_SYSCLK_DIV_2
459 * @arg @ref LL_RCC_SYSCLK_DIV_4
460 * @arg @ref LL_RCC_SYSCLK_DIV_8
461 * @arg @ref LL_RCC_SYSCLK_DIV_16
462 * @arg @ref LL_RCC_SYSCLK_DIV_64
463 * @arg @ref LL_RCC_SYSCLK_DIV_128
464 * @arg @ref LL_RCC_SYSCLK_DIV_256
465 * @arg @ref LL_RCC_SYSCLK_DIV_512
466 * @retval HCLK clock frequency (in Hz)
467 */
468 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__)\
469 & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
470
471 /**
472 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
473 * @param __HCLKFREQ__ HCLK frequency
474 * @param __APB1PRESCALER__ This parameter can be one of the following values:
475 * @arg @ref LL_RCC_APB1_DIV_1
476 * @arg @ref LL_RCC_APB1_DIV_2
477 * @arg @ref LL_RCC_APB1_DIV_4
478 * @arg @ref LL_RCC_APB1_DIV_8
479 * @arg @ref LL_RCC_APB1_DIV_16
480 * @retval PCLK1 clock frequency (in Hz)
481 */
482 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos]\
483 & 0x1FU))
484
485 /**
486 * @brief Helper macro to calculate the HSISYS frequency
487 * @param __HSIDIV__ This parameter can be one of the following values:
488 * @arg @ref LL_RCC_HSI_DIV_1
489 * @arg @ref LL_RCC_HSI_DIV_2
490 * @arg @ref LL_RCC_HSI_DIV_4
491 * @arg @ref LL_RCC_HSI_DIV_8
492 * @arg @ref LL_RCC_HSI_DIV_16
493 * @arg @ref LL_RCC_HSI_DIV_32
494 * @arg @ref LL_RCC_HSI_DIV_64
495 * @arg @ref LL_RCC_HSI_DIV_128
496 * @retval HSISYS clock frequency (in Hz)
497 */
498 #define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos)))
499
500 /**
501 * @brief Helper macro to calculate the HSI Kernel frequency
502 * @param __HSIKERDIV__ This parameter can be one of the following values:
503 * @arg @ref LL_RCC_HSIKER_DIV_1
504 * @arg @ref LL_RCC_HSIKER_DIV_2
505 * @arg @ref LL_RCC_HSIKER_DIV_3
506 * @arg @ref LL_RCC_HSIKER_DIV_4
507 * @arg @ref LL_RCC_HSIKER_DIV_5
508 * @arg @ref LL_RCC_HSIKER_DIV_6
509 * @arg @ref LL_RCC_HSIKER_DIV_7
510 * @arg @ref LL_RCC_HSIKER_DIV_8
511 * @retval HSIKER clock frequency (in Hz)
512 */
513 #define __LL_RCC_CALC_HSIKER_FREQ(__HSIKERDIV__) (HSI_VALUE / (((__HSIKERDIV__)>> RCC_CR_HSIKERDIV_Pos) +1U))
514 /**
515 * @}
516 */
517
518
519 /* Exported functions --------------------------------------------------------*/
520 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
521 * @{
522 */
523
524 /** @defgroup RCC_LL_EF_HSE HSE
525 * @{
526 */
527
528 /**
529 * @brief Enable the Clock Security System.
530 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
531 * @retval None
532 */
LL_RCC_HSE_EnableCSS(void)533 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
534 {
535 SET_BIT(RCC->CR, RCC_CR_CSSON);
536 }
537
538 /**
539 * @brief Enable HSE external oscillator (HSE Bypass)
540 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
541 * @retval None
542 */
LL_RCC_HSE_EnableBypass(void)543 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
544 {
545 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
546 }
547
548 /**
549 * @brief Disable HSE external oscillator (HSE Bypass)
550 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
551 * @retval None
552 */
LL_RCC_HSE_DisableBypass(void)553 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
554 {
555 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
556 }
557
558 /**
559 * @brief Enable HSE crystal oscillator (HSE ON)
560 * @rmtoll CR HSEON LL_RCC_HSE_Enable
561 * @retval None
562 */
LL_RCC_HSE_Enable(void)563 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
564 {
565 SET_BIT(RCC->CR, RCC_CR_HSEON);
566 }
567
568 /**
569 * @brief Disable HSE crystal oscillator (HSE ON)
570 * @rmtoll CR HSEON LL_RCC_HSE_Disable
571 * @retval None
572 */
LL_RCC_HSE_Disable(void)573 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
574 {
575 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
576 }
577
578 /**
579 * @brief Check if HSE oscillator Ready
580 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
581 * @retval State of bit (1 or 0).
582 */
LL_RCC_HSE_IsReady(void)583 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
584 {
585 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
586 }
587
588 /**
589 * @}
590 */
591
592 /** @defgroup RCC_LL_EF_HSI HSI
593 * @{
594 */
595
596 /**
597 * @brief Enable HSI even in stop mode
598 * @note HSI oscillator is forced ON even in Stop mode
599 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
600 * @retval None
601 */
LL_RCC_HSI_EnableInStopMode(void)602 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
603 {
604 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
605 }
606
607 /**
608 * @brief Disable HSI in stop mode
609 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
610 * @retval None
611 */
LL_RCC_HSI_DisableInStopMode(void)612 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
613 {
614 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
615 }
616
617 /**
618 * @brief Check if HSI in stop mode is enabled
619 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
620 * @retval State of bit (1 or 0).
621 */
LL_RCC_HSI_IsEnabledInStopMode(void)622 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
623 {
624 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
625 }
626
627 /**
628 * @brief Set HSIKER divider
629 * @rmtoll CR HSIKERDIV LL_RCC_HSIKER_SetDivider
630 * @param Divider This parameter can be one of the following values:
631 * @arg @ref LL_RCC_HSIKER_DIV_1
632 * @arg @ref LL_RCC_HSIKER_DIV_2
633 * @arg @ref LL_RCC_HSIKER_DIV_3
634 * @arg @ref LL_RCC_HSIKER_DIV_4
635 * @arg @ref LL_RCC_HSIKER_DIV_5
636 * @arg @ref LL_RCC_HSIKER_DIV_6
637 * @arg @ref LL_RCC_HSIKER_DIV_7
638 * @arg @ref LL_RCC_HSIKER_DIV_8
639 * @retval None.
640 */
LL_RCC_HSIKER_SetDivider(uint32_t Divider)641 __STATIC_INLINE void LL_RCC_HSIKER_SetDivider(uint32_t Divider)
642 {
643 MODIFY_REG(RCC->CR, RCC_CR_HSIKERDIV, Divider);
644 }
645
646 /**
647 * @brief Get HSIKER divider
648 * @rmtoll CR HSIKERDIV LL_RCC_HSIKER_GetDivider
649 * @retval can be one of the following values:
650 * @arg @ref LL_RCC_HSIKER_DIV_1
651 * @arg @ref LL_RCC_HSIKER_DIV_2
652 * @arg @ref LL_RCC_HSIKER_DIV_3
653 * @arg @ref LL_RCC_HSIKER_DIV_4
654 * @arg @ref LL_RCC_HSIKER_DIV_5
655 * @arg @ref LL_RCC_HSIKER_DIV_6
656 * @arg @ref LL_RCC_HSIKER_DIV_7
657 * @arg @ref LL_RCC_HSIKER_DIV_8
658 */
LL_RCC_HSIKER_GetDivider(void)659 __STATIC_INLINE uint32_t LL_RCC_HSIKER_GetDivider(void)
660 {
661 return (READ_BIT(RCC->CR, RCC_CR_HSIKERDIV));
662 }
663
664 /**
665 * @brief Enable HSI oscillator
666 * @rmtoll CR HSION LL_RCC_HSI_Enable
667 * @retval None
668 */
LL_RCC_HSI_Enable(void)669 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
670 {
671 SET_BIT(RCC->CR, RCC_CR_HSION);
672 }
673
674
675 /**
676 * @brief Set HSI divider
677 * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider
678 * @param Divider This parameter can be one of the following values:
679 * @arg @ref LL_RCC_HSI_DIV_1
680 * @arg @ref LL_RCC_HSI_DIV_2
681 * @arg @ref LL_RCC_HSI_DIV_4
682 * @arg @ref LL_RCC_HSI_DIV_8
683 * @arg @ref LL_RCC_HSI_DIV_16
684 * @arg @ref LL_RCC_HSI_DIV_32
685 * @arg @ref LL_RCC_HSI_DIV_64
686 * @arg @ref LL_RCC_HSI_DIV_128
687 * @retval None.
688 */
LL_RCC_HSI_SetDivider(uint32_t Divider)689 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
690 {
691 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
692 }
693
694 /**
695 * @brief Get HSI divider
696 * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider
697 * @retval can be one of the following values:
698 * @arg @ref LL_RCC_HSI_DIV_1
699 * @arg @ref LL_RCC_HSI_DIV_2
700 * @arg @ref LL_RCC_HSI_DIV_4
701 * @arg @ref LL_RCC_HSI_DIV_8
702 * @arg @ref LL_RCC_HSI_DIV_16
703 * @arg @ref LL_RCC_HSI_DIV_32
704 * @arg @ref LL_RCC_HSI_DIV_64
705 * @arg @ref LL_RCC_HSI_DIV_128
706 */
LL_RCC_HSI_GetDivider(void)707 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
708 {
709 return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
710 }
711
712 /**
713 * @brief Disable HSI oscillator
714 * @rmtoll CR HSION LL_RCC_HSI_Disable
715 * @retval None
716 */
LL_RCC_HSI_Disable(void)717 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
718 {
719 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
720 }
721
722 /**
723 * @brief Check if HSI clock is ready
724 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
725 * @retval State of bit (1 or 0).
726 */
LL_RCC_HSI_IsReady(void)727 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
728 {
729 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
730 }
731
732 /**
733 * @brief Get HSI Calibration value
734 * @note When HSITRIM is written, HSICAL is updated with the sum of
735 * HSITRIM and the factory trim value
736 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
737 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
738 */
LL_RCC_HSI_GetCalibration(void)739 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
740 {
741 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
742 }
743
744 /**
745 * @brief Set HSI Calibration trimming
746 * @note user-programmable trimming value that is added to the HSICAL
747 * @note Default value is 64, which, when added to the HSICAL value,
748 * should trim the HSI to 16 MHz +/- 1 %
749 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
750 * @param Value Between Min_Data = 0 and Max_Data = 127
751 * @retval None
752 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)753 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
754 {
755 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
756 }
757
758 /**
759 * @brief Get HSI Calibration trimming
760 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
761 * @retval Between Min_Data = 0 and Max_Data = 127
762 */
LL_RCC_HSI_GetCalibTrimming(void)763 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
764 {
765 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
766 }
767
768 /**
769 * @}
770 */
771
772 /** @defgroup RCC_LL_EF_LSE LSE
773 * @{
774 */
775
776 /**
777 * @brief Enable Low Speed External (LSE) crystal.
778 * @rmtoll CSR1 LSEON LL_RCC_LSE_Enable
779 * @retval None
780 */
LL_RCC_LSE_Enable(void)781 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
782 {
783 SET_BIT(RCC->CSR1, RCC_CSR1_LSEON);
784 }
785
786 /**
787 * @brief Disable Low Speed External (LSE) crystal.
788 * @rmtoll CSR1 LSEON LL_RCC_LSE_Disable
789 * @retval None
790 */
LL_RCC_LSE_Disable(void)791 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
792 {
793 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEON);
794 }
795
796 /**
797 * @brief Enable external clock source (LSE bypass).
798 * @rmtoll CSR1 LSEBYP LL_RCC_LSE_EnableBypass
799 * @retval None
800 */
LL_RCC_LSE_EnableBypass(void)801 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
802 {
803 SET_BIT(RCC->CSR1, RCC_CSR1_LSEBYP);
804 }
805
806 /**
807 * @brief Disable external clock source (LSE bypass).
808 * @rmtoll CSR1 LSEBYP LL_RCC_LSE_DisableBypass
809 * @retval None
810 */
LL_RCC_LSE_DisableBypass(void)811 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
812 {
813 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEBYP);
814 }
815
816 /**
817 * @brief Set LSE oscillator drive capability
818 * @note The oscillator is in Xtal mode when it is not in bypass mode.
819 * @rmtoll CSR1 LSEDRV LL_RCC_LSE_SetDriveCapability
820 * @param LSEDrive This parameter can be one of the following values:
821 * @arg @ref LL_RCC_LSEDRIVE_LOW
822 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
823 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
824 * @arg @ref LL_RCC_LSEDRIVE_HIGH
825 * @retval None
826 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)827 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
828 {
829 MODIFY_REG(RCC->CSR1, RCC_CSR1_LSEDRV, LSEDrive);
830 }
831
832 /**
833 * @brief Get LSE oscillator drive capability
834 * @rmtoll CSR1 LSEDRV LL_RCC_LSE_GetDriveCapability
835 * @retval Returned value can be one of the following values:
836 * @arg @ref LL_RCC_LSEDRIVE_LOW
837 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
838 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
839 * @arg @ref LL_RCC_LSEDRIVE_HIGH
840 */
LL_RCC_LSE_GetDriveCapability(void)841 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
842 {
843 return (uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_LSEDRV));
844 }
845
846 /**
847 * @brief Enable Clock security system on LSE.
848 * @rmtoll CSR1 LSECSSON LL_RCC_LSE_EnableCSS
849 * @retval None
850 */
LL_RCC_LSE_EnableCSS(void)851 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
852 {
853 SET_BIT(RCC->CSR1, RCC_CSR1_LSECSSON);
854 }
855
856 /**
857 * @brief Disable Clock security system on LSE.
858 * @note Clock security system can be disabled only after a LSE
859 * failure detection. In that case it MUST be disabled by software.
860 * @rmtoll CSR1 LSECSSON LL_RCC_LSE_DisableCSS
861 * @retval None
862 */
LL_RCC_LSE_DisableCSS(void)863 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
864 {
865 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSECSSON);
866 }
867
868 /**
869 * @brief Check if LSE oscillator Ready
870 * @rmtoll CSR1 LSERDY LL_RCC_LSE_IsReady
871 * @retval State of bit (1 or 0).
872 */
LL_RCC_LSE_IsReady(void)873 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
874 {
875 return ((READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == (RCC_CSR1_LSERDY)) ? 1UL : 0UL);
876 }
877
878 /**
879 * @brief Check if CSS on LSE failure Detection
880 * @rmtoll CSR1 LSECSSD LL_RCC_LSE_IsCSSDetected
881 * @retval State of bit (1 or 0).
882 */
LL_RCC_LSE_IsCSSDetected(void)883 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
884 {
885 return ((READ_BIT(RCC->CSR1, RCC_CSR1_LSECSSD) == (RCC_CSR1_LSECSSD)) ? 1UL : 0UL);
886 }
887
888 /**
889 * @}
890 */
891
892 /** @defgroup RCC_LL_EF_LSI LSI
893 * @{
894 */
895
896 /**
897 * @brief Enable LSI Oscillator
898 * @rmtoll CSR2 LSION LL_RCC_LSI_Enable
899 * @retval None
900 */
LL_RCC_LSI_Enable(void)901 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
902 {
903 SET_BIT(RCC->CSR2, RCC_CSR2_LSION);
904 }
905
906 /**
907 * @brief Disable LSI Oscillator
908 * @rmtoll CSR2 LSION LL_RCC_LSI_Disable
909 * @retval None
910 */
LL_RCC_LSI_Disable(void)911 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
912 {
913 CLEAR_BIT(RCC->CSR2, RCC_CSR2_LSION);
914 }
915
916 /**
917 * @brief Check if LSI is Ready
918 * @rmtoll CSR2 LSIRDY LL_RCC_LSI_IsReady
919 * @retval State of bit (1 or 0).
920 */
LL_RCC_LSI_IsReady(void)921 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
922 {
923 return ((READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == (RCC_CSR2_LSIRDY)) ? 1UL : 0UL);
924 }
925
926 /**
927 * @}
928 */
929
930 /** @defgroup RCC_LL_EF_LSCO LSCO
931 * @{
932 */
933
934 /**
935 * @brief Enable Low speed clock
936 * @rmtoll CSR1 LSCOEN LL_RCC_LSCO_Enable
937 * @retval None
938 */
LL_RCC_LSCO_Enable(void)939 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
940 {
941 SET_BIT(RCC->CSR1, RCC_CSR1_LSCOEN);
942 }
943
944 /**
945 * @brief Disable Low speed clock
946 * @rmtoll CSR1 LSCOEN LL_RCC_LSCO_Disable
947 * @retval None
948 */
LL_RCC_LSCO_Disable(void)949 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
950 {
951 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSCOEN);
952 }
953
954 /**
955 * @brief Configure Low speed clock selection
956 * @rmtoll CSR1 LSCOSEL LL_RCC_LSCO_SetSource
957 * @param Source This parameter can be one of the following values:
958 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
959 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
960 * @retval None
961 */
LL_RCC_LSCO_SetSource(uint32_t Source)962 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
963 {
964 MODIFY_REG(RCC->CSR1, RCC_CSR1_LSCOSEL, Source);
965 }
966
967 /**
968 * @brief Get Low speed clock selection
969 * @rmtoll CSR1 LSCOSEL LL_RCC_LSCO_GetSource
970 * @retval Returned value can be one of the following values:
971 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
972 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
973 */
LL_RCC_LSCO_GetSource(void)974 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
975 {
976 return (uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_LSCOSEL));
977 }
978
979 /**
980 * @}
981 */
982
983 /** @defgroup RCC_LL_EF_System System
984 * @{
985 */
986
987 /**
988 * @brief Configure the system clock source
989 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
990 * @param Source This parameter can be one of the following values:
991 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
992 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
993 * @arg @ref LL_RCC_SYS_CLKSOURCE_LSI
994 * @arg @ref LL_RCC_SYS_CLKSOURCE_LSE
995 * @retval None
996 */
LL_RCC_SetSysClkSource(uint32_t Source)997 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
998 {
999 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1000 }
1001
1002 /**
1003 * @brief Get the system clock source
1004 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1005 * @retval Returned value can be one of the following values:
1006 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1007 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1008 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI
1009 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE
1010 */
LL_RCC_GetSysClkSource(void)1011 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1012 {
1013 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1014 }
1015
1016 /**
1017 * @brief Set AHB prescaler
1018 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1019 * @param Prescaler This parameter can be one of the following values:
1020 * @arg @ref LL_RCC_SYSCLK_DIV_1
1021 * @arg @ref LL_RCC_SYSCLK_DIV_2
1022 * @arg @ref LL_RCC_SYSCLK_DIV_4
1023 * @arg @ref LL_RCC_SYSCLK_DIV_8
1024 * @arg @ref LL_RCC_SYSCLK_DIV_16
1025 * @arg @ref LL_RCC_SYSCLK_DIV_64
1026 * @arg @ref LL_RCC_SYSCLK_DIV_128
1027 * @arg @ref LL_RCC_SYSCLK_DIV_256
1028 * @arg @ref LL_RCC_SYSCLK_DIV_512
1029 * @retval None
1030 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1031 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1032 {
1033 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1034 }
1035
1036 /**
1037 * @brief Set APB1 prescaler
1038 * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler
1039 * @param Prescaler This parameter can be one of the following values:
1040 * @arg @ref LL_RCC_APB1_DIV_1
1041 * @arg @ref LL_RCC_APB1_DIV_2
1042 * @arg @ref LL_RCC_APB1_DIV_4
1043 * @arg @ref LL_RCC_APB1_DIV_8
1044 * @arg @ref LL_RCC_APB1_DIV_16
1045 * @retval None
1046 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1047 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1048 {
1049 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
1050 }
1051
1052 /**
1053 * @brief Set HSI48 division factor
1054 * @rmtoll CR HSIDIV LL_RCC_SetHSIDiv
1055 * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
1056 * system clock source.
1057 * @param HSIDiv This parameter can be one of the following values:
1058 * @arg @ref LL_RCC_HSI_DIV_1
1059 * @arg @ref LL_RCC_HSI_DIV_2
1060 * @arg @ref LL_RCC_HSI_DIV_4
1061 * @arg @ref LL_RCC_HSI_DIV_8
1062 * @arg @ref LL_RCC_HSI_DIV_16
1063 * @arg @ref LL_RCC_HSI_DIV_32
1064 * @arg @ref LL_RCC_HSI_DIV_64
1065 * @arg @ref LL_RCC_HSI_DIV_128
1066 * @retval None
1067 */
LL_RCC_SetHSIDiv(uint32_t HSIDiv)1068 __STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv)
1069 {
1070 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv);
1071 }
1072
1073 /**
1074 * @brief Set HSIKER division factor
1075 * @rmtoll CR HSIKERDIV LL_RCC_SetHSIKERDiv
1076 * @param HSIKERDiv This parameter can be one of the following values:
1077 * @arg @ref LL_RCC_HSIKER_DIV_1
1078 * @arg @ref LL_RCC_HSIKER_DIV_2
1079 * @arg @ref LL_RCC_HSIKER_DIV_3
1080 * @arg @ref LL_RCC_HSIKER_DIV_4
1081 * @arg @ref LL_RCC_HSIKER_DIV_5
1082 * @arg @ref LL_RCC_HSIKER_DIV_6
1083 * @arg @ref LL_RCC_HSIKER_DIV_7
1084 * @arg @ref LL_RCC_HSIKER_DIV_8
1085 * @retval None
1086 */
LL_RCC_SetHSIKERDiv(uint32_t HSIKERDiv)1087 __STATIC_INLINE void LL_RCC_SetHSIKERDiv(uint32_t HSIKERDiv)
1088 {
1089 MODIFY_REG(RCC->CR, RCC_CR_HSIKERDIV, HSIKERDiv);
1090 }
1091 /**
1092 * @brief Get AHB prescaler
1093 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1094 * @retval Returned value can be one of the following values:
1095 * @arg @ref LL_RCC_SYSCLK_DIV_1
1096 * @arg @ref LL_RCC_SYSCLK_DIV_2
1097 * @arg @ref LL_RCC_SYSCLK_DIV_4
1098 * @arg @ref LL_RCC_SYSCLK_DIV_8
1099 * @arg @ref LL_RCC_SYSCLK_DIV_16
1100 * @arg @ref LL_RCC_SYSCLK_DIV_64
1101 * @arg @ref LL_RCC_SYSCLK_DIV_128
1102 * @arg @ref LL_RCC_SYSCLK_DIV_256
1103 * @arg @ref LL_RCC_SYSCLK_DIV_512
1104 */
LL_RCC_GetAHBPrescaler(void)1105 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1106 {
1107 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1108 }
1109
1110 /**
1111 * @brief Get APB1 prescaler
1112 * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler
1113 * @retval Returned value can be one of the following values:
1114 * @arg @ref LL_RCC_APB1_DIV_1
1115 * @arg @ref LL_RCC_APB1_DIV_2
1116 * @arg @ref LL_RCC_APB1_DIV_4
1117 * @arg @ref LL_RCC_APB1_DIV_8
1118 * @arg @ref LL_RCC_APB1_DIV_16
1119 */
LL_RCC_GetAPB1Prescaler(void)1120 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1121 {
1122 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
1123 }
1124
1125 /**
1126 * @brief Get HSI48 Division factor
1127 * @rmtoll CR HSIDIV LL_RCC_GetHSIDiv
1128 * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
1129 * system clock source.
1130 * @retval Returned value can be one of the following values:
1131 * @arg @ref LL_RCC_HSI_DIV_1
1132 * @arg @ref LL_RCC_HSI_DIV_2
1133 * @arg @ref LL_RCC_HSI_DIV_4
1134 * @arg @ref LL_RCC_HSI_DIV_8
1135 * @arg @ref LL_RCC_HSI_DIV_16
1136 * @arg @ref LL_RCC_HSI_DIV_32
1137 * @arg @ref LL_RCC_HSI_DIV_64
1138 * @arg @ref LL_RCC_HSI_DIV_128
1139 */
LL_RCC_GetHSIDiv(void)1140 __STATIC_INLINE uint32_t LL_RCC_GetHSIDiv(void)
1141 {
1142 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV));
1143 }
1144 /**
1145 * @}
1146 */
1147
1148 /** @defgroup RCC_LL_EF_MCO MCO
1149 * @{
1150 */
1151
1152 /**
1153 * @brief Configure MCOx
1154 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
1155 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
1156 * CFGR MCO2 LL_RCC_ConfigMCO\n
1157 * CFGR MCO2PRE LL_RCC_ConfigMCO
1158 * @param MCOxSource This parameter can be one of the following values:
1159 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1160 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1161 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1162 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1163 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1164 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1165 * @param MCOxPrescaler This parameter can be one of the following values:
1166 * @arg @ref LL_RCC_MCO1_DIV_1
1167 * @arg @ref LL_RCC_MCO1_DIV_2
1168 * @arg @ref LL_RCC_MCO1_DIV_4
1169 * @arg @ref LL_RCC_MCO1_DIV_8
1170 * @arg @ref LL_RCC_MCO1_DIV_16
1171 * @arg @ref LL_RCC_MCO1_DIV_32
1172 * @arg @ref LL_RCC_MCO1_DIV_64
1173 * @arg @ref LL_RCC_MCO1_DIV_128
1174 * @retval None
1175 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1176 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1177 {
1178 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1179 }
1180
1181 /**
1182 * @}
1183 */
1184
1185 /** @defgroup RCC_LL_EF_MCO2 MCO2
1186 * @{
1187 */
1188
1189 /**
1190 * @brief Configure MCO2
1191 * @rmtoll CFGR MCO2SEL LL_RCC_ConfigMCO2\n
1192 * CFGR MCO2PRE LL_RCC_ConfigMCO2
1193 * @note feature not available in all devices.
1194 * @param MCOxSource This parameter can be one of the following values:
1195 * @arg @ref LL_RCC_MCO2SOURCE_NOCLOCK
1196 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
1197 * @arg @ref LL_RCC_MCO2SOURCE_HSI
1198 * @arg @ref LL_RCC_MCO2SOURCE_HSE
1199 * @arg @ref LL_RCC_MCO2SOURCE_LSI
1200 * @arg @ref LL_RCC_MCO2SOURCE_LSE
1201 * @param MCOxPrescaler This parameter can be one of the following values:
1202 * @arg @ref LL_RCC_MCO2_DIV_1
1203 * @arg @ref LL_RCC_MCO2_DIV_2
1204 * @arg @ref LL_RCC_MCO2_DIV_4
1205 * @arg @ref LL_RCC_MCO2_DIV_8
1206 * @arg @ref LL_RCC_MCO2_DIV_16
1207 * @arg @ref LL_RCC_MCO2_DIV_32
1208 * @arg @ref LL_RCC_MCO2_DIV_64
1209 * @arg @ref LL_RCC_MCO2_DIV_128
1210 * @retval None
1211 */
LL_RCC_ConfigMCO2(uint32_t MCOxSource,uint32_t MCOxPrescaler)1212 __STATIC_INLINE void LL_RCC_ConfigMCO2(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1213 {
1214 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE, MCOxSource | MCOxPrescaler);
1215 }
1216
1217 /**
1218 * @}
1219 */
1220 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1221 * @{
1222 */
1223
1224 /**
1225 * @brief Configure USARTx clock source
1226 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
1227 * @param USARTxSource This parameter can be one of the following values:
1228 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
1229 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1230 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSIKER
1231 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1232 * @retval None
1233 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1234 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1235 {
1236 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
1237 }
1238
1239
1240 /**
1241 * @brief Configure I2Cx clock source
1242 * @rmtoll CCIPR I2C1SEL LL_RCC_SetI2CClockSource
1243 * @param I2CxSource This parameter can be one of the following values:
1244 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1245 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1246 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSIKER
1247 * @retval None
1248 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1249 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1250 {
1251 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, I2CxSource);
1252 }
1253
1254
1255 /**
1256 * @brief Configure ADC clock source
1257 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
1258 * @param ADCxSource This parameter can be one of the following values:
1259 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
1260 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSIKER
1261 * @retval None
1262 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)1263 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1264 {
1265 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
1266 }
1267
1268 /**
1269 * @brief Configure I2Sx clock source
1270 * @rmtoll CCIPR I2S1SEL LL_RCC_SetI2SClockSource
1271 * @param I2SxSource This parameter can be one of the following values:
1272 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
1273 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
1274 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSIKER
1275 * @retval None
1276 */
LL_RCC_SetI2SClockSource(uint32_t I2SxSource)1277 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
1278 {
1279 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, I2SxSource);
1280 }
1281
1282 /**
1283 * @brief Get USARTx clock source
1284 * @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource
1285 * @param USARTx This parameter can be one of the following values:
1286 * @arg @ref LL_RCC_USART1_CLKSOURCE
1287 * @retval Returned value can be one of the following values:
1288 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
1289 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1290 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSIKER
1291 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1292 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)1293 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1294 {
1295 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
1296 }
1297
1298
1299 /**
1300 * @brief Get I2Cx clock source
1301 * @rmtoll CCIPR I2C1SEL LL_RCC_GetI2CClockSource
1302 * @param I2Cx This parameter can be one of the following values:
1303 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1304 * @retval Returned value can be one of the following values:
1305 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1306 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1307 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSIKER
1308 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)1309 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
1310 {
1311 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Cx));
1312 }
1313
1314 /**
1315 * @brief Get ADCx clock source
1316 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
1317 * @param ADCx This parameter can be one of the following values:
1318 * @arg @ref LL_RCC_ADC_CLKSOURCE
1319 * @retval Returned value can be one of the following values:
1320 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSIKER
1321 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
1322 */
LL_RCC_GetADCClockSource(uint32_t ADCx)1323 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1324 {
1325 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
1326 }
1327
1328 /**
1329 * @brief Get I2Sx clock source
1330 * @rmtoll CCIPR I2S LL_RCC_GetI2SClockSource
1331 * @param I2Sx This parameter can be one of the following values:
1332 * @arg @ref LL_RCC_I2S1_CLKSOURCE
1333 * @retval Returned value can be one of the following values:
1334 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
1335 * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
1336 * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSIKER
1337 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)1338 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
1339 {
1340 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
1341 }
1342 /**
1343 * @}
1344 */
1345
1346 /** @defgroup RCC_LL_EF_RTC RTC
1347 * @{
1348 */
1349
1350 /**
1351 * @brief Set RTC Clock Source
1352 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
1353 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
1354 * set). The BDRST bit can be used to reset them.
1355 * @rmtoll CSR1 RTCSEL LL_RCC_SetRTCClockSource
1356 * @param Source This parameter can be one of the following values:
1357 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1358 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1359 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1360 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
1361 * @retval None
1362 */
LL_RCC_SetRTCClockSource(uint32_t Source)1363 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
1364 {
1365 MODIFY_REG(RCC->CSR1, RCC_CSR1_RTCSEL, Source);
1366 }
1367
1368 /**
1369 * @brief Get RTC Clock Source
1370 * @rmtoll CSR1 RTCSEL LL_RCC_GetRTCClockSource
1371 * @retval Returned value can be one of the following values:
1372 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1373 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1374 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1375 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
1376 */
LL_RCC_GetRTCClockSource(void)1377 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
1378 {
1379 return (uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL));
1380 }
1381
1382 /**
1383 * @brief Enable RTC
1384 * @rmtoll CSR1 RTCEN LL_RCC_EnableRTC
1385 * @retval None
1386 */
LL_RCC_EnableRTC(void)1387 __STATIC_INLINE void LL_RCC_EnableRTC(void)
1388 {
1389 SET_BIT(RCC->CSR1, RCC_CSR1_RTCEN);
1390 }
1391
1392 /**
1393 * @brief Disable RTC
1394 * @rmtoll CSR1 RTCEN LL_RCC_DisableRTC
1395 * @retval None
1396 */
LL_RCC_DisableRTC(void)1397 __STATIC_INLINE void LL_RCC_DisableRTC(void)
1398 {
1399 CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCEN);
1400 }
1401
1402 /**
1403 * @brief Check if RTC has been enabled or not
1404 * @rmtoll CSR1 RTCEN LL_RCC_IsEnabledRTC
1405 * @retval State of bit (1 or 0).
1406 */
LL_RCC_IsEnabledRTC(void)1407 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
1408 {
1409 return ((READ_BIT(RCC->CSR1, RCC_CSR1_RTCEN) == (RCC_CSR1_RTCEN)) ? 1UL : 0UL);
1410 }
1411
1412 /**
1413 * @brief Force the Backup domain reset
1414 * @rmtoll CSR1 RTCRST LL_RCC_ForceBackupDomainReset
1415 * @retval None
1416 */
LL_RCC_ForceBackupDomainReset(void)1417 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
1418 {
1419 SET_BIT(RCC->CSR1, RCC_CSR1_RTCRST);
1420 }
1421
1422 /**
1423 * @brief Release the Backup domain reset
1424 * @rmtoll CSR1 RTCRST LL_RCC_ReleaseBackupDomainReset
1425 * @retval None
1426 */
LL_RCC_ReleaseBackupDomainReset(void)1427 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
1428 {
1429 CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCRST);
1430 }
1431
1432 /**
1433 * @}
1434 */
1435
1436 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
1437 * @{
1438 */
1439
1440 /**
1441 * @brief Clear LSI ready interrupt flag
1442 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
1443 * @retval None
1444 */
LL_RCC_ClearFlag_LSIRDY(void)1445 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
1446 {
1447 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
1448 }
1449
1450 /**
1451 * @brief Clear LSE ready interrupt flag
1452 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
1453 * @retval None
1454 */
LL_RCC_ClearFlag_LSERDY(void)1455 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
1456 {
1457 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
1458 }
1459
1460 /**
1461 * @brief Clear HSI ready interrupt flag
1462 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
1463 * @retval None
1464 */
LL_RCC_ClearFlag_HSIRDY(void)1465 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
1466 {
1467 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
1468 }
1469
1470 /**
1471 * @brief Clear HSE ready interrupt flag
1472 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
1473 * @retval None
1474 */
LL_RCC_ClearFlag_HSERDY(void)1475 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
1476 {
1477 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
1478 }
1479
1480 /**
1481 * @brief Clear Clock security system interrupt flag
1482 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
1483 * @retval None
1484 */
LL_RCC_ClearFlag_HSECSS(void)1485 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
1486 {
1487 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
1488 }
1489
1490 /**
1491 * @brief Clear LSE Clock security system interrupt flag
1492 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
1493 * @retval None
1494 */
LL_RCC_ClearFlag_LSECSS(void)1495 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
1496 {
1497 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
1498 }
1499
1500 /**
1501 * @brief Check if LSI ready interrupt occurred or not
1502 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
1503 * @retval State of bit (1 or 0).
1504 */
LL_RCC_IsActiveFlag_LSIRDY(void)1505 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
1506 {
1507 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
1508 }
1509
1510 /**
1511 * @brief Check if LSE ready interrupt occurred or not
1512 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
1513 * @retval State of bit (1 or 0).
1514 */
LL_RCC_IsActiveFlag_LSERDY(void)1515 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
1516 {
1517 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
1518 }
1519
1520 /**
1521 * @brief Check if HSI ready interrupt occurred or not
1522 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
1523 * @retval State of bit (1 or 0).
1524 */
LL_RCC_IsActiveFlag_HSIRDY(void)1525 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
1526 {
1527 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
1528 }
1529
1530 /**
1531 * @brief Check if HSE ready interrupt occurred or not
1532 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
1533 * @retval State of bit (1 or 0).
1534 */
LL_RCC_IsActiveFlag_HSERDY(void)1535 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
1536 {
1537 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
1538 }
1539
1540 /**
1541 * @brief Check if Clock security system interrupt occurred or not
1542 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
1543 * @retval State of bit (1 or 0).
1544 */
LL_RCC_IsActiveFlag_HSECSS(void)1545 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
1546 {
1547 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
1548 }
1549
1550 /**
1551 * @brief Check if LSE Clock security system interrupt occurred or not
1552 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
1553 * @retval State of bit (1 or 0).
1554 */
LL_RCC_IsActiveFlag_LSECSS(void)1555 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
1556 {
1557 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
1558 }
1559
1560 /**
1561 * @brief Check if RCC flag Independent Watchdog reset is set or not.
1562 * @rmtoll CSR2 IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
1563 * @retval State of bit (1 or 0).
1564 */
LL_RCC_IsActiveFlag_IWDGRST(void)1565 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
1566 {
1567 return ((READ_BIT(RCC->CSR2, RCC_CSR2_IWDGRSTF) == (RCC_CSR2_IWDGRSTF)) ? 1UL : 0UL);
1568 }
1569
1570 /**
1571 * @brief Check if RCC flag Low Power reset is set or not.
1572 * @rmtoll CSR2 LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
1573 * @retval State of bit (1 or 0).
1574 */
LL_RCC_IsActiveFlag_LPWRRST(void)1575 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
1576 {
1577 return ((READ_BIT(RCC->CSR2, RCC_CSR2_LPWRRSTF) == (RCC_CSR2_LPWRRSTF)) ? 1UL : 0UL);
1578 }
1579
1580 /**
1581 * @brief Check if RCC flag Option byte reset is set or not.
1582 * @rmtoll CSR2 OBLRSTF LL_RCC_IsActiveFlag_OBLRST
1583 * @retval State of bit (1 or 0).
1584 */
LL_RCC_IsActiveFlag_OBLRST(void)1585 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
1586 {
1587 return ((READ_BIT(RCC->CSR2, RCC_CSR2_OBLRSTF) == (RCC_CSR2_OBLRSTF)) ? 1UL : 0UL);
1588 }
1589
1590 /**
1591 * @brief Check if RCC flag Pin reset is set or not.
1592 * @rmtoll CSR2 PINRSTF LL_RCC_IsActiveFlag_PINRST
1593 * @retval State of bit (1 or 0).
1594 */
LL_RCC_IsActiveFlag_PINRST(void)1595 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
1596 {
1597 return ((READ_BIT(RCC->CSR2, RCC_CSR2_PINRSTF) == (RCC_CSR2_PINRSTF)) ? 1UL : 0UL);
1598 }
1599
1600 /**
1601 * @brief Check if RCC flag Software reset is set or not.
1602 * @rmtoll CSR2 SFTRSTF LL_RCC_IsActiveFlag_SFTRST
1603 * @retval State of bit (1 or 0).
1604 */
LL_RCC_IsActiveFlag_SFTRST(void)1605 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
1606 {
1607 return ((READ_BIT(RCC->CSR2, RCC_CSR2_SFTRSTF) == (RCC_CSR2_SFTRSTF)) ? 1UL : 0UL);
1608 }
1609
1610 /**
1611 * @brief Check if RCC flag Window Watchdog reset is set or not.
1612 * @rmtoll CSR2 WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
1613 * @retval State of bit (1 or 0).
1614 */
LL_RCC_IsActiveFlag_WWDGRST(void)1615 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
1616 {
1617 return ((READ_BIT(RCC->CSR2, RCC_CSR2_WWDGRSTF) == (RCC_CSR2_WWDGRSTF)) ? 1UL : 0UL);
1618 }
1619
1620 /**
1621 * @brief Check if RCC flag BOR or POR/PDR reset is set or not.
1622 * @rmtoll CSR2 PWRRSTF LL_RCC_IsActiveFlag_PWRRST
1623 * @retval State of bit (1 or 0).
1624 */
LL_RCC_IsActiveFlag_PWRRST(void)1625 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void)
1626 {
1627 return ((READ_BIT(RCC->CSR2, RCC_CSR2_PWRRSTF) == (RCC_CSR2_PWRRSTF)) ? 1UL : 0UL);
1628 }
1629
1630 /**
1631 * @brief Set RMVF bit to clear the reset flags.
1632 * @rmtoll CSR2 RMVF LL_RCC_ClearResetFlags
1633 * @retval None
1634 */
LL_RCC_ClearResetFlags(void)1635 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
1636 {
1637 SET_BIT(RCC->CSR2, RCC_CSR2_RMVF);
1638 }
1639
1640 /**
1641 * @}
1642 */
1643
1644 /** @defgroup RCC_LL_EF_IT_Management IT Management
1645 * @{
1646 */
1647
1648 /**
1649 * @brief Enable LSI ready interrupt
1650 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
1651 * @retval None
1652 */
LL_RCC_EnableIT_LSIRDY(void)1653 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
1654 {
1655 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
1656 }
1657
1658 /**
1659 * @brief Enable LSE ready interrupt
1660 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
1661 * @retval None
1662 */
LL_RCC_EnableIT_LSERDY(void)1663 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
1664 {
1665 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
1666 }
1667
1668 /**
1669 * @brief Enable HSI ready interrupt
1670 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
1671 * @retval None
1672 */
LL_RCC_EnableIT_HSIRDY(void)1673 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
1674 {
1675 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
1676 }
1677
1678 /**
1679 * @brief Enable HSE ready interrupt
1680 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
1681 * @retval None
1682 */
LL_RCC_EnableIT_HSERDY(void)1683 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
1684 {
1685 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
1686 }
1687
1688 /**
1689 * @brief Disable LSI ready interrupt
1690 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
1691 * @retval None
1692 */
LL_RCC_DisableIT_LSIRDY(void)1693 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
1694 {
1695 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
1696 }
1697
1698 /**
1699 * @brief Disable LSE ready interrupt
1700 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
1701 * @retval None
1702 */
LL_RCC_DisableIT_LSERDY(void)1703 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
1704 {
1705 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
1706 }
1707
1708 /**
1709 * @brief Disable HSI ready interrupt
1710 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
1711 * @retval None
1712 */
LL_RCC_DisableIT_HSIRDY(void)1713 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
1714 {
1715 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
1716 }
1717
1718 /**
1719 * @brief Disable HSE ready interrupt
1720 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
1721 * @retval None
1722 */
LL_RCC_DisableIT_HSERDY(void)1723 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
1724 {
1725 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
1726 }
1727
1728
1729 /**
1730 * @brief Checks if LSI ready interrupt source is enabled or disabled.
1731 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
1732 * @retval State of bit (1 or 0).
1733 */
LL_RCC_IsEnabledIT_LSIRDY(void)1734 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
1735 {
1736 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
1737 }
1738
1739 /**
1740 * @brief Checks if LSE ready interrupt source is enabled or disabled.
1741 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
1742 * @retval State of bit (1 or 0).
1743 */
LL_RCC_IsEnabledIT_LSERDY(void)1744 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
1745 {
1746 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
1747 }
1748
1749 /**
1750 * @brief Checks if HSI ready interrupt source is enabled or disabled.
1751 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
1752 * @retval State of bit (1 or 0).
1753 */
LL_RCC_IsEnabledIT_HSIRDY(void)1754 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
1755 {
1756 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
1757 }
1758
1759 /**
1760 * @brief Checks if HSE ready interrupt source is enabled or disabled.
1761 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
1762 * @retval State of bit (1 or 0).
1763 */
LL_RCC_IsEnabledIT_HSERDY(void)1764 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
1765 {
1766 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
1767 }
1768
1769 /**
1770 * @}
1771 */
1772
1773 #if defined(USE_FULL_LL_DRIVER)
1774 /** @defgroup RCC_LL_EF_Init De-initialization function
1775 * @{
1776 */
1777 ErrorStatus LL_RCC_DeInit(void);
1778 /**
1779 * @}
1780 */
1781
1782 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
1783 * @{
1784 */
1785 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
1786 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
1787 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
1788 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
1789 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
1790 uint32_t LL_RCC_GetRTCClockFreq(void);
1791 /**
1792 * @}
1793 */
1794 #endif /* USE_FULL_LL_DRIVER */
1795
1796 /**
1797 * @}
1798 */
1799
1800 /**
1801 * @}
1802 */
1803
1804 #endif /* defined(RCC) */
1805
1806 /**
1807 * @}
1808 */
1809
1810 #ifdef __cplusplus
1811 }
1812 #endif
1813
1814 #endif /* STM32C0xx_LL_RCC_H */
1815
