1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL SYSTEM driver contains a set of generic APIs that can be
23 used by user:
24 (+) Some of the FLASH features need to be handled in the SYSTEM file.
25 (+) Access to DBGCMU registers
26 (+) Access to SYSCFG registers
27 @endverbatim
28 ******************************************************************************
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef STM32C0xx_LL_SYSTEM_H
33 #define STM32C0xx_LL_SYSTEM_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32c0xx.h"
41
42 /** @addtogroup STM32C0xx_LL_Driver
43 * @{
44 */
45
46 #if defined (FLASH) || defined (SYSCFG) || defined (DBG)
47
48 /** @defgroup SYSTEM_LL SYSTEM
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
57 * @{
58 */
59
60 /**
61 * @}
62 */
63
64 /* Private macros ------------------------------------------------------------*/
65
66 /* Exported types ------------------------------------------------------------*/
67 /* Exported constants --------------------------------------------------------*/
68 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
69 * @{
70 */
71
72 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
73 * @{
74 */
75 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
76 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
77 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */
78 /**
79 * @}
80 */
81
82 /** @defgroup SYSTEM_LL_EC_PIN_RMP SYSCFG PIN RMP
83 * @{
84 */
85 #define LL_SYSCFG_PIN_RMP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves as PA9 pin */
86 #define LL_SYSCFG_PIN_RMP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves as PA10 pin */
87 /**
88 * @}
89 */
90
91 /** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
92 * @{
93 */
94 #define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IRDA Modulation envelope source */
95 #define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IRDA Modulation envelope source */
96 #define LL_SYSCFG_IR_MOD_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IRDA Modulation envelope source */
97
98 /**
99 * @}
100 */
101 /** @defgroup SYSTEM_LL_EC_IR_POL SYSCFG IR Polarity
102 * @{
103 */
104 #define LL_SYSCFG_IR_POL_NOT_INVERTED 0x00000000U /*!< 0: Output of IRDA (IROut) not inverted */
105 #define LL_SYSCFG_IR_POL_INVERTED (SYSCFG_CFGR1_IR_POL) /*!< 1: Output of IRDA (IROut) inverted */
106 /**
107 * @}
108 */
109
110 /** @defgroup SYSTEM_LL_EC_BOOSTEN SYSCFG I/O analog switch voltage booster enable
111 * @{
112 */
113 #define LL_SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN /*!< I/O analog switch voltage booster enable */
114 /**
115 * @}
116 */
117
118 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
119 * @{
120 */
121 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< I2C PB6 Fast mode plus */
122 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< I2C PB7 Fast mode plus */
123 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< I2C PB8 Fast mode plus */
124 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< I2C PB9 Fast mode plus */
125 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable I2C1 Fast mode Plus */
126 #if defined(I2C2)
127 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable I2C2 Fast mode Plus */
128 #endif /* I2C2 */
129 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast Mode Plus on PA9 */
130 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast Mode Plus on PA10 */
131 #define LL_SYSCFG_I2C_FASTMODEPLUS_PC14 SYSCFG_CFGR1_I2C_PC14_FMP /*!< Enable Fast Mode Plus on PC14 */
132 /**
133 * @}
134 */
135
136 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
137 * @{
138 */
139 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP (Hardfault) output of
140 CortexM0 with Break Input of TIM1/16/17 */
141 /**
142 * @}
143 */
144
145 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
146 * @{
147 */
148 #if defined(TIM2)
149 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBG_APB_FZ1_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
150 #endif /* TIM2 */
151 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
152 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */
153 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
154 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
155 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
156
157 /**
158 * @}
159 */
160
161 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
162 * @{
163 */
164 #define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
165 #if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
166 #define LL_DBGMCU_APB1_GRP2_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
167 #endif /* DBG_APB_FZ2_DBG_TIM14_STOP */
168 #define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
169 #define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
170
171 /* defines for legacy purpose */
172 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP LL_DBGMCU_APB1_GRP2_TIM1_STOP
173 #define LL_DBGMCU_APB2_GRP1_TIM14_STOP LL_DBGMCU_APB1_GRP2_TIM14_STOP
174 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP LL_DBGMCU_APB1_GRP2_TIM16_STOP
175 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP LL_DBGMCU_APB1_GRP2_TIM17_STOP
176 /**
177 * @}
178 */
179
180 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
181 * @{
182 */
183 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
184 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
185
186 /**
187 * @}
188 */
189
190 /** @defgroup SYSTEM_LL_PINMUX_CFG PINMUX Config
191 * @{
192 */
193 #if (DEV_ID == 0x443UL)
194 #define LL_PINMUX_SO8_PIN1_PB7 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PB7 */
195 #define LL_PINMUX_SO8_PIN1_PC14 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | \
196 SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PC14 */
197 #define LL_PINMUX_SO8_PIN4_PF2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PF2 */
198 #define LL_PINMUX_SO8_PIN4_PA0 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \
199 SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA0 */
200 #define LL_PINMUX_SO8_PIN4_PA1 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \
201 SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA1 */
202 #define LL_PINMUX_SO8_PIN4_PA2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \
203 SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA2 */
204 #define LL_PINMUX_SO8_PIN5_PA8 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA8 */
205 #define LL_PINMUX_SO8_PIN5_PA11 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \
206 SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA11 */
207 #define LL_PINMUX_SO8_PIN8_PA14 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PA14 */
208 #define LL_PINMUX_SO8_PIN8_PB6 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \
209 SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PB6 */
210 #define LL_PINMUX_SO8_PIN8_PC15 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \
211 SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PC15 */
212 #define LL_PINMUX_WLCSP12_PINE2_PA7 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | 0x00000000U) /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA7 */
213 #define LL_PINMUX_WLCSP12_PINE2_PA12 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | \
214 SYSCFG_CFGR3_PINMUX4_0) /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA12 */
215 #define LL_PINMUX_WLCSP12_PINF1_PA3 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | 0x00000000U) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA3*/
216 #define LL_PINMUX_WLCSP12_PINF1_PA4 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | \
217 SYSCFG_CFGR3_PINMUX5_0) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA4 */
218 #define LL_PINMUX_WLCSP12_PINF1_PA5 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | \
219 SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA5 */
220 #define LL_PINMUX_WLCSP12_PINF1_PA6 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | \
221 SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA6 */
222
223 #elif (DEV_ID == 0x453UL)
224 #define LL_PINMUX_WLCSP14_PINF2_PA1 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA1 */
225 #define LL_PINMUX_WLCSP14_PINF2_PA2 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | \
226 SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA2 */
227 #define LL_PINMUX_WLCSP14_PING3_PF2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PF2 */
228 #define LL_PINMUX_WLCSP14_PING3_PA0 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \
229 SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PA0 */
230 #define LL_PINMUX_WLCSP14_PINJ1_PA8 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA8 */
231 #define LL_PINMUX_WLCSP14_PINJ1_PA11 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \
232 SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA11 */
233 #define LL_PINMUX_WLCSP14_PINH2_PA5 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA5 */
234 #define LL_PINMUX_WLCSP14_PINH2_PA6 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \
235 SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA6 */
236 #define LL_PINMUX_WLCSP14_PING1_PA7 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA7 */
237 #define LL_PINMUX_WLCSP14_PING1_PA12 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | \
238 SYSCFG_CFGR3_PINMUX4_0) /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA12 */
239 #define LL_PINMUX_WLCSP14_PINJ3_PA3 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA3 */
240 #define LL_PINMUX_WLCSP14_PINJ3_PA4 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | \
241 SYSCFG_CFGR3_PINMUX5_0) /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA4 */
242
243 #elif (DEV_ID == 0x493UL)
244 #define LL_PINMUX_WLCSP19_PINH3_PF2 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C071 WLCSP19 package, PinH3 assigned to GPIO PF2 */
245 #define LL_PINMUX_WLCSP19_PINH3_PA0 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | \
246 SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C071 WLCSP19 package, PinH3 assigned to GPIO PA0 */
247 #define LL_PINMUX_WLCSP19_PINB1_PA14 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C071 WLCSP19 package, PinB1 assigned to GPIO PA14 */
248 #define LL_PINMUX_WLCSP19_PINB1_PA15 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | \
249 SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C071 WLCSP19 package, PinB1 assigned to GPIO PA15 */
250 #define LL_PINMUX_TSSOP20_PIN19_PA14 LL_PINMUX_WLCSP19_PINB1_PA14
251 #define LL_PINMUX_TSSOP20_PIN19_PA15 LL_PINMUX_WLCSP19_PINB1_PA15
252 #define LL_PINMUX_TSSOP20_PIN20_PB6 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB6 */
253 #define LL_PINMUX_TSSOP20_PIN20_PB3 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \
254 SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB3 */
255 #define LL_PINMUX_TSSOP20_PIN20_PB4 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \
256 SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB4 */
257 #define LL_PINMUX_TSSOP20_PIN20_PB5 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | \
258 SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C071 TSSOP20 package, Pin20 assigned to GPIO PB5 */
259 #define LL_PINMUX_WLCSP19_PINB3_PB7 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB7 */
260 #define LL_PINMUX_WLCSP19_PINB3_PB8 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | \
261 SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C071 WLCSP19 package, PinH2 assigned to GPIO PB8 */
262 #define LL_PINMUX_TSSOP20_PIN1_PB7 LL_PINMUX_WLCSP19_PINB3_PB7
263 #define LL_PINMUX_TSSOP20_PIN1_PB8 LL_PINMUX_WLCSP19_PINB3_PB8
264 #endif /* DEV_ID == 0x443UL */
265 /**
266 * @}
267 */
268
269 /** @defgroup SYSTEM_LL_PINMUX_SOURCE PINMUX Config Source
270 * @{
271 */
272 #if (DEV_ID == 0x443UL)
273 #define LL_PINMUX_SO8_PIN1 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C011 SO8 package, GPIO Pin1 multiplexer */
274 #define LL_PINMUX_SO8_PIN4 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C011 SO8 package, GPIO Pin4 multiplexer */
275 #define LL_PINMUX_SO8_PIN5 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C011 SO8 package, GPIO Pin5 multiplexer */
276 #define LL_PINMUX_SO8_PIN8 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C011 SO8 package, GPIO Pin8 multiplexer */
277 #define LL_PINMUX_WLCSP12_PINE2 (SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) /*!< STM32C011 WLCSP12 package, GPIO PinE2 multiplexer */
278 #define LL_PINMUX_WLCSP12_PINF1 (SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C011 WLCSP12 package, GPIO PinF1 multiplexer */
279 #elif (DEV_ID == 0x453UL)
280 #define LL_PINMUX_WLCSP14_PINF2 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C031 WLCSP14 package, GPIO PinF2 multiplexer */
281 #define LL_PINMUX_WLCSP14_PING3 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C031 WLCSP14 package, GPIO PinG3 multiplexer */
282 #define LL_PINMUX_WLCSP14_PINJ1 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C031 WLCSP14 package, GPIO PinJ1 multiplexer */
283 #define LL_PINMUX_WLCSP14_PINH2 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C031 WLCSP14 package, GPIO PinH2 multiplexer */
284 #define LL_PINMUX_WLCSP14_PING1 (SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) /*!< STM32C031 WLCSP14 package, GPIO PinG1 multiplexer */
285 #define LL_PINMUX_WLCSP14_PINJ3 (SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C031 WLCSP14 package, GPIO PinJ3 multiplexer */
286 #elif (DEV_ID == 0x493UL)
287 #define LL_PINMUX_WLCSP19_PINH3 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C071 WLCSP19 package, GPIO PinH3 multiplexer */
288 #define LL_PINMUX_WLCSP19_PINB1 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C071 WLCSP19 package, GPIO PinB1 multiplexer */
289 #define LL_PINMUX_TSSOP20_PIN19 LL_PINMUX_WLCSP19_PINB1 /*!< STM32C071 TSSOP20 package, GPIO Pin19 multiplexer */
290 #define LL_PINMUX_TSSOP20_PIN20 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C071 TSSOP20 package, GPIO Pin20 multiplexer */
291 #define LL_PINMUX_WLCSP19_PINB3 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C071 WLCSP19 package, GPIO PinB3 multiplexer */
292 #define LL_PINMUX_TSSOP20_PIN1 LL_PINMUX_WLCSP19_PINB3 /*!< STM32C071 TSSOP20 package, GPIO Pin1 multiplexer */
293 #endif /* DEV_ID == 0x443UL */
294 /**
295 * @}
296 */
297
298 /**
299 * @}
300 */
301
302 /* Exported macro ------------------------------------------------------------*/
303
304 /* Exported functions --------------------------------------------------------*/
305 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
306 * @{
307 */
308
309 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
310 * @{
311 */
312
313 /**
314 * @brief Set memory mapping at address 0x00000000
315 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
316 * @param Memory This parameter can be one of the following values:
317 * @arg @ref LL_SYSCFG_REMAP_FLASH
318 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
319 * @arg @ref LL_SYSCFG_REMAP_SRAM
320 * @retval None
321 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)322 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
323 {
324 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
325 }
326
327 /**
328 * @brief Get memory mapping at address 0x00000000
329 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
330 * @retval Returned value can be one of the following values:
331 * @arg @ref LL_SYSCFG_REMAP_FLASH
332 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
333 * @arg @ref LL_SYSCFG_REMAP_SRAM
334 */
LL_SYSCFG_GetRemapMemory(void)335 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
336 {
337 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
338 }
339
340 /**
341 * @brief Enable remap of a pin on different pad
342 * @rmtoll SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_EnablePinRemap\n
343 * SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_EnablePinRemap\n
344 * @param PinRemap This parameter can be a combination of the following values:
345 * @arg @ref LL_SYSCFG_PIN_RMP_PA11
346 * @arg @ref LL_SYSCFG_PIN_RMP_PA12
347 * @retval None
348 */
LL_SYSCFG_EnablePinRemap(uint32_t PinRemap)349 __STATIC_INLINE void LL_SYSCFG_EnablePinRemap(uint32_t PinRemap)
350 {
351 SET_BIT(SYSCFG->CFGR1, PinRemap);
352 }
353
354 /**
355 * @brief Enable remap of a pin on different pad
356 * @rmtoll SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_DisablePinRemap\n
357 * SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_DisablePinRemap\n
358 * @param PinRemap This parameter can be a combination of the following values:
359 * @arg @ref LL_SYSCFG_PIN_RMP_PA11
360 * @arg @ref LL_SYSCFG_PIN_RMP_PA12
361 * @retval None
362 */
LL_SYSCFG_DisablePinRemap(uint32_t PinRemap)363 __STATIC_INLINE void LL_SYSCFG_DisablePinRemap(uint32_t PinRemap)
364 {
365 CLEAR_BIT(SYSCFG->CFGR1, PinRemap);
366 }
367
368 /**
369 * @brief Set IR Modulation Envelope signal source.
370 * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal
371 * @param Source This parameter can be one of the following values:
372 * @arg @ref LL_SYSCFG_IR_MOD_TIM16
373 * @arg @ref LL_SYSCFG_IR_MOD_USART1
374 * @arg @ref LL_SYSCFG_IR_MOD_USART2
375 * @retval None
376 */
LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)377 __STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
378 {
379 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
380 }
381
382 /**
383 * @brief Get IR Modulation Envelope signal source.
384 * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal
385 * @retval Returned value can be one of the following values:
386 * @arg @ref LL_SYSCFG_IR_MOD_TIM16
387 * @arg @ref LL_SYSCFG_IR_MOD_USART1
388 * @arg @ref LL_SYSCFG_IR_MOD_USART2
389 */
LL_SYSCFG_GetIRModEnvelopeSignal(void)390 __STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
391 {
392 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
393 }
394
395 /**
396 * @brief Set IR Output polarity.
397 * @rmtoll SYSCFG_CFGR1 IR_POL LL_SYSCFG_SetIRPolarity
398 * @param Polarity This parameter can be one of the following values:
399 * @arg @ref LL_SYSCFG_IR_POL_INVERTED
400 * @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
401 * @retval None
402 */
LL_SYSCFG_SetIRPolarity(uint32_t Polarity)403 __STATIC_INLINE void LL_SYSCFG_SetIRPolarity(uint32_t Polarity)
404 {
405 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL, Polarity);
406 }
407
408 /**
409 * @brief Get IR Output polarity.
410 * @rmtoll SYSCFG_CFGR1 IR_POL LL_SYSCFG_GetIRPolarity
411 * @retval Returned value can be one of the following values:
412 * @arg @ref LL_SYSCFG_IR_POL_INVERTED
413 * @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
414 */
LL_SYSCFG_GetIRPolarity(void)415 __STATIC_INLINE uint32_t LL_SYSCFG_GetIRPolarity(void)
416 {
417 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL));
418 }
419
420
421 /**
422 * @brief Enable the I2C fast mode plus driving capability.
423 * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n
424 * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n
425 * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n
426 * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n
427 * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n
428 * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n
429 * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n
430 * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus
431 * SYSCFG_CFGR1 I2C_FMP_PC14 LL_SYSCFG_EnableFastModePlus
432 * @param ConfigFastModePlus This parameter can be a combination of the following values:
433 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
434 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
435 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
436 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
437 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
438 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
439 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9
440 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10
441 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PC14
442 *
443 * @retval None
444 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)445 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
446 {
447 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
448 }
449
450 /**
451 * @brief Disable the I2C fast mode plus driving capability.
452 * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n
453 * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n
454 * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n
455 * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n
456 * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n
457 * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n
458 * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n
459 * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus
460 * SYSCFG_CFGR1 I2C_FMP_PC14 LL_SYSCFG_EnableFastModePlus
461 * @param ConfigFastModePlus This parameter can be a combination of the following values:
462 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
463 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
464 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
465 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
466 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
467 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
468 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9
469 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10
470 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PC14
471 *
472 * @retval None
473 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)474 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
475 {
476 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
477 }
478
479 /**
480 * @brief Set connections to TIM1/16/17 Break inputs
481 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
482 * @param Break This parameter can be a combination of the following values:
483 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
484 * @retval None
485 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)486 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
487 {
488 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL, Break);
489 }
490
491 /**
492 * @brief Get connections to TIM1/16/17 Break inputs
493 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
494 * @retval Returned value can be can be a combination of the following values:
495 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
496 */
LL_SYSCFG_GetTIMBreakInputs(void)497 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
498 {
499 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL));
500 }
501
502 /**
503 * @brief Config PinMux
504 * @rmtoll SYSCFG_CFGR3 CLL LL_SYSCFG_ConfigPinMux\n
505 * @param mux_cfg This parameter can be a value of @ref SYSTEM_LL_PINMUX_CFG
506 * @retval None
507 */
LL_SYSCFG_ConfigPinMux(uint32_t mux_cfg)508 __STATIC_INLINE void LL_SYSCFG_ConfigPinMux(uint32_t mux_cfg)
509 {
510 MODIFY_REG(SYSCFG->CFGR3, (mux_cfg >> 16U), (mux_cfg & 0x0000FFFFU));
511 }
512
513 /**
514 * @brief Get PinMux configuration
515 * @rmtoll SYSCFG_CFGR3 CLL LL_SYSCFG_GetConfigPinMux\n
516 * @param LL_PINMUX_PACKx_PINy This parameter can be a value of @ref SYSTEM_LL_PINMUX_SOURCE
517 * @retval Returned value can be one of SYSTEM_LL_PINMUX_CFG defines
518 */
LL_SYSCFG_GetConfigPinMux(uint32_t LL_PINMUX_PACKx_PINy)519 __STATIC_INLINE uint32_t LL_SYSCFG_GetConfigPinMux(uint32_t LL_PINMUX_PACKx_PINy)
520 {
521 return (uint32_t)(READ_BIT(SYSCFG->CFGR3, LL_PINMUX_PACKx_PINy) | (LL_PINMUX_PACKx_PINy << 16U));
522 }
523
524 #if defined(SYSCFG_ITLINE0_SR_WWDG)
525 /**
526 * @brief Check if Window watchdog interrupt occurred or not.
527 * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG
528 * @retval State of bit (1 or 0).
529 */
LL_SYSCFG_IsActiveFlag_WWDG(void)530 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
531 {
532 return ((READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_WWDG) == (SYSCFG_ITLINE0_SR_WWDG)) ? 1UL : 0UL);
533 }
534 #endif /* SYSCFG_ITLINE0_SR_WWDG */
535
536 #if defined(SYSCFG_ITLINE1_SR_PVM_VDDIO2_OUT)
537 /**
538 * @brief Check if VDDIO2 supply monitoring interrupt occurred or not.
539 * @rmtoll SYSCFG_ITLINE1_SR_PVM_VDDIO2_OUT LL_SYSCFG_IsActiveFlag_PVM_VDDIO2_OUT
540 * @retval State of bit (1 or 0).
541 */
LL_SYSCFG_IsActiveFlag_PVM_VDDIO2_OUT(void)542 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVM_VDDIO2_OUT(void)
543 {
544 return ((READ_BIT(SYSCFG->IT_LINE_SR[1],
545 SYSCFG_ITLINE1_SR_PVM_VDDIO2_OUT) == (SYSCFG_ITLINE1_SR_PVM_VDDIO2_OUT)) ? 1UL : 0UL);
546 }
547 #endif /* SYSCFG_ITLINE1_SR_PVM_VDDIO2_OUT */
548
549 #if defined(SYSCFG_ITLINE2_SR_RTC)
550 /**
551 * @brief Check if RTC interrupt occurred or not (EXTI line 19).
552 * @rmtoll SYSCFG_ITLINE2 SR_RTC LL_SYSCFG_IsActiveFlag_RTC
553 * @retval State of bit (1 or 0).
554 */
LL_SYSCFG_IsActiveFlag_RTC(void)555 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC(void)
556 {
557 return ((READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC) == (SYSCFG_ITLINE2_SR_RTC)) ? 1UL : 0UL);
558 }
559 #endif /* SYSCFG_ITLINE2_SR_RTC */
560
561 #if defined(SYSCFG_ITLINE3_SR_FLASH_ITF)
562 /**
563 * @brief Check if Flash interface interrupt occurred or not.
564 * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF
565 * @retval State of bit (1 or 0).
566 */
LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)567 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
568 {
569 return ((READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)) ? 1UL : 0UL);
570 }
571 #endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */
572
573 #if defined(SYSCFG_ITLINE4_SR_RCC)
574 /**
575 * @brief Check if Reset and clock control interrupt occurred or not.
576 * @rmtoll SYSCFG_ITLINE4_SR_RCC LL_SYSCFG_IsActiveFlag_CLK_CTRL
577 * @retval State of bit (1 or 0).
578 */
LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)579 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
580 {
581 return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_RCC) == (SYSCFG_ITLINE4_SR_RCC)) ? 1UL : 0UL);
582 }
583 #endif /* SYSCFG_ITLINE4_SR_RCC */
584
585 #if defined(SYSCFG_ITLINE4_SR_CRS)
586 /**
587 * @brief Check if CRS interrupt occurred or not.
588 * @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS
589 * @retval State of bit (1 or 0).
590 */
LL_SYSCFG_IsActiveFlag_CRS(void)591 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void)
592 {
593 return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)) ? 1UL : 0UL);
594 }
595 #endif /* SYSCFG_ITLINE4_SR_CRS */
596
597 #if defined(SYSCFG_ITLINE5_SR_EXTI0)
598 /**
599 * @brief Check if EXTI line 0 interrupt occurred or not.
600 * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0
601 * @retval State of bit (1 or 0).
602 */
LL_SYSCFG_IsActiveFlag_EXTI0(void)603 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
604 {
605 return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)) ? 1UL : 0UL);
606 }
607 #endif /* SYSCFG_ITLINE5_SR_EXTI0 */
608
609 #if defined(SYSCFG_ITLINE5_SR_EXTI1)
610 /**
611 * @brief Check if EXTI line 1 interrupt occurred or not.
612 * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1
613 * @retval State of bit (1 or 0).
614 */
LL_SYSCFG_IsActiveFlag_EXTI1(void)615 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
616 {
617 return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)) ? 1UL : 0UL);
618 }
619 #endif /* SYSCFG_ITLINE5_SR_EXTI1 */
620
621 #if defined(SYSCFG_ITLINE6_SR_EXTI2)
622 /**
623 * @brief Check if EXTI line 2 interrupt occurred or not.
624 * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2
625 * @retval State of bit (1 or 0).
626 */
LL_SYSCFG_IsActiveFlag_EXTI2(void)627 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
628 {
629 return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)) ? 1UL : 0UL);
630 }
631 #endif /* SYSCFG_ITLINE6_SR_EXTI2 */
632
633 #if defined(SYSCFG_ITLINE6_SR_EXTI3)
634 /**
635 * @brief Check if EXTI line 3 interrupt occurred or not.
636 * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3
637 * @retval State of bit (1 or 0).
638 */
LL_SYSCFG_IsActiveFlag_EXTI3(void)639 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
640 {
641 return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)) ? 1UL : 0UL);
642 }
643 #endif /* SYSCFG_ITLINE6_SR_EXTI3 */
644
645 #if defined(SYSCFG_ITLINE7_SR_EXTI4)
646 /**
647 * @brief Check if EXTI line 4 interrupt occurred or not.
648 * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4
649 * @retval State of bit (1 or 0).
650 */
LL_SYSCFG_IsActiveFlag_EXTI4(void)651 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
652 {
653 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)) ? 1UL : 0UL);
654 }
655 #endif /* SYSCFG_ITLINE7_SR_EXTI4 */
656
657 #if defined(SYSCFG_ITLINE7_SR_EXTI5)
658 /**
659 * @brief Check if EXTI line 5 interrupt occurred or not.
660 * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5
661 * @retval State of bit (1 or 0).
662 */
LL_SYSCFG_IsActiveFlag_EXTI5(void)663 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
664 {
665 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)) ? 1UL : 0UL);
666 }
667 #endif /* SYSCFG_ITLINE7_SR_EXTI5 */
668
669 #if defined(SYSCFG_ITLINE7_SR_EXTI6)
670 /**
671 * @brief Check if EXTI line 6 interrupt occurred or not.
672 * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6
673 * @retval State of bit (1 or 0).
674 */
LL_SYSCFG_IsActiveFlag_EXTI6(void)675 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
676 {
677 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)) ? 1UL : 0UL);
678 }
679 #endif /* SYSCFG_ITLINE7_SR_EXTI6 */
680
681 #if defined(SYSCFG_ITLINE7_SR_EXTI7)
682 /**
683 * @brief Check if EXTI line 7 interrupt occurred or not.
684 * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7
685 * @retval State of bit (1 or 0).
686 */
LL_SYSCFG_IsActiveFlag_EXTI7(void)687 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
688 {
689 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)) ? 1UL : 0UL);
690 }
691 #endif /* SYSCFG_ITLINE7_SR_EXTI7 */
692
693 #if defined(SYSCFG_ITLINE7_SR_EXTI8)
694 /**
695 * @brief Check if EXTI line 8 interrupt occurred or not.
696 * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8
697 * @retval State of bit (1 or 0).
698 */
LL_SYSCFG_IsActiveFlag_EXTI8(void)699 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
700 {
701 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)) ? 1UL : 0UL);
702 }
703 #endif /* SYSCFG_ITLINE7_SR_EXTI8 */
704
705 #if defined(SYSCFG_ITLINE7_SR_EXTI9)
706 /**
707 * @brief Check if EXTI line 9 interrupt occurred or not.
708 * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9
709 * @retval State of bit (1 or 0).
710 */
LL_SYSCFG_IsActiveFlag_EXTI9(void)711 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
712 {
713 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)) ? 1UL : 0UL);
714 }
715 #endif /* SYSCFG_ITLINE7_SR_EXTI9 */
716
717 #if defined(SYSCFG_ITLINE7_SR_EXTI10)
718 /**
719 * @brief Check if EXTI line 10 interrupt occurred or not.
720 * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10
721 * @retval State of bit (1 or 0).
722 */
LL_SYSCFG_IsActiveFlag_EXTI10(void)723 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
724 {
725 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)) ? 1UL : 0UL);
726 }
727 #endif /* SYSCFG_ITLINE7_SR_EXTI10 */
728
729 #if defined(SYSCFG_ITLINE7_SR_EXTI11)
730 /**
731 * @brief Check if EXTI line 11 interrupt occurred or not.
732 * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11
733 * @retval State of bit (1 or 0).
734 */
LL_SYSCFG_IsActiveFlag_EXTI11(void)735 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
736 {
737 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)) ? 1UL : 0UL);
738 }
739 #endif /* SYSCFG_ITLINE7_SR_EXTI11 */
740
741 #if defined(SYSCFG_ITLINE7_SR_EXTI12)
742 /**
743 * @brief Check if EXTI line 12 interrupt occurred or not.
744 * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12
745 * @retval State of bit (1 or 0).
746 */
LL_SYSCFG_IsActiveFlag_EXTI12(void)747 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
748 {
749 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)) ? 1UL : 0UL);
750 }
751 #endif /* SYSCFG_ITLINE7_SR_EXTI12 */
752
753 #if defined(SYSCFG_ITLINE7_SR_EXTI13)
754 /**
755 * @brief Check if EXTI line 13 interrupt occurred or not.
756 * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13
757 * @retval State of bit (1 or 0).
758 */
LL_SYSCFG_IsActiveFlag_EXTI13(void)759 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
760 {
761 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)) ? 1UL : 0UL);
762 }
763 #endif /* SYSCFG_ITLINE7_SR_EXTI13 */
764
765 #if defined(SYSCFG_ITLINE7_SR_EXTI14)
766 /**
767 * @brief Check if EXTI line 14 interrupt occurred or not.
768 * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14
769 * @retval State of bit (1 or 0).
770 */
LL_SYSCFG_IsActiveFlag_EXTI14(void)771 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
772 {
773 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)) ? 1UL : 0UL);
774 }
775 #endif /* SYSCFG_ITLINE7_SR_EXTI14 */
776
777 #if defined(SYSCFG_ITLINE7_SR_EXTI15)
778 /**
779 * @brief Check if EXTI line 15 interrupt occurred or not.
780 * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15
781 * @retval State of bit (1 or 0).
782 */
LL_SYSCFG_IsActiveFlag_EXTI15(void)783 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
784 {
785 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)) ? 1UL : 0UL);
786 }
787 #endif /* SYSCFG_ITLINE7_SR_EXTI15 */
788
789 #if defined(SYSCFG_ITLINE8_SR_USB)
790 /**
791 * @brief Check if USB interrupt occurred or not.
792 * @rmtoll SYSCFG_ITLINE8_SR_USB LL_SYSCFG_IsActiveFlag_USB
793 * @retval State of bit (1 or 0).
794 */
LL_SYSCFG_IsActiveFlag_USB(void)795 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USB(void)
796 {
797 return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_USB) == (SYSCFG_ITLINE8_SR_USB)) ? 1UL : 0UL);
798 }
799 #endif /* SYSCFG_ITLINE8_SR_USB */
800
801 #if defined(SYSCFG_ITLINE9_SR_DMA1_CH1)
802 /**
803 * @brief Check if DMA1 channel 1 interrupt occurred or not.
804 * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1
805 * @retval State of bit (1 or 0).
806 */
LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)807 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
808 {
809 return ((READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)) ? 1UL : 0UL);
810 }
811 #endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */
812
813 #if defined(SYSCFG_ITLINE10_SR_DMA1_CH2)
814 /**
815 * @brief Check if DMA1 channel 2 interrupt occurred or not.
816 * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2
817 * @retval State of bit (1 or 0).
818 */
LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)819 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
820 {
821 return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)) ? 1UL : 0UL);
822 }
823 #endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */
824
825 #if defined(SYSCFG_ITLINE10_SR_DMA1_CH3)
826 /**
827 * @brief Check if DMA1 channel 3 interrupt occurred or not.
828 * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3
829 * @retval State of bit (1 or 0).
830 */
LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)831 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
832 {
833 return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)) ? 1UL : 0UL);
834 }
835 #endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */
836
837 #if defined(SYSCFG_ITLINE11_SR_DMAMUX1)
838 /**
839 * @brief Check if DMAMUX interrupt occurred or not.
840 * @rmtoll SYSCFG_ITLINE11 SR_DMAMUX1 LL_SYSCFG_IsActiveFlag_DMAMUX
841 * @retval State of bit (1 or 0).
842 */
LL_SYSCFG_IsActiveFlag_DMAMUX(void)843 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMAMUX(void)
844 {
845 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMAMUX1) == (SYSCFG_ITLINE11_SR_DMAMUX1)) ? 1UL : 0UL);
846 }
847 #endif /* SYSCFG_ITLINE11_SR_DMAMUX */
848
849 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH4)
850 /**
851 * @brief Check if DMA1_CH4 interrupt occurred or not.
852 * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4
853 * @retval State of bit (1 or 0).
854 */
LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)855 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)
856 {
857 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4)) ? 1UL : 0UL);
858 }
859 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */
860
861 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
862 /**
863 * @brief Check if DMA1_CH5 interrupt occurred or not.
864 * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5
865 * @retval State of bit (1 or 0).
866 */
LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)867 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)
868 {
869 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5)) ? 1UL : 0UL);
870 }
871 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */
872
873 #if defined(SYSCFG_ITLINE12_SR_ADC)
874 /**
875 * @brief Check if ADC interrupt occurred or not.
876 * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC
877 * @retval State of bit (1 or 0).
878 */
LL_SYSCFG_IsActiveFlag_ADC(void)879 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
880 {
881 return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)) ? 1UL : 0UL);
882 }
883 #endif /* SYSCFG_ITLINE12_SR_ADC */
884
885 #if defined(SYSCFG_ITLINE13_SR_TIM1_BRK)
886 /**
887 * @brief Check if Timer 1 break interrupt occurred or not.
888 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK
889 * @retval State of bit (1 or 0).
890 */
LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)891 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
892 {
893 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)) ? 1UL : 0UL);
894 }
895 #endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */
896
897 #if defined(SYSCFG_ITLINE13_SR_TIM1_UPD)
898 /**
899 * @brief Check if Timer 1 update interrupt occurred or not.
900 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD
901 * @retval State of bit (1 or 0).
902 */
LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)903 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
904 {
905 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)) ? 1UL : 0UL);
906 }
907 #endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */
908
909 #if defined(SYSCFG_ITLINE13_SR_TIM1_TRG)
910 /**
911 * @brief Check if Timer 1 trigger interrupt occurred or not.
912 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG
913 * @retval State of bit (1 or 0).
914 */
LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)915 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
916 {
917 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)) ? 1UL : 0UL);
918 }
919 #endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */
920
921 #if defined(SYSCFG_ITLINE13_SR_TIM1_CCU)
922 /**
923 * @brief Check if Timer 1 commutation interrupt occurred or not.
924 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU
925 * @retval State of bit (1 or 0).
926 */
LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)927 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
928 {
929 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)) ? 1UL : 0UL);
930 }
931 #endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */
932
933 #if defined(SYSCFG_ITLINE14_SR_TIM1_CC)
934 /**
935 * @brief Check if Timer 1 capture compare interrupt occurred or not.
936 * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC
937 * @retval State of bit (1 or 0).
938 */
LL_SYSCFG_IsActiveFlag_TIM1_CC(void)939 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void)
940 {
941 return ((READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC)) ? 1UL : 0UL);
942 }
943 #endif /* SYSCFG_ITLINE14_SR_TIM1_CC */
944
945 #if defined(SYSCFG_ITLINE15_SR_TIM2)
946 /**
947 * @brief Check if Timer 2 interrupt occurred or not.
948 * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2
949 * @retval State of bit (1 or 0).
950 */
LL_SYSCFG_IsActiveFlag_TIM2(void)951 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void)
952 {
953 return ((READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2) == (SYSCFG_ITLINE15_SR_TIM2)) ? 1UL : 0UL);
954 }
955 #endif /* SYSCFG_ITLINE15_SR_TIM2 */
956
957 #if defined(SYSCFG_ITLINE16_SR_TIM3_GLB)
958 /**
959 * @brief Check if Timer 3 interrupt occurred or not.
960 * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3
961 * @retval State of bit (1 or 0).
962 */
LL_SYSCFG_IsActiveFlag_TIM3(void)963 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
964 {
965 return ((READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB)) ? 1UL : 0UL);
966 }
967 #endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */
968
969 #if defined(SYSCFG_ITLINE19_SR_TIM14_GLB)
970 /**
971 * @brief Check if Timer 14 interrupt occurred or not.
972 * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14
973 * @retval State of bit (1 or 0).
974 */
LL_SYSCFG_IsActiveFlag_TIM14(void)975 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void)
976 {
977 return ((READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == \
978 (SYSCFG_ITLINE19_SR_TIM14_GLB)) ? 1UL : 0UL);
979 }
980 #endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */
981
982 #if defined(SYSCFG_ITLINE21_SR_TIM16_GLB)
983 /**
984 * @brief Check if Timer 16 interrupt occurred or not.
985 * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16
986 * @retval State of bit (1 or 0).
987 */
LL_SYSCFG_IsActiveFlag_TIM16(void)988 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
989 {
990 return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == \
991 (SYSCFG_ITLINE21_SR_TIM16_GLB)) ? 1UL : 0UL);
992 }
993 #endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */
994
995 #if defined(SYSCFG_ITLINE22_SR_TIM17_GLB)
996 /**
997 * @brief Check if Timer 17 interrupt occurred or not.
998 * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17
999 * @retval State of bit (1 or 0).
1000 */
LL_SYSCFG_IsActiveFlag_TIM17(void)1001 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void)
1002 {
1003 return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == \
1004 (SYSCFG_ITLINE22_SR_TIM17_GLB)) ? 1UL : 0UL);
1005 }
1006 #endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */
1007
1008 #if defined(SYSCFG_ITLINE23_SR_I2C1_GLB)
1009 /**
1010 * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
1011 * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1
1012 * @retval State of bit (1 or 0).
1013 */
LL_SYSCFG_IsActiveFlag_I2C1(void)1014 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
1015 {
1016 return ((READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB)) ? 1UL : 0UL);
1017 }
1018 #endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */
1019
1020 #if defined(SYSCFG_ITLINE24_SR_I2C2_GLB)
1021 /**
1022 * @brief Check if I2C2 interrupt occurred or not.
1023 * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2
1024 * @retval State of bit (1 or 0).
1025 */
LL_SYSCFG_IsActiveFlag_I2C2(void)1026 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void)
1027 {
1028 return ((READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB)) ? 1UL : 0UL);
1029 }
1030 #endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */
1031
1032 #if defined(SYSCFG_ITLINE25_SR_SPI1)
1033 /**
1034 * @brief Check if SPI1 interrupt occurred or not.
1035 * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1
1036 * @retval State of bit (1 or 0).
1037 */
LL_SYSCFG_IsActiveFlag_SPI1(void)1038 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
1039 {
1040 return ((READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)) ? 1UL : 0UL);
1041 }
1042 #endif /* SYSCFG_ITLINE25_SR_SPI1 */
1043
1044 #if defined(SYSCFG_ITLINE26_SR_SPI2)
1045 /**
1046 * @brief Check if SPI2 interrupt occurred or not.
1047 * @rmtoll SYSCFG_ITLINE26_SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2
1048 * @retval State of bit (1 or 0).
1049 */
LL_SYSCFG_IsActiveFlag_SPI2(void)1050 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void)
1051 {
1052 return ((READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)) ? 1UL : 0UL);
1053 }
1054 #endif /* SYSCFG_ITLINE26_SR_SPI2 */
1055
1056 #if defined(SYSCFG_ITLINE27_SR_USART1_GLB)
1057 /**
1058 * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25.
1059 * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1
1060 * @retval State of bit (1 or 0).
1061 */
LL_SYSCFG_IsActiveFlag_USART1(void)1062 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
1063 {
1064 return ((READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == \
1065 (SYSCFG_ITLINE27_SR_USART1_GLB)) ? 1UL : 0UL);
1066 }
1067 #endif /* SYSCFG_ITLINE27_SR_USART1_GLB */
1068
1069 #if defined(SYSCFG_ITLINE28_SR_USART2_GLB)
1070 /**
1071 * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26.
1072 * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2
1073 * @retval State of bit (1 or 0).
1074 */
LL_SYSCFG_IsActiveFlag_USART2(void)1075 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
1076 {
1077 return ((READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == \
1078 (SYSCFG_ITLINE28_SR_USART2_GLB)) ? 1UL : 0UL);
1079 }
1080 #endif /* SYSCFG_ITLINE28_SR_USART2_GLB */
1081
1082 /**
1083 * @}
1084 */
1085
1086 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1087 * @{
1088 */
1089
1090 /**
1091 * @brief Return the device identifier
1092 * @rmtoll DBG_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1093 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1094 */
LL_DBGMCU_GetDeviceID(void)1095 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1096 {
1097 return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_DEV_ID));
1098 }
1099
1100 /**
1101 * @brief Return the device revision identifier
1102 * @note This field indicates the revision of the device.
1103 * @rmtoll DBG_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1104 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1105 */
LL_DBGMCU_GetRevisionID(void)1106 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1107 {
1108 return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_REV_ID) >> DBG_IDCODE_REV_ID_Pos);
1109 }
1110
1111 /**
1112 * @brief Enable the Debug Module during STOP mode
1113 * @rmtoll DBG_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1114 * @retval None
1115 */
LL_DBGMCU_EnableDBGStopMode(void)1116 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1117 {
1118 SET_BIT(DBG->CR, DBG_CR_DBG_STOP);
1119 }
1120
1121 /**
1122 * @brief Disable the Debug Module during STOP mode
1123 * @rmtoll DBG_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1124 * @retval None
1125 */
LL_DBGMCU_DisableDBGStopMode(void)1126 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1127 {
1128 CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP);
1129 }
1130
1131 /**
1132 * @brief Enable the Debug Module during STANDBY mode
1133 * @rmtoll DBG_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1134 * @retval None
1135 */
LL_DBGMCU_EnableDBGStandbyMode(void)1136 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1137 {
1138 SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
1139 }
1140
1141 /**
1142 * @brief Disable the Debug Module during STANDBY mode
1143 * @rmtoll DBG_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1144 * @retval None
1145 */
LL_DBGMCU_DisableDBGStandbyMode(void)1146 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1147 {
1148 CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
1149 }
1150
1151 /**
1152 * @brief Freeze APB1 peripherals (group1 peripherals)
1153 * @rmtoll DBG_APB_FZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1154 * DBG_APB_FZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1155 * DBG_APB_FZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1156 * DBG_APB_FZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1157 * DBG_APB_FZ1 DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1158 * @param Periphs This parameter can be a combination of the following values:
1159 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1160 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1161 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1162 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1163 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1164 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1165 *
1166 * @retval None
1167 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1168 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1169 {
1170 SET_BIT(DBG->APBFZ1, Periphs);
1171 }
1172
1173 /**
1174 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1175 * @rmtoll DBG_APB_FZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1176 * DBG_APB_FZ1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1177 * DBG_APB_FZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1178 * DBG_APB_FZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1179 * DBG_APB_FZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1180 * DBG_APB_FZ1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1181 * @param Periphs This parameter can be a combination of the following values:
1182 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1183 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1184 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1185 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1186 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1187 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1188 *
1189 * (*) value not defined in all devices
1190 * @retval None
1191 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1192 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1193 {
1194 CLEAR_BIT(DBG->APBFZ1, Periphs);
1195 }
1196
1197 /**
1198 * @brief Freeze APB1 peripherals (group2 peripherals)
1199 * @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
1200 * DBG_APB_FZ2 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
1201 * DBG_APB_FZ2 DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
1202 * DBG_APB_FZ2 DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1203 * @param Periphs This parameter can be a combination of the following values:
1204 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
1205 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP
1206 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
1207 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
1208 *
1209 * @retval None
1210 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1211 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1212 {
1213 SET_BIT(DBG->APBFZ2, Periphs);
1214 }
1215
1216 #define LL_DBGMCU_APB2_GRP1_FreezePeriph LL_DBGMCU_APB1_GRP2_FreezePeriph /* define for legacy purpose */
1217 /**
1218 * @brief Unfreeze APB2 peripherals
1219 * @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
1220 * DBG_APB_FZ2 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
1221 * DBG_APB_FZ2 DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
1222 * DBG_APB_FZ2 DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1223 * @param Periphs This parameter can be a combination of the following values:
1224 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
1225 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP
1226 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
1227 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
1228 *
1229 * @retval None
1230 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1231 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1232 {
1233 CLEAR_BIT(DBG->APBFZ2, Periphs);
1234 }
1235
1236 #define LL_DBGMCU_APB2_GRP1_UnFreezePeriph LL_DBGMCU_APB1_GRP2_UnFreezePeriph /* define for legacy purpose */
1237 /**
1238 * @}
1239 */
1240
1241
1242 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1243 * @{
1244 */
1245
1246 /**
1247 * @brief Set FLASH Latency
1248 * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_SetLatency
1249 * @param Latency This parameter can be one of the following values:
1250 * @arg @ref LL_FLASH_LATENCY_0
1251 * @arg @ref LL_FLASH_LATENCY_1
1252 * @retval None
1253 */
LL_FLASH_SetLatency(uint32_t Latency)1254 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1255 {
1256 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1257 }
1258
1259 /**
1260 * @brief Get FLASH Latency
1261 * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_GetLatency
1262 * @retval Returned value can be one of the following values:
1263 * @arg @ref LL_FLASH_LATENCY_0
1264 * @arg @ref LL_FLASH_LATENCY_1
1265 */
LL_FLASH_GetLatency(void)1266 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1267 {
1268 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1269 }
1270
1271 /**
1272 * @brief Enable Prefetch
1273 * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_EnablePrefetch
1274 * @retval None
1275 */
LL_FLASH_EnablePrefetch(void)1276 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1277 {
1278 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1279 }
1280
1281 /**
1282 * @brief Disable Prefetch
1283 * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_DisablePrefetch
1284 * @retval None
1285 */
LL_FLASH_DisablePrefetch(void)1286 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1287 {
1288 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1289 }
1290
1291 /**
1292 * @brief Check if Prefetch buffer is enabled
1293 * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_IsPrefetchEnabled
1294 * @retval State of bit (1 or 0).
1295 */
LL_FLASH_IsPrefetchEnabled(void)1296 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1297 {
1298 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
1299 }
1300
1301 /**
1302 * @brief Enable Instruction cache
1303 * @rmtoll FLASH_ACR FLASH_ACR_ICEN LL_FLASH_EnableInstCache
1304 * @retval None
1305 */
LL_FLASH_EnableInstCache(void)1306 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1307 {
1308 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1309 }
1310
1311 /**
1312 * @brief Disable Instruction cache
1313 * @rmtoll FLASH_ACR FLASH_ACR_ICEN LL_FLASH_DisableInstCache
1314 * @retval None
1315 */
LL_FLASH_DisableInstCache(void)1316 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1317 {
1318 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1319 }
1320
1321 /**
1322 * @brief Enable Instruction cache reset
1323 * @note bit can be written only when the instruction cache is disabled
1324 * @rmtoll FLASH_ACR FLASH_ACR_ICRST LL_FLASH_EnableInstCacheReset
1325 * @retval None
1326 */
LL_FLASH_EnableInstCacheReset(void)1327 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1328 {
1329 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1330 }
1331
1332 /**
1333 * @brief Disable Instruction cache reset
1334 * @rmtoll FLASH_ACR FLASH_ACR_ICRST LL_FLASH_DisableInstCacheReset
1335 * @retval None
1336 */
LL_FLASH_DisableInstCacheReset(void)1337 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1338 {
1339 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1340 }
1341
1342 /**
1343 * @}
1344 */
1345
1346 /**
1347 * @}
1348 */
1349
1350 /**
1351 * @}
1352 */
1353
1354 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBG) */
1355
1356 /**
1357 * @}
1358 */
1359
1360 #ifdef __cplusplus
1361 }
1362 #endif
1363
1364 #endif /* STM32C0xx_LL_SYSTEM_H */
1365
