1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_i3c.h
4 * @author MCD Application Team
5 * @brief Header file of I3C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_I3C_H
21 #define STM32H5xx_LL_I3C_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (I3C1)
35
36 /** @defgroup I3C_LL I3C
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46 /** @defgroup I3C_LL_Private_Macros I3C Private Macros
47 * @{
48 */
49 /**
50 * @}
51 */
52
53 /* Exported types ------------------------------------------------------------*/
54 /** @defgroup I3C_LL_ES_CONTROLLER_BUS_CONFIG_STRUCTURE_DEFINITION I3C Controller Bus Configuration Structure definition
55 * @brief I3C LL Controller Bus Configuration Structure definition
56 * @{
57 */
58 typedef struct
59 {
60 uint32_t SDAHoldTime; /*!< Specifies the I3C SDA hold time.
61 This parameter must be a value of @ref I3C_LL_EC_SDA_HOLD_TIME */
62
63 uint32_t WaitTime; /*!< Specifies the time that the main and the new controllers should wait before
64 issuing a start.
65 This parameter must be a value of @ref I3C_LL_EC_OWN_ACTIVITY_STATE */
66
67 uint8_t SCLPPLowDuration; /*!< Specifies the I3C SCL low duration in number of kernel clock cycles
68 in I3C push-pull phases.
69 This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */
70
71 uint8_t SCLI3CHighDuration; /*!< Specifies the I3C SCL high duration in number of kernel clock cycles,
72 used for I3C messages for I3C open-drain and push pull phases.
73 This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */
74
75 uint8_t SCLODLowDuration; /*!< Specifies the I3C SCL low duration in number of kernel clock cycles in
76 open-drain phases, used for legacy I2C commands and for I3C open-drain phases.
77 This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */
78
79 uint8_t SCLI2CHighDuration; /*!< Specifies the I3C SCL high duration in number of kernel clock cycles, used
80 for legacy I2C commands.
81 This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */
82
83 uint8_t BusFreeDuration; /*!< Specifies the I3C controller duration in number of kernel clock cycles, after
84 a stop and before a start.
85 This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */
86
87 uint8_t BusIdleDuration; /*!< Specifies the I3C controller duration in number of kernel clock cycles to be
88 elapsed, after that both SDA and SCL are continuously high and stable
89 before issuing a hot-join event.
90 This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */
91 } LL_I3C_CtrlBusConfTypeDef;
92 /**
93 * @}
94 */
95
96 /** @defgroup I3C_LL_ES_TARGET_BUS_CONFIG_STRUCTURE_DEFINITION I3C Target Bus Configuration Structure definition
97 * @brief I3C LL Target Bus Configuration Structure definition
98 * @{
99 */
100 typedef struct
101 {
102 uint8_t BusAvailableDuration; /*!< Specifies the I3C target duration in number of kernel clock cycles, when
103 the SDA and the SCL are high for at least taval.
104 This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */
105 } LL_I3C_TgtBusConfTypeDef;
106 /**
107 * @}
108 */
109 #if defined(USE_FULL_LL_DRIVER)
110
111 /** @defgroup I3C_LL_ES_INIT I3C Exported Init structure
112 * @brief I3C LL Init Structure definition
113 * @{
114 */
115 typedef struct
116 {
117 LL_I3C_CtrlBusConfTypeDef CtrlBusCharacteristic; /*!< Specifies the I3C controller bus characteristic configuration
118 when Controller mode */
119
120 LL_I3C_TgtBusConfTypeDef TgtBusCharacteristic; /*!< Specifies the I3C target bus characteristic configuration
121 when Target mode */
122
123 } LL_I3C_InitTypeDef;
124 /**
125 * @}
126 */
127 #endif /* USE_FULL_LL_DRIVER */
128
129 /* Exported constants --------------------------------------------------------*/
130 /** @defgroup I3C_LL_Exported_Constants I3C Exported Constants
131 * @{
132 */
133
134 /** @defgroup I3C_LL_EC_GET_FLAG Get Flags Defines
135 * @brief Flags defines which can be used with LL_I3C_ReadReg function
136 * @{
137 */
138 #define LL_I3C_EVR_CFEF I3C_EVR_CFEF
139 #define LL_I3C_EVR_TXFEF I3C_EVR_TXFEF
140 #define LL_I3C_EVR_CFNFF I3C_EVR_CFNFF
141 #define LL_I3C_EVR_SFNEF I3C_EVR_SFNEF
142 #define LL_I3C_EVR_TXFNFF I3C_EVR_TXFNFF
143 #define LL_I3C_EVR_RXFNEF I3C_EVR_RXFNEF
144 #define LL_I3C_EVR_RXLASTF I3C_EVR_RXLASTF
145 #define LL_I3C_EVR_TXLASTF I3C_EVR_TXLASTF
146 #define LL_I3C_EVR_FCF I3C_EVR_FCF
147 #define LL_I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF
148 #define LL_I3C_EVR_ERRF I3C_EVR_ERRF
149 #define LL_I3C_EVR_IBIF I3C_EVR_IBIF
150 #define LL_I3C_EVR_IBIENDF I3C_EVR_IBIENDF
151 #define LL_I3C_EVR_CRF I3C_EVR_CRF
152 #define LL_I3C_EVR_CRUPDF I3C_EVR_CRUPDF
153 #define LL_I3C_EVR_HJF I3C_EVR_HJF
154 #define LL_I3C_EVR_WKPF I3C_EVR_WKPF
155 #define LL_I3C_EVR_GETF I3C_EVR_GETF
156 #define LL_I3C_EVR_STAF I3C_EVR_STAF
157 #define LL_I3C_EVR_DAUPDF I3C_EVR_DAUPDF
158 #define LL_I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF
159 #define LL_I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF
160 #define LL_I3C_EVR_RSTF I3C_EVR_RSTF
161 #define LL_I3C_EVR_ASUPDF I3C_EVR_ASUPDF
162 #define LL_I3C_EVR_INTUPDF I3C_EVR_INTUPDF
163 #define LL_I3C_EVR_DEFF I3C_EVR_DEFF
164 #define LL_I3C_EVR_GRPF I3C_EVR_GRPF
165 #define LL_I3C_SER_PERR I3C_SER_PERR
166 #define LL_I3C_SER_STALL I3C_SER_STALL
167 #define LL_I3C_SER_DOVR I3C_SER_DOVR
168 #define LL_I3C_SER_COVR I3C_SER_COVR
169 #define LL_I3C_SER_ANACK I3C_SER_ANACK
170 #define LL_I3C_SER_DNACK I3C_SER_DNACK
171 #define LL_I3C_SER_DERR I3C_SER_DERR
172 /**
173 * @}
174 */
175
176 /** @defgroup I3C_LL_EC_IT IT Defines
177 * @brief IT defines which can be used with LL_I3C_ReadReg and LL_I3C_WriteReg functions
178 * @{
179 */
180 #define LL_I3C_IER_CFNFIE I3C_IER_CFNFIE
181 #define LL_I3C_IER_SFNEIE I3C_IER_SFNEIE
182 #define LL_I3C_IER_TXFNFIE I3C_IER_TXFNFIE
183 #define LL_I3C_IER_RXFNEIE I3C_IER_RXFNEIE
184 #define LL_I3C_IER_FCIE I3C_IER_FCIE
185 #define LL_I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE
186 #define LL_I3C_IER_ERRIE I3C_IER_ERRIE
187 #define LL_I3C_IER_IBIIE I3C_IER_IBIIE
188 #define LL_I3C_IER_IBIENDIE I3C_IER_IBIENDIE
189 #define LL_I3C_IER_CRIE I3C_IER_CRIE
190 #define LL_I3C_IER_CRUPDIE I3C_IER_CRUPDIE
191 #define LL_I3C_IER_HJIE I3C_IER_HJIE
192 #define LL_I3C_IER_WKPIE I3C_IER_WKPIE
193 #define LL_I3C_IER_GETIE I3C_IER_GETIE
194 #define LL_I3C_IER_STAIE I3C_IER_STAIE
195 #define LL_I3C_IER_DAUPDIE I3C_IER_DAUPDIE
196 #define LL_I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE
197 #define LL_I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE
198 #define LL_I3C_IER_RSTIE I3C_IER_RSTIE
199 #define LL_I3C_IER_ASUPDIE I3C_IER_ASUPDIE
200 #define LL_I3C_IER_INTUPDIE I3C_IER_INTUPDIE
201 #define LL_I3C_IER_DEFIE I3C_IER_DEFIE
202 #define LL_I3C_IER_GRPIE I3C_IER_GRPIE
203 /**
204 * @}
205 */
206
207 /** @defgroup I3C_LL_EC_MODE MODE
208 * @{
209 */
210 #define LL_I3C_MODE_CONTROLLER I3C_CFGR_CRINIT /*!< I3C Controller mode */
211 #define LL_I3C_MODE_TARGET 0x00000000U /*!< I3C Target (Controller capable) mode */
212 /**
213 * @}
214 */
215
216 /** @defgroup I3C_LL_EC_DMA_REG_DATA DMA Register Data
217 * @{
218 */
219 #define LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE 0x00000000U /*!< Get address of data register used
220 for transmission in Byte */
221 #define LL_I3C_DMA_REG_DATA_RECEIVE_BYTE 0x00000001U /*!< Get address of data register used
222 for reception in Byte */
223 #define LL_I3C_DMA_REG_DATA_TRANSMIT_WORD 0x00000002U /*!< Get address of data register used for
224 transmission in Word */
225 #define LL_I3C_DMA_REG_DATA_RECEIVE_WORD 0x00000003U /*!< Get address of data register used
226 for reception in Word */
227 #define LL_I3C_DMA_REG_STATUS 0x00000004U /*!< Get address of status register used
228 for transfer status in Word */
229 #define LL_I3C_DMA_REG_CONTROL 0x00000005U /*!< Get address of control register used
230 for transfer control in Word */
231 /**
232 * @}
233 */
234
235 /** @defgroup I3C_LL_EC_RX_THRESHOLD RX THRESHOLD
236 * @{
237 */
238 #define LL_I3C_RXFIFO_THRESHOLD_1_4 0x00000000U
239 /*!< Rx Fifo Threshold is 1 byte in a Fifo depth of 4 bytes */
240 #define LL_I3C_RXFIFO_THRESHOLD_4_4 I3C_CFGR_RXTHRES
241 /*!< Rx Fifo Threshold is 4 bytes in a Fifo depth of 4 bytes */
242 /**
243 * @}
244 */
245
246 /** @defgroup I3C_LL_EC_TX_THRESHOLD TX THRESHOLD
247 * @{
248 */
249 #define LL_I3C_TXFIFO_THRESHOLD_1_4 0x00000000U
250 /*!< Tx Fifo Threshold is 1 byte in a Fifo depth of 4 bytes */
251 #define LL_I3C_TXFIFO_THRESHOLD_4_4 I3C_CFGR_TXTHRES
252 /*!< Tx Fifo Threshold is 4 bytes in a Fifo depth of 4 bytes */
253 /**
254 * @}
255 */
256
257 /** @defgroup I3C_LL_EC_PAYLOAD PAYLOAD
258 * @{
259 */
260 #define LL_I3C_PAYLOAD_EMPTY 0x00000000U
261 /*!< Empty payload, no additional data after IBI acknowledge */
262 #define LL_I3C_PAYLOAD_1_BYTE I3C_MAXRLR_IBIP_0
263 /*!< One additional data byte after IBI acknowledge */
264 #define LL_I3C_PAYLOAD_2_BYTES I3C_MAXRLR_IBIP_1
265 /*!< Two additional data bytes after IBI acknowledge */
266 #define LL_I3C_PAYLOAD_3_BYTES (I3C_MAXRLR_IBIP_1 | I3C_MAXRLR_IBIP_0)
267 /*!< Three additional data bytes after IBI acknowledge */
268 #define LL_I3C_PAYLOAD_4_BYTES I3C_MAXRLR_IBIP_2
269 /*!< Four additional data bytes after IBI acknowledge */
270 /**
271 * @}
272 */
273
274 /** @defgroup I3C_LL_EC_SDA_HOLD_TIME SDA HOLD TIME 0
275 * @{
276 */
277 #define LL_I3C_SDA_HOLD_TIME_0_5 0x00000000U /*!< SDA hold time is 0.5 x ti3cclk */
278 #define LL_I3C_SDA_HOLD_TIME_1_5 I3C_TIMINGR1_SDA_HD /*!< SDA hold time is 1.5 x ti3cclk */
279 /**
280 * @}
281 */
282
283 /** @defgroup I3C_LL_EC_OWN_ACTIVITY_STATE OWN ACTIVITY STATE
284 * @{
285 */
286 #define LL_I3C_OWN_ACTIVITY_STATE_0 0x00000000U
287 /*!< Own Controller Activity state 0 */
288 #define LL_I3C_OWN_ACTIVITY_STATE_1 I3C_TIMINGR1_ASNCR_0
289 /*!< Own Controller Activity state 1 */
290 #define LL_I3C_OWN_ACTIVITY_STATE_2 I3C_TIMINGR1_ASNCR_1
291 /*!< Own Controller Activity state 2 */
292 #define LL_I3C_OWN_ACTIVITY_STATE_3 (I3C_TIMINGR1_ASNCR_1 | I3C_TIMINGR1_ASNCR_0)
293 /*!< Own Controller Activity state 3 */
294 /**
295 * @}
296 */
297
298 /** @defgroup I3C_LL_EC_DEVICE_ROLE_AS DEVICE ROLE AS
299 * @{
300 */
301 #define LL_I3C_DEVICE_ROLE_AS_TARGET 0x00000000U /*!< I3C Target */
302 #define LL_I3C_DEVICE_ROLE_AS_CONTROLLER I3C_BCR_BCR6 /*!< I3C Controller */
303 /**
304 * @}
305 */
306
307 /** @defgroup I3C_LL_EC_IBI_NO_ADDITIONAL IBI NO ADDITIONAL
308 * @{
309 */
310 #define LL_I3C_IBI_NO_ADDITIONAL_DATA 0x00000000U /*!< No data byte follows the accepted IBI */
311 #define LL_I3C_IBI_ADDITIONAL_DATA I3C_BCR_BCR2 /*!< A Mandatory Data Byte (MDB)
312 follows the accepted IBI */
313 /**
314 * @}
315 */
316
317 /** @defgroup I3C_LL_EC_MAX_DATA_SPEED_LIMITATION MAX DATA SPEED LIMITATION
318 * @{
319 */
320 #define LL_I3C_NO_DATA_SPEED_LIMITATION 0x00000000U /*!< No max data speed limitation */
321 #define LL_I3C_MAX_DATA_SPEED_LIMITATION I3C_BCR_BCR0 /*!< Max data speed limitation */
322 /**
323 * @}
324 */
325
326 /** @defgroup I3C_LL_EC_IBI_MDB_READ_NOTIFICATION IBI MDB READ NOTIFICATION
327 * @{
328 */
329 #define LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION 0x00000000U
330 /*!< No support of pending read notification via the IBI MDB[7:0] value */
331 #define LL_I3C_MDB_PENDING_READ_NOTIFICATION I3C_GETCAPR_CAPPEND
332 /*!< Support of pending read notification via the IBI MDB[7:0] value */
333 /**
334 * @}
335 */
336
337 /** @defgroup I3C_LL_EC_HANDOFF_GRP_ADDR_NOT HANDOFF GRP ADDR NOT
338 * @{
339 */
340 #define LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED 0x00000000U /*!< Group Address Handoff is not supported */
341 #define LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED I3C_CRCAPR_CAPGRP /*!< Group Address Handoff is supported */
342 /**
343 * @}
344 */
345
346 /** @defgroup I3C_LL_EC_HANDOFF HANDOFF
347 * @{
348 */
349 #define LL_I3C_HANDOFF_NOT_DELAYED 0x00000000U
350 /*!< Additional time to process controllership handoff is not needed */
351 #define LL_I3C_HANDOFF_DELAYED I3C_CRCAPR_CAPDHOFF
352 /*!< Additional time to process controllership handoff is needed */
353 /**
354 * @}
355 */
356
357 /** @defgroup I3C_LL_EC_HANDOFF_ACTIVITY_STATE HANDOFF ACTIVITY STATE
358 * @{
359 */
360 #define LL_I3C_HANDOFF_ACTIVITY_STATE_0 0x00000000U
361 /*!< Indicates that will act according to Activity State 0 after controllership handoff */
362 #define LL_I3C_HANDOFF_ACTIVITY_STATE_1 I3C_GETMXDSR_HOFFAS_0
363 /*!< Indicates that will act according to Activity State 1 after controllership handoff */
364 #define LL_I3C_HANDOFF_ACTIVITY_STATE_2 I3C_GETMXDSR_HOFFAS_1
365 /*!< Indicates that will act according to Activity State 2 after controllership handoff */
366 #define LL_I3C_HANDOFF_ACTIVITY_STATE_3 (I3C_GETMXDSR_HOFFAS_1 | I3C_GETMXDSR_HOFFAS_0)
367 /*!< Indicates that will act according to Activity State 3 after controllership handoff */
368 /**
369 * @}
370 */
371
372 /** @defgroup I3C_LL_EC_GETMXDS_FORMAT GETMXDS FORMAT
373 * @{
374 */
375 #define LL_I3C_GETMXDS_FORMAT_1 0x00000000U
376 /*!< GETMXDS CCC Format 1 is used, no MaxRdTurn field in response */
377 #define LL_I3C_GETMXDS_FORMAT_2_LSB I3C_GETMXDSR_FMT_0
378 /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, LSB = RDTURN[7:0] */
379 #define LL_I3C_GETMXDS_FORMAT_2_MID I3C_GETMXDSR_FMT_1
380 /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, Middle byte = RDTURN[7:0] */
381 #define LL_I3C_GETMXDS_FORMAT_2_MSB (I3C_GETMXDSR_FMT_1 | I3C_GETMXDSR_FMT_0)
382 /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, MSB = RDTURN[7:0] */
383 /**
384 * @}
385 */
386
387 /** @defgroup I3C_LL_EC_GETMXDS_TSCO GETMXDS TSCO
388 * @{
389 */
390 #define LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS 0x00000000U /*!< clock-to-data turnaround time tSCO <= 12ns */
391 #define LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS I3C_GETMXDSR_TSCO /*!< clock-to-data turnaround time tSCO > 12ns */
392 /**
393 * @}
394 */
395
396 /** @defgroup I3C_LL_EC_BUS_ACTIVITY_STATE BUS ACTIVITY STATE
397 * @{
398 */
399 #define LL_I3C_BUS_ACTIVITY_STATE_0 0x00000000U
400 /*!< Controller on the Bus Activity State 0 */
401 #define LL_I3C_BUS_ACTIVITY_STATE_1 I3C_DEVR0_AS_0
402 /*!< Controller on the Bus Activity State 1 */
403 #define LL_I3C_BUS_ACTIVITY_STATE_2 I3C_DEVR0_AS_1
404 /*!< Controller on the Bus Activity State 2 */
405 #define LL_I3C_BUS_ACTIVITY_STATE_3 (I3C_DEVR0_AS_1 | I3C_DEVR0_AS_0)
406 /*!< Controller on the Bus Activity State 3 */
407 /**
408 * @}
409 */
410
411 /** @defgroup I3C_LL_EC_RESET_ACTION RESET ACTION
412 * @{
413 */
414 #define LL_I3C_RESET_ACTION_NONE 0x00000000U
415 /*!< No Reset Action Required */
416 #define LL_I3C_RESET_ACTION_PARTIAL I3C_DEVR0_RSTACT_0
417 /*!< Reset of some internal registers of the peripheral*/
418 #define LL_I3C_RESET_ACTION_FULL I3C_DEVR0_RSTACT_1
419 /*!< Reset all internal registers of the peripheral */
420 /**
421 * @}
422 */
423
424 /** @defgroup I3C_LL_EC_DIRECTION DIRECTION
425 * @{
426 */
427 #define LL_I3C_DIRECTION_WRITE 0x00000000U /*!< Write transfer */
428 #define LL_I3C_DIRECTION_READ I3C_CR_RNW /*!< Read transfer */
429 /**
430 * @}
431 */
432
433 /** @defgroup I3C_LL_EC_GENERATE GENERATE
434 * @{
435 */
436 #define LL_I3C_GENERATE_STOP I3C_CR_MEND
437 /*!< Generate Stop condition after sending a message */
438 #define LL_I3C_GENERATE_RESTART 0x00000000U
439 /*!< Generate Restart condition after sending a message */
440 /**
441 * @}
442 */
443
444 /** @defgroup I3C_LL_EC_CONTROLLER_MTYPE CONTROLLER MTYPE
445 * @{
446 */
447 #define LL_I3C_CONTROLLER_MTYPE_RELEASE 0x00000000U
448 /*!< SCL output clock stops running until next instruction executed */
449 #define LL_I3C_CONTROLLER_MTYPE_HEADER I3C_CR_MTYPE_0
450 /*!< Header Message */
451 #define LL_I3C_CONTROLLER_MTYPE_PRIVATE I3C_CR_MTYPE_1
452 /*!< Private Message Type */
453 #define LL_I3C_CONTROLLER_MTYPE_DIRECT (I3C_CR_MTYPE_1 | I3C_CR_MTYPE_0)
454 /*!< Direct Message Type */
455 #define LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C I3C_CR_MTYPE_2
456 /*!< Legacy I2C Message Type */
457 #define LL_I3C_CONTROLLER_MTYPE_CCC (I3C_CR_MTYPE_2 | I3C_CR_MTYPE_1)
458 /*!< Common Command Code */
459 /**
460 * @}
461 */
462
463 /** @defgroup I3C_LL_EC_TARGET_MTYPE_HOT TARGET MTYPE HOT
464 * @{
465 */
466 #define LL_I3C_TARGET_MTYPE_HOT_JOIN I3C_CR_MTYPE_3 /*!< Hot Join*/
467 #define LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ (I3C_CR_MTYPE_3 | I3C_CR_MTYPE_0) /*!< Controller-role Request */
468 #define LL_I3C_TARGET_MTYPE_IBI (I3C_CR_MTYPE_3 | I3C_CR_MTYPE_1) /*!< In Band Interrupt (IBI) */
469 /**
470 * @}
471 */
472
473 /** @defgroup I3C_LL_EC_MESSAGE MESSAGE
474 * @{
475 */
476 #define LL_I3C_MESSAGE_ERROR 0x00000000U /*!< An error has been detected in the message */
477 #define LL_I3C_MESSAGE_SUCCESS I3C_SR_OK /*!< The message ended with success */
478 /**
479 * @}
480 */
481
482 /** @defgroup I3C_LL_EC_MESSAGE_DIRECTION MESSAGE DIRECTION
483 * @{
484 */
485 #define LL_I3C_MESSAGE_DIRECTION_WRITE 0x00000000U /*!< Write data or command */
486 #define LL_I3C_MESSAGE_DIRECTION_READ I3C_SR_DIR /*!< Read data */
487 /**
488 * @}
489 */
490
491 /** @defgroup I3C_LL_EC_CONTROLLER_ERROR CONTROLLER ERROR
492 * @{
493 */
494 #define LL_I3C_CONTROLLER_ERROR_CE0 0x00000000U
495 /*!< Controller detected an illegally formatted CCC */
496 #define LL_I3C_CONTROLLER_ERROR_CE1 I3C_SER_CODERR_0
497 /*!< Controller detected that transmitted data on the bus is different than expected */
498 #define LL_I3C_CONTROLLER_ERROR_CE2 I3C_SER_CODERR_1
499 /*!< Controller detected that broadcast address 7'h7E has been nacked */
500 #define LL_I3C_CONTROLLER_ERROR_CE3 (I3C_SER_CODERR_1 | I3C_SER_CODERR_0)
501 /*!< Controller detected that new Controller did not drive the bus after Controller-role handoff */
502 /**
503 * @}
504 */
505
506 /** @defgroup I3C_LL_EC_TARGET_ERROR TARGET ERROR
507 * @{
508 */
509 #define LL_I3C_TARGET_ERROR_TE0 I3C_SER_CODERR_3
510 /*!< Target detected an invalid broadcast address */
511 #define LL_I3C_TARGET_ERROR_TE1 (I3C_SER_CODERR_3 | I3C_SER_CODERR_0)
512 /*!< Target detected an invalid CCC Code */
513 #define LL_I3C_TARGET_ERROR_TE2 (I3C_SER_CODERR_3 | I3C_SER_CODERR_1)
514 /*!< Target detected an invalid write data */
515 #define LL_I3C_TARGET_ERROR_TE3 (I3C_SER_CODERR_3 | I3C_SER_CODERR_1 | I3C_SER_CODERR_0)
516 /*!< Target detected an invalid assigned address during Dynamic Address Assignment procedure */
517 #define LL_I3C_TARGET_ERROR_TE4 (I3C_SER_CODERR_3 | I3C_SER_CODERR_2)
518 /*!< Target detected 7'h7E missing after Restart during Dynamic Address Assignment procedure */
519 #define LL_I3C_TARGET_ERROR_TE5 (I3C_SER_CODERR_3 | I3C_SER_CODERR_2 | I3C_SER_CODERR_0)
520 /*!< Target detected an illegally formatted CCC */
521 #define LL_I3C_TARGET_ERROR_TE6 (I3C_SER_CODERR_3 | I3C_SER_CODERR_2 | I3C_SER_CODERR_1)
522 /*!< Target detected that transmitted data on the bus is different than expected */
523 /**
524 * @}
525 */
526
527 /** @defgroup I3C_BCR_IN_PAYLOAD I3C BCR IN PAYLOAD
528 * @{
529 */
530 #define LL_I3C_BCR_IN_PAYLOAD_SHIFT 48 /*!< BCR field in target payload */
531 /**
532 * @}
533 */
534
535 /** @defgroup I3C_LL_EC_IBI_CAPABILITY IBI CAPABILITY
536 * @{
537 */
538 #define LL_I3C_IBI_CAPABILITY I3C_DEVRX_IBIACK
539 /*!< Controller acknowledge Target In Band Interrupt capable */
540 #define LL_I3C_IBI_NO_CAPABILITY 0x00000000U
541 /*!< Controller no acknowledge Target In Band Interrupt capable */
542 /**
543 * @}
544 */
545
546 /** @defgroup I3C_LL_EC_IBI_ADDITIONAL_DATA IBI ADDITIONAL DATA
547 * @{
548 */
549 #define LL_I3C_IBI_DATA_ENABLE I3C_DEVRX_IBIDEN
550 /*!< A mandatory data byte follows the IBI acknowledgement */
551 #define LL_I3C_IBI_DATA_DISABLE 0x00000000U
552 /*!< No mandatory data byte follows the IBI acknowledgement */
553 /**
554 * @}
555 */
556
557 /** @defgroup I3C_LL_EC_CR_CAPABILITY CR CAPABILITY
558 * @{
559 */
560 #define LL_I3C_CR_CAPABILITY I3C_DEVRX_CRACK
561 /*!< Controller acknowledge Target Controller Role capable */
562 #define LL_I3C_CR_NO_CAPABILITY 0x00000000U
563 /*!< Controller no acknowledge Target Controller Role capable */
564 /**
565 * @}
566 */
567
568 /**
569 * @}
570 */
571
572 /* Exported macro ------------------------------------------------------------*/
573 /** @defgroup I3C_LL_Exported_Macros I3C Exported Macros
574 * @{
575 */
576
577 /** @defgroup I3C_LL_EM_WRITE_READ Common Write and read registers Macros
578 * @{
579 */
580
581 /** @brief Get Bus Characterics in payload (64bits) receive during ENTDAA procedure.
582 * @param __PAYLOAD__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
583 * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF.
584 * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF.
585 */
586 #define LL_I3C_GET_BCR(__PAYLOAD__) (((uint32_t)((uint64_t)(__PAYLOAD__) >> LL_I3C_BCR_IN_PAYLOAD_SHIFT)) & \
587 I3C_BCR_BCR)
588
589 /** @brief Check IBI request capabilities.
590 * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
591 * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
592 * @retval Value of @ref I3C_LL_EC_IBI_CAPABILITY.
593 */
594 #define LL_I3C_GET_IBI_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR1_Msk) >> I3C_BCR_BCR1_Pos) == 1U) \
595 ? LL_I3C_IBI_CAPABILITY : LL_I3C_IBI_NO_CAPABILITY)
596
597 /** @brief Check IBI additional data byte capabilities.
598 * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
599 * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
600 * @retval Value of @ref I3C_LL_EC_IBI_ADDITIONAL_DATA.
601 */
602 #define LL_I3C_GET_IBI_PAYLOAD(__BCR__) (((((__BCR__) & I3C_BCR_BCR2_Msk) >> I3C_BCR_BCR2_Pos) == 1U) \
603 ? LL_I3C_IBI_DATA_ENABLE : LL_I3C_IBI_DATA_DISABLE)
604
605 /** @brief Check Controller role request capabilities.
606 * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
607 * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
608 * @retval Value of @ref I3C_LL_EC_CR_CAPABILITY.
609 */
610 #define LL_I3C_GET_CR_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR6_Msk) >> I3C_BCR_BCR6_Pos) == 1U) \
611 ? LL_I3C_CR_CAPABILITY : LL_I3C_CR_NO_CAPABILITY)
612
613 /**
614 * @brief Write a value in I3C register
615 * @param __INSTANCE__ I3C Instance
616 * @param __REG__ Register to be written
617 * @param __VALUE__ Value to be written in the register
618 * @retval None
619 */
620 #define LL_I3C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
621
622 /**
623 * @brief Read a value in I3C register
624 * @param __INSTANCE__ I3C Instance
625 * @param __REG__ Register to be read
626 * @retval Register value
627 */
628 #define LL_I3C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
629 /**
630 * @}
631 */
632
633 /**
634 * @}
635 */
636
637 /* Exported functions --------------------------------------------------------*/
638 /** @defgroup I3C_LL_Exported_Functions I3C Exported Functions
639 * @{
640 */
641
642 /** @defgroup I3C_LL_EF_Configuration Configuration
643 * @{
644 */
645
646 /**
647 * @brief Enable I3C peripheral (EN = 1).
648 * @rmtoll CFGR EN LL_I3C_Enable
649 * @param I3Cx I3C Instance.
650 * @retval None
651 */
LL_I3C_Enable(I3C_TypeDef * I3Cx)652 __STATIC_INLINE void LL_I3C_Enable(I3C_TypeDef *I3Cx)
653 {
654 SET_BIT(I3Cx->CFGR, I3C_CFGR_EN);
655 }
656
657 /**
658 * @brief Disable I3C peripheral (EN = 0).
659 * @note Controller mode: before clearing EN, all possible target requests must be disabled using DISEC CCC.
660 * Target mode: software is not expected clearing EN unless a partial reset of the IP is needed
661 * @rmtoll CFGR EN LL_I3C_Disable
662 * @param I3Cx I3C Instance.
663 * @retval None
664 */
LL_I3C_Disable(I3C_TypeDef * I3Cx)665 __STATIC_INLINE void LL_I3C_Disable(I3C_TypeDef *I3Cx)
666 {
667 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_EN);
668 }
669
670 /**
671 * @brief Check if the I3C peripheral is enabled or disabled.
672 * @rmtoll CFGR EN LL_I3C_IsEnabled
673 * @param I3Cx I3C Instance.
674 * @retval State of bit (1 or 0).
675 */
LL_I3C_IsEnabled(const I3C_TypeDef * I3Cx)676 __STATIC_INLINE uint32_t LL_I3C_IsEnabled(const I3C_TypeDef *I3Cx)
677 {
678 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_EN) == (I3C_CFGR_EN)) ? 1UL : 0UL);
679 }
680
681 /**
682 * @brief Check if Reset action is required or not required.
683 * @note This bit indicates if Reset Action field has been updated by HW upon reception
684 * of RSTACT during current frame.
685 * @rmtoll DEVR0 RSTVAL LL_I3C_IsEnabledReset
686 * @param I3Cx I3C Instance.
687 * @retval State of bit (1 or 0).
688 */
LL_I3C_IsEnabledReset(const I3C_TypeDef * I3Cx)689 __STATIC_INLINE uint32_t LL_I3C_IsEnabledReset(const I3C_TypeDef *I3Cx)
690 {
691 return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_RSTVAL) == (I3C_DEVR0_RSTVAL)) ? 1UL : 0UL);
692 }
693
694 /**
695 * @brief Configure peripheral mode.
696 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
697 * @rmtoll CFGR CRINIT LL_I3C_SetMode
698 * @param I3Cx I3C Instance.
699 * @param PeripheralMode This parameter can be one of the following values:
700 * @arg @ref LL_I3C_MODE_CONTROLLER
701 * @arg @ref LL_I3C_MODE_TARGET
702 * @retval None
703 */
LL_I3C_SetMode(I3C_TypeDef * I3Cx,uint32_t PeripheralMode)704 __STATIC_INLINE void LL_I3C_SetMode(I3C_TypeDef *I3Cx, uint32_t PeripheralMode)
705 {
706 MODIFY_REG(I3Cx->CFGR, I3C_CFGR_CRINIT, PeripheralMode);
707 }
708
709 /**
710 * @brief Get peripheral mode.
711 * @rmtoll CFGR CRINIT LL_I3C_GetMode
712 * @param I3Cx I3C Instance.
713 * @retval Returned value can be one of the following values:
714 * @arg @ref LL_I3C_MODE_CONTROLLER
715 * @arg @ref LL_I3C_MODE_TARGET
716 */
LL_I3C_GetMode(const I3C_TypeDef * I3Cx)717 __STATIC_INLINE uint32_t LL_I3C_GetMode(const I3C_TypeDef *I3Cx)
718 {
719 return (uint32_t)((READ_BIT(I3Cx->CFGR, I3C_CFGR_CRINIT) == (I3C_CFGR_CRINIT)) ? 1UL : 0UL);
720 }
721
722 /**
723 * @brief An arbitration header (7'h7E) is sent after Start in case of legacy I2C or I3C private transfers.
724 * @note This bit can be modified only when there is no frame ongoing
725 * @rmtoll CFGR NOARBH LL_I3C_EnableArbitrationHeader
726 * @param I3Cx I3C Instance.
727 * @retval None
728 */
LL_I3C_EnableArbitrationHeader(I3C_TypeDef * I3Cx)729 __STATIC_INLINE void LL_I3C_EnableArbitrationHeader(I3C_TypeDef *I3Cx)
730 {
731 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH);
732 }
733
734 /**
735 * @brief Target address is sent directly after a Start in case of legacy I2C or I3C private transfers.
736 * @note This bit can be modified only when there is no frame ongoing
737 * @rmtoll CFGR NOARBH LL_I3C_DisableArbitrationHeader
738 * @param I3Cx I3C Instance.
739 * @retval None
740 */
LL_I3C_DisableArbitrationHeader(I3C_TypeDef * I3Cx)741 __STATIC_INLINE void LL_I3C_DisableArbitrationHeader(I3C_TypeDef *I3Cx)
742 {
743 SET_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH);
744 }
745
746 /**
747 * @brief Check if the arbitration header is enabled of disabled.
748 * @rmtoll CFGR NOARBH LL_I3C_IsEnabledArbitrationHeader
749 * @param I3Cx I3C Instance.
750 * @retval State of bit (1 or 0).
751 */
LL_I3C_IsEnabledArbitrationHeader(const I3C_TypeDef * I3Cx)752 __STATIC_INLINE uint32_t LL_I3C_IsEnabledArbitrationHeader(const I3C_TypeDef *I3Cx)
753 {
754 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH) == (I3C_CFGR_NOARBH)) ? 0UL : 1UL);
755 }
756
757 /**
758 * @brief A Reset Pattern is inserted before the STOP at the end of a frame when the last CCC
759 * of the frame was RSTACT CCC.
760 * @note This bit can be modified only when there is no frame ongoing
761 * @rmtoll CFGR RSTPTRN LL_I3C_EnableResetPattern
762 * @param I3Cx I3C Instance.
763 * @retval None
764 */
LL_I3C_EnableResetPattern(I3C_TypeDef * I3Cx)765 __STATIC_INLINE void LL_I3C_EnableResetPattern(I3C_TypeDef *I3Cx)
766 {
767 SET_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN);
768 }
769
770 /**
771 * @brief A single STOP is emitted at the end of a frame.
772 * @note This bit can be modified only when there is no frame ongoing
773 * @rmtoll CFGR RSTPTRN LL_I3C_DisableResetPattern
774 * @param I3Cx I3C Instance.
775 * @retval None
776 */
LL_I3C_DisableResetPattern(I3C_TypeDef * I3Cx)777 __STATIC_INLINE void LL_I3C_DisableResetPattern(I3C_TypeDef *I3Cx)
778 {
779 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN);
780 }
781
782 /**
783 * @brief Check if Reset Pattern is enabled of disabled.
784 * @rmtoll CFGR RSTPTRN LL_I3C_IsEnabledResetPattern
785 * @param I3Cx I3C Instance.
786 * @retval State of bit (1 or 0).
787 */
LL_I3C_IsEnabledResetPattern(const I3C_TypeDef * I3Cx)788 __STATIC_INLINE uint32_t LL_I3C_IsEnabledResetPattern(const I3C_TypeDef *I3Cx)
789 {
790 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN) == (I3C_CFGR_RSTPTRN)) ? 1UL : 0UL);
791 }
792
793 /**
794 * @brief An Exit Pattern is sent after header (MTYPE = header) to program an escalation fault.
795 * @note This bit can be modified only when there is no frame ongoing
796 * @rmtoll CFGR EXITPTRN LL_I3C_EnableExitPattern
797 * @param I3Cx I3C Instance.
798 * @retval None
799 */
LL_I3C_EnableExitPattern(I3C_TypeDef * I3Cx)800 __STATIC_INLINE void LL_I3C_EnableExitPattern(I3C_TypeDef *I3Cx)
801 {
802 SET_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN);
803 }
804
805 /**
806 * @brief An Exit Pattern is not sent after header (MTYPE = header).
807 * @note This bit can be modified only when there is no frame ongoing
808 * @rmtoll CFGR EXITPTRN LL_I3C_DisableExitPattern
809 * @param I3Cx I3C Instance.
810 * @retval None
811 */
LL_I3C_DisableExitPattern(I3C_TypeDef * I3Cx)812 __STATIC_INLINE void LL_I3C_DisableExitPattern(I3C_TypeDef *I3Cx)
813 {
814 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN);
815 }
816
817 /**
818 * @brief Check if Exit Pattern is enabled or disabled.
819 * @rmtoll CFGR EXITPTRN LL_I3C_IsEnabledExitPattern
820 * @param I3Cx I3C Instance.
821 * @retval State of bit (1 or 0).
822 */
LL_I3C_IsEnabledExitPattern(const I3C_TypeDef * I3Cx)823 __STATIC_INLINE uint32_t LL_I3C_IsEnabledExitPattern(const I3C_TypeDef *I3Cx)
824 {
825 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN) == (I3C_CFGR_EXITPTRN)) ? 1UL : 0UL);
826 }
827
828 /**
829 * @brief High Keeper is enabled and will be used in place of standard Open drain Pull Up device
830 * during handoff procedures.
831 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
832 * @rmtoll CFGR HKSDAEN LL_I3C_EnableHighKeeperSDA
833 * @param I3Cx I3C Instance.
834 * @retval None
835 */
LL_I3C_EnableHighKeeperSDA(I3C_TypeDef * I3Cx)836 __STATIC_INLINE void LL_I3C_EnableHighKeeperSDA(I3C_TypeDef *I3Cx)
837 {
838 SET_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN);
839 }
840
841 /**
842 * @brief High Keeper is disabled.
843 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
844 * @rmtoll CFGR HKSDAEN LL_I3C_DisableHighKeeperSDA
845 * @param I3Cx I3C Instance.
846 * @retval None
847 */
LL_I3C_DisableHighKeeperSDA(I3C_TypeDef * I3Cx)848 __STATIC_INLINE void LL_I3C_DisableHighKeeperSDA(I3C_TypeDef *I3Cx)
849 {
850 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN);
851 }
852
853 /**
854 * @brief Check if High Keeper is enabled or disabled.
855 * @rmtoll CFGR HKSDAEN LL_I3C_IsEnabledHighKeeperSDA
856 * @param I3Cx I3C Instance.
857 * @retval State of bit (1 or 0).
858 */
LL_I3C_IsEnabledHighKeeperSDA(const I3C_TypeDef * I3Cx)859 __STATIC_INLINE uint32_t LL_I3C_IsEnabledHighKeeperSDA(const I3C_TypeDef *I3Cx)
860 {
861 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN) == (I3C_CFGR_HKSDAEN)) ? 1UL : 0UL);
862 }
863
864 /**
865 * @brief Hot Join Request is Acked. Current frame on the bus is continued.
866 * An Hot Join interrupt is sent through HJF flag.
867 * @note This bit can be used when I3C is acting as a Controller.
868 * @rmtoll CFGR HJACK LL_I3C_EnableHJAck
869 * @param I3Cx I3C Instance.
870 * @retval None
871 */
LL_I3C_EnableHJAck(I3C_TypeDef * I3Cx)872 __STATIC_INLINE void LL_I3C_EnableHJAck(I3C_TypeDef *I3Cx)
873 {
874 SET_BIT(I3Cx->CFGR, I3C_CFGR_HJACK);
875 }
876
877 /**
878 * @brief Hot Join Request is Nacked. Current frame on the bus is continued.
879 * No Hot Join interrupt is generated.
880 * @note This bit can be used when I3C is acting as a Controller.
881 * @rmtoll CFGR HJACK LL_I3C_DisableHJAck
882 * @param I3Cx I3C Instance.
883 * @retval None
884 */
LL_I3C_DisableHJAck(I3C_TypeDef * I3Cx)885 __STATIC_INLINE void LL_I3C_DisableHJAck(I3C_TypeDef *I3Cx)
886 {
887 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_HJACK);
888 }
889
890 /**
891 * @brief Check if Hot Join Request Acknowledgement is enabled or disabled.
892 * @rmtoll CFGR HJACK LL_I3C_IsEnabledHJAck
893 * @param I3Cx I3C Instance.
894 * @retval State of bit (1 or 0).
895 */
LL_I3C_IsEnabledHJAck(const I3C_TypeDef * I3Cx)896 __STATIC_INLINE uint32_t LL_I3C_IsEnabledHJAck(const I3C_TypeDef *I3Cx)
897 {
898 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_HJACK) == (I3C_CFGR_HJACK)) ? 1UL : 0UL);
899 }
900
901 /**
902 * @brief Get the data register address used for DMA transfer
903 * @rmtoll TDR TDB0 LL_I3C_DMA_GetRegAddr\n
904 * TDWR TDWR LL_I3C_DMA_GetRegAddr\n
905 * RDR RXRB0 LL_I3C_DMA_GetRegAddr\n
906 * RDWR RDWR LL_I3C_DMA_GetRegAddr\n
907 * SR SR LL_I3C_DMA_GetRegAddr\n
908 * CR CR LL_I3C_DMA_GetRegAddr
909 * @param I3Cx I3C Instance
910 * @param Direction This parameter can be one of the following values:
911 * @arg @ref LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE
912 * @arg @ref LL_I3C_DMA_REG_DATA_RECEIVE_BYTE
913 * @arg @ref LL_I3C_DMA_REG_DATA_TRANSMIT_WORD
914 * @arg @ref LL_I3C_DMA_REG_DATA_RECEIVE_WORD
915 * @arg @ref LL_I3C_DMA_REG_STATUS
916 * @arg @ref LL_I3C_DMA_REG_CONTROL
917 * @retval Address of data register
918 */
LL_I3C_DMA_GetRegAddr(const I3C_TypeDef * I3Cx,uint32_t Direction)919 __STATIC_INLINE uint32_t LL_I3C_DMA_GetRegAddr(const I3C_TypeDef *I3Cx, uint32_t Direction)
920 {
921 register uint32_t data_reg_addr;
922
923 if (Direction == LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE)
924 {
925 /* return address of TDR register */
926 data_reg_addr = (uint32_t) &(I3Cx->TDR);
927 }
928 else if (Direction == LL_I3C_DMA_REG_DATA_RECEIVE_BYTE)
929 {
930 /* return address of RDR register */
931 data_reg_addr = (uint32_t) &(I3Cx->RDR);
932 }
933 else if (Direction == LL_I3C_DMA_REG_DATA_TRANSMIT_WORD)
934 {
935 /* return address of TDWR register */
936 data_reg_addr = (uint32_t) &(I3Cx->TDWR);
937 }
938 else if (Direction == LL_I3C_DMA_REG_DATA_RECEIVE_WORD)
939 {
940 /* return address of RDWR register */
941 data_reg_addr = (uint32_t) &(I3Cx->RDWR);
942 }
943 else if (Direction == LL_I3C_DMA_REG_STATUS)
944 {
945 /* return address of SR register */
946 data_reg_addr = (uint32_t) &(I3Cx->SR);
947 }
948 else
949 {
950 /* return address of CR register */
951 data_reg_addr = (uint32_t) &(I3Cx->CR);
952 }
953
954 return data_reg_addr;
955 }
956
957 /**
958 * @brief Enable DMA FIFO reception requests.
959 * @rmtoll CFGR RXDMAEN LL_I3C_EnableDMAReq_RX
960 * @param I3Cx I3C Instance.
961 * @retval None
962 */
LL_I3C_EnableDMAReq_RX(I3C_TypeDef * I3Cx)963 __STATIC_INLINE void LL_I3C_EnableDMAReq_RX(I3C_TypeDef *I3Cx)
964 {
965 SET_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN);
966 }
967
968 /**
969 * @brief Disable DMA FIFO reception requests.
970 * @rmtoll CFGR RXDMAEN LL_I3C_DisableDMAReq_RX
971 * @param I3Cx I3C Instance.
972 * @retval None
973 */
LL_I3C_DisableDMAReq_RX(I3C_TypeDef * I3Cx)974 __STATIC_INLINE void LL_I3C_DisableDMAReq_RX(I3C_TypeDef *I3Cx)
975 {
976 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN);
977 }
978
979 /**
980 * @brief Check if DMA FIFO reception requests are enabled or disabled.
981 * @rmtoll CFGR RXDMAEN LL_I3C_IsEnabledDMAReq_RX
982 * @param I3Cx I3C Instance.
983 * @retval State of bit (1 or 0).
984 */
LL_I3C_IsEnabledDMAReq_RX(const I3C_TypeDef * I3Cx)985 __STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_RX(const I3C_TypeDef *I3Cx)
986 {
987 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN) == (I3C_CFGR_RXDMAEN)) ? 1UL : 0UL);
988 }
989
990 /**
991 * @brief Set the Receive FIFO Threshold level.
992 * @rmtoll CFGR RXTHRES LL_I3C_SetRxFIFOThreshold
993 * @param I3Cx I3C Instance.
994 * @param RxFIFOThreshold This parameter can be one of the following values:
995 * @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_4
996 * @arg @ref LL_I3C_RXFIFO_THRESHOLD_4_4
997 * @retval None
998 */
LL_I3C_SetRxFIFOThreshold(I3C_TypeDef * I3Cx,uint32_t RxFIFOThreshold)999 __STATIC_INLINE void LL_I3C_SetRxFIFOThreshold(I3C_TypeDef *I3Cx, uint32_t RxFIFOThreshold)
1000 {
1001 MODIFY_REG(I3Cx->CFGR, I3C_CFGR_RXTHRES, RxFIFOThreshold);
1002 }
1003
1004 /**
1005 * @brief Get the Receive FIFO Threshold level.
1006 * @rmtoll CFGR RXTHRES LL_I3C_GetRxFIFOThreshold
1007 * @param I3Cx I3C Instance.
1008 * @retval Returned value can be one of the following values:
1009 * @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_4
1010 * @arg @ref LL_I3C_RXFIFO_THRESHOLD_4_4
1011 */
LL_I3C_GetRxFIFOThreshold(const I3C_TypeDef * I3Cx)1012 __STATIC_INLINE uint32_t LL_I3C_GetRxFIFOThreshold(const I3C_TypeDef *I3Cx)
1013 {
1014 return (uint32_t)(READ_BIT(I3Cx->CFGR, I3C_CFGR_RXTHRES));
1015 }
1016
1017 /**
1018 * @brief Enable DMA FIFO transmission requests.
1019 * @rmtoll CFGR TXDMAEN LL_I3C_EnableDMAReq_TX
1020 * @param I3Cx I3C Instance.
1021 * @retval None
1022 */
LL_I3C_EnableDMAReq_TX(I3C_TypeDef * I3Cx)1023 __STATIC_INLINE void LL_I3C_EnableDMAReq_TX(I3C_TypeDef *I3Cx)
1024 {
1025 SET_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN);
1026 }
1027
1028 /**
1029 * @brief Disable DMA FIFO transmission requests.
1030 * @rmtoll CFGR TXDMAEN LL_I3C_DisableDMAReq_TX
1031 * @param I3Cx I3C Instance.
1032 * @retval None
1033 */
LL_I3C_DisableDMAReq_TX(I3C_TypeDef * I3Cx)1034 __STATIC_INLINE void LL_I3C_DisableDMAReq_TX(I3C_TypeDef *I3Cx)
1035 {
1036 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN);
1037 }
1038
1039 /**
1040 * @brief Check if DMA FIFO transmission requests are enabled or disabled.
1041 * @rmtoll CFGR TXDMAEN LL_I3C_IsEnabledDMAReq_TX
1042 * @param I3Cx I3C Instance.
1043 * @retval State of bit (1 or 0).
1044 */
LL_I3C_IsEnabledDMAReq_TX(const I3C_TypeDef * I3Cx)1045 __STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_TX(const I3C_TypeDef *I3Cx)
1046 {
1047 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN) == (I3C_CFGR_TXDMAEN)) ? 1UL : 0UL);
1048 }
1049
1050 /**
1051 * @brief Set the Transmit FIFO Threshold level.
1052 * @rmtoll CFGR TXTHRES LL_I3C_SetTxFIFOThreshold
1053 * @param I3Cx I3C Instance.
1054 * @param TxFIFOThreshold This parameter can be one of the following values:
1055 * @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_4
1056 * @arg @ref LL_I3C_TXFIFO_THRESHOLD_4_4
1057 * @retval None
1058 */
LL_I3C_SetTxFIFOThreshold(I3C_TypeDef * I3Cx,uint32_t TxFIFOThreshold)1059 __STATIC_INLINE void LL_I3C_SetTxFIFOThreshold(I3C_TypeDef *I3Cx, uint32_t TxFIFOThreshold)
1060 {
1061 MODIFY_REG(I3Cx->CFGR, I3C_CFGR_TXTHRES, TxFIFOThreshold);
1062 }
1063
1064 /**
1065 * @brief Get the Transmit FIFO Threshold level.
1066 * @rmtoll CFGR TXTHRES LL_I3C_GetTxFIFOThreshold
1067 * @param I3Cx I3C Instance.
1068 * @retval Returned value can be one of the following values:
1069 * @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_4
1070 * @arg @ref LL_I3C_TXFIFO_THRESHOLD_4_4
1071 * @retval State of bit (1 or 0).
1072 */
LL_I3C_GetTxFIFOThreshold(const I3C_TypeDef * I3Cx)1073 __STATIC_INLINE uint32_t LL_I3C_GetTxFIFOThreshold(const I3C_TypeDef *I3Cx)
1074 {
1075 return (uint32_t)(READ_BIT(I3Cx->CFGR, I3C_CFGR_TXTHRES));
1076 }
1077
1078 /**
1079 * @brief Enable DMA FIFO Status requests.
1080 * @rmtoll CFGR SDMAEN LL_I3C_EnableDMAReq_Status
1081 * @param I3Cx I3C Instance.
1082 * @retval None
1083 */
LL_I3C_EnableDMAReq_Status(I3C_TypeDef * I3Cx)1084 __STATIC_INLINE void LL_I3C_EnableDMAReq_Status(I3C_TypeDef *I3Cx)
1085 {
1086 SET_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN);
1087 }
1088
1089 /**
1090 * @brief Disable DMA FIFO Status requests.
1091 * @rmtoll CFGR SDMAEN LL_I3C_DisableDMAReq_Status
1092 * @param I3Cx I3C Instance.
1093 * @retval None
1094 */
LL_I3C_DisableDMAReq_Status(I3C_TypeDef * I3Cx)1095 __STATIC_INLINE void LL_I3C_DisableDMAReq_Status(I3C_TypeDef *I3Cx)
1096 {
1097 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN);
1098 }
1099
1100 /**
1101 * @brief Check if DMA FIFO Status requests are enabled or disabled.
1102 * @rmtoll CFGR SDMAEN LL_I3C_IsEnabledDMAReq_Status
1103 * @param I3Cx I3C Instance.
1104 * @retval State of bit (1 or 0).
1105 */
LL_I3C_IsEnabledDMAReq_Status(const I3C_TypeDef * I3Cx)1106 __STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_Status(const I3C_TypeDef *I3Cx)
1107 {
1108 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN) == (I3C_CFGR_SDMAEN)) ? 1UL : 0UL);
1109 }
1110
1111 /**
1112 * @brief Enable the Status FIFO.
1113 * @note Not applicable in target mode. Status FIFO always disabled in target mode.
1114 * @rmtoll CFGR SMODE LL_I3C_EnableStatusFIFO
1115 * @param I3Cx I3C Instance.
1116 * @retval None
1117 */
LL_I3C_EnableStatusFIFO(I3C_TypeDef * I3Cx)1118 __STATIC_INLINE void LL_I3C_EnableStatusFIFO(I3C_TypeDef *I3Cx)
1119 {
1120 SET_BIT(I3Cx->CFGR, I3C_CFGR_SMODE);
1121 }
1122
1123 /**
1124 * @brief Disable the Status FIFO Threshold.
1125 * @rmtoll CFGR SMODE LL_I3C_DisableStatusFIFO
1126 * @param I3Cx I3C Instance.
1127 * @retval None
1128 */
LL_I3C_DisableStatusFIFO(I3C_TypeDef * I3Cx)1129 __STATIC_INLINE void LL_I3C_DisableStatusFIFO(I3C_TypeDef *I3Cx)
1130 {
1131 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_SMODE);
1132 }
1133
1134 /**
1135 * @brief Check if the Status FIFO Threshold is enabled or disabled.
1136 * @rmtoll CFGR SMODE LL_I3C_IsEnabledStatusFIFO
1137 * @param I3Cx I3C Instance.
1138 * @retval State of bit (1 or 0).
1139 */
LL_I3C_IsEnabledStatusFIFO(const I3C_TypeDef * I3Cx)1140 __STATIC_INLINE uint32_t LL_I3C_IsEnabledStatusFIFO(const I3C_TypeDef *I3Cx)
1141 {
1142 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_SMODE) == (I3C_CFGR_SMODE)) ? 1UL : 0UL);
1143 }
1144
1145 /**
1146 * @brief Enable the Control and Transmit FIFO preloaded before starting a transfer on I3C bus.
1147 * @note Not applicable in target mode. Control FIFO always disabled in target mode.
1148 * @rmtoll CFGR TMODE LL_I3C_EnableControlFIFO
1149 * @param I3Cx I3C Instance.
1150 * @retval None
1151 */
LL_I3C_EnableControlFIFO(I3C_TypeDef * I3Cx)1152 __STATIC_INLINE void LL_I3C_EnableControlFIFO(I3C_TypeDef *I3Cx)
1153 {
1154 SET_BIT(I3Cx->CFGR, I3C_CFGR_TMODE);
1155 }
1156
1157 /**
1158 * @brief Disable the Control and Transmit FIFO preloaded before starting a transfer on I3C bus.
1159 * @rmtoll CFGR TMODE LL_I3C_DisableControlFIFO
1160 * @param I3Cx I3C Instance.
1161 * @retval None
1162 */
LL_I3C_DisableControlFIFO(I3C_TypeDef * I3Cx)1163 __STATIC_INLINE void LL_I3C_DisableControlFIFO(I3C_TypeDef *I3Cx)
1164 {
1165 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_TMODE);
1166 }
1167
1168 /**
1169 * @brief Check if the Control and Transmit FIFO preloaded is enabled or disabled.
1170 * @rmtoll CFGR TMODE LL_I3C_IsEnabledControlFIFO
1171 * @param I3Cx I3C Instance.
1172 * @retval State of bit (1 or 0).
1173 */
LL_I3C_IsEnabledControlFIFO(const I3C_TypeDef * I3Cx)1174 __STATIC_INLINE uint32_t LL_I3C_IsEnabledControlFIFO(const I3C_TypeDef *I3Cx)
1175 {
1176 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_TMODE) == (I3C_CFGR_TMODE)) ? 1UL : 0UL);
1177 }
1178
1179 /**
1180 * @brief Enable DMA FIFO Control word transfer requests.
1181 * @rmtoll CFGR CDMAEN LL_I3C_EnableDMAReq_Control
1182 * @param I3Cx I3C Instance.
1183 * @retval None
1184 */
LL_I3C_EnableDMAReq_Control(I3C_TypeDef * I3Cx)1185 __STATIC_INLINE void LL_I3C_EnableDMAReq_Control(I3C_TypeDef *I3Cx)
1186 {
1187 SET_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN);
1188 }
1189
1190 /**
1191 * @brief Disable DMA FIFO Control word transfer requests.
1192 * @rmtoll CFGR CDMAEN LL_I3C_DisableDMAReq_Control
1193 * @param I3Cx I3C Instance.
1194 * @retval None
1195 */
LL_I3C_DisableDMAReq_Control(I3C_TypeDef * I3Cx)1196 __STATIC_INLINE void LL_I3C_DisableDMAReq_Control(I3C_TypeDef *I3Cx)
1197 {
1198 CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN);
1199 }
1200
1201 /**
1202 * @brief Check if DMA FIFO Control word transfer requests are enabled or disabled.
1203 * @rmtoll CFGR CDMAEN LL_I3C_IsEnabledDMAReq_Control
1204 * @param I3Cx I3C Instance.
1205 * @retval State of bit (1 or 0).
1206 */
LL_I3C_IsEnabledDMAReq_Control(const I3C_TypeDef * I3Cx)1207 __STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_Control(const I3C_TypeDef *I3Cx)
1208 {
1209 return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN) == (I3C_CFGR_CDMAEN)) ? 1UL : 0UL);
1210 }
1211
1212 /**
1213 * @brief Set Own Dynamic Address as Valid.
1214 * @rmtoll DEVR0 DAVAL LL_I3C_EnableOwnDynAddress
1215 * @param I3Cx I3C Instance.
1216 * @retval None
1217 */
LL_I3C_EnableOwnDynAddress(I3C_TypeDef * I3Cx)1218 __STATIC_INLINE void LL_I3C_EnableOwnDynAddress(I3C_TypeDef *I3Cx)
1219 {
1220 SET_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL);
1221 }
1222
1223 /**
1224 * @brief Set Own Dynamic Address as Not-Valid.
1225 * @rmtoll DEVR0 DAVAL LL_I3C_DisableOwnDynAddress
1226 * @param I3Cx I3C Instance.
1227 * @retval None
1228 */
LL_I3C_DisableOwnDynAddress(I3C_TypeDef * I3Cx)1229 __STATIC_INLINE void LL_I3C_DisableOwnDynAddress(I3C_TypeDef *I3Cx)
1230 {
1231 CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL);
1232 }
1233
1234 /**
1235 * @brief Check if Own Dynamic address is Valid or Not-Valid.
1236 * @rmtoll DEVR0 DAVAL LL_I3C_IsEnabledOwnDynAddress
1237 * @param I3Cx I3C Instance.
1238 * @retval State of bit (1 or 0).
1239 */
LL_I3C_IsEnabledOwnDynAddress(const I3C_TypeDef * I3Cx)1240 __STATIC_INLINE uint32_t LL_I3C_IsEnabledOwnDynAddress(const I3C_TypeDef *I3Cx)
1241 {
1242 return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL) == (I3C_DEVR0_DAVAL)) ? 1UL : 0UL);
1243 }
1244
1245 /**
1246 * @brief Configure Own Dynamic Address.
1247 * @note This bit can be programmed in controller mode or during Dynamic Address procedure from current controller.
1248 * @rmtoll DEVR0 DA LL_I3C_SetOwnDynamicAddress
1249 * @param I3Cx I3C Instance.
1250 * @param OwnDynamicAddress This parameter must be a value between Min_Data=0 and Max_Data=0x7F
1251 * @retval None
1252 */
LL_I3C_SetOwnDynamicAddress(I3C_TypeDef * I3Cx,uint32_t OwnDynamicAddress)1253 __STATIC_INLINE void LL_I3C_SetOwnDynamicAddress(I3C_TypeDef *I3Cx, uint32_t OwnDynamicAddress)
1254 {
1255 MODIFY_REG(I3Cx->DEVR0, I3C_DEVR0_DA, (OwnDynamicAddress << I3C_DEVR0_DA_Pos));
1256 }
1257
1258 /**
1259 * @brief Get Own Dynamic Address.
1260 * @rmtoll DEVR0 DA LL_I3C_GetOwnDynamicAddress
1261 * @param I3Cx I3C Instance.
1262 * @retval Value between Min_Data=0 and Max_Data=0x7F
1263 */
LL_I3C_GetOwnDynamicAddress(const I3C_TypeDef * I3Cx)1264 __STATIC_INLINE uint8_t LL_I3C_GetOwnDynamicAddress(const I3C_TypeDef *I3Cx)
1265 {
1266 return (uint8_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_DA) >> I3C_DEVR0_DA_Pos);
1267 }
1268
1269 /**
1270 * @brief Set IBI procedure allowed (when the I3C is acting as target).
1271 * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1272 * @rmtoll DEVR0 IBIEN LL_I3C_EnableIBI
1273 * @param I3Cx I3C Instance.
1274 * @retval None
1275 */
LL_I3C_EnableIBI(I3C_TypeDef * I3Cx)1276 __STATIC_INLINE void LL_I3C_EnableIBI(I3C_TypeDef *I3Cx)
1277 {
1278 SET_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN);
1279 }
1280
1281 /**
1282 * @brief Set IBI procedure not-allowed (when the I3C is acting as target).
1283 * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1284 * @rmtoll DEVR0 IBIEN LL_I3C_DisableIBI
1285 * @param I3Cx I3C Instance.
1286 * @retval None
1287 */
LL_I3C_DisableIBI(I3C_TypeDef * I3Cx)1288 __STATIC_INLINE void LL_I3C_DisableIBI(I3C_TypeDef *I3Cx)
1289 {
1290 CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN);
1291 }
1292
1293 /**
1294 * @brief Check if IBI procedure is allowed or not allowed.
1295 * @rmtoll DEVR0 IBIEN LL_I3C_IsEnabledIBI
1296 * @param I3Cx I3C Instance.
1297 * @retval State of bit (1 or 0).
1298 */
LL_I3C_IsEnabledIBI(const I3C_TypeDef * I3Cx)1299 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIBI(const I3C_TypeDef *I3Cx)
1300 {
1301 return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN) == (I3C_DEVR0_IBIEN)) ? 1UL : 0UL);
1302 }
1303
1304 /**
1305 * @brief Set Controller-role Request allowed (when the I3C is acting as target).
1306 * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1307 * @rmtoll DEVR0 CREN LL_I3C_EnableControllerRoleReq
1308 * @param I3Cx I3C Instance.
1309 * @retval None
1310 */
LL_I3C_EnableControllerRoleReq(I3C_TypeDef * I3Cx)1311 __STATIC_INLINE void LL_I3C_EnableControllerRoleReq(I3C_TypeDef *I3Cx)
1312 {
1313 SET_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN);
1314 }
1315
1316 /**
1317 * @brief Set Controller-role Request as not-allowed (when the I3C is acting as target).
1318 * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1319 * @rmtoll DEVR0 CREN LL_I3C_DisableControllerRoleReq
1320 * @param I3Cx I3C Instance.
1321 * @retval None
1322 */
LL_I3C_DisableControllerRoleReq(I3C_TypeDef * I3Cx)1323 __STATIC_INLINE void LL_I3C_DisableControllerRoleReq(I3C_TypeDef *I3Cx)
1324 {
1325 CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN);
1326 }
1327
1328 /**
1329 * @brief Check if Controller-role Request is allowed or not-allowed.
1330 * @rmtoll DEVR0 CREN LL_I3C_IsEnabledControllerRoleReq
1331 * @param I3Cx I3C Instance.
1332 * @retval State of bit (1 or 0).
1333 */
LL_I3C_IsEnabledControllerRoleReq(const I3C_TypeDef * I3Cx)1334 __STATIC_INLINE uint32_t LL_I3C_IsEnabledControllerRoleReq(const I3C_TypeDef *I3Cx)
1335 {
1336 return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN) == (I3C_DEVR0_CREN)) ? 1UL : 0UL);
1337 }
1338
1339 /**
1340 * @brief Set Hot Join allowed (when the I3C is acting as target).
1341 * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1342 * @rmtoll DEVR0 HJEN LL_I3C_EnableHotJoin
1343 * @param I3Cx I3C Instance.
1344 * @retval None
1345 */
LL_I3C_EnableHotJoin(I3C_TypeDef * I3Cx)1346 __STATIC_INLINE void LL_I3C_EnableHotJoin(I3C_TypeDef *I3Cx)
1347 {
1348 SET_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN);
1349 }
1350
1351 /**
1352 * @brief Set Hot Join as not-allowed (when the I3C is acting as target).
1353 * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1354 * @rmtoll DEVR0 HJEN LL_I3C_DisableHotJoin
1355 * @param I3Cx I3C Instance.
1356 * @retval None
1357 */
LL_I3C_DisableHotJoin(I3C_TypeDef * I3Cx)1358 __STATIC_INLINE void LL_I3C_DisableHotJoin(I3C_TypeDef *I3Cx)
1359 {
1360 CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN);
1361 }
1362
1363 /**
1364 * @brief Check if Hot Join is allowed or not-allowed.
1365 * @rmtoll DEVR0 HJEN LL_I3C_IsEnabledHotJoin
1366 * @param I3Cx I3C Instance.
1367 * @retval State of bit (1 or 0).
1368 */
LL_I3C_IsEnabledHotJoin(const I3C_TypeDef * I3Cx)1369 __STATIC_INLINE uint32_t LL_I3C_IsEnabledHotJoin(const I3C_TypeDef *I3Cx)
1370 {
1371 return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN) == (I3C_DEVR0_HJEN)) ? 1UL : 0UL);
1372 }
1373
1374 /**
1375 * @brief Configure Maximum Read Length (target mode).
1376 * @note Those bits can be updated by HW upon reception of GETMRL CCC.
1377 * @rmtoll MAXRLR MRL LL_I3C_SetMaxReadLength
1378 * @param I3Cx I3C Instance.
1379 * @param MaxReadLength This parameter must be a value between Min_Data=0x0 and Max_Data=0xFFFF
1380 * @retval None
1381 */
LL_I3C_SetMaxReadLength(I3C_TypeDef * I3Cx,uint16_t MaxReadLength)1382 __STATIC_INLINE void LL_I3C_SetMaxReadLength(I3C_TypeDef *I3Cx, uint16_t MaxReadLength)
1383 {
1384 MODIFY_REG(I3Cx->MAXRLR, I3C_MAXRLR_MRL, MaxReadLength);
1385 }
1386
1387 /**
1388 * @brief Return Maximum Read Length (target mode).
1389 * @rmtoll MAXRLR MRL LL_I3C_GetMaxReadLength
1390 * @param I3Cx I3C Instance.
1391 * @retval Value between Min_Data=0x0 and Max_Data=0xFFFFF
1392 */
LL_I3C_GetMaxReadLength(const I3C_TypeDef * I3Cx)1393 __STATIC_INLINE uint32_t LL_I3C_GetMaxReadLength(const I3C_TypeDef *I3Cx)
1394 {
1395 return (uint32_t)(READ_BIT(I3Cx->MAXRLR, I3C_MAXRLR_MRL));
1396 }
1397
1398 /**
1399 * @brief Configure the number of additional Mandatory Data Byte (MDB) sent to the controller
1400 * after an acknowledge of the IBI (target mode).
1401 * @rmtoll MAXRLR IBIP LL_I3C_ConfigNbIBIAddData
1402 * @param I3Cx I3C Instance.
1403 * @param NbIBIAddData This parameter can be one of the following values:
1404 * @arg @ref LL_I3C_PAYLOAD_EMPTY
1405 * @arg @ref LL_I3C_PAYLOAD_1_BYTE
1406 * @arg @ref LL_I3C_PAYLOAD_2_BYTES
1407 * @arg @ref LL_I3C_PAYLOAD_3_BYTES
1408 * @arg @ref LL_I3C_PAYLOAD_4_BYTES
1409 * @retval None
1410 */
LL_I3C_ConfigNbIBIAddData(I3C_TypeDef * I3Cx,uint32_t NbIBIAddData)1411 __STATIC_INLINE void LL_I3C_ConfigNbIBIAddData(I3C_TypeDef *I3Cx, uint32_t NbIBIAddData)
1412 {
1413 MODIFY_REG(I3Cx->MAXRLR, I3C_MAXRLR_IBIP, NbIBIAddData);
1414 }
1415
1416 /**
1417 * @brief Return the number of additional Mandatory Data Byte (MDB) sent to the controller
1418 * after an acknowledge of the IBI (target mode).
1419 * @rmtoll MAXRLR IBIP LL_I3C_GetConfigNbIBIAddData
1420 * @param I3Cx I3C Instance.
1421 * @retval Returned value can be one of the following values:
1422 * @arg @ref LL_I3C_PAYLOAD_EMPTY
1423 * @arg @ref LL_I3C_PAYLOAD_1_BYTE
1424 * @arg @ref LL_I3C_PAYLOAD_2_BYTES
1425 * @arg @ref LL_I3C_PAYLOAD_3_BYTES
1426 * @arg @ref LL_I3C_PAYLOAD_4_BYTES
1427 */
LL_I3C_GetConfigNbIBIAddData(const I3C_TypeDef * I3Cx)1428 __STATIC_INLINE uint32_t LL_I3C_GetConfigNbIBIAddData(const I3C_TypeDef *I3Cx)
1429 {
1430 return (uint32_t)(READ_BIT(I3Cx->MAXRLR, I3C_MAXRLR_IBIP));
1431 }
1432
1433 /**
1434 * @brief Configure Maximum Write Length (target mode).
1435 * @note Those bits can be updated by HW upon reception of GETMWL CCC.
1436 * @rmtoll MAXWLR MWL LL_I3C_SetMaxWriteLength
1437 * @param I3Cx I3C Instance.
1438 * @param MaxWriteLength This parameter must be a value between Min_Data=0x0 and Max_Data=0xFFFF
1439 * @retval None
1440 */
LL_I3C_SetMaxWriteLength(I3C_TypeDef * I3Cx,uint16_t MaxWriteLength)1441 __STATIC_INLINE void LL_I3C_SetMaxWriteLength(I3C_TypeDef *I3Cx, uint16_t MaxWriteLength)
1442 {
1443 MODIFY_REG(I3Cx->MAXWLR, I3C_MAXWLR_MWL, MaxWriteLength);
1444 }
1445
1446 /**
1447 * @brief Return Maximum Write Length (target mode).
1448 * @rmtoll MAXWLR MWL LL_I3C_GetMaxWriteLength
1449 * @param I3Cx I3C Instance.
1450 * @retval Value between Min_Data=0x0 and Max_Data=0xFFFFF
1451 */
LL_I3C_GetMaxWriteLength(const I3C_TypeDef * I3Cx)1452 __STATIC_INLINE uint32_t LL_I3C_GetMaxWriteLength(const I3C_TypeDef *I3Cx)
1453 {
1454 return (uint32_t)(READ_BIT(I3Cx->MAXWLR, I3C_MAXWLR_MWL));
1455 }
1456
1457 /**
1458 * @brief Configure the SCL clock signal waveform.
1459 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
1460 *
1461 * @note This parameter is computed with the STM32CubeMX Tool.
1462 * @rmtoll TIMINGR0 TIMINGR0 LL_I3C_ConfigClockWaveForm
1463 * @param I3Cx I3C Instance.
1464 * @param ClockWaveForm This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
1465 * @retval None
1466 */
LL_I3C_ConfigClockWaveForm(I3C_TypeDef * I3Cx,uint32_t ClockWaveForm)1467 __STATIC_INLINE void LL_I3C_ConfigClockWaveForm(I3C_TypeDef *I3Cx, uint32_t ClockWaveForm)
1468 {
1469 WRITE_REG(I3Cx->TIMINGR0, ClockWaveForm);
1470 }
1471
1472 /**
1473 * @brief Get the SCL clock signal waveform.
1474 * @rmtoll TIMINGR0 TIMINGR0 LL_I3C_GetClockWaveForm
1475 * @param I3Cx I3C Instance.
1476 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF.
1477 */
LL_I3C_GetClockWaveForm(const I3C_TypeDef * I3Cx)1478 __STATIC_INLINE uint32_t LL_I3C_GetClockWaveForm(const I3C_TypeDef *I3Cx)
1479 {
1480 return (uint32_t)(READ_REG(I3Cx->TIMINGR0));
1481 }
1482
1483 /**
1484 * @brief Configure the SCL clock low period during I3C push-pull phases.
1485 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
1486 *
1487 * @note This parameter is computed with the STM32CubeMX Tool.
1488 * @rmtoll TIMINGR0 SCLL_PP LL_I3C_SetPeriodClockLowPP
1489 * @param I3Cx I3C Instance.
1490 * @param PeriodClockLowPP This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1491 * @retval None
1492 */
LL_I3C_SetPeriodClockLowPP(I3C_TypeDef * I3Cx,uint32_t PeriodClockLowPP)1493 __STATIC_INLINE void LL_I3C_SetPeriodClockLowPP(I3C_TypeDef *I3Cx, uint32_t PeriodClockLowPP)
1494 {
1495 MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_PP, (PeriodClockLowPP << I3C_TIMINGR0_SCLL_PP_Pos));
1496 }
1497
1498 /**
1499 * @brief Get the SCL clock low period during I3C push-pull phases.
1500 * @rmtoll TIMINGR0 SCLL_PP LL_I3C_GetPeriodClockLowPP
1501 * @param I3Cx I3C Instance.
1502 * @retval Value between Min_Data=0 and Max_Data=0xFF.
1503 */
LL_I3C_GetPeriodClockLowPP(const I3C_TypeDef * I3Cx)1504 __STATIC_INLINE uint32_t LL_I3C_GetPeriodClockLowPP(const I3C_TypeDef *I3Cx)
1505 {
1506 return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_PP) >> I3C_TIMINGR0_SCLL_PP_Pos);
1507 }
1508
1509 /**
1510 * @brief Configure the SCL clock High period during I3C open drain and push-pull phases.
1511 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
1512 *
1513 * @note This parameter is computed with the STM32CubeMX Tool.
1514 * @rmtoll TIMINGR0 SCLH_I3C LL_I3C_SetPeriodClockHighI3C
1515 * @param I3Cx I3C Instance.
1516 * @param PeriodClockHighI3C This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1517 * @retval None
1518 */
LL_I3C_SetPeriodClockHighI3C(I3C_TypeDef * I3Cx,uint32_t PeriodClockHighI3C)1519 __STATIC_INLINE void LL_I3C_SetPeriodClockHighI3C(I3C_TypeDef *I3Cx, uint32_t PeriodClockHighI3C)
1520 {
1521 MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I3C, (PeriodClockHighI3C << I3C_TIMINGR0_SCLH_I3C_Pos));
1522 }
1523
1524 /**
1525 * @brief Get the SCL clock high period during I3C open drain and push-pull phases.
1526 * @rmtoll TIMINGR0 SCLH_I3C LL_I3C_GetPeriodClockHighI3C
1527 * @param I3Cx I3C Instance.
1528 * @retval Value between Min_Data=0 and Max_Data=0xFF.
1529 */
LL_I3C_GetPeriodClockHighI3C(const I3C_TypeDef * I3Cx)1530 __STATIC_INLINE uint32_t LL_I3C_GetPeriodClockHighI3C(const I3C_TypeDef *I3Cx)
1531 {
1532 return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I3C) >> I3C_TIMINGR0_SCLH_I3C_Pos);
1533 }
1534
1535 /**
1536 * @brief Configure the SCL clock low period during I3C open drain phases.
1537 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
1538 *
1539 * @note This parameter is computed with the STM32CubeMX Tool.
1540 * @rmtoll TIMINGR0 SCLL_OD LL_I3C_SetPeriodClockLowOD
1541 * @param I3Cx I3C Instance.
1542 * @param PeriodClockLowOD This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1543 * @retval None
1544 */
LL_I3C_SetPeriodClockLowOD(I3C_TypeDef * I3Cx,uint32_t PeriodClockLowOD)1545 __STATIC_INLINE void LL_I3C_SetPeriodClockLowOD(I3C_TypeDef *I3Cx, uint32_t PeriodClockLowOD)
1546 {
1547 MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_OD, (PeriodClockLowOD << I3C_TIMINGR0_SCLL_OD_Pos));
1548 }
1549
1550 /**
1551 * @brief Get the SCL clock low period during I3C open phases.
1552 * @rmtoll TIMINGR0 SCLL_OD LL_I3C_GetPeriodClockLowOD
1553 * @param I3Cx I3C Instance.
1554 * @retval Value between Min_Data=0 and Max_Data=0xFF.
1555 */
LL_I3C_GetPeriodClockLowOD(const I3C_TypeDef * I3Cx)1556 __STATIC_INLINE uint32_t LL_I3C_GetPeriodClockLowOD(const I3C_TypeDef *I3Cx)
1557 {
1558 return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_OD) >> I3C_TIMINGR0_SCLL_OD_Pos);
1559 }
1560
1561 /**
1562 * @brief Configure the SCL clock High period during I2C open drain phases.
1563 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
1564 *
1565 * @note This parameter is computed with the STM32CubeMX Tool.
1566 * @rmtoll TIMINGR0 SCLH_I2C LL_I3C_SetPeriodClockHighI2C
1567 * @param I3Cx I3C Instance.
1568 * @param PeriodClockHighI2C This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1569 * @retval None
1570 */
LL_I3C_SetPeriodClockHighI2C(I3C_TypeDef * I3Cx,uint32_t PeriodClockHighI2C)1571 __STATIC_INLINE void LL_I3C_SetPeriodClockHighI2C(I3C_TypeDef *I3Cx, uint32_t PeriodClockHighI2C)
1572 {
1573 MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I2C, PeriodClockHighI2C << I3C_TIMINGR0_SCLH_I2C_Pos);
1574 }
1575
1576 /**
1577 * @brief Get the SCL clock high period during I2C open drain phases.
1578 * @rmtoll TIMINGR0 SCLH_I2C LL_I3C_GetPeriodClockHighI2C
1579 * @param I3Cx I3C Instance.
1580 * @retval Value between Min_Data=0 and Max_Data=0xFF.
1581 */
LL_I3C_GetPeriodClockHighI2C(const I3C_TypeDef * I3Cx)1582 __STATIC_INLINE uint32_t LL_I3C_GetPeriodClockHighI2C(const I3C_TypeDef *I3Cx)
1583 {
1584 return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I2C) >> I3C_TIMINGR0_SCLH_I2C_Pos);
1585 }
1586
1587 /**
1588 * @brief Configure the Controller additional hold time on SDA line.
1589 * @rmtoll TIMINGR1 SDA_HD LL_I3C_SetDataHoldTime
1590 * @param I3Cx I3C Instance.
1591 * @param DataHoldTime This parameter can be one of the following values:
1592 * @arg @ref LL_I3C_SDA_HOLD_TIME_0_5
1593 * @arg @ref LL_I3C_SDA_HOLD_TIME_1_5
1594 * @retval None
1595 */
LL_I3C_SetDataHoldTime(I3C_TypeDef * I3Cx,uint32_t DataHoldTime)1596 __STATIC_INLINE void LL_I3C_SetDataHoldTime(I3C_TypeDef *I3Cx, uint32_t DataHoldTime)
1597 {
1598 MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_SDA_HD, DataHoldTime);
1599 }
1600
1601 /**
1602 * @brief Get the Controller additional hold time on SDA line.
1603 * @rmtoll TIMINGR1 SDA_HD LL_I3C_GetDataHoldTime
1604 * @param I3Cx I3C Instance.
1605 * @retval Returned value can be one of the following values:
1606 * @arg @ref LL_I3C_SDA_HOLD_TIME_0_5
1607 * @arg @ref LL_I3C_SDA_HOLD_TIME_1_5
1608 */
LL_I3C_GetDataHoldTime(const I3C_TypeDef * I3Cx)1609 __STATIC_INLINE uint32_t LL_I3C_GetDataHoldTime(const I3C_TypeDef *I3Cx)
1610 {
1611 return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_SDA_HD));
1612 }
1613
1614 /**
1615 * @brief Configure the Idle, Available state.
1616 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
1617 *
1618 * @note This parameter is computed with the STM32CubeMX Tool.
1619 * @rmtoll TIMINGR1 AVAL LL_I3C_SetAvalTiming
1620 * @param I3Cx I3C Instance.
1621 * @param AvalTiming This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1622 * @retval None
1623 */
LL_I3C_SetAvalTiming(I3C_TypeDef * I3Cx,uint32_t AvalTiming)1624 __STATIC_INLINE void LL_I3C_SetAvalTiming(I3C_TypeDef *I3Cx, uint32_t AvalTiming)
1625 {
1626 MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL, (AvalTiming << I3C_TIMINGR1_AVAL_Pos));
1627 }
1628
1629 /**
1630 * @brief Get the Idle, Available integer value state.
1631 * @rmtoll TIMINGR1 AVAL LL_I3C_GetAvalTiming
1632 * @param I3Cx I3C Instance.
1633 * @retval Value between Min_Data=0 and Max_Data=0xFF.
1634 */
LL_I3C_GetAvalTiming(const I3C_TypeDef * I3Cx)1635 __STATIC_INLINE uint32_t LL_I3C_GetAvalTiming(const I3C_TypeDef *I3Cx)
1636 {
1637 return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL) >> I3C_TIMINGR1_AVAL_Pos);
1638 }
1639
1640 /**
1641 * @brief Configure the Free state.
1642 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
1643 *
1644 * @note This parameter is computed with the STM32CubeMX Tool.
1645 * @rmtoll TIMINGR1 FREE LL_I3C_SetFreeTiming
1646 * @param I3Cx I3C Instance.
1647 * @param FreeTiming This parameter must be a value between Min_Data=0 and Max_Data=0x3F.
1648 * @retval None
1649 */
LL_I3C_SetFreeTiming(I3C_TypeDef * I3Cx,uint32_t FreeTiming)1650 __STATIC_INLINE void LL_I3C_SetFreeTiming(I3C_TypeDef *I3Cx, uint32_t FreeTiming)
1651 {
1652 MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_FREE, (FreeTiming << I3C_TIMINGR1_FREE_Pos));
1653 }
1654
1655 /**
1656 * @brief Get the Free integeter value state.
1657 * @rmtoll TIMINGR1 FREE LL_I3C_GetFreeTiming
1658 * @param I3Cx I3C Instance.
1659 * @retval Value between Min_Data=0 and Max_Data=0x3F.
1660 */
LL_I3C_GetFreeTiming(const I3C_TypeDef * I3Cx)1661 __STATIC_INLINE uint32_t LL_I3C_GetFreeTiming(const I3C_TypeDef *I3Cx)
1662 {
1663 return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_FREE) >> I3C_TIMINGR1_FREE_Pos);
1664 }
1665
1666 /**
1667 * @brief Configure the activity state of the new controller.
1668 * @note Refer to MIPI I3C specification (https:__www.mipi.org_specifications)
1669 * for more details related to Activity State.
1670 * @rmtoll TIMINGR1 ASNCR LL_I3C_SetControllerActivityState
1671 * @param I3Cx I3C Instance.
1672 * @param ControllerActivityState This parameter can be one of the following values:
1673 * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_0
1674 * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_1
1675 * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_2
1676 * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_3
1677 * @retval None
1678 */
LL_I3C_SetControllerActivityState(I3C_TypeDef * I3Cx,uint32_t ControllerActivityState)1679 __STATIC_INLINE void LL_I3C_SetControllerActivityState(I3C_TypeDef *I3Cx, uint32_t ControllerActivityState)
1680 {
1681 MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_ASNCR, ControllerActivityState);
1682 }
1683
1684 /**
1685 * @brief Get the activity state of the new controller.
1686 * @note Refer to MIPI I3C specification (https:__www.mipi.org_specifications)
1687 * for more details related to Activity State.
1688 * @rmtoll TIMINGR1 ASNCR LL_I3C_GetControllerActivityState
1689 * @param I3Cx I3C Instance.
1690 * @retval Returned value can be one of the following values:
1691 * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_0
1692 * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_1
1693 * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_2
1694 * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_3
1695 */
LL_I3C_GetControllerActivityState(const I3C_TypeDef * I3Cx)1696 __STATIC_INLINE uint32_t LL_I3C_GetControllerActivityState(const I3C_TypeDef *I3Cx)
1697 {
1698 return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_ASNCR));
1699 }
1700
1701 /**
1702 * @brief Configure the Controller SDA Hold time, Bus Free, Activity state, Idle state.
1703 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
1704 *
1705 * @note This parameter is computed with the STM32CubeMX Tool.
1706 * @rmtoll TIMINGR1 SDA_HD LL_I3C_SetCtrlBusCharacteristic\n
1707 * TIMINGR1 FREE LL_I3C_SetCtrlBusCharacteristic\n
1708 * TIMINGR1 ASNCR LL_I3C_SetCtrlBusCharacteristic\n
1709 * TIMINGR1 IDLE LL_I3C_SetCtrlBusCharacteristic
1710 * @param I3Cx I3C Instance.
1711 * @param CtrlBusCharacteristic This parameter must be a value between Min_Data=0 and Max_Data=0x107F03FF.
1712 * @retval None
1713 */
LL_I3C_SetCtrlBusCharacteristic(I3C_TypeDef * I3Cx,uint32_t CtrlBusCharacteristic)1714 __STATIC_INLINE void LL_I3C_SetCtrlBusCharacteristic(I3C_TypeDef *I3Cx, uint32_t CtrlBusCharacteristic)
1715 {
1716 WRITE_REG(I3Cx->TIMINGR1, CtrlBusCharacteristic);
1717 }
1718
1719 /**
1720 * @brief Get the Controller SDA Hold time, Bus Free, Activity state, Idle state.
1721 * @rmtoll TIMINGR1 SDA_HD LL_I3C_GetCtrlBusCharacteristic\n
1722 * TIMINGR1 FREE LL_I3C_GetCtrlBusCharacteristic\n
1723 * TIMINGR1 ASNCR LL_I3C_GetCtrlBusCharacteristic\n
1724 * TIMINGR1 IDLE LL_I3C_GetCtrlBusCharacteristic
1725 * @param I3Cx I3C Instance.
1726 * @retval Value between Min_Data=0 and Max_Data=0x107F03FF.
1727 */
LL_I3C_GetCtrlBusCharacteristic(const I3C_TypeDef * I3Cx)1728 __STATIC_INLINE uint32_t LL_I3C_GetCtrlBusCharacteristic(const I3C_TypeDef *I3Cx)
1729 {
1730 return (uint32_t)(READ_REG(I3Cx->TIMINGR1));
1731 }
1732
1733 /**
1734 * @brief Configure the Target Available state.
1735 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
1736 *
1737 * @note This parameter is computed with the STM32CubeMX Tool.
1738 * @rmtoll TIMINGR1 IDLE LL_I3C_SetTgtBusCharacteristic
1739 * @param I3Cx I3C Instance.
1740 * @param TgtBusCharacteristic This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1741 * @retval None
1742 */
LL_I3C_SetTgtBusCharacteristic(I3C_TypeDef * I3Cx,uint32_t TgtBusCharacteristic)1743 __STATIC_INLINE void LL_I3C_SetTgtBusCharacteristic(I3C_TypeDef *I3Cx, uint32_t TgtBusCharacteristic)
1744 {
1745 MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL, (TgtBusCharacteristic & I3C_TIMINGR1_AVAL));
1746 }
1747
1748 /**
1749 * @brief Get the Target Available state.
1750 * @rmtoll TIMINGR1 IDLE LL_I3C_GetTgtBusCharacteristic
1751 * @param I3Cx I3C Instance.
1752 * @retval Value between Min_Data=0 and Max_Data=0xFF.
1753 */
LL_I3C_GetTgtBusCharacteristic(const I3C_TypeDef * I3Cx)1754 __STATIC_INLINE uint32_t LL_I3C_GetTgtBusCharacteristic(const I3C_TypeDef *I3Cx)
1755 {
1756 return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL));
1757 }
1758
1759 /**
1760 * @brief Configure the SCL clock stalling time on I3C Bus (controller mode).
1761 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
1762 *
1763 * @note This parameter is computed with the STM32CubeMX Tool.
1764 * @rmtoll TIMINGR2 STALL LL_I3C_SetStallTime
1765 * @param I3Cx I3C Instance.
1766 * @param ControllerStallTime This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1767 * @retval None
1768 */
LL_I3C_SetStallTime(I3C_TypeDef * I3Cx,uint32_t ControllerStallTime)1769 __STATIC_INLINE void LL_I3C_SetStallTime(I3C_TypeDef *I3Cx, uint32_t ControllerStallTime)
1770 {
1771 MODIFY_REG(I3Cx->TIMINGR2, I3C_TIMINGR2_STALL, (ControllerStallTime << I3C_TIMINGR2_STALL_Pos));
1772 }
1773
1774 /**
1775 * @brief Get the SCL clock stalling time on I3C Bus (controller mode).
1776 * @rmtoll TIMINGR2 STALL LL_I3C_GetStallTime
1777 * @param I3Cx I3C Instance.
1778 * @retval Value between Min_Data=0 and Max_Data=0xFF.
1779 */
LL_I3C_GetStallTime(const I3C_TypeDef * I3Cx)1780 __STATIC_INLINE uint32_t LL_I3C_GetStallTime(const I3C_TypeDef *I3Cx)
1781 {
1782 return (uint32_t)(READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALL));
1783 }
1784
1785 /**
1786 * @brief Set stall on ACK bit (controller mode).
1787 * @note This bit can be programmed when the I3C is disabled (EN = 0).
1788 * @rmtoll TIMINGR2 STALLA LL_I3C_EnableStallACK
1789 * @param I3Cx I3C Instance.
1790 * @retval None
1791 */
LL_I3C_EnableStallACK(I3C_TypeDef * I3Cx)1792 __STATIC_INLINE void LL_I3C_EnableStallACK(I3C_TypeDef *I3Cx)
1793 {
1794 SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA);
1795 }
1796
1797 /**
1798 * @brief Disable stall on ACK bit (controller mode).
1799 * @note This bit can be programmed when the I3C is disabled (EN = 0).
1800 * @rmtoll TIMINGR2 STALLA LL_I3C_DisableStallACK
1801 * @param I3Cx I3C Instance.
1802 * @retval None
1803 */
LL_I3C_DisableStallACK(I3C_TypeDef * I3Cx)1804 __STATIC_INLINE void LL_I3C_DisableStallACK(I3C_TypeDef *I3Cx)
1805 {
1806 CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA);
1807 }
1808
1809 /**
1810 * @brief Check if stall on ACK bit is enabled or disabled (controller mode).
1811 * @rmtoll TIMINGR2 STALLA LL_I3C_IsEnabledStallACK
1812 * @param I3Cx I3C Instance.
1813 * @retval State of bit (1 or 0).
1814 */
LL_I3C_IsEnabledStallACK(const I3C_TypeDef * I3Cx)1815 __STATIC_INLINE uint32_t LL_I3C_IsEnabledStallACK(const I3C_TypeDef *I3Cx)
1816 {
1817 return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA) == (I3C_TIMINGR2_STALLA)) ? 1UL : 0UL);
1818 }
1819
1820 /**
1821 * @brief Set stall on Parity bit of Command Code byte (controller mode).
1822 * @note This bit can be programmed when the I3C is disabled (EN = 0).
1823 * @rmtoll TIMINGR2 STALLC LL_I3C_EnableStallParityCCC
1824 * @param I3Cx I3C Instance.
1825 * @retval None
1826 */
LL_I3C_EnableStallParityCCC(I3C_TypeDef * I3Cx)1827 __STATIC_INLINE void LL_I3C_EnableStallParityCCC(I3C_TypeDef *I3Cx)
1828 {
1829 SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC);
1830 }
1831
1832 /**
1833 * @brief Disable stall on Parity bit of Command Code byte (controller mode).
1834 * @note This bit can be programmed when the I3C is disabled (EN = 0).
1835 * @rmtoll TIMINGR2 STALLC LL_I3C_DisableStallParityCCC
1836 * @param I3Cx I3C Instance.
1837 * @retval None
1838 */
LL_I3C_DisableStallParityCCC(I3C_TypeDef * I3Cx)1839 __STATIC_INLINE void LL_I3C_DisableStallParityCCC(I3C_TypeDef *I3Cx)
1840 {
1841 CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC);
1842 }
1843
1844 /**
1845 * @brief Check if stall on Parity bit of Command Code byte is enabled or disabled (controller mode).
1846 * @rmtoll TIMINGR2 STALLC LL_I3C_IsEnabledStallParityCCC
1847 * @param I3Cx I3C Instance.
1848 * @retval State of bit (1 or 0).
1849 */
LL_I3C_IsEnabledStallParityCCC(const I3C_TypeDef * I3Cx)1850 __STATIC_INLINE uint32_t LL_I3C_IsEnabledStallParityCCC(const I3C_TypeDef *I3Cx)
1851 {
1852 return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC) == (I3C_TIMINGR2_STALLC)) ? 1UL : 0UL);
1853 }
1854
1855 /**
1856 * @brief Set stall on Parity bit of Data bytes (controller mode).
1857 * @note This bit can be programmed when the I3C is disabled (EN = 0).
1858 * @rmtoll TIMINGR2 STALLD LL_I3C_EnableStallParityData
1859 * @param I3Cx I3C Instance.
1860 * @retval None
1861 */
LL_I3C_EnableStallParityData(I3C_TypeDef * I3Cx)1862 __STATIC_INLINE void LL_I3C_EnableStallParityData(I3C_TypeDef *I3Cx)
1863 {
1864 SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD);
1865 }
1866
1867 /**
1868 * @brief Disable stall on Parity bit of Data bytes (controller mode).
1869 * @note This bit can be programmed when the I3C is disabled (EN = 0).
1870 * @rmtoll TIMINGR2 STALLD LL_I3C_DisableStallParityData
1871 * @param I3Cx I3C Instance.
1872 * @retval None
1873 */
LL_I3C_DisableStallParityData(I3C_TypeDef * I3Cx)1874 __STATIC_INLINE void LL_I3C_DisableStallParityData(I3C_TypeDef *I3Cx)
1875 {
1876 CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD);
1877 }
1878
1879 /**
1880 * @brief Check if stall on Parity bit of Data bytes is enabled or disabled (controller mode).
1881 * @rmtoll TIMINGR2 STALLD LL_I3C_IsEnabledStallParityData
1882 * @param I3Cx I3C Instance.
1883 * @retval State of bit (1 or 0).
1884 */
LL_I3C_IsEnabledStallParityData(const I3C_TypeDef * I3Cx)1885 __STATIC_INLINE uint32_t LL_I3C_IsEnabledStallParityData(const I3C_TypeDef *I3Cx)
1886 {
1887 return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD) == (I3C_TIMINGR2_STALLD)) ? 1UL : 0UL);
1888 }
1889
1890 /**
1891 * @brief Set stall on T bit (controller mode).
1892 * @note This bit can be programmed when the I3C is disabled (EN = 0).
1893 * @rmtoll TIMINGR2 STALLT LL_I3C_EnableStallTbit
1894 * @param I3Cx I3C Instance.
1895 * @retval None
1896 */
LL_I3C_EnableStallTbit(I3C_TypeDef * I3Cx)1897 __STATIC_INLINE void LL_I3C_EnableStallTbit(I3C_TypeDef *I3Cx)
1898 {
1899 SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT);
1900 }
1901
1902 /**
1903 * @brief Disable stall on T bit (controller mode).
1904 * @note This bit can be programmed when the I3C is disabled (EN = 0).
1905 * @rmtoll TIMINGR2 STALLT LL_I3C_DisableStallTbit
1906 * @param I3Cx I3C Instance.
1907 * @retval None
1908 */
LL_I3C_DisableStallTbit(I3C_TypeDef * I3Cx)1909 __STATIC_INLINE void LL_I3C_DisableStallTbit(I3C_TypeDef *I3Cx)
1910 {
1911 CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT);
1912 }
1913
1914 /**
1915 * @brief Check if stall on T bit is enabled or disabled (controller mode).
1916 * @rmtoll TIMINGR2 STALLT LL_I3C_IsEnabledStallTbit
1917 * @param I3Cx I3C Instance.
1918 * @retval State of bit (1 or 0).
1919 */
LL_I3C_IsEnabledStallTbit(const I3C_TypeDef * I3Cx)1920 __STATIC_INLINE uint32_t LL_I3C_IsEnabledStallTbit(const I3C_TypeDef *I3Cx)
1921 {
1922 return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT) == (I3C_TIMINGR2_STALLT)) ? 1UL : 0UL);
1923 }
1924
1925 /**
1926 * @brief Configure the Device Capability on Bus as Target or Controller (MIPI Bus Characteristics Register BCR6).
1927 * @note Those bits can be programmed when the I3C is disabled (EN = 0).
1928 * @rmtoll BCR BCR6 LL_I3C_SetDeviceCapabilityOnBus
1929 * @param I3Cx I3C Instance.
1930 * @param DeviceCapabilityOnBus This parameter can be one of the following values:
1931 * @arg @ref LL_I3C_DEVICE_ROLE_AS_TARGET
1932 * @arg @ref LL_I3C_DEVICE_ROLE_AS_CONTROLLER
1933 * @retval None
1934 */
LL_I3C_SetDeviceCapabilityOnBus(I3C_TypeDef * I3Cx,uint32_t DeviceCapabilityOnBus)1935 __STATIC_INLINE void LL_I3C_SetDeviceCapabilityOnBus(I3C_TypeDef *I3Cx, uint32_t DeviceCapabilityOnBus)
1936 {
1937 MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR6, DeviceCapabilityOnBus);
1938 }
1939
1940 /**
1941 * @brief Get the Device Capability on Bus as Target or Controller (MIPI Bus Characteristics Register BCR6).
1942 * @rmtoll BCR BCR6 LL_I3C_GetDeviceCapabilityOnBus
1943 * @param I3Cx I3C Instance.
1944 * @retval Returned value can be one of the following values:
1945 * @arg @ref LL_I3C_DEVICE_ROLE_AS_TARGET
1946 * @arg @ref LL_I3C_DEVICE_ROLE_AS_CONTROLLER
1947 */
LL_I3C_GetDeviceCapabilityOnBus(const I3C_TypeDef * I3Cx)1948 __STATIC_INLINE uint32_t LL_I3C_GetDeviceCapabilityOnBus(const I3C_TypeDef *I3Cx)
1949 {
1950 return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR6));
1951 }
1952
1953 /**
1954 * @brief Configure the Device IBI Payload (MIPI Bus Characteristics Register BCR2).
1955 * @note Those bits can be programmed when the I3C is disabled (EN = 0).
1956 * @rmtoll BCR BCR2 LL_I3C_SetDeviceIBIPayload
1957 * @param I3Cx I3C Instance.
1958 * @param DeviceIBIPayload This parameter can be one of the following values:
1959 * @arg @ref LL_I3C_IBI_NO_ADDITIONAL_DATA
1960 * @arg @ref LL_I3C_IBI_ADDITIONAL_DATA
1961 * @retval None
1962 */
LL_I3C_SetDeviceIBIPayload(I3C_TypeDef * I3Cx,uint32_t DeviceIBIPayload)1963 __STATIC_INLINE void LL_I3C_SetDeviceIBIPayload(I3C_TypeDef *I3Cx, uint32_t DeviceIBIPayload)
1964 {
1965 MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR2, DeviceIBIPayload);
1966 }
1967
1968 /**
1969 * @brief Get the Device IBI Payload (MIPI Bus Characteristics Register BCR2).
1970 * @rmtoll BCR BCR2 LL_I3C_GetDeviceIBIPayload
1971 * @param I3Cx I3C Instance.
1972 * @retval Returned value can be one of the following values:
1973 * @arg @ref LL_I3C_IBI_NO_ADDITIONAL_DATA
1974 * @arg @ref LL_I3C_IBI_ADDITIONAL_DATA
1975 */
LL_I3C_GetDeviceIBIPayload(const I3C_TypeDef * I3Cx)1976 __STATIC_INLINE uint32_t LL_I3C_GetDeviceIBIPayload(const I3C_TypeDef *I3Cx)
1977 {
1978 return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR2));
1979 }
1980
1981 /**
1982 * @brief Configure the Data Speed Limitation (limitation, as described by I3C_GETMXDSR).
1983 * @note Those bits can be programmed when the I3C is disabled (EN = 0).
1984 * @rmtoll BCR BCR0 LL_I3C_SetDataSpeedLimitation
1985 * @param I3Cx I3C Instance.
1986 * @param DataSpeedLimitation This parameter can be one of the following values:
1987 * @arg @ref LL_I3C_NO_DATA_SPEED_LIMITATION
1988 * @arg @ref LL_I3C_MAX_DATA_SPEED_LIMITATION
1989 * @retval None
1990 */
LL_I3C_SetDataSpeedLimitation(I3C_TypeDef * I3Cx,uint32_t DataSpeedLimitation)1991 __STATIC_INLINE void LL_I3C_SetDataSpeedLimitation(I3C_TypeDef *I3Cx, uint32_t DataSpeedLimitation)
1992 {
1993 MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR0, DataSpeedLimitation);
1994 }
1995
1996 /**
1997 * @brief Get the Data Speed Limitation (limitation, as described by I3C_GETMXDSR).
1998 * @rmtoll BCR BCR0 LL_I3C_GetDataSpeedLimitation
1999 * @param I3Cx I3C Instance.
2000 * @retval Returned value can be one of the following values:
2001 * @arg @ref LL_I3C_NO_DATA_SPEED_LIMITATION
2002 * @arg @ref LL_I3C_MAX_DATA_SPEED_LIMITATION
2003 */
LL_I3C_GetDataSpeedLimitation(const I3C_TypeDef * I3Cx)2004 __STATIC_INLINE uint32_t LL_I3C_GetDataSpeedLimitation(const I3C_TypeDef *I3Cx)
2005 {
2006 return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR0));
2007 }
2008
2009 /**
2010 * @brief Configure the Device Characteristics Register (DCR).
2011 * @note This bit can only be programmed when the I3C is disabled (EN = 0).
2012 *
2013 * @note Refer MIPI web site for the list of device code available.
2014 * @rmtoll DCR DC LL_I3C_SetDeviceCharacteristics
2015 * @param I3Cx I3C Instance.
2016 * @param DeviceCharacteristics This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
2017 * @retval None
2018 */
LL_I3C_SetDeviceCharacteristics(I3C_TypeDef * I3Cx,uint32_t DeviceCharacteristics)2019 __STATIC_INLINE void LL_I3C_SetDeviceCharacteristics(I3C_TypeDef *I3Cx, uint32_t DeviceCharacteristics)
2020 {
2021 MODIFY_REG(I3Cx->DCR, I3C_DCR_DCR, DeviceCharacteristics);
2022 }
2023
2024 /**
2025 * @brief Get the Device Characteristics Register (DCR).
2026 * @note Refer MIPI web site to associated value with the list of device code available.
2027 * @rmtoll DCR DCR LL_I3C_GetDeviceCharacteristics
2028 * @param I3Cx I3C Instance.
2029 * @retval Value between Min_Data=0 and Max_Data=0xFF.
2030 */
LL_I3C_GetDeviceCharacteristics(const I3C_TypeDef * I3Cx)2031 __STATIC_INLINE uint32_t LL_I3C_GetDeviceCharacteristics(const I3C_TypeDef *I3Cx)
2032 {
2033 return (uint32_t)(READ_BIT(I3Cx->DCR, I3C_DCR_DCR));
2034 }
2035
2036 /**
2037 * @brief Configure IBI MDB support for pending read notification.
2038 * @note Those bits can be programmed when the I3C is disabled (EN = 0).
2039 * @rmtoll GETCAPR CAPPEND LL_I3C_SetPendingReadMDB
2040 * @param I3Cx I3C Instance.
2041 * @param PendingReadMDB This parameter can be one of the following values:
2042 * @arg @ref LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION
2043 * @arg @ref LL_I3C_MDB_PENDING_READ_NOTIFICATION
2044 * @retval None
2045 */
LL_I3C_SetPendingReadMDB(I3C_TypeDef * I3Cx,uint32_t PendingReadMDB)2046 __STATIC_INLINE void LL_I3C_SetPendingReadMDB(I3C_TypeDef *I3Cx, uint32_t PendingReadMDB)
2047 {
2048 MODIFY_REG(I3Cx->GETCAPR, I3C_GETCAPR_CAPPEND, PendingReadMDB);
2049 }
2050
2051 /**
2052 * @brief Get IBI MDB support for pending read notification value.
2053 * @rmtoll GETCAPR CAPPEND LL_I3C_GetPendingReadMDB
2054 * @param I3Cx I3C Instance.
2055 * @retval Returned value can be one of the following values:
2056 * @arg @ref LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION
2057 * @arg @ref LL_I3C_MDB_PENDING_READ_NOTIFICATION
2058 */
LL_I3C_GetPendingReadMDB(const I3C_TypeDef * I3Cx)2059 __STATIC_INLINE uint32_t LL_I3C_GetPendingReadMDB(const I3C_TypeDef *I3Cx)
2060 {
2061 return (uint32_t)(READ_BIT(I3Cx->GETCAPR, I3C_GETCAPR_CAPPEND));
2062 }
2063
2064 /**
2065 * @brief Configure the Group Management Support bit of MSTCAP1.
2066 * @note Those bits can be programmed when the I3C is disabled (EN = 0).
2067 * @rmtoll CRCAPR CAPGRP LL_I3C_SetGrpAddrHandoffSupport
2068 * @param I3Cx I3C Instance.
2069 * @param GrpAddrHandoffSupport This parameter can be one of the following values:
2070 * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED
2071 * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED
2072 * @retval None
2073 */
LL_I3C_SetGrpAddrHandoffSupport(I3C_TypeDef * I3Cx,uint32_t GrpAddrHandoffSupport)2074 __STATIC_INLINE void LL_I3C_SetGrpAddrHandoffSupport(I3C_TypeDef *I3Cx, uint32_t GrpAddrHandoffSupport)
2075 {
2076 MODIFY_REG(I3Cx->CRCAPR, I3C_CRCAPR_CAPGRP, GrpAddrHandoffSupport);
2077 }
2078
2079 /**
2080 * @brief Get the Group Management Support bit of MSTCAP1.
2081 * @rmtoll CRCAPR CAPGRP LL_I3C_GetGrpAddrHandoffSupport
2082 * @param I3Cx I3C Instance.
2083 * @retval Returned value can be one of the following values:
2084 * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED
2085 * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED
2086 */
LL_I3C_GetGrpAddrHandoffSupport(const I3C_TypeDef * I3Cx)2087 __STATIC_INLINE uint32_t LL_I3C_GetGrpAddrHandoffSupport(const I3C_TypeDef *I3Cx)
2088 {
2089 return (uint32_t)(READ_BIT(I3Cx->CRCAPR, I3C_CRCAPR_CAPGRP));
2090 }
2091
2092 /**
2093 * @brief Configure the Delayed Controller Handoff bit in MSTCAP2.
2094 * @note Those bits can be programmed when the I3C is disabled (EN = 0).
2095 * @rmtoll CRCAPR CAPDHOFF LL_I3C_SetControllerHandoffDelayed
2096 * @param I3Cx I3C Instance.
2097 * @param ControllerHandoffDelayed This parameter can be one of the following values:
2098 * @arg @ref LL_I3C_HANDOFF_NOT_DELAYED
2099 * @arg @ref LL_I3C_HANDOFF_DELAYED
2100 * @retval None
2101 */
LL_I3C_SetControllerHandoffDelayed(I3C_TypeDef * I3Cx,uint32_t ControllerHandoffDelayed)2102 __STATIC_INLINE void LL_I3C_SetControllerHandoffDelayed(I3C_TypeDef *I3Cx, uint32_t ControllerHandoffDelayed)
2103 {
2104 MODIFY_REG(I3Cx->CRCAPR, I3C_CRCAPR_CAPDHOFF, ControllerHandoffDelayed);
2105 }
2106
2107 /**
2108 * @brief Get the Delayed Controller Handoff bit in MSTCAP2.
2109 * @rmtoll CRCAPR CAPDHOFF LL_I3C_GetControllerHandoffDelayed
2110 * @param I3Cx I3C Instance.
2111 * @retval Returned value can be one of the following values:
2112 * @arg @ref LL_I3C_HANDOFF_NOT_DELAYED
2113 * @arg @ref LL_I3C_HANDOFF_DELAYED
2114 */
LL_I3C_GetControllerHandoffDelayed(const I3C_TypeDef * I3Cx)2115 __STATIC_INLINE uint32_t LL_I3C_GetControllerHandoffDelayed(const I3C_TypeDef *I3Cx)
2116 {
2117 return (uint32_t)(READ_BIT(I3Cx->CRCAPR, I3C_CRCAPR_CAPDHOFF));
2118 }
2119
2120 /**
2121 * @brief Configure the Activity State after controllership handoff.
2122 * @note Those bits can be programmed when the I3C is disabled (EN = 0).
2123 * @rmtoll GETMXDSR HOFFAS LL_I3C_SetHandoffActivityState
2124 * @param I3Cx I3C Instance.
2125 * @param HandoffActivityState This parameter can be one of the following values:
2126 * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_0
2127 * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_1
2128 * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_2
2129 * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_3
2130 * @retval None
2131 */
LL_I3C_SetHandoffActivityState(I3C_TypeDef * I3Cx,uint32_t HandoffActivityState)2132 __STATIC_INLINE void LL_I3C_SetHandoffActivityState(I3C_TypeDef *I3Cx, uint32_t HandoffActivityState)
2133 {
2134 MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_HOFFAS, HandoffActivityState);
2135 }
2136
2137 /**
2138 * @brief Get the Activity State after controllership handoff.
2139 * @rmtoll GETMXDSR HOFFAS LL_I3C_GetHandoffActivityState
2140 * @param I3Cx I3C Instance.
2141 * @retval Returned value can be one of the following values:
2142 * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_0
2143 * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_1
2144 * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_2
2145 * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_3
2146 */
LL_I3C_GetHandoffActivityState(const I3C_TypeDef * I3Cx)2147 __STATIC_INLINE uint32_t LL_I3C_GetHandoffActivityState(const I3C_TypeDef *I3Cx)
2148 {
2149 return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_HOFFAS));
2150 }
2151
2152 /**
2153 * @brief Configure the Max Data Speed Format response for GETMXDS CCC.
2154 * @note Those bits can be programmed when the I3C is disabled (EN = 0).
2155 * @rmtoll GETMXDSR FMT LL_I3C_SetMaxDataSpeedFormat
2156 * @param I3Cx I3C Instance.
2157 * @param MaxDataSpeedFormat This parameter can be one of the following values:
2158 * @arg @ref LL_I3C_GETMXDS_FORMAT_1
2159 * @arg @ref LL_I3C_GETMXDS_FORMAT_2_LSB
2160 * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MID
2161 * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MSB
2162 * @retval None
2163 */
LL_I3C_SetMaxDataSpeedFormat(I3C_TypeDef * I3Cx,uint32_t MaxDataSpeedFormat)2164 __STATIC_INLINE void LL_I3C_SetMaxDataSpeedFormat(I3C_TypeDef *I3Cx, uint32_t MaxDataSpeedFormat)
2165 {
2166 MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_FMT, MaxDataSpeedFormat);
2167 }
2168
2169 /**
2170 * @brief Get the Max Data Speed Format response for GETMXDS CCC.
2171 * @rmtoll GETMXDSR FMT LL_I3C_GetMaxDataSpeedFormat
2172 * @param I3Cx I3C Instance.
2173 * @retval Returned value can be one of the following values:
2174 * @arg @ref LL_I3C_GETMXDS_FORMAT_1
2175 * @arg @ref LL_I3C_GETMXDS_FORMAT_2_LSB
2176 * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MID
2177 * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MSB
2178 */
LL_I3C_GetMaxDataSpeedFormat(const I3C_TypeDef * I3Cx)2179 __STATIC_INLINE uint32_t LL_I3C_GetMaxDataSpeedFormat(const I3C_TypeDef *I3Cx)
2180 {
2181 return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_FMT));
2182 }
2183
2184 /**
2185 * @brief Configure the Middle byte of MaxRdTurn field of GETMXDS CCC Format 2 with turnaround.
2186 * @note Those bits can be programmed when the I3C is disabled (EN = 0).
2187 * @rmtoll GETMXDSR RDTURN LL_I3C_SetMiddleByteTurnAround
2188 * @param I3Cx I3C Instance.
2189 * @param MiddleByteTurnAround This parameter must be a value between Min_Data=0 and Max_Data=0xF.
2190 * @retval None
2191 */
LL_I3C_SetMiddleByteTurnAround(I3C_TypeDef * I3Cx,uint32_t MiddleByteTurnAround)2192 __STATIC_INLINE void LL_I3C_SetMiddleByteTurnAround(I3C_TypeDef *I3Cx, uint32_t MiddleByteTurnAround)
2193 {
2194 MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_RDTURN, (MiddleByteTurnAround << I3C_GETMXDSR_RDTURN_Pos));
2195 }
2196
2197 /**
2198 * @brief Get the value of Middle byte of MaxRdTurn field of GETMXDS CCC Format 2 with turnaround.
2199 * @rmtoll GETMXDSR RDTURN LL_I3C_GetMiddleByteTurnAround
2200 * @param I3Cx I3C Instance.
2201 * @retval Value between Min_Data=0 and Max_Data=0xF.
2202 */
LL_I3C_GetMiddleByteTurnAround(const I3C_TypeDef * I3Cx)2203 __STATIC_INLINE uint32_t LL_I3C_GetMiddleByteTurnAround(const I3C_TypeDef *I3Cx)
2204 {
2205 return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_RDTURN));
2206 }
2207
2208 /**
2209 * @brief Configure clock-to-data turnaround time.
2210 * @note Those bits can be programmed when the I3C is disabled (EN = 0).
2211 * @rmtoll GETMXDSR TSCO LL_I3C_SetDataTurnAroundTime
2212 * @param I3Cx I3C Instance.
2213 * @param DataTurnAroundTime This parameter can be one of the following values:
2214 * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS
2215 * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS
2216 * @retval None
2217 */
LL_I3C_SetDataTurnAroundTime(I3C_TypeDef * I3Cx,uint32_t DataTurnAroundTime)2218 __STATIC_INLINE void LL_I3C_SetDataTurnAroundTime(I3C_TypeDef *I3Cx, uint32_t DataTurnAroundTime)
2219 {
2220 MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_TSCO, DataTurnAroundTime);
2221 }
2222
2223 /**
2224 * @brief Get clock-to-data turnaround time.
2225 * @rmtoll GETMXDSR TSCO LL_I3C_GetDataTurnAroundTime
2226 * @param I3Cx I3C Instance.
2227 * @retval Returned value can be one of the following values:
2228 * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS
2229 * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS
2230 */
LL_I3C_GetDataTurnAroundTime(const I3C_TypeDef * I3Cx)2231 __STATIC_INLINE uint32_t LL_I3C_GetDataTurnAroundTime(const I3C_TypeDef *I3Cx)
2232 {
2233 return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_TSCO));
2234 }
2235
2236 /**
2237 * @brief Configure the MIPI Instance ID.
2238 * @note Those bits can be programmed when the I3C is disabled (EN = 0).
2239 * @rmtoll EPIDR MIPIID LL_I3C_SetMIPIInstanceID
2240 * @param I3Cx I3C Instance.
2241 * @param MIPIInstanceID This parameter must be a value between Min_Data=0 and Max_Data=0xF.
2242 * @retval None
2243 */
LL_I3C_SetMIPIInstanceID(I3C_TypeDef * I3Cx,uint32_t MIPIInstanceID)2244 __STATIC_INLINE void LL_I3C_SetMIPIInstanceID(I3C_TypeDef *I3Cx, uint32_t MIPIInstanceID)
2245 {
2246 MODIFY_REG(I3Cx->EPIDR, I3C_EPIDR_MIPIID, (MIPIInstanceID << I3C_EPIDR_MIPIID_Pos));
2247 }
2248
2249 /**
2250 * @brief Get the MIPI Instance ID.
2251 * @rmtoll EPIDR MIPIID LL_I3C_GetMIPIInstanceID
2252 * @param I3Cx I3C Instance.
2253 * @retval Value between Min_Data=0 and Max_Data=0xF.
2254 */
LL_I3C_GetMIPIInstanceID(const I3C_TypeDef * I3Cx)2255 __STATIC_INLINE uint32_t LL_I3C_GetMIPIInstanceID(const I3C_TypeDef *I3Cx)
2256 {
2257 return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_MIPIID) >> I3C_EPIDR_MIPIID_Pos);
2258 }
2259
2260 /**
2261 * @brief Get the ID type selector.
2262 * @rmtoll EPIDR IDTSEL LL_I3C_GetIDTypeSelector
2263 * @param I3Cx I3C Instance.
2264 * @retval Value between Min_Data=0x0 and Max_Data=0x1
2265 */
LL_I3C_GetIDTypeSelector(const I3C_TypeDef * I3Cx)2266 __STATIC_INLINE uint32_t LL_I3C_GetIDTypeSelector(const I3C_TypeDef *I3Cx)
2267 {
2268 return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_IDTSEL) >> I3C_EPIDR_IDTSEL_Pos);
2269 }
2270
2271 /**
2272 * @brief Get the MIPI Manufacturer ID.
2273 * @rmtoll EPIDR MIPIMID LL_I3C_GetMIPIManufacturerID
2274 * @param I3Cx I3C Instance.
2275 * @retval Value between Min_Data=0 and Max_Data=0x7FFF.
2276 */
LL_I3C_GetMIPIManufacturerID(const I3C_TypeDef * I3Cx)2277 __STATIC_INLINE uint32_t LL_I3C_GetMIPIManufacturerID(const I3C_TypeDef *I3Cx)
2278 {
2279 return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_MIPIMID) >> I3C_EPIDR_MIPIMID_Pos);
2280 }
2281
2282 /**
2283 * @}
2284 */
2285
2286 /** @defgroup I3C_LL_EF_Data Management
2287 * @{
2288 */
2289
2290 /**
2291 * @brief Request a reception Data FIFO Flush.
2292 * @rmtoll CFGR RXFLUSH LL_I3C_RequestRxFIFOFlush
2293 * @param I3Cx I3C Instance.
2294 * @retval None
2295 */
LL_I3C_RequestRxFIFOFlush(I3C_TypeDef * I3Cx)2296 __STATIC_INLINE void LL_I3C_RequestRxFIFOFlush(I3C_TypeDef *I3Cx)
2297 {
2298 SET_BIT(I3Cx->CFGR, I3C_CFGR_RXFLUSH);
2299 }
2300
2301 /**
2302 * @brief Request a transmission Data FIFO Flush.
2303 * @rmtoll CFGR TXFLUSH LL_I3C_RequestTxFIFOFlush
2304 * @param I3Cx I3C Instance.
2305 * @retval None
2306 */
LL_I3C_RequestTxFIFOFlush(I3C_TypeDef * I3Cx)2307 __STATIC_INLINE void LL_I3C_RequestTxFIFOFlush(I3C_TypeDef *I3Cx)
2308 {
2309 SET_BIT(I3Cx->CFGR, I3C_CFGR_TXFLUSH);
2310 }
2311
2312 /**
2313 * @brief Request a Status Data FIFO Flush.
2314 * @rmtoll CFGR SFLUSH LL_I3C_RequestStatusFIFOFlush
2315 * @param I3Cx I3C Instance.
2316 * @retval None
2317 */
LL_I3C_RequestStatusFIFOFlush(I3C_TypeDef * I3Cx)2318 __STATIC_INLINE void LL_I3C_RequestStatusFIFOFlush(I3C_TypeDef *I3Cx)
2319 {
2320 SET_BIT(I3Cx->CFGR, I3C_CFGR_SFLUSH);
2321 }
2322
2323 /**
2324 * @brief Get Activity state of Controller on the I3C Bus (Target only).
2325 * @rmtoll DEVR0 AS LL_I3C_GetActivityState
2326 * @param I3Cx I3C Instance.
2327 * @retval Returned value can be one of the following values:
2328 * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_0
2329 * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_1
2330 * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_2
2331 * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_3
2332 */
LL_I3C_GetActivityState(const I3C_TypeDef * I3Cx)2333 __STATIC_INLINE uint32_t LL_I3C_GetActivityState(const I3C_TypeDef *I3Cx)
2334 {
2335 return (uint32_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_AS));
2336 }
2337
2338 /**
2339 * @brief Get Reset Action (Target only).
2340 * @rmtoll DEVR0 RSTACT LL_I3C_GetResetAction
2341 * @param I3Cx I3C Instance.
2342 * @retval Returned value can be one of the following values:
2343 * @arg @ref LL_I3C_RESET_ACTION_NONE
2344 * @arg @ref LL_I3C_RESET_ACTION_PARTIAL
2345 * @arg @ref LL_I3C_RESET_ACTION_FULL
2346 */
LL_I3C_GetResetAction(const I3C_TypeDef * I3Cx)2347 __STATIC_INLINE uint32_t LL_I3C_GetResetAction(const I3C_TypeDef *I3Cx)
2348 {
2349 return (uint32_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_RSTACT));
2350 }
2351
2352 /**
2353 * @brief Request a Control word FIFO Flush.
2354 * @rmtoll CFGR CFLUSH LL_I3C_RequestControlFIFOFlush
2355 * @param I3Cx I3C Instance.
2356 * @retval None
2357 */
LL_I3C_RequestControlFIFOFlush(I3C_TypeDef * I3Cx)2358 __STATIC_INLINE void LL_I3C_RequestControlFIFOFlush(I3C_TypeDef *I3Cx)
2359 {
2360 SET_BIT(I3Cx->CFGR, I3C_CFGR_CFLUSH);
2361 }
2362
2363 /**
2364 * @brief Request a Transfer start.
2365 * @note After request, the current instruction in Control Register is executed on I3C Bus.
2366 * @rmtoll CFGR TSFSET LL_I3C_RequestTransfer
2367 * @param I3Cx I3C Instance.
2368 * @retval None
2369 */
LL_I3C_RequestTransfer(I3C_TypeDef * I3Cx)2370 __STATIC_INLINE void LL_I3C_RequestTransfer(I3C_TypeDef *I3Cx)
2371 {
2372 SET_BIT(I3Cx->CFGR, I3C_CFGR_TSFSET);
2373 }
2374
2375 /**
2376 * @brief Handles I3C Message content on the I3C Bus as Controller.
2377 * @rmtoll CR ADD LL_I3C_ControllerHandleMessage\n
2378 * CR DCNT LL_I3C_ControllerHandleMessage\n
2379 * CR RNW LL_I3C_ControllerHandleMessage\n
2380 * CR MTYPE LL_I3C_ControllerHandleMessage\n
2381 * CR MEND LL_I3C_ControllerHandleMessage
2382 * @param I3Cx I3C Instance.
2383 * @param TargetAddr Specifies the target address to be programmed.
2384 * This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
2385 * @param TransferSize Specifies the number of bytes to be programmed.
2386 * This parameter must be a value between Min_Data=0 and Max_Data=65535.
2387 * @param Direction This parameter can be one of the following values:
2388 * @arg @ref LL_I3C_DIRECTION_WRITE
2389 * @arg @ref LL_I3C_DIRECTION_READ
2390 * @param MessageType This parameter can be one of the following values:
2391 * @arg @ref LL_I3C_CONTROLLER_MTYPE_RELEASE
2392 * @arg @ref LL_I3C_CONTROLLER_MTYPE_HEADER
2393 * @arg @ref LL_I3C_CONTROLLER_MTYPE_PRIVATE
2394 * @arg @ref LL_I3C_CONTROLLER_MTYPE_DIRECT
2395 * @arg @ref LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C
2396 * @param EndMode This parameter can be one of the following values:
2397 * @arg @ref LL_I3C_GENERATE_STOP
2398 * @arg @ref LL_I3C_GENERATE_RESTART
2399 * @retval None
2400 */
LL_I3C_ControllerHandleMessage(I3C_TypeDef * I3Cx,uint32_t TargetAddr,uint32_t TransferSize,uint32_t Direction,uint32_t MessageType,uint32_t EndMode)2401 __STATIC_INLINE void LL_I3C_ControllerHandleMessage(I3C_TypeDef *I3Cx, uint32_t TargetAddr, uint32_t TransferSize,
2402 uint32_t Direction, uint32_t MessageType, uint32_t EndMode)
2403 {
2404 WRITE_REG(I3Cx->CR, ((TargetAddr << I3C_CR_ADD_Pos) | TransferSize | Direction | MessageType | EndMode) \
2405 & (I3C_CR_ADD | I3C_CR_DCNT | I3C_CR_RNW | I3C_CR_MTYPE | I3C_CR_MEND));
2406 }
2407
2408 /**
2409 * @brief Handles I3C Common Command Code content on the I3C Bus as Controller.
2410 * @rmtoll CR CCC LL_I3C_ControllerHandleCCC\n
2411 * CR DCNT LL_I3C_ControllerHandleCCC\n
2412 * CR MTYPE LL_I3C_ControllerHandleCCC\n
2413 * CR MEND LL_I3C_ControllerHandleCCC
2414 * @param I3Cx I3C Instance.
2415 * @param CCCValue Specifies the Command Code to be programmed.
2416 * This parameter must be a value between Min_Data=0 and Max_Data=0x1FF.
2417 * @param AddByteSize Specifies the number of CCC additional bytes to be programmed.
2418 * This parameter must be a value between Min_Data=0 and Max_Data=65535.
2419 * @param EndMode This parameter can be one of the following values:
2420 * @arg @ref LL_I3C_GENERATE_STOP
2421 * @arg @ref LL_I3C_GENERATE_RESTART
2422 * @retval None
2423 */
LL_I3C_ControllerHandleCCC(I3C_TypeDef * I3Cx,uint32_t CCCValue,uint32_t AddByteSize,uint32_t EndMode)2424 __STATIC_INLINE void LL_I3C_ControllerHandleCCC(I3C_TypeDef *I3Cx, uint32_t CCCValue,
2425 uint32_t AddByteSize, uint32_t EndMode)
2426 {
2427 WRITE_REG(I3Cx->CR, ((CCCValue << I3C_CR_CCC_Pos) | AddByteSize | EndMode | LL_I3C_CONTROLLER_MTYPE_CCC) \
2428 & (I3C_CR_CCC | I3C_CR_DCNT | I3C_CR_MTYPE | I3C_CR_MEND));
2429 }
2430
2431 /**
2432 * @brief Handles I3C Message content on the I3C Bus as Target.
2433 * @rmtoll CR MTYPE LL_I3C_TargetHandleMessage\n
2434 * CR DCNT LL_I3C_TargetHandleMessage
2435 * @param I3Cx I3C Instance.
2436 * @param MessageType This parameter can be one of the following values:
2437 * @arg @ref LL_I3C_TARGET_MTYPE_HOT_JOIN
2438 * @arg @ref LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ
2439 * @arg @ref LL_I3C_TARGET_MTYPE_IBI
2440 * @param IBISize Specifies the number of IBI bytes.
2441 * This parameter must be a value between Min_Data=0 and Max_Data=65535.
2442 * @retval None
2443 */
LL_I3C_TargetHandleMessage(I3C_TypeDef * I3Cx,uint32_t MessageType,uint32_t IBISize)2444 __STATIC_INLINE void LL_I3C_TargetHandleMessage(I3C_TypeDef *I3Cx, uint32_t MessageType, uint32_t IBISize)
2445 {
2446 WRITE_REG(I3Cx->CR, (MessageType | IBISize) & (I3C_CR_DCNT | I3C_CR_MTYPE));
2447 }
2448
2449 /**
2450 * @}
2451 */
2452
2453 /** @defgroup I3C_LL_EF_Data_Management Data_Management
2454 * @{
2455 */
2456
2457 /**
2458 * @brief Read Receive Data Byte register.
2459 * @rmtoll RDR RDB0 LL_I3C_ReceiveData8
2460 * @param I3Cx I3C Instance.
2461 * @retval Value between Min_Data=0 to Max_Data=0xFF
2462 */
LL_I3C_ReceiveData8(const I3C_TypeDef * I3Cx)2463 __STATIC_INLINE uint8_t LL_I3C_ReceiveData8(const I3C_TypeDef *I3Cx)
2464 {
2465 return (uint8_t)(READ_BIT(I3Cx->RDR, I3C_RDR_RDB0));
2466 }
2467
2468 /**
2469 * @brief Write in Transmit Data Byte Register.
2470 * @rmtoll TDR TDB0 LL_I3C_TransmitData8
2471 * @param I3Cx I3C Instance.
2472 * @param Data This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
2473 * @retval None
2474 */
LL_I3C_TransmitData8(I3C_TypeDef * I3Cx,uint8_t Data)2475 __STATIC_INLINE void LL_I3C_TransmitData8(I3C_TypeDef *I3Cx, uint8_t Data)
2476 {
2477 WRITE_REG(I3Cx->TDR, Data);
2478 }
2479
2480 /**
2481 * @brief Read Receive Data Word register.
2482 * @note Content of register is filled in Little Endian.
2483 * Mean MSB correspond to last data byte received,
2484 * LSB correspond to first data byte received.
2485 * @rmtoll RDWR RDWR LL_I3C_ReceiveData32
2486 * @param I3Cx I3C Instance.
2487 * @retval Value between Min_Data=0 to Max_Data=0xFFFFFFFF
2488 */
LL_I3C_ReceiveData32(const I3C_TypeDef * I3Cx)2489 __STATIC_INLINE uint32_t LL_I3C_ReceiveData32(const I3C_TypeDef *I3Cx)
2490 {
2491 return (uint32_t)(READ_REG(I3Cx->RDWR));
2492 }
2493
2494 /**
2495 * @brief Write in Transmit Data Word Register.
2496 * @note Content of register is filled in Little Endian.
2497 * Mean MSB correspond to last data byte transmitted,
2498 * LSB correspond to first data byte transmitted.
2499 * @rmtoll TDWR TDWR LL_I3C_TransmitData32
2500 * @param I3Cx I3C Instance.
2501 * @param Data This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
2502 * @retval None
2503 */
LL_I3C_TransmitData32(I3C_TypeDef * I3Cx,uint32_t Data)2504 __STATIC_INLINE void LL_I3C_TransmitData32(I3C_TypeDef *I3Cx, uint32_t Data)
2505 {
2506 WRITE_REG(I3Cx->TDWR, Data);
2507 }
2508
2509 /**
2510 * @brief Configure the IBI data payload to be sent during IBI (target mode).
2511 * @note Content of register is filled in Little Endian.
2512 * Mean MSB correspond to last IBI data byte,
2513 * LSB correspond to first IBI data byte.
2514 * @rmtoll IBIDR IBIDR LL_I3C_SetIBIPayload
2515 * @param I3Cx I3C Instance.
2516 * @param OwnIBIPayload This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF
2517 * @retval None
2518 */
LL_I3C_SetIBIPayload(I3C_TypeDef * I3Cx,uint32_t OwnIBIPayload)2519 __STATIC_INLINE void LL_I3C_SetIBIPayload(I3C_TypeDef *I3Cx, uint32_t OwnIBIPayload)
2520 {
2521 WRITE_REG(I3Cx->IBIDR, OwnIBIPayload);
2522 }
2523
2524 /**
2525 * @brief Get the own IBI data payload (target mode), or get the Target IBI received (controller mode).
2526 * @note Content of register is filled in Little Endian.
2527 * Mean MSB correspond to last IBI data byte,
2528 * LSB correspond to first IBI data byte.
2529 * @rmtoll IBIDR IBIDR LL_I3C_GetIBIPayload
2530 * @param I3Cx I3C Instance.
2531 * @retval Value between Min_Data=0 to Max_Data=0xFFFFFFFF
2532 */
LL_I3C_GetIBIPayload(const I3C_TypeDef * I3Cx)2533 __STATIC_INLINE uint32_t LL_I3C_GetIBIPayload(const I3C_TypeDef *I3Cx)
2534 {
2535 return (uint32_t)(READ_REG(I3Cx->IBIDR));
2536 }
2537
2538 /**
2539 * @brief Get the number of data bytes received when reading IBI data (controller mode).
2540 * @rmtoll RMR IBIRDCNT LL_I3C_GetNbIBIAddData
2541 * @param I3Cx I3C Instance.
2542 * @retval Value between Min_Data=0 to Max_Data=0x7
2543 */
LL_I3C_GetNbIBIAddData(const I3C_TypeDef * I3Cx)2544 __STATIC_INLINE uint32_t LL_I3C_GetNbIBIAddData(const I3C_TypeDef *I3Cx)
2545 {
2546 return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_IBIRDCNT));
2547 }
2548
2549 /**
2550 * @brief Get the target address received during accepted IBI or Controller-role request.
2551 * @rmtoll RMR RADD LL_I3C_GetIBITargetAddr
2552 * @param I3Cx I3C Instance.
2553 * @retval Value between Min_Data=0 to Max_Data=0x3F
2554 */
LL_I3C_GetIBITargetAddr(const I3C_TypeDef * I3Cx)2555 __STATIC_INLINE uint32_t LL_I3C_GetIBITargetAddr(const I3C_TypeDef *I3Cx)
2556 {
2557 return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_RADD) >> I3C_RMR_RADD_Pos);
2558 }
2559
2560 /**
2561 * @brief Set TX FIFO Preload (target mode).
2562 * @note Set high by Software, cleared by hardware when all the bytes to transmit have been loaded to TX FIFO.
2563 * @rmtoll TGTTDR PRELOAD LL_I3C_ConfigTxPreload
2564 * @rmtoll TGTTDR TDCNT LL_I3C_ConfigTxPreload
2565 * @param I3Cx I3C Instance.
2566 * @param TxDataCount This parameter must be a value between Min_Data=0 and Max_Data=0xFFFF
2567 * @retval None
2568 */
LL_I3C_ConfigTxPreload(I3C_TypeDef * I3Cx,uint16_t TxDataCount)2569 __STATIC_INLINE void LL_I3C_ConfigTxPreload(I3C_TypeDef *I3Cx, uint16_t TxDataCount)
2570 {
2571 MODIFY_REG(I3Cx->TGTTDR, (I3C_TGTTDR_PRELOAD | I3C_TGTTDR_TGTTDCNT), (I3C_TGTTDR_PRELOAD | TxDataCount));
2572 }
2573
2574 /**
2575 * @brief Indicates the status of TX FIFO preload (target mode).
2576 * RESET: No preload of TX FIFO.
2577 * SET: Preload of TX FIFO ongoing.
2578 * @note Set high by Software, cleared by hardware when all the bytes to transmit have been loaded to TX FIFO.
2579 * @rmtoll TGTTDR PRELOAD LL_I3C_IsActiveTxPreload
2580 * @param I3Cx I3C Instance.
2581 * @retval State of bit (1 or 0).
2582 */
LL_I3C_IsActiveTxPreload(const I3C_TypeDef * I3Cx)2583 __STATIC_INLINE uint32_t LL_I3C_IsActiveTxPreload(const I3C_TypeDef *I3Cx)
2584 {
2585 return ((READ_BIT(I3Cx->TGTTDR, I3C_TGTTDR_PRELOAD) == (I3C_TGTTDR_PRELOAD)) ? 1UL : 0UL);
2586 }
2587
2588 /**
2589 * @brief Get the number of bytes to transmit (target mode).
2590 * @note The return value correspond to the remaining number of bytes to load in TX FIFO.
2591 * @rmtoll TGTTDR TDCNT LL_I3C_GetTxPreloadDataCount
2592 * @param I3Cx I3C Instance.
2593 * @retval Value between Min_Data=0 to Max_Data=0xFFFF
2594 */
LL_I3C_GetTxPreloadDataCount(const I3C_TypeDef * I3Cx)2595 __STATIC_INLINE uint16_t LL_I3C_GetTxPreloadDataCount(const I3C_TypeDef *I3Cx)
2596 {
2597 return (uint16_t)(READ_BIT(I3Cx->TGTTDR, I3C_TGTTDR_TGTTDCNT));
2598 }
2599
2600 /**
2601 * @brief Get the number of data during a Transfer.
2602 * @note The return value correspond to number of transmitted bytes reported
2603 * during Address Assignment process in Target mode.
2604 * The return value correspond to number of target detected
2605 * during Address Assignment process in Controller mode.
2606 * The return value correspond to number of data bytes read from or sent to the I3C bus
2607 * during the message link to MID current value.
2608 * @rmtoll SR XDCNT LL_I3C_GetXferDataCount
2609 * @param I3Cx I3C Instance.
2610 * @retval Value between Min_Data=0 to Max_Data=0xFFFF
2611 */
LL_I3C_GetXferDataCount(const I3C_TypeDef * I3Cx)2612 __STATIC_INLINE uint32_t LL_I3C_GetXferDataCount(const I3C_TypeDef *I3Cx)
2613 {
2614 return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_XDCNT));
2615 }
2616
2617 /**
2618 * @brief Indicates if a Target abort a private read command.
2619 * @rmtoll SR ABT LL_I3C_IsTargetAbortPrivateRead
2620 * @param I3Cx I3C Instance.
2621 * @retval State of bit (1 or 0).
2622 */
LL_I3C_IsTargetAbortPrivateRead(const I3C_TypeDef * I3Cx)2623 __STATIC_INLINE uint32_t LL_I3C_IsTargetAbortPrivateRead(const I3C_TypeDef *I3Cx)
2624 {
2625 return ((READ_BIT(I3Cx->SR, I3C_SR_ABT) == (I3C_SR_ABT)) ? 1UL : 0UL);
2626 }
2627
2628 /**
2629 * @brief Get Direction of the Message.
2630 * @rmtoll SR DIR LL_I3C_GetMessageDirection
2631 * @param I3Cx I3C Instance.
2632 * @retval Returned value can be one of the following values:
2633 * @arg @ref LL_I3C_MESSAGE_DIRECTION_WRITE
2634 * @arg @ref LL_I3C_MESSAGE_DIRECTION_READ
2635 */
LL_I3C_GetMessageDirection(const I3C_TypeDef * I3Cx)2636 __STATIC_INLINE uint32_t LL_I3C_GetMessageDirection(const I3C_TypeDef *I3Cx)
2637 {
2638 return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_DIR));
2639 }
2640
2641 /**
2642 * @brief Get Message identifier.
2643 * @rmtoll SR MID LL_I3C_GetMessageIdentifier
2644 * @param I3Cx I3C Instance.
2645 * @retval Value between Min_Data=0 to Max_Data=0xFF, representing the internal hardware counter value.
2646 */
LL_I3C_GetMessageIdentifier(const I3C_TypeDef * I3Cx)2647 __STATIC_INLINE uint32_t LL_I3C_GetMessageIdentifier(const I3C_TypeDef *I3Cx)
2648 {
2649 return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_MID));
2650 }
2651
2652 /**
2653 * @brief Get Message error code.
2654 * @rmtoll SER CODERR LL_I3C_GetMessageErrorCode
2655 * @param I3Cx I3C Instance.
2656 * @retval Returned value can be one of the following values:
2657 * @arg @ref LL_I3C_CONTROLLER_ERROR_CE0
2658 * @arg @ref LL_I3C_CONTROLLER_ERROR_CE1
2659 * @arg @ref LL_I3C_CONTROLLER_ERROR_CE2
2660 * @arg @ref LL_I3C_CONTROLLER_ERROR_CE3
2661 * @arg @ref LL_I3C_TARGET_ERROR_TE0
2662 * @arg @ref LL_I3C_TARGET_ERROR_TE1
2663 * @arg @ref LL_I3C_TARGET_ERROR_TE2
2664 * @arg @ref LL_I3C_TARGET_ERROR_TE3
2665 * @arg @ref LL_I3C_TARGET_ERROR_TE4
2666 * @arg @ref LL_I3C_TARGET_ERROR_TE5
2667 * @arg @ref LL_I3C_TARGET_ERROR_TE6
2668 */
LL_I3C_GetMessageErrorCode(const I3C_TypeDef * I3Cx)2669 __STATIC_INLINE uint32_t LL_I3C_GetMessageErrorCode(const I3C_TypeDef *I3Cx)
2670 {
2671 return (uint32_t)(READ_BIT(I3Cx->SER, I3C_SER_CODERR));
2672 }
2673
2674 /**
2675 * @brief Get CCC code of received command.
2676 * @rmtoll RMR RCODE LL_I3C_GetReceiveCommandCode
2677 * @param I3Cx I3C Instance.
2678 * @retval Value between Min_Data=0 to Max_Data=0xFF.
2679 */
LL_I3C_GetReceiveCommandCode(const I3C_TypeDef * I3Cx)2680 __STATIC_INLINE uint32_t LL_I3C_GetReceiveCommandCode(const I3C_TypeDef *I3Cx)
2681 {
2682 return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_RCODE) >> I3C_RMR_RCODE_Pos);
2683 }
2684
2685 /**
2686 * @}
2687 */
2688
2689 /** @defgroup I3C_LL_EF_Target Payload
2690 * @{
2691 */
2692
2693 /**
2694 * @brief Set Dynamic Address assigned to target x.
2695 * @rmtoll DEVRX DA LL_I3C_SetTargetDynamicAddress
2696 * @param I3Cx I3C Instance.
2697 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2698 * @param DynamicAddr Value between Min_Data=0 to Max_Data=0x7F
2699 * @retval None
2700 */
LL_I3C_SetTargetDynamicAddress(I3C_TypeDef * I3Cx,uint32_t TargetId,uint32_t DynamicAddr)2701 __STATIC_INLINE void LL_I3C_SetTargetDynamicAddress(I3C_TypeDef *I3Cx, uint32_t TargetId, uint32_t DynamicAddr)
2702 {
2703 MODIFY_REG(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DA, (DynamicAddr << I3C_DEVRX_DA_Pos));
2704 }
2705
2706 /**
2707 * @brief Get Dynamic Address assigned to target x.
2708 * @rmtoll DEVRX DA LL_I3C_GetTargetDynamicAddress
2709 * @param I3Cx I3C Instance.
2710 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2711 * @retval Value between Min_Data=0 to Max_Data=0x7F
2712 */
LL_I3C_GetTargetDynamicAddress(const I3C_TypeDef * I3Cx,uint32_t TargetId)2713 __STATIC_INLINE uint32_t LL_I3C_GetTargetDynamicAddress(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2714 {
2715 return (uint32_t)((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DA)) >> I3C_DEVRX_DA_Pos);
2716 }
2717
2718 /**
2719 * @brief Enable IBI Acknowledgement from target x(controller mode).
2720 * @note The bit DIS is automatically set when CRACK or IBIACK are set.
2721 * This mean DEVRX register access is not allowed.
2722 * Reset CRACK and IBIACK will reset DIS bit.
2723 * @rmtoll DEVRX IBIACK LL_I3C_EnableTargetIBIAck
2724 * @param I3Cx I3C Instance.
2725 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2726 * @retval None
2727 */
LL_I3C_EnableTargetIBIAck(I3C_TypeDef * I3Cx,uint32_t TargetId)2728 __STATIC_INLINE void LL_I3C_EnableTargetIBIAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
2729 {
2730 SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK);
2731 }
2732
2733 /**
2734 * @brief Disable IBI Acknowledgement from target x (controller mode).
2735 * @rmtoll DEVRX IBIACK LL_I3C_DisableTargetIBIAck
2736 * @param I3Cx I3C Instance.
2737 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2738 * @retval None
2739 */
LL_I3C_DisableTargetIBIAck(I3C_TypeDef * I3Cx,uint32_t TargetId)2740 __STATIC_INLINE void LL_I3C_DisableTargetIBIAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
2741 {
2742 CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK);
2743 }
2744
2745 /**
2746 * @brief Indicates if IBI from target x will be Acknowledged or Not Acknowledged (controller mode).
2747 * RESET: IBI Not Acknowledged.
2748 * SET: IBI Acknowledged.
2749 * @rmtoll DEVRX IBIACK LL_I3C_IsEnabledTargetIBIAck
2750 * @param I3Cx I3C Instance.
2751 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2752 * @retval State of bit (1 or 0).
2753 */
LL_I3C_IsEnabledTargetIBIAck(const I3C_TypeDef * I3Cx,uint32_t TargetId)2754 __STATIC_INLINE uint32_t LL_I3C_IsEnabledTargetIBIAck(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2755 {
2756 return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK) == I3C_DEVRX_IBIACK) ? 1UL : 0UL);
2757 }
2758
2759 /**
2760 * @brief Enable Controller-role Request Acknowledgement from target x(controller mode).
2761 * @note The bit DIS is automatically set when CRACK or IBIACK are set.
2762 * This mean DEVRX register access is not allowed.
2763 * Reset CRACK and IBIACK will reset DIS bit.
2764 * @rmtoll DEVRX CRACK LL_I3C_EnableTargetCRAck
2765 * @param I3Cx I3C Instance.
2766 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2767 * @retval None
2768 */
LL_I3C_EnableTargetCRAck(I3C_TypeDef * I3Cx,uint32_t TargetId)2769 __STATIC_INLINE void LL_I3C_EnableTargetCRAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
2770 {
2771 SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK);
2772 }
2773
2774 /**
2775 * @brief Disable Controller-role Request Acknowledgement from target x (controller mode).
2776 * @rmtoll DEVRX CRACK LL_I3C_DisableTargetCRAck
2777 * @param I3Cx I3C Instance.
2778 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2779 * @retval None
2780 */
LL_I3C_DisableTargetCRAck(I3C_TypeDef * I3Cx,uint32_t TargetId)2781 __STATIC_INLINE void LL_I3C_DisableTargetCRAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
2782 {
2783 CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK);
2784 }
2785
2786 /**
2787 * @brief Indicates if Controller-role Request from target x will be
2788 * Acknowledged or Not Acknowledged (controller mode).
2789 * RESET: Controller-role Request Not Acknowledged.
2790 * SET: Controller-role Request Acknowledged.
2791 * @rmtoll DEVRX CRACK LL_I3C_IsEnabledTargetCRAck
2792 * @param I3Cx I3C Instance.
2793 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2794 * @retval State of bit (1 or 0).
2795 */
LL_I3C_IsEnabledTargetCRAck(const I3C_TypeDef * I3Cx,uint32_t TargetId)2796 __STATIC_INLINE uint32_t LL_I3C_IsEnabledTargetCRAck(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2797 {
2798 return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK) == I3C_DEVRX_CRACK) ? 1UL : 0UL);
2799 }
2800
2801 /**
2802 * @brief Enable additional Mandatory Data Byte (MDB) follows the accepted IBI from target x.
2803 * @rmtoll DEVRX IBIDEN LL_I3C_EnableIBIAddData
2804 * @param I3Cx I3C Instance.
2805 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2806 * @retval None
2807 */
LL_I3C_EnableIBIAddData(I3C_TypeDef * I3Cx,uint32_t TargetId)2808 __STATIC_INLINE void LL_I3C_EnableIBIAddData(I3C_TypeDef *I3Cx, uint32_t TargetId)
2809 {
2810 SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN);
2811 }
2812
2813 /**
2814 * @brief Disable additional Mandatory Data Byte (MDB) follows the accepted IBI from target x.
2815 * @rmtoll DEVRX IBIDEN LL_I3C_DisableIBIAddData
2816 * @param I3Cx I3C Instance.
2817 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2818 * @retval None
2819 */
LL_I3C_DisableIBIAddData(I3C_TypeDef * I3Cx,uint32_t TargetId)2820 __STATIC_INLINE void LL_I3C_DisableIBIAddData(I3C_TypeDef *I3Cx, uint32_t TargetId)
2821 {
2822 CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN);
2823 }
2824
2825 /**
2826 * @brief Indicates if additional Mandatory Data Byte (MDB) follows the accepted IBI from target x.
2827 * RESET: No Mandatory Data Byte follows IBI.
2828 * SET: Mandatory Data Byte follows IBI.
2829 * @rmtoll DEVRX IBIDEN LL_I3C_IsEnabledIBIAddData
2830 * @param I3Cx I3C Instance.
2831 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2832 * @retval State of bit (1 or 0).
2833 */
LL_I3C_IsEnabledIBIAddData(const I3C_TypeDef * I3Cx,uint32_t TargetId)2834 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIBIAddData(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2835 {
2836 return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN) == I3C_DEVRX_IBIDEN) ? 1UL : 0UL);
2837 }
2838
2839 /**
2840 * @brief Enable Suspension of Current transfer during IBI treatment.
2841 * @note When set, this feature will allow controller to send
2842 * a Stop condition and CR FIFO is flushed after IBI treatment.
2843 * Software has to rewrite instructions in Control Register to start a new transfer.
2844 * @rmtoll DEVRX SUSP LL_I3C_EnableFrameSuspend
2845 * @param I3Cx I3C Instance.
2846 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2847 * @retval None
2848 */
LL_I3C_EnableFrameSuspend(I3C_TypeDef * I3Cx,uint32_t TargetId)2849 __STATIC_INLINE void LL_I3C_EnableFrameSuspend(I3C_TypeDef *I3Cx, uint32_t TargetId)
2850 {
2851 SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP);
2852 }
2853
2854 /**
2855 * @brief Disable Suspension of Current transfer during IBI treatment.
2856 * @note When set, this feature will allow controller to continue CR FIFO treatment after IBI treatment.
2857 * @rmtoll DEVRX SUSP LL_I3C_DisableFrameSuspend
2858 * @param I3Cx I3C Instance.
2859 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2860 * @retval None
2861 */
LL_I3C_DisableFrameSuspend(I3C_TypeDef * I3Cx,uint32_t TargetId)2862 __STATIC_INLINE void LL_I3C_DisableFrameSuspend(I3C_TypeDef *I3Cx, uint32_t TargetId)
2863 {
2864 CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP);
2865 }
2866
2867 /**
2868 * @brief Indicates if I3C transfer must be Suspended or not Suspended during IBI treatment from target x.
2869 * RESET: Transfer is not suspended. Instruction in CR FIFO are executed after IBI.
2870 * SET: Transfer is suspended (a Stop condition is sent). CR FIFO is flushed.
2871 * @rmtoll DEVRX SUSP LL_I3C_IsFrameMustBeSuspended
2872 * @param I3Cx I3C Instance.
2873 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2874 * @retval State of bit (1 or 0).
2875 */
LL_I3C_IsFrameMustBeSuspended(const I3C_TypeDef * I3Cx,uint32_t TargetId)2876 __STATIC_INLINE uint32_t LL_I3C_IsFrameMustBeSuspended(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2877 {
2878 return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP) == I3C_DEVRX_SUSP) ? 1UL : 0UL);
2879 }
2880
2881 /**
2882 * @brief Indicates if update of the Device Characteristics Register is Allowed or Not Allowed.
2883 * RESET: Device Characteristics Register update is Not Allowed.
2884 * SET: Device Characteristics Register update is Allowed.
2885 * @note Used to prevent software writing during reception of an IBI or Controller-role Request from target x.
2886 * @rmtoll DEVRX DIS LL_I3C_IsAllowedPayloadUpdate
2887 * @param I3Cx I3C Instance.
2888 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2889 * @retval State of bit (1 or 0).
2890 */
LL_I3C_IsAllowedPayloadUpdate(const I3C_TypeDef * I3Cx,uint32_t TargetId)2891 __STATIC_INLINE uint32_t LL_I3C_IsAllowedPayloadUpdate(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2892 {
2893 return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DIS) != I3C_DEVRX_DIS) ? 1UL : 0UL);
2894 }
2895
2896 /**
2897 * @brief Set I3C bus devices configuration.
2898 * @note This function is called only when the I3C instance is initialized as controller.
2899 * This function can be called by the controller application to help the automatic treatment when target have
2900 * capability of IBI and/or Control-Role.
2901 * @rmtoll DEVRX DA LL_I3C_ConfigDeviceCapabilities
2902 * @rmtoll DEVRX IBIACK LL_I3C_ConfigDeviceCapabilities
2903 * @rmtoll DEVRX IBIDEN LL_I3C_ConfigDeviceCapabilities
2904 * @rmtoll DEVRX CRACK LL_I3C_ConfigDeviceCapabilities
2905 * @param I3Cx I3C Instance.
2906 * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2907 * @param DynamicAddr Value between Min_Data=0 to Max_Data=0x7F
2908 * @param IBIAck Value This parameter can be one of the following values:
2909 * @arg @ref LL_I3C_IBI_CAPABILITY
2910 * @arg @ref LL_I3C_IBI_NO_CAPABILITY
2911 * @param IBIAddData This parameter can be one of the following values:
2912 * @arg @ref LL_I3C_IBI_DATA_ENABLE
2913 * @arg @ref LL_I3C_IBI_DATA_DISABLE
2914 * @param CRAck This parameter can be one of the following values:
2915 * @arg @ref LL_I3C_CR_CAPABILITY
2916 * @arg @ref LL_I3C_CR_NO_CAPABILITY
2917 * @retval None
2918 */
LL_I3C_ConfigDeviceCapabilities(I3C_TypeDef * I3Cx,uint32_t TargetId,uint32_t DynamicAddr,uint32_t IBIAck,uint32_t IBIAddData,uint32_t CRAck)2919 __STATIC_INLINE void LL_I3C_ConfigDeviceCapabilities(I3C_TypeDef *I3Cx,
2920 uint32_t TargetId,
2921 uint32_t DynamicAddr,
2922 uint32_t IBIAck,
2923 uint32_t IBIAddData,
2924 uint32_t CRAck)
2925 {
2926 MODIFY_REG(I3Cx->DEVRX[TargetId - 1U], \
2927 (I3C_DEVRX_DA | I3C_DEVRX_IBIACK | I3C_DEVRX_CRACK | I3C_DEVRX_IBIDEN), \
2928 ((DynamicAddr << I3C_DEVRX_DA_Pos) | IBIAck | IBIAddData | CRAck));
2929 }
2930 /**
2931 * @}
2932 */
2933
2934 /** @defgroup I3C_LL_EF_FLAG_management FLAG_management
2935 * @{
2936 */
2937
2938 /**
2939 * @brief Indicates the status of Control FIFO Empty flag.
2940 * RESET: One or more data are available in Control FIFO.
2941 * SET: No more data available in Control FIFO.
2942 * @rmtoll EVR CFEF LL_I3C_IsActiveFlag_CFE
2943 * @param I3Cx I3C Instance.
2944 * @retval State of bit (1 or 0).
2945 */
LL_I3C_IsActiveFlag_CFE(const I3C_TypeDef * I3Cx)2946 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CFE(const I3C_TypeDef *I3Cx)
2947 {
2948 return ((READ_BIT(I3Cx->EVR, I3C_EVR_CFEF) == (I3C_EVR_CFEF)) ? 1UL : 0UL);
2949 }
2950
2951 /**
2952 * @brief Indicates the status of Transmit FIFO Empty flag.
2953 * RESET: One or more data are available in Transmit FIFO.
2954 * SET: No more data available in Transmit FIFO.
2955 * @rmtoll EVR TXFEF LL_I3C_IsActiveFlag_TXFE
2956 * @param I3Cx I3C Instance.
2957 * @retval State of bit (1 or 0).
2958 */
LL_I3C_IsActiveFlag_TXFE(const I3C_TypeDef * I3Cx)2959 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXFE(const I3C_TypeDef *I3Cx)
2960 {
2961 return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXFEF) == (I3C_EVR_TXFEF)) ? 1UL : 0UL);
2962 }
2963
2964 /**
2965 * @brief Indicates the status of Control FIFO Not Full flag.
2966 * RESET: One or more free space available in Control FIFO.
2967 * SET: No more free space available in Control FIFO.
2968 * @note When a transfer is ongoing, the Control FIFO shall not be written unless this flag is set.
2969 * @rmtoll EVR CFNFF LL_I3C_IsActiveFlag_CFNF
2970 * @param I3Cx I3C Instance.
2971 * @retval State of bit (1 or 0).
2972 */
LL_I3C_IsActiveFlag_CFNF(const I3C_TypeDef * I3Cx)2973 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CFNF(const I3C_TypeDef *I3Cx)
2974 {
2975 return ((READ_BIT(I3Cx->EVR, I3C_EVR_CFNFF) == (I3C_EVR_CFNFF)) ? 1UL : 0UL);
2976 }
2977
2978 /**
2979 * @brief Indicates the status of Status FIFO Not Empty flag.
2980 * RESET: One or more free space available in Status FIFO.
2981 * SET: No more free space available in Status FIFO.
2982 * @note This flag is updated only when the FIFO is used, mean SMODE = 1.
2983 * @rmtoll EVR SFNEF LL_I3C_IsActiveFlag_SFNE
2984 * @param I3Cx I3C Instance.
2985 * @retval State of bit (1 or 0).
2986 */
LL_I3C_IsActiveFlag_SFNE(const I3C_TypeDef * I3Cx)2987 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_SFNE(const I3C_TypeDef *I3Cx)
2988 {
2989 return ((READ_BIT(I3Cx->EVR, I3C_EVR_SFNEF) == (I3C_EVR_SFNEF)) ? 1UL : 0UL);
2990 }
2991
2992 /**
2993 * @brief Indicates the status of Transmit FIFO Not Full flag.
2994 * RESET: One or more free space available in Transmit FIFO.
2995 * SET: No more free space available in Transmit FIFO.
2996 * @note When a transfer is ongoing, the Transmit FIFO shall not be written unless this flag is set.
2997 * @rmtoll EVR TXFNFF LL_I3C_IsActiveFlag_TXFNF
2998 * @param I3Cx I3C Instance.
2999 * @retval State of bit (1 or 0).
3000 */
LL_I3C_IsActiveFlag_TXFNF(const I3C_TypeDef * I3Cx)3001 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXFNF(const I3C_TypeDef *I3Cx)
3002 {
3003 return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXFNFF) == (I3C_EVR_TXFNFF)) ? 1UL : 0UL);
3004 }
3005
3006 /**
3007 * @brief Indicates the status of Receive FIFO Not Full flag.
3008 * RESET: One or more data are available in Receive FIFO.
3009 * SET: No more data available in Receive FIFO.
3010 * @rmtoll EVR RXFNEF LL_I3C_IsActiveFlag_RXFNE
3011 * @param I3Cx I3C Instance.
3012 * @retval State of bit (1 or 0).
3013 */
LL_I3C_IsActiveFlag_RXFNE(const I3C_TypeDef * I3Cx)3014 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXFNE(const I3C_TypeDef *I3Cx)
3015 {
3016 return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXFNEF) == (I3C_EVR_RXFNEF)) ? 1UL : 0UL);
3017 }
3018
3019 /**
3020 * @brief Indicates that the last Receive byte is available.
3021 * RESET: Clear default value.
3022 * SET: Last Receive byte ready to read from Receive FIFO.
3023 * @rmtoll EVR RXLASTF LL_I3C_IsActiveFlag_RXLAST
3024 * @param I3Cx I3C Instance.
3025 * @retval State of bit (1 or 0).
3026 */
LL_I3C_IsActiveFlag_RXLAST(const I3C_TypeDef * I3Cx)3027 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXLAST(const I3C_TypeDef *I3Cx)
3028 {
3029 return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXLASTF) == (I3C_EVR_RXLASTF)) ? 1UL : 0UL);
3030 }
3031
3032 /**
3033 * @brief Indicates that the last Transmit byte is written in FIFO.
3034 * RESET: Transmission is not finalized.
3035 * SET: Last Transmit byte is written in transmit FIFO.
3036 * @rmtoll EVR TXLASTF LL_I3C_IsActiveFlag_TXLAST
3037 * @param I3Cx I3C Instance.
3038 * @retval State of bit (1 or 0).
3039 */
LL_I3C_IsActiveFlag_TXLAST(const I3C_TypeDef * I3Cx)3040 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXLAST(const I3C_TypeDef *I3Cx)
3041 {
3042 return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXLASTF) == (I3C_EVR_TXLASTF)) ? 1UL : 0UL);
3043 }
3044
3045 /**
3046 * @brief Indicates the status of Frame Complete flag (controller and target mode).
3047 * RESET: Current Frame transfer is not finalized.
3048 * SET: Current Frame transfer is completed.
3049 * @rmtoll EVR FCF LL_I3C_IsActiveFlag_FC
3050 * @param I3Cx I3C Instance.
3051 * @retval State of bit (1 or 0).
3052 */
LL_I3C_IsActiveFlag_FC(const I3C_TypeDef * I3Cx)3053 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_FC(const I3C_TypeDef *I3Cx)
3054 {
3055 return ((READ_BIT(I3Cx->EVR, I3C_EVR_FCF) == (I3C_EVR_FCF)) ? 1UL : 0UL);
3056 }
3057
3058 /**
3059 * @brief Indicates the status of Reception Target End flag (controller mode).
3060 * RESET: Clear default value.
3061 * SET: Target prematurely ended a Read Command.
3062 * @note This flag is set only when status FIFO is not used, mean SMODE = 0.
3063 * @rmtoll EVR RXTGTENDF LL_I3C_IsActiveFlag_RXTGTEND
3064 * @param I3Cx I3C Instance.
3065 * @retval State of bit (1 or 0).
3066 */
LL_I3C_IsActiveFlag_RXTGTEND(const I3C_TypeDef * I3Cx)3067 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXTGTEND(const I3C_TypeDef *I3Cx)
3068 {
3069 return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXTGTENDF) == (I3C_EVR_RXTGTENDF)) ? 1UL : 0UL);
3070 }
3071
3072 /**
3073 * @brief Indicates the status of Error flag (controller and target mode).
3074 * RESET: Clear default value.
3075 * SET: One or more Errors are detected.
3076 * @rmtoll EVR ERRF LL_I3C_IsActiveFlag_ERR
3077 * @param I3Cx I3C Instance.
3078 * @retval State of bit (1 or 0).
3079 */
LL_I3C_IsActiveFlag_ERR(const I3C_TypeDef * I3Cx)3080 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ERR(const I3C_TypeDef *I3Cx)
3081 {
3082 return ((READ_BIT(I3Cx->EVR, I3C_EVR_ERRF) == (I3C_EVR_ERRF)) ? 1UL : 0UL);
3083 }
3084
3085 /**
3086 * @brief Indicates the status of IBI flag (controller mode).
3087 * RESET: Clear default value.
3088 * SET: An IBI have been received.
3089 * @rmtoll EVR IBIF LL_I3C_IsActiveFlag_IBI
3090 * @param I3Cx I3C Instance.
3091 * @retval State of bit (1 or 0).
3092 */
LL_I3C_IsActiveFlag_IBI(const I3C_TypeDef * I3Cx)3093 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_IBI(const I3C_TypeDef *I3Cx)
3094 {
3095 return ((READ_BIT(I3Cx->EVR, I3C_EVR_IBIF) == (I3C_EVR_IBIF)) ? 1UL : 0UL);
3096 }
3097
3098 /**
3099 * @brief Indicates the status of IBI End flag (target mode).
3100 * RESET: Clear default value.
3101 * SET: IBI procedure is finished.
3102 * @rmtoll EVR IBIENDF LL_I3C_IsActiveFlag_IBIEND
3103 * @param I3Cx I3C Instance.
3104 * @retval State of bit (1 or 0).
3105 */
LL_I3C_IsActiveFlag_IBIEND(const I3C_TypeDef * I3Cx)3106 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_IBIEND(const I3C_TypeDef *I3Cx)
3107 {
3108 return ((READ_BIT(I3Cx->EVR, I3C_EVR_IBIENDF) == (I3C_EVR_IBIENDF)) ? 1UL : 0UL);
3109 }
3110
3111 /**
3112 * @brief Indicates the status of Controller-role Request flag (controller mode).
3113 * RESET: Clear default value.
3114 * SET: A Controller-role request procedure have been received.
3115 * @rmtoll EVR CRF LL_I3C_IsActiveFlag_CR
3116 * @param I3Cx I3C Instance.
3117 * @retval State of bit (1 or 0).
3118 */
LL_I3C_IsActiveFlag_CR(const I3C_TypeDef * I3Cx)3119 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CR(const I3C_TypeDef *I3Cx)
3120 {
3121 return ((READ_BIT(I3Cx->EVR, I3C_EVR_CRF) == (I3C_EVR_CRF)) ? 1UL : 0UL);
3122 }
3123
3124 /**
3125 * @brief Indicates the status of Controller-role Request Update flag (target mode).
3126 * RESET: Clear default value.
3127 * SET: I3C device have gained Controller-role of the I3C Bus.
3128 * @rmtoll EVR BCUPDF LL_I3C_IsActiveFlag_CRUPD
3129 * @param I3Cx I3C Instance.
3130 * @retval State of bit (1 or 0).
3131 */
LL_I3C_IsActiveFlag_CRUPD(const I3C_TypeDef * I3Cx)3132 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CRUPD(const I3C_TypeDef *I3Cx)
3133 {
3134 return ((READ_BIT(I3Cx->EVR, I3C_EVR_CRUPDF) == (I3C_EVR_CRUPDF)) ? 1UL : 0UL);
3135 }
3136
3137 /**
3138 * @brief Indicates the status of Hot Join flag (controller mode).
3139 * RESET: Clear default value.
3140 * SET: A Hot Join request have been received.
3141 * @rmtoll EVR HJF LL_I3C_IsActiveFlag_HJ
3142 * @param I3Cx I3C Instance.
3143 * @retval State of bit (1 or 0).
3144 */
LL_I3C_IsActiveFlag_HJ(const I3C_TypeDef * I3Cx)3145 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_HJ(const I3C_TypeDef *I3Cx)
3146 {
3147 return ((READ_BIT(I3Cx->EVR, I3C_EVR_HJF) == (I3C_EVR_HJF)) ? 1UL : 0UL);
3148 }
3149
3150 /**
3151 * @brief Indicates the status of Wake Up flag (target mode).
3152 * RESET: Clear default value.
3153 * SET: I3C Internal clock not available on time to treat the falling edge on SCL.
3154 * @rmtoll EVR WKPF LL_I3C_IsActiveFlag_WKP
3155 * @param I3Cx I3C Instance.
3156 * @retval State of bit (1 or 0).
3157 */
LL_I3C_IsActiveFlag_WKP(const I3C_TypeDef * I3Cx)3158 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_WKP(const I3C_TypeDef *I3Cx)
3159 {
3160 return ((READ_BIT(I3Cx->EVR, I3C_EVR_WKPF) == (I3C_EVR_WKPF)) ? 1UL : 0UL);
3161 }
3162
3163 /**
3164 * @brief Indicates the status of Get flag (target mode).
3165 * RESET: Clear default value.
3166 * SET: A "get" type CCC have been received.
3167 * @rmtoll EVR GETF LL_I3C_IsActiveFlag_GET
3168 * @param I3Cx I3C Instance.
3169 * @retval State of bit (1 or 0).
3170 */
LL_I3C_IsActiveFlag_GET(const I3C_TypeDef * I3Cx)3171 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_GET(const I3C_TypeDef *I3Cx)
3172 {
3173 return ((READ_BIT(I3Cx->EVR, I3C_EVR_GETF) == (I3C_EVR_GETF)) ? 1UL : 0UL);
3174 }
3175
3176 /**
3177 * @brief Indicates the status of Get Status flag (target mode).
3178 * RESET: Clear default value.
3179 * SET: A GETSTATUS Command have been received.
3180 * @rmtoll EVR STAF LL_I3C_IsActiveFlag_STA
3181 * @param I3Cx I3C Instance.
3182 * @retval State of bit (1 or 0).
3183 */
LL_I3C_IsActiveFlag_STA(const I3C_TypeDef * I3Cx)3184 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_STA(const I3C_TypeDef *I3Cx)
3185 {
3186 return ((READ_BIT(I3Cx->EVR, I3C_EVR_STAF) == (I3C_EVR_STAF)) ? 1UL : 0UL);
3187 }
3188
3189 /**
3190 * @brief Indicates the status of Dynamic Address Update flag (target mode).
3191 * RESET: Clear default value.
3192 * SET: Own Dynamic Address have been updated.
3193 * @rmtoll EVR DAUPDF LL_I3C_IsActiveFlag_DAUPD
3194 * @param I3Cx I3C Instance.
3195 * @retval State of bit (1 or 0).
3196 */
LL_I3C_IsActiveFlag_DAUPD(const I3C_TypeDef * I3Cx)3197 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DAUPD(const I3C_TypeDef *I3Cx)
3198 {
3199 return ((READ_BIT(I3Cx->EVR, I3C_EVR_DAUPDF) == (I3C_EVR_DAUPDF)) ? 1UL : 0UL);
3200 }
3201
3202 /**
3203 * @brief Indicates the status of Max Write Length flag (target mode).
3204 * RESET: Clear default value.
3205 * SET: Max Write Length have been updated.
3206 * @rmtoll EVR MWLUPDF LL_I3C_IsActiveFlag_MWLUPD
3207 * @param I3Cx I3C Instance.
3208 * @retval State of bit (1 or 0).
3209 */
LL_I3C_IsActiveFlag_MWLUPD(const I3C_TypeDef * I3Cx)3210 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_MWLUPD(const I3C_TypeDef *I3Cx)
3211 {
3212 return ((READ_BIT(I3Cx->EVR, I3C_EVR_MWLUPDF) == (I3C_EVR_MWLUPDF)) ? 1UL : 0UL);
3213 }
3214
3215 /**
3216 * @brief Indicates the status of Max Read Length flag (target mode).
3217 * RESET: Clear default value.
3218 * SET: Max Read Length have been updated.
3219 * @rmtoll EVR MRLUPDF LL_I3C_IsActiveFlag_MRLUPD
3220 * @param I3Cx I3C Instance.
3221 * @retval State of bit (1 or 0).
3222 */
LL_I3C_IsActiveFlag_MRLUPD(const I3C_TypeDef * I3Cx)3223 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_MRLUPD(const I3C_TypeDef *I3Cx)
3224 {
3225 return ((READ_BIT(I3Cx->EVR, I3C_EVR_MRLUPDF) == (I3C_EVR_MRLUPDF)) ? 1UL : 0UL);
3226 }
3227
3228 /**
3229 * @brief Indicates the status of Reset flag (target mode).
3230 * RESET: Clear default value.
3231 * SET: A Reset Pattern have been received.
3232 * @rmtoll EVR RSTF LL_I3C_IsActiveFlag_RST
3233 * @param I3Cx I3C Instance.
3234 * @retval State of bit (1 or 0).
3235 */
LL_I3C_IsActiveFlag_RST(const I3C_TypeDef * I3Cx)3236 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RST(const I3C_TypeDef *I3Cx)
3237 {
3238 return ((READ_BIT(I3Cx->EVR, I3C_EVR_RSTF) == (I3C_EVR_RSTF)) ? 1UL : 0UL);
3239 }
3240
3241 /**
3242 * @brief Indicates the status of Active State flag (target mode).
3243 * RESET: Clear default value.
3244 * SET: The Activity State have been updated.
3245 * @rmtoll EVR ASUPDF LL_I3C_IsActiveFlag_ASUPD
3246 * @param I3Cx I3C Instance.
3247 * @retval State of bit (1 or 0).
3248 */
LL_I3C_IsActiveFlag_ASUPD(const I3C_TypeDef * I3Cx)3249 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ASUPD(const I3C_TypeDef *I3Cx)
3250 {
3251 return ((READ_BIT(I3Cx->EVR, I3C_EVR_ASUPDF) == (I3C_EVR_ASUPDF)) ? 1UL : 0UL);
3252 }
3253
3254 /**
3255 * @brief Indicates the status of Interrupt Update flag (target mode).
3256 * RESET: Clear default value.
3257 * SET: One or more Interrupt autorized have been updated.
3258 * @rmtoll EVR INTUPDF LL_I3C_IsActiveFlag_INTUPD
3259 * @param I3Cx I3C Instance.
3260 * @retval State of bit (1 or 0).
3261 */
LL_I3C_IsActiveFlag_INTUPD(const I3C_TypeDef * I3Cx)3262 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_INTUPD(const I3C_TypeDef *I3Cx)
3263 {
3264 return ((READ_BIT(I3Cx->EVR, I3C_EVR_INTUPDF) == (I3C_EVR_INTUPDF)) ? 1UL : 0UL);
3265 }
3266
3267 /**
3268 * @brief Indicates the status of Define List Targets flag (target mode).
3269 * RESET: Clear default value.
3270 * SET: A Define List Targets Command have been received.
3271 * @rmtoll EVR DEFF LL_I3C_IsActiveFlag_DEF
3272 * @param I3Cx I3C Instance.
3273 * @retval State of bit (1 or 0).
3274 */
LL_I3C_IsActiveFlag_DEF(const I3C_TypeDef * I3Cx)3275 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DEF(const I3C_TypeDef *I3Cx)
3276 {
3277 return ((READ_BIT(I3Cx->EVR, I3C_EVR_DEFF) == (I3C_EVR_DEFF)) ? 1UL : 0UL);
3278 }
3279
3280 /**
3281 * @brief Indicates the status of Define List Group Addresses flag.
3282 * RESET: Clear default value.
3283 * SET: A Define List Group Addresses have been received.
3284 * @rmtoll EVR GRPF LL_I3C_IsActiveFlag_GRP
3285 * @param I3Cx I3C Instance.
3286 * @retval State of bit (1 or 0).
3287 */
LL_I3C_IsActiveFlag_GRP(const I3C_TypeDef * I3Cx)3288 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_GRP(const I3C_TypeDef *I3Cx)
3289 {
3290 return ((READ_BIT(I3Cx->EVR, I3C_EVR_GRPF) == (I3C_EVR_GRPF)) ? 1UL : 0UL);
3291 }
3292
3293 /**
3294 * @brief Indicates the status of Protocol Error flag.
3295 * RESET: Clear default value.
3296 * SET: Protocol error detected.
3297 * @rmtoll SER PERR LL_I3C_IsActiveFlag_PERR
3298 * @param I3Cx I3C Instance.
3299 * @retval State of bit (1 or 0).
3300 */
LL_I3C_IsActiveFlag_PERR(const I3C_TypeDef * I3Cx)3301 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_PERR(const I3C_TypeDef *I3Cx)
3302 {
3303 return ((READ_BIT(I3Cx->SER, I3C_SER_PERR) == (I3C_SER_PERR)) ? 1UL : 0UL);
3304 }
3305
3306 /**
3307 * @brief Indicates the status of SCL Stall Error flag (target mode).
3308 * RESET: Clear default value.
3309 * SET: Target detected that SCL was stable for more than 125us during I3C SDR read.
3310 * @rmtoll SER STALL LL_I3C_IsActiveFlag_STALL
3311 * @param I3Cx I3C Instance.
3312 * @retval State of bit (1 or 0).
3313 */
LL_I3C_IsActiveFlag_STALL(const I3C_TypeDef * I3Cx)3314 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_STALL(const I3C_TypeDef *I3Cx)
3315 {
3316 return ((READ_BIT(I3Cx->SER, I3C_SER_STALL) == (I3C_SER_STALL)) ? 1UL : 0UL);
3317 }
3318
3319 /**
3320 * @brief Indicates the status of RX or TX FIFO Overrun flag.
3321 * RESET: Clear default value.
3322 * SET: RX FIFO Full or TX FIFO Empty depending of direction of message.
3323 * @rmtoll SER DOVR LL_I3C_IsActiveFlag_DOVR
3324 * @param I3Cx I3C Instance.
3325 * @retval State of bit (1 or 0).
3326 */
LL_I3C_IsActiveFlag_DOVR(const I3C_TypeDef * I3Cx)3327 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DOVR(const I3C_TypeDef *I3Cx)
3328 {
3329 return ((READ_BIT(I3Cx->SER, I3C_SER_DOVR) == (I3C_SER_DOVR)) ? 1UL : 0UL);
3330 }
3331
3332 /**
3333 * @brief Indicates the status of Control or Status FIFO Overrun flag (controller mode).
3334 * RESET: Clear default value.
3335 * SET: Status FIFO Full or Control FIFO Empty after Restart.
3336 * @rmtoll SER COVR LL_I3C_IsActiveFlag_COVR
3337 * @param I3Cx I3C Instance.
3338 * @retval State of bit (1 or 0).
3339 */
LL_I3C_IsActiveFlag_COVR(const I3C_TypeDef * I3Cx)3340 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_COVR(const I3C_TypeDef *I3Cx)
3341 {
3342 return ((READ_BIT(I3Cx->SER, I3C_SER_COVR) == (I3C_SER_COVR)) ? 1UL : 0UL);
3343 }
3344
3345 /**
3346 * @brief Indicates the status of Address not acknowledged flag (controller mode).
3347 * RESET: Clear default value.
3348 * SET: Controller detected that Target nacked static or dynamic address.
3349 * @rmtoll SER ANACK LL_I3C_IsActiveFlag_ANACK
3350 * @param I3Cx I3C Instance.
3351 * @retval State of bit (1 or 0).
3352 */
LL_I3C_IsActiveFlag_ANACK(const I3C_TypeDef * I3Cx)3353 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ANACK(const I3C_TypeDef *I3Cx)
3354 {
3355 return ((READ_BIT(I3Cx->SER, I3C_SER_ANACK) == (I3C_SER_ANACK)) ? 1UL : 0UL);
3356 }
3357
3358 /**
3359 * @brief Indicates the status of Data not acknowledged flag (controller mode).
3360 * RESET: Clear default value.
3361 * SET: Controller detected that Target nacked Data byte.
3362 * @rmtoll SER DNACK LL_I3C_IsActiveFlag_DNACK
3363 * @param I3Cx I3C Instance.
3364 * @retval State of bit (1 or 0).
3365 */
LL_I3C_IsActiveFlag_DNACK(const I3C_TypeDef * I3Cx)3366 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DNACK(const I3C_TypeDef *I3Cx)
3367 {
3368 return ((READ_BIT(I3Cx->SER, I3C_SER_DNACK) == (I3C_SER_DNACK)) ? 1UL : 0UL);
3369 }
3370
3371 /**
3372 * @brief Indicates the status of Data error flag (controller mode).
3373 * RESET: Clear default value.
3374 * SET: Controller detected data error during Controller-role handoff process.
3375 * @rmtoll SER DERR LL_I3C_IsActiveFlag_DERR
3376 * @param I3Cx I3C Instance.
3377 * @retval State of bit (1 or 0).
3378 */
LL_I3C_IsActiveFlag_DERR(const I3C_TypeDef * I3Cx)3379 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DERR(const I3C_TypeDef *I3Cx)
3380 {
3381 return ((READ_BIT(I3Cx->SER, I3C_SER_DERR) == (I3C_SER_DERR)) ? 1UL : 0UL);
3382 }
3383
3384 /**
3385 * @}
3386 */
3387
3388 /** @defgroup I3C_LL_EF_IT_Management IT_Management
3389 * @{
3390 */
3391
3392 /**
3393 * @brief Enable Control FIFO Not Full interrupt.
3394 * @rmtoll IER CFNFIE LL_I3C_EnableIT_CFNF
3395 * @param I3Cx I3C Instance.
3396 * @retval None
3397 */
LL_I3C_EnableIT_CFNF(I3C_TypeDef * I3Cx)3398 __STATIC_INLINE void LL_I3C_EnableIT_CFNF(I3C_TypeDef *I3Cx)
3399 {
3400 SET_BIT(I3Cx->IER, I3C_IER_CFNFIE);
3401 }
3402
3403 /**
3404 * @brief Disable Control FIFO Not Full interrupt.
3405 * @rmtoll IER CFNFIE LL_I3C_DisableIT_CFNF
3406 * @param I3Cx I3C Instance.
3407 * @retval None
3408 */
LL_I3C_DisableIT_CFNF(I3C_TypeDef * I3Cx)3409 __STATIC_INLINE void LL_I3C_DisableIT_CFNF(I3C_TypeDef *I3Cx)
3410 {
3411 CLEAR_BIT(I3Cx->IER, I3C_IER_CFNFIE);
3412 }
3413
3414 /**
3415 * @brief Check if Control FIFO Not Full interrupt is enabled or disabled.
3416 * @rmtoll IER CFNFIE LL_I3C_IsEnabledIT_CFNF
3417 * @param I3Cx I3C Instance.
3418 * @retval State of bit (1 or 0).
3419 */
LL_I3C_IsEnabledIT_CFNF(const I3C_TypeDef * I3Cx)3420 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CFNF(const I3C_TypeDef *I3Cx)
3421 {
3422 return ((READ_BIT(I3Cx->IER, I3C_IER_CFNFIE) == (I3C_IER_CFNFIE)) ? 1UL : 0UL);
3423 }
3424
3425 /**
3426 * @brief Enable Status FIFO Not Empty interrupt.
3427 * @rmtoll IER SFNEIE LL_I3C_EnableIT_SFNE
3428 * @param I3Cx I3C Instance.
3429 * @retval None
3430 */
LL_I3C_EnableIT_SFNE(I3C_TypeDef * I3Cx)3431 __STATIC_INLINE void LL_I3C_EnableIT_SFNE(I3C_TypeDef *I3Cx)
3432 {
3433 SET_BIT(I3Cx->IER, I3C_IER_SFNEIE);
3434 }
3435
3436 /**
3437 * @brief Disable Status FIFO Not Empty interrupt.
3438 * @rmtoll IER SFNEIE LL_I3C_DisableIT_SFNE
3439 * @param I3Cx I3C Instance.
3440 * @retval None
3441 */
LL_I3C_DisableIT_SFNE(I3C_TypeDef * I3Cx)3442 __STATIC_INLINE void LL_I3C_DisableIT_SFNE(I3C_TypeDef *I3Cx)
3443 {
3444 CLEAR_BIT(I3Cx->IER, I3C_IER_SFNEIE);
3445 }
3446
3447 /**
3448 * @brief Check if Status FIFO Not Empty interrupt is enabled or disabled.
3449 * @rmtoll IER SFNEIE LL_I3C_IsEnabledIT_SFNE
3450 * @param I3Cx I3C Instance.
3451 * @retval State of bit (1 or 0).
3452 */
LL_I3C_IsEnabledIT_SFNE(const I3C_TypeDef * I3Cx)3453 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_SFNE(const I3C_TypeDef *I3Cx)
3454 {
3455 return ((READ_BIT(I3Cx->IER, I3C_IER_SFNEIE) == (I3C_IER_SFNEIE)) ? 1UL : 0UL);
3456 }
3457
3458 /**
3459 * @brief Enable Transmit FIFO Not Full interrupt.
3460 * @rmtoll IER TXFNFIE LL_I3C_EnableIT_TXFNF
3461 * @param I3Cx I3C Instance.
3462 * @retval None
3463 */
LL_I3C_EnableIT_TXFNF(I3C_TypeDef * I3Cx)3464 __STATIC_INLINE void LL_I3C_EnableIT_TXFNF(I3C_TypeDef *I3Cx)
3465 {
3466 SET_BIT(I3Cx->IER, I3C_IER_TXFNFIE);
3467 }
3468
3469 /**
3470 * @brief Disable Transmit FIFO Not Full interrupt.
3471 * @rmtoll IER TXFNFIE LL_I3C_DisableIT_TXFNF
3472 * @param I3Cx I3C Instance.
3473 * @retval None
3474 */
LL_I3C_DisableIT_TXFNF(I3C_TypeDef * I3Cx)3475 __STATIC_INLINE void LL_I3C_DisableIT_TXFNF(I3C_TypeDef *I3Cx)
3476 {
3477 CLEAR_BIT(I3Cx->IER, I3C_IER_TXFNFIE);
3478 }
3479
3480 /**
3481 * @brief Check if Transmit FIFO Not Full interrupt is enabled or disabled.
3482 * @rmtoll IER TXFNFIE LL_I3C_IsEnabledIT_TXFNF
3483 * @param I3Cx I3C Instance.
3484 * @retval State of bit (1 or 0).
3485 */
LL_I3C_IsEnabledIT_TXFNF(const I3C_TypeDef * I3Cx)3486 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_TXFNF(const I3C_TypeDef *I3Cx)
3487 {
3488 return ((READ_BIT(I3Cx->IER, I3C_IER_TXFNFIE) == (I3C_IER_TXFNFIE)) ? 1UL : 0UL);
3489 }
3490
3491 /**
3492 * @brief Enable Receive FIFO Not Empty interrupt.
3493 * @rmtoll IER RXFNEIE LL_I3C_EnableIT_RXFNE
3494 * @param I3Cx I3C Instance.
3495 * @retval None
3496 */
LL_I3C_EnableIT_RXFNE(I3C_TypeDef * I3Cx)3497 __STATIC_INLINE void LL_I3C_EnableIT_RXFNE(I3C_TypeDef *I3Cx)
3498 {
3499 SET_BIT(I3Cx->IER, I3C_IER_RXFNEIE);
3500 }
3501
3502 /**
3503 * @brief Disable Receive FIFO Not Empty interrupt.
3504 * @rmtoll IER RXFNEIE LL_I3C_DisableIT_RXFNE
3505 * @param I3Cx I3C Instance.
3506 * @retval None
3507 */
LL_I3C_DisableIT_RXFNE(I3C_TypeDef * I3Cx)3508 __STATIC_INLINE void LL_I3C_DisableIT_RXFNE(I3C_TypeDef *I3Cx)
3509 {
3510 CLEAR_BIT(I3Cx->IER, I3C_IER_RXFNEIE);
3511 }
3512
3513 /**
3514 * @brief Check if Receive FIFO Not Empty interrupt is enabled or disabled.
3515 * @rmtoll IER RXFNEIE LL_I3C_IsEnabledIT_RXFNE
3516 * @param I3Cx I3C Instance.
3517 * @retval State of bit (1 or 0).
3518 */
LL_I3C_IsEnabledIT_RXFNE(const I3C_TypeDef * I3Cx)3519 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RXFNE(const I3C_TypeDef *I3Cx)
3520 {
3521 return ((READ_BIT(I3Cx->IER, I3C_IER_RXFNEIE) == (I3C_IER_RXFNEIE)) ? 1UL : 0UL);
3522 }
3523
3524 /**
3525 * @brief Enable Frame Complete interrupt.
3526 * @rmtoll IER FCIE LL_I3C_EnableIT_FC
3527 * @param I3Cx I3C Instance.
3528 * @retval None
3529 */
LL_I3C_EnableIT_FC(I3C_TypeDef * I3Cx)3530 __STATIC_INLINE void LL_I3C_EnableIT_FC(I3C_TypeDef *I3Cx)
3531 {
3532 SET_BIT(I3Cx->IER, I3C_IER_FCIE);
3533 }
3534
3535 /**
3536 * @brief Disable Frame Complete interrupt.
3537 * @rmtoll IER FCIE LL_I3C_DisableIT_FC
3538 * @param I3Cx I3C Instance.
3539 * @retval None
3540 */
LL_I3C_DisableIT_FC(I3C_TypeDef * I3Cx)3541 __STATIC_INLINE void LL_I3C_DisableIT_FC(I3C_TypeDef *I3Cx)
3542 {
3543 CLEAR_BIT(I3Cx->IER, I3C_IER_FCIE);
3544 }
3545
3546 /**
3547 * @brief Check if Frame Complete interrupt is enabled or disabled.
3548 * @rmtoll IER FCIE LL_I3C_IsEnabledIT_FC
3549 * @param I3Cx I3C Instance.
3550 * @retval State of bit (1 or 0).
3551 */
LL_I3C_IsEnabledIT_FC(const I3C_TypeDef * I3Cx)3552 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_FC(const I3C_TypeDef *I3Cx)
3553 {
3554 return ((READ_BIT(I3Cx->IER, I3C_IER_FCIE) == (I3C_IER_FCIE)) ? 1UL : 0UL);
3555 }
3556
3557 /**
3558 * @brief Enable Reception Target End interrupt.
3559 * @rmtoll IER RXTGTENDIE LL_I3C_EnableIT_RXTGTEND
3560 * @param I3Cx I3C Instance.
3561 * @retval None
3562 */
LL_I3C_EnableIT_RXTGTEND(I3C_TypeDef * I3Cx)3563 __STATIC_INLINE void LL_I3C_EnableIT_RXTGTEND(I3C_TypeDef *I3Cx)
3564 {
3565 SET_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE);
3566 }
3567
3568 /**
3569 * @brief Disable Reception Target End interrupt.
3570 * @rmtoll IER RXTGTENDIE LL_I3C_DisableIT_RXTGTEND
3571 * @param I3Cx I3C Instance.
3572 * @retval None
3573 */
LL_I3C_DisableIT_RXTGTEND(I3C_TypeDef * I3Cx)3574 __STATIC_INLINE void LL_I3C_DisableIT_RXTGTEND(I3C_TypeDef *I3Cx)
3575 {
3576 CLEAR_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE);
3577 }
3578
3579 /**
3580 * @brief Check if Reception Target End interrupt is enabled or disabled.
3581 * @rmtoll IER RXTGTENDIE LL_I3C_IsEnabledIT_RXTGTEND
3582 * @param I3Cx I3C Instance.
3583 * @retval State of bit (1 or 0).
3584 */
LL_I3C_IsEnabledIT_RXTGTEND(const I3C_TypeDef * I3Cx)3585 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RXTGTEND(const I3C_TypeDef *I3Cx)
3586 {
3587 return ((READ_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE) == (I3C_IER_RXTGTENDIE)) ? 1UL : 0UL);
3588 }
3589
3590 /**
3591 * @brief Enable Error interrupt.
3592 * @rmtoll IER ERRIE LL_I3C_EnableIT_ERR
3593 * @param I3Cx I3C Instance.
3594 * @retval None
3595 */
LL_I3C_EnableIT_ERR(I3C_TypeDef * I3Cx)3596 __STATIC_INLINE void LL_I3C_EnableIT_ERR(I3C_TypeDef *I3Cx)
3597 {
3598 SET_BIT(I3Cx->IER, I3C_IER_ERRIE);
3599 }
3600
3601 /**
3602 * @brief Disable Error interrupt.
3603 * @rmtoll IER ERRIE LL_I3C_DisableIT_ERR
3604 * @param I3Cx I3C Instance.
3605 * @retval None
3606 */
LL_I3C_DisableIT_ERR(I3C_TypeDef * I3Cx)3607 __STATIC_INLINE void LL_I3C_DisableIT_ERR(I3C_TypeDef *I3Cx)
3608 {
3609 CLEAR_BIT(I3Cx->IER, I3C_IER_ERRIE);
3610 }
3611
3612 /**
3613 * @brief Check if Error interrupt is enabled or disabled.
3614 * @rmtoll IER ERRIE LL_I3C_IsEnabledIT_ERR
3615 * @param I3Cx I3C Instance.
3616 * @retval State of bit (1 or 0).
3617 */
LL_I3C_IsEnabledIT_ERR(const I3C_TypeDef * I3Cx)3618 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_ERR(const I3C_TypeDef *I3Cx)
3619 {
3620 return ((READ_BIT(I3Cx->IER, I3C_IER_ERRIE) == (I3C_IER_ERRIE)) ? 1UL : 0UL);
3621 }
3622
3623 /**
3624 * @brief Enable IBI interrupt.
3625 * @rmtoll IER IBIIE LL_I3C_EnableIT_IBI
3626 * @param I3Cx I3C Instance.
3627 * @retval None
3628 */
LL_I3C_EnableIT_IBI(I3C_TypeDef * I3Cx)3629 __STATIC_INLINE void LL_I3C_EnableIT_IBI(I3C_TypeDef *I3Cx)
3630 {
3631 SET_BIT(I3Cx->IER, I3C_IER_IBIIE);
3632 }
3633
3634 /**
3635 * @brief Disable IBI interrupt.
3636 * @rmtoll IER IBIIE LL_I3C_DisableIT_IBI
3637 * @param I3Cx I3C Instance.
3638 * @retval None
3639 */
LL_I3C_DisableIT_IBI(I3C_TypeDef * I3Cx)3640 __STATIC_INLINE void LL_I3C_DisableIT_IBI(I3C_TypeDef *I3Cx)
3641 {
3642 CLEAR_BIT(I3Cx->IER, I3C_IER_IBIIE);
3643 }
3644
3645 /**
3646 * @brief Check if IBI interrupt is enabled or disabled.
3647 * @rmtoll IER IBIIE LL_I3C_IsEnabledIT_IBI
3648 * @param I3Cx I3C Instance.
3649 * @retval State of bit (1 or 0).
3650 */
LL_I3C_IsEnabledIT_IBI(const I3C_TypeDef * I3Cx)3651 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_IBI(const I3C_TypeDef *I3Cx)
3652 {
3653 return ((READ_BIT(I3Cx->IER, I3C_IER_IBIIE) == (I3C_IER_IBIIE)) ? 1UL : 0UL);
3654 }
3655
3656 /**
3657 * @brief Enable IBI End interrupt.
3658 * @rmtoll IER IBIENDIE LL_I3C_EnableIT_IBIEND
3659 * @param I3Cx I3C Instance.
3660 * @retval None
3661 */
LL_I3C_EnableIT_IBIEND(I3C_TypeDef * I3Cx)3662 __STATIC_INLINE void LL_I3C_EnableIT_IBIEND(I3C_TypeDef *I3Cx)
3663 {
3664 SET_BIT(I3Cx->IER, I3C_IER_IBIENDIE);
3665 }
3666
3667 /**
3668 * @brief Disable IBI End interrupt.
3669 * @rmtoll IER IBIENDIE LL_I3C_DisableIT_IBIEND
3670 * @param I3Cx I3C Instance.
3671 * @retval None
3672 */
LL_I3C_DisableIT_IBIEND(I3C_TypeDef * I3Cx)3673 __STATIC_INLINE void LL_I3C_DisableIT_IBIEND(I3C_TypeDef *I3Cx)
3674 {
3675 CLEAR_BIT(I3Cx->IER, I3C_IER_IBIENDIE);
3676 }
3677
3678 /**
3679 * @brief Check if IBI End interrupt is enabled or disabled.
3680 * @rmtoll IER IBIENDIE LL_I3C_IsEnabledIT_IBIEND
3681 * @param I3Cx I3C Instance.
3682 * @retval State of bit (1 or 0).
3683 */
LL_I3C_IsEnabledIT_IBIEND(const I3C_TypeDef * I3Cx)3684 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_IBIEND(const I3C_TypeDef *I3Cx)
3685 {
3686 return ((READ_BIT(I3Cx->IER, I3C_IER_IBIENDIE) == (I3C_IER_IBIENDIE)) ? 1UL : 0UL);
3687 }
3688
3689 /**
3690 * @brief Enable Controller-role interrupt.
3691 * @rmtoll IER CRIE LL_I3C_EnableIT_CR
3692 * @param I3Cx I3C Instance.
3693 * @retval None
3694 */
LL_I3C_EnableIT_CR(I3C_TypeDef * I3Cx)3695 __STATIC_INLINE void LL_I3C_EnableIT_CR(I3C_TypeDef *I3Cx)
3696 {
3697 SET_BIT(I3Cx->IER, I3C_IER_CRIE);
3698 }
3699
3700 /**
3701 * @brief Disable Controller-role interrupt.
3702 * @rmtoll IER CRIE LL_I3C_DisableIT_CR
3703 * @param I3Cx I3C Instance.
3704 * @retval None
3705 */
LL_I3C_DisableIT_CR(I3C_TypeDef * I3Cx)3706 __STATIC_INLINE void LL_I3C_DisableIT_CR(I3C_TypeDef *I3Cx)
3707 {
3708 CLEAR_BIT(I3Cx->IER, I3C_IER_CRIE);
3709 }
3710
3711 /**
3712 * @brief Check if Controller-role interrupt is enabled or disabled.
3713 * @rmtoll IER CRIE LL_I3C_IsEnabledIT_CR
3714 * @param I3Cx I3C Instance.
3715 * @retval State of bit (1 or 0).
3716 */
LL_I3C_IsEnabledIT_CR(const I3C_TypeDef * I3Cx)3717 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CR(const I3C_TypeDef *I3Cx)
3718 {
3719 return ((READ_BIT(I3Cx->IER, I3C_IER_CRIE) == (I3C_IER_CRIE)) ? 1UL : 0UL);
3720 }
3721
3722 /**
3723 * @brief Enable Controller-role Update interrupt.
3724 * @rmtoll IER CRUPDIE LL_I3C_EnableIT_CRUPD
3725 * @param I3Cx I3C Instance.
3726 * @retval None
3727 */
LL_I3C_EnableIT_CRUPD(I3C_TypeDef * I3Cx)3728 __STATIC_INLINE void LL_I3C_EnableIT_CRUPD(I3C_TypeDef *I3Cx)
3729 {
3730 SET_BIT(I3Cx->IER, I3C_IER_CRUPDIE);
3731 }
3732
3733 /**
3734 * @brief Disable Controller-role Update interrupt.
3735 * @rmtoll IER CRUPDIE LL_I3C_DisableIT_CRUPD
3736 * @param I3Cx I3C Instance.
3737 * @retval None
3738 */
LL_I3C_DisableIT_CRUPD(I3C_TypeDef * I3Cx)3739 __STATIC_INLINE void LL_I3C_DisableIT_CRUPD(I3C_TypeDef *I3Cx)
3740 {
3741 CLEAR_BIT(I3Cx->IER, I3C_IER_CRUPDIE);
3742 }
3743
3744 /**
3745 * @brief Check if Controller-role Update interrupt is enabled or disabled.
3746 * @rmtoll IER CRUPDIE LL_I3C_IsEnabledIT_CRUPD
3747 * @param I3Cx I3C Instance.
3748 * @retval State of bit (1 or 0).
3749 */
LL_I3C_IsEnabledIT_CRUPD(const I3C_TypeDef * I3Cx)3750 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CRUPD(const I3C_TypeDef *I3Cx)
3751 {
3752 return ((READ_BIT(I3Cx->IER, I3C_IER_CRUPDIE) == (I3C_IER_CRUPDIE)) ? 1UL : 0UL);
3753 }
3754
3755 /**
3756 * @brief Enable Hot Join interrupt.
3757 * @rmtoll IER HJIE LL_I3C_EnableIT_HJ
3758 * @param I3Cx I3C Instance.
3759 * @retval None
3760 */
LL_I3C_EnableIT_HJ(I3C_TypeDef * I3Cx)3761 __STATIC_INLINE void LL_I3C_EnableIT_HJ(I3C_TypeDef *I3Cx)
3762 {
3763 SET_BIT(I3Cx->IER, I3C_IER_HJIE);
3764 }
3765
3766 /**
3767 * @brief Disable Hot Join interrupt.
3768 * @rmtoll IER HJIE LL_I3C_DisableIT_HJ
3769 * @param I3Cx I3C Instance.
3770 * @retval None
3771 */
LL_I3C_DisableIT_HJ(I3C_TypeDef * I3Cx)3772 __STATIC_INLINE void LL_I3C_DisableIT_HJ(I3C_TypeDef *I3Cx)
3773 {
3774 CLEAR_BIT(I3Cx->IER, I3C_IER_HJIE);
3775 }
3776
3777 /**
3778 * @brief Check if Hot Join interrupt is enabled or disabled.
3779 * @rmtoll IER HJIE LL_I3C_IsEnabledIT_HJ
3780 * @param I3Cx I3C Instance.
3781 * @retval State of bit (1 or 0).
3782 */
LL_I3C_IsEnabledIT_HJ(const I3C_TypeDef * I3Cx)3783 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_HJ(const I3C_TypeDef *I3Cx)
3784 {
3785 return ((READ_BIT(I3Cx->IER, I3C_IER_HJIE) == (I3C_IER_HJIE)) ? 1UL : 0UL);
3786 }
3787
3788 /**
3789 * @brief Enable Wake Up interrupt.
3790 * @rmtoll IER WKPIE LL_I3C_EnableIT_WKP
3791 * @param I3Cx I3C Instance.
3792 * @retval None
3793 */
LL_I3C_EnableIT_WKP(I3C_TypeDef * I3Cx)3794 __STATIC_INLINE void LL_I3C_EnableIT_WKP(I3C_TypeDef *I3Cx)
3795 {
3796 SET_BIT(I3Cx->IER, I3C_IER_WKPIE);
3797 }
3798
3799 /**
3800 * @brief Disable Wake Up interrupt.
3801 * @rmtoll IER WKPIE LL_I3C_DisableIT_WKP
3802 * @param I3Cx I3C Instance.
3803 * @retval None
3804 */
LL_I3C_DisableIT_WKP(I3C_TypeDef * I3Cx)3805 __STATIC_INLINE void LL_I3C_DisableIT_WKP(I3C_TypeDef *I3Cx)
3806 {
3807 CLEAR_BIT(I3Cx->IER, I3C_IER_WKPIE);
3808 }
3809
3810 /**
3811 * @brief Check if Wake Up is enabled or disabled.
3812 * @rmtoll IER WKPIE LL_I3C_IsEnabledIT_WKP
3813 * @param I3Cx I3C Instance.
3814 * @retval State of bit (1 or 0).
3815 */
LL_I3C_IsEnabledIT_WKP(const I3C_TypeDef * I3Cx)3816 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_WKP(const I3C_TypeDef *I3Cx)
3817 {
3818 return ((READ_BIT(I3Cx->IER, I3C_IER_WKPIE) == (I3C_IER_WKPIE)) ? 1UL : 0UL);
3819 }
3820
3821 /**
3822 * @brief Enable Get Command interrupt.
3823 * @rmtoll IER GETIE LL_I3C_EnableIT_GET
3824 * @param I3Cx I3C Instance.
3825 * @retval None
3826 */
LL_I3C_EnableIT_GET(I3C_TypeDef * I3Cx)3827 __STATIC_INLINE void LL_I3C_EnableIT_GET(I3C_TypeDef *I3Cx)
3828 {
3829 SET_BIT(I3Cx->IER, I3C_IER_GETIE);
3830 }
3831
3832 /**
3833 * @brief Disable Get Command interrupt.
3834 * @rmtoll IER GETIE LL_I3C_DisableIT_GET
3835 * @param I3Cx I3C Instance.
3836 * @retval None
3837 */
LL_I3C_DisableIT_GET(I3C_TypeDef * I3Cx)3838 __STATIC_INLINE void LL_I3C_DisableIT_GET(I3C_TypeDef *I3Cx)
3839 {
3840 CLEAR_BIT(I3Cx->IER, I3C_IER_GETIE);
3841 }
3842
3843 /**
3844 * @brief Check if Get Command is enabled or disabled.
3845 * @rmtoll IER GETIE LL_I3C_IsEnabledIT_GET
3846 * @param I3Cx I3C Instance.
3847 * @retval State of bit (1 or 0).
3848 */
LL_I3C_IsEnabledIT_GET(const I3C_TypeDef * I3Cx)3849 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_GET(const I3C_TypeDef *I3Cx)
3850 {
3851 return ((READ_BIT(I3Cx->IER, I3C_IER_GETIE) == (I3C_IER_GETIE)) ? 1UL : 0UL);
3852 }
3853
3854 /**
3855 * @brief Enable Get Status interrupt.
3856 * @rmtoll IER STAIE LL_I3C_EnableIT_STA
3857 * @param I3Cx I3C Instance.
3858 * @retval None
3859 */
LL_I3C_EnableIT_STA(I3C_TypeDef * I3Cx)3860 __STATIC_INLINE void LL_I3C_EnableIT_STA(I3C_TypeDef *I3Cx)
3861 {
3862 SET_BIT(I3Cx->IER, I3C_IER_STAIE);
3863 }
3864
3865 /**
3866 * @brief Disable Get Status interrupt.
3867 * @rmtoll IER STAIE LL_I3C_DisableIT_STA
3868 * @param I3Cx I3C Instance.
3869 * @retval None
3870 */
LL_I3C_DisableIT_STA(I3C_TypeDef * I3Cx)3871 __STATIC_INLINE void LL_I3C_DisableIT_STA(I3C_TypeDef *I3Cx)
3872 {
3873 CLEAR_BIT(I3Cx->IER, I3C_IER_STAIE);
3874 }
3875
3876 /**
3877 * @brief Check if Get Status interrupt is enabled or disabled.
3878 * @rmtoll IER STAIE LL_I3C_IsEnabledIT_STA
3879 * @param I3Cx I3C Instance.
3880 * @retval State of bit (1 or 0).
3881 */
LL_I3C_IsEnabledIT_STA(const I3C_TypeDef * I3Cx)3882 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_STA(const I3C_TypeDef *I3Cx)
3883 {
3884 return ((READ_BIT(I3Cx->IER, I3C_IER_STAIE) == (I3C_IER_STAIE)) ? 1UL : 0UL);
3885 }
3886
3887 /**
3888 * @brief Enable Dynamic Address Update interrupt.
3889 * @rmtoll IER DAUPDIE LL_I3C_EnableIT_DAUPD
3890 * @param I3Cx I3C Instance.
3891 * @retval None
3892 */
LL_I3C_EnableIT_DAUPD(I3C_TypeDef * I3Cx)3893 __STATIC_INLINE void LL_I3C_EnableIT_DAUPD(I3C_TypeDef *I3Cx)
3894 {
3895 SET_BIT(I3Cx->IER, I3C_IER_DAUPDIE);
3896 }
3897
3898 /**
3899 * @brief Disable Dynamic Address Update interrupt.
3900 * @rmtoll IER DAUPDIE LL_I3C_DisableIT_DAUPD
3901 * @param I3Cx I3C Instance.
3902 * @retval None
3903 */
LL_I3C_DisableIT_DAUPD(I3C_TypeDef * I3Cx)3904 __STATIC_INLINE void LL_I3C_DisableIT_DAUPD(I3C_TypeDef *I3Cx)
3905 {
3906 CLEAR_BIT(I3Cx->IER, I3C_IER_DAUPDIE);
3907 }
3908
3909 /**
3910 * @brief Check if Dynamic Address Update interrupt is enabled or disabled.
3911 * @rmtoll IER DAUPDIE LL_I3C_IsEnabledIT_DAUPD
3912 * @param I3Cx I3C Instance.
3913 * @retval State of bit (1 or 0).
3914 */
LL_I3C_IsEnabledIT_DAUPD(const I3C_TypeDef * I3Cx)3915 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_DAUPD(const I3C_TypeDef *I3Cx)
3916 {
3917 return ((READ_BIT(I3Cx->IER, I3C_IER_DAUPDIE) == (I3C_IER_DAUPDIE)) ? 1UL : 0UL);
3918 }
3919
3920 /**
3921 * @brief Enable Max Write Length Update interrupt.
3922 * @rmtoll IER MWLUPDIE LL_I3C_EnableIT_MWLUPD
3923 * @param I3Cx I3C Instance.
3924 * @retval None
3925 */
LL_I3C_EnableIT_MWLUPD(I3C_TypeDef * I3Cx)3926 __STATIC_INLINE void LL_I3C_EnableIT_MWLUPD(I3C_TypeDef *I3Cx)
3927 {
3928 SET_BIT(I3Cx->IER, I3C_IER_MWLUPDIE);
3929 }
3930
3931 /**
3932 * @brief Disable Max Write Length Update interrupt.
3933 * @rmtoll IER MWLUPDIE LL_I3C_DisableIT_MWLUPD
3934 * @param I3Cx I3C Instance.
3935 * @retval None
3936 */
LL_I3C_DisableIT_MWLUPD(I3C_TypeDef * I3Cx)3937 __STATIC_INLINE void LL_I3C_DisableIT_MWLUPD(I3C_TypeDef *I3Cx)
3938 {
3939 CLEAR_BIT(I3Cx->IER, I3C_IER_MWLUPDIE);
3940 }
3941
3942 /**
3943 * @brief Check if Max Write Length Update interrupt is enabled or disabled.
3944 * @rmtoll IER MWLUPDIE LL_I3C_IsEnabledIT_MWLUPD
3945 * @param I3Cx I3C Instance.
3946 * @retval State of bit (1 or 0).
3947 */
LL_I3C_IsEnabledIT_MWLUPD(const I3C_TypeDef * I3Cx)3948 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_MWLUPD(const I3C_TypeDef *I3Cx)
3949 {
3950 return ((READ_BIT(I3Cx->IER, I3C_IER_MWLUPDIE) == (I3C_IER_MWLUPDIE)) ? 1UL : 0UL);
3951 }
3952
3953 /**
3954 * @brief Enable Max Read Length Update interrupt.
3955 * @rmtoll IER MRLUPDIE LL_I3C_EnableIT_MRLUPD
3956 * @param I3Cx I3C Instance.
3957 * @retval None
3958 */
LL_I3C_EnableIT_MRLUPD(I3C_TypeDef * I3Cx)3959 __STATIC_INLINE void LL_I3C_EnableIT_MRLUPD(I3C_TypeDef *I3Cx)
3960 {
3961 SET_BIT(I3Cx->IER, I3C_IER_MRLUPDIE);
3962 }
3963
3964 /**
3965 * @brief Disable Max Read Length Update interrupt.
3966 * @rmtoll IER MRLUPDIE LL_I3C_DisableIT_MRLUPD
3967 * @param I3Cx I3C Instance.
3968 * @retval None
3969 */
LL_I3C_DisableIT_MRLUPD(I3C_TypeDef * I3Cx)3970 __STATIC_INLINE void LL_I3C_DisableIT_MRLUPD(I3C_TypeDef *I3Cx)
3971 {
3972 CLEAR_BIT(I3Cx->IER, I3C_IER_MRLUPDIE);
3973 }
3974
3975 /**
3976 * @brief Check if Max Read Length Update interrupt is enabled or disabled.
3977 * @rmtoll IER MRLUPDIE LL_I3C_IsEnabledIT_MRLUPD
3978 * @param I3Cx I3C Instance.
3979 * @retval State of bit (1 or 0).
3980 */
LL_I3C_IsEnabledIT_MRLUPD(const I3C_TypeDef * I3Cx)3981 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_MRLUPD(const I3C_TypeDef *I3Cx)
3982 {
3983 return ((READ_BIT(I3Cx->IER, I3C_IER_MRLUPDIE) == (I3C_IER_MRLUPDIE)) ? 1UL : 0UL);
3984 }
3985
3986 /**
3987 * @brief Enable Reset interrupt.
3988 * @rmtoll IER RSTIE LL_I3C_EnableIT_RST
3989 * @param I3Cx I3C Instance.
3990 * @retval None
3991 */
LL_I3C_EnableIT_RST(I3C_TypeDef * I3Cx)3992 __STATIC_INLINE void LL_I3C_EnableIT_RST(I3C_TypeDef *I3Cx)
3993 {
3994 SET_BIT(I3Cx->IER, I3C_IER_RSTIE);
3995 }
3996
3997 /**
3998 * @brief Disable Reset interrupt.
3999 * @rmtoll IER RSTIE LL_I3C_DisableIT_RST
4000 * @param I3Cx I3C Instance.
4001 * @retval None
4002 */
LL_I3C_DisableIT_RST(I3C_TypeDef * I3Cx)4003 __STATIC_INLINE void LL_I3C_DisableIT_RST(I3C_TypeDef *I3Cx)
4004 {
4005 CLEAR_BIT(I3Cx->IER, I3C_IER_RSTIE);
4006 }
4007
4008 /**
4009 * @brief Check if Reset interrupt is enabled or disabled.
4010 * @rmtoll IER RSTIE LL_I3C_IsEnabledIT_RST
4011 * @param I3Cx I3C Instance.
4012 * @retval State of bit (1 or 0).
4013 */
LL_I3C_IsEnabledIT_RST(const I3C_TypeDef * I3Cx)4014 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RST(const I3C_TypeDef *I3Cx)
4015 {
4016 return ((READ_BIT(I3Cx->IER, I3C_IER_RSTIE) == (I3C_IER_RSTIE)) ? 1UL : 0UL);
4017 }
4018
4019 /**
4020 * @brief Enable Activity State Update interrupt.
4021 * @rmtoll IER ASUPDIE LL_I3C_EnableIT_ASUPD
4022 * @param I3Cx I3C Instance.
4023 * @retval None
4024 */
LL_I3C_EnableIT_ASUPD(I3C_TypeDef * I3Cx)4025 __STATIC_INLINE void LL_I3C_EnableIT_ASUPD(I3C_TypeDef *I3Cx)
4026 {
4027 SET_BIT(I3Cx->IER, I3C_IER_ASUPDIE);
4028 }
4029
4030 /**
4031 * @brief Disable Activity State Update interrupt.
4032 * @rmtoll IER ASUPDIE LL_I3C_DisableIT_ASUPD
4033 * @param I3Cx I3C Instance.
4034 * @retval None
4035 */
LL_I3C_DisableIT_ASUPD(I3C_TypeDef * I3Cx)4036 __STATIC_INLINE void LL_I3C_DisableIT_ASUPD(I3C_TypeDef *I3Cx)
4037 {
4038 CLEAR_BIT(I3Cx->IER, I3C_IER_ASUPDIE);
4039 }
4040
4041 /**
4042 * @brief Check if Activity State Update interrupt is enabled or disabled.
4043 * @rmtoll IER ASUPDIE LL_I3C_IsEnabledIT_ASUPD
4044 * @param I3Cx I3C Instance.
4045 * @retval State of bit (1 or 0).
4046 */
LL_I3C_IsEnabledIT_ASUPD(const I3C_TypeDef * I3Cx)4047 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_ASUPD(const I3C_TypeDef *I3Cx)
4048 {
4049 return ((READ_BIT(I3Cx->IER, I3C_IER_ASUPDIE) == (I3C_IER_ASUPDIE)) ? 1UL : 0UL);
4050 }
4051
4052 /**
4053 * @brief Enable Interrupt Update interrupt.
4054 * @rmtoll IER INTUPDIE LL_I3C_EnableIT_INTUPD
4055 * @param I3Cx I3C Instance.
4056 * @retval None
4057 */
LL_I3C_EnableIT_INTUPD(I3C_TypeDef * I3Cx)4058 __STATIC_INLINE void LL_I3C_EnableIT_INTUPD(I3C_TypeDef *I3Cx)
4059 {
4060 SET_BIT(I3Cx->IER, I3C_IER_INTUPDIE);
4061 }
4062
4063 /**
4064 * @brief Disable Interrupt Update interrupt.
4065 * @rmtoll IER INTUPDIE LL_I3C_DisableIT_INTUPD
4066 * @param I3Cx I3C Instance.
4067 * @retval None
4068 */
LL_I3C_DisableIT_INTUPD(I3C_TypeDef * I3Cx)4069 __STATIC_INLINE void LL_I3C_DisableIT_INTUPD(I3C_TypeDef *I3Cx)
4070 {
4071 CLEAR_BIT(I3Cx->IER, I3C_IER_INTUPDIE);
4072 }
4073
4074 /**
4075 * @brief Check if Interrupt Update interrupt is enabled or disabled.
4076 * @rmtoll IER INTUPDIE LL_I3C_IsEnabledIT_INTUPD
4077 * @param I3Cx I3C Instance.
4078 * @retval State of bit (1 or 0).
4079 */
LL_I3C_IsEnabledIT_INTUPD(const I3C_TypeDef * I3Cx)4080 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_INTUPD(const I3C_TypeDef *I3Cx)
4081 {
4082 return ((READ_BIT(I3Cx->IER, I3C_IER_INTUPDIE) == (I3C_IER_INTUPDIE)) ? 1UL : 0UL);
4083 }
4084
4085 /**
4086 * @brief Enable Define List Target interrupt.
4087 * @rmtoll IER DEFIE LL_I3C_EnableIT_DEF
4088 * @param I3Cx I3C Instance.
4089 * @retval None
4090 */
LL_I3C_EnableIT_DEF(I3C_TypeDef * I3Cx)4091 __STATIC_INLINE void LL_I3C_EnableIT_DEF(I3C_TypeDef *I3Cx)
4092 {
4093 SET_BIT(I3Cx->IER, I3C_IER_DEFIE);
4094 }
4095
4096 /**
4097 * @brief Disable Define List Target interrupt.
4098 * @rmtoll IER DEFIE LL_I3C_DisableIT_DEF
4099 * @param I3Cx I3C Instance.
4100 * @retval None
4101 */
LL_I3C_DisableIT_DEF(I3C_TypeDef * I3Cx)4102 __STATIC_INLINE void LL_I3C_DisableIT_DEF(I3C_TypeDef *I3Cx)
4103 {
4104 CLEAR_BIT(I3Cx->IER, I3C_IER_DEFIE);
4105 }
4106
4107 /**
4108 * @brief Check if Define List Target interrupt is enabled or disabled.
4109 * @rmtoll IER DEFIE LL_I3C_IsEnabledIT_DEF
4110 * @param I3Cx I3C Instance.
4111 * @retval State of bit (1 or 0).
4112 */
LL_I3C_IsEnabledIT_DEF(const I3C_TypeDef * I3Cx)4113 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_DEF(const I3C_TypeDef *I3Cx)
4114 {
4115 return ((READ_BIT(I3Cx->IER, I3C_IER_DEFIE) == (I3C_IER_DEFIE)) ? 1UL : 0UL);
4116 }
4117
4118 /**
4119 * @brief Enable Define List Group Addresses interrupt.
4120 * @rmtoll IER GRPIE LL_I3C_EnableIT_GRP
4121 * @param I3Cx I3C Instance.
4122 * @retval None
4123 */
LL_I3C_EnableIT_GRP(I3C_TypeDef * I3Cx)4124 __STATIC_INLINE void LL_I3C_EnableIT_GRP(I3C_TypeDef *I3Cx)
4125 {
4126 SET_BIT(I3Cx->IER, I3C_IER_GRPIE);
4127 }
4128
4129 /**
4130 * @brief Disable Define List Group Addresses interrupt.
4131 * @rmtoll IER GRPIE LL_I3C_DisableIT_GRP
4132 * @param I3Cx I3C Instance.
4133 * @retval None
4134 */
LL_I3C_DisableIT_GRP(I3C_TypeDef * I3Cx)4135 __STATIC_INLINE void LL_I3C_DisableIT_GRP(I3C_TypeDef *I3Cx)
4136 {
4137 CLEAR_BIT(I3Cx->IER, I3C_IER_GRPIE);
4138 }
4139
4140 /**
4141 * @brief Check if Define List Group Addresses interrupt is enabled or disabled.
4142 * @rmtoll IER GRPIE LL_I3C_IsEnabledIT_GRP
4143 * @param I3Cx I3C Instance.
4144 * @retval State of bit (1 or 0).
4145 */
LL_I3C_IsEnabledIT_GRP(const I3C_TypeDef * I3Cx)4146 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_GRP(const I3C_TypeDef *I3Cx)
4147 {
4148 return ((READ_BIT(I3Cx->IER, I3C_IER_GRPIE) == (I3C_IER_GRPIE)) ? 1UL : 0UL);
4149 }
4150
4151 /**
4152 * @}
4153 */
4154
4155 /** @addtogroup I3C_LL_EF_FLAG_management FLAG_management
4156 * @{
4157 */
4158
4159 /**
4160 * @brief Clear Frame Complete flag (controller and target mode).
4161 * @rmtoll CEVR CFCF LL_I3C_ClearFlag_FC
4162 * @param I3Cx I3C Instance.
4163 * @retval None
4164 */
LL_I3C_ClearFlag_FC(I3C_TypeDef * I3Cx)4165 __STATIC_INLINE void LL_I3C_ClearFlag_FC(I3C_TypeDef *I3Cx)
4166 {
4167 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CFCF);
4168 }
4169
4170 /**
4171 * @brief Clear Reception Target End flag (controller mode).
4172 * @rmtoll CEVR CRXTGTENDF LL_I3C_ClearFlag_RXTGTEND
4173 * @param I3Cx I3C Instance.
4174 * @retval None
4175 */
LL_I3C_ClearFlag_RXTGTEND(I3C_TypeDef * I3Cx)4176 __STATIC_INLINE void LL_I3C_ClearFlag_RXTGTEND(I3C_TypeDef *I3Cx)
4177 {
4178 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CRXTGTENDF);
4179 }
4180
4181 /**
4182 * @brief Clear Error flag (controller and target mode).
4183 * @rmtoll CEVR CERRF LL_I3C_ClearFlag_ERR
4184 * @param I3Cx I3C Instance.
4185 * @retval None
4186 */
LL_I3C_ClearFlag_ERR(I3C_TypeDef * I3Cx)4187 __STATIC_INLINE void LL_I3C_ClearFlag_ERR(I3C_TypeDef *I3Cx)
4188 {
4189 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CERRF);
4190 }
4191
4192 /**
4193 * @brief Clear IBI flag (controller mode).
4194 * @rmtoll CEVR CIBIF LL_I3C_ClearFlag_IBI
4195 * @param I3Cx I3C Instance.
4196 * @retval None
4197 */
LL_I3C_ClearFlag_IBI(I3C_TypeDef * I3Cx)4198 __STATIC_INLINE void LL_I3C_ClearFlag_IBI(I3C_TypeDef *I3Cx)
4199 {
4200 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CIBIF);
4201 }
4202
4203 /**
4204 * @brief Clear IBI End flag (target mode).
4205 * @rmtoll CEVR CIBIENDF LL_I3C_ClearFlag_IBIEND
4206 * @param I3Cx I3C Instance.
4207 * @retval None
4208 */
LL_I3C_ClearFlag_IBIEND(I3C_TypeDef * I3Cx)4209 __STATIC_INLINE void LL_I3C_ClearFlag_IBIEND(I3C_TypeDef *I3Cx)
4210 {
4211 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CIBIENDF);
4212 }
4213
4214 /**
4215 * @brief Clear Controller-role Request flag (controller mode).
4216 * @rmtoll CEVR CCRF LL_I3C_ClearFlag_CR
4217 * @param I3Cx I3C Instance.
4218 * @retval None
4219 */
LL_I3C_ClearFlag_CR(I3C_TypeDef * I3Cx)4220 __STATIC_INLINE void LL_I3C_ClearFlag_CR(I3C_TypeDef *I3Cx)
4221 {
4222 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CCRF);
4223 }
4224
4225 /**
4226 * @brief Clear Controller-role Request Update flag (target mode).
4227 * @rmtoll CEVR CCRUPDF LL_I3C_ClearFlag_CRUPD
4228 * @param I3Cx I3C Instance.
4229 * @retval None
4230 */
LL_I3C_ClearFlag_CRUPD(I3C_TypeDef * I3Cx)4231 __STATIC_INLINE void LL_I3C_ClearFlag_CRUPD(I3C_TypeDef *I3Cx)
4232 {
4233 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CCRUPDF);
4234 }
4235
4236 /**
4237 * @brief Clear Hot Join flag (controller mode).
4238 * @rmtoll CEVR CHJF LL_I3C_ClearFlag_HJ
4239 * @param I3Cx I3C Instance.
4240 * @retval None
4241 */
LL_I3C_ClearFlag_HJ(I3C_TypeDef * I3Cx)4242 __STATIC_INLINE void LL_I3C_ClearFlag_HJ(I3C_TypeDef *I3Cx)
4243 {
4244 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CHJF);
4245 }
4246
4247 /**
4248 * @brief Clear Wake Up flag (target mode).
4249 * @rmtoll CEVR CWKPF LL_I3C_ClearFlag_WKP
4250 * @param I3Cx I3C Instance.
4251 * @retval None
4252 */
LL_I3C_ClearFlag_WKP(I3C_TypeDef * I3Cx)4253 __STATIC_INLINE void LL_I3C_ClearFlag_WKP(I3C_TypeDef *I3Cx)
4254 {
4255 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CWKPF);
4256 }
4257
4258 /**
4259 * @brief Clear Get flag (target mode).
4260 * @rmtoll CEVR CGETF LL_I3C_ClearFlag_GET
4261 * @param I3Cx I3C Instance.
4262 * @retval None
4263 */
LL_I3C_ClearFlag_GET(I3C_TypeDef * I3Cx)4264 __STATIC_INLINE void LL_I3C_ClearFlag_GET(I3C_TypeDef *I3Cx)
4265 {
4266 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CGETF);
4267 }
4268
4269 /**
4270 * @brief Clear Get Status flag (target mode).
4271 * @rmtoll CEVR CSTAF LL_I3C_ClearFlag_STA
4272 * @param I3Cx I3C Instance.
4273 * @retval None
4274 */
LL_I3C_ClearFlag_STA(I3C_TypeDef * I3Cx)4275 __STATIC_INLINE void LL_I3C_ClearFlag_STA(I3C_TypeDef *I3Cx)
4276 {
4277 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CSTAF);
4278 }
4279
4280 /**
4281 * @brief Clear Dynamic Address Update flag (target mode).
4282 * @rmtoll CEVR CDAUPDF LL_I3C_ClearFlag_DAUPD
4283 * @param I3Cx I3C Instance.
4284 * @retval None
4285 */
LL_I3C_ClearFlag_DAUPD(I3C_TypeDef * I3Cx)4286 __STATIC_INLINE void LL_I3C_ClearFlag_DAUPD(I3C_TypeDef *I3Cx)
4287 {
4288 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CDAUPDF);
4289 }
4290
4291 /**
4292 * @brief Clear Max Write Length flag (target mode).
4293 * @rmtoll CEVR CMWLUPDF LL_I3C_ClearFlag_MWLUPD
4294 * @param I3Cx I3C Instance.
4295 * @retval None
4296 */
LL_I3C_ClearFlag_MWLUPD(I3C_TypeDef * I3Cx)4297 __STATIC_INLINE void LL_I3C_ClearFlag_MWLUPD(I3C_TypeDef *I3Cx)
4298 {
4299 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CMWLUPDF);
4300 }
4301
4302 /**
4303 * @brief Clear Max Read Length flag (target mode).
4304 * @rmtoll CEVR CMRLUPDF LL_I3C_ClearFlag_MRLUPD
4305 * @param I3Cx I3C Instance.
4306 * @retval None
4307 */
LL_I3C_ClearFlag_MRLUPD(I3C_TypeDef * I3Cx)4308 __STATIC_INLINE void LL_I3C_ClearFlag_MRLUPD(I3C_TypeDef *I3Cx)
4309 {
4310 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CMRLUPDF);
4311 }
4312
4313 /**
4314 * @brief Clear Reset flag (target mode).
4315 * @rmtoll CEVR CRSTF LL_I3C_ClearFlag_RST
4316 * @param I3Cx I3C Instance.
4317 * @retval None
4318 */
LL_I3C_ClearFlag_RST(I3C_TypeDef * I3Cx)4319 __STATIC_INLINE void LL_I3C_ClearFlag_RST(I3C_TypeDef *I3Cx)
4320 {
4321 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CRSTF);
4322 }
4323
4324 /**
4325 * @brief Clear Active State flag (target mode).
4326 * @rmtoll CEVR CASUPDF LL_I3C_ClearFlag_ASUPD
4327 * @param I3Cx I3C Instance.
4328 * @retval None
4329 */
LL_I3C_ClearFlag_ASUPD(I3C_TypeDef * I3Cx)4330 __STATIC_INLINE void LL_I3C_ClearFlag_ASUPD(I3C_TypeDef *I3Cx)
4331 {
4332 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CASUPDF);
4333 }
4334
4335 /**
4336 * @brief Clear Interrupt Update flag (target mode).
4337 * @rmtoll CEVR CINTUPDF LL_I3C_ClearFlag_INTUPD
4338 * @param I3Cx I3C Instance.
4339 * @retval None
4340 */
LL_I3C_ClearFlag_INTUPD(I3C_TypeDef * I3Cx)4341 __STATIC_INLINE void LL_I3C_ClearFlag_INTUPD(I3C_TypeDef *I3Cx)
4342 {
4343 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CINTUPDF);
4344 }
4345
4346 /**
4347 * @brief Clear Define List Targets flag (target mode).
4348 * @rmtoll CEVR CDEFF LL_I3C_ClearFlag_DEF
4349 * @param I3Cx I3C Instance.
4350 * @retval None
4351 */
LL_I3C_ClearFlag_DEF(I3C_TypeDef * I3Cx)4352 __STATIC_INLINE void LL_I3C_ClearFlag_DEF(I3C_TypeDef *I3Cx)
4353 {
4354 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CDEFF);
4355 }
4356
4357 /**
4358 * @brief Clear Define List Group Addresses flag.
4359 * @rmtoll CEVR CGRPF LL_I3C_ClearFlag_GRP
4360 * @param I3Cx I3C Instance.
4361 * @retval None
4362 */
LL_I3C_ClearFlag_GRP(I3C_TypeDef * I3Cx)4363 __STATIC_INLINE void LL_I3C_ClearFlag_GRP(I3C_TypeDef *I3Cx)
4364 {
4365 WRITE_REG(I3Cx->CEVR, I3C_CEVR_CGRPF);
4366 }
4367
4368 /**
4369 * @}
4370 */
4371
4372 #if defined(USE_FULL_LL_DRIVER)
4373 /** @defgroup I3C_LL_EF_Init Initialization and de-initialization functions
4374 * @{
4375 */
4376
4377 ErrorStatus LL_I3C_Init(I3C_TypeDef *I3Cx, LL_I3C_InitTypeDef *I3C_InitStruct, uint32_t Mode);
4378 ErrorStatus LL_I3C_DeInit(I3C_TypeDef *I3Cx);
4379 void LL_I3C_StructInit(LL_I3C_InitTypeDef *I3C_InitStruct);
4380
4381 /**
4382 * @}
4383 */
4384 #endif /* USE_FULL_LL_DRIVER */
4385
4386 /**
4387 * @}
4388 */
4389
4390 /**
4391 * @}
4392 */
4393
4394 #endif /* I3C1 */
4395
4396 /**
4397 * @}
4398 */
4399
4400 #ifdef __cplusplus
4401 }
4402 #endif
4403
4404 #endif /* __STM32H5xx_LL_I3C_H */
4405
