1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_gpio.h
4 * @author MCD Application Team
5 * @brief Header file of GPIO LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F1xx_LL_GPIO_H
21 #define STM32F1xx_LL_GPIO_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f1xx.h"
29
30 /** @addtogroup STM32F1xx_LL_Driver
31 * @{
32 */
33
34 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
35
36 /** @defgroup GPIO_LL GPIO
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43
44 /** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
45 * @{
46 */
47 /* Defines used for Pin Mask Initialization */
48 #define GPIO_PIN_MASK_POS 8U
49 #define GPIO_PIN_NB 16U
50 /**
51 * @}
52 */
53
54 /* Private macros ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
57 * @{
58 */
59
60 /**
61 * @}
62 */
63 #endif /*USE_FULL_LL_DRIVER*/
64
65 /* Exported types ------------------------------------------------------------*/
66 #if defined(USE_FULL_LL_DRIVER)
67 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
68 * @{
69 */
70
71 /**
72 * @brief LL GPIO Init Structure definition
73 */
74 typedef struct
75 {
76 uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
77 This parameter can be any value of @ref GPIO_LL_EC_PIN */
78
79 uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
80 This parameter can be a value of @ref GPIO_LL_EC_MODE.
81
82 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
83
84 uint32_t Speed; /*!< Specifies the speed for the selected pins.
85 This parameter can be a value of @ref GPIO_LL_EC_SPEED.
86
87 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
88
89 uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
90 This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
91
92 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
93
94 uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
95 This parameter can be a value of @ref GPIO_LL_EC_PULL.
96
97 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
98 } LL_GPIO_InitTypeDef;
99
100 /**
101 * @}
102 */
103 #endif /* USE_FULL_LL_DRIVER */
104
105 /* Exported constants --------------------------------------------------------*/
106 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
107 * @{
108 */
109
110 /** @defgroup GPIO_LL_EC_PIN PIN
111 * @{
112 */
113 #define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) | 0x00000001U) /*!< Select pin 0 */
114 #define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) | 0x00000002U) /*!< Select pin 1 */
115 #define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) | 0x00000004U) /*!< Select pin 2 */
116 #define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) | 0x00000008U) /*!< Select pin 3 */
117 #define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) | 0x00000010U) /*!< Select pin 4 */
118 #define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) | 0x00000020U) /*!< Select pin 5 */
119 #define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) | 0x00000040U) /*!< Select pin 6 */
120 #define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) | 0x00000080U) /*!< Select pin 7 */
121 #define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) | 0x04000001U) /*!< Select pin 8 */
122 #define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) | 0x04000002U) /*!< Select pin 9 */
123 #define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) | 0x04000004U) /*!< Select pin 10 */
124 #define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) | 0x04000008U) /*!< Select pin 11 */
125 #define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) | 0x04000010U) /*!< Select pin 12 */
126 #define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) | 0x04000020U) /*!< Select pin 13 */
127 #define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) | 0x04000040U) /*!< Select pin 14 */
128 #define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) | 0x04000080U) /*!< Select pin 15 */
129 #define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \
130 LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \
131 LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \
132 LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \
133 LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \
134 LL_GPIO_PIN_15) /*!< Select all pins */
135 /**
136 * @}
137 */
138
139 /** @defgroup GPIO_LL_EC_MODE Mode
140 * @{
141 */
142 #define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */
143 #define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */
144 #define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */
145 #define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */
146 #define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */
147 /**
148 * @}
149 */
150
151 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
152 * @{
153 */
154 #define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */
155 #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */
156 /**
157 * @}
158 */
159
160 /** @defgroup GPIO_LL_EC_SPEED Output Speed
161 * @{
162 */
163 #define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */
164 #define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */
165 #define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */
166 /**
167 * @}
168 */
169
170 #define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */
171 #define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */
172 #define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */
173
174 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
175 * @{
176 */
177 #define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */
178 #define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */
179
180 /**
181 * @}
182 */
183
184 /** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
185 * @{
186 */
187
188 #define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
189 #define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
190 #define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
191 #define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
192 #define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
193 #define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
194 #define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
195 #define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
196 #define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
197 #define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
198 #define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
199 #define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
200 #define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
201 #define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
202 #define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
203 #define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
204
205 /**
206 * @}
207 */
208
209 /** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
210 * @{
211 */
212
213 #define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
214 #define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
215 #define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
216 #define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
217 #define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
218
219 /**
220 * @}
221 */
222
223 /** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
224 * @{
225 */
226 #define LL_GPIO_AF_EXTI_PORTA 0U /*!< EXTI PORT A */
227 #define LL_GPIO_AF_EXTI_PORTB 1U /*!< EXTI PORT B */
228 #define LL_GPIO_AF_EXTI_PORTC 2U /*!< EXTI PORT C */
229 #define LL_GPIO_AF_EXTI_PORTD 3U /*!< EXTI PORT D */
230 #define LL_GPIO_AF_EXTI_PORTE 4U /*!< EXTI PORT E */
231 #define LL_GPIO_AF_EXTI_PORTF 5U /*!< EXTI PORT F */
232 #define LL_GPIO_AF_EXTI_PORTG 6U /*!< EXTI PORT G */
233 /**
234 * @}
235 */
236
237 /** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
238 * @{
239 */
240 #define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
241 #define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
242 #define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
243 #define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
244 #define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
245 #define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
246 #define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
247 #define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
248 #define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
249 #define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
250 #define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
251 #define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
252 #define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
253 #define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
254 #define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
255 #define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
256 /**
257 * @}
258 */
259
260 /**
261 * @}
262 */
263
264 /* Exported macro ------------------------------------------------------------*/
265 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
266 * @{
267 */
268
269 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
270 * @{
271 */
272
273 /**
274 * @brief Write a value in GPIO register
275 * @param __INSTANCE__ GPIO Instance
276 * @param __REG__ Register to be written
277 * @param __VALUE__ Value to be written in the register
278 * @retval None
279 */
280 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
281
282 /**
283 * @brief Read a value in GPIO register
284 * @param __INSTANCE__ GPIO Instance
285 * @param __REG__ Register to be read
286 * @retval Register value
287 */
288 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
289 /**
290 * @}
291 */
292
293 /**
294 * @}
295 */
296
297 /* Exported functions --------------------------------------------------------*/
298 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
299 * @{
300 */
301
302 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
303 * @{
304 */
305
306 /**
307 * @brief Configure gpio mode for a dedicated pin on dedicated port.
308 * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
309 * Alternate function Output.
310 * @note Warning: only one pin can be passed as parameter.
311 * @rmtoll CRL CNFy LL_GPIO_SetPinMode
312 * @rmtoll CRL MODEy LL_GPIO_SetPinMode
313 * @rmtoll CRH CNFy LL_GPIO_SetPinMode
314 * @rmtoll CRH MODEy LL_GPIO_SetPinMode
315 * @param GPIOx GPIO Port
316 * @param Pin This parameter can be one of the following values:
317 * @arg @ref LL_GPIO_PIN_0
318 * @arg @ref LL_GPIO_PIN_1
319 * @arg @ref LL_GPIO_PIN_2
320 * @arg @ref LL_GPIO_PIN_3
321 * @arg @ref LL_GPIO_PIN_4
322 * @arg @ref LL_GPIO_PIN_5
323 * @arg @ref LL_GPIO_PIN_6
324 * @arg @ref LL_GPIO_PIN_7
325 * @arg @ref LL_GPIO_PIN_8
326 * @arg @ref LL_GPIO_PIN_9
327 * @arg @ref LL_GPIO_PIN_10
328 * @arg @ref LL_GPIO_PIN_11
329 * @arg @ref LL_GPIO_PIN_12
330 * @arg @ref LL_GPIO_PIN_13
331 * @arg @ref LL_GPIO_PIN_14
332 * @arg @ref LL_GPIO_PIN_15
333 * @param Mode This parameter can be one of the following values:
334 * @arg @ref LL_GPIO_MODE_ANALOG
335 * @arg @ref LL_GPIO_MODE_FLOATING
336 * @arg @ref LL_GPIO_MODE_INPUT
337 * @arg @ref LL_GPIO_MODE_OUTPUT
338 * @arg @ref LL_GPIO_MODE_ALTERNATE
339 * @retval None
340 */
LL_GPIO_SetPinMode(GPIO_TypeDef * GPIOx,uint32_t Pin,uint32_t Mode)341 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
342 {
343 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
344 MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
345 }
346
347 /**
348 * @brief Return gpio mode for a dedicated pin on dedicated port.
349 * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
350 * Alternate function Output.
351 * @note Warning: only one pin can be passed as parameter.
352 * @rmtoll CRL CNFy LL_GPIO_GetPinMode
353 * @rmtoll CRL MODEy LL_GPIO_GetPinMode
354 * @rmtoll CRH CNFy LL_GPIO_GetPinMode
355 * @rmtoll CRH MODEy LL_GPIO_GetPinMode
356 * @param GPIOx GPIO Port
357 * @param Pin This parameter can be one of the following values:
358 * @arg @ref LL_GPIO_PIN_0
359 * @arg @ref LL_GPIO_PIN_1
360 * @arg @ref LL_GPIO_PIN_2
361 * @arg @ref LL_GPIO_PIN_3
362 * @arg @ref LL_GPIO_PIN_4
363 * @arg @ref LL_GPIO_PIN_5
364 * @arg @ref LL_GPIO_PIN_6
365 * @arg @ref LL_GPIO_PIN_7
366 * @arg @ref LL_GPIO_PIN_8
367 * @arg @ref LL_GPIO_PIN_9
368 * @arg @ref LL_GPIO_PIN_10
369 * @arg @ref LL_GPIO_PIN_11
370 * @arg @ref LL_GPIO_PIN_12
371 * @arg @ref LL_GPIO_PIN_13
372 * @arg @ref LL_GPIO_PIN_14
373 * @arg @ref LL_GPIO_PIN_15
374 * @retval Returned value can be one of the following values:
375 * @arg @ref LL_GPIO_MODE_ANALOG
376 * @arg @ref LL_GPIO_MODE_FLOATING
377 * @arg @ref LL_GPIO_MODE_INPUT
378 * @arg @ref LL_GPIO_MODE_OUTPUT
379 * @arg @ref LL_GPIO_MODE_ALTERNATE
380 */
LL_GPIO_GetPinMode(GPIO_TypeDef * GPIOx,uint32_t Pin)381 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
382 {
383 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
384 return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
385 }
386
387 /**
388 * @brief Configure gpio speed for a dedicated pin on dedicated port.
389 * @note I/O speed can be Low, Medium or Fast speed.
390 * @note Warning: only one pin can be passed as parameter.
391 * @note Refer to datasheet for frequency specifications and the power
392 * supply and load conditions for each speed.
393 * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed
394 * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed
395 * @param GPIOx GPIO Port
396 * @param Pin This parameter can be one of the following values:
397 * @arg @ref LL_GPIO_PIN_0
398 * @arg @ref LL_GPIO_PIN_1
399 * @arg @ref LL_GPIO_PIN_2
400 * @arg @ref LL_GPIO_PIN_3
401 * @arg @ref LL_GPIO_PIN_4
402 * @arg @ref LL_GPIO_PIN_5
403 * @arg @ref LL_GPIO_PIN_6
404 * @arg @ref LL_GPIO_PIN_7
405 * @arg @ref LL_GPIO_PIN_8
406 * @arg @ref LL_GPIO_PIN_9
407 * @arg @ref LL_GPIO_PIN_10
408 * @arg @ref LL_GPIO_PIN_11
409 * @arg @ref LL_GPIO_PIN_12
410 * @arg @ref LL_GPIO_PIN_13
411 * @arg @ref LL_GPIO_PIN_14
412 * @arg @ref LL_GPIO_PIN_15
413 * @param Speed This parameter can be one of the following values:
414 * @arg @ref LL_GPIO_SPEED_FREQ_LOW
415 * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
416 * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
417 * @retval None
418 */
LL_GPIO_SetPinSpeed(GPIO_TypeDef * GPIOx,uint32_t Pin,uint32_t Speed)419 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
420 {
421 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
422 MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
423 (Speed << (POSITION_VAL(Pin) * 4U)));
424 }
425
426 /**
427 * @brief Return gpio speed for a dedicated pin on dedicated port.
428 * @note I/O speed can be Low, Medium, Fast or High speed.
429 * @note Warning: only one pin can be passed as parameter.
430 * @note Refer to datasheet for frequency specifications and the power
431 * supply and load conditions for each speed.
432 * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed
433 * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed
434 * @param GPIOx GPIO Port
435 * @param Pin This parameter can be one of the following values:
436 * @arg @ref LL_GPIO_PIN_0
437 * @arg @ref LL_GPIO_PIN_1
438 * @arg @ref LL_GPIO_PIN_2
439 * @arg @ref LL_GPIO_PIN_3
440 * @arg @ref LL_GPIO_PIN_4
441 * @arg @ref LL_GPIO_PIN_5
442 * @arg @ref LL_GPIO_PIN_6
443 * @arg @ref LL_GPIO_PIN_7
444 * @arg @ref LL_GPIO_PIN_8
445 * @arg @ref LL_GPIO_PIN_9
446 * @arg @ref LL_GPIO_PIN_10
447 * @arg @ref LL_GPIO_PIN_11
448 * @arg @ref LL_GPIO_PIN_12
449 * @arg @ref LL_GPIO_PIN_13
450 * @arg @ref LL_GPIO_PIN_14
451 * @arg @ref LL_GPIO_PIN_15
452 * @retval Returned value can be one of the following values:
453 * @arg @ref LL_GPIO_SPEED_FREQ_LOW
454 * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
455 * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
456 */
LL_GPIO_GetPinSpeed(GPIO_TypeDef * GPIOx,uint32_t Pin)457 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
458 {
459 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
460 return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
461 }
462
463 /**
464 * @brief Configure gpio output type for several pins on dedicated port.
465 * @note Output type as to be set when gpio pin is in output or
466 * alternate modes. Possible type are Push-pull or Open-drain.
467 * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType
468 * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType
469 * @param GPIOx GPIO Port
470 * @param Pin This parameter can be a combination of the following values:
471 * @arg @ref LL_GPIO_PIN_0
472 * @arg @ref LL_GPIO_PIN_1
473 * @arg @ref LL_GPIO_PIN_2
474 * @arg @ref LL_GPIO_PIN_3
475 * @arg @ref LL_GPIO_PIN_4
476 * @arg @ref LL_GPIO_PIN_5
477 * @arg @ref LL_GPIO_PIN_6
478 * @arg @ref LL_GPIO_PIN_7
479 * @arg @ref LL_GPIO_PIN_8
480 * @arg @ref LL_GPIO_PIN_9
481 * @arg @ref LL_GPIO_PIN_10
482 * @arg @ref LL_GPIO_PIN_11
483 * @arg @ref LL_GPIO_PIN_12
484 * @arg @ref LL_GPIO_PIN_13
485 * @arg @ref LL_GPIO_PIN_14
486 * @arg @ref LL_GPIO_PIN_15
487 * @arg @ref LL_GPIO_PIN_ALL
488 * @param OutputType This parameter can be one of the following values:
489 * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
490 * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
491 * @retval None
492 */
LL_GPIO_SetPinOutputType(GPIO_TypeDef * GPIOx,uint32_t Pin,uint32_t OutputType)493 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
494 {
495 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
496 MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
497 (OutputType << (POSITION_VAL(Pin) * 4U)));
498 }
499
500 /**
501 * @brief Return gpio output type for several pins on dedicated port.
502 * @note Output type as to be set when gpio pin is in output or
503 * alternate modes. Possible type are Push-pull or Open-drain.
504 * @note Warning: only one pin can be passed as parameter.
505 * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType
506 * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType
507 * @param GPIOx GPIO Port
508 * @param Pin This parameter can be one of the following values:
509 * @arg @ref LL_GPIO_PIN_0
510 * @arg @ref LL_GPIO_PIN_1
511 * @arg @ref LL_GPIO_PIN_2
512 * @arg @ref LL_GPIO_PIN_3
513 * @arg @ref LL_GPIO_PIN_4
514 * @arg @ref LL_GPIO_PIN_5
515 * @arg @ref LL_GPIO_PIN_6
516 * @arg @ref LL_GPIO_PIN_7
517 * @arg @ref LL_GPIO_PIN_8
518 * @arg @ref LL_GPIO_PIN_9
519 * @arg @ref LL_GPIO_PIN_10
520 * @arg @ref LL_GPIO_PIN_11
521 * @arg @ref LL_GPIO_PIN_12
522 * @arg @ref LL_GPIO_PIN_13
523 * @arg @ref LL_GPIO_PIN_14
524 * @arg @ref LL_GPIO_PIN_15
525 * @arg @ref LL_GPIO_PIN_ALL
526 * @retval Returned value can be one of the following values:
527 * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
528 * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
529 */
LL_GPIO_GetPinOutputType(GPIO_TypeDef * GPIOx,uint32_t Pin)530 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
531 {
532 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
533 return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
534
535 }
536
537 /**
538 * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
539 * @note Warning: only one pin can be passed as parameter.
540 * @rmtoll ODR ODR LL_GPIO_SetPinPull
541 * @param GPIOx GPIO Port
542 * @param Pin This parameter can be one of the following values:
543 * @arg @ref LL_GPIO_PIN_0
544 * @arg @ref LL_GPIO_PIN_1
545 * @arg @ref LL_GPIO_PIN_2
546 * @arg @ref LL_GPIO_PIN_3
547 * @arg @ref LL_GPIO_PIN_4
548 * @arg @ref LL_GPIO_PIN_5
549 * @arg @ref LL_GPIO_PIN_6
550 * @arg @ref LL_GPIO_PIN_7
551 * @arg @ref LL_GPIO_PIN_8
552 * @arg @ref LL_GPIO_PIN_9
553 * @arg @ref LL_GPIO_PIN_10
554 * @arg @ref LL_GPIO_PIN_11
555 * @arg @ref LL_GPIO_PIN_12
556 * @arg @ref LL_GPIO_PIN_13
557 * @arg @ref LL_GPIO_PIN_14
558 * @arg @ref LL_GPIO_PIN_15
559 * @param Pull This parameter can be one of the following values:
560 * @arg @ref LL_GPIO_PULL_DOWN
561 * @arg @ref LL_GPIO_PULL_UP
562 * @retval None
563 */
LL_GPIO_SetPinPull(GPIO_TypeDef * GPIOx,uint32_t Pin,uint32_t Pull)564 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
565 {
566 MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
567 }
568
569 /**
570 * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
571 * @note Warning: only one pin can be passed as parameter.
572 * @rmtoll ODR ODR LL_GPIO_GetPinPull
573 * @param GPIOx GPIO Port
574 * @param Pin This parameter can be one of the following values:
575 * @arg @ref LL_GPIO_PIN_0
576 * @arg @ref LL_GPIO_PIN_1
577 * @arg @ref LL_GPIO_PIN_2
578 * @arg @ref LL_GPIO_PIN_3
579 * @arg @ref LL_GPIO_PIN_4
580 * @arg @ref LL_GPIO_PIN_5
581 * @arg @ref LL_GPIO_PIN_6
582 * @arg @ref LL_GPIO_PIN_7
583 * @arg @ref LL_GPIO_PIN_8
584 * @arg @ref LL_GPIO_PIN_9
585 * @arg @ref LL_GPIO_PIN_10
586 * @arg @ref LL_GPIO_PIN_11
587 * @arg @ref LL_GPIO_PIN_12
588 * @arg @ref LL_GPIO_PIN_13
589 * @arg @ref LL_GPIO_PIN_14
590 * @arg @ref LL_GPIO_PIN_15
591 * @retval Returned value can be one of the following values:
592 * @arg @ref LL_GPIO_PULL_DOWN
593 * @arg @ref LL_GPIO_PULL_UP
594 */
LL_GPIO_GetPinPull(GPIO_TypeDef * GPIOx,uint32_t Pin)595 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
596 {
597 return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
598 }
599
600 /**
601 * @brief Lock configuration of several pins for a dedicated port.
602 * @note When the lock sequence has been applied on a port bit, the
603 * value of this port bit can no longer be modified until the
604 * next reset.
605 * @note Each lock bit freezes a specific configuration register
606 * (control and alternate function registers).
607 * @rmtoll LCKR LCKK LL_GPIO_LockPin
608 * @param GPIOx GPIO Port
609 * @param PinMask This parameter can be a combination of the following values:
610 * @arg @ref LL_GPIO_PIN_0
611 * @arg @ref LL_GPIO_PIN_1
612 * @arg @ref LL_GPIO_PIN_2
613 * @arg @ref LL_GPIO_PIN_3
614 * @arg @ref LL_GPIO_PIN_4
615 * @arg @ref LL_GPIO_PIN_5
616 * @arg @ref LL_GPIO_PIN_6
617 * @arg @ref LL_GPIO_PIN_7
618 * @arg @ref LL_GPIO_PIN_8
619 * @arg @ref LL_GPIO_PIN_9
620 * @arg @ref LL_GPIO_PIN_10
621 * @arg @ref LL_GPIO_PIN_11
622 * @arg @ref LL_GPIO_PIN_12
623 * @arg @ref LL_GPIO_PIN_13
624 * @arg @ref LL_GPIO_PIN_14
625 * @arg @ref LL_GPIO_PIN_15
626 * @arg @ref LL_GPIO_PIN_ALL
627 * @retval None
628 */
LL_GPIO_LockPin(GPIO_TypeDef * GPIOx,uint32_t PinMask)629 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
630 {
631 __IO uint32_t temp;
632 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
633 WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
634 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
635 temp = READ_REG(GPIOx->LCKR);
636 (void) temp;
637 }
638
639 /**
640 * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
641 * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
642 * @param GPIOx GPIO Port
643 * @param PinMask This parameter can be a combination of the following values:
644 * @arg @ref LL_GPIO_PIN_0
645 * @arg @ref LL_GPIO_PIN_1
646 * @arg @ref LL_GPIO_PIN_2
647 * @arg @ref LL_GPIO_PIN_3
648 * @arg @ref LL_GPIO_PIN_4
649 * @arg @ref LL_GPIO_PIN_5
650 * @arg @ref LL_GPIO_PIN_6
651 * @arg @ref LL_GPIO_PIN_7
652 * @arg @ref LL_GPIO_PIN_8
653 * @arg @ref LL_GPIO_PIN_9
654 * @arg @ref LL_GPIO_PIN_10
655 * @arg @ref LL_GPIO_PIN_11
656 * @arg @ref LL_GPIO_PIN_12
657 * @arg @ref LL_GPIO_PIN_13
658 * @arg @ref LL_GPIO_PIN_14
659 * @arg @ref LL_GPIO_PIN_15
660 * @arg @ref LL_GPIO_PIN_ALL
661 * @retval State of bit (1 or 0).
662 */
LL_GPIO_IsPinLocked(GPIO_TypeDef * GPIOx,uint32_t PinMask)663 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
664 {
665 return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
666 }
667
668 /**
669 * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
670 * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
671 * @param GPIOx GPIO Port
672 * @retval State of bit (1 or 0).
673 */
LL_GPIO_IsAnyPinLocked(GPIO_TypeDef * GPIOx)674 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
675 {
676 return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
677 }
678
679 /**
680 * @}
681 */
682
683 /** @defgroup GPIO_LL_EF_Data_Access Data Access
684 * @{
685 */
686
687 /**
688 * @brief Return full input data register value for a dedicated port.
689 * @rmtoll IDR IDy LL_GPIO_ReadInputPort
690 * @param GPIOx GPIO Port
691 * @retval Input data register value of port
692 */
LL_GPIO_ReadInputPort(GPIO_TypeDef * GPIOx)693 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
694 {
695 return (READ_REG(GPIOx->IDR));
696 }
697
698 /**
699 * @brief Return if input data level for several pins of dedicated port is high or low.
700 * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
701 * @param GPIOx GPIO Port
702 * @param PinMask This parameter can be a combination of the following values:
703 * @arg @ref LL_GPIO_PIN_0
704 * @arg @ref LL_GPIO_PIN_1
705 * @arg @ref LL_GPIO_PIN_2
706 * @arg @ref LL_GPIO_PIN_3
707 * @arg @ref LL_GPIO_PIN_4
708 * @arg @ref LL_GPIO_PIN_5
709 * @arg @ref LL_GPIO_PIN_6
710 * @arg @ref LL_GPIO_PIN_7
711 * @arg @ref LL_GPIO_PIN_8
712 * @arg @ref LL_GPIO_PIN_9
713 * @arg @ref LL_GPIO_PIN_10
714 * @arg @ref LL_GPIO_PIN_11
715 * @arg @ref LL_GPIO_PIN_12
716 * @arg @ref LL_GPIO_PIN_13
717 * @arg @ref LL_GPIO_PIN_14
718 * @arg @ref LL_GPIO_PIN_15
719 * @arg @ref LL_GPIO_PIN_ALL
720 * @retval State of bit (1 or 0).
721 */
LL_GPIO_IsInputPinSet(GPIO_TypeDef * GPIOx,uint32_t PinMask)722 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
723 {
724 return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
725 }
726
727 /**
728 * @brief Write output data register for the port.
729 * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
730 * @param GPIOx GPIO Port
731 * @param PortValue Level value for each pin of the port
732 * @retval None
733 */
LL_GPIO_WriteOutputPort(GPIO_TypeDef * GPIOx,uint32_t PortValue)734 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
735 {
736 WRITE_REG(GPIOx->ODR, PortValue);
737 }
738
739 /**
740 * @brief Return full output data register value for a dedicated port.
741 * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
742 * @param GPIOx GPIO Port
743 * @retval Output data register value of port
744 */
LL_GPIO_ReadOutputPort(GPIO_TypeDef * GPIOx)745 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
746 {
747 return (uint32_t)(READ_REG(GPIOx->ODR));
748 }
749
750 /**
751 * @brief Return if input data level for several pins of dedicated port is high or low.
752 * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
753 * @param GPIOx GPIO Port
754 * @param PinMask This parameter can be a combination of the following values:
755 * @arg @ref LL_GPIO_PIN_0
756 * @arg @ref LL_GPIO_PIN_1
757 * @arg @ref LL_GPIO_PIN_2
758 * @arg @ref LL_GPIO_PIN_3
759 * @arg @ref LL_GPIO_PIN_4
760 * @arg @ref LL_GPIO_PIN_5
761 * @arg @ref LL_GPIO_PIN_6
762 * @arg @ref LL_GPIO_PIN_7
763 * @arg @ref LL_GPIO_PIN_8
764 * @arg @ref LL_GPIO_PIN_9
765 * @arg @ref LL_GPIO_PIN_10
766 * @arg @ref LL_GPIO_PIN_11
767 * @arg @ref LL_GPIO_PIN_12
768 * @arg @ref LL_GPIO_PIN_13
769 * @arg @ref LL_GPIO_PIN_14
770 * @arg @ref LL_GPIO_PIN_15
771 * @arg @ref LL_GPIO_PIN_ALL
772 * @retval State of bit (1 or 0).
773 */
LL_GPIO_IsOutputPinSet(GPIO_TypeDef * GPIOx,uint32_t PinMask)774 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
775 {
776 return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
777 }
778
779 /**
780 * @brief Set several pins to high level on dedicated gpio port.
781 * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
782 * @param GPIOx GPIO Port
783 * @param PinMask This parameter can be a combination of the following values:
784 * @arg @ref LL_GPIO_PIN_0
785 * @arg @ref LL_GPIO_PIN_1
786 * @arg @ref LL_GPIO_PIN_2
787 * @arg @ref LL_GPIO_PIN_3
788 * @arg @ref LL_GPIO_PIN_4
789 * @arg @ref LL_GPIO_PIN_5
790 * @arg @ref LL_GPIO_PIN_6
791 * @arg @ref LL_GPIO_PIN_7
792 * @arg @ref LL_GPIO_PIN_8
793 * @arg @ref LL_GPIO_PIN_9
794 * @arg @ref LL_GPIO_PIN_10
795 * @arg @ref LL_GPIO_PIN_11
796 * @arg @ref LL_GPIO_PIN_12
797 * @arg @ref LL_GPIO_PIN_13
798 * @arg @ref LL_GPIO_PIN_14
799 * @arg @ref LL_GPIO_PIN_15
800 * @arg @ref LL_GPIO_PIN_ALL
801 * @retval None
802 */
LL_GPIO_SetOutputPin(GPIO_TypeDef * GPIOx,uint32_t PinMask)803 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
804 {
805 WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
806 }
807
808 /**
809 * @brief Set several pins to low level on dedicated gpio port.
810 * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
811 * @param GPIOx GPIO Port
812 * @param PinMask This parameter can be a combination of the following values:
813 * @arg @ref LL_GPIO_PIN_0
814 * @arg @ref LL_GPIO_PIN_1
815 * @arg @ref LL_GPIO_PIN_2
816 * @arg @ref LL_GPIO_PIN_3
817 * @arg @ref LL_GPIO_PIN_4
818 * @arg @ref LL_GPIO_PIN_5
819 * @arg @ref LL_GPIO_PIN_6
820 * @arg @ref LL_GPIO_PIN_7
821 * @arg @ref LL_GPIO_PIN_8
822 * @arg @ref LL_GPIO_PIN_9
823 * @arg @ref LL_GPIO_PIN_10
824 * @arg @ref LL_GPIO_PIN_11
825 * @arg @ref LL_GPIO_PIN_12
826 * @arg @ref LL_GPIO_PIN_13
827 * @arg @ref LL_GPIO_PIN_14
828 * @arg @ref LL_GPIO_PIN_15
829 * @arg @ref LL_GPIO_PIN_ALL
830 * @retval None
831 */
LL_GPIO_ResetOutputPin(GPIO_TypeDef * GPIOx,uint32_t PinMask)832 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
833 {
834 WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
835 }
836
837 /**
838 * @brief Toggle data value for several pin of dedicated port.
839 * @rmtoll ODR ODy LL_GPIO_TogglePin
840 * @param GPIOx GPIO Port
841 * @param PinMask This parameter can be a combination of the following values:
842 * @arg @ref LL_GPIO_PIN_0
843 * @arg @ref LL_GPIO_PIN_1
844 * @arg @ref LL_GPIO_PIN_2
845 * @arg @ref LL_GPIO_PIN_3
846 * @arg @ref LL_GPIO_PIN_4
847 * @arg @ref LL_GPIO_PIN_5
848 * @arg @ref LL_GPIO_PIN_6
849 * @arg @ref LL_GPIO_PIN_7
850 * @arg @ref LL_GPIO_PIN_8
851 * @arg @ref LL_GPIO_PIN_9
852 * @arg @ref LL_GPIO_PIN_10
853 * @arg @ref LL_GPIO_PIN_11
854 * @arg @ref LL_GPIO_PIN_12
855 * @arg @ref LL_GPIO_PIN_13
856 * @arg @ref LL_GPIO_PIN_14
857 * @arg @ref LL_GPIO_PIN_15
858 * @arg @ref LL_GPIO_PIN_ALL
859 * @retval None
860 */
LL_GPIO_TogglePin(GPIO_TypeDef * GPIOx,uint32_t PinMask)861 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
862 {
863 uint32_t odr = READ_REG(GPIOx->ODR);
864 uint32_t pinmask = ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
865 WRITE_REG(GPIOx->BSRR, ((odr & pinmask) << 16u) | (~odr & pinmask));
866 }
867
868 /**
869 * @}
870 */
871
872 /** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping
873 * @brief This section propose definition to remap the alternate function to some other port/pins.
874 * @{
875 */
876
877 /**
878 * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
879 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1
880 * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
881 * @retval None
882 */
LL_GPIO_AF_EnableRemap_SPI1(void)883 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
884 {
885 SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG);
886 }
887
888 /**
889 * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
890 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1
891 * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
892 * @retval None
893 */
LL_GPIO_AF_DisableRemap_SPI1(void)894 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
895 {
896 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
897 }
898
899 /**
900 * @brief Check if SPI1 has been remapped or not
901 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1
902 * @retval State of bit (1 or 0).
903 */
LL_GPIO_AF_IsEnabledRemap_SPI1(void)904 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void)
905 {
906 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP));
907 }
908
909 /**
910 * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
911 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1
912 * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
913 * @retval None
914 */
LL_GPIO_AF_EnableRemap_I2C1(void)915 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
916 {
917 SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG);
918 }
919
920 /**
921 * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
922 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1
923 * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
924 * @retval None
925 */
LL_GPIO_AF_DisableRemap_I2C1(void)926 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
927 {
928 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
929 }
930
931 /**
932 * @brief Check if I2C1 has been remapped or not
933 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1
934 * @retval State of bit (1 or 0).
935 */
LL_GPIO_AF_IsEnabledRemap_I2C1(void)936 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void)
937 {
938 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP));
939 }
940
941 /**
942 * @brief Enable the remapping of USART1 alternate function TX and RX.
943 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1
944 * @note ENABLE: Remap (TX/PB6, RX/PB7)
945 * @retval None
946 */
LL_GPIO_AF_EnableRemap_USART1(void)947 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
948 {
949 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG);
950 }
951
952 /**
953 * @brief Disable the remapping of USART1 alternate function TX and RX.
954 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1
955 * @note DISABLE: No remap (TX/PA9, RX/PA10)
956 * @retval None
957 */
LL_GPIO_AF_DisableRemap_USART1(void)958 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
959 {
960 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
961 }
962
963 /**
964 * @brief Check if USART1 has been remapped or not
965 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1
966 * @retval State of bit (1 or 0).
967 */
LL_GPIO_AF_IsEnabledRemap_USART1(void)968 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void)
969 {
970 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP));
971 }
972
973 /**
974 * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
975 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2
976 * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
977 * @retval None
978 */
LL_GPIO_AF_EnableRemap_USART2(void)979 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
980 {
981 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG);
982 }
983
984 /**
985 * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
986 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2
987 * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
988 * @retval None
989 */
LL_GPIO_AF_DisableRemap_USART2(void)990 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
991 {
992 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
993 }
994
995 /**
996 * @brief Check if USART2 has been remapped or not
997 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2
998 * @retval State of bit (1 or 0).
999 */
LL_GPIO_AF_IsEnabledRemap_USART2(void)1000 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void)
1001 {
1002 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP));
1003 }
1004
1005 #if defined (AFIO_MAPR_USART3_REMAP)
1006 /**
1007 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
1008 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3
1009 * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
1010 * @retval None
1011 */
LL_GPIO_AF_EnableRemap_USART3(void)1012 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
1013 {
1014 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1015 }
1016
1017 /**
1018 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
1019 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3
1020 * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
1021 * @retval None
1022 */
LL_GPIO_AF_RemapPartial_USART3(void)1023 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
1024 {
1025 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
1026 }
1027
1028 /**
1029 * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
1030 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3
1031 * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
1032 * @retval None
1033 */
LL_GPIO_AF_DisableRemap_USART3(void)1034 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
1035 {
1036 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1037 }
1038 #endif
1039
1040 /**
1041 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
1042 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1
1043 * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
1044 * @retval None
1045 */
LL_GPIO_AF_EnableRemap_TIM1(void)1046 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
1047 {
1048 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1049 }
1050
1051 /**
1052 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
1053 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1
1054 * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
1055 * @retval None
1056 */
LL_GPIO_AF_RemapPartial_TIM1(void)1057 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
1058 {
1059 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
1060 }
1061
1062 /**
1063 * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
1064 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1
1065 * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
1066 * @retval None
1067 */
LL_GPIO_AF_DisableRemap_TIM1(void)1068 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
1069 {
1070 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1071 }
1072
1073 /**
1074 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1075 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2
1076 * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
1077 * @retval None
1078 */
LL_GPIO_AF_EnableRemap_TIM2(void)1079 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
1080 {
1081 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1082 }
1083
1084 /**
1085 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1086 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2
1087 * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
1088 * @retval None
1089 */
LL_GPIO_AF_RemapPartial2_TIM2(void)1090 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
1091 {
1092 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 | AFIO_MAPR_SWJ_CFG));
1093 }
1094
1095 /**
1096 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1097 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2
1098 * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
1099 * @retval None
1100 */
LL_GPIO_AF_RemapPartial1_TIM2(void)1101 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
1102 {
1103 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 | AFIO_MAPR_SWJ_CFG));
1104 }
1105
1106 /**
1107 * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1108 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2
1109 * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
1110 * @retval None
1111 */
LL_GPIO_AF_DisableRemap_TIM2(void)1112 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
1113 {
1114 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1115 }
1116
1117 /**
1118 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
1119 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3
1120 * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
1121 * @note TIM3_ETR on PE0 is not re-mapped.
1122 * @retval None
1123 */
LL_GPIO_AF_EnableRemap_TIM3(void)1124 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
1125 {
1126 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1127 }
1128
1129 /**
1130 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
1131 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3
1132 * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
1133 * @note TIM3_ETR on PE0 is not re-mapped.
1134 * @retval None
1135 */
LL_GPIO_AF_RemapPartial_TIM3(void)1136 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
1137 {
1138 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
1139 }
1140
1141 /**
1142 * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
1143 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3
1144 * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
1145 * @note TIM3_ETR on PE0 is not re-mapped.
1146 * @retval None
1147 */
LL_GPIO_AF_DisableRemap_TIM3(void)1148 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
1149 {
1150 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1151 }
1152
1153 #if defined(AFIO_MAPR_TIM4_REMAP)
1154 /**
1155 * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
1156 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4
1157 * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
1158 * @note TIM4_ETR on PE0 is not re-mapped.
1159 * @retval None
1160 */
LL_GPIO_AF_EnableRemap_TIM4(void)1161 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
1162 {
1163 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG);
1164 }
1165 /**
1166 * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
1167 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4
1168 * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
1169 * @note TIM4_ETR on PE0 is not re-mapped.
1170 * @retval None
1171 */
LL_GPIO_AF_DisableRemap_TIM4(void)1172 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
1173 {
1174 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1175 }
1176
1177 /**
1178 * @brief Check if TIM4 has been remapped or not
1179 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4
1180 * @retval State of bit (1 or 0).
1181 */
LL_GPIO_AF_IsEnabledRemap_TIM4(void)1182 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void)
1183 {
1184 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP));
1185 }
1186 #endif
1187
1188 #if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
1189
1190 /**
1191 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
1192 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1
1193 * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
1194 * @retval None
1195 */
LL_GPIO_AF_RemapPartial1_CAN1(void)1196 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
1197 {
1198 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP1 | AFIO_MAPR_SWJ_CFG));
1199 }
1200
1201 /**
1202 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
1203 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1
1204 * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
1205 * @retval None
1206 */
LL_GPIO_AF_RemapPartial2_CAN1(void)1207 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
1208 {
1209 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP2 | AFIO_MAPR_SWJ_CFG));
1210 }
1211
1212 /**
1213 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
1214 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1
1215 * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
1216 * @retval None
1217 */
LL_GPIO_AF_RemapPartial3_CAN1(void)1218 __STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
1219 {
1220 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP3 | AFIO_MAPR_SWJ_CFG));
1221 }
1222 #endif
1223
1224 /**
1225 * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
1226 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
1227 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
1228 * on 100-pin and 144-pin packages, no need for remapping).
1229 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01
1230 * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
1231 * @retval None
1232 */
LL_GPIO_AF_EnableRemap_PD01(void)1233 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
1234 {
1235 SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG);
1236 }
1237
1238 /**
1239 * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
1240 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
1241 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
1242 * on 100-pin and 144-pin packages, no need for remapping).
1243 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01
1244 * @note DISABLE: No remapping of PD0 and PD1
1245 * @retval None
1246 */
LL_GPIO_AF_DisableRemap_PD01(void)1247 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
1248 {
1249 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1250 }
1251
1252 /**
1253 * @brief Check if PD01 has been remapped or not
1254 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01
1255 * @retval State of bit (1 or 0).
1256 */
LL_GPIO_AF_IsEnabledRemap_PD01(void)1257 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void)
1258 {
1259 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP));
1260 }
1261
1262 #if defined(AFIO_MAPR_TIM5CH4_IREMAP)
1263 /**
1264 * @brief Enable the remapping of TIM5CH4.
1265 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4
1266 * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
1267 * @note This function is available only in high density value line devices.
1268 * @retval None
1269 */
LL_GPIO_AF_EnableRemap_TIM5CH4(void)1270 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
1271 {
1272 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG);
1273 }
1274
1275 /**
1276 * @brief Disable the remapping of TIM5CH4.
1277 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4
1278 * @note DISABLE: TIM5_CH4 is connected to PA3
1279 * @note This function is available only in high density value line devices.
1280 * @retval None
1281 */
LL_GPIO_AF_DisableRemap_TIM5CH4(void)1282 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
1283 {
1284 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1285 }
1286
1287 /**
1288 * @brief Check if TIM5CH4 has been remapped or not
1289 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4
1290 * @retval State of bit (1 or 0).
1291 */
LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)1292 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)
1293 {
1294 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP));
1295 }
1296 #endif
1297
1298 #if defined(AFIO_MAPR_ETH_REMAP)
1299 /**
1300 * @brief Enable the remapping of Ethernet MAC connections with the PHY.
1301 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH
1302 * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
1303 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1304 * @retval None
1305 */
LL_GPIO_AF_EnableRemap_ETH(void)1306 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
1307 {
1308 SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG);
1309 }
1310
1311 /**
1312 * @brief Disable the remapping of Ethernet MAC connections with the PHY.
1313 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH
1314 * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
1315 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1316 * @retval None
1317 */
LL_GPIO_AF_DisableRemap_ETH(void)1318 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
1319 {
1320 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1321 }
1322
1323 /**
1324 * @brief Check if ETH has been remapped or not
1325 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH
1326 * @retval State of bit (1 or 0).
1327 */
LL_GPIO_AF_IsEnabledRemap_ETH(void)1328 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void)
1329 {
1330 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP));
1331 }
1332 #endif
1333
1334 #if defined(AFIO_MAPR_CAN2_REMAP)
1335
1336 /**
1337 * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
1338 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2
1339 * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
1340 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1341 * @retval None
1342 */
LL_GPIO_AF_EnableRemap_CAN2(void)1343 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
1344 {
1345 SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG);
1346 }
1347 /**
1348 * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
1349 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2
1350 * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
1351 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1352 * @retval None
1353 */
LL_GPIO_AF_DisableRemap_CAN2(void)1354 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
1355 {
1356 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1357 }
1358
1359 /**
1360 * @brief Check if CAN2 has been remapped or not
1361 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2
1362 * @retval State of bit (1 or 0).
1363 */
LL_GPIO_AF_IsEnabledRemap_CAN2(void)1364 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void)
1365 {
1366 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP));
1367 }
1368 #endif
1369
1370 #if defined(AFIO_MAPR_MII_RMII_SEL)
1371 /**
1372 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
1373 * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII
1374 * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
1375 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1376 * @retval None
1377 */
LL_GPIO_AF_Select_ETH_RMII(void)1378 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
1379 {
1380 SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG);
1381 }
1382
1383 /**
1384 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
1385 * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII
1386 * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
1387 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1388 * @retval None
1389 */
LL_GPIO_AF_Select_ETH_MII(void)1390 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
1391 {
1392 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1393 }
1394 #endif
1395
1396 #if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
1397 /**
1398 * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
1399 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ
1400 * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
1401 * @retval None
1402 */
LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)1403 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
1404 {
1405 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG);
1406 }
1407
1408 /**
1409 * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
1410 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
1411 * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
1412 * @retval None
1413 */
LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)1414 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
1415 {
1416 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1417 }
1418
1419 /**
1420 * @brief Check if ADC1_ETRGINJ has been remapped or not
1421 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
1422 * @retval State of bit (1 or 0).
1423 */
LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)1424 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)
1425 {
1426 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP));
1427 }
1428 #endif
1429
1430 #if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
1431 /**
1432 * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
1433 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG
1434 * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
1435 * @retval None
1436 */
LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)1437 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
1438 {
1439 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG);
1440 }
1441
1442 /**
1443 * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
1444 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
1445 * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
1446 * @retval None
1447 */
LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)1448 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
1449 {
1450 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1451 }
1452
1453 /**
1454 * @brief Check if ADC1_ETRGREG has been remapped or not
1455 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
1456 * @retval State of bit (1 or 0).
1457 */
LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)1458 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)
1459 {
1460 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP));
1461 }
1462 #endif
1463
1464 #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
1465
1466 /**
1467 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
1468 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ
1469 * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
1470 * @retval None
1471 */
LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)1472 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
1473 {
1474 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG);
1475 }
1476
1477 /**
1478 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
1479 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
1480 * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
1481 * @retval None
1482 */
LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)1483 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
1484 {
1485 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1486 }
1487
1488 /**
1489 * @brief Check if ADC2_ETRGINJ has been remapped or not
1490 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
1491 * @retval State of bit (1 or 0).
1492 */
LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)1493 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)
1494 {
1495 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP));
1496 }
1497 #endif
1498
1499 #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
1500
1501 /**
1502 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1503 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG
1504 * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
1505 * @retval None
1506 */
LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)1507 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
1508 {
1509 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG);
1510 }
1511
1512 /**
1513 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1514 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
1515 * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
1516 * @retval None
1517 */
LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)1518 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
1519 {
1520 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1521 }
1522
1523 /**
1524 * @brief Check if ADC2_ETRGREG has been remapped or not
1525 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
1526 * @retval State of bit (1 or 0).
1527 */
LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)1528 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)
1529 {
1530 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP));
1531 }
1532 #endif
1533
1534 /**
1535 * @brief Enable the Serial wire JTAG configuration
1536 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ
1537 * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
1538 * @retval None
1539 */
LL_GPIO_AF_EnableRemap_SWJ(void)1540 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void)
1541 {
1542 MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET);
1543 }
1544
1545 /**
1546 * @brief Enable the Serial wire JTAG configuration
1547 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST
1548 * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
1549 * @retval None
1550 */
LL_GPIO_AF_Remap_SWJ_NONJTRST(void)1551 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void)
1552 {
1553 MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST);
1554 }
1555
1556 /**
1557 * @brief Enable the Serial wire JTAG configuration
1558 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG
1559 * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
1560 * @retval None
1561 */
LL_GPIO_AF_Remap_SWJ_NOJTAG(void)1562 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void)
1563 {
1564 MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE);
1565 }
1566
1567 /**
1568 * @brief Disable the Serial wire JTAG configuration
1569 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ
1570 * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
1571 * @retval None
1572 */
LL_GPIO_AF_DisableRemap_SWJ(void)1573 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void)
1574 {
1575 MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE);
1576 }
1577
1578 #if defined(AFIO_MAPR_SPI3_REMAP)
1579
1580 /**
1581 * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
1582 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3
1583 * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
1584 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1585 * @retval None
1586 */
LL_GPIO_AF_EnableRemap_SPI3(void)1587 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
1588 {
1589 SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG);
1590 }
1591
1592 /**
1593 * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
1594 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3
1595 * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
1596 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1597 * @retval None
1598 */
LL_GPIO_AF_DisableRemap_SPI3(void)1599 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
1600 {
1601 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1602 }
1603
1604 /**
1605 * @brief Check if SPI3 has been remapped or not
1606 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
1607 * @retval State of bit (1 or 0).
1608 */
LL_GPIO_AF_IsEnabledRemap_SPI3(void)1609 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void)
1610 {
1611 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP));
1612 }
1613 #endif
1614
1615 #if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
1616
1617 /**
1618 * @brief Control of TIM2_ITR1 internal mapping.
1619 * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB
1620 * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
1621 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1622 * @retval None
1623 */
LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)1624 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
1625 {
1626 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG);
1627 }
1628
1629 /**
1630 * @brief Control of TIM2_ITR1 internal mapping.
1631 * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
1632 * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
1633 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1634 * @retval None
1635 */
LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)1636 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
1637 {
1638 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1639 }
1640 #endif
1641
1642 #if defined(AFIO_MAPR_PTP_PPS_REMAP)
1643
1644 /**
1645 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1646 * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS
1647 * @note ENABLE: PTP_PPS is output on PB5 pin.
1648 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1649 * @retval None
1650 */
LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)1651 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
1652 {
1653 SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG);
1654 }
1655
1656 /**
1657 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1658 * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
1659 * @note DISABLE: PTP_PPS not output on PB5 pin.
1660 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1661 * @retval None
1662 */
LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)1663 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
1664 {
1665 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1666 }
1667 #endif
1668
1669 #if defined(AFIO_MAPR2_TIM9_REMAP)
1670
1671 /**
1672 * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
1673 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9
1674 * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
1675 * @retval None
1676 */
LL_GPIO_AF_EnableRemap_TIM9(void)1677 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void)
1678 {
1679 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
1680 }
1681
1682 /**
1683 * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
1684 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9
1685 * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
1686 * @retval None
1687 */
LL_GPIO_AF_DisableRemap_TIM9(void)1688 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void)
1689 {
1690 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
1691 }
1692
1693 /**
1694 * @brief Check if TIM9_CH1 and TIM9_CH2 have been remapped or not
1695 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9
1696 * @retval State of bit (1 or 0).
1697 */
LL_GPIO_AF_IsEnabledRemap_TIM9(void)1698 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void)
1699 {
1700 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP));
1701 }
1702 #endif
1703
1704 #if defined(AFIO_MAPR2_TIM10_REMAP)
1705
1706 /**
1707 * @brief Enable the remapping of TIM10_CH1.
1708 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10
1709 * @note ENABLE: Remap (TIM10_CH1 on PF6).
1710 * @retval None
1711 */
LL_GPIO_AF_EnableRemap_TIM10(void)1712 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void)
1713 {
1714 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
1715 }
1716
1717 /**
1718 * @brief Disable the remapping of TIM10_CH1.
1719 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10
1720 * @note DISABLE: No remap (TIM10_CH1 on PB8).
1721 * @retval None
1722 */
LL_GPIO_AF_DisableRemap_TIM10(void)1723 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void)
1724 {
1725 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
1726 }
1727
1728 /**
1729 * @brief Check if TIM10_CH1 has been remapped or not
1730 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10
1731 * @retval State of bit (1 or 0).
1732 */
LL_GPIO_AF_IsEnabledRemap_TIM10(void)1733 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void)
1734 {
1735 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP));
1736 }
1737 #endif
1738
1739 #if defined(AFIO_MAPR2_TIM11_REMAP)
1740 /**
1741 * @brief Enable the remapping of TIM11_CH1.
1742 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11
1743 * @note ENABLE: Remap (TIM11_CH1 on PF7).
1744 * @retval None
1745 */
LL_GPIO_AF_EnableRemap_TIM11(void)1746 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void)
1747 {
1748 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
1749 }
1750
1751 /**
1752 * @brief Disable the remapping of TIM11_CH1.
1753 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11
1754 * @note DISABLE: No remap (TIM11_CH1 on PB9).
1755 * @retval None
1756 */
LL_GPIO_AF_DisableRemap_TIM11(void)1757 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void)
1758 {
1759 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
1760 }
1761
1762 /**
1763 * @brief Check if TIM11_CH1 has been remapped or not
1764 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11
1765 * @retval State of bit (1 or 0).
1766 */
LL_GPIO_AF_IsEnabledRemap_TIM11(void)1767 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void)
1768 {
1769 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP));
1770 }
1771 #endif
1772
1773 #if defined(AFIO_MAPR2_TIM13_REMAP)
1774
1775 /**
1776 * @brief Enable the remapping of TIM13_CH1.
1777 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13
1778 * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
1779 * @retval None
1780 */
LL_GPIO_AF_EnableRemap_TIM13(void)1781 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void)
1782 {
1783 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
1784 }
1785
1786 /**
1787 * @brief Disable the remapping of TIM13_CH1.
1788 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13
1789 * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
1790 * @retval None
1791 */
LL_GPIO_AF_DisableRemap_TIM13(void)1792 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void)
1793 {
1794 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
1795 }
1796
1797 /**
1798 * @brief Check if TIM13_CH1 has been remapped or not
1799 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13
1800 * @retval State of bit (1 or 0).
1801 */
LL_GPIO_AF_IsEnabledRemap_TIM13(void)1802 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void)
1803 {
1804 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP));
1805 }
1806 #endif
1807
1808 #if defined(AFIO_MAPR2_TIM14_REMAP)
1809
1810 /**
1811 * @brief Enable the remapping of TIM14_CH1.
1812 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14
1813 * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
1814 * @retval None
1815 */
LL_GPIO_AF_EnableRemap_TIM14(void)1816 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void)
1817 {
1818 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
1819 }
1820
1821 /**
1822 * @brief Disable the remapping of TIM14_CH1.
1823 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14
1824 * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
1825 * @retval None
1826 */
LL_GPIO_AF_DisableRemap_TIM14(void)1827 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void)
1828 {
1829 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
1830 }
1831
1832 /**
1833 * @brief Check if TIM14_CH1 has been remapped or not
1834 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14
1835 * @retval State of bit (1 or 0).
1836 */
LL_GPIO_AF_IsEnabledRemap_TIM14(void)1837 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void)
1838 {
1839 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP));
1840 }
1841 #endif
1842
1843 #if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
1844
1845 /**
1846 * @brief Controls the use of the optional FSMC_NADV signal.
1847 * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV
1848 * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
1849 * @retval None
1850 */
LL_GPIO_AF_Disconnect_FSMCNADV(void)1851 __STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void)
1852 {
1853 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
1854 }
1855
1856 /**
1857 * @brief Controls the use of the optional FSMC_NADV signal.
1858 * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV
1859 * @note CONNECTED: The NADV signal is connected to the output (default).
1860 * @retval None
1861 */
LL_GPIO_AF_Connect_FSMCNADV(void)1862 __STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void)
1863 {
1864 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
1865 }
1866 #endif
1867
1868 #if defined(AFIO_MAPR2_TIM15_REMAP)
1869
1870 /**
1871 * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
1872 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15
1873 * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
1874 * @retval None
1875 */
LL_GPIO_AF_EnableRemap_TIM15(void)1876 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void)
1877 {
1878 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
1879 }
1880 /**
1881 * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
1882 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15
1883 * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
1884 * @retval None
1885 */
LL_GPIO_AF_DisableRemap_TIM15(void)1886 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void)
1887 {
1888 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
1889 }
1890
1891 /**
1892 * @brief Check if TIM15_CH1 has been remapped or not
1893 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15
1894 * @retval State of bit (1 or 0).
1895 */
LL_GPIO_AF_IsEnabledRemap_TIM15(void)1896 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void)
1897 {
1898 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP));
1899 }
1900 #endif
1901
1902 #if defined(AFIO_MAPR2_TIM16_REMAP)
1903
1904 /**
1905 * @brief Enable the remapping of TIM16_CH1.
1906 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16
1907 * @note ENABLE: Remap (TIM16_CH1 on PA6).
1908 * @retval None
1909 */
LL_GPIO_AF_EnableRemap_TIM16(void)1910 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void)
1911 {
1912 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
1913 }
1914
1915 /**
1916 * @brief Disable the remapping of TIM16_CH1.
1917 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16
1918 * @note DISABLE: No remap (TIM16_CH1 on PB8).
1919 * @retval None
1920 */
LL_GPIO_AF_DisableRemap_TIM16(void)1921 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void)
1922 {
1923 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
1924 }
1925
1926 /**
1927 * @brief Check if TIM16_CH1 has been remapped or not
1928 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16
1929 * @retval State of bit (1 or 0).
1930 */
LL_GPIO_AF_IsEnabledRemap_TIM16(void)1931 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void)
1932 {
1933 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP));
1934 }
1935 #endif
1936
1937 #if defined(AFIO_MAPR2_TIM17_REMAP)
1938
1939 /**
1940 * @brief Enable the remapping of TIM17_CH1.
1941 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17
1942 * @note ENABLE: Remap (TIM17_CH1 on PA7).
1943 * @retval None
1944 */
LL_GPIO_AF_EnableRemap_TIM17(void)1945 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void)
1946 {
1947 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
1948 }
1949
1950 /**
1951 * @brief Disable the remapping of TIM17_CH1.
1952 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17
1953 * @note DISABLE: No remap (TIM17_CH1 on PB9).
1954 * @retval None
1955 */
LL_GPIO_AF_DisableRemap_TIM17(void)1956 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void)
1957 {
1958 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
1959 }
1960
1961 /**
1962 * @brief Check if TIM17_CH1 has been remapped or not
1963 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17
1964 * @retval State of bit (1 or 0).
1965 */
LL_GPIO_AF_IsEnabledRemap_TIM17(void)1966 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void)
1967 {
1968 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP));
1969 }
1970 #endif
1971
1972 #if defined(AFIO_MAPR2_CEC_REMAP)
1973
1974 /**
1975 * @brief Enable the remapping of CEC.
1976 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC
1977 * @note ENABLE: Remap (CEC on PB10).
1978 * @retval None
1979 */
LL_GPIO_AF_EnableRemap_CEC(void)1980 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void)
1981 {
1982 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
1983 }
1984
1985 /**
1986 * @brief Disable the remapping of CEC.
1987 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC
1988 * @note DISABLE: No remap (CEC on PB8).
1989 * @retval None
1990 */
LL_GPIO_AF_DisableRemap_CEC(void)1991 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void)
1992 {
1993 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
1994 }
1995
1996 /**
1997 * @brief Check if CEC has been remapped or not
1998 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC
1999 * @retval State of bit (1 or 0).
2000 */
LL_GPIO_AF_IsEnabledRemap_CEC(void)2001 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void)
2002 {
2003 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP));
2004 }
2005 #endif
2006
2007 #if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
2008
2009 /**
2010 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
2011 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA
2012 * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
2013 * @retval None
2014 */
LL_GPIO_AF_EnableRemap_TIM1DMA(void)2015 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void)
2016 {
2017 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
2018 }
2019
2020 /**
2021 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
2022 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA
2023 * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
2024 * @retval None
2025 */
LL_GPIO_AF_DisableRemap_TIM1DMA(void)2026 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void)
2027 {
2028 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
2029 }
2030
2031 /**
2032 * @brief Check if TIM1DMA has been remapped or not
2033 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA
2034 * @retval State of bit (1 or 0).
2035 */
LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)2036 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)
2037 {
2038 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP));
2039 }
2040 #endif
2041
2042 #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
2043
2044 /**
2045 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
2046 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA
2047 * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
2048 * @retval None
2049 */
LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)2050 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)
2051 {
2052 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
2053 }
2054
2055 /**
2056 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
2057 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA
2058 * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
2059 * @retval None
2060 */
LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)2061 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)
2062 {
2063 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
2064 }
2065
2066 /**
2067 * @brief Check if TIM67DACDMA has been remapped or not
2068 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA
2069 * @retval State of bit (1 or 0).
2070 */
LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)2071 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)
2072 {
2073 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP));
2074 }
2075 #endif
2076
2077 #if defined(AFIO_MAPR2_TIM12_REMAP)
2078
2079 /**
2080 * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
2081 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12
2082 * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
2083 * @note This bit is available only in high density value line devices.
2084 * @retval None
2085 */
LL_GPIO_AF_EnableRemap_TIM12(void)2086 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void)
2087 {
2088 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
2089 }
2090
2091 /**
2092 * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
2093 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12
2094 * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
2095 * @note This bit is available only in high density value line devices.
2096 * @retval None
2097 */
LL_GPIO_AF_DisableRemap_TIM12(void)2098 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void)
2099 {
2100 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
2101 }
2102
2103 /**
2104 * @brief Check if TIM12_CH1 has been remapped or not
2105 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12
2106 * @retval State of bit (1 or 0).
2107 */
LL_GPIO_AF_IsEnabledRemap_TIM12(void)2108 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void)
2109 {
2110 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP));
2111 }
2112 #endif
2113
2114 #if defined(AFIO_MAPR2_MISC_REMAP)
2115
2116 /**
2117 * @brief Miscellaneous features remapping.
2118 * This bit is set and cleared by software. It controls miscellaneous features.
2119 * The DMA2 channel 5 interrupt position in the vector table.
2120 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
2121 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC
2122 * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
2123 * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
2124 * @note This bit is available only in high density value line devices.
2125 * @retval None
2126 */
LL_GPIO_AF_EnableRemap_MISC(void)2127 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void)
2128 {
2129 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
2130 }
2131
2132 /**
2133 * @brief Miscellaneous features remapping.
2134 * This bit is set and cleared by software. It controls miscellaneous features.
2135 * The DMA2 channel 5 interrupt position in the vector table.
2136 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
2137 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC
2138 * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
2139 * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
2140 * @note This bit is available only in high density value line devices.
2141 * @retval None
2142 */
LL_GPIO_AF_DisableRemap_MISC(void)2143 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void)
2144 {
2145 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
2146 }
2147
2148 /**
2149 * @brief Check if MISC has been remapped or not
2150 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC
2151 * @retval State of bit (1 or 0).
2152 */
LL_GPIO_AF_IsEnabledRemap_MISC(void)2153 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void)
2154 {
2155 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP));
2156 }
2157 #endif
2158
2159 /**
2160 * @}
2161 */
2162
2163 /** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration
2164 * @brief This section propose definition to Configure EVENTOUT Cortex feature .
2165 * @{
2166 */
2167
2168 /**
2169 * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
2170 * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n
2171 * EVCR PIN LL_GPIO_AF_ConfigEventout
2172 * @param LL_GPIO_PortSource This parameter can be one of the following values:
2173 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A
2174 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B
2175 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C
2176 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D
2177 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E
2178 * @param LL_GPIO_PinSource This parameter can be one of the following values:
2179 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0
2180 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1
2181 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2
2182 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3
2183 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4
2184 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5
2185 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6
2186 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7
2187 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8
2188 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9
2189 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10
2190 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11
2191 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12
2192 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13
2193 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14
2194 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15
2195 * @retval None
2196 */
LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource,uint32_t LL_GPIO_PinSource)2197 __STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
2198 {
2199 MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource));
2200 }
2201
2202 /**
2203 * @brief Enables the Event Output.
2204 * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout
2205 * @retval None
2206 */
LL_GPIO_AF_EnableEventout(void)2207 __STATIC_INLINE void LL_GPIO_AF_EnableEventout(void)
2208 {
2209 SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
2210 }
2211
2212 /**
2213 * @brief Disables the Event Output.
2214 * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout
2215 * @retval None
2216 */
LL_GPIO_AF_DisableEventout(void)2217 __STATIC_INLINE void LL_GPIO_AF_DisableEventout(void)
2218 {
2219 CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
2220 }
2221
2222 /**
2223 * @}
2224 */
2225 /** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt
2226 * @brief This section Configure source input for the EXTI external interrupt .
2227 * @{
2228 */
2229
2230 /**
2231 * @brief Configure source input for the EXTI external interrupt.
2232 * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n
2233 * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n
2234 * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n
2235 * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource
2236 * @param Port This parameter can be one of the following values:
2237 * @arg @ref LL_GPIO_AF_EXTI_PORTA
2238 * @arg @ref LL_GPIO_AF_EXTI_PORTB
2239 * @arg @ref LL_GPIO_AF_EXTI_PORTC
2240 * @arg @ref LL_GPIO_AF_EXTI_PORTD
2241 * @arg @ref LL_GPIO_AF_EXTI_PORTE
2242 * @arg @ref LL_GPIO_AF_EXTI_PORTF
2243 * @arg @ref LL_GPIO_AF_EXTI_PORTG
2244 * @param Line This parameter can be one of the following values:
2245 * @arg @ref LL_GPIO_AF_EXTI_LINE0
2246 * @arg @ref LL_GPIO_AF_EXTI_LINE1
2247 * @arg @ref LL_GPIO_AF_EXTI_LINE2
2248 * @arg @ref LL_GPIO_AF_EXTI_LINE3
2249 * @arg @ref LL_GPIO_AF_EXTI_LINE4
2250 * @arg @ref LL_GPIO_AF_EXTI_LINE5
2251 * @arg @ref LL_GPIO_AF_EXTI_LINE6
2252 * @arg @ref LL_GPIO_AF_EXTI_LINE7
2253 * @arg @ref LL_GPIO_AF_EXTI_LINE8
2254 * @arg @ref LL_GPIO_AF_EXTI_LINE9
2255 * @arg @ref LL_GPIO_AF_EXTI_LINE10
2256 * @arg @ref LL_GPIO_AF_EXTI_LINE11
2257 * @arg @ref LL_GPIO_AF_EXTI_LINE12
2258 * @arg @ref LL_GPIO_AF_EXTI_LINE13
2259 * @arg @ref LL_GPIO_AF_EXTI_LINE14
2260 * @arg @ref LL_GPIO_AF_EXTI_LINE15
2261 * @retval None
2262 */
LL_GPIO_AF_SetEXTISource(uint32_t Port,uint32_t Line)2263 __STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line)
2264 {
2265 MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
2266 }
2267
2268 /**
2269 * @brief Get the configured defined for specific EXTI Line
2270 * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n
2271 * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n
2272 * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n
2273 * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource
2274 * @param Line This parameter can be one of the following values:
2275 * @arg @ref LL_GPIO_AF_EXTI_LINE0
2276 * @arg @ref LL_GPIO_AF_EXTI_LINE1
2277 * @arg @ref LL_GPIO_AF_EXTI_LINE2
2278 * @arg @ref LL_GPIO_AF_EXTI_LINE3
2279 * @arg @ref LL_GPIO_AF_EXTI_LINE4
2280 * @arg @ref LL_GPIO_AF_EXTI_LINE5
2281 * @arg @ref LL_GPIO_AF_EXTI_LINE6
2282 * @arg @ref LL_GPIO_AF_EXTI_LINE7
2283 * @arg @ref LL_GPIO_AF_EXTI_LINE8
2284 * @arg @ref LL_GPIO_AF_EXTI_LINE9
2285 * @arg @ref LL_GPIO_AF_EXTI_LINE10
2286 * @arg @ref LL_GPIO_AF_EXTI_LINE11
2287 * @arg @ref LL_GPIO_AF_EXTI_LINE12
2288 * @arg @ref LL_GPIO_AF_EXTI_LINE13
2289 * @arg @ref LL_GPIO_AF_EXTI_LINE14
2290 * @arg @ref LL_GPIO_AF_EXTI_LINE15
2291 * @retval Returned value can be one of the following values:
2292 * @arg @ref LL_GPIO_AF_EXTI_PORTA
2293 * @arg @ref LL_GPIO_AF_EXTI_PORTB
2294 * @arg @ref LL_GPIO_AF_EXTI_PORTC
2295 * @arg @ref LL_GPIO_AF_EXTI_PORTD
2296 * @arg @ref LL_GPIO_AF_EXTI_PORTE
2297 * @arg @ref LL_GPIO_AF_EXTI_PORTF
2298 * @arg @ref LL_GPIO_AF_EXTI_PORTG
2299 */
LL_GPIO_AF_GetEXTISource(uint32_t Line)2300 __STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line)
2301 {
2302 return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
2303 }
2304
2305 /**
2306 * @}
2307 */
2308
2309 #if defined(USE_FULL_LL_DRIVER)
2310 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
2311 * @{
2312 */
2313
2314 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
2315 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
2316 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
2317
2318 /**
2319 * @}
2320 */
2321 #endif /* USE_FULL_LL_DRIVER */
2322
2323 /**
2324 * @}
2325 */
2326
2327 /**
2328 * @}
2329 */
2330
2331 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
2332 /**
2333 * @}
2334 */
2335
2336 #ifdef __cplusplus
2337 }
2338 #endif
2339
2340 #endif /* STM32F1xx_LL_GPIO_H */
2341
2342
