1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_dmamux.h
4 * @author MCD Application Team
5 * @brief Header file of DMAMUX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G0xx_LL_DMAMUX_H
22 #define STM32G0xx_LL_DMAMUX_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g0xx.h"
30
31 /** @addtogroup STM32G0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMAMUX1)
36
37 /** @defgroup DMAMUX_LL DMAMUX
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
45 * @{
46 */
47 /* Define used to get DMAMUX CCR register size */
48 #define DMAMUX_CCR_SIZE 0x00000004UL
49
50 /* Define used to get DMAMUX RGCR register size */
51 #define DMAMUX_RGCR_SIZE 0x00000004UL
52 /**
53 * @}
54 */
55
56 /* Private macros ------------------------------------------------------------*/
57 /* Exported types ------------------------------------------------------------*/
58 /* Exported constants --------------------------------------------------------*/
59 /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
60 * @{
61 */
62 /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
63 * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
64 * @{
65 */
66 #define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
67 #define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
68 #define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
69 #define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
70 #define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
71 #if defined(DMAMUX1_Channel5)
72 #define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
73 #endif /* DMAMUX1_Channel5 */
74 #if defined(DMAMUX1_Channel6)
75 #define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
76 #endif /* DMAMUX1_Channel6 */
77 #if defined(DMA2)
78 #define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
79 #define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
80 #define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
81 #define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
82 #define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
83 #endif /* DMA2 */
84 #define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
85 #define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
86 #define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
87 #define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
88 /**
89 * @}
90 */
91
92 /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
93 * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
94 * @{
95 */
96 #define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
97 #define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
98 #define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
99 #define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
100 #define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
101 #if defined(DMAMUX1_Channel5)
102 #define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
103 #endif /* DMAMUX1_Channel5 */
104 #if defined(DMAMUX1_Channel6)
105 #define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
106 #endif /* DMAMUX1_Channel6 */
107 #if defined(DMA2)
108 #define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
109 #define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
110 #define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
111 #define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
112 #define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
113 #endif /* DMA2 */
114 #define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
115 #define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
116 #define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
117 #define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
118 /**
119 * @}
120 */
121
122 /** @defgroup DMAMUX_LL_EC_IT IT Defines
123 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions
124 * @{
125 */
126 #define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
127 #define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
128 /**
129 * @}
130 */
131
132 /** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
133 * @{
134 */
135 #define LL_DMAMUX_REQ_MEM2MEM 0x00000000U /*!< memory to memory transfer */
136 #define LL_DMAMUX_REQ_GENERATOR0 0x00000001U /*!< DMAMUX request generator 0 */
137 #define LL_DMAMUX_REQ_GENERATOR1 0x00000002U /*!< DMAMUX request generator 1 */
138 #define LL_DMAMUX_REQ_GENERATOR2 0x00000003U /*!< DMAMUX request generator 2 */
139 #define LL_DMAMUX_REQ_GENERATOR3 0x00000004U /*!< DMAMUX request generator 3 */
140 #define LL_DMAMUX_REQ_ADC1 0x00000005U /*!< DMAMUX ADC1 request */
141 #if defined(AES)
142 #define LL_DMAMUX_REQ_AES_IN 0x00000006U /*!< DMAMUX AES_IN request */
143 #define LL_DMAMUX_REQ_AES_OUT 0x00000007U /*!< DMAMUX AES_OUT request */
144 #endif /* AES */
145 #if defined(DAC1)
146 #define LL_DMAMUX_REQ_DAC1_CH1 0x00000008U /*!< DMAMUX DAC_CH1 request */
147 #define LL_DMAMUX_REQ_DAC1_CH2 0x00000009U /*!< DMAMUX DAC_CH2 request */
148 #endif /* DAC1 */
149 #define LL_DMAMUX_REQ_I2C1_RX 0x0000000AU /*!< DMAMUX I2C1 RX request */
150 #define LL_DMAMUX_REQ_I2C1_TX 0x0000000BU /*!< DMAMUX I2C1 TX request */
151 #define LL_DMAMUX_REQ_I2C2_RX 0x0000000CU /*!< DMAMUX I2C2 RX request */
152 #define LL_DMAMUX_REQ_I2C2_TX 0x0000000DU /*!< DMAMUX I2C2 TX request */
153 #if defined(LPUART1)
154 #define LL_DMAMUX_REQ_LPUART1_RX 0x0000000EU /*!< DMAMUX LPUART1 RX request */
155 #define LL_DMAMUX_REQ_LPUART1_TX 0x0000000FU /*!< DMAMUX LPUART1 TX request */
156 #endif /* LPUART1 */
157 #define LL_DMAMUX_REQ_SPI1_RX 0x00000010U /*!< DMAMUX SPI1 RX request */
158 #define LL_DMAMUX_REQ_SPI1_TX 0x00000011U /*!< DMAMUX SPI1 TX request */
159 #define LL_DMAMUX_REQ_SPI2_RX 0x00000012U /*!< DMAMUX SPI2 RX request */
160 #define LL_DMAMUX_REQ_SPI2_TX 0x00000013U /*!< DMAMUX SPI2 TX request */
161 #define LL_DMAMUX_REQ_TIM1_CH1 0x00000014U /*!< DMAMUX TIM1 CH1 request */
162 #define LL_DMAMUX_REQ_TIM1_CH2 0x00000015U /*!< DMAMUX TIM1 CH2 request */
163 #define LL_DMAMUX_REQ_TIM1_CH3 0x00000016U /*!< DMAMUX TIM1 CH3 request */
164 #define LL_DMAMUX_REQ_TIM1_CH4 0x00000017U /*!< DMAMUX TIM1 CH4 request */
165 #define LL_DMAMUX_REQ_TIM1_TRIG_COM 0x00000018U /*!< DMAMUX TIM1 TRIG COM request */
166 #define LL_DMAMUX_REQ_TIM1_UP 0x00000019U /*!< DMAMUX TIM1 UP request */
167 #if defined(TIM2)
168 #define LL_DMAMUX_REQ_TIM2_CH1 0x0000001AU /*!< DMAMUX TIM2 CH1 request */
169 #define LL_DMAMUX_REQ_TIM2_CH2 0x0000001BU /*!< DMAMUX TIM2 CH2 request */
170 #define LL_DMAMUX_REQ_TIM2_CH3 0x0000001CU /*!< DMAMUX TIM2 CH3 request */
171 #define LL_DMAMUX_REQ_TIM2_CH4 0x0000001DU /*!< DMAMUX TIM2 CH4 request */
172 #define LL_DMAMUX_REQ_TIM2_TRIG 0x0000001EU /*!< DMAMUX TIM2 TRIG request */
173 #define LL_DMAMUX_REQ_TIM2_UP 0x0000001FU /*!< DMAMUX TIM2 UP request */
174 #endif /* TIM2 */
175 #define LL_DMAMUX_REQ_TIM3_CH1 0x00000020U /*!< DMAMUX TIM3 CH1 request */
176 #define LL_DMAMUX_REQ_TIM3_CH2 0x00000021U /*!< DMAMUX TIM3 CH2 request */
177 #define LL_DMAMUX_REQ_TIM3_CH3 0x00000022U /*!< DMAMUX TIM3 CH3 request */
178 #define LL_DMAMUX_REQ_TIM3_CH4 0x00000023U /*!< DMAMUX TIM3 CH4 request */
179 #define LL_DMAMUX_REQ_TIM3_TRIG 0x00000024U /*!< DMAMUX TIM3 TRIG request */
180 #define LL_DMAMUX_REQ_TIM3_UP 0x00000025U /*!< DMAMUX TIM3 UP request */
181 #if defined(TIM6)
182 #define LL_DMAMUX_REQ_TIM6_UP 0x00000026U /*!< DMAMUX TIM6 UP request */
183 #endif /* TIM6 */
184 #if defined(TIM7)
185 #define LL_DMAMUX_REQ_TIM7_UP 0x00000027U /*!< DMAMUX TIM7 UP request */
186 #endif /* TIM7 */
187 #if defined(TIM15)
188 #define LL_DMAMUX_REQ_TIM15_CH1 0x00000028U /*!< DMAMUX TIM15 CH1 request */
189 #define LL_DMAMUX_REQ_TIM15_CH2 0x00000029U /*!< DMAMUX TIM15 CH2 request */
190 #define LL_DMAMUX_REQ_TIM15_TRIG_COM 0x0000002AU /*!< DMAMUX TIM15 TRIG COM request */
191 #define LL_DMAMUX_REQ_TIM15_UP 0x0000002BU /*!< DMAMUX TIM15 UP request */
192 #endif /* TIM15 */
193 #define LL_DMAMUX_REQ_TIM16_CH1 0x0000002CU /*!< DMAMUX TIM16 CH1 request */
194 #define LL_DMAMUX_REQ_TIM16_COM 0x0000002DU /*!< DMAMUX TIM16 COM request */
195 #define LL_DMAMUX_REQ_TIM16_UP 0x0000002EU /*!< DMAMUX TIM16 UP request */
196 #define LL_DMAMUX_REQ_TIM17_CH1 0x0000002FU /*!< DMAMUX TIM17 CH1 request */
197 #define LL_DMAMUX_REQ_TIM17_COM 0x00000030U /*!< DMAMUX TIM17 COM request */
198 #define LL_DMAMUX_REQ_TIM17_UP 0x00000031U /*!< DMAMUX TIM17 UP request */
199 #define LL_DMAMUX_REQ_USART1_RX 0x00000032U /*!< DMAMUX USART1 RX request */
200 #define LL_DMAMUX_REQ_USART1_TX 0x00000033U /*!< DMAMUX USART1 TX request */
201 #define LL_DMAMUX_REQ_USART2_RX 0x00000034U /*!< DMAMUX USART2 RX request */
202 #define LL_DMAMUX_REQ_USART2_TX 0x00000035U /*!< DMAMUX USART2 TX request */
203 #if defined(USART3)
204 #define LL_DMAMUX_REQ_USART3_RX 0x00000036U /*!< DMAMUX USART3 RX request */
205 #define LL_DMAMUX_REQ_USART3_TX 0x00000037U /*!< DMAMUX USART3 TX request */
206 #endif /* USART3 */
207 #if defined(USART4)
208 #define LL_DMAMUX_REQ_USART4_RX 0x00000038U /*!< DMAMUX USART4 RX request */
209 #define LL_DMAMUX_REQ_USART4_TX 0x00000039U /*!< DMAMUX USART4 TX request */
210 #endif /* USART4 */
211 #if defined(UCPD1)
212 #define LL_DMAMUX_REQ_UCPD1_RX 0x0000003AU /*!< DMAMUX UCPD1 RX request */
213 #define LL_DMAMUX_REQ_UCPD1_TX 0x0000003BU /*!< DMAMUX UCPD1 TX request */
214 #endif /* UCPD1 */
215 #if defined(UCPD2)
216 #define LL_DMAMUX_REQ_UCPD2_RX 0x0000003CU /*!< DMAMUX UCPD2 RX request */
217 #define LL_DMAMUX_REQ_UCPD2_TX 0x0000003DU /*!< DMAMUX UCPD2 TX request */
218 #endif /* UCPD2 */
219
220 #if defined(I2C3)
221 #define LL_DMAMUX_REQ_I2C3_RX 0x0000003EU /*!< DMAMUX I2C3 RX request */
222 #define LL_DMAMUX_REQ_I2C3_TX 0x0000003FU /*!< DMAMUX I2C3 TX request */
223 #endif /* I2C3 */
224
225 #if defined(LPUART2)
226 #define LL_DMAMUX_REQ_LPUART2_RX 0x00000040U /*!< DMAMUX LPUART2 RX request */
227 #define LL_DMAMUX_REQ_LPUART2_TX 0x00000041U /*!< DMAMUX LPUART2 TX request */
228 #endif /* LPUART2 */
229
230 #if defined(SPI3)
231 #define LL_DMAMUX_REQ_SPI3_RX 0x00000042U /*!< DMAMUX SPI3 RX request */
232 #define LL_DMAMUX_REQ_SPI3_TX 0x00000043U /*!< DMAMUX SPI3 TX request */
233 #endif /* SPI3 */
234
235 #if defined(TIM4)
236 #define LL_DMAMUX_REQ_TIM4_CH1 0x00000044U /*!< DMAMUX TIM4 CH1 request */
237 #define LL_DMAMUX_REQ_TIM4_CH2 0x00000045U /*!< DMAMUX TIM4 CH2 request */
238 #define LL_DMAMUX_REQ_TIM4_CH3 0x00000046U /*!< DMAMUX TIM4 CH3 request */
239 #define LL_DMAMUX_REQ_TIM4_CH4 0x00000047U /*!< DMAMUX TIM4 CH4 request */
240 #define LL_DMAMUX_REQ_TIM4_TRIG 0x00000048U /*!< DMAMUX TIM4 TRIG request */
241 #define LL_DMAMUX_REQ_TIM4_UP 0x00000049U /*!< DMAMUX TIM4 UP request */
242 #endif /* TIM4 */
243
244 #if defined(USART5)
245 #define LL_DMAMUX_REQ_USART5_RX 0x0000004AU /*!< DMAMUX USART5 RX request */
246 #define LL_DMAMUX_REQ_USART5_TX 0x0000004BU /*!< DMAMUX USART5 TX request */
247 #endif /* USART5 */
248
249 #if defined(USART6)
250 #define LL_DMAMUX_REQ_USART6_RX 0x0000004CU /*!< DMAMUX USART6 RX request */
251 #define LL_DMAMUX_REQ_USART6_TX 0x0000004DU /*!< DMAMUX USART6 TX request */
252 #endif /* USART6 */
253
254 #if defined(STM32G0C1xx)||defined(STM32G0B1xx)
255 #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART6_TX
256 #elif defined(STM32G0B0xx)
257 #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART4_TX
258 #elif defined(STM32G081xx)||defined(STM32G071xx)
259 #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_UCPD2_TX
260 #elif defined(STM32G070xx)
261 #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART4_TX
262 #else
263 #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART2_TX
264 #endif /* STM32G0C1xx || STM32G0B1xx */
265 /**
266 * @}
267 */
268
269 /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
270 * @{
271 */
272 #define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */
273 #define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */
274 #define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */
275 #define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */
276 #define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */
277 #if defined(DMAMUX1_Channel5)
278 #define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */
279 #endif /* DMAMUX1_Channel5 */
280 #if defined(DMAMUX1_Channel6)
281 #define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */
282 #endif /* DMAMUX1_Channel6 */
283 #if defined(DMA2)
284 #define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */
285 #define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */
286 #define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */
287 #define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */
288 #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */
289 #endif /* DMA2 */
290 /**
291 * @}
292 */
293
294 /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
295 * @{
296 */
297 #define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
298 #define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
299 #define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
300 #define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
301 /**
302 * @}
303 */
304
305 /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
306 * @{
307 */
308 #define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */
309 #define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */
310 #define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */
311 #define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */
312 #define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */
313 #define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */
314 #define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */
315 #define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */
316 #define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */
317 #define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */
318 #define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */
319 #define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */
320 #define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */
321 #define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 3 */
322 #define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line1 4 */
323 #define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 5 */
324 #define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */
325 #define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */
326 #define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */
327 #define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */
328 #if defined(LPTIM1)
329 #define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */
330 #endif /* LPTIM1 */
331 #if defined(LPTIM2)
332 #define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */
333 #endif /* LPTIM2 */
334 #define LL_DMAMUX_SYNC_TIM14_OC (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from TIM14 OC */
335 /**
336 * @}
337 */
338
339 /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
340 * @{
341 */
342 #define LL_DMAMUX_REQ_GEN_0 0x00000000U
343 #define LL_DMAMUX_REQ_GEN_1 0x00000001U
344 #define LL_DMAMUX_REQ_GEN_2 0x00000002U
345 #define LL_DMAMUX_REQ_GEN_3 0x00000003U
346 /**
347 * @}
348 */
349
350 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
351 * @{
352 */
353 #define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */
354 #define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */
355 #define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */
356 #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */
357 /**
358 * @}
359 */
360
361 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
362 * @{
363 */
364 #define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */
365 #define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */
366 #define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */
367 #define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */
368 #define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */
369 #define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */
370 #define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */
371 #define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */
372 #define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */
373 #define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */
374 #define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */
375 #define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */
376 #define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */
377 #define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */
378 #define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */
379 #define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
380 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */
381 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */
382 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */
383 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */
384 #if defined(LPTIM1)
385 #define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */
386 #endif /* LPTIM1 */
387 #if defined(LPTIM2)
388 #define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */
389 #endif /* LPTIM2 */
390 #define LL_DMAMUX_REQ_GEN_TIM14_OC (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from TIM14 OC */
391 /**
392 * @}
393 */
394
395 /**
396 * @}
397 */
398
399 /* Exported macro ------------------------------------------------------------*/
400 /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
401 * @{
402 */
403
404 /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
405 * @{
406 */
407 /**
408 * @brief Write a value in DMAMUX register
409 * @param __INSTANCE__ DMAMUX Instance
410 * @param __REG__ Register to be written
411 * @param __VALUE__ Value to be written in the register
412 * @retval None
413 */
414 #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
415
416 /**
417 * @brief Read a value in DMAMUX register
418 * @param __INSTANCE__ DMAMUX Instance
419 * @param __REG__ Register to be read
420 * @retval Register value
421 */
422 #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
423 /**
424 * @}
425 */
426
427 /**
428 * @}
429 */
430
431 /* Exported functions --------------------------------------------------------*/
432 /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
433 * @{
434 */
435
436 /** @defgroup DMAMUX_LL_EF_Configuration Configuration
437 * @{
438 */
439 /**
440 * @brief Set DMAMUX request ID for DMAMUX Channel x.
441 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
442 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
443 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
444 * @param DMAMUXx DMAMUXx Instance
445 * @param Channel This parameter can be one of the following values:
446 * @arg @ref LL_DMAMUX_CHANNEL_0
447 * @arg @ref LL_DMAMUX_CHANNEL_1
448 * @arg @ref LL_DMAMUX_CHANNEL_2
449 * @arg @ref LL_DMAMUX_CHANNEL_3
450 * @arg @ref LL_DMAMUX_CHANNEL_4
451 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
452 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
453 *
454 * @arg All the next values are only available on chip which support DMA2:
455 * @arg @ref LL_DMAMUX_CHANNEL_7
456 * @arg @ref LL_DMAMUX_CHANNEL_8
457 * @arg @ref LL_DMAMUX_CHANNEL_9
458 * @arg @ref LL_DMAMUX_CHANNEL_10
459 * @arg @ref LL_DMAMUX_CHANNEL_11
460 * @param Request This parameter can be one of the following values:
461 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
462 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
463 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
464 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
465 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
466 * @arg @ref LL_DMAMUX_REQ_ADC1
467 * @arg @ref LL_DMAMUX_REQ_AES_IN
468 * @arg @ref LL_DMAMUX_REQ_AES_OUT
469 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
470 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
471 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
472 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
473 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
474 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
475 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
476 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
477 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
478 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
479 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
480 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
481 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
482 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
483 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
484 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
485 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
486 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
487 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
488 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
489 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
490 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
491 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
492 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
493 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
494 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
495 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
496 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
497 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
498 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
499 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
500 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
501 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
502 * @arg @ref LL_DMAMUX_REQ_TIM15_CH2
503 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
504 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
505 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
506 * @arg @ref LL_DMAMUX_REQ_TIM16_COM
507 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
508 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
509 * @arg @ref LL_DMAMUX_REQ_TIM17_COM
510 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
511 * @arg @ref LL_DMAMUX_REQ_USART1_RX
512 * @arg @ref LL_DMAMUX_REQ_USART1_TX
513 * @arg @ref LL_DMAMUX_REQ_USART2_RX
514 * @arg @ref LL_DMAMUX_REQ_USART2_TX
515 * @arg @ref LL_DMAMUX_REQ_USART3_RX
516 * @arg @ref LL_DMAMUX_REQ_USART3_TX
517 * @arg @ref LL_DMAMUX_REQ_USART4_RX
518 * @arg @ref LL_DMAMUX_REQ_USART4_TX
519 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
520 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
521 * @arg @ref LL_DMAMUX_REQ_UCPD2_RX
522 * @arg @ref LL_DMAMUX_REQ_UCPD2_TX
523 * @retval None
524 */
LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t Request)525 __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
526 {
527 (void)(DMAMUXx);
528 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
529 }
530
531 /**
532 * @brief Get DMAMUX request ID for DMAMUX Channel x.
533 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
534 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
535 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
536 * @param DMAMUXx DMAMUXx Instance
537 * @param Channel This parameter can be one of the following values:
538 * @arg @ref LL_DMAMUX_CHANNEL_0
539 * @arg @ref LL_DMAMUX_CHANNEL_1
540 * @arg @ref LL_DMAMUX_CHANNEL_2
541 * @arg @ref LL_DMAMUX_CHANNEL_3
542 * @arg @ref LL_DMAMUX_CHANNEL_4
543 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
544 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
545 *
546 * @arg All the next values are only available on chip which support DMA2:
547 * @arg @ref LL_DMAMUX_CHANNEL_7
548 * @arg @ref LL_DMAMUX_CHANNEL_8
549 * @arg @ref LL_DMAMUX_CHANNEL_9
550 * @arg @ref LL_DMAMUX_CHANNEL_10
551 * @arg @ref LL_DMAMUX_CHANNEL_11
552 * @retval Returned value can be one of the following values:
553 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
554 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
555 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
556 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
557 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
558 * @arg @ref LL_DMAMUX_REQ_ADC1
559 * @arg @ref LL_DMAMUX_REQ_AES_IN
560 * @arg @ref LL_DMAMUX_REQ_AES_OUT
561 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
562 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
563 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
564 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
565 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
566 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
567 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
568 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
569 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
570 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
571 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
572 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
573 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
574 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
575 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
576 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
577 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
578 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
579 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
580 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
581 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
582 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
583 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
584 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
585 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
586 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
587 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
588 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
589 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
590 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
591 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
592 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
593 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
594 * @arg @ref LL_DMAMUX_REQ_TIM15_CH2
595 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
596 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
597 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
598 * @arg @ref LL_DMAMUX_REQ_TIM16_COM
599 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
600 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
601 * @arg @ref LL_DMAMUX_REQ_TIM17_COM
602 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
603 * @arg @ref LL_DMAMUX_REQ_USART1_RX
604 * @arg @ref LL_DMAMUX_REQ_USART1_TX
605 * @arg @ref LL_DMAMUX_REQ_USART2_RX
606 * @arg @ref LL_DMAMUX_REQ_USART2_TX
607 * @arg @ref LL_DMAMUX_REQ_USART3_RX
608 * @arg @ref LL_DMAMUX_REQ_USART3_TX
609 * @arg @ref LL_DMAMUX_REQ_USART4_RX
610 * @arg @ref LL_DMAMUX_REQ_USART4_TX
611 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
612 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
613 * @arg @ref LL_DMAMUX_REQ_UCPD2_RX
614 * @arg @ref LL_DMAMUX_REQ_UCPD2_TX
615 */
LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)616 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
617 {
618 (void)(DMAMUXx);
619 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
620 }
621
622 /**
623 * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
624 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
625 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
626 * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
627 * @param DMAMUXx DMAMUXx Instance
628 * @param Channel This parameter can be one of the following values:
629 * @arg @ref LL_DMAMUX_CHANNEL_0
630 * @arg @ref LL_DMAMUX_CHANNEL_1
631 * @arg @ref LL_DMAMUX_CHANNEL_2
632 * @arg @ref LL_DMAMUX_CHANNEL_3
633 * @arg @ref LL_DMAMUX_CHANNEL_4
634 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
635 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
636 *
637 * @arg All the next values are only available on chip which support DMA2:
638 * @arg @ref LL_DMAMUX_CHANNEL_7
639 * @arg @ref LL_DMAMUX_CHANNEL_8
640 * @arg @ref LL_DMAMUX_CHANNEL_9
641 * @arg @ref LL_DMAMUX_CHANNEL_10
642 * @arg @ref LL_DMAMUX_CHANNEL_11
643 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
644 * @retval None
645 */
LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t RequestNb)646 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
647 {
648 (void)(DMAMUXx);
649 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
650 }
651
652 /**
653 * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
654 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
655 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
656 * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
657 * @param DMAMUXx DMAMUXx Instance
658 * @param Channel This parameter can be one of the following values:
659 * @arg @ref LL_DMAMUX_CHANNEL_0
660 * @arg @ref LL_DMAMUX_CHANNEL_1
661 * @arg @ref LL_DMAMUX_CHANNEL_2
662 * @arg @ref LL_DMAMUX_CHANNEL_3
663 * @arg @ref LL_DMAMUX_CHANNEL_4
664 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
665 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
666 *
667 * @arg All the next values are only available on chip which support DMA2:
668 * @arg @ref LL_DMAMUX_CHANNEL_7
669 * @arg @ref LL_DMAMUX_CHANNEL_8
670 * @arg @ref LL_DMAMUX_CHANNEL_9
671 * @arg @ref LL_DMAMUX_CHANNEL_10
672 * @arg @ref LL_DMAMUX_CHANNEL_11
673 * @retval Between Min_Data = 1 and Max_Data = 32
674 */
LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)675 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
676 {
677 (void)(DMAMUXx);
678 return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
679 }
680
681 /**
682 * @brief Set the polarity of the signal on which the DMA request is synchronized.
683 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
684 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
685 * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
686 * @param DMAMUXx DMAMUXx Instance
687 * @param Channel This parameter can be one of the following values:
688 * @arg @ref LL_DMAMUX_CHANNEL_0
689 * @arg @ref LL_DMAMUX_CHANNEL_1
690 * @arg @ref LL_DMAMUX_CHANNEL_2
691 * @arg @ref LL_DMAMUX_CHANNEL_3
692 * @arg @ref LL_DMAMUX_CHANNEL_4
693 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
694 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
695 *
696 * @arg All the next values are only available on chip which support DMA2:
697 * @arg @ref LL_DMAMUX_CHANNEL_7
698 * @arg @ref LL_DMAMUX_CHANNEL_8
699 * @arg @ref LL_DMAMUX_CHANNEL_9
700 * @arg @ref LL_DMAMUX_CHANNEL_10
701 * @arg @ref LL_DMAMUX_CHANNEL_11
702 * @param Polarity This parameter can be one of the following values:
703 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
704 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
705 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
706 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
707 * @retval None
708 */
LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t Polarity)709 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
710 {
711 (void)(DMAMUXx);
712 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
713 }
714
715 /**
716 * @brief Get the polarity of the signal on which the DMA request is synchronized.
717 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
718 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
719 * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
720 * @param DMAMUXx DMAMUXx Instance
721 * @param Channel This parameter can be one of the following values:
722 * @arg @ref LL_DMAMUX_CHANNEL_0
723 * @arg @ref LL_DMAMUX_CHANNEL_1
724 * @arg @ref LL_DMAMUX_CHANNEL_2
725 * @arg @ref LL_DMAMUX_CHANNEL_3
726 * @arg @ref LL_DMAMUX_CHANNEL_4
727 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
728 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
729 *
730 * @arg All the next values are only available on chip which support DMA2:
731 * @arg @ref LL_DMAMUX_CHANNEL_7
732 * @arg @ref LL_DMAMUX_CHANNEL_8
733 * @arg @ref LL_DMAMUX_CHANNEL_9
734 * @arg @ref LL_DMAMUX_CHANNEL_10
735 * @arg @ref LL_DMAMUX_CHANNEL_11
736 * @retval Returned value can be one of the following values:
737 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
738 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
739 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
740 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
741 */
LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)742 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
743 {
744 (void)(DMAMUXx);
745 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
746 }
747
748 /**
749 * @brief Enable the Event Generation on DMAMUX channel x.
750 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
751 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
752 * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
753 * @param DMAMUXx DMAMUXx Instance
754 * @param Channel This parameter can be one of the following values:
755 * @arg @ref LL_DMAMUX_CHANNEL_0
756 * @arg @ref LL_DMAMUX_CHANNEL_1
757 * @arg @ref LL_DMAMUX_CHANNEL_2
758 * @arg @ref LL_DMAMUX_CHANNEL_3
759 * @arg @ref LL_DMAMUX_CHANNEL_4
760 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
761 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
762 *
763 * @arg All the next values are only available on chip which support DMA2:
764 * @arg @ref LL_DMAMUX_CHANNEL_7
765 * @arg @ref LL_DMAMUX_CHANNEL_8
766 * @arg @ref LL_DMAMUX_CHANNEL_9
767 * @arg @ref LL_DMAMUX_CHANNEL_10
768 * @arg @ref LL_DMAMUX_CHANNEL_11
769 * @retval None
770 */
LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)771 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
772 {
773 (void)(DMAMUXx);
774 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
775 }
776
777 /**
778 * @brief Disable the Event Generation on DMAMUX channel x.
779 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
780 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
781 * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
782 * @param DMAMUXx DMAMUXx Instance
783 * @param Channel This parameter can be one of the following values:
784 * @arg @ref LL_DMAMUX_CHANNEL_0
785 * @arg @ref LL_DMAMUX_CHANNEL_1
786 * @arg @ref LL_DMAMUX_CHANNEL_2
787 * @arg @ref LL_DMAMUX_CHANNEL_3
788 * @arg @ref LL_DMAMUX_CHANNEL_4
789 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
790 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
791 *
792 * @arg All the next values are only available on chip which support DMA2:
793 * @arg @ref LL_DMAMUX_CHANNEL_7
794 * @arg @ref LL_DMAMUX_CHANNEL_8
795 * @arg @ref LL_DMAMUX_CHANNEL_9
796 * @arg @ref LL_DMAMUX_CHANNEL_10
797 * @arg @ref LL_DMAMUX_CHANNEL_11
798 * @retval None
799 */
LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)800 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
801 {
802 (void)(DMAMUXx);
803 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
804 }
805
806 /**
807 * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled.
808 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
809 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
810 * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
811 * @param DMAMUXx DMAMUXx Instance
812 * @param Channel This parameter can be one of the following values:
813 * @arg @ref LL_DMAMUX_CHANNEL_0
814 * @arg @ref LL_DMAMUX_CHANNEL_1
815 * @arg @ref LL_DMAMUX_CHANNEL_2
816 * @arg @ref LL_DMAMUX_CHANNEL_3
817 * @arg @ref LL_DMAMUX_CHANNEL_4
818 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
819 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
820 *
821 * @arg All the next values are only available on chip which support DMA2:
822 * @arg @ref LL_DMAMUX_CHANNEL_7
823 * @arg @ref LL_DMAMUX_CHANNEL_8
824 * @arg @ref LL_DMAMUX_CHANNEL_9
825 * @arg @ref LL_DMAMUX_CHANNEL_10
826 * @arg @ref LL_DMAMUX_CHANNEL_11
827 * @retval State of bit (1 or 0).
828 */
LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)829 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
830 {
831 (void)(DMAMUXx);
832 return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
833 }
834
835 /**
836 * @brief Enable the synchronization mode.
837 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
838 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
839 * @rmtoll CxCR SE LL_DMAMUX_EnableSync
840 * @param DMAMUXx DMAMUXx Instance
841 * @param Channel This parameter can be one of the following values:
842 * @arg @ref LL_DMAMUX_CHANNEL_0
843 * @arg @ref LL_DMAMUX_CHANNEL_1
844 * @arg @ref LL_DMAMUX_CHANNEL_2
845 * @arg @ref LL_DMAMUX_CHANNEL_3
846 * @arg @ref LL_DMAMUX_CHANNEL_4
847 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
848 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
849 *
850 * @arg All the next values are only available on chip which support DMA2:
851 * @arg @ref LL_DMAMUX_CHANNEL_7
852 * @arg @ref LL_DMAMUX_CHANNEL_8
853 * @arg @ref LL_DMAMUX_CHANNEL_9
854 * @arg @ref LL_DMAMUX_CHANNEL_10
855 * @arg @ref LL_DMAMUX_CHANNEL_11
856 * @retval None
857 */
LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)858 __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
859 {
860 (void)(DMAMUXx);
861 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
862 }
863
864 /**
865 * @brief Disable the synchronization mode.
866 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
867 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
868 * @rmtoll CxCR SE LL_DMAMUX_DisableSync
869 * @param DMAMUXx DMAMUXx Instance
870 * @param Channel This parameter can be one of the following values:
871 * @arg @ref LL_DMAMUX_CHANNEL_0
872 * @arg @ref LL_DMAMUX_CHANNEL_1
873 * @arg @ref LL_DMAMUX_CHANNEL_2
874 * @arg @ref LL_DMAMUX_CHANNEL_3
875 * @arg @ref LL_DMAMUX_CHANNEL_4
876 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
877 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
878 *
879 * @arg All the next values are only available on chip which support DMA2:
880 * @arg @ref LL_DMAMUX_CHANNEL_7
881 * @arg @ref LL_DMAMUX_CHANNEL_8
882 * @arg @ref LL_DMAMUX_CHANNEL_9
883 * @arg @ref LL_DMAMUX_CHANNEL_10
884 * @arg @ref LL_DMAMUX_CHANNEL_11
885 * @retval None
886 */
LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)887 __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
888 {
889 (void)(DMAMUXx);
890 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
891 }
892
893 /**
894 * @brief Check if the synchronization mode is enabled or disabled.
895 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
896 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
897 * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
898 * @param DMAMUXx DMAMUXx Instance
899 * @param Channel This parameter can be one of the following values:
900 * @arg @ref LL_DMAMUX_CHANNEL_0
901 * @arg @ref LL_DMAMUX_CHANNEL_1
902 * @arg @ref LL_DMAMUX_CHANNEL_2
903 * @arg @ref LL_DMAMUX_CHANNEL_3
904 * @arg @ref LL_DMAMUX_CHANNEL_4
905 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
906 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
907 *
908 * @arg All the next values are only available on chip which support DMA2:
909 * @arg @ref LL_DMAMUX_CHANNEL_7
910 * @arg @ref LL_DMAMUX_CHANNEL_8
911 * @arg @ref LL_DMAMUX_CHANNEL_9
912 * @arg @ref LL_DMAMUX_CHANNEL_10
913 * @arg @ref LL_DMAMUX_CHANNEL_11
914 * @retval State of bit (1 or 0).
915 */
LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)916 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
917 {
918 (void)(DMAMUXx);
919 return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
920 }
921
922 /**
923 * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
924 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
925 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
926 * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
927 * @param DMAMUXx DMAMUXx Instance
928 * @param Channel This parameter can be one of the following values:
929 * @arg @ref LL_DMAMUX_CHANNEL_0
930 * @arg @ref LL_DMAMUX_CHANNEL_1
931 * @arg @ref LL_DMAMUX_CHANNEL_2
932 * @arg @ref LL_DMAMUX_CHANNEL_3
933 * @arg @ref LL_DMAMUX_CHANNEL_4
934 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
935 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
936 *
937 * @arg All the next values are only available on chip which support DMA2:
938 * @arg @ref LL_DMAMUX_CHANNEL_7
939 * @arg @ref LL_DMAMUX_CHANNEL_8
940 * @arg @ref LL_DMAMUX_CHANNEL_9
941 * @arg @ref LL_DMAMUX_CHANNEL_10
942 * @arg @ref LL_DMAMUX_CHANNEL_11
943 * @param SyncID This parameter can be one of the following values:
944 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
945 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
946 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
947 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
948 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
949 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
950 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
951 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
952 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
953 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
954 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
955 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
956 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
957 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
958 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
959 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
960 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
961 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
962 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
963 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
964 * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
965 * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
966 * @arg @ref LL_DMAMUX_SYNC_TIM14_OC
967 * @retval None
968 */
LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t SyncID)969 __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
970 {
971 (void)(DMAMUXx);
972 MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
973 }
974
975 /**
976 * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
977 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
978 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
979 * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
980 * @param DMAMUXx DMAMUXx Instance
981 * @param Channel This parameter can be one of the following values:
982 * @arg @ref LL_DMAMUX_CHANNEL_0
983 * @arg @ref LL_DMAMUX_CHANNEL_1
984 * @arg @ref LL_DMAMUX_CHANNEL_2
985 * @arg @ref LL_DMAMUX_CHANNEL_3
986 * @arg @ref LL_DMAMUX_CHANNEL_4
987 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
988 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
989 *
990 * @arg All the next values are only available on chip which support DMA2:
991 * @arg @ref LL_DMAMUX_CHANNEL_7
992 * @arg @ref LL_DMAMUX_CHANNEL_8
993 * @arg @ref LL_DMAMUX_CHANNEL_9
994 * @arg @ref LL_DMAMUX_CHANNEL_10
995 * @arg @ref LL_DMAMUX_CHANNEL_11
996 * @retval Returned value can be one of the following values:
997 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
998 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
999 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
1000 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
1001 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
1002 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
1003 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
1004 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
1005 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
1006 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
1007 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
1008 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
1009 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
1010 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
1011 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
1012 * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
1013 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
1014 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
1015 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
1016 * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
1017 * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
1018 * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
1019 * @arg @ref LL_DMAMUX_SYNC_TIM14_OC
1020 */
LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1021 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1022 {
1023 (void)(DMAMUXx);
1024 return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
1025 }
1026
1027 /**
1028 * @brief Enable the Request Generator.
1029 * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
1030 * @param DMAMUXx DMAMUXx Instance
1031 * @param RequestGenChannel This parameter can be one of the following values:
1032 * @arg @ref LL_DMAMUX_REQ_GEN_0
1033 * @arg @ref LL_DMAMUX_REQ_GEN_1
1034 * @arg @ref LL_DMAMUX_REQ_GEN_2
1035 * @arg @ref LL_DMAMUX_REQ_GEN_3
1036 * @retval None
1037 */
LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1038 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1039 {
1040 (void)(DMAMUXx);
1041 SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
1042 }
1043
1044 /**
1045 * @brief Disable the Request Generator.
1046 * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
1047 * @param DMAMUXx DMAMUXx Instance
1048 * @param RequestGenChannel This parameter can be one of the following values:
1049 * @arg @ref LL_DMAMUX_REQ_GEN_0
1050 * @arg @ref LL_DMAMUX_REQ_GEN_1
1051 * @arg @ref LL_DMAMUX_REQ_GEN_2
1052 * @arg @ref LL_DMAMUX_REQ_GEN_3
1053 * @retval None
1054 */
LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1055 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1056 {
1057 (void)(DMAMUXx);
1058 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
1059 }
1060
1061 /**
1062 * @brief Check if the Request Generator is enabled or disabled.
1063 * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
1064 * @param DMAMUXx DMAMUXx Instance
1065 * @param RequestGenChannel This parameter can be one of the following values:
1066 * @arg @ref LL_DMAMUX_REQ_GEN_0
1067 * @arg @ref LL_DMAMUX_REQ_GEN_1
1068 * @arg @ref LL_DMAMUX_REQ_GEN_2
1069 * @arg @ref LL_DMAMUX_REQ_GEN_3
1070 * @retval State of bit (1 or 0).
1071 */
LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1072 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1073 {
1074 (void)(DMAMUXx);
1075 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
1076 }
1077
1078 /**
1079 * @brief Set the polarity of the signal on which the DMA request is generated.
1080 * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
1081 * @param DMAMUXx DMAMUXx Instance
1082 * @param RequestGenChannel This parameter can be one of the following values:
1083 * @arg @ref LL_DMAMUX_REQ_GEN_0
1084 * @arg @ref LL_DMAMUX_REQ_GEN_1
1085 * @arg @ref LL_DMAMUX_REQ_GEN_2
1086 * @arg @ref LL_DMAMUX_REQ_GEN_3
1087 * @param Polarity This parameter can be one of the following values:
1088 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1089 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1090 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1091 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1092 * @retval None
1093 */
LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t Polarity)1094 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
1095 {
1096 (void)(DMAMUXx);
1097 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
1098 }
1099
1100 /**
1101 * @brief Get the polarity of the signal on which the DMA request is generated.
1102 * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
1103 * @param DMAMUXx DMAMUXx Instance
1104 * @param RequestGenChannel This parameter can be one of the following values:
1105 * @arg @ref LL_DMAMUX_REQ_GEN_0
1106 * @arg @ref LL_DMAMUX_REQ_GEN_1
1107 * @arg @ref LL_DMAMUX_REQ_GEN_2
1108 * @arg @ref LL_DMAMUX_REQ_GEN_3
1109 * @retval Returned value can be one of the following values:
1110 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1111 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1112 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1113 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1114 */
LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1115 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1116 {
1117 (void)(DMAMUXx);
1118 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));
1119 }
1120
1121 /**
1122 * @brief Set the number of DMA request that will be autorized after a generation event.
1123 * @note This field can only be written when Generator is disabled.
1124 * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
1125 * @param DMAMUXx DMAMUXx Instance
1126 * @param RequestGenChannel This parameter can be one of the following values:
1127 * @arg @ref LL_DMAMUX_REQ_GEN_0
1128 * @arg @ref LL_DMAMUX_REQ_GEN_1
1129 * @arg @ref LL_DMAMUX_REQ_GEN_2
1130 * @arg @ref LL_DMAMUX_REQ_GEN_3
1131 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
1132 * @retval None
1133 */
LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t RequestNb)1134 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
1135 {
1136 (void)(DMAMUXx);
1137 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
1138 }
1139
1140 /**
1141 * @brief Get the number of DMA request that will be autorized after a generation event.
1142 * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
1143 * @param DMAMUXx DMAMUXx Instance
1144 * @param RequestGenChannel This parameter can be one of the following values:
1145 * @arg @ref LL_DMAMUX_REQ_GEN_0
1146 * @arg @ref LL_DMAMUX_REQ_GEN_1
1147 * @arg @ref LL_DMAMUX_REQ_GEN_2
1148 * @arg @ref LL_DMAMUX_REQ_GEN_3
1149 * @retval Between Min_Data = 1 and Max_Data = 32
1150 */
LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1151 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1152 {
1153 (void)(DMAMUXx);
1154 return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
1155 }
1156
1157 /**
1158 * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
1159 * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
1160 * @param DMAMUXx DMAMUXx Instance
1161 * @param RequestGenChannel This parameter can be one of the following values:
1162 * @arg @ref LL_DMAMUX_REQ_GEN_0
1163 * @arg @ref LL_DMAMUX_REQ_GEN_1
1164 * @arg @ref LL_DMAMUX_REQ_GEN_2
1165 * @arg @ref LL_DMAMUX_REQ_GEN_3
1166 * @param RequestSignalID This parameter can be one of the following values:
1167 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
1168 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
1169 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
1170 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
1171 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
1172 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
1173 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
1174 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
1175 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
1176 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
1177 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
1178 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
1179 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
1180 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
1181 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
1182 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
1183 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
1184 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
1185 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
1186 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
1187 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
1188 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
1189 * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC
1190 * @retval None
1191 */
LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t RequestSignalID)1192 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
1193 {
1194 (void)(DMAMUXx);
1195 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
1196 }
1197
1198 /**
1199 * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
1200 * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
1201 * @param DMAMUXx DMAMUXx Instance
1202 * @param RequestGenChannel This parameter can be one of the following values:
1203 * @arg @ref LL_DMAMUX_REQ_GEN_0
1204 * @arg @ref LL_DMAMUX_REQ_GEN_1
1205 * @arg @ref LL_DMAMUX_REQ_GEN_2
1206 * @arg @ref LL_DMAMUX_REQ_GEN_3
1207 * @retval Returned value can be one of the following values:
1208 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
1209 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
1210 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
1211 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
1212 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
1213 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
1214 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
1215 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
1216 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
1217 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
1218 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
1219 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
1220 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
1221 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
1222 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
1223 * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
1224 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
1225 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
1226 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
1227 * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
1228 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
1229 * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
1230 * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC
1231 */
LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1232 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1233 {
1234 (void)(DMAMUXx);
1235 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));
1236 }
1237
1238 /**
1239 * @}
1240 */
1241
1242 /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
1243 * @{
1244 */
1245
1246 /**
1247 * @brief Get Synchronization Event Overrun Flag Channel 0.
1248 * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
1249 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1250 * @retval State of bit (1 or 0).
1251 */
LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx)1252 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1253 {
1254 (void)(DMAMUXx);
1255 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
1256 }
1257
1258 /**
1259 * @brief Get Synchronization Event Overrun Flag Channel 1.
1260 * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
1261 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1262 * @retval State of bit (1 or 0).
1263 */
LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef * DMAMUXx)1264 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1265 {
1266 (void)(DMAMUXx);
1267 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
1268 }
1269
1270 /**
1271 * @brief Get Synchronization Event Overrun Flag Channel 2.
1272 * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
1273 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1274 * @retval State of bit (1 or 0).
1275 */
LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef * DMAMUXx)1276 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1277 {
1278 (void)(DMAMUXx);
1279 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
1280 }
1281
1282 /**
1283 * @brief Get Synchronization Event Overrun Flag Channel 3.
1284 * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
1285 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1286 * @retval State of bit (1 or 0).
1287 */
LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef * DMAMUXx)1288 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1289 {
1290 (void)(DMAMUXx);
1291 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
1292 }
1293
1294 /**
1295 * @brief Get Synchronization Event Overrun Flag Channel 4.
1296 * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
1297 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1298 * @retval State of bit (1 or 0).
1299 */
LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef * DMAMUXx)1300 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1301 {
1302 (void)(DMAMUXx);
1303 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
1304 }
1305
1306 #if defined(DMAMUX1_Channel5)
1307 /**
1308 * @brief Get Synchronization Event Overrun Flag Channel 5.
1309 * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
1310 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1311 * @retval State of bit (1 or 0).
1312 */
LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef * DMAMUXx)1313 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1314 {
1315 (void)(DMAMUXx);
1316 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
1317 }
1318
1319 #endif /* DMAMUX1_Channel5 */
1320 #if defined(DMAMUX1_Channel6)
1321 /**
1322 * @brief Get Synchronization Event Overrun Flag Channel 6.
1323 * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
1324 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1325 * @retval State of bit (1 or 0).
1326 */
LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef * DMAMUXx)1327 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1328 {
1329 (void)(DMAMUXx);
1330 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
1331 }
1332
1333 #endif /* DMAMUX1_Channel6 */
1334 #if defined(DMAMUX1_Channel7)
1335 /**
1336 * @brief Get Synchronization Event Overrun Flag Channel 7.
1337 * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
1338 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1339 * @retval State of bit (1 or 0).
1340 */
LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef * DMAMUXx)1341 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1342 {
1343 (void)(DMAMUXx);
1344 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
1345 }
1346
1347 #endif /* DMAMUX1_Channel7 */
1348 #if defined(DMAMUX1_Channel8)
1349 /**
1350 * @brief Get Synchronization Event Overrun Flag Channel 8.
1351 * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
1352 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1353 * @retval State of bit (1 or 0).
1354 */
LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef * DMAMUXx)1355 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
1356 {
1357 (void)(DMAMUXx);
1358 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
1359 }
1360
1361 #endif /* DMAMUX1_Channel8 */
1362 #if defined(DMAMUX1_Channel9)
1363 /**
1364 * @brief Get Synchronization Event Overrun Flag Channel 9.
1365 * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
1366 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1367 * @retval State of bit (1 or 0).
1368 */
LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef * DMAMUXx)1369 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
1370 {
1371 (void)(DMAMUXx);
1372 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
1373 }
1374
1375 #endif /* DMAMUX1_Channel9 */
1376 #if defined(DMAMUX1_Channel10)
1377 /**
1378 * @brief Get Synchronization Event Overrun Flag Channel 10.
1379 * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
1380 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1381 * @retval State of bit (1 or 0).
1382 */
LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef * DMAMUXx)1383 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
1384 {
1385 (void)(DMAMUXx);
1386 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
1387 }
1388
1389 #endif /* DMAMUX1_Channel10 */
1390 #if defined(DMAMUX1_Channel11)
1391 /**
1392 * @brief Get Synchronization Event Overrun Flag Channel 11.
1393 * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
1394 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1395 * @retval State of bit (1 or 0).
1396 */
LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef * DMAMUXx)1397 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
1398 {
1399 (void)(DMAMUXx);
1400 return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
1401 }
1402
1403 #endif /* DMAMUX1_Channel11 */
1404 /**
1405 * @brief Get Request Generator 0 Trigger Event Overrun Flag.
1406 * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
1407 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1408 * @retval State of bit (1 or 0).
1409 */
LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef * DMAMUXx)1410 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1411 {
1412 (void)(DMAMUXx);
1413 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
1414 }
1415
1416 /**
1417 * @brief Get Request Generator 1 Trigger Event Overrun Flag.
1418 * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
1419 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1420 * @retval State of bit (1 or 0).
1421 */
LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef * DMAMUXx)1422 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1423 {
1424 (void)(DMAMUXx);
1425 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
1426 }
1427
1428 /**
1429 * @brief Get Request Generator 2 Trigger Event Overrun Flag.
1430 * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
1431 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1432 * @retval State of bit (1 or 0).
1433 */
LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef * DMAMUXx)1434 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1435 {
1436 (void)(DMAMUXx);
1437 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
1438 }
1439
1440 /**
1441 * @brief Get Request Generator 3 Trigger Event Overrun Flag.
1442 * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
1443 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1444 * @retval State of bit (1 or 0).
1445 */
LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef * DMAMUXx)1446 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1447 {
1448 (void)(DMAMUXx);
1449 return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
1450 }
1451
1452 /**
1453 * @brief Clear Synchronization Event Overrun Flag Channel 0.
1454 * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
1455 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1456 * @retval None
1457 */
LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx)1458 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1459 {
1460 (void)(DMAMUXx);
1461 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
1462 }
1463
1464 /**
1465 * @brief Clear Synchronization Event Overrun Flag Channel 1.
1466 * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
1467 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1468 * @retval None
1469 */
LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef * DMAMUXx)1470 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1471 {
1472 (void)(DMAMUXx);
1473 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
1474 }
1475
1476 /**
1477 * @brief Clear Synchronization Event Overrun Flag Channel 2.
1478 * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
1479 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1480 * @retval None
1481 */
LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef * DMAMUXx)1482 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1483 {
1484 (void)(DMAMUXx);
1485 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
1486 }
1487
1488 /**
1489 * @brief Clear Synchronization Event Overrun Flag Channel 3.
1490 * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
1491 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1492 * @retval None
1493 */
LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef * DMAMUXx)1494 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1495 {
1496 (void)(DMAMUXx);
1497 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
1498 }
1499
1500 /**
1501 * @brief Clear Synchronization Event Overrun Flag Channel 4.
1502 * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
1503 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1504 * @retval None
1505 */
LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef * DMAMUXx)1506 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1507 {
1508 (void)(DMAMUXx);
1509 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
1510 }
1511
1512 #if defined(DMAMUX1_Channel5)
1513 /**
1514 * @brief Clear Synchronization Event Overrun Flag Channel 5.
1515 * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
1516 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1517 * @retval None
1518 */
LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef * DMAMUXx)1519 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1520 {
1521 (void)(DMAMUXx);
1522 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
1523 }
1524
1525 #endif /* DMAMUX1_Channel5 */
1526 #if defined(DMAMUX1_Channel6)
1527 /**
1528 * @brief Clear Synchronization Event Overrun Flag Channel 6.
1529 * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
1530 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1531 * @retval None
1532 */
LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef * DMAMUXx)1533 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1534 {
1535 (void)(DMAMUXx);
1536 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
1537 }
1538
1539 #endif /* DMAMUX1_Channel6 */
1540 #if defined(DMAMUX1_Channel7)
1541 /**
1542 * @brief Clear Synchronization Event Overrun Flag Channel 7.
1543 * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
1544 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1545 * @retval None
1546 */
LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef * DMAMUXx)1547 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1548 {
1549 (void)(DMAMUXx);
1550 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
1551 }
1552
1553 #endif /* DMAMUX1_Channel7 */
1554 #if defined(DMAMUX1_Channel8)
1555 /**
1556 * @brief Clear Synchronization Event Overrun Flag Channel 8.
1557 * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
1558 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1559 * @retval None
1560 */
LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef * DMAMUXx)1561 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
1562 {
1563 (void)(DMAMUXx);
1564 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
1565 }
1566
1567 #endif /* DMAMUX1_Channel8 */
1568 #if defined(DMAMUX1_Channel9)
1569 /**
1570 * @brief Clear Synchronization Event Overrun Flag Channel 9.
1571 * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
1572 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1573 * @retval None
1574 */
LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef * DMAMUXx)1575 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
1576 {
1577 (void)(DMAMUXx);
1578 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
1579 }
1580
1581 #endif /* DMAMUX1_Channel9 */
1582 #if defined(DMAMUX1_Channel10)
1583 /**
1584 * @brief Clear Synchronization Event Overrun Flag Channel 10.
1585 * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
1586 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1587 * @retval None
1588 */
LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef * DMAMUXx)1589 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
1590 {
1591 (void)(DMAMUXx);
1592 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
1593 }
1594
1595 #endif /* DMAMUX1_Channel10 */
1596 #if defined(DMAMUX1_Channel11)
1597 /**
1598 * @brief Clear Synchronization Event Overrun Flag Channel 11.
1599 * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
1600 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1601 * @retval None
1602 */
LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef * DMAMUXx)1603 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
1604 {
1605 (void)(DMAMUXx);
1606 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
1607 }
1608
1609 #endif /* DMAMUX1_Channel11 */
1610 /**
1611 * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
1612 * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
1613 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1614 * @retval None
1615 */
LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef * DMAMUXx)1616 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1617 {
1618 (void)(DMAMUXx);
1619 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
1620 }
1621
1622 /**
1623 * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
1624 * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
1625 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1626 * @retval None
1627 */
LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef * DMAMUXx)1628 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1629 {
1630 (void)(DMAMUXx);
1631 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
1632 }
1633
1634 /**
1635 * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
1636 * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
1637 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1638 * @retval None
1639 */
LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef * DMAMUXx)1640 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1641 {
1642 (void)(DMAMUXx);
1643 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
1644 }
1645
1646 /**
1647 * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
1648 * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
1649 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1650 * @retval None
1651 */
LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef * DMAMUXx)1652 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1653 {
1654 (void)(DMAMUXx);
1655 SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
1656 }
1657
1658 /**
1659 * @}
1660 */
1661
1662 /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
1663 * @{
1664 */
1665
1666 /**
1667 * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
1668 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1669 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
1670 * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
1671 * @param DMAMUXx DMAMUXx Instance
1672 * @param Channel This parameter can be one of the following values:
1673 * @arg @ref LL_DMAMUX_CHANNEL_0
1674 * @arg @ref LL_DMAMUX_CHANNEL_1
1675 * @arg @ref LL_DMAMUX_CHANNEL_2
1676 * @arg @ref LL_DMAMUX_CHANNEL_3
1677 * @arg @ref LL_DMAMUX_CHANNEL_4
1678 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
1679 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
1680 *
1681 * @arg All the next values are only available on chip which support DMA2:
1682 * @arg @ref LL_DMAMUX_CHANNEL_7
1683 * @arg @ref LL_DMAMUX_CHANNEL_8
1684 * @arg @ref LL_DMAMUX_CHANNEL_9
1685 * @arg @ref LL_DMAMUX_CHANNEL_10
1686 * @arg @ref LL_DMAMUX_CHANNEL_11
1687 * @retval None
1688 */
LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1689 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1690 {
1691 (void)(DMAMUXx);
1692 SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
1693 }
1694
1695 /**
1696 * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
1697 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1698 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
1699 * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
1700 * @param DMAMUXx DMAMUXx Instance
1701 * @param Channel This parameter can be one of the following values:
1702 * @arg @ref LL_DMAMUX_CHANNEL_0
1703 * @arg @ref LL_DMAMUX_CHANNEL_1
1704 * @arg @ref LL_DMAMUX_CHANNEL_2
1705 * @arg @ref LL_DMAMUX_CHANNEL_3
1706 * @arg @ref LL_DMAMUX_CHANNEL_4
1707 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
1708 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
1709 *
1710 * @arg All the next values are only available on chip which support DMA2:
1711 * @arg @ref LL_DMAMUX_CHANNEL_7
1712 * @arg @ref LL_DMAMUX_CHANNEL_8
1713 * @arg @ref LL_DMAMUX_CHANNEL_9
1714 * @arg @ref LL_DMAMUX_CHANNEL_10
1715 * @arg @ref LL_DMAMUX_CHANNEL_11
1716 * @retval None
1717 */
LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1718 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1719 {
1720 (void)(DMAMUXx);
1721 CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
1722 }
1723
1724 /**
1725 * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
1726 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1727 * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
1728 * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
1729 * @param DMAMUXx DMAMUXx Instance
1730 * @param Channel This parameter can be one of the following values:
1731 * @arg @ref LL_DMAMUX_CHANNEL_0
1732 * @arg @ref LL_DMAMUX_CHANNEL_1
1733 * @arg @ref LL_DMAMUX_CHANNEL_2
1734 * @arg @ref LL_DMAMUX_CHANNEL_3
1735 * @arg @ref LL_DMAMUX_CHANNEL_4
1736 * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
1737 * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
1738 *
1739 * @arg All the next values are only available on chip which support DMA2:
1740 * @arg @ref LL_DMAMUX_CHANNEL_7
1741 * @arg @ref LL_DMAMUX_CHANNEL_8
1742 * @arg @ref LL_DMAMUX_CHANNEL_9
1743 * @arg @ref LL_DMAMUX_CHANNEL_10
1744 * @arg @ref LL_DMAMUX_CHANNEL_11
1745 * @retval State of bit (1 or 0).
1746 */
LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1747 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1748 {
1749 (void)(DMAMUXx);
1750 return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL);
1751 }
1752
1753 /**
1754 * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
1755 * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
1756 * @param DMAMUXx DMAMUXx Instance
1757 * @param RequestGenChannel This parameter can be one of the following values:
1758 * @arg @ref LL_DMAMUX_REQ_GEN_0
1759 * @arg @ref LL_DMAMUX_REQ_GEN_1
1760 * @arg @ref LL_DMAMUX_REQ_GEN_2
1761 * @arg @ref LL_DMAMUX_REQ_GEN_3
1762 * @retval None
1763 */
LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1764 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1765 {
1766 (void)(DMAMUXx);
1767 SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
1768 }
1769
1770 /**
1771 * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
1772 * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
1773 * @param DMAMUXx DMAMUXx Instance
1774 * @param RequestGenChannel This parameter can be one of the following values:
1775 * @arg @ref LL_DMAMUX_REQ_GEN_0
1776 * @arg @ref LL_DMAMUX_REQ_GEN_1
1777 * @arg @ref LL_DMAMUX_REQ_GEN_2
1778 * @arg @ref LL_DMAMUX_REQ_GEN_3
1779 * @retval None
1780 */
LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1781 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1782 {
1783 (void)(DMAMUXx);
1784 CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
1785 }
1786
1787 /**
1788 * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
1789 * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
1790 * @param DMAMUXx DMAMUXx Instance
1791 * @param RequestGenChannel This parameter can be one of the following values:
1792 * @arg @ref LL_DMAMUX_REQ_GEN_0
1793 * @arg @ref LL_DMAMUX_REQ_GEN_1
1794 * @arg @ref LL_DMAMUX_REQ_GEN_2
1795 * @arg @ref LL_DMAMUX_REQ_GEN_3
1796 * @retval State of bit (1 or 0).
1797 */
LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1798 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1799 {
1800 (void)(DMAMUXx);
1801 return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
1802 }
1803
1804 /**
1805 * @}
1806 */
1807
1808 /**
1809 * @}
1810 */
1811
1812 /**
1813 * @}
1814 */
1815
1816 #endif /* DMAMUX1 */
1817
1818 /**
1819 * @}
1820 */
1821
1822 #ifdef __cplusplus
1823 }
1824 #endif
1825
1826 #endif /* STM32G0xx_LL_DMAMUX_H */
1827
1828 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1829
