1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L1xx_LL_DAC_H
22 #define STM32L1xx_LL_DAC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l1xx.h"
30
31 /** @addtogroup STM32L1xx_LL_Driver
32 * @{
33 */
34
35 #if defined(DAC1)
36
37 /** @defgroup DAC_LL DAC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
46 * @{
47 */
48
49 /* Internal masks for DAC channels definition */
50 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
51 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
52 /* - channel bits position into register SWTRIG */
53 /* - channel register offset of data holding register DHRx */
54 /* - channel register offset of data output register DORx */
55 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
56 CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 2 */
59 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
60
61 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
62 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
63 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
64
65 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
66 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
67 DHR12Rx channel 1 (shifted left of 20 bits) */
68 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
69 DHR12Rx channel 1 (shifted left of 24 bits) */
70
71 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
72 DHR12Rx channel 1 (shifted left of 16 bits) */
73 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
74 DHR12Rx channel 1 (shifted left of 20 bits) */
75 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
76 DHR12Rx channel 1 (shifted left of 24 bits) */
77
78 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
79 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
80 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
81 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
82 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
83
84 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
85
86 #define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
87 DORx channel 2 (shifted left of 28 bits) */
88 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
89
90
91
92 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
93 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
94 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
95 to position 0 */
96 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
97 to position 0 */
98
99 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
100 channel 1 or 2 versus DHR12Rx channel 1
101 (shifted left of 16 bits) */
102 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
103 channel 1 or 2 versus DHR12Rx channel 1
104 (shifted left of 20 bits) */
105 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
106 channel 1 or 2 versus DHR12Rx channel 1
107 (shifted left of 24 bits) */
108 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
109 channel 1 or 2 versus DORx channel 1
110 (shifted left of 28 bits) */
111
112 /* DAC registers bits positions */
113 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
114 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
115 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
116
117 /* Miscellaneous data */
118 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
119 bits (voltage range determined by analog voltage
120 references Vref+ and Vref-, refer to reference manual) */
121
122 /**
123 * @}
124 */
125
126
127 /* Private macros ------------------------------------------------------------*/
128 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
129 * @{
130 */
131
132 /**
133 * @brief Driver macro reserved for internal use: set a pointer to
134 * a register from a register basis from which an offset
135 * is applied.
136 * @param __REG__ Register basis from which the offset is applied.
137 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
138 * @retval Pointer to register address
139 */
140 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
141 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
142
143 /**
144 * @}
145 */
146
147
148 /* Exported types ------------------------------------------------------------*/
149 #if defined(USE_FULL_LL_DRIVER)
150 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
151 * @{
152 */
153
154 /**
155 * @brief Structure definition of some features of DAC instance.
156 */
157 typedef struct
158 {
159 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
160 internal (SW start) or from external peripheral
161 (timer event, external interrupt line).
162 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
163
164 This feature can be modified afterwards using unitary
165 function @ref LL_DAC_SetTriggerSource(). */
166
167 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
168 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
169
170 This feature can be modified afterwards using unitary
171 function @ref LL_DAC_SetWaveAutoGeneration(). */
172
173 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
174 If waveform automatic generation mode is set to noise, this parameter
175 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
176 If waveform automatic generation mode is set to triangle,
177 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
178 @note If waveform automatic generation mode is disabled,
179 this parameter is discarded.
180
181 This feature can be modified afterwards using unitary
182 function @ref LL_DAC_SetWaveNoiseLFSR(),
183 @ref LL_DAC_SetWaveTriangleAmplitude()
184 depending on the wave automatic generation selected. */
185
186 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
187 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
188
189 This feature can be modified afterwards using unitary
190 function @ref LL_DAC_SetOutputBuffer(). */
191 } LL_DAC_InitTypeDef;
192
193 /**
194 * @}
195 */
196 #endif /* USE_FULL_LL_DRIVER */
197
198 /* Exported constants --------------------------------------------------------*/
199 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
200 * @{
201 */
202
203 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
204 * @brief Flags defines which can be used with LL_DAC_ReadReg function
205 * @{
206 */
207 /* DAC channel 1 flags */
208 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
209
210 /* DAC channel 2 flags */
211 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
212
213 /**
214 * @}
215 */
216
217 /** @defgroup DAC_LL_EC_IT DAC interruptions
218 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
219 * @{
220 */
221 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
222
223 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
224
225 /**
226 * @}
227 */
228
229 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
230 * @{
231 */
232 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
233
234 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
235
236 /**
237 * @}
238 */
239
240 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
241 * @{
242 */
243 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
244 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
245 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
246 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
247 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
248 #define LL_DAC_TRIG_EXT_TIM9_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
249 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
250 /**
251 * @}
252 */
253
254 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
255 * @{
256 */
257 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
258 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
259 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
260 /**
261 * @}
262 */
263
264 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
265 * @{
266 */
267 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
268 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
269 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
270 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
271 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
272 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
273 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
274 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
275 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
276 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
277 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
278 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
279 /**
280 * @}
281 */
282
283 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
284 * @{
285 */
286 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
287 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
288 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
289 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
290 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
291 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
292 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
293 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
294 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
295 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
296 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
297 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
298 /**
299 * @}
300 */
301
302 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
303 * @{
304 */
305 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
306 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
307 /**
308 * @}
309 */
310
311 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
312 * @{
313 */
314 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
315 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
316 /**
317 * @}
318 */
319
320 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
321 * @{
322 */
323 /* List of DAC registers intended to be used (most commonly) with */
324 /* DMA transfer. */
325 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
326 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
327 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
328 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
329 /**
330 * @}
331 */
332
333 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
334 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
335 * not timeout values.
336 * For details on delays values, refer to descriptions in source code
337 * above each literal definition.
338 * @{
339 */
340
341 /* Delay for DAC channel voltage settling time from DAC channel startup */
342 /* (transition from disable to enable). */
343 /* Note: DAC channel startup time depends on board application environment: */
344 /* impedance connected to DAC channel output. */
345 /* The delay below is specified under conditions: */
346 /* - voltage maximum transition (lowest to highest value) */
347 /* - until voltage reaches final value +-1LSB */
348 /* - DAC channel output buffer enabled */
349 /* - load impedance of 5kOhm (min), 50pF (max) */
350 /* Literal set to maximum value (refer to device datasheet, */
351 /* parameter "tWAKEUP"). */
352 /* Unit: us */
353 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
354
355 /* Delay for DAC channel voltage settling time. */
356 /* Note: DAC channel startup time depends on board application environment: */
357 /* impedance connected to DAC channel output. */
358 /* The delay below is specified under conditions: */
359 /* - voltage maximum transition (lowest to highest value) */
360 /* - until voltage reaches final value +-1LSB */
361 /* - DAC channel output buffer enabled */
362 /* - load impedance of 5kOhm min, 50pF max */
363 /* Literal set to maximum value (refer to device datasheet, */
364 /* parameter "tSETTLING"). */
365 /* Unit: us */
366 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
367
368 /**
369 * @}
370 */
371
372 /**
373 * @}
374 */
375
376 /* Exported macro ------------------------------------------------------------*/
377 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
378 * @{
379 */
380
381 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
382 * @{
383 */
384
385 /**
386 * @brief Write a value in DAC register
387 * @param __INSTANCE__ DAC Instance
388 * @param __REG__ Register to be written
389 * @param __VALUE__ Value to be written in the register
390 * @retval None
391 */
392 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
393
394 /**
395 * @brief Read a value in DAC register
396 * @param __INSTANCE__ DAC Instance
397 * @param __REG__ Register to be read
398 * @retval Register value
399 */
400 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
401
402 /**
403 * @}
404 */
405
406 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
407 * @{
408 */
409
410 /**
411 * @brief Helper macro to get DAC channel number in decimal format
412 * from literals LL_DAC_CHANNEL_x.
413 * Example:
414 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
415 * will return decimal number "1".
416 * @note The input can be a value from functions where a channel
417 * number is returned.
418 * @param __CHANNEL__ This parameter can be one of the following values:
419 * @arg @ref LL_DAC_CHANNEL_1
420 * @arg @ref LL_DAC_CHANNEL_2
421 * @retval 1...2
422 */
423 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
424 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
425
426 /**
427 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
428 * from number in decimal format.
429 * Example:
430 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
431 * will return a data equivalent to "LL_DAC_CHANNEL_1".
432 * @note If the input parameter does not correspond to a DAC channel,
433 * this macro returns value '0'.
434 * @param __DECIMAL_NB__ 1...2
435 * @retval Returned value can be one of the following values:
436 * @arg @ref LL_DAC_CHANNEL_1
437 * @arg @ref LL_DAC_CHANNEL_2
438 */
439 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
440 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
441
442 /**
443 * @brief Helper macro to define the DAC conversion data full-scale digital
444 * value corresponding to the selected DAC resolution.
445 * @note DAC conversion data full-scale corresponds to voltage range
446 * determined by analog voltage references Vref+ and Vref-
447 * (refer to reference manual).
448 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
449 * @arg @ref LL_DAC_RESOLUTION_12B
450 * @arg @ref LL_DAC_RESOLUTION_8B
451 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
452 */
453 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
454 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
455
456 /**
457 * @brief Helper macro to calculate the DAC conversion data (unit: digital
458 * value) corresponding to a voltage (unit: mVolt).
459 * @note This helper macro is intended to provide input data in voltage
460 * rather than digital value,
461 * to be used with LL DAC functions such as
462 * @ref LL_DAC_ConvertData12RightAligned().
463 * @note Analog reference voltage (Vref+) must be either known from
464 * user board environment or can be calculated using ADC measurement
465 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
466 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
467 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
468 * (unit: mVolt).
469 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
470 * @arg @ref LL_DAC_RESOLUTION_12B
471 * @arg @ref LL_DAC_RESOLUTION_8B
472 * @retval DAC conversion data (unit: digital value)
473 */
474 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
475 __DAC_VOLTAGE__,\
476 __DAC_RESOLUTION__) \
477 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
478 / (__VREFANALOG_VOLTAGE__) \
479 )
480
481 /**
482 * @}
483 */
484
485 /**
486 * @}
487 */
488
489
490 /* Exported functions --------------------------------------------------------*/
491 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
492 * @{
493 */
494 /**
495 * @brief Set the conversion trigger source for the selected DAC channel.
496 * @note For conversion trigger source to be effective, DAC trigger
497 * must be enabled using function @ref LL_DAC_EnableTrigger().
498 * @note To set conversion trigger source, DAC channel must be disabled.
499 * Otherwise, the setting is discarded.
500 * @note Availability of parameters of trigger sources from timer
501 * depends on timers availability on the selected device.
502 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
503 * CR TSEL2 LL_DAC_SetTriggerSource
504 * @param DACx DAC instance
505 * @param DAC_Channel This parameter can be one of the following values:
506 * @arg @ref LL_DAC_CHANNEL_1
507 * @arg @ref LL_DAC_CHANNEL_2
508 * @param TriggerSource This parameter can be one of the following values:
509 * @arg @ref LL_DAC_TRIG_SOFTWARE
510 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
511 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
512 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
513 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
514 * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO
515 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
516 * @retval None
517 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)518 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
519 {
520 MODIFY_REG(DACx->CR,
521 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
522 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
523 }
524
525 /**
526 * @brief Get the conversion trigger source for the selected DAC channel.
527 * @note For conversion trigger source to be effective, DAC trigger
528 * must be enabled using function @ref LL_DAC_EnableTrigger().
529 * @note Availability of parameters of trigger sources from timer
530 * depends on timers availability on the selected device.
531 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
532 * CR TSEL2 LL_DAC_GetTriggerSource
533 * @param DACx DAC instance
534 * @param DAC_Channel This parameter can be one of the following values:
535 * @arg @ref LL_DAC_CHANNEL_1
536 * @arg @ref LL_DAC_CHANNEL_2
537 * @retval Returned value can be one of the following values:
538 * @arg @ref LL_DAC_TRIG_SOFTWARE
539 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
540 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
541 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
542 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
543 * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO
544 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
545 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)546 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
547 {
548 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
549 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
550 );
551 }
552
553 /**
554 * @brief Set the waveform automatic generation mode
555 * for the selected DAC channel.
556 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
557 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
558 * @param DACx DAC instance
559 * @param DAC_Channel This parameter can be one of the following values:
560 * @arg @ref LL_DAC_CHANNEL_1
561 * @arg @ref LL_DAC_CHANNEL_2
562 * @param WaveAutoGeneration This parameter can be one of the following values:
563 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
564 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
565 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
566 * @retval None
567 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)568 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
569 {
570 MODIFY_REG(DACx->CR,
571 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
572 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
573 }
574
575 /**
576 * @brief Get the waveform automatic generation mode
577 * for the selected DAC channel.
578 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
579 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
580 * @param DACx DAC instance
581 * @param DAC_Channel This parameter can be one of the following values:
582 * @arg @ref LL_DAC_CHANNEL_1
583 * @arg @ref LL_DAC_CHANNEL_2
584 * @retval Returned value can be one of the following values:
585 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
586 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
587 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
588 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)589 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
590 {
591 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
592 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
593 );
594 }
595
596 /**
597 * @brief Set the noise waveform generation for the selected DAC channel:
598 * Noise mode and parameters LFSR (linear feedback shift register).
599 * @note For wave generation to be effective, DAC channel
600 * wave generation mode must be enabled using
601 * function @ref LL_DAC_SetWaveAutoGeneration().
602 * @note This setting can be set when the selected DAC channel is disabled
603 * (otherwise, the setting operation is ignored).
604 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
605 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
606 * @param DACx DAC instance
607 * @param DAC_Channel This parameter can be one of the following values:
608 * @arg @ref LL_DAC_CHANNEL_1
609 * @arg @ref LL_DAC_CHANNEL_2
610 * @param NoiseLFSRMask This parameter can be one of the following values:
611 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
612 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
613 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
614 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
615 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
616 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
617 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
618 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
619 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
620 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
621 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
622 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
623 * @retval None
624 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)625 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
626 {
627 MODIFY_REG(DACx->CR,
628 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
629 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
630 }
631
632 /**
633 * @brief Get the noise waveform generation for the selected DAC channel:
634 * Noise mode and parameters LFSR (linear feedback shift register).
635 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
636 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
637 * @param DACx DAC instance
638 * @param DAC_Channel This parameter can be one of the following values:
639 * @arg @ref LL_DAC_CHANNEL_1
640 * @arg @ref LL_DAC_CHANNEL_2
641 * @retval Returned value can be one of the following values:
642 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
643 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
644 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
645 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
646 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
647 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
648 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
649 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
650 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
651 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
652 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
653 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
654 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)655 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
656 {
657 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
658 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
659 );
660 }
661
662 /**
663 * @brief Set the triangle waveform generation for the selected DAC channel:
664 * triangle mode and amplitude.
665 * @note For wave generation to be effective, DAC channel
666 * wave generation mode must be enabled using
667 * function @ref LL_DAC_SetWaveAutoGeneration().
668 * @note This setting can be set when the selected DAC channel is disabled
669 * (otherwise, the setting operation is ignored).
670 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
671 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
672 * @param DACx DAC instance
673 * @param DAC_Channel This parameter can be one of the following values:
674 * @arg @ref LL_DAC_CHANNEL_1
675 * @arg @ref LL_DAC_CHANNEL_2
676 * @param TriangleAmplitude This parameter can be one of the following values:
677 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
678 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
679 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
680 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
681 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
682 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
683 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
684 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
685 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
686 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
687 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
688 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
689 * @retval None
690 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)691 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
692 uint32_t TriangleAmplitude)
693 {
694 MODIFY_REG(DACx->CR,
695 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
696 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
697 }
698
699 /**
700 * @brief Get the triangle waveform generation for the selected DAC channel:
701 * triangle mode and amplitude.
702 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
703 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
704 * @param DACx DAC instance
705 * @param DAC_Channel This parameter can be one of the following values:
706 * @arg @ref LL_DAC_CHANNEL_1
707 * @arg @ref LL_DAC_CHANNEL_2
708 * @retval Returned value can be one of the following values:
709 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
710 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
711 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
712 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
713 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
714 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
715 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
716 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
717 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
718 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
719 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
720 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
721 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)722 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
723 {
724 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
725 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
726 );
727 }
728
729 /**
730 * @brief Set the output buffer for the selected DAC channel.
731 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
732 * CR BOFF2 LL_DAC_SetOutputBuffer
733 * @param DACx DAC instance
734 * @param DAC_Channel This parameter can be one of the following values:
735 * @arg @ref LL_DAC_CHANNEL_1
736 * @arg @ref LL_DAC_CHANNEL_2
737 * @param OutputBuffer This parameter can be one of the following values:
738 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
739 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
740 * @retval None
741 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)742 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
743 {
744 MODIFY_REG(DACx->CR,
745 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
746 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
747 }
748
749 /**
750 * @brief Get the output buffer state for the selected DAC channel.
751 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
752 * CR BOFF2 LL_DAC_GetOutputBuffer
753 * @param DACx DAC instance
754 * @param DAC_Channel This parameter can be one of the following values:
755 * @arg @ref LL_DAC_CHANNEL_1
756 * @arg @ref LL_DAC_CHANNEL_2
757 * @retval Returned value can be one of the following values:
758 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
759 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
760 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)761 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
762 {
763 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
764 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
765 );
766 }
767
768 /**
769 * @}
770 */
771
772 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
773 * @{
774 */
775
776 /**
777 * @brief Enable DAC DMA transfer request of the selected channel.
778 * @note To configure DMA source address (peripheral address),
779 * use function @ref LL_DAC_DMA_GetRegAddr().
780 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
781 * CR DMAEN2 LL_DAC_EnableDMAReq
782 * @param DACx DAC instance
783 * @param DAC_Channel This parameter can be one of the following values:
784 * @arg @ref LL_DAC_CHANNEL_1
785 * @arg @ref LL_DAC_CHANNEL_2
786 * @retval None
787 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)788 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
789 {
790 SET_BIT(DACx->CR,
791 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
792 }
793
794 /**
795 * @brief Disable DAC DMA transfer request of the selected channel.
796 * @note To configure DMA source address (peripheral address),
797 * use function @ref LL_DAC_DMA_GetRegAddr().
798 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
799 * CR DMAEN2 LL_DAC_DisableDMAReq
800 * @param DACx DAC instance
801 * @param DAC_Channel This parameter can be one of the following values:
802 * @arg @ref LL_DAC_CHANNEL_1
803 * @arg @ref LL_DAC_CHANNEL_2
804 * @retval None
805 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)806 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
807 {
808 CLEAR_BIT(DACx->CR,
809 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
810 }
811
812 /**
813 * @brief Get DAC DMA transfer request state of the selected channel.
814 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
815 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
816 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
817 * @param DACx DAC instance
818 * @param DAC_Channel This parameter can be one of the following values:
819 * @arg @ref LL_DAC_CHANNEL_1
820 * @arg @ref LL_DAC_CHANNEL_2
821 * @retval State of bit (1 or 0).
822 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)823 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
824 {
825 return ((READ_BIT(DACx->CR,
826 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
827 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
828 }
829
830 /**
831 * @brief Function to help to configure DMA transfer to DAC: retrieve the
832 * DAC register address from DAC instance and a list of DAC registers
833 * intended to be used (most commonly) with DMA transfer.
834 * @note These DAC registers are data holding registers:
835 * when DAC conversion is requested, DAC generates a DMA transfer
836 * request to have data available in DAC data holding registers.
837 * @note This macro is intended to be used with LL DMA driver, refer to
838 * function "LL_DMA_ConfigAddresses()".
839 * Example:
840 * LL_DMA_ConfigAddresses(DMA1,
841 * LL_DMA_CHANNEL_1,
842 * (uint32_t)&< array or variable >,
843 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
844 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
845 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
846 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
847 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
848 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
849 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
850 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
851 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
852 * @param DACx DAC instance
853 * @param DAC_Channel This parameter can be one of the following values:
854 * @arg @ref LL_DAC_CHANNEL_1
855 * @arg @ref LL_DAC_CHANNEL_2
856 * @param Register This parameter can be one of the following values:
857 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
858 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
859 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
860 * @retval DAC register address
861 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)862 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
863 {
864 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
865 /* DAC channel selected. */
866 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
867 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
868 }
869 /**
870 * @}
871 */
872
873 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
874 * @{
875 */
876
877 /**
878 * @brief Enable DAC selected channel.
879 * @rmtoll CR EN1 LL_DAC_Enable\n
880 * CR EN2 LL_DAC_Enable
881 * @note After enable from off state, DAC channel requires a delay
882 * for output voltage to reach accuracy +/- 1 LSB.
883 * Refer to device datasheet, parameter "tWAKEUP".
884 * @param DACx DAC instance
885 * @param DAC_Channel This parameter can be one of the following values:
886 * @arg @ref LL_DAC_CHANNEL_1
887 * @arg @ref LL_DAC_CHANNEL_2
888 * @retval None
889 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)890 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
891 {
892 SET_BIT(DACx->CR,
893 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
894 }
895
896 /**
897 * @brief Disable DAC selected channel.
898 * @rmtoll CR EN1 LL_DAC_Disable\n
899 * CR EN2 LL_DAC_Disable
900 * @param DACx DAC instance
901 * @param DAC_Channel This parameter can be one of the following values:
902 * @arg @ref LL_DAC_CHANNEL_1
903 * @arg @ref LL_DAC_CHANNEL_2
904 * @retval None
905 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)906 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
907 {
908 CLEAR_BIT(DACx->CR,
909 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
910 }
911
912 /**
913 * @brief Get DAC enable state of the selected channel.
914 * (0: DAC channel is disabled, 1: DAC channel is enabled)
915 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
916 * CR EN2 LL_DAC_IsEnabled
917 * @param DACx DAC instance
918 * @param DAC_Channel This parameter can be one of the following values:
919 * @arg @ref LL_DAC_CHANNEL_1
920 * @arg @ref LL_DAC_CHANNEL_2
921 * @retval State of bit (1 or 0).
922 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)923 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
924 {
925 return ((READ_BIT(DACx->CR,
926 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
927 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
928 }
929
930 /**
931 * @brief Enable DAC trigger of the selected channel.
932 * @note - If DAC trigger is disabled, DAC conversion is performed
933 * automatically once the data holding register is updated,
934 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
935 * @ref LL_DAC_ConvertData12RightAligned(), ...
936 * - If DAC trigger is enabled, DAC conversion is performed
937 * only when a hardware of software trigger event is occurring.
938 * Select trigger source using
939 * function @ref LL_DAC_SetTriggerSource().
940 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
941 * CR TEN2 LL_DAC_EnableTrigger
942 * @param DACx DAC instance
943 * @param DAC_Channel This parameter can be one of the following values:
944 * @arg @ref LL_DAC_CHANNEL_1
945 * @arg @ref LL_DAC_CHANNEL_2
946 * @retval None
947 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)948 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
949 {
950 SET_BIT(DACx->CR,
951 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
952 }
953
954 /**
955 * @brief Disable DAC trigger of the selected channel.
956 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
957 * CR TEN2 LL_DAC_DisableTrigger
958 * @param DACx DAC instance
959 * @param DAC_Channel This parameter can be one of the following values:
960 * @arg @ref LL_DAC_CHANNEL_1
961 * @arg @ref LL_DAC_CHANNEL_2
962 * @retval None
963 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)964 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
965 {
966 CLEAR_BIT(DACx->CR,
967 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
968 }
969
970 /**
971 * @brief Get DAC trigger state of the selected channel.
972 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
973 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
974 * CR TEN2 LL_DAC_IsTriggerEnabled
975 * @param DACx DAC instance
976 * @param DAC_Channel This parameter can be one of the following values:
977 * @arg @ref LL_DAC_CHANNEL_1
978 * @arg @ref LL_DAC_CHANNEL_2
979 * @retval State of bit (1 or 0).
980 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)981 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
982 {
983 return ((READ_BIT(DACx->CR,
984 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
985 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
986 }
987
988 /**
989 * @brief Trig DAC conversion by software for the selected DAC channel.
990 * @note Preliminarily, DAC trigger must be set to software trigger
991 * using function
992 * @ref LL_DAC_Init()
993 * @ref LL_DAC_SetTriggerSource()
994 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
995 * and DAC trigger must be enabled using
996 * function @ref LL_DAC_EnableTrigger().
997 * @note For devices featuring DAC with 2 channels: this function
998 * can perform a SW start of both DAC channels simultaneously.
999 * Two channels can be selected as parameter.
1000 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1001 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1002 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1003 * @param DACx DAC instance
1004 * @param DAC_Channel This parameter can a combination of the following values:
1005 * @arg @ref LL_DAC_CHANNEL_1
1006 * @arg @ref LL_DAC_CHANNEL_2
1007 * @retval None
1008 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1009 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1010 {
1011 SET_BIT(DACx->SWTRIGR,
1012 (DAC_Channel & DAC_SWTR_CHX_MASK));
1013 }
1014
1015 /**
1016 * @brief Set the data to be loaded in the data holding register
1017 * in format 12 bits left alignment (LSB aligned on bit 0),
1018 * for the selected DAC channel.
1019 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1020 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1021 * @param DACx DAC instance
1022 * @param DAC_Channel This parameter can be one of the following values:
1023 * @arg @ref LL_DAC_CHANNEL_1
1024 * @arg @ref LL_DAC_CHANNEL_2
1025 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1026 * @retval None
1027 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1028 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1029 {
1030 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1031 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1032
1033 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1034 }
1035
1036 /**
1037 * @brief Set the data to be loaded in the data holding register
1038 * in format 12 bits left alignment (MSB aligned on bit 15),
1039 * for the selected DAC channel.
1040 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1041 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1042 * @param DACx DAC instance
1043 * @param DAC_Channel This parameter can be one of the following values:
1044 * @arg @ref LL_DAC_CHANNEL_1
1045 * @arg @ref LL_DAC_CHANNEL_2
1046 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1047 * @retval None
1048 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1049 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1050 {
1051 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1052 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1053
1054 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1055 }
1056
1057 /**
1058 * @brief Set the data to be loaded in the data holding register
1059 * in format 8 bits left alignment (LSB aligned on bit 0),
1060 * for the selected DAC channel.
1061 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1062 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1063 * @param DACx DAC instance
1064 * @param DAC_Channel This parameter can be one of the following values:
1065 * @arg @ref LL_DAC_CHANNEL_1
1066 * @arg @ref LL_DAC_CHANNEL_2
1067 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1068 * @retval None
1069 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1070 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1071 {
1072 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1073 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1074
1075 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1076 }
1077
1078
1079 /**
1080 * @brief Set the data to be loaded in the data holding register
1081 * in format 12 bits left alignment (LSB aligned on bit 0),
1082 * for both DAC channels.
1083 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1084 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1085 * @param DACx DAC instance
1086 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1087 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1088 * @retval None
1089 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1090 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1091 uint32_t DataChannel2)
1092 {
1093 MODIFY_REG(DACx->DHR12RD,
1094 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1095 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1096 }
1097
1098 /**
1099 * @brief Set the data to be loaded in the data holding register
1100 * in format 12 bits left alignment (MSB aligned on bit 15),
1101 * for both DAC channels.
1102 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1103 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1104 * @param DACx DAC instance
1105 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1106 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1107 * @retval None
1108 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1109 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1110 uint32_t DataChannel2)
1111 {
1112 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1113 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1114 /* the 4 LSB must be taken into account for the shift value. */
1115 MODIFY_REG(DACx->DHR12LD,
1116 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1117 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1118 }
1119
1120 /**
1121 * @brief Set the data to be loaded in the data holding register
1122 * in format 8 bits left alignment (LSB aligned on bit 0),
1123 * for both DAC channels.
1124 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1125 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1126 * @param DACx DAC instance
1127 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1128 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1129 * @retval None
1130 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1131 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1132 uint32_t DataChannel2)
1133 {
1134 MODIFY_REG(DACx->DHR8RD,
1135 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1136 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1137 }
1138
1139
1140 /**
1141 * @brief Retrieve output data currently generated for the selected DAC channel.
1142 * @note Whatever alignment and resolution settings
1143 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1144 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1145 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1146 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1147 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1148 * @param DACx DAC instance
1149 * @param DAC_Channel This parameter can be one of the following values:
1150 * @arg @ref LL_DAC_CHANNEL_1
1151 * @arg @ref LL_DAC_CHANNEL_2
1152 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1153 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1154 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1155 {
1156 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1157 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1158
1159 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1160 }
1161
1162 /**
1163 * @}
1164 */
1165
1166 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1167 * @{
1168 */
1169
1170 /**
1171 * @brief Get DAC underrun flag for DAC channel 1
1172 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1173 * @param DACx DAC instance
1174 * @retval State of bit (1 or 0).
1175 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1176 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1177 {
1178 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1179 }
1180
1181
1182 /**
1183 * @brief Get DAC underrun flag for DAC channel 2
1184 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1185 * @param DACx DAC instance
1186 * @retval State of bit (1 or 0).
1187 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1188 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1189 {
1190 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1191 }
1192
1193
1194 /**
1195 * @brief Clear DAC underrun flag for DAC channel 1
1196 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1197 * @param DACx DAC instance
1198 * @retval None
1199 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1200 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1201 {
1202 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1203 }
1204
1205
1206 /**
1207 * @brief Clear DAC underrun flag for DAC channel 2
1208 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1209 * @param DACx DAC instance
1210 * @retval None
1211 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1212 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1213 {
1214 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1215 }
1216
1217
1218 /**
1219 * @}
1220 */
1221
1222 /** @defgroup DAC_LL_EF_IT_Management IT management
1223 * @{
1224 */
1225
1226 /**
1227 * @brief Enable DMA underrun interrupt for DAC channel 1
1228 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1229 * @param DACx DAC instance
1230 * @retval None
1231 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1232 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1233 {
1234 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1235 }
1236
1237
1238 /**
1239 * @brief Enable DMA underrun interrupt for DAC channel 2
1240 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1241 * @param DACx DAC instance
1242 * @retval None
1243 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1244 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1245 {
1246 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1247 }
1248
1249
1250 /**
1251 * @brief Disable DMA underrun interrupt for DAC channel 1
1252 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1253 * @param DACx DAC instance
1254 * @retval None
1255 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1256 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1257 {
1258 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1259 }
1260
1261
1262 /**
1263 * @brief Disable DMA underrun interrupt for DAC channel 2
1264 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1265 * @param DACx DAC instance
1266 * @retval None
1267 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1268 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1269 {
1270 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1271 }
1272
1273
1274 /**
1275 * @brief Get DMA underrun interrupt for DAC channel 1
1276 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1277 * @param DACx DAC instance
1278 * @retval State of bit (1 or 0).
1279 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1280 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1281 {
1282 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1283 }
1284
1285
1286 /**
1287 * @brief Get DMA underrun interrupt for DAC channel 2
1288 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1289 * @param DACx DAC instance
1290 * @retval State of bit (1 or 0).
1291 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1292 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1293 {
1294 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1295 }
1296
1297
1298 /**
1299 * @}
1300 */
1301
1302 #if defined(USE_FULL_LL_DRIVER)
1303 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1304 * @{
1305 */
1306
1307 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1308 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
1309 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1310
1311 /**
1312 * @}
1313 */
1314 #endif /* USE_FULL_LL_DRIVER */
1315
1316 /**
1317 * @}
1318 */
1319
1320 /**
1321 * @}
1322 */
1323
1324 #endif /* DAC1 */
1325
1326 /**
1327 * @}
1328 */
1329
1330 #ifdef __cplusplus
1331 }
1332 #endif
1333
1334 #endif /* STM32L1xx_LL_DAC_H */
1335
1336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1337
