1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G4xx_LL_DAC_H
21 #define STM32G4xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR, STMODR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel bits position into register SWTRIGB */
53 /* - channel register offset of data holding register DHRx */
54 /* - channel register offset of data output register DORx */
55 /* - channel register offset of sample-and-hold sample time register SHSRx */
56 /* - channel register offset of sawtooth register STRx */
57 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */
59 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
60 CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */
61 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
62
63 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
64 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
65 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
66
67 #define DAC_SWTRB_CH1 (DAC_SWTRIGR_SWTRIGB1) /* Channel bit into register SWTRIGRB of channel 1.*/
68 #define DAC_SWTRB_CH2 (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/
69 #define DAC_SWTRB_CHX_MASK (DAC_SWTRB_CH1 | DAC_SWTRB_CH2)
70
71 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
72 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
73 DHR12Rx channel 1 (shifted left of 20 bits) */
74 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
75 DHR12Rx channel 1 (shifted left of 24 bits) */
76
77 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
78 DHR12Rx channel 1 (shifted left of 28 bits) */
79 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
80 DHR12Rx channel 1 (shifted left of 20 bits) */
81 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
82 DHR12Rx channel 1 (shifted left of 24 bits) */
83
84 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
85 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
86 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
87 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
88 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
89
90 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
91
92 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
93 DORx channel 2 (shifted left of 5 bits) */
94 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
95
96 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
97 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
98 SHSRx channel 2 (shifted left of 6 bits) */
99 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
100
101 #define DAC_REG_STR1_REGOFFSET 0x00000000UL /* Register STRx channel 1 taken as reference */
102 #define DAC_REG_STR2_REGOFFSET 0x00000080UL /* Register offset of STRx channel 1 versus
103 STRx channel 2 (shifted left of 7 bits) */
104 #define DAC_REG_STRX_REGOFFSET_MASK (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET)
105
106 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
107 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
108 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
109 to position 0 */
110 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
111 to position 0 */
112 #define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of STRx registers offset when shifted
113 to position 0 */
114
115 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
116 channel 1 or 2 versus DHR12Rx channel 1
117 (shifted left of 28 bits) */
118 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
119 channel 1 or 2 versus DHR12Rx channel 1
120 (shifted left of 20 bits) */
121 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
122 channel 1 or 2 versus DHR12Rx channel 1
123 (shifted left of 24 bits) */
124 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
125 channel 1 or 2 versus DORx channel 1
126 (shifted left of 5 bits) */
127 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
128 channel 1 or 2 versus SHSRx channel 1
129 (shifted left of 6 bits) */
130 #define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS 7UL /* Position of bits register offset of STRx
131 channel 1 or 2 versus STRx channel 1
132 (shifted left of 7 bits) */
133
134 /* DAC registers bits positions */
135 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
136 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
137 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
138
139 /* Miscellaneous data */
140 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
141 bits (voltage range determined by analog voltage
142 references Vref+ and Vref-, refer to reference manual) */
143
144 /**
145 * @}
146 */
147
148
149 /* Private macros ------------------------------------------------------------*/
150 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
151 * @{
152 */
153
154 /**
155 * @brief Driver macro reserved for internal use: set a pointer to
156 * a register from a register basis from which an offset
157 * is applied.
158 * @param __REG__ Register basis from which the offset is applied.
159 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
160 * @retval Pointer to register address
161 */
162 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
163 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
164
165 /**
166 * @}
167 */
168
169
170 /* Exported types ------------------------------------------------------------*/
171 #if defined(USE_FULL_LL_DRIVER)
172 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
173 * @{
174 */
175
176 /**
177 * @brief Structure definition of some features of DAC instance.
178 */
179 typedef struct
180 {
181 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
182 internal (SW start) or from external peripheral
183 (timer event, external interrupt line).
184 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
185
186 This feature can be modified afterwards using unitary
187 function @ref LL_DAC_SetTriggerSource().
188 @note If waveform automatic generation mode is set to sawtooth,
189 this parameter is used as sawtooth RESET trigger */
190
191 uint32_t TriggerSource2; /*!< Set the conversion secondary trigger source for the selected DAC channel:
192 internal (SW start) or from external peripheral
193 (timer event, external interrupt line).
194 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
195
196 This feature can be modified afterwards using unitary
197 function @ref LL_DAC_SetTriggerSource2().
198 @note If waveform automatic generation mode is set to sawtooth,
199 this parameter is used as sawtooth step trigger */
200
201 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
202 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
203
204 This feature can be modified afterwards using unitary
205 function @ref LL_DAC_SetWaveAutoGeneration(). */
206
207 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
208 If waveform automatic generation mode is set to noise, this parameter
209 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
210 If waveform automatic generation mode is set to triangle,
211 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
212 If waveform automatic generation mode is set to sawtooth, this parameter
213 host the sawtooth configuration: polarity, reset data, increment data.
214 Use __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG macro to set this parameter value.
215 @note If waveform automatic generation mode is disabled,
216 this parameter is discarded.
217
218 This feature can be modified afterwards using unitary
219 function @ref LL_DAC_SetWaveNoiseLFSR(),
220 @ref LL_DAC_SetWaveTriangleAmplitude(),
221 @ref LL_DAC_SetWaveSawtoothPolarity(),
222 @ref LL_DAC_SetWaveSawtoothResetData()
223 or @ref LL_DAC_SetWaveSawtoothStepData(),
224 depending on the wave automatic generation selected. */
225
226 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
227 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
228
229 This feature can be modified afterwards using unitary
230 function @ref LL_DAC_SetOutputBuffer(). */
231
232 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
233 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
234
235 This feature can be modified afterwards using unitary
236 function @ref LL_DAC_SetOutputConnection(). */
237
238 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
239 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
240
241 This feature can be modified afterwards using unitary
242 function @ref LL_DAC_SetOutputMode(). */
243 } LL_DAC_InitTypeDef;
244
245 /**
246 * @}
247 */
248 #endif /* USE_FULL_LL_DRIVER */
249
250 /* Exported constants --------------------------------------------------------*/
251 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
252 * @{
253 */
254
255 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
256 * @brief Flags defines which can be used with LL_DAC_ReadReg function
257 * @{
258 */
259 /* DAC channel 1 flags */
260 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
261 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
262 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
263 #define LL_DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) /*!< DAC channel 1 flag ready */
264 #define LL_DAC_FLAG_DORSTAT1 (DAC_SR_DORSTAT1) /*!< DAC channel 1 flag output register */
265
266 /* DAC channel 2 flags */
267 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
268 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
269 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
270 #define LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /*!< DAC channel 2 flag ready */
271 #define LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2) /*!< DAC channel 2 flag output register */
272
273 /**
274 * @}
275 */
276
277 /** @defgroup DAC_LL_EC_IT DAC interruptions
278 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
279 * @{
280 */
281 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
282
283 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
284
285 /**
286 * @}
287 */
288
289 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
290 * @{
291 */
292 #define LL_DAC_CHANNEL_1 (DAC_REG_STR1_REGOFFSET | DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1 | DAC_SWTRB_CH1) /*!< DAC channel 1 */
293 #define LL_DAC_CHANNEL_2 (DAC_REG_STR2_REGOFFSET | DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2 | DAC_SWTRB_CH2) /*!< DAC channel 2 */
294 /**
295 * @}
296 */
297
298 /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
299 * @brief High frequency interface mode defines that can be used
300 * with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
301 * @{
302 */
303 #define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
304 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
305 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
306 /**
307 * @}
308 */
309
310 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
311 * @{
312 */
313 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
314 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
315 /**
316 * @}
317 */
318
319 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
320 * @{
321 */
322 #define LL_DAC_TRIG_SOFTWARE 0x00000000UL /*!< DAC (all) channel conversion trigger internal (SW start) */
323 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: TIM1 TRGO. */
324 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC1/2/4 channel conversion trigger from external peripheral: TIM8 TRGO. Refer to device datasheet for DACx instance availability. */
325 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM7 TRGO. */
326 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM15 TRGO. */
327 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM2 TRGO. */
328 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM4 TRGO. */
329 #define LL_DAC_TRIG_EXT_EXTI_LINE9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 9. Note: only to be used as update or reset (sawtooth generation) trigger */
330 #define LL_DAC_TRIG_EXT_EXTI_LINE10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 10. Note: only to be used as increment (sawtooth generation) trigger */
331 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM6 TRGO. */
332 #define LL_DAC_TRIG_EXT_TIM3_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM3 TRGO. */
333 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
334 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
335 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
336 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
337 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
338 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
339 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
340 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
341 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
342 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
343 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
344 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
345 #define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC1&4 channel conversion trigger from external peripheral: HRTIM1 DACTRG1. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
346 #define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC2 channel conversion trigger from external peripheral: HRTIM1 DACTRG2. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
347 #define LL_DAC_TRIG_EXT_HRTIM_TRGO3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: HRTIM1 DACTRG3. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
348 /**
349 * @}
350 */
351
352 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
353 * @{
354 */
355 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
356 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
357 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
358 #define LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH (DAC_CR_WAVE1_1|DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated sawtooth waveform. */
359 /**
360 * @}
361 */
362
363 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
364 * @{
365 */
366 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
367 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
368 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
369 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
370 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
371 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
372 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
373 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
374 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
375 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
376 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
377 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
378 /**
379 * @}
380 */
381
382 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
383 * @{
384 */
385 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
386 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
387 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
388 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
389 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
390 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
391 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
392 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
393 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
394 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
395 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
396 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
397 /**
398 * @}
399 */
400
401 /** @defgroup DAC_LL_EC_SAWTOOTH_POLARITY_MODE DAC wave generation - Sawtooth polarity mode
402 * @{
403 */
404 #define LL_DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */
405 #define LL_DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */
406 /**
407 * @}
408 */
409
410 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
411 * @{
412 */
413 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
414 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
415 /**
416 * @}
417 */
418
419 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
420 * @{
421 */
422 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
423 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
424 /**
425 * @}
426 */
427
428 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
429 * @{
430 */
431 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
432 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
433 /**
434 * @}
435 */
436
437 /** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format
438 * @{
439 */
440 #define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL /*!< The selected DAC channel data format is not signed */
441 #define LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1) /*!< The selected DAC channel data format is signed */
442 /**
443 * @}
444 */
445
446 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
447 * @{
448 */
449 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
450 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
451 /**
452 * @}
453 */
454
455 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
456 * @{
457 */
458 /* List of DAC registers intended to be used (most commonly) with */
459 /* DMA transfer. */
460 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
461 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
462 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
463 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
464 /**
465 * @}
466 */
467
468 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
469 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
470 * not timeout values.
471 * For details on delays values, refer to descriptions in source code
472 * above each literal definition.
473 * @{
474 */
475
476 /* Delay for DAC channel voltage settling time from DAC channel startup */
477 /* (transition from disable to enable). */
478 /* Note: DAC channel startup time depends on board application environment: */
479 /* impedance connected to DAC channel output. */
480 /* The delay below is specified under conditions: */
481 /* - voltage maximum transition (lowest to highest value) */
482 /* - until voltage reaches final value +-1LSB */
483 /* - DAC channel output buffer enabled */
484 /* - load impedance of 5kOhm (min), 50pF (max) */
485 /* Literal set to maximum value (refer to device datasheet, */
486 /* parameter "tWAKEUP"). */
487 /* Unit: us */
488 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
489
490 /* Delay for DAC channel voltage settling time. */
491 /* Note: DAC channel startup time depends on board application environment: */
492 /* impedance connected to DAC channel output. */
493 /* The delay below is specified under conditions: */
494 /* - voltage maximum transition (lowest to highest value) */
495 /* - until voltage reaches final value +-1LSB */
496 /* - DAC channel output buffer enabled */
497 /* - load impedance of 5kOhm min, 50pF max */
498 /* Literal set to maximum value (refer to device datasheet, */
499 /* parameter "tSETTLING"). */
500 /* Unit: us */
501 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
502
503 /**
504 * @}
505 */
506
507 /**
508 * @}
509 */
510
511 /* Exported macro ------------------------------------------------------------*/
512 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
513 * @{
514 */
515
516 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
517 * @{
518 */
519
520 /**
521 * @brief Write a value in DAC register
522 * @param __INSTANCE__ DAC Instance
523 * @param __REG__ Register to be written
524 * @param __VALUE__ Value to be written in the register
525 * @retval None
526 */
527 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
528
529 /**
530 * @brief Read a value in DAC register
531 * @param __INSTANCE__ DAC Instance
532 * @param __REG__ Register to be read
533 * @retval Register value
534 */
535 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
536
537 /**
538 * @}
539 */
540
541 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
542 * @{
543 */
544
545 /**
546 * @brief Helper macro to get DAC channel number in decimal format
547 * from literals LL_DAC_CHANNEL_x.
548 * Example:
549 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
550 * will return decimal number "1".
551 * @note The input can be a value from functions where a channel
552 * number is returned.
553 * @param __CHANNEL__ This parameter can be one of the following values:
554 * @arg @ref LL_DAC_CHANNEL_1
555 * @arg @ref LL_DAC_CHANNEL_2 (1)
556 *
557 * (1) On this STM32 series, parameter not available on all instances.
558 * Refer to device datasheet for channels availability.
559 * @retval 1...2
560 */
561 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
562 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
563
564 /**
565 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
566 * from number in decimal format.
567 * Example:
568 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
569 * will return a data equivalent to "LL_DAC_CHANNEL_1".
570 * @note If the input parameter does not correspond to a DAC channel,
571 * this macro returns value '0'.
572 * @param __DECIMAL_NB__ 1...2
573 * @retval Returned value can be one of the following values:
574 * @arg @ref LL_DAC_CHANNEL_1
575 * @arg @ref LL_DAC_CHANNEL_2 (1)
576 *
577 * (1) On this STM32 series, parameter not available on all instances.
578 * Refer to device datasheet for channels availability.
579 */
580 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
581 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
582
583 /**
584 * @brief Helper macro to define the DAC conversion data full-scale digital
585 * value corresponding to the selected DAC resolution.
586 * @note DAC conversion data full-scale corresponds to voltage range
587 * determined by analog voltage references Vref+ and Vref-
588 * (refer to reference manual).
589 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
590 * @arg @ref LL_DAC_RESOLUTION_12B
591 * @arg @ref LL_DAC_RESOLUTION_8B
592 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
593 */
594 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
595 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
596
597 /**
598 * @brief Helper macro to calculate the DAC conversion data (unit: digital
599 * value) corresponding to a voltage (unit: mVolt).
600 * @note This helper macro is intended to provide input data in voltage
601 * rather than digital value,
602 * to be used with LL DAC functions such as
603 * @ref LL_DAC_ConvertData12RightAligned().
604 * @note Analog reference voltage (Vref+) must be either known from
605 * user board environment or can be calculated using ADC measurement
606 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
607 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
608 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
609 * (unit: mVolt).
610 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
611 * @arg @ref LL_DAC_RESOLUTION_12B
612 * @arg @ref LL_DAC_RESOLUTION_8B
613 * @retval DAC conversion data (unit: digital value)
614 */
615 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
616 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
617 / (__VREFANALOG_VOLTAGE__) \
618 )
619
620 /**
621 * @brief Helper macro to format sawtooth wave generation configuration
622 * value to be filled into WaveAutoGenerationConfig parameter of @ref LL_DAC_InitTypeDef.
623 * @note This helper will format information to fit in DAC_STRx register.
624 * @param __POLARITY__ sawtooth wave polarity (must be value of @ref DAC_LL_EC_SAWTOOTH_POLARITY_MODE)
625 * @param __RESET_DATA__ sawtooth reset data.
626 * @param __STEP_DATA__ sawtooth step data
627 * @retval Sawtooth configuration organized in DAC_STRx compatible format.
628 */
629 #define __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__, __RESET_DATA__, __STEP_DATA__) \
630 ( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk) \
631 | ((__POLARITY__) & DAC_STR1_STDIR1_Msk) \
632 | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk) \
633 )
634
635 /**
636 * @}
637 */
638
639 /**
640 * @}
641 */
642
643
644 /* Exported functions --------------------------------------------------------*/
645 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
646 * @{
647 */
648 /** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
649 * @{
650 */
651 /**
652 * @brief Set the high frequency interface mode for the selected DAC instance
653 * @rmtoll MCR HFSEL LL_DAC_SetHighFrequencyMode
654 * @param DACx DAC instance
655 * @param HighFreqMode This parameter can be one of the following values:
656 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
657 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
658 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
659 * @retval None
660 */
LL_DAC_SetHighFrequencyMode(DAC_TypeDef * DACx,uint32_t HighFreqMode)661 __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
662 {
663 MODIFY_REG(DACx->MCR, DAC_MCR_HFSEL, HighFreqMode);
664 }
665
666 /**
667 * @brief Get the high frequency interface mode for the selected DAC instance
668 * @rmtoll MCR HFSEL LL_DAC_GetHighFrequencyMode
669 * @param DACx DAC instance
670 * @retval Returned value can be one of the following values:
671 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
672 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
673 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
674 */
LL_DAC_GetHighFrequencyMode(const DAC_TypeDef * DACx)675 __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(const DAC_TypeDef *DACx)
676 {
677 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_HFSEL));
678 }
679 /**
680 * @}
681 */
682
683
684 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
685 * @{
686 */
687
688 /**
689 * @brief Set the operating mode for the selected DAC channel:
690 * calibration or normal operating mode.
691 * @rmtoll CR CEN1 LL_DAC_SetMode\n
692 * CR CEN2 LL_DAC_SetMode
693 * @param DACx DAC instance
694 * @param DAC_Channel This parameter can be one of the following values:
695 * @arg @ref LL_DAC_CHANNEL_1
696 * @arg @ref LL_DAC_CHANNEL_2 (1)
697 *
698 * (1) On this STM32 series, parameter not available on all instances.
699 * Refer to device datasheet for channels availability.
700 * @param ChannelMode This parameter can be one of the following values:
701 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
702 * @arg @ref LL_DAC_MODE_CALIBRATION
703 * @retval None
704 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)705 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
706 {
707 MODIFY_REG(DACx->CR,
708 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
709 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
710 }
711
712 /**
713 * @brief Get the operating mode for the selected DAC channel:
714 * calibration or normal operating mode.
715 * @rmtoll CR CEN1 LL_DAC_GetMode\n
716 * CR CEN2 LL_DAC_GetMode
717 * @param DACx DAC instance
718 * @param DAC_Channel This parameter can be one of the following values:
719 * @arg @ref LL_DAC_CHANNEL_1
720 * @arg @ref LL_DAC_CHANNEL_2 (1)
721 *
722 * (1) On this STM32 series, parameter not available on all instances.
723 * Refer to device datasheet for channels availability.
724 * @retval Returned value can be one of the following values:
725 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
726 * @arg @ref LL_DAC_MODE_CALIBRATION
727 */
LL_DAC_GetMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)728 __STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
729 {
730 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
731 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
732 );
733 }
734
735 /**
736 * @brief Set the offset trimming value for the selected DAC channel.
737 * Trimming has an impact when output buffer is enabled
738 * and is intended to replace factory calibration default values.
739 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
740 * CCR OTRIM2 LL_DAC_SetTrimmingValue
741 * @param DACx DAC instance
742 * @param DAC_Channel This parameter can be one of the following values:
743 * @arg @ref LL_DAC_CHANNEL_1
744 * @arg @ref LL_DAC_CHANNEL_2 (1)
745 *
746 * (1) On this STM32 series, parameter not available on all instances.
747 * Refer to device datasheet for channels availability.
748 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
749 * @retval None
750 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)751 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
752 {
753 MODIFY_REG(DACx->CCR,
754 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
755 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
756 }
757
758 /**
759 * @brief Get the offset trimming value for the selected DAC channel.
760 * Trimming has an impact when output buffer is enabled
761 * and is intended to replace factory calibration default values.
762 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
763 * CCR OTRIM2 LL_DAC_GetTrimmingValue
764 * @param DACx DAC instance
765 * @param DAC_Channel This parameter can be one of the following values:
766 * @arg @ref LL_DAC_CHANNEL_1
767 * @arg @ref LL_DAC_CHANNEL_2 (1)
768 *
769 * (1) On this STM32 series, parameter not available on all instances.
770 * Refer to device datasheet for channels availability.
771 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
772 */
LL_DAC_GetTrimmingValue(const DAC_TypeDef * DACx,uint32_t DAC_Channel)773 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
774 {
775 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
776 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
777 );
778 }
779
780 /**
781 * @brief Set the conversion trigger source for the selected DAC channel.
782 * @note For conversion trigger source to be effective, DAC trigger
783 * must be enabled using function @ref LL_DAC_EnableTrigger().
784 * @note To set conversion trigger source, DAC channel must be disabled.
785 * Otherwise, the setting is discarded.
786 * @note Availability of parameters of trigger sources from timer
787 * depends on timers availability on the selected device.
788 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
789 * CR TSEL2 LL_DAC_SetTriggerSource
790 * @param DACx DAC instance
791 * @param DAC_Channel This parameter can be one of the following values:
792 * @arg @ref LL_DAC_CHANNEL_1
793 * @arg @ref LL_DAC_CHANNEL_2 (1)
794 *
795 * (1) On this STM32 series, parameter not available on all instances.
796 * Refer to device datasheet for channels availability.
797 * @param TriggerSource This parameter can be one of the following values:
798 * @arg @ref LL_DAC_TRIG_SOFTWARE
799 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
800 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
801 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
802 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
803 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
804 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
805 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
806 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
807 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
808 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
809 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
810 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
811 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
812 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
813 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
814 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
815 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
816 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
817 *
818 * (1) On this STM32 series, parameter only available on DAC3.
819 * (2) On this STM32 series, parameter only available on DAC1/2/4.
820 * (3) On this STM32 series, parameter only available on DAC1&4.
821 * (4) On this STM32 series, parameter only available on DAC2.
822 * Refer to device datasheet for DACx instances availability.
823 * (5) On this STM32 series, parameter not available on all devices.
824 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
825 * @retval None
826 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)827 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
828 {
829 MODIFY_REG(DACx->CR,
830 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
831 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
832 }
833
834 /**
835 * @brief Get the conversion trigger source for the selected DAC channel.
836 * @note For conversion trigger source to be effective, DAC trigger
837 * must be enabled using function @ref LL_DAC_EnableTrigger().
838 * @note Availability of parameters of trigger sources from timer
839 * depends on timers availability on the selected device.
840 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
841 * CR TSEL2 LL_DAC_GetTriggerSource
842 * @param DACx DAC instance
843 * @param DAC_Channel This parameter can be one of the following values:
844 * @arg @ref LL_DAC_CHANNEL_1
845 * @arg @ref LL_DAC_CHANNEL_2 (1)
846 *
847 * (1) On this STM32 series, parameter not available on all instances.
848 * Refer to device datasheet for channels availability.
849 * @retval Returned value can be one of the following values:
850 * @arg @ref LL_DAC_TRIG_SOFTWARE
851 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
852 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
853 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
854 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
855 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
856 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
857 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
858 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
859 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
860 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
861 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
862 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
863 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
864 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
865 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
866 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
867 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
868 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
869 *
870 * (1) On this STM32 series, parameter only available on DAC3.
871 * (2) On this STM32 series, parameter only available on DAC1/2/4.
872 * (3) On this STM32 series, parameter only available on DAC1&4.
873 * (4) On this STM32 series, parameter only available on DAC2.
874 * Refer to device datasheet for DACx instances availability.
875 * (5) On this STM32 series, parameter not available on all devices.
876 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
877 */
LL_DAC_GetTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)878 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
879 {
880 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
881 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
882 );
883 }
884
885 /**
886 * @brief Set the waveform automatic generation mode
887 * for the selected DAC channel.
888 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
889 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
890 * @param DACx DAC instance
891 * @param DAC_Channel This parameter can be one of the following values:
892 * @arg @ref LL_DAC_CHANNEL_1
893 * @arg @ref LL_DAC_CHANNEL_2 (1)
894 *
895 * (1) On this STM32 series, parameter not available on all instances.
896 * Refer to device datasheet for channels availability.
897 * @param WaveAutoGeneration This parameter can be one of the following values:
898 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
899 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
900 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
901 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
902 * @retval None
903 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)904 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
905 {
906 MODIFY_REG(DACx->CR,
907 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
908 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
909 }
910
911 /**
912 * @brief Get the waveform automatic generation mode
913 * for the selected DAC channel.
914 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
915 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
916 * @param DACx DAC instance
917 * @param DAC_Channel This parameter can be one of the following values:
918 * @arg @ref LL_DAC_CHANNEL_1
919 * @arg @ref LL_DAC_CHANNEL_2 (1)
920 *
921 * (1) On this STM32 series, parameter not available on all instances.
922 * Refer to device datasheet for channels availability.
923 * @retval Returned value can be one of the following values:
924 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
925 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
926 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
927 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
928 */
LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef * DACx,uint32_t DAC_Channel)929 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
930 {
931 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
932 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
933 );
934 }
935
936 /**
937 * @brief Set the noise waveform generation for the selected DAC channel:
938 * Noise mode and parameters LFSR (linear feedback shift register).
939 * @note For wave generation to be effective, DAC channel
940 * wave generation mode must be enabled using
941 * function @ref LL_DAC_SetWaveAutoGeneration().
942 * @note This setting can be set when the selected DAC channel is disabled
943 * (otherwise, the setting operation is ignored).
944 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
945 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
946 * @param DACx DAC instance
947 * @param DAC_Channel This parameter can be one of the following values:
948 * @arg @ref LL_DAC_CHANNEL_1
949 * @arg @ref LL_DAC_CHANNEL_2 (1)
950 *
951 * (1) On this STM32 series, parameter not available on all instances.
952 * Refer to device datasheet for channels availability.
953 * @param NoiseLFSRMask This parameter can be one of the following values:
954 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
955 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
956 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
957 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
958 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
959 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
960 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
961 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
962 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
963 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
964 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
965 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
966 * @retval None
967 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)968 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
969 {
970 MODIFY_REG(DACx->CR,
971 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
972 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
973 }
974
975 /**
976 * @brief Get the noise waveform generation for the selected DAC channel:
977 * Noise mode and parameters LFSR (linear feedback shift register).
978 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
979 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
980 * @param DACx DAC instance
981 * @param DAC_Channel This parameter can be one of the following values:
982 * @arg @ref LL_DAC_CHANNEL_1
983 * @arg @ref LL_DAC_CHANNEL_2 (1)
984 *
985 * (1) On this STM32 series, parameter not available on all instances.
986 * Refer to device datasheet for channels availability.
987 * @retval Returned value can be one of the following values:
988 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
989 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
990 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
991 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
992 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
993 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
994 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
995 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
996 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
997 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
998 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
999 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
1000 */
LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1001 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1002 {
1003 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1004 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1005 );
1006 }
1007
1008 /**
1009 * @brief Set the triangle waveform generation for the selected DAC channel:
1010 * triangle mode and amplitude.
1011 * @note For wave generation to be effective, DAC channel
1012 * wave generation mode must be enabled using
1013 * function @ref LL_DAC_SetWaveAutoGeneration().
1014 * @note This setting can be set when the selected DAC channel is disabled
1015 * (otherwise, the setting operation is ignored).
1016 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
1017 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
1018 * @param DACx DAC instance
1019 * @param DAC_Channel This parameter can be one of the following values:
1020 * @arg @ref LL_DAC_CHANNEL_1
1021 * @arg @ref LL_DAC_CHANNEL_2 (1)
1022 *
1023 * (1) On this STM32 series, parameter not available on all instances.
1024 * Refer to device datasheet for channels availability.
1025 * @param TriangleAmplitude This parameter can be one of the following values:
1026 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
1027 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
1028 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
1029 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
1030 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
1031 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
1032 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
1033 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
1034 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
1035 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
1036 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
1037 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
1038 * @retval None
1039 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)1040 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
1041 uint32_t TriangleAmplitude)
1042 {
1043 MODIFY_REG(DACx->CR,
1044 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1045 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1046 }
1047
1048 /**
1049 * @brief Get the triangle waveform generation for the selected DAC channel:
1050 * triangle mode and amplitude.
1051 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
1052 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
1053 * @param DACx DAC instance
1054 * @param DAC_Channel This parameter can be one of the following values:
1055 * @arg @ref LL_DAC_CHANNEL_1
1056 * @arg @ref LL_DAC_CHANNEL_2 (1)
1057 *
1058 * (1) On this STM32 series, parameter not available on all instances.
1059 * Refer to device datasheet for channels availability.
1060 * @retval Returned value can be one of the following values:
1061 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
1062 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
1063 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
1064 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
1065 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
1066 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
1067 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
1068 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
1069 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
1070 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
1071 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
1072 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
1073 */
LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1074 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1075 {
1076 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1077 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1078 );
1079 }
1080
1081 /**
1082 * @brief Set the swatooth waveform generation polarity.
1083 * @note For wave generation to be effective, DAC channel
1084 * wave generation mode must be enabled using
1085 * function @ref LL_DAC_SetWaveAutoGeneration().
1086 * @note This setting can be set when the selected DAC channel is disabled
1087 * (otherwise, the setting operation is ignored).
1088 * @rmtoll STR1 STDIR1 LL_DAC_SetWaveSawtoothPolarity\n
1089 * STR2 STDIR2 LL_DAC_SetWaveSawtoothPolarity
1090 * @param DACx DAC instance
1091 * @param DAC_Channel This parameter can be one of the following values:
1092 * @arg @ref LL_DAC_CHANNEL_1
1093 * @arg @ref LL_DAC_CHANNEL_2 (1)
1094 *
1095 * (1) On this STM32 series, parameter not available on all instances.
1096 * Refer to device datasheet for channels availability.
1097 * @param Polarity This parameter can be one of the following values:
1098 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
1099 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
1100 * @retval None
1101 */
LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Polarity)1102 __STATIC_INLINE void LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Polarity)
1103 {
1104 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
1105 (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) &
1106 DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1107
1108 MODIFY_REG(*preg,
1109 DAC_STR1_STDIR1,
1110 Polarity);
1111 }
1112
1113 /**
1114 * @brief Get the sawtooth waveform generation polarity.
1115 * @rmtoll STR1 STDIR1 LL_DAC_GetWaveSawtoothPolarity\n
1116 * STR2 STDIR2 LL_DAC_GetWaveSawtoothPolarity
1117 * @param DACx DAC instance
1118 * @param DAC_Channel This parameter can be one of the following values:
1119 * @arg @ref LL_DAC_CHANNEL_1
1120 * @arg @ref LL_DAC_CHANNEL_2 (1)
1121 *
1122 * (1) On this STM32 series, parameter not available on all instances.
1123 * Refer to device datasheet for channels availability.
1124 * @retval Returned value can be one of the following values:
1125 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
1126 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
1127 */
LL_DAC_GetWaveSawtoothPolarity(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1128 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1129 {
1130 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
1131 (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS)
1132 & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1133
1134 return (uint32_t) READ_BIT(*preg, DAC_STR1_STDIR1);
1135 }
1136
1137 /**
1138 * @brief Set the swatooth waveform generation reset data.
1139 * @note For wave generation to be effective, DAC channel
1140 * wave generation mode must be enabled using
1141 * function @ref LL_DAC_SetWaveAutoGeneration().
1142 * @note This setting can be set when the selected DAC channel is disabled
1143 * (otherwise, the setting operation is ignored).
1144 * @rmtoll STR1 STRSTDATA1 LL_DAC_SetWaveSawtoothResetData\n
1145 * STR2 STRSTDATA2 LL_DAC_SetWaveSawtoothResetData
1146 * @param DACx DAC instance
1147 * @param DAC_Channel This parameter can be one of the following values:
1148 * @arg @ref LL_DAC_CHANNEL_1
1149 * @arg @ref LL_DAC_CHANNEL_2 (1)
1150 *
1151 * (1) On this STM32 series, parameter not available on all instances.
1152 * Refer to device datasheet for channels availability.
1153 * @param ResetData This parameter is the sawtooth reset value.
1154 * Range is from 0 to DAC full range 4095 (0xFFF)
1155 * @retval None
1156 */
LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ResetData)1157 __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ResetData)
1158 {
1159 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
1160 (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) &
1161 DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1162
1163 MODIFY_REG(*preg,
1164 DAC_STR1_STRSTDATA1,
1165 ResetData << DAC_STR1_STRSTDATA1_Pos);
1166 }
1167
1168 /**
1169 * @brief Get the sawtooth waveform generation reset data.
1170 * @rmtoll STR1 STRSTDATA1 LL_DAC_GetWaveSawtoothResetData\n
1171 * STR2 STRSTDATA2 LL_DAC_GetWaveSawtoothResetData
1172 * @param DACx DAC instance
1173 * @param DAC_Channel This parameter can be one of the following values:
1174 * @arg @ref LL_DAC_CHANNEL_1
1175 * @arg @ref LL_DAC_CHANNEL_2 (1)
1176 *
1177 * (1) On this STM32 series, parameter not available on all instances.
1178 * Refer to device datasheet for channels availability.
1179 * @retval Returned value is the sawtooth reset value.
1180 * Range is from 0 to DAC full range 4095 (0xFFF)
1181 */
LL_DAC_GetWaveSawtoothResetData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1182 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1183 {
1184 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
1185 (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS)
1186 & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1187
1188 return (uint32_t)(READ_BIT(*preg, DAC_STR1_STRSTDATA1) >> DAC_STR1_STRSTDATA1_Pos);
1189 }
1190
1191 /**
1192 * @brief Set the sawtooth waveform generation step data.
1193 * @note For wave generation to be effective, DAC channel
1194 * wave generation mode must be enabled using
1195 * function @ref LL_DAC_SetWaveAutoGeneration().
1196 * @note This setting can be set when the selected DAC channel is disabled
1197 * (otherwise, the setting operation is ignored).
1198 * @rmtoll STR1 STINCDATA1 LL_DAC_SetWaveSawtoothStepData\n
1199 * STR2 STINCDATA2 LL_DAC_SetWaveSawtoothStepData
1200 * @param DACx DAC instance
1201 * @param DAC_Channel This parameter can be one of the following values:
1202 * @arg @ref LL_DAC_CHANNEL_1
1203 * @arg @ref LL_DAC_CHANNEL_2 (1)
1204 *
1205 * (1) On this STM32 series, parameter not available on all instances.
1206 * Refer to device datasheet for channels availability.
1207 * @param StepData This parameter is the sawtooth step value.
1208 * 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
1209 * Step value step is 1/16 = 0.0625
1210 * Step value range is 0.0000 to 4095.9375 (0xFFF.F)
1211 * @retval None
1212 */
LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t StepData)1213 __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t StepData)
1214 {
1215 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
1216 (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) &
1217 DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1218
1219 MODIFY_REG(*preg,
1220 DAC_STR1_STINCDATA1,
1221 StepData << DAC_STR1_STINCDATA1_Pos);
1222 }
1223
1224 /**
1225 * @brief Get the sawtooth waveform generation step data.
1226 * @rmtoll STR1 STINCDATA1 LL_DAC_GetWaveSawtoothStepData\n
1227 * STR2 STINCDATA2 LL_DAC_GetWaveSawtoothStepData
1228 * @param DACx DAC instance
1229 * @param DAC_Channel This parameter can be one of the following values:
1230 * @arg @ref LL_DAC_CHANNEL_1
1231 * @arg @ref LL_DAC_CHANNEL_2 (1)
1232 *
1233 * (1) On this STM32 series, parameter not available on all instances.
1234 * Refer to device datasheet for channels availability.
1235 * @retval Returned value is the sawtooth step value.
1236 * 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
1237 * Step value step is 1/16 = 0.0625
1238 * Step value range is 0.0000 to 4095.9375 (0xFFF.F)
1239 */
LL_DAC_GetWaveSawtoothStepData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1240 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1241 {
1242 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
1243 (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS)
1244 & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1245
1246 return (uint32_t)(READ_BIT(*preg, DAC_STR1_STINCDATA1) >> DAC_STR1_STINCDATA1_Pos);
1247 }
1248
1249 /**
1250 * @brief Set the sawtooth waveform generation reset trigger source.
1251 * @note For wave generation to be effective, DAC channel
1252 * wave generation mode must be enabled using
1253 * function @ref LL_DAC_SetWaveAutoGeneration().
1254 * @note This setting can be set when the selected DAC channel is disabled
1255 * (otherwise, the setting operation is ignored).
1256 * @rmtoll STMODR STRSTTRIGSEL1 LL_DAC_SetWaveSawtoothResetTriggerSource\n
1257 * STMODR STRSTTRIGSEL2 LL_DAC_SetWaveSawtoothResetTriggerSource
1258 * @param DACx DAC instance
1259 * @param DAC_Channel This parameter can be one of the following values:
1260 * @arg @ref LL_DAC_CHANNEL_1
1261 * @arg @ref LL_DAC_CHANNEL_2 (1)
1262 *
1263 * (1) On this STM32 series, parameter not available on all instances.
1264 * Refer to device datasheet for channels availability.
1265 * @param TriggerSource This parameter can be one of the following values:
1266 * @arg @ref LL_DAC_TRIG_SOFTWARE
1267 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1268 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1269 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1270 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1271 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1272 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1273 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
1274 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1275 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1276 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
1277 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
1278 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
1279 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
1280 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
1281 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
1282 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
1283 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
1284 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
1285 *
1286 * (1) On this STM32 series, parameter only available on DAC3.
1287 * (2) On this STM32 series, parameter only available on DAC1/2/4.
1288 * (3) On this STM32 series, parameter only available on DAC1&4.
1289 * (4) On this STM32 series, parameter only available on DAC2.
1290 * Refer to device datasheet for DACx instances availability.
1291 * (5) On this STM32 series, parameter not available on all devices.
1292 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1293 * @retval None
1294 */
LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)1295 __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
1296 uint32_t TriggerSource)
1297 {
1298 MODIFY_REG(DACx->STMODR,
1299 DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1300 ( ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos)
1301 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ));
1302 }
1303
1304 /**
1305 * @brief Get the sawtooth waveform generation reset trigger source.
1306 * @rmtoll STMODR STRSTTRIGSEL1 LL_DAC_GetWaveSawtoothResetTriggerSource\n
1307 * STMODR STRSTTRIGSEL2 LL_DAC_GetWaveSawtoothResetTriggerSource
1308 * @param DACx DAC instance
1309 * @param DAC_Channel This parameter can be one of the following values:
1310 * @arg @ref LL_DAC_CHANNEL_1
1311 * @arg @ref LL_DAC_CHANNEL_2 (1)
1312 *
1313 * (1) On this STM32 series, parameter not available on all instances.
1314 * Refer to device datasheet for channels availability.
1315 * @retval Returned value can be one of the following values:
1316 * @arg @ref LL_DAC_TRIG_SOFTWARE
1317 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1318 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1319 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1320 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1321 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1322 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1323 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
1324 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1325 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1326 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
1327 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
1328 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
1329 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
1330 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
1331 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
1332 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
1333 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
1334 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
1335 *
1336 * (1) On this STM32 series, parameter only available on DAC3.
1337 * (2) On this STM32 series, parameter only available on DAC1/2/4.
1338 * (3) On this STM32 series, parameter only available on DAC1&4.
1339 * (4) On this STM32 series, parameter only available on DAC2.
1340 * Refer to device datasheet for DACx instances availability.
1341 * (5) On this STM32 series, parameter not available on all devices.
1342 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1343 */
LL_DAC_GetWaveSawtoothResetTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1344 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1345 {
1346 return (uint32_t)((READ_BIT(DACx->STMODR,
1347 DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1348 )
1349 >> (DAC_STMODR_STRSTTRIGSEL1_Pos + (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1350 ) << DAC_CR_TSEL1_Pos);
1351 }
1352
1353 /**
1354 * @brief Set the swatooth waveform generation step trigger source.
1355 * @note For wave generation to be effective, DAC channel
1356 * wave generation mode must be enabled using
1357 * function @ref LL_DAC_SetWaveAutoGeneration().
1358 * @note This setting can be set when the selected DAC channel is disabled
1359 * (otherwise, the setting operation is ignored).
1360 * @rmtoll STMODR STINCTRIGSEL1 LL_DAC_SetWaveSawtoothStepTriggerSource\n
1361 * STMODR STINCTRIGSEL2 LL_DAC_SetWaveSawtoothStepTriggerSource
1362 * @param DACx DAC instance
1363 * @param DAC_Channel This parameter can be one of the following values:
1364 * @arg @ref LL_DAC_CHANNEL_1
1365 * @arg @ref LL_DAC_CHANNEL_2 (1)
1366 *
1367 * (1) On this STM32 series, parameter not available on all instances.
1368 * Refer to device datasheet for channels availability.
1369 * @param TriggerSource This parameter can be one of the following values:
1370 * @arg @ref LL_DAC_TRIG_SOFTWARE
1371 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1372 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1373 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1374 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1375 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1376 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1377 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
1378 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1379 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1380 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (3)
1381 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (3)
1382 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (3)
1383 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (3)
1384 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3)
1385 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3)
1386 *
1387 * (1) On this STM32 series, parameter only available on DAC3.
1388 * (2) On this STM32 series, parameter only available on DAC1/2/4.
1389 * Refer to device datasheet for DACx instances availability.
1390 * (3) On this STM32 series, parameter not available on all devices.
1391 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1392 * @retval None
1393 */
LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)1394 __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
1395 uint32_t TriggerSource)
1396 {
1397 MODIFY_REG(DACx->STMODR,
1398 DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1399 ( ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos)
1400 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1401 ));
1402 }
1403
1404 /**
1405 * @brief Get the sawtooth waveform generation step trigger source.
1406 * @rmtoll STMODR STINCTRIGSEL1 LL_DAC_GetWaveSawtoothStepTriggerSource\n
1407 * STMODR STINCTRIGSEL2 LL_DAC_GetWaveSawtoothStepTriggerSource
1408 * @param DACx DAC instance
1409 * @param DAC_Channel This parameter can be one of the following values:
1410 * @arg @ref LL_DAC_CHANNEL_1
1411 * @arg @ref LL_DAC_CHANNEL_2 (1)
1412 *
1413 * (1) On this STM32 series, parameter not available on all instances.
1414 * Refer to device datasheet for channels availability.
1415 * @retval Returned value can be one of the following values:
1416 * @arg @ref LL_DAC_TRIG_SOFTWARE
1417 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1418 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1419 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1420 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1421 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1422 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1423 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
1424 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1425 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1426 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (3)
1427 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (3)
1428 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (3)
1429 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (3)
1430 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3)
1431 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3)
1432 *
1433 * (1) On this STM32 series, parameter only available on DAC3.
1434 * (2) On this STM32 series, parameter only available on DAC1/2/4.
1435 * Refer to device datasheet for DACx instances availability.
1436 * (3) On this STM32 series, parameter not available on all devices.
1437 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1438 */
LL_DAC_GetWaveSawtoothStepTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1439 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1440 {
1441 return (uint32_t)((READ_BIT(DACx->STMODR,
1442 DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1443 )
1444 >> (DAC_STMODR_STINCTRIGSEL1_Pos + (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1445 ) << DAC_CR_TSEL1_Pos);
1446 }
1447
1448 /**
1449 * @brief Set the output for the selected DAC channel.
1450 * @note This function set several features:
1451 * - mode normal or sample-and-hold
1452 * - buffer
1453 * - connection to GPIO or internal path.
1454 * These features can also be set individually using
1455 * dedicated functions:
1456 * - @ref LL_DAC_SetOutputBuffer()
1457 * - @ref LL_DAC_SetOutputMode()
1458 * - @ref LL_DAC_SetOutputConnection()
1459 * @note On this STM32 series, output connection depends on output mode
1460 * (normal or sample and hold) and output buffer state.
1461 * - if output connection is set to internal path and output buffer
1462 * is enabled (whatever output mode):
1463 * output connection is also connected to GPIO pin
1464 * (both connections to GPIO pin and internal path).
1465 * - if output connection is set to GPIO pin, output buffer
1466 * is disabled, output mode set to sample and hold:
1467 * output connection is also connected to internal path
1468 * (both connections to GPIO pin and internal path).
1469 * @note Mode sample-and-hold requires an external capacitor
1470 * to be connected between DAC channel output and ground.
1471 * Capacitor value depends on load on DAC channel output and
1472 * sample-and-hold timings configured.
1473 * As indication, capacitor typical value is 100nF
1474 * (refer to device datasheet, parameter "CSH").
1475 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
1476 * CR MODE2 LL_DAC_ConfigOutput
1477 * @param DACx DAC instance
1478 * @param DAC_Channel This parameter can be one of the following values:
1479 * @arg @ref LL_DAC_CHANNEL_1
1480 * @arg @ref LL_DAC_CHANNEL_2 (1)
1481 *
1482 * (1) On this STM32 series, parameter not available on all instances.
1483 * Refer to device datasheet for channels availability.
1484 * @param OutputMode This parameter can be one of the following values:
1485 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1486 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1487 * @param OutputBuffer This parameter can be one of the following values:
1488 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1489 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1490 * @param OutputConnection This parameter can be one of the following values:
1491 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1492 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1493 * @retval None
1494 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)1495 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
1496 uint32_t OutputBuffer, uint32_t OutputConnection)
1497 {
1498 MODIFY_REG(DACx->MCR,
1499 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1500 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1501 }
1502
1503 /**
1504 * @brief Set the output mode normal or sample-and-hold
1505 * for the selected DAC channel.
1506 * @note Mode sample-and-hold requires an external capacitor
1507 * to be connected between DAC channel output and ground.
1508 * Capacitor value depends on load on DAC channel output and
1509 * sample-and-hold timings configured.
1510 * As indication, capacitor typical value is 100nF
1511 * (refer to device datasheet, parameter "CSH").
1512 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
1513 * CR MODE2 LL_DAC_SetOutputMode
1514 * @param DACx DAC instance
1515 * @param DAC_Channel This parameter can be one of the following values:
1516 * @arg @ref LL_DAC_CHANNEL_1
1517 * @arg @ref LL_DAC_CHANNEL_2 (1)
1518 *
1519 * (1) On this STM32 series, parameter not available on all instances.
1520 * Refer to device datasheet for channels availability.
1521 * @param OutputMode This parameter can be one of the following values:
1522 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1523 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1524 * @retval None
1525 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)1526 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
1527 {
1528 MODIFY_REG(DACx->MCR,
1529 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1530 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1531 }
1532
1533 /**
1534 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
1535 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
1536 * CR MODE2 LL_DAC_GetOutputMode
1537 * @param DACx DAC instance
1538 * @param DAC_Channel This parameter can be one of the following values:
1539 * @arg @ref LL_DAC_CHANNEL_1
1540 * @arg @ref LL_DAC_CHANNEL_2 (1)
1541 *
1542 * (1) On this STM32 series, parameter not available on all instances.
1543 * Refer to device datasheet for channels availability.
1544 * @retval Returned value can be one of the following values:
1545 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1546 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1547 */
LL_DAC_GetOutputMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1548 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1549 {
1550 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1551 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1552 );
1553 }
1554
1555 /**
1556 * @brief Set the output buffer for the selected DAC channel.
1557 * @note On this STM32 series, when buffer is enabled, its offset can be
1558 * trimmed: factory calibration default values can be
1559 * replaced by user trimming values, using function
1560 * @ref LL_DAC_SetTrimmingValue().
1561 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
1562 * CR MODE2 LL_DAC_SetOutputBuffer
1563 * @param DACx DAC instance
1564 * @param DAC_Channel This parameter can be one of the following values:
1565 * @arg @ref LL_DAC_CHANNEL_1
1566 * @arg @ref LL_DAC_CHANNEL_2 (1)
1567 *
1568 * (1) On this STM32 series, parameter not available on all instances.
1569 * Refer to device datasheet for channels availability.
1570 * @param OutputBuffer This parameter can be one of the following values:
1571 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1572 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1573 * @retval None
1574 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)1575 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1576 {
1577 MODIFY_REG(DACx->MCR,
1578 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1579 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1580 }
1581
1582 /**
1583 * @brief Get the output buffer state for the selected DAC channel.
1584 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
1585 * CR MODE2 LL_DAC_GetOutputBuffer
1586 * @param DACx DAC instance
1587 * @param DAC_Channel This parameter can be one of the following values:
1588 * @arg @ref LL_DAC_CHANNEL_1
1589 * @arg @ref LL_DAC_CHANNEL_2 (1)
1590 *
1591 * (1) On this STM32 series, parameter not available on all instances.
1592 * Refer to device datasheet for channels availability.
1593 * @retval Returned value can be one of the following values:
1594 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1595 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1596 */
LL_DAC_GetOutputBuffer(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1597 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1598 {
1599 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1600 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1601 );
1602 }
1603
1604 /**
1605 * @brief Set the output connection for the selected DAC channel.
1606 * @note On this STM32 series, output connection depends on output mode (normal or
1607 * sample and hold) and output buffer state.
1608 * - if output connection is set to internal path and output buffer
1609 * is enabled (whatever output mode):
1610 * output connection is also connected to GPIO pin
1611 * (both connections to GPIO pin and internal path).
1612 * - if output connection is set to GPIO pin, output buffer
1613 * is disabled, output mode set to sample and hold:
1614 * output connection is also connected to internal path
1615 * (both connections to GPIO pin and internal path).
1616 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1617 * CR MODE2 LL_DAC_SetOutputConnection
1618 * @param DACx DAC instance
1619 * @param DAC_Channel This parameter can be one of the following values:
1620 * @arg @ref LL_DAC_CHANNEL_1
1621 * @arg @ref LL_DAC_CHANNEL_2 (1)
1622 *
1623 * (1) On this STM32 series, parameter not available on all instances.
1624 * Refer to device datasheet for channels availability.
1625 * @param OutputConnection This parameter can be one of the following values:
1626 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1627 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1628 * @retval None
1629 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)1630 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1631 {
1632 MODIFY_REG(DACx->MCR,
1633 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1634 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1635 }
1636
1637 /**
1638 * @brief Get the output connection for the selected DAC channel.
1639 * @note On this STM32 series, output connection depends on output mode (normal or
1640 * sample and hold) and output buffer state.
1641 * - if output connection is set to internal path and output buffer
1642 * is enabled (whatever output mode):
1643 * output connection is also connected to GPIO pin
1644 * (both connections to GPIO pin and internal path).
1645 * - if output connection is set to GPIO pin, output buffer
1646 * is disabled, output mode set to sample and hold:
1647 * output connection is also connected to internal path
1648 * (both connections to GPIO pin and internal path).
1649 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1650 * CR MODE2 LL_DAC_GetOutputConnection
1651 * @param DACx DAC instance
1652 * @param DAC_Channel This parameter can be one of the following values:
1653 * @arg @ref LL_DAC_CHANNEL_1
1654 * @arg @ref LL_DAC_CHANNEL_2 (1)
1655 *
1656 * (1) On this STM32 series, parameter not available on all instances.
1657 * Refer to device datasheet for channels availability.
1658 * @retval Returned value can be one of the following values:
1659 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1660 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1661 */
LL_DAC_GetOutputConnection(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1662 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1663 {
1664 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1665 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1666 );
1667 }
1668
1669 /**
1670 * @brief Set the sample-and-hold timing for the selected DAC channel:
1671 * sample time
1672 * @note Sample time must be set when DAC channel is disabled
1673 * or during DAC operation when DAC channel flag BWSTx is reset,
1674 * otherwise the setting is ignored.
1675 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1676 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1677 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1678 * @param DACx DAC instance
1679 * @param DAC_Channel This parameter can be one of the following values:
1680 * @arg @ref LL_DAC_CHANNEL_1
1681 * @arg @ref LL_DAC_CHANNEL_2 (1)
1682 *
1683 * (1) On this STM32 series, parameter not available on all instances.
1684 * Refer to device datasheet for channels availability.
1685 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1686 * @retval None
1687 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1688 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1689 {
1690 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1691 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1692
1693 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1694 }
1695
1696 /**
1697 * @brief Get the sample-and-hold timing for the selected DAC channel:
1698 * sample time
1699 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1700 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1701 * @param DACx DAC instance
1702 * @param DAC_Channel This parameter can be one of the following values:
1703 * @arg @ref LL_DAC_CHANNEL_1
1704 * @arg @ref LL_DAC_CHANNEL_2 (1)
1705 *
1706 * (1) On this STM32 series, parameter not available on all instances.
1707 * Refer to device datasheet for channels availability.
1708 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1709 */
LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1710 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1711 {
1712 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1713 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1714
1715 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1716 }
1717
1718 /**
1719 * @brief Set the sample-and-hold timing for the selected DAC channel:
1720 * hold time
1721 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1722 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1723 * @param DACx DAC instance
1724 * @param DAC_Channel This parameter can be one of the following values:
1725 * @arg @ref LL_DAC_CHANNEL_1
1726 * @arg @ref LL_DAC_CHANNEL_2 (1)
1727 *
1728 * (1) On this STM32 series, parameter not available on all instances.
1729 * Refer to device datasheet for channels availability.
1730 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1731 * @retval None
1732 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1733 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1734 {
1735 MODIFY_REG(DACx->SHHR,
1736 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1737 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1738 }
1739
1740 /**
1741 * @brief Get the sample-and-hold timing for the selected DAC channel:
1742 * hold time
1743 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1744 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1745 * @param DACx DAC instance
1746 * @param DAC_Channel This parameter can be one of the following values:
1747 * @arg @ref LL_DAC_CHANNEL_1
1748 * @arg @ref LL_DAC_CHANNEL_2 (1)
1749 *
1750 * (1) On this STM32 series, parameter not available on all instances.
1751 * Refer to device datasheet for channels availability.
1752 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1753 */
LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1754 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1755 {
1756 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1757 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1758 );
1759 }
1760
1761 /**
1762 * @brief Set the sample-and-hold timing for the selected DAC channel:
1763 * refresh time
1764 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1765 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1766 * @param DACx DAC instance
1767 * @param DAC_Channel This parameter can be one of the following values:
1768 * @arg @ref LL_DAC_CHANNEL_1
1769 * @arg @ref LL_DAC_CHANNEL_2 (1)
1770 *
1771 * (1) On this STM32 series, parameter not available on all instances.
1772 * Refer to device datasheet for channels availability.
1773 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1774 * @retval None
1775 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1776 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1777 {
1778 MODIFY_REG(DACx->SHRR,
1779 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1780 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1781 }
1782
1783 /**
1784 * @brief Get the sample-and-hold timing for the selected DAC channel:
1785 * refresh time
1786 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1787 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1788 * @param DACx DAC instance
1789 * @param DAC_Channel This parameter can be one of the following values:
1790 * @arg @ref LL_DAC_CHANNEL_1
1791 * @arg @ref LL_DAC_CHANNEL_2 (1)
1792 *
1793 * (1) On this STM32 series, parameter not available on all instances.
1794 * Refer to device datasheet for channels availability.
1795 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1796 */
LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1797 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1798 {
1799 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1800 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1801 );
1802 }
1803
1804 /**
1805 * @brief Set the signed format for the selected DAC channel.
1806 * @note On this STM32 series, signed format can be used to inject
1807 * Q1.15, Q1.11, Q1.7 signed format data to DAC.
1808 * Ex when using 12bits data format (Q1.11 is used):
1809 * 0x800 will output 0v level
1810 * 0xFFF will output mid-scale level
1811 * 0x000 will output mid-scale level
1812 * 0x7FF will output full-scale level
1813 * @rmtoll MCR SINFORMAT1 LL_DAC_SetSignedFormat\n
1814 * MCR SINFORMAT2 LL_DAC_SetSignedFormat
1815 * @param DACx DAC instance
1816 * @param DAC_Channel This parameter can be one of the following values:
1817 * @arg @ref LL_DAC_CHANNEL_1
1818 * @arg @ref LL_DAC_CHANNEL_2 (1)
1819 *
1820 * (1) On this STM32 series, parameter not available on all instances.
1821 * Refer to device datasheet for channels availability.
1822 * @param SignedFormat This parameter can be one of the following values:
1823 * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
1824 * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
1825 * @retval None
1826 */
LL_DAC_SetSignedFormat(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SignedFormat)1827 __STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
1828 {
1829 MODIFY_REG(DACx->MCR,
1830 DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1831 SignedFormat << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1832 }
1833
1834 /**
1835 * @brief Get the signed format state for the selected DAC channel.
1836 * @rmtoll MCR SINFORMAT1 LL_DAC_GetSignedFormat\n
1837 * MCR SINFORMAT2 LL_DAC_GetSignedFormat
1838 * @param DACx DAC instance
1839 * @param DAC_Channel This parameter can be one of the following values:
1840 * @arg @ref LL_DAC_CHANNEL_1
1841 * @arg @ref LL_DAC_CHANNEL_2 (1)
1842 *
1843 * (1) On this STM32 series, parameter not available on all instances.
1844 * Refer to device datasheet for channels availability.
1845 * @retval Returned value can be one of the following values:
1846 * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
1847 * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
1848 */
LL_DAC_GetSignedFormat(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1849 __STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1850 {
1851 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1852 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1853 );
1854 }
1855
1856 /**
1857 * @}
1858 */
1859
1860 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1861 * @{
1862 */
1863
1864 /**
1865 * @brief Enable DAC DMA transfer request of the selected channel.
1866 * @note To configure DMA source address (peripheral address),
1867 * use function @ref LL_DAC_DMA_GetRegAddr().
1868 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1869 * CR DMAEN2 LL_DAC_EnableDMAReq
1870 * @param DACx DAC instance
1871 * @param DAC_Channel This parameter can be one of the following values:
1872 * @arg @ref LL_DAC_CHANNEL_1
1873 * @arg @ref LL_DAC_CHANNEL_2 (1)
1874 *
1875 * (1) On this STM32 series, parameter not available on all instances.
1876 * Refer to device datasheet for channels availability.
1877 * @retval None
1878 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1879 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1880 {
1881 SET_BIT(DACx->CR,
1882 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1883 }
1884
1885 /**
1886 * @brief Disable DAC DMA transfer request of the selected channel.
1887 * @note To configure DMA source address (peripheral address),
1888 * use function @ref LL_DAC_DMA_GetRegAddr().
1889 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1890 * CR DMAEN2 LL_DAC_DisableDMAReq
1891 * @param DACx DAC instance
1892 * @param DAC_Channel This parameter can be one of the following values:
1893 * @arg @ref LL_DAC_CHANNEL_1
1894 * @arg @ref LL_DAC_CHANNEL_2 (1)
1895 *
1896 * (1) On this STM32 series, parameter not available on all instances.
1897 * Refer to device datasheet for channels availability.
1898 * @retval None
1899 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1900 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1901 {
1902 CLEAR_BIT(DACx->CR,
1903 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1904 }
1905
1906 /**
1907 * @brief Get DAC DMA transfer request state of the selected channel.
1908 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1909 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1910 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1911 * @param DACx DAC instance
1912 * @param DAC_Channel This parameter can be one of the following values:
1913 * @arg @ref LL_DAC_CHANNEL_1
1914 * @arg @ref LL_DAC_CHANNEL_2 (1)
1915 *
1916 * (1) On this STM32 series, parameter not available on all instances.
1917 * Refer to device datasheet for channels availability.
1918 * @retval State of bit (1 or 0).
1919 */
LL_DAC_IsDMAReqEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1920 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1921 {
1922 return ((READ_BIT(DACx->CR,
1923 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1924 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1925 }
1926
1927 /**
1928 * @brief Enable DAC DMA Double data mode of the selected channel.
1929 * @rmtoll MCR DMADOUBLE1 LL_DAC_EnableDMADoubleDataMode\n
1930 * MCR DMADOUBLE2 LL_DAC_EnableDMADoubleDataMode
1931 * @param DACx DAC instance
1932 * @param DAC_Channel This parameter can be one of the following values:
1933 * @arg @ref LL_DAC_CHANNEL_1
1934 * @arg @ref LL_DAC_CHANNEL_2 (1)
1935 *
1936 * (1) On this STM32 series, parameter not available on all instances.
1937 * Refer to device datasheet for channels availability.
1938 * @retval None
1939 */
LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1940 __STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1941 {
1942 SET_BIT(DACx->MCR,
1943 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1944 }
1945
1946 /**
1947 * @brief Disable DAC DMA Double data mode of the selected channel.
1948 * @rmtoll MCR DMADOUBLE1 LL_DAC_DisableDMADoubleDataMode\n
1949 * MCR DMADOUBLE2 LL_DAC_DisableDMADoubleDataMode
1950 * @param DACx DAC instance
1951 * @param DAC_Channel This parameter can be one of the following values:
1952 * @arg @ref LL_DAC_CHANNEL_1
1953 * @arg @ref LL_DAC_CHANNEL_2 (1)
1954 *
1955 * (1) On this STM32 series, parameter not available on all instances.
1956 * Refer to device datasheet for channels availability.
1957 * @retval None
1958 */
LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1959 __STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1960 {
1961 CLEAR_BIT(DACx->MCR,
1962 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1963 }
1964
1965 /**
1966 * @brief Get DAC DMA double data mode state of the selected channel.
1967 * (0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled)
1968 * @rmtoll MCR DMADOUBLE1 LL_DAC_IsDMADoubleDataModeEnabled\n
1969 * MCR DMADOUBLE2 LL_DAC_IsDMADoubleDataModeEnabled
1970 * @param DACx DAC instance
1971 * @param DAC_Channel This parameter can be one of the following values:
1972 * @arg @ref LL_DAC_CHANNEL_1
1973 * @arg @ref LL_DAC_CHANNEL_2 (1)
1974 *
1975 * (1) On this STM32 series, parameter not available on all instances.
1976 * Refer to device datasheet for channels availability.
1977 * @retval State of bit (1 or 0).
1978 */
LL_DAC_IsDMADoubleDataModeEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1979 __STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1980 {
1981 return ((READ_BIT(DACx->MCR,
1982 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1983 == (DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1984 }
1985
1986 /**
1987 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1988 * DAC register address from DAC instance and a list of DAC registers
1989 * intended to be used (most commonly) with DMA transfer.
1990 * @note These DAC registers are data holding registers:
1991 * when DAC conversion is requested, DAC generates a DMA transfer
1992 * request to have data available in DAC data holding registers.
1993 * @note This macro is intended to be used with LL DMA driver, refer to
1994 * function "LL_DMA_ConfigAddresses()".
1995 * Example:
1996 * LL_DMA_ConfigAddresses(DMA1,
1997 * LL_DMA_CHANNEL_1,
1998 * (uint32_t)&< array or variable >,
1999 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
2000 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
2001 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
2002 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
2003 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
2004 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
2005 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
2006 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
2007 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
2008 * @param DACx DAC instance
2009 * @param DAC_Channel This parameter can be one of the following values:
2010 * @arg @ref LL_DAC_CHANNEL_1
2011 * @arg @ref LL_DAC_CHANNEL_2 (1)
2012 *
2013 * (1) On this STM32 series, parameter not available on all instances.
2014 * Refer to device datasheet for channels availability.
2015 * @param Register This parameter can be one of the following values:
2016 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
2017 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
2018 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
2019 * @retval DAC register address
2020 */
LL_DAC_DMA_GetRegAddr(const DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)2021 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
2022 {
2023 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
2024 /* DAC channel selected. */
2025 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
2026 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
2027 }
2028 /**
2029 * @}
2030 */
2031
2032 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
2033 * @{
2034 */
2035
2036 /**
2037 * @brief Enable DAC selected channel.
2038 * @rmtoll CR EN1 LL_DAC_Enable\n
2039 * CR EN2 LL_DAC_Enable
2040 * @note After enable from off state, DAC channel requires a delay
2041 * for output voltage to reach accuracy +/- 1 LSB.
2042 * Refer to device datasheet, parameter "tWAKEUP".
2043 * @param DACx DAC instance
2044 * @param DAC_Channel This parameter can be one of the following values:
2045 * @arg @ref LL_DAC_CHANNEL_1
2046 * @arg @ref LL_DAC_CHANNEL_2 (1)
2047 *
2048 * (1) On this STM32 series, parameter not available on all instances.
2049 * Refer to device datasheet for channels availability.
2050 * @retval None
2051 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)2052 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2053 {
2054 SET_BIT(DACx->CR,
2055 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
2056 }
2057
2058 /**
2059 * @brief Disable DAC selected channel.
2060 * @rmtoll CR EN1 LL_DAC_Disable\n
2061 * CR EN2 LL_DAC_Disable
2062 * @param DACx DAC instance
2063 * @param DAC_Channel This parameter can be one of the following values:
2064 * @arg @ref LL_DAC_CHANNEL_1
2065 * @arg @ref LL_DAC_CHANNEL_2 (1)
2066 *
2067 * (1) On this STM32 series, parameter not available on all instances.
2068 * Refer to device datasheet for channels availability.
2069 * @retval None
2070 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)2071 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2072 {
2073 CLEAR_BIT(DACx->CR,
2074 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
2075 }
2076
2077 /**
2078 * @brief Get DAC enable state of the selected channel.
2079 * (0: DAC channel is disabled, 1: DAC channel is enabled)
2080 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
2081 * CR EN2 LL_DAC_IsEnabled
2082 * @param DACx DAC instance
2083 * @param DAC_Channel This parameter can be one of the following values:
2084 * @arg @ref LL_DAC_CHANNEL_1
2085 * @arg @ref LL_DAC_CHANNEL_2 (1)
2086 *
2087 * (1) On this STM32 series, parameter not available on all instances.
2088 * Refer to device datasheet for channels availability.
2089 * @retval State of bit (1 or 0).
2090 */
LL_DAC_IsEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)2091 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
2092 {
2093 return ((READ_BIT(DACx->CR,
2094 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
2095 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
2096 }
2097
2098 /**
2099 * @brief Get DAC ready for conversion state of the selected channel.
2100 * (0: DAC channel is not ready, 1: DAC channel is ready)
2101 * @rmtoll SR DAC1RDY LL_DAC_IsReady\n
2102 * SR DAC2RDY LL_DAC_IsReady
2103 * @param DACx DAC instance
2104 * @param DAC_Channel This parameter can be one of the following values:
2105 * @arg @ref LL_DAC_CHANNEL_1
2106 * @arg @ref LL_DAC_CHANNEL_2 (1)
2107 *
2108 * (1) On this STM32 series, parameter not available on all instances.
2109 * Refer to device datasheet for channels availability.
2110 * @retval State of bit (1 or 0).
2111 */
LL_DAC_IsReady(const DAC_TypeDef * DACx,uint32_t DAC_Channel)2112 __STATIC_INLINE uint32_t LL_DAC_IsReady(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
2113 {
2114 return ((READ_BIT(DACx->SR,
2115 DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
2116 == (DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
2117 }
2118
2119 /**
2120 * @brief Enable DAC trigger of the selected channel.
2121 * @note - If DAC trigger is disabled, DAC conversion is performed
2122 * automatically once the data holding register is updated,
2123 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
2124 * @ref LL_DAC_ConvertData12RightAligned(), ...
2125 * - If DAC trigger is enabled, DAC conversion is performed
2126 * only when a hardware of software trigger event is occurring.
2127 * Select trigger source using
2128 * function @ref LL_DAC_SetTriggerSource().
2129 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
2130 * CR TEN2 LL_DAC_EnableTrigger
2131 * @param DACx DAC instance
2132 * @param DAC_Channel This parameter can be one of the following values:
2133 * @arg @ref LL_DAC_CHANNEL_1
2134 * @arg @ref LL_DAC_CHANNEL_2 (1)
2135 *
2136 * (1) On this STM32 series, parameter not available on all instances.
2137 * Refer to device datasheet for channels availability.
2138 * @retval None
2139 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)2140 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2141 {
2142 SET_BIT(DACx->CR,
2143 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
2144 }
2145
2146 /**
2147 * @brief Disable DAC trigger of the selected channel.
2148 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
2149 * CR TEN2 LL_DAC_DisableTrigger
2150 * @param DACx DAC instance
2151 * @param DAC_Channel This parameter can be one of the following values:
2152 * @arg @ref LL_DAC_CHANNEL_1
2153 * @arg @ref LL_DAC_CHANNEL_2 (1)
2154 *
2155 * (1) On this STM32 series, parameter not available on all instances.
2156 * Refer to device datasheet for channels availability.
2157 * @retval None
2158 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)2159 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2160 {
2161 CLEAR_BIT(DACx->CR,
2162 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
2163 }
2164
2165 /**
2166 * @brief Get DAC trigger state of the selected channel.
2167 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
2168 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
2169 * CR TEN2 LL_DAC_IsTriggerEnabled
2170 * @param DACx DAC instance
2171 * @param DAC_Channel This parameter can be one of the following values:
2172 * @arg @ref LL_DAC_CHANNEL_1
2173 * @arg @ref LL_DAC_CHANNEL_2 (1)
2174 *
2175 * (1) On this STM32 series, parameter not available on all instances.
2176 * Refer to device datasheet for channels availability.
2177 * @retval State of bit (1 or 0).
2178 */
LL_DAC_IsTriggerEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)2179 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
2180 {
2181 return ((READ_BIT(DACx->CR,
2182 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
2183 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
2184 }
2185
2186 /**
2187 * @brief Trig DAC conversion by software for the selected DAC channel.
2188 * @note Preliminarily, DAC trigger must be set to software trigger
2189 * using function
2190 * @ref LL_DAC_Init()
2191 * @ref LL_DAC_SetTriggerSource()
2192 * @ref LL_DAC_SetWaveSawtoothResetTriggerSource() (1)
2193 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
2194 * and DAC trigger must be enabled using
2195 * function @ref LL_DAC_EnableTrigger().
2196 *
2197 * (1) In case, Sawtooth wave generation has been configured.
2198 * @note For devices featuring DAC with 2 channels: this function
2199 * can perform a SW start of both DAC channels simultaneously.
2200 * Two channels can be selected as parameter.
2201 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
2202 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
2203 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
2204 * @param DACx DAC instance
2205 * @param DAC_Channel This parameter can a combination of the following values:
2206 * @arg @ref LL_DAC_CHANNEL_1
2207 * @arg @ref LL_DAC_CHANNEL_2 (1)
2208 *
2209 * (1) On this STM32 series, parameter not available on all instances.
2210 * Refer to device datasheet for channels availability.
2211 * @retval None
2212 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)2213 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2214 {
2215 SET_BIT(DACx->SWTRIGR,
2216 (DAC_Channel & DAC_SWTR_CHX_MASK));
2217 }
2218
2219 /**
2220 * @brief Trig DAC conversion by secondary software trigger for the selected DAC channel.
2221 * @note Preliminarily, DAC secondary trigger must be set to software trigger
2222 * using function
2223 * @ref LL_DAC_Init()
2224 * @ref LL_DAC_SetWaveSawtoothStepTriggerSource() (1)
2225 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
2226 * and DAC trigger must be enabled using
2227 * function @ref LL_DAC_EnableTrigger().
2228 *
2229 * (1) In case, Sawtooth wave generation has been configured.
2230 * @note For devices featuring DAC with 2 channels: this function
2231 * can perform a SW start of both DAC channels simultaneously.
2232 * Two channels can be selected as parameter.
2233 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
2234 * @rmtoll SWTRIGR SWTRIGB1 LL_DAC_TrigSWConversion2\n
2235 * SWTRIGR SWTRIGB2 LL_DAC_TrigSWConversion2
2236 * @param DACx DAC instance
2237 * @param DAC_Channel This parameter can a combination of the following values:
2238 * @arg @ref LL_DAC_CHANNEL_1
2239 * @arg @ref LL_DAC_CHANNEL_2 (1)
2240 *
2241 * (1) On this STM32 series, parameter not available on all instances.
2242 * Refer to device datasheet for channels availability.
2243 * @retval None
2244 */
LL_DAC_TrigSWConversion2(DAC_TypeDef * DACx,uint32_t DAC_Channel)2245 __STATIC_INLINE void LL_DAC_TrigSWConversion2(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2246 {
2247 SET_BIT(DACx->SWTRIGR,
2248 (DAC_Channel & DAC_SWTRB_CHX_MASK));
2249 }
2250
2251 /**
2252 * @brief Set the data to be loaded in the data holding register
2253 * in format 12 bits left alignment (LSB aligned on bit 0),
2254 * for the selected DAC channel.
2255 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
2256 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
2257 * @param DACx DAC instance
2258 * @param DAC_Channel This parameter can be one of the following values:
2259 * @arg @ref LL_DAC_CHANNEL_1
2260 * @arg @ref LL_DAC_CHANNEL_2 (1)
2261 *
2262 * (1) On this STM32 series, parameter not available on all instances.
2263 * Refer to device datasheet for channels availability.
2264 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
2265 * @retval None
2266 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)2267 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
2268 {
2269 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
2270 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
2271
2272 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
2273 }
2274
2275 /**
2276 * @brief Set the data to be loaded in the data holding register
2277 * in format 12 bits left alignment (MSB aligned on bit 15),
2278 * for the selected DAC channel.
2279 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
2280 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
2281 * @param DACx DAC instance
2282 * @param DAC_Channel This parameter can be one of the following values:
2283 * @arg @ref LL_DAC_CHANNEL_1
2284 * @arg @ref LL_DAC_CHANNEL_2 (1)
2285 *
2286 * (1) On this STM32 series, parameter not available on all instances.
2287 * Refer to device datasheet for channels availability.
2288 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
2289 * @retval None
2290 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)2291 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
2292 {
2293 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
2294 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
2295
2296 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
2297 }
2298
2299 /**
2300 * @brief Set the data to be loaded in the data holding register
2301 * in format 8 bits left alignment (LSB aligned on bit 0),
2302 * for the selected DAC channel.
2303 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
2304 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
2305 * @param DACx DAC instance
2306 * @param DAC_Channel This parameter can be one of the following values:
2307 * @arg @ref LL_DAC_CHANNEL_1
2308 * @arg @ref LL_DAC_CHANNEL_2 (1)
2309 *
2310 * (1) On this STM32 series, parameter not available on all instances.
2311 * Refer to device datasheet for channels availability.
2312 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2313 * @retval None
2314 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)2315 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
2316 {
2317 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
2318 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
2319
2320 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
2321 }
2322
2323
2324 /**
2325 * @brief Set the data to be loaded in the data holding register
2326 * in format 12 bits left alignment (LSB aligned on bit 0),
2327 * for both DAC channels.
2328 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
2329 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
2330 * @param DACx DAC instance
2331 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
2332 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
2333 * @retval None
2334 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)2335 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
2336 uint32_t DataChannel2)
2337 {
2338 MODIFY_REG(DACx->DHR12RD,
2339 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
2340 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
2341 }
2342
2343 /**
2344 * @brief Set the data to be loaded in the data holding register
2345 * in format 12 bits left alignment (MSB aligned on bit 15),
2346 * for both DAC channels.
2347 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
2348 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
2349 * @param DACx DAC instance
2350 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
2351 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
2352 * @retval None
2353 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)2354 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
2355 uint32_t DataChannel2)
2356 {
2357 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
2358 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
2359 /* the 4 LSB must be taken into account for the shift value. */
2360 MODIFY_REG(DACx->DHR12LD,
2361 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
2362 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
2363 }
2364
2365 /**
2366 * @brief Set the data to be loaded in the data holding register
2367 * in format 8 bits left alignment (LSB aligned on bit 0),
2368 * for both DAC channels.
2369 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
2370 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
2371 * @param DACx DAC instance
2372 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
2373 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
2374 * @retval None
2375 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)2376 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
2377 uint32_t DataChannel2)
2378 {
2379 MODIFY_REG(DACx->DHR8RD,
2380 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
2381 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
2382 }
2383
2384
2385 /**
2386 * @brief Retrieve output data currently generated for the selected DAC channel.
2387 * @note Whatever alignment and resolution settings
2388 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
2389 * @ref LL_DAC_ConvertData12RightAligned(), ...),
2390 * output data format is 12 bits right aligned (LSB aligned on bit 0).
2391 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
2392 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
2393 * @param DACx DAC instance
2394 * @param DAC_Channel This parameter can be one of the following values:
2395 * @arg @ref LL_DAC_CHANNEL_1
2396 * @arg @ref LL_DAC_CHANNEL_2 (1)
2397 *
2398 * (1) On this STM32 series, parameter not available on all instances.
2399 * Refer to device datasheet for channels availability.
2400 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2401 */
LL_DAC_RetrieveOutputData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)2402 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
2403 {
2404 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
2405 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
2406
2407 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
2408 }
2409
2410 /**
2411 * @}
2412 */
2413
2414 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
2415 * @{
2416 */
2417
2418 /**
2419 * @brief Get DAC calibration offset flag for DAC channel 1
2420 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
2421 * @param DACx DAC instance
2422 * @retval State of bit (1 or 0).
2423 */
LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef * DACx)2424 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
2425 {
2426 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
2427 }
2428
2429
2430 /**
2431 * @brief Get DAC calibration offset flag for DAC channel 2
2432 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
2433 * @param DACx DAC instance
2434 * @retval State of bit (1 or 0).
2435 */
LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef * DACx)2436 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
2437 {
2438 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
2439 }
2440
2441
2442 /**
2443 * @brief Get DAC busy writing sample time flag for DAC channel 1
2444 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
2445 * @param DACx DAC instance
2446 * @retval State of bit (1 or 0).
2447 */
LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef * DACx)2448 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
2449 {
2450 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
2451 }
2452
2453 /**
2454 * @brief Get DAC busy writing sample time flag for DAC channel 2
2455 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
2456 * @param DACx DAC instance
2457 * @retval State of bit (1 or 0).
2458 */
LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef * DACx)2459 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
2460 {
2461 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
2462 }
2463
2464
2465 /**
2466 * @brief Get DAC ready status flag for DAC channel 1
2467 * @rmtoll SR DAC1RDY LL_DAC_IsActiveFlag_DAC1RDY
2468 * @param DACx DAC instance
2469 * @retval State of bit (1 or 0).
2470 */
LL_DAC_IsActiveFlag_DAC1RDY(const DAC_TypeDef * DACx)2471 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(const DAC_TypeDef *DACx)
2472 {
2473 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL);
2474 }
2475
2476
2477 /**
2478 * @brief Get DAC ready status flag for DAC channel 2
2479 * @rmtoll SR DAC2RDY LL_DAC_IsActiveFlag_DAC2RDY
2480 * @param DACx DAC instance
2481 * @retval State of bit (1 or 0).
2482 */
LL_DAC_IsActiveFlag_DAC2RDY(const DAC_TypeDef * DACx)2483 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(const DAC_TypeDef *DACx)
2484 {
2485 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL);
2486 }
2487
2488
2489 /**
2490 * @brief Get DAC output register status flag for DAC channel 1
2491 * @rmtoll SR DORSTAT1 LL_DAC_IsActiveFlag_DORSTAT1
2492 * @param DACx DAC instance
2493 * @retval State of bit (1 or 0).
2494 */
LL_DAC_IsActiveFlag_DORSTAT1(const DAC_TypeDef * DACx)2495 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(const DAC_TypeDef *DACx)
2496 {
2497 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL);
2498 }
2499
2500
2501 /**
2502 * @brief Get DAC output register status flag for DAC channel 2
2503 * @rmtoll SR DORSTAT2 LL_DAC_IsActiveFlag_DORSTAT2
2504 * @param DACx DAC instance
2505 * @retval State of bit (1 or 0).
2506 */
LL_DAC_IsActiveFlag_DORSTAT2(const DAC_TypeDef * DACx)2507 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(const DAC_TypeDef *DACx)
2508 {
2509 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL);
2510 }
2511
2512 /**
2513 * @brief Get DAC underrun flag for DAC channel 1
2514 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
2515 * @param DACx DAC instance
2516 * @retval State of bit (1 or 0).
2517 */
LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef * DACx)2518 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
2519 {
2520 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
2521 }
2522
2523
2524 /**
2525 * @brief Get DAC underrun flag for DAC channel 2
2526 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
2527 * @param DACx DAC instance
2528 * @retval State of bit (1 or 0).
2529 */
LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef * DACx)2530 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
2531 {
2532 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
2533 }
2534
2535
2536 /**
2537 * @brief Clear DAC underrun flag for DAC channel 1
2538 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
2539 * @param DACx DAC instance
2540 * @retval None
2541 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)2542 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
2543 {
2544 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
2545 }
2546
2547
2548 /**
2549 * @brief Clear DAC underrun flag for DAC channel 2
2550 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
2551 * @param DACx DAC instance
2552 * @retval None
2553 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)2554 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
2555 {
2556 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
2557 }
2558
2559
2560 /**
2561 * @}
2562 */
2563
2564 /** @defgroup DAC_LL_EF_IT_Management IT management
2565 * @{
2566 */
2567
2568 /**
2569 * @brief Enable DMA underrun interrupt for DAC channel 1
2570 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
2571 * @param DACx DAC instance
2572 * @retval None
2573 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)2574 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
2575 {
2576 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
2577 }
2578
2579
2580 /**
2581 * @brief Enable DMA underrun interrupt for DAC channel 2
2582 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
2583 * @param DACx DAC instance
2584 * @retval None
2585 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)2586 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
2587 {
2588 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
2589 }
2590
2591
2592 /**
2593 * @brief Disable DMA underrun interrupt for DAC channel 1
2594 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
2595 * @param DACx DAC instance
2596 * @retval None
2597 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)2598 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
2599 {
2600 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
2601 }
2602
2603
2604 /**
2605 * @brief Disable DMA underrun interrupt for DAC channel 2
2606 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
2607 * @param DACx DAC instance
2608 * @retval None
2609 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)2610 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
2611 {
2612 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
2613 }
2614
2615
2616 /**
2617 * @brief Get DMA underrun interrupt for DAC channel 1
2618 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
2619 * @param DACx DAC instance
2620 * @retval State of bit (1 or 0).
2621 */
LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef * DACx)2622 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
2623 {
2624 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
2625 }
2626
2627
2628 /**
2629 * @brief Get DMA underrun interrupt for DAC channel 2
2630 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
2631 * @param DACx DAC instance
2632 * @retval State of bit (1 or 0).
2633 */
LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef * DACx)2634 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
2635 {
2636 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
2637 }
2638
2639
2640 /**
2641 * @}
2642 */
2643
2644 #if defined(USE_FULL_LL_DRIVER)
2645 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
2646 * @{
2647 */
2648
2649 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
2650 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
2651 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
2652
2653 /**
2654 * @}
2655 */
2656 #endif /* USE_FULL_LL_DRIVER */
2657
2658 /**
2659 * @}
2660 */
2661
2662 /**
2663 * @}
2664 */
2665
2666 #endif /* DAC1 || DAC2 || DAC3 || DAC4 */
2667
2668 /**
2669 * @}
2670 */
2671
2672 #ifdef __cplusplus
2673 }
2674 #endif
2675
2676 #endif /* STM32G4xx_LL_DAC_H */
2677
