1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ##### RCC Limitations #####
19 ==============================================================================
20 [..]
21 A delay between an RCC peripheral clock enable and the effective peripheral
22 enabling should be taken into account in order to manage the peripheral read/write
23 from/to registers.w<
24 (+) This delay depends on the peripheral mapping.
25 (++) AHB & APB peripherals, 1 dummy read is necessary
26
27 [..]
28 Workarounds:
29 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
30 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
31
32 @endverbatim
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32WLxx_LL_BUS_H
38 #define __STM32WLxx_LL_BUS_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32wlxx.h"
46
47 /** @addtogroup STM32WLxx_LL_Driver
48 * @{
49 */
50
51 #if defined(RCC)
52
53 /** @defgroup BUS_LL BUS
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61
62 /* Private macros ------------------------------------------------------------*/
63
64 /* Exported types ------------------------------------------------------------*/
65
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
68 * @{
69 */
70
71 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
72 * @{
73 */
74 #define LL_AHB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)
75 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
76 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
77 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
78 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
79 /**
80 * @}
81 */
82
83 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
84 * @{
85 */
86 #define LL_AHB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)
87 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
88 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
89 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
90 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
91 /**
92 * @}
93 */
94
95 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
96 * @{
97 */
98 #define LL_AHB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)
99 #define LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN
100 #define LL_AHB3_GRP1_PERIPH_AES RCC_AHB3ENR_AESEN
101 #define LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN
102 #define LL_AHB3_GRP1_PERIPH_HSEM RCC_AHB3ENR_HSEMEN
103 #if defined(DUAL_CORE)
104 #define LL_AHB3_GRP1_PERIPH_IPCC RCC_AHB3ENR_IPCCEN
105 #endif /* DUAL_CORE */
106 #define LL_AHB3_GRP1_PERIPH_SRAM1 RCC_AHB3SMENR_SRAM1SMEN
107 #define LL_AHB3_GRP1_PERIPH_SRAM2 RCC_AHB3SMENR_SRAM2SMEN
108 #define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3ENR_FLASHEN
109 /**
110 * @}
111 */
112
113 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
114 * @{
115 */
116 #define LL_APB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)
117 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
118 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
119 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
120 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
121 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
122 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
123 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
124 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
125 #define LL_APB1_GRP1_PERIPH_DAC RCC_APB1ENR1_DACEN
126 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
127 /**
128 * @}
129 */
130
131
132 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
133 * @{
134 */
135 #define LL_APB1_GRP2_PERIPH_ALL (0xFFFFFFFFU)
136 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
137 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
138 #define LL_APB1_GRP2_PERIPH_LPTIM3 RCC_APB1ENR2_LPTIM3EN
139 /**
140 * @}
141 */
142
143 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
144 * @{
145 */
146 #define LL_APB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)
147 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2ENR_ADCEN
148 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
149 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
150 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
151 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
152 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
153 /**
154 * @}
155 */
156
157 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
158 * @{
159 */
160 #define LL_APB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)
161 #define LL_APB3_GRP1_PERIPH_SUBGHZSPI RCC_APB3ENR_SUBGHZSPIEN
162 /**
163 * @}
164 */
165
166 #if defined(DUAL_CORE)
167 /** @defgroup BUS_LL_EC_C2_AHB1_GRP1_PERIPH C2 AHB1 GRP1 PERIPH
168 * @{
169 */
170 #define LL_C2_AHB1_GRP1_PERIPH_DMA1 RCC_C2AHB1ENR_DMA1EN
171 #define LL_C2_AHB1_GRP1_PERIPH_DMA2 RCC_C2AHB1ENR_DMA2EN
172 #define LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 RCC_C2AHB1ENR_DMAMUX1EN
173 #define LL_C2_AHB1_GRP1_PERIPH_CRC RCC_C2AHB1ENR_CRCEN
174 /**
175 * @}
176 */
177
178
179 /** @defgroup BUS_LL_EC_C2_AHB2_GRP1_PERIPH C2 AHB2 GRP1 PERIPH
180 * @{
181 */
182 #define LL_C2_AHB2_GRP1_PERIPH_GPIOA RCC_C2AHB2ENR_GPIOAEN
183 #define LL_C2_AHB2_GRP1_PERIPH_GPIOB RCC_C2AHB2ENR_GPIOBEN
184 #define LL_C2_AHB2_GRP1_PERIPH_GPIOC RCC_C2AHB2ENR_GPIOCEN
185 #define LL_C2_AHB2_GRP1_PERIPH_GPIOH RCC_C2AHB2ENR_GPIOHEN
186 /**
187 * @}
188 */
189
190
191 /** @defgroup BUS_LL_EC_C2_AHB3_GRP1_PERIPH C2 AHB3 GRP1 PERIPH
192 * @{
193 */
194 #define LL_C2_AHB3_GRP1_PERIPH_PKA RCC_C2AHB3ENR_PKAEN
195 #define LL_C2_AHB3_GRP1_PERIPH_AES RCC_C2AHB3ENR_AESEN
196 #define LL_C2_AHB3_GRP1_PERIPH_RNG RCC_C2AHB3ENR_RNGEN
197 #define LL_C2_AHB3_GRP1_PERIPH_HSEM RCC_C2AHB3ENR_HSEMEN
198 #define LL_C2_AHB3_GRP1_PERIPH_IPCC RCC_C2AHB3ENR_IPCCEN
199 #define LL_C2_AHB3_GRP1_PERIPH_FLASH RCC_C2AHB3ENR_FLASHEN
200 #define LL_C2_AHB3_GRP1_PERIPH_SRAM1 RCC_C2AHB3SMENR_SRAM1SMEN
201 #define LL_C2_AHB3_GRP1_PERIPH_SRAM2 RCC_C2AHB3SMENR_SRAM2SMEN
202 /**
203 * @}
204 */
205
206
207 /** @defgroup BUS_LL_EC_C2_APB1_GRP1_PERIPH C2 APB1 GRP1 PERIPH
208 * @{
209 */
210 #define LL_C2_APB1_GRP1_PERIPH_TIM2 RCC_C2APB1ENR1_TIM2EN
211 #define LL_C2_APB1_GRP1_PERIPH_RTCAPB RCC_C2APB1ENR1_RTCAPBEN
212 #define LL_C2_APB1_GRP1_PERIPH_SPI2 RCC_C2APB1ENR1_SPI2EN
213 #define LL_C2_APB1_GRP1_PERIPH_USART2 RCC_C2APB1ENR1_USART2EN
214 #define LL_C2_APB1_GRP1_PERIPH_I2C1 RCC_C2APB1ENR1_I2C1EN
215 #define LL_C2_APB1_GRP1_PERIPH_I2C2 RCC_C2APB1ENR1_I2C2EN
216 #define LL_C2_APB1_GRP1_PERIPH_I2C3 RCC_C2APB1ENR1_I2C3EN
217 #define LL_C2_APB1_GRP1_PERIPH_DAC RCC_C2APB1ENR1_DACEN
218 #define LL_C2_APB1_GRP1_PERIPH_LPTIM1 RCC_C2APB1ENR1_LPTIM1EN
219 /**
220 * @}
221 */
222
223
224 /** @defgroup BUS_LL_EC_C2_APB1_GRP2_PERIPH C2 APB1 GRP2 PERIPH
225 * @{
226 */
227 #define LL_C2_APB1_GRP2_PERIPH_LPUART1 RCC_C2APB1ENR2_LPUART1EN
228 #define LL_C2_APB1_GRP2_PERIPH_LPTIM2 RCC_C2APB1ENR2_LPTIM2EN
229 #define LL_C2_APB1_GRP2_PERIPH_LPTIM3 RCC_C2APB1ENR2_LPTIM3EN
230 /**
231 * @}
232 */
233
234
235 /** @defgroup BUS_LL_EC_C2_APB2_GRP1_PERIPH C2 APB2 GRP1 PERIPH
236 * @{
237 */
238 #define LL_C2_APB2_GRP1_PERIPH_ADC RCC_C2APB2ENR_ADCEN
239 #define LL_C2_APB2_GRP1_PERIPH_TIM1 RCC_C2APB2ENR_TIM1EN
240 #define LL_C2_APB2_GRP1_PERIPH_SPI1 RCC_C2APB2ENR_SPI1EN
241 #define LL_C2_APB2_GRP1_PERIPH_USART1 RCC_C2APB2ENR_USART1EN
242 #define LL_C2_APB2_GRP1_PERIPH_TIM16 RCC_C2APB2ENR_TIM16EN
243 #define LL_C2_APB2_GRP1_PERIPH_TIM17 RCC_C2APB2ENR_TIM17EN
244 /**
245 * @}
246 */
247
248
249 /** @defgroup BUS_LL_EC_C2_APB3_GRP1_PERIPH C2 APB3 GRP1 PERIPH
250 * @{
251 */
252 #define LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI RCC_C2APB3ENR_SUBGHZSPIEN
253 /**
254 * @}
255 */
256 #endif /* DUAL_CORE */
257
258 /**
259 * @}
260 */
261
262 /* Exported macro ------------------------------------------------------------*/
263
264 /* Exported functions --------------------------------------------------------*/
265
266 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
267 * @{
268 */
269
270 /** @defgroup BUS_LL_EF_AHB1 AHB1
271 * @{
272 */
273
274 /**
275 * @brief Enable AHB1 peripherals clock.
276 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
277 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
278 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n
279 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
280 * @param Periphs This parameter can be a combination of the following values:
281 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
282 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
283 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
284 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
285 * @retval None
286 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)287 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
288 {
289 __IO uint32_t tmpreg;
290 SET_BIT(RCC->AHB1ENR, Periphs);
291 /* Delay after an RCC peripheral clock enabling */
292 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
293 (void)tmpreg;
294 }
295
296 /**
297 * @brief Check if AHB1 peripheral clock is enabled or not
298 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
299 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
300 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n
301 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
302 * @param Periphs This parameter can be a combination of the following values:
303 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
304 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
305 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
306 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
307 * @retval uint32_t
308 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)309 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
310 {
311 return ((READ_BIT(RCC->AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
312 }
313
314 /**
315 * @brief Disable AHB1 peripherals clock.
316 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
317 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
318 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n
319 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
320 * @param Periphs This parameter can be a combination of the following values:
321 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
322 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
323 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
324 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
325 * @retval None
326 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)327 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
328 {
329 CLEAR_BIT(RCC->AHB1ENR, Periphs);
330 }
331
332 /**
333 * @brief Force AHB1 peripherals reset.
334 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
335 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
336 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n
337 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
338 * @param Periphs This parameter can be a combination of the following values:
339 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
340 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
341 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
342 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
343 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
344 * @retval None
345 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)346 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
347 {
348 SET_BIT(RCC->AHB1RSTR, Periphs);
349 }
350
351 /**
352 * @brief Release AHB1 peripherals reset.
353 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
354 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
355 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n
356 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
357 * @param Periphs This parameter can be a combination of the following values:
358 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
359 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
360 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
361 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
362 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
363 * @retval None
364 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)365 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
366 {
367 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
368 }
369
370 /**
371 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
372 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockSleep\n
373 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockSleep\n
374 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockSleep\n
375 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n
376 * @param Periphs This parameter can be a combination of the following values:
377 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
378 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
379 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
380 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
381 * @retval None
382 */
LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)383 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
384 {
385 __IO uint32_t tmpreg;
386 SET_BIT(RCC->AHB1SMENR, Periphs);
387 /* Delay after an RCC peripheral clock enabling */
388 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
389 (void)tmpreg;
390 }
391
392 /**
393 * @brief Check if AHB1 peripheral clock is enabled by the clock gating during CPU1 CSleep mode
394 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_IsEnabledClockSleep\n
395 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_IsEnabledClockSleep\n
396 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_IsEnabledClockSleep\n
397 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockSleep
398 * @param Periphs This parameter can be a combination of the following values:
399 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
400 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
401 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
402 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
403 * @retval uint32_t
404 */
LL_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)405 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)
406 {
407 return ((READ_BIT(RCC->AHB1SMENR, Periphs) == (Periphs)) ? 1UL : 0UL);
408 }
409
410 /**
411 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
412 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockSleep\n
413 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockSleep\n
414 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockSleep\n
415 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n
416 * @param Periphs This parameter can be a combination of the following values:
417 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
418 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
419 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
420 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
421 * @retval None
422 */
LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)423 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
424 {
425 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
426 }
427
428 /**
429 * @}
430 */
431
432 /** @defgroup BUS_LL_EF_AHB2 AHB2
433 * @{
434 */
435
436 /**
437 * @brief Enable AHB2 peripherals clock.
438 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
439 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
440 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
441 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
442 * @param Periphs This parameter can be a combination of the following values:
443 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
444 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
445 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
446 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
447 * @retval None
448 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)449 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
450 {
451 __IO uint32_t tmpreg;
452 SET_BIT(RCC->AHB2ENR, Periphs);
453 /* Delay after an RCC peripheral clock enabling */
454 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
455 (void)tmpreg;
456 }
457
458 /**
459 * @brief Check if AHB2 peripheral clock is enabled or not
460 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
461 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
462 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
463 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
464 * @param Periphs This parameter can be a combination of the following values:
465 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
466 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
467 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
468 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
469 * @retval uint32_t
470 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)471 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
472 {
473 return ((READ_BIT(RCC->AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
474 }
475
476 /**
477 * @brief Disable AHB2 peripherals clock.
478 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
479 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
480 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
481 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
482 * @param Periphs This parameter can be a combination of the following values:
483 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
484 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
485 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
486 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
487 * @retval None
488 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)489 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
490 {
491 CLEAR_BIT(RCC->AHB2ENR, Periphs);
492 }
493
494 /**
495 * @brief Force AHB2 peripherals reset.
496 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
497 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
498 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
499 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset
500 * @param Periphs This parameter can be a combination of the following values:
501 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
502 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
503 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
504 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
505 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
506 * @retval None
507 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)508 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
509 {
510 SET_BIT(RCC->AHB2RSTR, Periphs);
511 }
512
513 /**
514 * @brief Release AHB2 peripherals reset.
515 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
516 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
517 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
518 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
519 * @param Periphs This parameter can be a combination of the following values:
520 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
521 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
522 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
523 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
524 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
525 * @retval None
526 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)527 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
528 {
529 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
530 }
531
532 /**
533 * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode.
534 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockSleep\n
535 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockSleep\n
536 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockSleep\n
537 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockSleep\n
538 * @param Periphs This parameter can be a combination of the following values:
539 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
540 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
541 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
542 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
543 * @retval None
544 */
LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)545 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
546 {
547 __IO uint32_t tmpreg;
548 SET_BIT(RCC->AHB2SMENR, Periphs);
549 /* Delay after an RCC peripheral clock enabling */
550 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
551 (void)tmpreg;
552 }
553
554 /**
555 * @brief Check if AHB2 peripheral clock is enabled by the clock gating during CPU1 CSleep mode
556 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_IsEnabledClockSleep\n
557 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_IsEnabledClockSleep\n
558 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_IsEnabledClockSleep\n
559 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockSleep
560 * @param Periphs This parameter can be a combination of the following values:
561 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
562 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
563 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
564 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
565 * @retval uint32_t
566 */
LL_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)567 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)
568 {
569 return ((READ_BIT(RCC->AHB2SMENR, Periphs) == (Periphs)) ? 1UL : 0UL);
570 }
571
572 /**
573 * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode.
574 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockSleep\n
575 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockSleep\n
576 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockSleep\n
577 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockSleep\n
578 * @param Periphs This parameter can be a combination of the following values:
579 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
580 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
581 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
582 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
583 * @retval None
584 */
LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)585 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
586 {
587 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
588 }
589
590 /**
591 * @}
592 */
593
594 /** @defgroup BUS_LL_EF_AHB3 AHB3
595 * @{
596 */
597
598 #if defined(DUAL_CORE) /* Switch added for Documentation generation purpose to exclude IPCC in else case*/
599 /**
600 * @brief Enable AHB3 peripherals clock.
601 * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_EnableClock\n
602 * AHB3ENR AESEN LL_AHB3_GRP1_EnableClock\n
603 * AHB3ENR RNGEN LL_AHB3_GRP1_EnableClock\n
604 * AHB3ENR HSEMEN LL_AHB3_GRP1_EnableClock\n
605 * AHB3ENR IPCCEN LL_AHB3_GRP1_EnableClock\n
606 * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock
607 * @param Periphs This parameter can be a combination of the following values:
608 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
609 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
610 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
611 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
612 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
613 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
614 * @retval None
615 */
616
617 #else
618 /**
619 * @brief Enable AHB3 peripherals clock.
620 * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_EnableClock\n
621 * AHB3ENR AESEN LL_AHB3_GRP1_EnableClock\n
622 * AHB3ENR RNGEN LL_AHB3_GRP1_EnableClock\n
623 * AHB3ENR HSEMEN LL_AHB3_GRP1_EnableClock\n
624 * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock
625 * @param Periphs This parameter can be a combination of the following values:
626 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
627 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
628 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
629 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
630 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
631 * @retval None
632 */
633 #endif /* DUAL_CORE */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)634 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
635 {
636 __IO uint32_t tmpreg;
637 SET_BIT(RCC->AHB3ENR, Periphs);
638 /* Delay after an RCC peripheral clock enabling */
639 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
640 (void)tmpreg;
641 }
642
643 #if defined(DUAL_CORE) /* Switch added for Documentation generation purpose to exclude IPCC in else case*/
644 /**
645 * @brief Check if AHB3 peripheral clock is enabled or not
646 * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_IsEnabledClock\n
647 * AHB3ENR AESEN LL_AHB3_GRP1_IsEnabledClock\n
648 * AHB3ENR RNGEN LL_AHB3_GRP1_IsEnabledClock\n
649 * AHB3ENR HSEMEN LL_AHB3_GRP1_IsEnabledClock\n
650 * AHB3ENR IPCCEN LL_AHB3_GRP1_IsEnabledClock\n
651 * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock
652 * @param Periphs This parameter can be a combination of the following values:
653 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
654 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
655 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
656 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
657 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
658 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
659 * @retval uint32_t
660 */
661 #else
662 /**
663 * @brief Check if AHB3 peripheral clock is enabled or not
664 * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_IsEnabledClock\n
665 * AHB3ENR AESEN LL_AHB3_GRP1_IsEnabledClock\n
666 * AHB3ENR RNGEN LL_AHB3_GRP1_IsEnabledClock\n
667 * AHB3ENR HSEMEN LL_AHB3_GRP1_IsEnabledClock\n
668 * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock
669 * @param Periphs This parameter can be a combination of the following values:
670 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
671 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
672 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
673 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
674 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
675 * @retval uint32_t
676 */
677
678 #endif /* DUAL_CORE */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)679 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
680 {
681 return ((READ_BIT(RCC->AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
682 }
683
684 #if defined(DUAL_CORE) /* Switch added for Documentation generation purpose to exclude IPCC in else case*/
685 /**
686 * @brief Disable AHB3 peripherals clock.
687 * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_DisableClock\n
688 * AHB3ENR AESEN LL_AHB3_GRP1_DisableClock\n
689 * AHB3ENR RNGEN LL_AHB3_GRP1_DisableClock\n
690 * AHB3ENR HSEMEN LL_AHB3_GRP1_DisableClock\n
691 * AHB3ENR IPCCEN LL_AHB3_GRP1_DisableClock\n
692 * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock
693 * @param Periphs This parameter can be a combination of the following values:
694 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
695 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
696 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
697 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
698 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
699 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
700 * @retval None
701 */
702
703 #else
704 /**
705 * @brief Disable AHB3 peripherals clock.
706 * @rmtoll AHB3ENR PKAEN LL_AHB3_GRP1_DisableClock\n
707 * AHB3ENR AESEN LL_AHB3_GRP1_DisableClock\n
708 * AHB3ENR RNGEN LL_AHB3_GRP1_DisableClock\n
709 * AHB3ENR HSEMEN LL_AHB3_GRP1_DisableClock\n
710 * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock
711 * @param Periphs This parameter can be a combination of the following values:
712 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
713 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
714 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
715 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
716 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
717 * @retval None
718 */
719 #endif /* DUAL_CORE */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)720 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
721 {
722 CLEAR_BIT(RCC->AHB3ENR, Periphs);
723 }
724
725 #if defined(DUAL_CORE) /* Switch added for Documentation generation purpose to exclude IPCC in else case*/
726 /**
727 * @brief Force AHB3 peripherals reset.
728 * @rmtoll AHB3RSTR PKARST LL_AHB3_GRP1_ForceReset\n
729 * AHB3RSTR AESRST LL_AHB3_GRP1_ForceReset\n
730 * AHB3RSTR RNGRST LL_AHB3_GRP1_ForceReset\n
731 * AHB3RSTR HSEMRST LL_AHB3_GRP1_ForceReset\n
732 * AHB3RSTR IPCCRST LL_AHB3_GRP1_ForceReset\n
733 * AHB3RSTR FLASHRST LL_AHB3_GRP1_ForceReset
734 * @param Periphs This parameter can be a combination of the following values:
735 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
736 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
737 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
738 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
739 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
740 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
741 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
742 * @retval None
743 */
744 #else
745 /**
746 * @brief Force AHB3 peripherals reset.
747 * @rmtoll AHB3RSTR PKARST LL_AHB3_GRP1_ForceReset\n
748 * AHB3RSTR AESRST LL_AHB3_GRP1_ForceReset\n
749 * AHB3RSTR RNGRST LL_AHB3_GRP1_ForceReset\n
750 * AHB3RSTR HSEMRST LL_AHB3_GRP1_ForceReset\n
751 * AHB3RSTR FLASHRST LL_AHB3_GRP1_ForceReset
752 * @param Periphs This parameter can be a combination of the following values:
753 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
754 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
755 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
756 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
757 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
758 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
759 * @retval None
760 */
761
762 #endif /* DUAL_CORE */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)763 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
764 {
765 SET_BIT(RCC->AHB3RSTR, Periphs);
766 }
767
768 #if defined(DUAL_CORE) /* Switch added for Documentation generation purpose to exclude IPCC in else case*/
769 /**
770 * @brief Release AHB3 peripherals reset.
771 * @rmtoll AHB3RSTR PKARST LL_AHB3_GRP1_ReleaseReset\n
772 * AHB3RSTR AESRST LL_AHB3_GRP1_ReleaseReset\n
773 * AHB3RSTR RNGRST LL_AHB3_GRP1_ReleaseReset\n
774 * AHB3RSTR HSEMRST LL_AHB3_GRP1_ReleaseReset\n
775 * AHB3RSTR IPCCRST LL_AHB3_GRP1_ReleaseReset\n
776 * AHB3RSTR FLASHRST LL_AHB3_GRP1_ReleaseReset
777 * @param Periphs This parameter can be a combination of the following values:
778 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
779 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
780 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
781 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
782 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
783 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
784 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
785 * @retval None
786 */
787 #else
788 /**
789 * @brief Release AHB3 peripherals reset.
790 * @rmtoll AHB3RSTR PKARST LL_AHB3_GRP1_ReleaseReset\n
791 * AHB3RSTR AESRST LL_AHB3_GRP1_ReleaseReset\n
792 * AHB3RSTR RNGRST LL_AHB3_GRP1_ReleaseReset\n
793 * AHB3RSTR HSEMRST LL_AHB3_GRP1_ReleaseReset\n
794 * AHB3RSTR FLASHRST LL_AHB3_GRP1_ReleaseReset
795 * @param Periphs This parameter can be a combination of the following values:
796 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
797 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
798 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
799 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
800 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
801 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
802 * @retval None
803 */
804
805 #endif /* DUAL_CORE */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)806 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
807 {
808 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
809 }
810
811 /**
812 * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode.
813 * @rmtoll AHB3SMENR PKASMEN LL_AHB3_GRP1_EnableClockSleep\n
814 * AHB3SMENR AESSMEN LL_AHB3_GRP1_EnableClockSleep\n
815 * AHB3SMENR RNGSMEN LL_AHB3_GRP1_EnableClockSleep\n
816 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockSleep\n
817 * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_EnableClockSleep\n
818 * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_EnableClockSleep
819 * @param Periphs This parameter can be a combination of the following values:
820 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
821 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
822 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
823 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM1
824 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2
825 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
826 * @retval None
827 */
LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)828 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
829 {
830 __IO uint32_t tmpreg;
831 SET_BIT(RCC->AHB3SMENR, Periphs);
832 /* Delay after an RCC peripheral clock enabling */
833 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
834 (void)tmpreg;
835 }
836
837 /**
838 * @brief Check if AHB3 peripheral clock is enabled by the clock gating during CPU1 CSleep mode
839 * @rmtoll AHB3SMENR PKASMEN LL_AHB3_GRP1_IsEnabledClockSleep\n
840 * AHB3SMENR AESSMEN LL_AHB3_GRP1_IsEnabledClockSleep\n
841 * AHB3SMENR RNGSMEN LL_AHB3_GRP1_IsEnabledClockSleep\n
842 * AHB1SMENR SRAM1SMEN LL_AHB3_GRP1_IsEnabledClockSleep\n
843 * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_IsEnabledClockSleep\n
844 * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_IsEnabledClockSleep
845 * @param Periphs This parameter can be a combination of the following values:
846 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
847 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
848 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
849 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM1
850 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2
851 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
852 * @retval None
853 */
LL_AHB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)854 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)
855 {
856 return ((READ_BIT(RCC->AHB3SMENR, Periphs) == (Periphs)) ? 1UL : 0UL);
857 }
858
859 /**
860 * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode.
861 * @rmtoll AHB3SMENR PKASMEN LL_AHB3_GRP1_DisableClockSleep\n
862 * AHB3SMENR AESSMEN LL_AHB3_GRP1_DisableClockSleep\n
863 * AHB3SMENR RNGSMEN LL_AHB3_GRP1_DisableClockSleep\n
864 * AHB3SMENR SRAM1SMEN LL_AHB3_GRP1_DisableClockSleep\n
865 * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_DisableClockSleep\n
866 * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_DisableClockSleep
867 * @param Periphs This parameter can be a combination of the following values:
868 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
869 * @arg @ref LL_AHB3_GRP1_PERIPH_AES
870 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
871 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM1
872 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2
873 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
874 * @retval None
875 */
LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)876 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
877 {
878 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
879 }
880
881 /**
882 * @}
883 */
884
885 /** @defgroup BUS_LL_EF_APB1 APB1
886 * @{
887 */
888
889 /**
890 * @brief Enable APB1 peripherals clock.
891 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
892 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
893 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
894 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
895 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
896 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
897 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
898 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
899 * APB1ENR1 DACEN LL_APB1_GRP1_EnableClock\n
900 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
901 * @param Periphs This parameter can be a combination of the following values:
902 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
903 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
904 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
905 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
906 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
907 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
908 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
909 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
910 * @arg @ref LL_APB1_GRP1_PERIPH_DAC
911 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
912 * @retval None
913 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)914 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
915 {
916 __IO uint32_t tmpreg;
917 SET_BIT(RCC->APB1ENR1, Periphs);
918 /* Delay after an RCC peripheral clock enabling */
919 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
920 (void)tmpreg;
921 }
922
923 /**
924 * @brief Enable APB1 peripherals clock.
925 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
926 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
927 * APB1ENR2 LPTIM3EN LL_APB1_GRP2_EnableClock
928 * @param Periphs This parameter can be a combination of the following values:
929 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
930 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
931 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
932
933 * @retval None
934 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)935 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
936 {
937 __IO uint32_t tmpreg;
938 SET_BIT(RCC->APB1ENR2, Periphs);
939 /* Delay after an RCC peripheral clock enabling */
940 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
941 (void)tmpreg;
942 }
943
944 /**
945 * @brief Check if APB1 peripheral clock is enabled or not
946 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
947 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
948 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
949 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
950 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
951 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
952 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
953 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
954 * APB1ENR1 DACEN LL_APB1_GRP1_IsEnabledClock\n
955 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
956
957 * @param Periphs This parameter can be a combination of the following values:
958 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
959 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
960 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
961 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
962 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
963 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
964 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
965 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
966 * @arg @ref LL_APB1_GRP1_PERIPH_DAC
967 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
968
969 * @retval uint32_t
970 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)971 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
972 {
973 return ((READ_BIT(RCC->APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
974 }
975
976 /**
977 * @brief Check if APB1 peripheral clock is enabled or not
978 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
979 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
980 * APB1ENR2 LPTIM3EN LL_APB1_GRP2_IsEnabledClock
981 * @param Periphs This parameter can be a combination of the following values:
982 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
983 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
984 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
985 * @retval uint32_t
986 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)987 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
988 {
989 return ((READ_BIT(RCC->APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
990 }
991
992 /**
993 * @brief Disable APB1 peripherals clock.
994 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
995 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
996 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
997 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
998 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
999 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
1000 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
1001 * APB1ENR1 DACEN LL_APB1_GRP1_DisableClock\n
1002 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
1003
1004 * @param Periphs This parameter can be a combination of the following values:
1005 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1006 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1007 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1008 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1009 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1010 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1011 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1012 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1013 * @arg @ref LL_APB1_GRP1_PERIPH_DAC
1014 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1015
1016 * @retval None
1017 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1018 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1019 {
1020 CLEAR_BIT(RCC->APB1ENR1, Periphs);
1021 }
1022
1023 /**
1024 * @brief Disable APB1 peripherals clock.
1025 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
1026 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
1027 * APB1ENR2 LPTIM3EN LL_APB1_GRP2_DisableClock
1028 * @param Periphs This parameter can be a combination of the following values:
1029 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1030 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1031 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
1032 * @retval None
1033 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1034 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1035 {
1036 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1037 }
1038
1039 /**
1040 * @brief Force APB1 peripherals reset.
1041 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1042 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
1043 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
1044 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
1045 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
1046 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
1047 * APB1RSTR1 DACRST LL_APB1_GRP1_ForceReset\n
1048 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
1049 * @param Periphs This parameter can be a combination of the following values:
1050 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1051 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1052 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1053 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1054 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1055 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1056 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1057 * @arg @ref LL_APB1_GRP1_PERIPH_DAC
1058 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1059
1060 * @retval None
1061 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1062 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1063 {
1064 SET_BIT(RCC->APB1RSTR1, Periphs);
1065 }
1066
1067 /**
1068 * @brief Force APB1 peripherals reset.
1069 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
1070 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
1071 * APB1RSTR2 LPTIM3RST LL_APB1_GRP2_ForceReset
1072 * @param Periphs This parameter can be a combination of the following values:
1073 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1074 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1075 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1076 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
1077 * @retval None
1078 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1079 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1080 {
1081 SET_BIT(RCC->APB1RSTR2, Periphs);
1082 }
1083
1084 /**
1085 * @brief Release APB1 peripherals reset.
1086 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1087 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
1088 * APB1RSTR1 DACRST LL_APB1_GRP1_ReleaseReset\n
1089 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
1090 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
1091 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
1092 * APB1RSTR1 DACRST LL_APB1_GRP1_ReleaseReset\n
1093 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
1094 * @param Periphs This parameter can be a combination of the following values:
1095 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1096 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1097 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1098 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1099 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1100 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1101 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1102 * @arg @ref LL_APB1_GRP1_PERIPH_DAC
1103 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1104
1105 * @retval None
1106 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1107 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1108 {
1109 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1110 }
1111
1112 /**
1113 * @brief Release APB1 peripherals reset.
1114 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
1115 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
1116 * APB1RSTR2 LPTIM3RST LL_APB1_GRP2_ReleaseReset
1117 * @param Periphs This parameter can be a combination of the following values:
1118 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1119 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1120 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1121 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
1122 * @retval None
1123 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1124 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1125 {
1126 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1127 }
1128
1129 /**
1130 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
1131 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n
1132 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockSleep\n
1133 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n
1134 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n
1135 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockSleep\n
1136 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n
1137 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n
1138 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n
1139 * APB1SMENR1 DACSMEN LL_APB1_GRP1_EnableClockSleep\n
1140 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep
1141 * @param Periphs This parameter can be a combination of the following values:
1142 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1143 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1144 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1145 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1146 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1147 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1148 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1149 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1150 * @arg @ref LL_APB1_GRP1_PERIPH_DAC
1151 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1152
1153 * @retval None
1154 */
LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)1155 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
1156 {
1157 __IO uint32_t tmpreg;
1158 SET_BIT(RCC->APB1SMENR1, Periphs);
1159 /* Delay after an RCC peripheral clock enabling */
1160 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
1161 (void)tmpreg;
1162 }
1163
1164 /**
1165 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
1166 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockSleep\n
1167 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockSleep
1168 * APB1SMENR2 LPTIM3SMEN LL_APB1_GRP2_EnableClockSleep
1169 * @param Periphs This parameter can be a combination of the following values:
1170 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1171 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1172 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
1173 * @retval None
1174 */
LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)1175 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
1176 {
1177 __IO uint32_t tmpreg;
1178 SET_BIT(RCC->APB1SMENR2, Periphs);
1179 /* Delay after an RCC peripheral clock enabling */
1180 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
1181 (void)tmpreg;
1182 }
1183
1184 /**
1185 * @brief Check if APB1 clock is enabled by the clock gating during CPU1 CSleep mode
1186 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockSleep\n
1187 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_IsEnabledClockSleep\n
1188 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_IsEnabledClockSleep\n
1189 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_IsEnabledClockSleep\n
1190 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockSleep\n
1191 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockSleep\n
1192 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_IsEnabledClockSleep\n
1193 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_IsEnabledClockSleep\n
1194 * APB1SMENR1 DACSMEN LL_APB1_GRP1_IsEnabledClockSleep\n
1195 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_IsEnabledClockSleep
1196 * @param Periphs This parameter can be a combination of the following values:
1197 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1198 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1199 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1200 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1201 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1202 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1203 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1204 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1205 * @arg @ref LL_APB1_GRP1_PERIPH_DAC
1206 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1207
1208 * @retval None
1209 */
LL_APB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)1210 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)
1211 {
1212 return ((READ_BIT(RCC->APB1SMENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
1213 }
1214
1215 /**
1216 * @brief Check if APB1 clock is enabled by the clock gating during CPU1 CSleep mode
1217 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_IsEnabledClockSleep\n
1218 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockSleep\n
1219 * APB1SMENR2 LPTIM3SMEN LL_APB1_GRP2_IsEnabledClockSleep
1220 * @param Periphs This parameter can be a combination of the following values:
1221 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1222 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1223 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
1224 * @retval None
1225 */
LL_APB1_GRP2_IsEnabledClockSleep(uint32_t Periphs)1226 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockSleep(uint32_t Periphs)
1227 {
1228 return ((READ_BIT(RCC->APB1SMENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
1229 }
1230
1231 /**
1232 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
1233 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n
1234 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockSleep\n
1235 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n
1236 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n
1237 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockSleep\n
1238 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n
1239 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n
1240 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n
1241 * APB1SMENR1 DACSMEN LL_APB1_GRP1_DisableClockSleep\n
1242 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep
1243 * @param Periphs This parameter can be a combination of the following values:
1244 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1245 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1246 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1247 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1248 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1249 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1250 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1251 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1252 * @arg @ref LL_APB1_GRP1_PERIPH_DAC
1253 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1254
1255 * @retval None
1256 */
LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)1257 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
1258 {
1259 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
1260 }
1261
1262 /**
1263 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
1264 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockSleep\n
1265 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockSleep
1266 * APB1SMENR2 LPTIM3SMEN LL_APB1_GRP2_DisableClockSleep
1267 * @param Periphs This parameter can be a combination of the following values:
1268 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1269 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1270 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM3
1271 * @retval None
1272 */
LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)1273 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
1274 {
1275 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
1276 }
1277
1278 /**
1279 * @}
1280 */
1281
1282 /** @defgroup BUS_LL_EF_APB2 APB2
1283 * @{
1284 */
1285
1286 /**
1287 * @brief Enable APB2 peripherals clock.
1288 * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n
1289 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1290 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1291 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1292 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1293 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1294 * @param Periphs This parameter can be a combination of the following values:
1295 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1296 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1297 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1298 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1299 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1300 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1301 * @retval None
1302 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1303 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1304 {
1305 __IO uint32_t tmpreg;
1306 SET_BIT(RCC->APB2ENR, Periphs);
1307 /* Delay after an RCC peripheral clock enabling */
1308 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1309 (void)tmpreg;
1310 }
1311
1312 /**
1313 * @brief Check if APB2 peripheral clock is enabled or not
1314 * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n
1315 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1316 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1317 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1318 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1319 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1320 * @param Periphs This parameter can be a combination of the following values:
1321 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1322 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1323 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1324 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1325 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1326 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1327 * @retval uint32_t
1328 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1329 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1330 {
1331 return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1332 }
1333
1334 /**
1335 * @brief Disable APB2 peripherals clock.
1336 * @rmtoll APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n
1337 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1338 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1339 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1340 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
1341 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
1342 * @param Periphs This parameter can be a combination of the following values:
1343 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1344 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1345 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1346 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1347 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1348 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1349 * @retval None
1350 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1351 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1352 {
1353 CLEAR_BIT(RCC->APB2ENR, Periphs);
1354 }
1355
1356 /**
1357 * @brief Force APB2 peripherals reset.
1358 * @rmtoll APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
1359 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1360 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1361 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1362 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1363 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1364 * @param Periphs This parameter can be a combination of the following values:
1365 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1366 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1367 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1368 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1369 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1370 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1371 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1372 * @retval None
1373 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1374 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1375 {
1376 SET_BIT(RCC->APB2RSTR, Periphs);
1377 }
1378
1379 /**
1380 * @brief Release APB2 peripherals reset.
1381 * @rmtoll APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
1382 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1383 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1384 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1385 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
1386 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
1387 * @param Periphs This parameter can be a combination of the following values:
1388 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1389 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1390 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1391 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1392 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1393 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1394 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1395 * @retval None
1396 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1397 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1398 {
1399 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1400 }
1401
1402 /**
1403 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
1404 * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_EnableClockSleep\n
1405 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockSleep\n
1406 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n
1407 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n
1408 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockSleep\n
1409 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockSleep\n
1410 * @param Periphs This parameter can be a combination of the following values:
1411 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1412 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1413 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1414 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1415 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1416 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1417 * @retval None
1418 */
LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)1419 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
1420 {
1421 __IO uint32_t tmpreg;
1422 SET_BIT(RCC->APB2SMENR, Periphs);
1423 /* Delay after an RCC peripheral clock enabling */
1424 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
1425 (void)tmpreg;
1426 }
1427
1428 /**
1429 * @brief Check if APB2 clock is enabled by the clock gating during CPU1 CSleep mode
1430 * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_IsEnabledClockSleep\n
1431 * APB2SMENR TIM1SMEN LL_APB2_GRP1_IsEnabledClockSleep\n
1432 * APB2SMENR SPI1SMEN LL_APB2_GRP1_IsEnabledClockSleep\n
1433 * APB2SMENR USART1SMEN LL_APB2_GRP1_IsEnabledClockSleep\n
1434 * APB2SMENR TIM16SMEN LL_APB2_GRP1_IsEnabledClockSleep\n
1435 * APB2SMENR TIM17SMEN LL_APB2_GRP1_IsEnabledClockSleep
1436 * @param Periphs This parameter can be a combination of the following values:
1437 * @param Periphs This parameter can be a combination of the following values:
1438 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1439 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1440 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1441 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1442 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1443 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1444 * @retval None
1445 */
LL_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)1446 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)
1447 {
1448 return ((READ_BIT(RCC->APB2SMENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1449 }
1450
1451 /**
1452 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
1453 * @rmtoll APB2SMENR ADCSMEN LL_APB2_GRP1_DisableClockSleep\n
1454 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockSleep\n
1455 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n
1456 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n
1457 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockSleep\n
1458 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockSleep\n
1459 * @param Periphs This parameter can be a combination of the following values:
1460 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1461 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1462 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1463 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1464 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1465 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1466 * @retval None
1467 */
LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)1468 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
1469 {
1470 CLEAR_BIT(RCC->APB2SMENR, Periphs);
1471 }
1472
1473 /**
1474 * @}
1475 */
1476
1477 /** @defgroup BUS_LL_EF_APB3 APB3
1478 * @{
1479 */
1480
1481 /**
1482 * @brief Enable APB3 peripherals clock.
1483 * @rmtoll APB3ENR SUBGHZSPIEN LL_APB3_GRP1_EnableClock\n
1484 * @param Periphs This parameter can be a combination of the following values:
1485 * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI
1486 * @retval None
1487 */
LL_APB3_GRP1_EnableClock(uint32_t Periphs)1488 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
1489 {
1490 __IO uint32_t tmpreg;
1491 SET_BIT(RCC->APB3ENR, Periphs);
1492 /* Delay after an RCC peripheral clock enabling */
1493 tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
1494 (void)tmpreg;
1495 }
1496
1497 /**
1498 * @brief Check if APB3 peripheral clock is enabled or not
1499 * @rmtoll APB3ENR SUBGHZSPIEN LL_APB3_GRP1_IsEnabledClock\n
1500 * @param Periphs This parameter can be a combination of the following values:
1501 * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI
1502 * @retval uint32_t
1503 */
LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)1504 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
1505 {
1506 return ((READ_BIT(RCC->APB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1507 }
1508
1509 /**
1510 * @brief Disable APB3 peripherals clock.
1511 * @rmtoll APB3ENR SUBGHZSPIEN LL_APB3_GRP1_DisableClock\n
1512 * @param Periphs This parameter can be a combination of the following values:
1513 * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI
1514 * @retval None
1515 */
LL_APB3_GRP1_DisableClock(uint32_t Periphs)1516 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
1517 {
1518 CLEAR_BIT(RCC->APB3ENR, Periphs);
1519 }
1520
1521
1522 /**
1523 * @brief Force APB3 peripherals reset.
1524 * @rmtoll APB3RSTR SUBGHZSPIRST LL_APB3_GRP1_ForceReset
1525 * @param Periphs This parameter can be a combination of the following values:
1526 * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI
1527 * @retval None
1528 */
LL_APB3_GRP1_ForceReset(uint32_t Periphs)1529 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
1530 {
1531 SET_BIT(RCC->APB3RSTR, Periphs);
1532 }
1533
1534 /**
1535 * @brief Release APB3 peripherals reset.
1536 * @rmtoll APB3RSTR SUBGHZSPIRST LL_APB3_GRP1_ReleaseReset
1537 * @param Periphs This parameter can be a combination of the following values:
1538 * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI
1539 * @retval None
1540 */
LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)1541 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
1542 {
1543 CLEAR_BIT(RCC->APB3RSTR, Periphs);
1544 }
1545
1546 /**
1547 * @brief Enable APB3 peripherals clock during Low Power (Sleep) mode.
1548 * @rmtoll APB3SMENR SUBGHZSPISMEN LL_APB3_GRP1_EnableClockSleep\n
1549 * @param Periphs This parameter can be a combination of the following values:
1550 * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI
1551 * @retval None
1552 */
LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)1553 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
1554 {
1555 __IO uint32_t tmpreg;
1556 SET_BIT(RCC->APB3SMENR, Periphs);
1557 /* Delay after an RCC peripheral clock enabling */
1558 tmpreg = READ_BIT(RCC->APB3SMENR, Periphs);
1559 (void)tmpreg;
1560 }
1561
1562 /**
1563 * @brief Check if APB3 clock is enabled by the clock gating during CPU1 CSleep mode
1564 * @rmtoll APB3SMENR SUBGHZSPISMEN LL_APB3_GRP1_IsEnabledClockSleep
1565 * @param Periphs This parameter can be a combination of the following values:
1566 * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI
1567 * @retval None
1568 */
LL_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)1569 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)
1570 {
1571 return ((READ_BIT(RCC->APB3SMENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1572 }
1573
1574 /**
1575 * @brief Disable APB3 peripherals clock during Low Power (Sleep) mode.
1576 * @rmtoll APB3SMENR SUBGHZSPISMEN LL_APB3_GRP1_DisableClockSleep\n
1577 * @param Periphs This parameter can be a combination of the following values:
1578 * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI
1579 * @retval None
1580 */
LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)1581 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
1582 {
1583 CLEAR_BIT(RCC->APB3SMENR, Periphs);
1584 }
1585
1586
1587 /**
1588 * @}
1589 */
1590
1591 #if defined(DUAL_CORE)
1592 /** @defgroup BUS_LL_EF_C2_AHB1 C2 AHB1
1593 * @{
1594 */
1595 /**
1596 * @brief Enable C2AHB1 peripherals clock.
1597 * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n
1598 * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n
1599 * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_EnableClock\n
1600 * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_EnableClock
1601 * @param Periphs This parameter can be a combination of the following values:
1602 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1603 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
1604 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1605 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1606 * @retval None
1607 */
LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)1608 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
1609 {
1610 __IO uint32_t tmpreg;
1611 SET_BIT(RCC->C2AHB1ENR, Periphs);
1612 /* Delay after an RCC peripheral clock enabling */
1613 tmpreg = READ_BIT(RCC->C2AHB1ENR, Periphs);
1614 (void)tmpreg;
1615 }
1616
1617 /**
1618 * @brief Check if C2AHB1 peripheral clock is enabled or not
1619 * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n
1620 * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n
1621 * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_IsEnabledClock\n
1622 * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_IsEnabledClock
1623 * @param Periphs This parameter can be a combination of the following values:
1624 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1625 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
1626 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1627 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1628 * @retval uint32_t
1629 */
LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)1630 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
1631 {
1632 return ((READ_BIT(RCC->C2AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1633 }
1634
1635 /**
1636 * @brief Disable C2AHB1 peripherals clock.
1637 * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n
1638 * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n
1639 * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_DisableClock\n
1640 * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_DisableClock
1641 * @param Periphs This parameter can be a combination of the following values:
1642 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1643 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
1644 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1645 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1646 * @retval None
1647 */
LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)1648 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
1649 {
1650 CLEAR_BIT(RCC->C2AHB1ENR, Periphs);
1651 }
1652
1653 /**
1654 * @brief Enable C2AHB1 peripherals clock during Low Power (Sleep) mode.
1655 * @rmtoll C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1656 * C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1657 * C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1658 * C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_EnableClockSleep
1659 * @param Periphs This parameter can be a combination of the following values:
1660 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1661 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
1662 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1663 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1664 * @retval None
1665 */
LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)1666 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
1667 {
1668 __IO uint32_t tmpreg;
1669 SET_BIT(RCC->C2AHB1SMENR, Periphs);
1670 /* Delay after an RCC peripheral clock enabling */
1671 tmpreg = READ_BIT(RCC->C2AHB1SMENR, Periphs);
1672 (void)tmpreg;
1673 }
1674
1675 /**
1676 * @brief Check if C2AHB1 peripheral clock is enabled by the clock gating during CPU1 CSleep mode.
1677 * @rmtoll C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_IsEnabledClockSleep\n
1678 * C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_IsEnabledClockSleep\n
1679 * C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_IsEnabledClockSleep\n
1680 * C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_IsEnabledClockSleep
1681 * @param Periphs This parameter can be a combination of the following values:
1682 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1683 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
1684 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1685 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1686 * @retval None
1687 */
LL_C2_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)1688 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)
1689 {
1690 return ((READ_BIT(RCC->C2AHB1SMENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1691 }
1692
1693 /**
1694 * @brief Disable C2AHB1 peripherals clock during Low Power (Sleep) mode.
1695 * @rmtoll C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1696 * C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1697 * C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1698 * C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_DisableClockSleep
1699 * @param Periphs This parameter can be a combination of the following values:
1700 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1701 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
1702 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1703 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1704 * @retval None
1705 */
LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)1706 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
1707 {
1708 CLEAR_BIT(RCC->C2AHB1SMENR, Periphs);
1709 }
1710
1711 /**
1712 * @}
1713 */
1714
1715 /** @defgroup BUS_LL_EF_C2_AHB2 C2 AHB2
1716 * @{
1717 */
1718
1719 /**
1720 * @brief Enable C2AHB2 peripherals clock.
1721 * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_EnableClock\n
1722 * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_EnableClock\n
1723 * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_EnableClock\n
1724 * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_EnableClock
1725 * @param Periphs This parameter can be a combination of the following values:
1726 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1727 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1728 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1729 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1730 * @retval None
1731 */
LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)1732 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
1733 {
1734 __IO uint32_t tmpreg;
1735 SET_BIT(RCC->C2AHB2ENR, Periphs);
1736 /* Delay after an RCC peripheral clock enabling */
1737 tmpreg = READ_BIT(RCC->C2AHB2ENR, Periphs);
1738 (void)tmpreg;
1739 }
1740
1741 /**
1742 * @brief Check if C2AHB2 peripheral clock is enabled or not
1743 * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1744 * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1745 * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1746 * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_IsEnabledClock
1747 * @param Periphs This parameter can be a combination of the following values:
1748 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1749 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1750 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1751 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1752 * @retval uint32_t
1753 */
LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)1754 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
1755 {
1756 return ((READ_BIT(RCC->C2AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1757 }
1758
1759 /**
1760 * @brief Disable C2AHB2 peripherals clock.
1761 * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_DisableClock\n
1762 * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_DisableClock\n
1763 * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_DisableClock\n
1764 * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_DisableClock
1765 * @param Periphs This parameter can be a combination of the following values:
1766 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1767 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1768 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1769 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1770 * @retval None
1771 */
LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)1772 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
1773 {
1774 CLEAR_BIT(RCC->C2AHB2ENR, Periphs);
1775 }
1776
1777 /**
1778 * @brief Enable C2AHB2 peripherals clock during Low Power (Sleep) mode.
1779 * @rmtoll C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1780 * C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1781 * C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1782 * C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_EnableClockSleep
1783 * @param Periphs This parameter can be a combination of the following values:
1784 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1785 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1786 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1787 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1788 * @retval None
1789 */
LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)1790 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
1791 {
1792 __IO uint32_t tmpreg;
1793 SET_BIT(RCC->C2AHB2SMENR, Periphs);
1794 /* Delay after an RCC peripheral clock enabling */
1795 tmpreg = READ_BIT(RCC->C2AHB2SMENR, Periphs);
1796 (void)tmpreg;
1797 }
1798
1799 /**
1800 * @brief Check if C2AHB2 peripheral clock is enabled by the clock gating during CPU1 CSleep mode.
1801 * @rmtoll C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_IsEnabledClockSleep\n
1802 * C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_IsEnabledClockSleep\n
1803 * C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_IsEnabledClockSleep\n
1804 * C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_IsEnabledClockSleep
1805 * @param Periphs This parameter can be a combination of the following values:
1806 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1807 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1808 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1809 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1810 * @retval None
1811 */
LL_C2_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)1812 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)
1813 {
1814 return ((READ_BIT(RCC->C2AHB2SMENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1815 }
1816
1817 /**
1818 * @brief Disable C2AHB2 peripherals clock during Low Power (Sleep) mode.
1819 * @rmtoll C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1820 * C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1821 * C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1822 * C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1823
1824 * @param Periphs This parameter can be a combination of the following values:
1825 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1826 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1827 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1828 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1829 * @retval None
1830 */
LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)1831 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
1832 {
1833 CLEAR_BIT(RCC->C2AHB2SMENR, Periphs);
1834 }
1835
1836 /**
1837 * @}
1838 */
1839
1840 /** @defgroup BUS_LL_EF_C2_AHB3 C2 AHB3
1841 * @{
1842 */
1843
1844 /**
1845 * @brief Enable C2AHB3 peripherals clock.
1846 * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_EnableClock\n
1847 * C2AHB3ENR AESEN LL_C2_AHB3_GRP1_EnableClock\n
1848 * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_EnableClock\n
1849 * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_EnableClock\n
1850 * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_EnableClock\n
1851 * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock
1852 * @param Periphs This parameter can be a combination of the following values:
1853 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1854 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES
1855 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1856 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
1857 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
1858 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1859 * @retval None
1860 */
LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)1861 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
1862 {
1863 __IO uint32_t tmpreg;
1864 SET_BIT(RCC->C2AHB3ENR, Periphs);
1865 /* Delay after an RCC peripheral clock enabling */
1866 tmpreg = READ_BIT(RCC->C2AHB3ENR, Periphs);
1867 (void)tmpreg;
1868 }
1869
1870 /**
1871 * @brief Check if C2AHB3 peripheral clock is enabled or not
1872 * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1873 * C2AHB3ENR AESEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1874 * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1875 * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1876 * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1877 * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock
1878 * @param Periphs This parameter can be a combination of the following values:
1879 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1880 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES
1881 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1882 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
1883 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
1884 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1885 * @retval uint32_t
1886 */
LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)1887 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
1888 {
1889 return ((READ_BIT(RCC->C2AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1890 }
1891
1892 /**
1893 * @brief Disable C2AHB3 peripherals clock.
1894 * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_DisableClock\n
1895 * C2AHB3ENR AESEN LL_C2_AHB3_GRP1_DisableClock\n
1896 * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_DisableClock\n
1897 * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_DisableClock\n
1898 * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_DisableClock\n
1899 * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock
1900 * @param Periphs This parameter can be a combination of the following values:
1901 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1902 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES
1903 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1904 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
1905 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
1906 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1907 * @retval None
1908 */
LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)1909 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
1910 {
1911 CLEAR_BIT(RCC->C2AHB3ENR, Periphs);
1912 }
1913
1914 /**
1915 * @brief Enable C2AHB3 peripherals clock during Low Power (Sleep) mode.
1916 * @rmtoll C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1917 * C2AHB3SMENR AESSMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1918 * C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1919 * C2AHB3SMENR SRAM1SMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1920 * C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1921 * C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_EnableClockSleep
1922 * @param Periphs This parameter can be a combination of the following values:
1923 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1924 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES
1925 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1926 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM1
1927 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2
1928 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1929 * @retval None
1930 */
LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)1931 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
1932 {
1933 __IO uint32_t tmpreg;
1934 SET_BIT(RCC->C2AHB3SMENR, Periphs);
1935 /* Delay after an RCC peripheral clock enabling */
1936 tmpreg = READ_BIT(RCC->C2AHB3SMENR, Periphs);
1937 (void)tmpreg;
1938 }
1939
1940 /**
1941 * @brief Check if C2AHB3 peripheral clock is enabled by the clock gating during CPU1 CSleep mode.
1942 * @rmtoll C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep\n
1943 * C2AHB3SMENR AESSMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep\n
1944 * C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep\n
1945 * C2AHB3SMENR SRAM1SMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep\n
1946 * C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep\n
1947 * C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_IsEnabledClockSleep
1948 * @param Periphs This parameter can be a combination of the following values:
1949 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1950 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES
1951 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1952 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM1
1953 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2
1954 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1955 * @retval None
1956 */
LL_C2_AHB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)1957 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)
1958 {
1959 return ((READ_BIT(RCC->C2AHB3SMENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1960 }
1961
1962 /**
1963 * @brief Disable C2AHB3 peripherals clock during Low Power (Sleep) mode.
1964 * @rmtoll C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1965 * C2AHB3SMENR AESSMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1966 * C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1967 * C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1968 * C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_DisableClockSleep
1969 * @param Periphs This parameter can be a combination of the following values:
1970 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1971 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES
1972 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1973 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2
1974 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1975 * @retval None
1976 */
LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)1977 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
1978 {
1979 CLEAR_BIT(RCC->C2AHB3SMENR, Periphs);
1980 }
1981
1982 /**
1983 * @}
1984 */
1985
1986 /** @defgroup BUS_LL_EF_C2_APB1 C2 APB1
1987 * @{
1988 */
1989
1990 /**
1991 * @brief Enable C2APB1 peripherals clock.
1992 * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_EnableClock\n
1993 * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_EnableClock\n
1994 * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_EnableClock\n
1995 * C2APB1ENR1 USART2EN LL_C2_APB1_GRP1_EnableClock\n
1996 * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_EnableClock\n
1997 * C2APB1ENR1 I2C2EN LL_C2_APB1_GRP1_EnableClock\n
1998 * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_EnableClock\n
1999 * C2APB1ENR1 DACEN LL_C2_APB1_GRP1_EnableClock\n
2000 * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_EnableClock
2001 * @param Periphs This parameter can be a combination of the following values:
2002 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
2003 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
2004 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
2005 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2
2006 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
2007 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2
2008 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
2009 * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC
2010 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
2011
2012 * @retval None
2013 */
LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)2014 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
2015 {
2016 __IO uint32_t tmpreg;
2017 SET_BIT(RCC->C2APB1ENR1, Periphs);
2018 /* Delay after an RCC peripheral clock enabling */
2019 tmpreg = READ_BIT(RCC->C2APB1ENR1, Periphs);
2020 (void)tmpreg;
2021 }
2022
2023 /**
2024 * @brief Enable C2APB1 peripherals clock.
2025 * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_EnableClock\n
2026 * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_EnableClock
2027 * @param Periphs This parameter can be a combination of the following values:
2028 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
2029 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
2030 * @retval None
2031 */
LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)2032 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
2033 {
2034 __IO uint32_t tmpreg;
2035 SET_BIT(RCC->C2APB1ENR2, Periphs);
2036 /* Delay after an RCC peripheral clock enabling */
2037 tmpreg = READ_BIT(RCC->C2APB1ENR2, Periphs);
2038 (void)tmpreg;
2039 }
2040
2041 /**
2042 * @brief Check if C2APB1 peripheral clock is enabled or not
2043 * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n
2044 * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_IsEnabledClock\n
2045 * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n
2046 * C2APB1ENR1 USART2EN LL_C2_APB1_GRP1_IsEnabledClock\n
2047 * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n
2048 * C2APB1ENR1 I2C2EN LL_C2_APB1_GRP1_IsEnabledClock\n
2049 * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n
2050 * C2APB1ENR1 DACEN LL_C2_APB1_GRP1_IsEnabledClock\n
2051 * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock
2052 * @param Periphs This parameter can be a combination of the following values:
2053 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
2054 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
2055 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
2056 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2
2057 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
2058 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2
2059 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
2060 * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC
2061 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
2062
2063 * @retval uint32_t
2064 */
LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)2065 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
2066 {
2067 return ((READ_BIT(RCC->C2APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
2068 }
2069
2070 /**
2071 * @brief Check if C2APB1 peripheral clock is enabled or not
2072 * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_IsEnabledClock\n
2073 * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_IsEnabledClock
2074 * @param Periphs This parameter can be a combination of the following values:
2075 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
2076 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
2077 * @retval uint32_t
2078 */
LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)2079 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
2080 {
2081 return ((READ_BIT(RCC->C2APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
2082 }
2083
2084 /**
2085 * @brief Disable C2APB1 peripherals clock.
2086 * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_DisableClock\n
2087 * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_DisableClock\n
2088 * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_DisableClock\n
2089 * C2APB1ENR1 USART2EN LL_C2_APB1_GRP1_DisableClock\n
2090 * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_DisableClock\n
2091 * C2APB1ENR1 I2C2EN LL_C2_APB1_GRP1_DisableClock\n
2092 * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_DisableClock\n
2093 * C2APB1ENR1 DACEN LL_C2_APB1_GRP1_DisableClock\n
2094 * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_DisableClock
2095 * @param Periphs This parameter can be a combination of the following values:
2096 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
2097 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
2098 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
2099 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2
2100 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
2101 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2
2102 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
2103 * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC
2104 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
2105
2106 * @retval None
2107 */
LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)2108 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
2109 {
2110 CLEAR_BIT(RCC->C2APB1ENR1, Periphs);
2111 }
2112
2113 /**
2114 * @brief Disable C2APB1 peripherals clock.
2115 * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_DisableClock\n
2116 * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_DisableClock
2117 * @param Periphs This parameter can be a combination of the following values:
2118 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
2119 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
2120 * @retval None
2121 */
LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)2122 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
2123 {
2124 CLEAR_BIT(RCC->C2APB1ENR2, Periphs);
2125 }
2126
2127 /**
2128 * @brief Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
2129 * @rmtoll C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2130 * C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2131 * C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2132 * C2APB1SMENR1 USART2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2133 * C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2134 * C2APB1SMENR1 I2C2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2135 * C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2136 * C2APB1SMENR1 DACSMEN LL_C2_APB1_GRP1_EnableClockSleep\n
2137 * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_EnableClockSleep
2138 * @param Periphs This parameter can be a combination of the following values:
2139 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
2140 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
2141 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
2142 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2
2143 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
2144 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2
2145 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
2146 * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC
2147 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
2148 * @retval None
2149 */
LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)2150 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
2151 {
2152 __IO uint32_t tmpreg;
2153 SET_BIT(RCC->C2APB1SMENR1, Periphs);
2154 /* Delay after an RCC peripheral clock enabling */
2155 tmpreg = READ_BIT(RCC->C2APB1SMENR1, Periphs);
2156 (void)tmpreg;
2157 }
2158
2159 /**
2160 * @brief Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
2161 * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_EnableClockSleep\n
2162 * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_EnableClockSleep\n
2163 * C2APB1SMENR2 LPTIM3SMEN LL_C2_APB1_GRP2_EnableClockSleep
2164 * @param Periphs This parameter can be a combination of the following values:
2165 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
2166 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
2167 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM3
2168 * @retval None
2169 */
LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)2170 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
2171 {
2172 __IO uint32_t tmpreg;
2173 SET_BIT(RCC->C2APB1SMENR2, Periphs);
2174 /* Delay after an RCC peripheral clock enabling */
2175 tmpreg = READ_BIT(RCC->C2APB1SMENR2, Periphs);
2176 (void)tmpreg;
2177 }
2178
2179 /**
2180 * @brief Check if C2APB1 peripheral clock is enabled by the clock gating during CPU1 CSleep mode.
2181 * @rmtoll C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n
2182 * C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n
2183 * C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n
2184 * C2APB1SMENR1 USART2SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n
2185 * C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n
2186 * C2APB1SMENR1 I2C2SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n
2187 * C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n
2188 * C2APB1SMENR1 DACSMEN LL_C2_APB1_GRP1_IsEnabledClockSleep\n
2189 * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_IsEnabledClockSleep
2190 * @param Periphs This parameter can be a combination of the following values:
2191 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
2192 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
2193 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
2194 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2
2195 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
2196 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2
2197 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
2198 * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC
2199 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
2200 * @retval None
2201 */
LL_C2_APB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)2202 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)
2203 {
2204 return ((READ_BIT(RCC->C2APB1SMENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
2205 }
2206
2207 /**
2208 * @brief Check if C2APB1 peripheral clock is enabled by the clock gating during CPU1 CSleep mode.
2209 * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_IsEnabledClockSleep\n
2210 * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_IsEnabledClockSleep\n
2211 * C2APB1SMENR2 LPTIM3SMEN LL_C2_APB1_GRP2_IsEnabledClockSleep
2212 * @param Periphs This parameter can be a combination of the following values:
2213 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
2214 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
2215 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM3
2216 * @retval None
2217 */
LL_C2_APB1_GRP2_IsEnabledClockSleep(uint32_t Periphs)2218 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClockSleep(uint32_t Periphs)
2219 {
2220 return ((READ_BIT(RCC->C2APB1SMENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
2221 }
2222
2223 /**
2224 * @brief Disable C2APB1 peripherals clock during Low Power (Sleep) mode.
2225 * @rmtoll C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2226 * C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2227 * C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2228 * C2APB1SMENR1 USART2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2229 * C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2230 * C2APB1SMENR1 I2C2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2231 * C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2232 * C2APB1SMENR1 DACSMEN LL_C2_APB1_GRP1_DisableClockSleep\n
2233 * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_DisableClockSleep
2234 * @param Periphs This parameter can be a combination of the following values:
2235 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
2236 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
2237 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
2238 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USART2
2239 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
2240 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C2
2241 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
2242 * @arg @ref LL_C2_APB1_GRP1_PERIPH_DAC
2243 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
2244
2245 * @retval None
2246 */
LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)2247 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
2248 {
2249 CLEAR_BIT(RCC->C2APB1SMENR1, Periphs);
2250 }
2251
2252 /**
2253 * @brief Disable C2APB1 peripherals clock during Low Power (Sleep) mode.
2254 * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_DisableClockSleep\n
2255 * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_DisableClockSleep
2256 * @param Periphs This parameter can be a combination of the following values:
2257 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
2258 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
2259 * @retval None
2260 */
LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)2261 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
2262 {
2263 CLEAR_BIT(RCC->C2APB1SMENR2, Periphs);
2264 }
2265
2266 /**
2267 * @}
2268 */
2269
2270 /** @defgroup BUS_LL_EF_C2_APB2 C2 APB2
2271 * @{
2272 */
2273
2274 /**
2275 * @brief Enable C2APB2 peripherals clock.
2276 * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_EnableClock\n
2277 * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n
2278 * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n
2279 * C2APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n
2280 * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n
2281 * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n
2282 * @param Periphs This parameter can be a combination of the following values:
2283 * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC
2284 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2285 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2286 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2287 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
2288 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
2289 * @retval None
2290 */
LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)2291 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
2292 {
2293 __IO uint32_t tmpreg;
2294 SET_BIT(RCC->C2APB2ENR, Periphs);
2295 /* Delay after an RCC peripheral clock enabling */
2296 tmpreg = READ_BIT(RCC->C2APB2ENR, Periphs);
2297 (void)tmpreg;
2298 }
2299
2300 /**
2301 * @brief Check if C2APB2 peripheral clock is enabled or not
2302 * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_IsEnabledClock\n
2303 * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n
2304 * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n
2305 * C2APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n
2306 * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n
2307 * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n
2308 * @param Periphs This parameter can be a combination of the following values:
2309 * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC
2310 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2311 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2312 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2313 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
2314 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
2315 * @retval uint32_t
2316 */
LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)2317 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
2318 {
2319 return ((READ_BIT(RCC->C2APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
2320 }
2321
2322 /**
2323 * @brief Disable C2APB2 peripherals clock.
2324 * @rmtoll C2APB2ENR ADCEN LL_C2_APB2_GRP1_DisableClock\n
2325 * C2APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n
2326 * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n
2327 * C2APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n
2328 * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n
2329 * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n
2330 * @param Periphs This parameter can be a combination of the following values:
2331 * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC
2332 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2333 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2334 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2335 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
2336 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
2337 * @retval None
2338 */
LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)2339 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
2340 {
2341 CLEAR_BIT(RCC->C2APB2ENR, Periphs);
2342 }
2343
2344 /**
2345 * @brief Enable C2APB2 peripherals clock during Low Power (Sleep) mode.
2346 * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2347 * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2348 * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2349 * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2350 * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2351 * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2352 * @param Periphs This parameter can be a combination of the following values:
2353 * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC
2354 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2355 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2356 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2357 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
2358 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
2359 * @retval None
2360 */
LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)2361 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
2362 {
2363 __IO uint32_t tmpreg;
2364 SET_BIT(RCC->C2APB2SMENR, Periphs);
2365 /* Delay after an RCC peripheral clock enabling */
2366 tmpreg = READ_BIT(RCC->C2APB2SMENR, Periphs);
2367 (void)tmpreg;
2368 }
2369
2370 /**
2371 * @brief Check if C2APB2 peripheral clock is enabled by the clock gating during CPU1 CSleep mode.
2372 * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_IsEnabledClockSleep\n
2373 * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_IsEnabledClockSleep\n
2374 * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_IsEnabledClockSleep\n
2375 * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_IsEnabledClockSleep\n
2376 * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_IsEnabledClockSleep\n
2377 * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_IsEnabledClockSleep
2378 * @param Periphs This parameter can be a combination of the following values:
2379 * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC
2380 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2381 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2382 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2383 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
2384 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
2385 * @retval None
2386 */
LL_C2_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)2387 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)
2388 {
2389 return ((READ_BIT(RCC->C2APB2SMENR, Periphs) == (Periphs)) ? 1UL : 0UL);
2390 }
2391
2392 /**
2393 * @brief Disable C2APB2 peripherals clock during Low Power (Sleep) mode.
2394 * @rmtoll C2APB2SMENR ADCSMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2395 * C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2396 * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2397 * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2398 * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2399 * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2400 * @param Periphs This parameter can be a combination of the following values:
2401 * @arg @ref LL_C2_APB2_GRP1_PERIPH_ADC
2402 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2403 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2404 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2405 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
2406 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
2407 * @retval None
2408 */
LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)2409 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
2410 {
2411 CLEAR_BIT(RCC->C2APB2SMENR, Periphs);
2412 }
2413
2414 /**
2415 * @}
2416 */
2417
2418 /** @defgroup BUS_LL_EF_C2_APB3 C2 APB3
2419 * @{
2420 */
2421
2422 /**
2423 * @brief Enable C2APB3 peripherals clock.
2424 * @rmtoll C2APB3ENR SUBGHZSPIEN LL_C2_APB3_GRP1_EnableClock\n
2425 * @param Periphs This parameter can be a combination of the following values:
2426 * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI
2427 * @retval None
2428 */
LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)2429 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
2430 {
2431 __IO uint32_t tmpreg;
2432 SET_BIT(RCC->C2APB3ENR, Periphs);
2433 /* Delay after an RCC peripheral clock enabling */
2434 tmpreg = READ_BIT(RCC->C2APB3ENR, Periphs);
2435 (void)tmpreg;
2436 }
2437
2438 /**
2439 * @brief Check if C2APB3 peripheral clock is enabled or not
2440 * @rmtoll C2APB3ENR SUBGHZSPIEN LL_C2_APB3_GRP1_IsEnabledClock\n
2441 * @param Periphs This parameter can be a combination of the following values:
2442 * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI
2443 * @retval uint32_t
2444 */
LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)2445 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
2446 {
2447 return ((READ_BIT(RCC->C2APB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
2448 }
2449
2450 /**
2451 * @brief Disable C2APB3 peripherals clock.
2452 * @rmtoll C2APB3ENR SUBGHZSPIEN LL_C2_APB3_GRP1_DisableClock\n
2453 * @param Periphs This parameter can be a combination of the following values:
2454 * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI
2455 * @retval None
2456 */
LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)2457 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
2458 {
2459 CLEAR_BIT(RCC->C2APB3ENR, Periphs);
2460 }
2461
2462 /**
2463 * @brief Enable C2APB3 peripherals clock during Low Power (Sleep) mode.
2464 * @rmtoll C2APB3SMENR SUBGHZSPISMEN LL_C2_APB3_GRP1_EnableClockSleep\n
2465 * @param Periphs This parameter can be a combination of the following values:
2466 * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI
2467 * @retval None
2468 */
LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)2469 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
2470 {
2471 __IO uint32_t tmpreg;
2472 SET_BIT(RCC->C2APB3SMENR, Periphs);
2473 /* Delay after an RCC peripheral clock enabling */
2474 tmpreg = READ_BIT(RCC->C2APB3SMENR, Periphs);
2475 (void)tmpreg;
2476 }
2477
2478 /**
2479 * @brief Check if C2APB3 peripheral clock is enabled by the clock gating during CPU1 CSleep mode.
2480 * @rmtoll C2APB3SMENR SUBGHZSPISMEN LL_C2_APB3_GRP1_IsEnabledClockSleep
2481 * @param Periphs This parameter can be a combination of the following values:
2482 * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI
2483 * @retval None
2484 */
LL_C2_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)2485 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)
2486 {
2487 return ((READ_BIT(RCC->C2APB3SMENR, Periphs) == (Periphs)) ? 1UL : 0UL);
2488 }
2489
2490 /**
2491 * @brief Disable C2APB3 peripherals clock during Low Power (Sleep) mode.
2492 * @rmtoll C2APB3SMENR SUBGHZSPISMEN LL_C2_APB3_GRP1_DisableClockSleep\n
2493 * @param Periphs This parameter can be a combination of the following values:
2494 * @arg @ref LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI
2495 * @retval None
2496 */
LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)2497 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
2498 {
2499 CLEAR_BIT(RCC->C2APB3SMENR, Periphs);
2500 }
2501
2502 /**
2503 * @}
2504 */
2505 #endif /* DUAL_CORE */
2506
2507 /**
2508 * @}
2509 */
2510
2511 /**
2512 * @}
2513 */
2514
2515 #endif /* defined(RCC) */
2516
2517 /**
2518 * @}
2519 */
2520
2521 #ifdef __cplusplus
2522 }
2523 #endif
2524
2525 #endif /* __STM32WLxx_LL_BUS_H */
2526
