1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### RCC Limitations #####
20 ==============================================================================
21 [..]
22 A delay between an RCC peripheral clock enable and the effective peripheral
23 enabling should be taken into account in order to manage the peripheral read/write
24 from/to registers.
25 (+) This delay depends on the peripheral mapping.
26 (++) AHB , APB peripherals, 1 dummy read is necessary
27
28 [..]
29 Workarounds:
30 (#) For AHB , APB peripherals, a dummy read to the peripheral register has been
31 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
32
33 @endverbatim
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef STM32WBAxx_LL_BUS_H
39 #define STM32WBAxx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32wbaxx.h"
47
48 /** @addtogroup STM32WBAxx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60 /* Private constants ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
73 #define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN
74 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
75 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
76 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
77 #define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN
78 #if defined(GTZC_TZSC)
79 #define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_GTZC1EN
80 #endif /* GTZC_TZSC */
81 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN
82 /**
83 * @}
84 */
85
86 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
87 * @{
88 */
89 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
90 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
91 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
92 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
93 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
94 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
95 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
96 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
97 #if defined(SAES)
98 #define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR_SAESEN
99 #endif /* SAES */
100 #define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN
101 #define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN
102 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR_SRAM2EN
103 /**
104 * @}
105 */
106
107 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH
108 * @{
109 */
110 #define LL_AHB4_GRP1_PERIPH_ALL 0xFFFFFFFFU
111 #define LL_AHB4_GRP1_PERIPH_PWR RCC_AHB4ENR_PWREN
112 #define LL_AHB4_GRP1_PERIPH_ADC4 RCC_AHB4ENR_ADC4EN
113 /**
114 * @}
115 */
116
117 /** @defgroup BUS_LL_EC_AHB5_GRP1_PERIPH AHB5 GRP1 PERIPH
118 * @{
119 */
120 #define LL_AHB5_GRP1_PERIPH_ALL 0xFFFFFFFFU
121 #if defined(PTACONV)
122 #define LL_AHB5_GRP1_PERIPH_PTACONV RCC_AHB5ENR_PTACONVEN
123 #endif /* PTACONV */
124 #define LL_AHB5_GRP1_PERIPH_RADIO RCC_AHB5ENR_RADIOEN
125 /**
126 * @}
127 */
128
129 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
130 * @{
131 */
132 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
133 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
134 #if defined(TIM3)
135 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
136 #endif /* TIM3 */
137 #if defined(WWDG)
138 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
139 #endif /* WWDG */
140 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
141 #if defined(I2C1)
142 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
143 #endif /* I2C1 */
144 /**
145 * @}
146 */
147
148
149 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
150 * @{
151 */
152 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
153 #if defined(LPTIM2)
154 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
155 #endif /* LPTIM2 */
156 /**
157 * @}
158 */
159
160 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
161 * @{
162 */
163 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
164 #if defined(TIM1)
165 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
166 #endif /* TIM1 */
167 #if defined(SPI1)
168 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
169 #endif /* SPI1 */
170 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
171 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
172 #if defined(TIM17)
173 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
174 #endif /* TIM17 */
175 #if defined(SAI1)
176 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
177 #endif /* SAI1 */
178 /**
179 * @}
180 */
181
182 /** @defgroup BUS_LL_EC_APB7_GRP1_PERIPH APB7 GRP1 PERIPH
183 * @{
184 */
185 #define LL_APB7_GRP1_PERIPH_ALL 0xFFFFFFFFU
186 #define LL_APB7_GRP1_PERIPH_SYSCFG RCC_APB7ENR_SYSCFGEN
187 #define LL_APB7_GRP1_PERIPH_SPI3 RCC_APB7ENR_SPI3EN
188 #define LL_APB7_GRP1_PERIPH_LPUART1 RCC_APB7ENR_LPUART1EN
189 #define LL_APB7_GRP1_PERIPH_I2C3 RCC_APB7ENR_I2C3EN
190 #define LL_APB7_GRP1_PERIPH_LPTIM1 RCC_APB7ENR_LPTIM1EN
191 #if defined(COMP1)
192 #define LL_APB7_GRP1_PERIPH_COMP RCC_APB7ENR_COMPEN
193 #endif /* COMP1 */
194 #define LL_APB7_GRP1_PERIPH_RTCAPB RCC_APB7ENR_RTCAPBEN
195 /**
196 * @}
197 */
198
199 /**
200 * @}
201 */
202
203 /* Exported macros -----------------------------------------------------------*/
204 /* Exported functions --------------------------------------------------------*/
205 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
206 * @{
207 */
208
209 /** @defgroup BUS_LL_EF_AHB1 AHB1
210 * @{
211 */
212 /**
213 * @brief Enable AHB1 peripherals clock.
214 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n
215 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
216 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
217 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
218 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n
219 * AHB1ENR GTZC1EN LL_AHB1_GRP1_EnableClock\n
220 * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock
221 * @param Periphs This parameter can be a combination of the following values:
222 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
223 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
224 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*)
225 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
226 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
227 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
228 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
229 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
230 *
231 * (*) value not defined in all devices.
232 * @retval None
233 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)234 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
235 {
236 __IO uint32_t tmpreg;
237 SET_BIT(RCC->AHB1ENR, Periphs);
238 /* Delay after an RCC peripheral clock enabling */
239 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
240 (void)tmpreg;
241 }
242
243 /**
244 * @brief Check if AHB1 peripheral clock is enabled or not
245 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock
246 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
247 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
248 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
249 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n
250 * AHB1ENR GTZC1EN LL_AHB1_GRP1_IsEnabledClock\n
251 * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock
252 * @param Periphs This parameter can be a combination of the following values:
253 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
254 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*)
255 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
256 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
257 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
258 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
259 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
260 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
261 *
262 * (*) value not defined in all devices.
263 * @retval State of Periphs (1 or 0).
264 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)265 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
266 {
267 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
268 }
269
270 /**
271 * @brief Disable AHB1 peripherals clock.
272 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock
273 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
274 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
275 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
276 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n
277 * AHB1ENR GTZC1EN LL_AHB1_GRP1_DisableClock\n
278 * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock
279 * @param Periphs This parameter can be a combination of the following values:
280 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
281 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
282 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*)
283 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
284 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
285 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
286 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
287 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
288 *
289 * (*) value not defined in all devices.
290 * @retval None
291 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)292 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
293 {
294 CLEAR_BIT(RCC->AHB1ENR, Periphs);
295 }
296
297 /**
298 * @brief Force AHB1 peripherals reset.
299 * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n
300 * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n
301 * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n
302 * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset
303 * @param Periphs This parameter can be a combination of the following values:
304 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
305 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*)
306 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
307 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
308 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
309 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
310 * @retval None
311 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)312 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
313 {
314 SET_BIT(RCC->AHB1RSTR, Periphs);
315 }
316
317 /**
318 * @brief Release AHB1 peripherals reset.
319 * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n
320 * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n
321 * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n
322 * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n
323 * @param Periphs This parameter can be a combination of the following values:
324 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
325 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*)
326 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
327 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
328 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
329 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
330 * @retval None
331 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)332 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
333 {
334 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
335 }
336
337 /**
338 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
339 * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
340 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
341 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
342 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
343 * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
344 * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
345 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep
346 * @param Periphs This parameter can be a combination of the following values:
347 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
348 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*)
349 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
350 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
351 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
352 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
353 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
354 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
355 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
356 *
357 * (*) value not defined in all devices.
358 * @retval None
359 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)360 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
361 {
362 __IO uint32_t tmpreg;
363 SET_BIT(RCC->AHB1SMENR, Periphs);
364 /* Delay after an RCC peripheral clock enabling */
365 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
366 (void)tmpreg;
367 }
368
369 /**
370 * @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not
371 * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
372 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
373 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
374 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
375 * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
376 * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
377 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep
378 * @param Periphs This parameter can be a combination of the following values:
379 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
380 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*)
381 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
382 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
383 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
384 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
385 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
386 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
387 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
388 *
389 * (*) value not defined in all devices.
390 * @retval State of Periphs (1 or 0).
391 */
LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)392 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
393 {
394 return ((READ_BIT(RCC->AHB1SMENR, Periphs) == Periphs) ? 1UL : 0UL);
395 }
396
397 /**
398 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
399 * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
400 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
401 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
402 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
403 * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
404 * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
405 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep
406 * @param Periphs This parameter can be a combination of the following values:
407 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
408 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*)
409 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
410 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
411 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
412 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
413 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
414 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*)
415 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
416 *
417 * (*) value not defined in all devices.
418 * @retval None
419 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)420 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
421 {
422 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
423 }
424
425 /**
426 * @}
427 */
428
429 /** @defgroup BUS_LL_EF_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
430 * @{
431 */
432 /**
433 * @brief Enable AHB2 peripherals clock.
434 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
435 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
436 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
437 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
438 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
439 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
440 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
441 * AHB2ENR SAESEN LL_AHB2_GRP1_EnableClock\n
442 * AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock\n
443 * AHB2ENR PKAEN LL_AHB2_GRP1_EnableClock\n
444 * AHB2ENR SRAM2EN LL_AHB2_GRP1_EnableClock
445 * @param Periphs This parameter can be a combination of the following values:
446 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
447 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
448 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
449 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
450 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
451 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
452 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
453 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
454 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
455 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM
456 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
457 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
458 *
459 * (*) value not defined in all devices.
460 * @retval None
461 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)462 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
463 {
464 __IO uint32_t tmpreg;
465 SET_BIT(RCC->AHB2ENR, Periphs);
466 /* Delay after an RCC peripheral clock enabling */
467 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
468 (void)tmpreg;
469 }
470
471 /**
472 * @brief Check if AHB2 peripheral clock is enabled or not
473 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
474 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
475 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
476 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
477 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
478 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
479 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
480 * AHB2ENR SAESEN LL_AHB2_GRP1_IsEnabledClock\n
481 * AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock\n
482 * AHB2ENR PKAEN LL_AHB2_GRP1_IsEnabledClock\n
483 * AHB2ENR SRAM2EN LL_AHB2_GRP1_IsEnabledClock
484 * @param Periphs This parameter can be a combination of the following values:
485 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
486 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
487 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
488 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
489 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
490 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
491 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
492 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
493 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
494 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM
495 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
496 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
497 *
498 * (*) value not defined in all devices.
499 * @retval State of Periphs (1 or 0).
500 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)501 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
502 {
503 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
504 }
505
506 /**
507 * @brief Disable AHB2 peripherals clock.
508 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
509 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
510 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
511 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
512 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
513 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
514 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
515 * AHB2ENR SAESEN LL_AHB2_GRP1_DisableClock\n
516 * AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock\n
517 * AHB2ENR PKAEN LL_AHB2_GRP1_DisableClock\n
518 * AHB2ENR SRAM2EN LL_AHB2_GRP1_DisableClock
519 * @param Periphs This parameter can be a combination of the following values:
520 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
521 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
522 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
523 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
524 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
525 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
526 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
527 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
528 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
529 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM
530 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
531 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
532 *
533 * (*) value not defined in all devices.
534 * @retval None
535 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)536 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
537 {
538 CLEAR_BIT(RCC->AHB2ENR, Periphs);
539 }
540
541 /**
542 * @brief Force AHB2 peripherals reset.
543 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
544 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
545 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
546 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
547 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
548 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
549 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
550 * AHB2RSTR SAESRST LL_AHB2_GRP1_ForceReset\n
551 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset\n
552 * AHB2RSTR PKARST LL_AHB2_GRP1_ForceReset
553 * @param Periphs This parameter can be a combination of the following values:
554 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
555 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
556 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
557 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
558 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
559 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
560 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
561 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
562 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
563 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM
564 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
565 *
566 * (*) value not defined in all devices.
567 * @retval None
568 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)569 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
570 {
571 SET_BIT(RCC->AHB2RSTR, Periphs);
572 }
573
574 /**
575 * @brief Release AHB2 peripherals reset.
576 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
577 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
578 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
579 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
580 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
581 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
582 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
583 * AHB2RSTR SAESRST LL_AHB2_GRP1_ReleaseReset\n
584 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset\n
585 * AHB2RSTR PKARST LL_AHB2_GRP1_ReleaseReset\n
586 * AHB2RSTR SRAM1RST LL_AHB2_GRP1_ReleaseReset
587 * @param Periphs This parameter can be a combination of the following values:
588 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
589 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
590 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
591 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
592 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
593 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
594 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
595 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
596 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
597 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM
598 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
599 *
600 * (*) value not defined in all devices.
601 * @retval None
602 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)603 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
604 {
605 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
606 }
607
608 /**
609 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
610 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
611 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
612 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
613 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
614 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
615 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
616 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
617 * AHB2SMENR SAESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
618 * AHB2SMENR PKASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
619 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep
620 * @param Periphs This parameter can be a combination of the following values:
621 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
622 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
623 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
624 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
625 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
626 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
627 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
628 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
629 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
630 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
631 *
632 * (*) value not defined in all devices.
633 * @retval None
634 */
LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)635 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
636 {
637 __IO uint32_t tmpreg;
638 SET_BIT(RCC->AHB2SMENR, Periphs);
639 /* Delay after an RCC peripheral clock enabling */
640 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
641 (void)tmpreg;
642 }
643
644 /**
645 * @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not
646 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
647 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
648 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
649 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
650 * AHB2SMENR AESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
651 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
652 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
653 * AHB2SMENR SAESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
654 * AHB2SMENR PKASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
655 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep
656 * @param Periphs This parameter can be a combination of the following values:
657 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
658 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
659 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
660 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
661 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
662 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
663 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
664 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
665 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
666 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
667 *
668 * (*) value not defined in all devices.
669 * @retval State of Periphs (1 or 0).
670 */
LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)671 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
672 {
673 return ((READ_BIT(RCC->AHB2SMENR, Periphs) == Periphs) ? 1UL : 0UL);
674 }
675
676 /**
677 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
678 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
679 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
680 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
681 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
682 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
683 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
684 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
685 * AHB2SMENR SAESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
686 * AHB2SMENR PKASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
687 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep
688 * @param Periphs This parameter can be a combination of the following values:
689 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
690 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
691 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
692 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
693 * @arg @ref LL_AHB2_GRP1_PERIPH_AES
694 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH
695 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
696 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
697 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA
698 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
699 *
700 * (*) value not defined in all devices.
701 * @retval None
702 */
LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)703 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
704 {
705 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
706 }
707
708 /**
709 * @}
710 */
711
712 /** @defgroup BUS_LL_EF_AHB4 AHB4
713 * @{
714 */
715 /**
716 * @brief Enable AHB4 peripherals clock.
717 * @rmtoll AHB4ENR PWREN LL_AHB4_GRP1_EnableClock\n
718 * AHB4ENR ADC4EN LL_AHB4_GRP1_EnableClock
719 * @param Periphs This parameter can be a combination of the following values:
720 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
721 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
722 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
723 * @retval None
724 */
LL_AHB4_GRP1_EnableClock(uint32_t Periphs)725 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
726 {
727 __IO uint32_t tmpreg;
728 SET_BIT(RCC->AHB4ENR, Periphs);
729 /* Delay after an RCC peripheral clock enabling */
730 tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
731 (void)tmpreg;
732 }
733
734 /**
735 * @brief Check if AHB4 peripheral clock is enabled or not
736 * @rmtoll AHB4ENR PWREN LL_AHB4_GRP1_IsEnabledClock\n
737 * AHB4ENR ADC4EN LL_AHB4_GRP1_IsEnabledClock
738 * @param Periphs This parameter can be a combination of the following values:
739 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
740 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
741 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
742 * @retval State of Periphs (1 or 0).
743 */
LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)744 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
745 {
746 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1UL : 0UL);
747 }
748
749 /**
750 * @brief Disable AHB4 peripherals clock.
751 * @rmtoll AHB4ENR PWREN LL_AHB4_GRP1_DisableClock\n
752 * AHB4ENR ADC4EN LL_AHB4_GRP1_DisableClock
753 * @param Periphs This parameter can be a combination of the following values:
754 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
755 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
756 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
757 * @retval None
758 */
LL_AHB4_GRP1_DisableClock(uint32_t Periphs)759 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
760 {
761 CLEAR_BIT(RCC->AHB4ENR, Periphs);
762 }
763
764 /**
765 * @brief Force AHB4 peripherals reset.
766 * @rmtoll AHB4RSTR ADC4RST LL_AHB4_GRP1_ForceReset
767 * @param Periphs This parameter can be a combination of the following values:
768 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
769 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
770 * @retval None
771 */
LL_AHB4_GRP1_ForceReset(uint32_t Periphs)772 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
773 {
774 SET_BIT(RCC->AHB4RSTR, Periphs);
775 }
776
777 /**
778 * @brief Release AHB4 peripherals reset.
779 * @rmtoll AHB4RSTR ADC4RST LL_AHB4_GRP1_ReleaseReset
780 * @param Periphs This parameter can be a combination of the following values:
781 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
782 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
783 * @retval None
784 */
LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)785 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
786 {
787 CLEAR_BIT(RCC->AHB4RSTR, Periphs);
788 }
789
790 /**
791 * @brief Enable AHB4 peripheral clocks in Sleep and Stop modes
792 * @rmtoll AHB4SMENR PWRSMEN LL_AHB4_GRP1_EnableClockStopSleep\n
793 * AHB4SMENR ADC4SMEN LL_AHB4_GRP1_EnableClockStopSleep
794 * @param Periphs This parameter can be a combination of the following values:
795 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
796 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
797 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
798 * @retval None
799 */
LL_AHB4_GRP1_EnableClockStopSleep(uint32_t Periphs)800 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockStopSleep(uint32_t Periphs)
801 {
802 __IO uint32_t tmpreg;
803 SET_BIT(RCC->AHB4SMENR, Periphs);
804 /* Delay after an RCC peripheral clock enabling */
805 tmpreg = READ_BIT(RCC->AHB4SMENR, Periphs);
806 (void)tmpreg;
807 }
808
809 /**
810 * @brief Check if AHB4 peripheral clocks in Sleep and Stop modes is enabled or not
811 * @rmtoll AHB4SMENR PWRSMEN LL_AHB4_GRP1_IsEnabledClockStopSleep\n
812 * AHB4SMENR ADC4SMEN LL_AHB4_GRP1_IsEnabledClockStopSleep
813 * @param Periphs This parameter can be a combination of the following values:
814 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
815 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
816 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
817 * @retval State of Periphs (1 or 0).
818 */
LL_AHB4_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)819 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
820 {
821 return ((READ_BIT(RCC->AHB4SMENR, Periphs) == Periphs) ? 1UL : 0UL);
822 }
823
824 /**
825 * @brief Disable AHB4 peripheral clocks in Sleep and Stop modes
826 * @rmtoll AHB4SMENR PWRSMEN LL_AHB4_GRP1_DisableClockStopSleep\n
827 * AHB4SMENR ADC4SMEN LL_AHB4_GRP1_DisableClockStopSleep
828 * @param Periphs This parameter can be a combination of the following values:
829 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
830 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
831 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4
832 * @retval None
833 */
LL_AHB4_GRP1_DisableClockStopSleep(uint32_t Periphs)834 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockStopSleep(uint32_t Periphs)
835 {
836 CLEAR_BIT(RCC->AHB4SMENR, Periphs);
837 }
838
839 /**
840 * @}
841 */
842
843 /** @defgroup BUS_LL_EF_AHB5 AHB5
844 * @{
845 */
846 /**
847 * @brief Enable AHB5 peripherals clock.
848 * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_EnableClock\n
849 * AHB5ENR PTACONVEN LL_AHB5_GRP1_EnableClock
850 * @param Periphs This parameter can be a combination of the following values:
851 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
852 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
853 * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*)
854 *
855 * (*) value not defined in all devices.
856 * @retval None
857 */
LL_AHB5_GRP1_EnableClock(uint32_t Periphs)858 __STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs)
859 {
860 __IO uint32_t tmpreg;
861 SET_BIT(RCC->AHB5ENR, Periphs);
862 /* Delay after an RCC peripheral clock enabling */
863 tmpreg = READ_BIT(RCC->AHB5ENR, Periphs);
864 (void)tmpreg;
865 }
866
867 /**
868 * @brief Check if AHB5 peripheral clock is enabled or not
869 * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_IsEnabledClock\n
870 * AHB5ENR PTACONVEN LL_AHB5_GRP1_IsEnabledClock
871 * @param Periphs This parameter can be a combination of the following values:
872 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
873 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
874 * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*)
875 *
876 * (*) value not defined in all devices.
877 * @retval State of Periphs (1 or 0).
878 */
LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)879 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)
880 {
881 return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1UL : 0UL);
882 }
883
884 /**
885 * @brief Disable AHB5 peripherals clock.
886 * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_DisableClock\n
887 * AHB5ENR PTACONVEN LL_AHB5_GRP1_DisableClock
888 * @param Periphs This parameter can be a combination of the following values:
889 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
890 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
891 * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*)
892 *
893 * (*) value not defined in all devices.
894 * @retval None
895 */
LL_AHB5_GRP1_DisableClock(uint32_t Periphs)896 __STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs)
897 {
898 CLEAR_BIT(RCC->AHB5ENR, Periphs);
899 }
900
901 /**
902 * @brief Force AHB5 peripherals reset.
903 * @rmtoll AHB5RSTR RADIORST LL_AHB5_GRP1_ForceReset\n
904 * AHB5RSTR PTACONVRST LL_AHB5_GRP1_ForceReset
905 * @param Periphs This parameter can be a combination of the following values:
906 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
907 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
908 * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*)
909 *
910 * (*) value not defined in all devices.
911 * @retval None
912 */
LL_AHB5_GRP1_ForceReset(uint32_t Periphs)913 __STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs)
914 {
915 SET_BIT(RCC->AHB5RSTR, Periphs);
916 }
917
918 /**
919 * @brief Release AHB5 peripherals reset.
920 * @rmtoll AHB5RSTR RADIORST LL_AHB5_GRP1_ReleaseReset\n
921 * AHB5RSTR PTACONVRST LL_AHB5_GRP1_ReleaseReset
922 * @param Periphs This parameter can be a combination of the following values:
923 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
924 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
925 * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*)
926 *
927 * (*) value not defined in all devices.
928 * @retval None
929 */
LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)930 __STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)
931 {
932 CLEAR_BIT(RCC->AHB5RSTR, Periphs);
933 }
934
935 /**
936 * @brief Enable AHB5 peripheral clocks in Sleep and Stop modes
937 * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_EnableClockStopSleep\n
938 * AHB5SMENR PTACONVSMEN LL_AHB5_GRP1_EnableClockStopSleep
939 * @param Periphs This parameter can be a combination of the following values:
940 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
941 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
942 * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*)
943 *
944 * (*) value not defined in all devices.
945 * @retval None
946 */
LL_AHB5_GRP1_EnableClockStopSleep(uint32_t Periphs)947 __STATIC_INLINE void LL_AHB5_GRP1_EnableClockStopSleep(uint32_t Periphs)
948 {
949 __IO uint32_t tmpreg;
950 SET_BIT(RCC->AHB5SMENR, Periphs);
951 /* Delay after an RCC peripheral clock enabling */
952 tmpreg = READ_BIT(RCC->AHB5SMENR, Periphs);
953 (void)tmpreg;
954 }
955
956 /**
957 * @brief Check if AHB5 peripheral clocks in Sleep and Stop modes is enabled or not
958 * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_IsEnabledClockStopSleep\n
959 * AHB5SMENR PTACONVSMEN LL_AHB5_GRP1_IsEnabledClockStopSleep
960 * @param Periphs This parameter can be a combination of the following values:
961 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
962 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
963 * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*)
964 *
965 * (*) value not defined in all devices.
966 * @retval State of Periphs (1 or 0).
967 */
LL_AHB5_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)968 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
969 {
970 return ((READ_BIT(RCC->AHB5SMENR, Periphs) == Periphs) ? 1UL : 0UL);
971 }
972
973 /**
974 * @brief Disable AHB5 peripheral clocks in Sleep and Stop modes
975 * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_DisableClockStopSleep\n
976 * AHB5SMENR PTACONVSMEN LL_AHB5_GRP1_DisableClockStopSleep
977 * @param Periphs This parameter can be a combination of the following values:
978 * @arg @ref LL_AHB5_GRP1_PERIPH_ALL
979 * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO
980 * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*)
981 *
982 * (*) value not defined in all devices.
983 * @retval None
984 */
LL_AHB5_GRP1_DisableClockStopSleep(uint32_t Periphs)985 __STATIC_INLINE void LL_AHB5_GRP1_DisableClockStopSleep(uint32_t Periphs)
986 {
987 CLEAR_BIT(RCC->AHB5SMENR, Periphs);
988 }
989
990 /**
991 * @}
992 */
993
994 /** @defgroup BUS_LL_EF_APB1 APB1
995 * @{
996 */
997
998 /**
999 * @brief Enable APB1 peripherals clock.
1000 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
1001 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
1002 #if defined(WWDG)
1003 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
1004 #endif
1005 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
1006 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
1007 * @param Periphs This parameter can be a combination of the following values:
1008 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1009 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1010 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1011 #if defined(WWDG)
1012 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*)
1013 #endif
1014 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1015 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1016 *
1017 * (*) value not defined in all devices.
1018 * @retval None
1019 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1020 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1021 {
1022 __IO uint32_t tmpreg;
1023 SET_BIT(RCC->APB1ENR1, Periphs);
1024 /* Delay after an RCC peripheral clock enabling */
1025 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
1026 (void)tmpreg;
1027 }
1028
1029 /**
1030 * @brief Enable APB1 peripherals clock.
1031 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
1032 * @param Periphs This parameter can be a combination of the following values:
1033 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1034 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1035 * @retval None
1036 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)1037 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
1038 {
1039 __IO uint32_t tmpreg;
1040 SET_BIT(RCC->APB1ENR2, Periphs);
1041 /* Delay after an RCC peripheral clock enabling */
1042 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
1043 (void)tmpreg;
1044 }
1045
1046 /**
1047 * @brief Check if APB1 peripheral clock is enabled or not
1048 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1049 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1050 #if defined(WWDG)
1051 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1052 #endif
1053 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
1054 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1055 * @param Periphs This parameter can be a combination of the following values:
1056 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1057 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1058 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1059 #if defined(WWDG)
1060 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*)
1061 #endif
1062 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1063 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1064 *
1065 * (*) value not defined in all devices.
1066 * @retval State of Periphs (1 or 0).
1067 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1068 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1069 {
1070 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
1071 }
1072
1073 /**
1074 * @brief Check if APB1 peripheral clock is enabled or not
1075 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
1076 * @param Periphs This parameter can be a combination of the following values:
1077 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1078 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1079 * @retval State of Periphs (1 or 0).
1080 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1081 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1082 {
1083 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
1084 }
1085
1086 /**
1087 * @brief Disable APB1 peripherals clock.
1088 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
1089 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
1090 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
1091 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
1092 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
1093 * @param Periphs This parameter can be a combination of the following values:
1094 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1095 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1096 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1097 #if defined(WWDG)
1098 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*)
1099 #endif
1100 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1101 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1102 *
1103 * (*) value not defined in all devices.
1104 * @retval None
1105 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1106 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1107 {
1108 CLEAR_BIT(RCC->APB1ENR1, Periphs);
1109 }
1110
1111 /**
1112 * @brief Disable APB1 peripherals clock.
1113 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
1114 * @param Periphs This parameter can be a combination of the following values:
1115 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1116 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1117 * @retval None
1118 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1119 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1120 {
1121 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1122 }
1123
1124 /**
1125 * @brief Force APB1 peripherals reset.
1126 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1127 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
1128 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
1129 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
1130 * @param Periphs This parameter can be a combination of the following values:
1131 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1132 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1133 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1134 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1135 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1136 *
1137 * (*) value not defined in all devices.
1138 * @retval None
1139 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1140 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1141 {
1142 SET_BIT(RCC->APB1RSTR1, Periphs);
1143 }
1144
1145 /**
1146 * @brief Force APB1 peripherals reset.
1147 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
1148 * @param Periphs This parameter can be a combination of the following values:
1149 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1150 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1151 * @retval None
1152 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1153 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1154 {
1155 SET_BIT(RCC->APB1RSTR2, Periphs);
1156 }
1157
1158 /**
1159 * @brief Release APB1 peripherals reset.
1160 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1161 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
1162 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
1163 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
1164 * @param Periphs This parameter can be a combination of the following values:
1165 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1166 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1167 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1168 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1169 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1170 *
1171 * (*) value not defined in all devices.
1172 * @retval None
1173 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1174 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1175 {
1176 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1177 }
1178
1179 /**
1180 * @brief Release APB1 peripherals reset.
1181 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
1182 * @param Periphs This parameter can be a combination of the following values:
1183 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1184 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1185 * @retval None
1186 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1187 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1188 {
1189 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1190 }
1191
1192 /**
1193 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1194 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1195 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1196 #if defined(WWDG)
1197 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1198 #endif
1199 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1200 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1201 * @param Periphs This parameter can be a combination of the following values:
1202 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1203 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1204 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1205 #if defined(WWDG)
1206 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*)
1207 #endif
1208 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1209 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1210 *
1211 * (*) value not defined in all devices.
1212 * @retval None
1213 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)1214 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
1215 {
1216 __IO uint32_t tmpreg;
1217 SET_BIT(RCC->APB1SMENR1, Periphs);
1218 /* Delay after an RCC peripheral clock enabling */
1219 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
1220 (void)tmpreg;
1221 }
1222
1223 /**
1224 * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not
1225 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
1226 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
1227 #if defined(WWDG)
1228 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
1229 #endif
1230 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
1231 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
1232 * @param Periphs This parameter can be a combination of the following values:
1233 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1234 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1235 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1236 #if defined(WWDG)
1237 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*)
1238 #endif
1239 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1240 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1241 *
1242 * (*) value not defined in all devices.
1243 * @retval State of Periphs (1 or 0).
1244 */
LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)1245 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
1246 {
1247 return ((READ_BIT(RCC->APB1SMENR1, Periphs) == Periphs) ? 1UL : 0UL);
1248 }
1249
1250 /**
1251 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1252 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1253 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1254 #if defined(WWDG)
1255 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1256 #endif
1257 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1258 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1259 * @param Periphs This parameter can be a combination of the following values:
1260 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1261 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1262 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1263 #if defined(WWDG)
1264 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*)
1265 #endif
1266 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1267 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*)
1268 *
1269 * (*) value not defined in all devices.
1270 * @retval None
1271 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)1272 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
1273 {
1274 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
1275 }
1276
1277 /**
1278 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1279 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
1280 * @param Periphs This parameter can be a combination of the following values:
1281 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1282 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1283 * @retval None
1284 */
LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)1285 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
1286 {
1287 __IO uint32_t tmpreg;
1288 SET_BIT(RCC->APB1SMENR2, Periphs);
1289 /* Delay after an RCC peripheral clock enabling */
1290 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
1291 (void)tmpreg;
1292 }
1293
1294 /**
1295 * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not
1296 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep
1297 * @param Periphs This parameter can be a combination of the following values:
1298 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1299 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1300 * @retval State of Periphs (1 or 0).
1301 */
LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)1302 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)
1303 {
1304 return ((READ_BIT(RCC->APB1SMENR2, Periphs) == Periphs) ? 1UL : 0UL);
1305 }
1306
1307 /**
1308 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1309 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
1310 * @param Periphs This parameter can be a combination of the following values:
1311 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1312 * @retval None
1313 */
LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)1314 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
1315 {
1316 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
1317 }
1318
1319 /**
1320 * @}
1321 */
1322
1323 /** @defgroup BUS_LL_EF_APB2 APB2
1324 * @{
1325 */
1326
1327 /**
1328 * @brief Enable APB2 peripherals clock.
1329 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1330 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1331 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1332 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1333 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1334 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock
1335 * @param Periphs This parameter can be a combination of the following values:
1336 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1337 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1338 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1339 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1340 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1341 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1342 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1343 *
1344 * (*) value not defined in all devices.
1345 * @retval None
1346 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1347 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1348 {
1349 __IO uint32_t tmpreg;
1350 SET_BIT(RCC->APB2ENR, Periphs);
1351 /* Delay after an RCC peripheral clock enabling */
1352 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1353 (void)tmpreg;
1354 }
1355
1356 /**
1357 * @brief Check if APB2 peripheral clock is enabled or not
1358 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1359 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1360 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1361 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1362 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1363 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock
1364 * @param Periphs This parameter can be a combination of the following values:
1365 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1366 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1367 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1368 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1369 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1370 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1371 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1372 *
1373 * (*) value not defined in all devices.
1374 * @retval State of Periphs (1 or 0).
1375 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1376 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1377 {
1378 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
1379 }
1380
1381 /**
1382 * @brief Disable APB2 peripherals clock.
1383 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1384 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1385 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1386 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
1387 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
1388 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock
1389 * @param Periphs This parameter can be a combination of the following values:
1390 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1391 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1392 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1393 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1394 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1395 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1396 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1397 *
1398 * (*) value not defined in all devices.
1399 * @retval None
1400 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1401 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1402 {
1403 CLEAR_BIT(RCC->APB2ENR, Periphs);
1404 }
1405
1406 /**
1407 * @brief Force APB2 peripherals reset.
1408 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1409 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1410 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1411 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1412 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1413 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset
1414 * @param Periphs This parameter can be a combination of the following values:
1415 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1416 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1417 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1418 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1419 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1420 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1421 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1422 *
1423 * (*) value not defined in all devices.
1424 * @retval None
1425 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1426 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1427 {
1428 SET_BIT(RCC->APB2RSTR, Periphs);
1429 }
1430
1431 /**
1432 * @brief Release APB2 peripherals reset.
1433 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1434 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1435 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1436 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
1437 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
1438 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset
1439 * @param Periphs This parameter can be a combination of the following values:
1440 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1441 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1442 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1443 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1444 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1445 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1446 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1447 *
1448 * (*) value not defined in all devices.
1449 * @retval None
1450 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1451 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1452 {
1453 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1454 }
1455
1456 /**
1457 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
1458 * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1459 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1460 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1461 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1462 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1463 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep
1464 * @param Periphs This parameter can be a combination of the following values:
1465 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1466 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1467 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1468 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1469 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1470 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1471 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1472 *
1473 * (*) value not defined in all devices.
1474 * @retval None
1475 */
LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)1476 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
1477 {
1478 __IO uint32_t tmpreg;
1479 SET_BIT(RCC->APB2SMENR, Periphs);
1480 /* Delay after an RCC peripheral clock enabling */
1481 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
1482 (void)tmpreg;
1483 }
1484
1485
1486 /**
1487 * @brief Check if APB2 peripheral clocks in Sleep and Stop modes is enabled or not
1488 * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
1489 * APB2SMENR SPI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
1490 * APB2SMENR USART1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
1491 * APB2SMENR TIM16SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
1492 * APB2SMENR TIM17SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
1493 * APB2SMENR SAI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep
1494 * @param Periphs This parameter can be a combination of the following values:
1495 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1496 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1497 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1498 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1499 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1500 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1501 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1502 *
1503 * (*) value not defined in all devices.
1504 * @retval State of Periphs (1 or 0).
1505 */
LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)1506 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
1507 {
1508 return ((READ_BIT(RCC->APB2SMENR, Periphs) == Periphs) ? 1UL : 0UL);
1509 }
1510
1511 /**
1512 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
1513 * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1514 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1515 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1516 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1517 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1518 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep
1519 * @param Periphs This parameter can be a combination of the following values:
1520 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1521 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1522 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1523 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1524 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1525 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1526 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1527 *
1528 * (*) value not defined in all devices.
1529 * @retval None
1530 */
LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)1531 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
1532 {
1533 CLEAR_BIT(RCC->APB2SMENR, Periphs);
1534 }
1535
1536 /**
1537 * @}
1538 */
1539
1540
1541 /** @defgroup BUS_LL_EF_APB7 APB7
1542 * @{
1543 */
1544
1545 /**
1546 * @brief Enable APB7 peripherals clock.
1547 * @rmtoll APB7ENR SYSCFGEN LL_APB7_GRP1_EnableClock\n
1548 * APB7ENR SPI3EN LL_APB7_GRP1_EnableClock\n
1549 * APB7ENR LPUART1EN LL_APB7_GRP1_EnableClock\n
1550 * APB7ENR I2C3EN LL_APB7_GRP1_EnableClock\n
1551 * APB7ENR LPTIM1EN LL_APB7_GRP1_EnableClock\n
1552 * APB7ENR COMPEN LL_APB7_GRP1_EnableClock\n
1553 * APB7ENR RTCAPBEN LL_APB7_GRP1_EnableClock
1554 * @param Periphs This parameter can be a combination of the following values:
1555 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1556 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1557 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1558 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1559 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1560 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1561 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1562 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1563 *
1564 * (*) value not defined in all devices.
1565 * @retval None
1566 */
LL_APB7_GRP1_EnableClock(uint32_t Periphs)1567 __STATIC_INLINE void LL_APB7_GRP1_EnableClock(uint32_t Periphs)
1568 {
1569 __IO uint32_t tmpreg;
1570 SET_BIT(RCC->APB7ENR, Periphs);
1571 /* Delay after an RCC peripheral clock enabling */
1572 tmpreg = READ_BIT(RCC->APB7ENR, Periphs);
1573 (void)tmpreg;
1574 }
1575
1576 /**
1577 * @brief Check if APB7 peripheral clock is enabled or not
1578 * @rmtoll APB7ENR SYSCFGEN LL_APB7_GRP1_IsEnabledClock\n
1579 * APB7ENR SPI3EN LL_APB7_GRP1_IsEnabledClock\n
1580 * APB7ENR LPUART1EN LL_APB7_GRP1_IsEnabledClock\n
1581 * APB7ENR I2C3EN LL_APB7_GRP1_IsEnabledClock\n
1582 * APB7ENR LPTIM1EN LL_APB7_GRP1_IsEnabledClock\n
1583 * APB7ENR COMPEN LL_APB7_GRP1_IsEnabledClock\n
1584 * APB7ENR RTCAPBEN LL_APB7_GRP1_IsEnabledClock
1585 * @param Periphs This parameter can be a combination of the following values:
1586 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1587 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1588 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1589 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1590 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1591 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1592 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1593 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1594 *
1595 * (*) value not defined in all devices.
1596 * @retval State of Periphs (1 or 0).
1597 */
LL_APB7_GRP1_IsEnabledClock(uint32_t Periphs)1598 __STATIC_INLINE uint32_t LL_APB7_GRP1_IsEnabledClock(uint32_t Periphs)
1599 {
1600 return ((READ_BIT(RCC->APB7ENR, Periphs) == Periphs) ? 1UL : 0UL);
1601 }
1602
1603 /**
1604 * @brief Disable APB2 peripherals clock.
1605 * @rmtoll APB7ENR SYSCFGEN LL_APB7_GRP1_DisableClock\n
1606 * APB7ENR SPI3EN LL_APB7_GRP1_DisableClock\n
1607 * APB7ENR LPUART1EN LL_APB7_GRP1_DisableClock\n
1608 * APB7ENR I2C3EN LL_APB7_GRP1_DisableClock\n
1609 * APB7ENR LPTIM1EN LL_APB7_GRP1_DisableClock\n
1610 * APB7ENR COMPEN LL_APB7_GRP1_DisableClock\n
1611 * APB7ENR RTCAPBEN LL_APB7_GRP1_DisableClock
1612 * @param Periphs This parameter can be a combination of the following values:
1613 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1614 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1615 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1616 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1617 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1618 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1619 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1620 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1621 *
1622 * (*) value not defined in all devices.
1623 * @retval None
1624 */
LL_APB7_GRP1_DisableClock(uint32_t Periphs)1625 __STATIC_INLINE void LL_APB7_GRP1_DisableClock(uint32_t Periphs)
1626 {
1627 CLEAR_BIT(RCC->APB7ENR, Periphs);
1628 }
1629
1630 /**
1631 * @brief Force APB7 peripherals reset.
1632 * @rmtoll APB7RSTR SYSCFGRST LL_APB7_GRP1_ForceReset\n
1633 * APB7RSTR SPI3RST LL_APB7_GRP1_ForceReset\n
1634 * APB7RSTR LPUART1RST LL_APB7_GRP1_ForceReset\n
1635 * APB7RSTR I2C3RST LL_APB7_GRP1_ForceReset\n
1636 * APB7RSTR LPTIM1RST LL_APB7_GRP1_ForceReset\n
1637 * APB7RSTR COMPRST LL_APB7_GRP1_ForceReset\n
1638 * @param Periphs This parameter can be a combination of the following values:
1639 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1640 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1641 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1642 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1643 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1644 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1645 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1646 *
1647 * (*) value not defined in all devices.
1648 * @retval None
1649 */
LL_APB7_GRP1_ForceReset(uint32_t Periphs)1650 __STATIC_INLINE void LL_APB7_GRP1_ForceReset(uint32_t Periphs)
1651 {
1652 SET_BIT(RCC->APB7RSTR, Periphs);
1653 }
1654
1655 /**
1656 * @brief Release APB7 peripherals reset.
1657 * @rmtoll APB7RSTR SYSCFGRST LL_APB7_GRP1_ReleaseReset\n
1658 * APB7RSTR SPI3RST LL_APB7_GRP1_ReleaseReset\n
1659 * APB7RSTR LPUART1RST LL_APB7_GRP1_ReleaseReset\n
1660 * APB7RSTR I2C3RST LL_APB7_GRP1_ReleaseReset\n
1661 * APB7RSTR LPTIM1RST LL_APB7_GRP1_ReleaseReset\n
1662 * APB7RSTR COMPRST LL_APB7_GRP1_ReleaseReset\n
1663 * @param Periphs This parameter can be a combination of the following values:
1664 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1665 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1666 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1667 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1668 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1669 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1670 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1671 *
1672 * (*) value not defined in all devices.
1673 * @retval None
1674 */
LL_APB7_GRP1_ReleaseReset(uint32_t Periphs)1675 __STATIC_INLINE void LL_APB7_GRP1_ReleaseReset(uint32_t Periphs)
1676 {
1677 CLEAR_BIT(RCC->APB7RSTR, Periphs);
1678 }
1679
1680 /**
1681 * @brief Enable APB7 peripheral clocks in Sleep and Stop modes
1682 * @rmtoll APB7SMENR SYSCFGSMEN LL_APB7_GRP1_EnableClockStopSleep\n
1683 * APB7SMENR SPI3SMEN LL_APB7_GRP1_EnableClockStopSleep\n
1684 * APB7SMENR LPUART1SMEN LL_APB7_GRP1_EnableClockStopSleep\n
1685 * APB7SMENR I2C3SMEN LL_APB7_GRP1_EnableClockStopSleep\n
1686 * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_EnableClockStopSleep\n
1687 * APB7SMENR COMPSMEN LL_APB7_GRP1_EnableClockStopSleep\n
1688 * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_EnableClockStopSleep
1689 * @param Periphs This parameter can be a combination of the following values:
1690 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1691 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1692 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1693 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1694 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1695 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1696 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1697 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1698 *
1699 * (*) value not defined in all devices.
1700 * @retval None
1701 */
LL_APB7_GRP1_EnableClockStopSleep(uint32_t Periphs)1702 __STATIC_INLINE void LL_APB7_GRP1_EnableClockStopSleep(uint32_t Periphs)
1703 {
1704 __IO uint32_t tmpreg;
1705 SET_BIT(RCC->APB7SMENR, Periphs);
1706 /* Delay after an RCC peripheral clock enabling */
1707 tmpreg = READ_BIT(RCC->APB7SMENR, Periphs);
1708 (void)tmpreg;
1709 }
1710
1711
1712 /**
1713 * @brief Check if APB7 peripheral clocks in Sleep and Stop modes is enabled or not
1714 * @rmtoll APB7SMENR SYSCFGSMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1715 * APB7SMENR SPI3SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1716 * APB7SMENR LPUART1SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1717 * APB7SMENR I2C3SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1718 * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1719 * APB7SMENR COMPSMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n
1720 * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_IsEnabledClockStopSleep
1721 * @param Periphs This parameter can be a combination of the following values:
1722 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1723 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1724 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1725 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1726 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1727 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1728 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1729 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1730 *
1731 * (*) value not defined in all devices.
1732 * @retval State of Periphs (1 or 0).
1733 */
LL_APB7_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)1734 __STATIC_INLINE uint32_t LL_APB7_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
1735 {
1736 return ((READ_BIT(RCC->APB7SMENR, Periphs) == Periphs) ? 1UL : 0UL);
1737 }
1738
1739 /**
1740 * @brief Disable APB7 peripheral clocks in Sleep and Stop modes
1741 * @rmtoll APB7SMENR SYSCFGSMEN LL_APB7_GRP1_DisableClockStopSleep\n
1742 * APB7SMENR SPI3SMEN LL_APB7_GRP1_DisableClockStopSleep\n
1743 * APB7SMENR LPUART1SMEN LL_APB7_GRP1_DisableClockStopSleep\n
1744 * APB7SMENR I2C3SMEN LL_APB7_GRP1_DisableClockStopSleep\n
1745 * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_DisableClockStopSleep\n
1746 * APB7SMENR COMPSMEN LL_APB7_GRP1_DisableClockStopSleep\n
1747 * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_DisableClockStopSleep
1748 * @param Periphs This parameter can be a combination of the following values:
1749 * @arg @ref LL_APB7_GRP1_PERIPH_ALL
1750 * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG
1751 * @arg @ref LL_APB7_GRP1_PERIPH_SPI3
1752 * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1
1753 * @arg @ref LL_APB7_GRP1_PERIPH_I2C3
1754 * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1
1755 * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*)
1756 * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB
1757 *
1758 * (*) value not defined in all devices.
1759 * @retval None
1760 */
LL_APB7_GRP1_DisableClockStopSleep(uint32_t Periphs)1761 __STATIC_INLINE void LL_APB7_GRP1_DisableClockStopSleep(uint32_t Periphs)
1762 {
1763 CLEAR_BIT(RCC->APB7SMENR, Periphs);
1764 }
1765
1766 /**
1767 * @}
1768 */
1769
1770 /**
1771 * @}
1772 */
1773
1774 /**
1775 * @}
1776 */
1777
1778 #endif /* defined(RCC) */
1779
1780 /**
1781 * @}
1782 */
1783
1784 #ifdef __cplusplus
1785 }
1786 #endif
1787
1788 #endif /* STM32WBAxx_LL_BUS_H */
1789
1790
