1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ##### RCC Limitations #####
19 ==============================================================================
20 [..]
21 A delay between an RCC peripheral clock enable and the effective peripheral
22 enabling should be taken into account in order to manage the peripheral read/write
23 from/to registers.
24 (+) This delay depends on the peripheral mapping.
25 (++) AHB & APB peripherals, 1 dummy read is necessary
26
27 [..]
28 Workarounds:
29 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
30 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
31
32 @endverbatim
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef STM32N6xx_LL_BUS_H
38 #define STM32N6xx_LL_BUS_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32n6xx.h"
46
47 /** @addtogroup STM32N6xx_LL_Driver
48 * @{
49 */
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private variables ---------------------------------------------------------*/
57
58 /* Private constants ---------------------------------------------------------*/
59
60 /* Private macros ------------------------------------------------------------*/
61
62 /* Exported types ------------------------------------------------------------*/
63
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AXI AXI
70 * @{
71 */
72 #define LL_ACLKN RCC_BUSENR_ACLKNEN
73 #define LL_ACLKNC RCC_BUSENR_ACLKNCEN
74 #define LL_AHBM RCC_BUSENR_AHBMEN
75 #define LL_AHB1 RCC_BUSENR_AHB1EN
76 #define LL_AHB2 RCC_BUSENR_AHB2EN
77 #define LL_AHB3 RCC_BUSENR_AHB3EN
78 #define LL_AHB4 RCC_BUSENR_AHB4EN
79 #define LL_AHB5 RCC_BUSENR_AHB5EN
80 #define LL_APB1 RCC_BUSENR_APB1EN
81 #define LL_APB2 RCC_BUSENR_APB2EN
82 #define LL_APB3 RCC_BUSENR_APB3EN
83 #define LL_APB4 RCC_BUSENR_APB4EN
84 #define LL_APB5 RCC_BUSENR_APB5EN
85 /**
86 * @}
87 */
88
89 /** @defgroup BUS_LL_EC_MEM MEM
90 * @{
91 */
92 #define LL_MEM_AXISRAM1 RCC_MEMENR_AXISRAM1EN
93 #define LL_MEM_AXISRAM2 RCC_MEMENR_AXISRAM2EN
94 #define LL_MEM_AXISRAM3 RCC_MEMENR_AXISRAM3EN
95 #define LL_MEM_AXISRAM4 RCC_MEMENR_AXISRAM4EN
96 #define LL_MEM_AXISRAM5 RCC_MEMENR_AXISRAM5EN
97 #define LL_MEM_AXISRAM6 RCC_MEMENR_AXISRAM6EN
98 #define LL_MEM_AHBSRAM1 RCC_MEMENR_AHBSRAM1EN
99 #define LL_MEM_AHBSRAM2 RCC_MEMENR_AHBSRAM2EN
100 #define LL_MEM_BKPSRAM RCC_MEMENR_BKPSRAMEN
101 #define LL_MEM_FLEXRAM RCC_MEMENR_FLEXRAMEN
102 #define LL_MEM_CACHEAXIRAM RCC_MEMENR_CACHEAXIRAMEN
103 #define LL_MEM_VENCRAM RCC_MEMENR_VENCRAMEN
104 #define LL_MEM_BOOTROM RCC_MEMENR_BOOTROMEN
105 /**
106 * @}
107 */
108
109 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
110 * @{
111 */
112 #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN
113 #define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN
114 #define LL_AHB1_GRP1_PERIPH_ALL (LL_AHB1_GRP1_PERIPH_ADC12 | LL_AHB1_GRP1_PERIPH_GPDMA1)
115 /**
116 * @}
117 */
118
119 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
120 * @{
121 */
122 #define LL_AHB2_GRP1_PERIPH_ADF1 RCC_AHB2ENR_ADF1EN
123 #define LL_AHB2_GRP1_PERIPH_MDF1 RCC_AHB2ENR_MDF1EN
124 #define LL_AHB2_GRP1_PERIPH_RAMCFG RCC_AHB2ENR_RAMCFGEN
125 #define LL_AHB2_GRP1_PERIPH_ALL (LL_AHB2_GRP1_PERIPH_ADF1 | LL_AHB2_GRP1_PERIPH_MDF1 | \
126 LL_AHB2_GRP1_PERIPH_RAMCFG)
127 /**
128 * @}
129 */
130
131 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
132 * @{
133 */
134 #if defined(CRYP)
135 #define LL_AHB3_GRP1_PERIPH_CRYP RCC_AHB3ENR_CRYPEN
136 #else
137 #define LL_AHB3_GRP1_PERIPH_CRYP
138 #endif /* CRYP */
139 #define LL_AHB3_GRP1_PERIPH_HASH RCC_AHB3ENR_HASHEN
140 #define LL_AHB3_GRP1_PERIPH_IAC RCC_AHB3ENR_IACEN
141 #if defined(PKA)
142 #define LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN
143 #else
144 #define LL_AHB3_GRP1_PERIPH_PKA
145 #endif /* PKA */
146 #define LL_AHB3_GRP1_PERIPH_RIFSC RCC_AHB3ENR_RIFSCEN
147 #define LL_AHB3_GRP1_PERIPH_RISAF RCC_AHB3ENR_RISAFEN
148 #define LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN
149 #if defined(SAES)
150 #define LL_AHB3_GRP1_PERIPH_SAES RCC_AHB3ENR_SAESEN
151 #else
152 #define LL_AHB3_GRP1_PERIPH_SAES
153 #endif /* SAES */
154 #define LL_AHB3_GRP1_PERIPH_ALL (LL_AHB3_GRP1_PERIPH_CRYP | LL_AHB3_GRP1_PERIPH_HASH | \
155 LL_AHB3_GRP1_PERIPH_IAC | LL_AHB3_GRP1_PERIPH_PKA | \
156 LL_AHB3_GRP1_PERIPH_RIFSC | LL_AHB3_GRP1_PERIPH_RISAF | \
157 LL_AHB3_GRP1_PERIPH_RNG | LL_AHB3_GRP1_PERIPH_SAES)
158 /**
159 * @}
160 */
161
162 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH
163 * @{
164 */
165 #define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN
166 #define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN
167 #define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN
168 #define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN
169 #define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN
170 #define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN
171 #define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN
172 #define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN
173 #define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN
174 #define LL_AHB4_GRP1_PERIPH_GPION RCC_AHB4ENR_GPIONEN
175 #define LL_AHB4_GRP1_PERIPH_GPIOO RCC_AHB4ENR_GPIOOEN
176 #define LL_AHB4_GRP1_PERIPH_GPIOP RCC_AHB4ENR_GPIOPEN
177 #define LL_AHB4_GRP1_PERIPH_GPIOQ RCC_AHB4ENR_GPIOQEN
178 #define LL_AHB4_GRP1_PERIPH_PWR RCC_AHB4ENR_PWREN
179 #define LL_AHB4_GRP1_PERIPH_ALL (LL_AHB4_GRP1_PERIPH_CRC | LL_AHB4_GRP1_PERIPH_GPIOA | \
180 LL_AHB4_GRP1_PERIPH_GPIOB | LL_AHB4_GRP1_PERIPH_GPIOC | \
181 LL_AHB4_GRP1_PERIPH_GPIOD | LL_AHB4_GRP1_PERIPH_GPIOE | \
182 LL_AHB4_GRP1_PERIPH_GPIOF | LL_AHB4_GRP1_PERIPH_GPIOG | \
183 LL_AHB4_GRP1_PERIPH_GPIOH | LL_AHB4_GRP1_PERIPH_GPION | \
184 LL_AHB4_GRP1_PERIPH_GPIOO | LL_AHB4_GRP1_PERIPH_GPIOP | \
185 LL_AHB4_GRP1_PERIPH_GPIOQ | LL_AHB4_GRP1_PERIPH_PWR)
186 /**
187 * @}
188 */
189
190 /** @defgroup BUS_LL_EC_AHB5_GRP1_PERIPH AHB5 GRP1 PERIPH
191 * @{
192 */
193 #define LL_AHB5_GRP1_PERIPH_DMA2D RCC_AHB5ENR_DMA2DEN
194 #define LL_AHB5_GRP1_PERIPH_ETH1 RCC_AHB5ENR_ETH1EN
195 #define LL_AHB5_GRP1_PERIPH_ETH1MAC RCC_AHB5ENR_ETH1MACEN
196 #define LL_AHB5_GRP1_PERIPH_ETH1TX RCC_AHB5ENR_ETH1TXEN
197 #define LL_AHB5_GRP1_PERIPH_ETH1RX RCC_AHB5ENR_ETH1RXEN
198 #define LL_AHB5_GRP1_PERIPH_FMC RCC_AHB5ENR_FMCEN
199 #define LL_AHB5_GRP1_PERIPH_GFXMMU RCC_AHB5ENR_GFXMMUEN
200 #define LL_AHB5_GRP1_PERIPH_GPU2D RCC_AHB5ENR_GPU2DEN
201 #define LL_AHB5_GRP1_PERIPH_HPDMA1 RCC_AHB5ENR_HPDMA1EN
202 #define LL_AHB5_GRP1_PERIPH_XSPI1 RCC_AHB5ENR_XSPI1EN
203 #define LL_AHB5_GRP1_PERIPH_XSPI2 RCC_AHB5ENR_XSPI2EN
204 #define LL_AHB5_GRP1_PERIPH_XSPI3 RCC_AHB5ENR_XSPI3EN
205 #define LL_AHB5_GRP1_PERIPH_XSPIM RCC_AHB5ENR_XSPIMEN
206 #define LL_AHB5_GRP1_PERIPH_JPEG RCC_AHB5ENR_JPEGEN
207 #define LL_AHB5_GRP1_PERIPH_MCE1 RCC_AHB5ENR_MCE1EN
208 #define LL_AHB5_GRP1_PERIPH_MCE2 RCC_AHB5ENR_MCE2EN
209 #define LL_AHB5_GRP1_PERIPH_MCE3 RCC_AHB5ENR_MCE3EN
210 #define LL_AHB5_GRP1_PERIPH_MCE4 RCC_AHB5ENR_MCE4EN
211 #define LL_AHB5_GRP1_PERIPH_CACHEAXI RCC_AHB5ENR_CACHEAXIEN
212 #define LL_AHB5_GRP1_PERIPH_NPU RCC_AHB5ENR_NPUEN
213 #define LL_AHB5_GRP1_PERIPH_OTG1 RCC_AHB5ENR_OTG1EN
214 #define LL_AHB5_GRP1_PERIPH_OTG2 RCC_AHB5ENR_OTG2EN
215 #define LL_AHB5_GRP1_PERIPH_OTGPHY1 RCC_AHB5ENR_OTGPHY1EN
216 #define LL_AHB5_GRP1_PERIPH_OTGPHY2 RCC_AHB5ENR_OTGPHY2EN
217 #define LL_AHB5_GRP1_PERIPH_OTG1PHYCTL RCC_AHB5RSTR_OTG1PHYCTLRST
218 #define LL_AHB5_GRP1_PERIPH_OTG2PHYCTL RCC_AHB5RSTR_OTG2PHYCTLRST
219 #define LL_AHB5_GRP1_PERIPH_PSSI RCC_AHB5ENR_PSSIEN
220 #define LL_AHB5_GRP1_PERIPH_SDMMC1 RCC_AHB5ENR_SDMMC1EN
221 #define LL_AHB5_GRP1_PERIPH_SDMMC2 RCC_AHB5ENR_SDMMC2EN
222 #define LL_AHB5_GRP1_PERIPH_ALL (LL_AHB5_GRP1_PERIPH_DMA2D | LL_AHB5_GRP1_PERIPH_ETH1 | \
223 LL_AHB5_GRP1_PERIPH_ETH1MAC | LL_AHB5_GRP1_PERIPH_ETH1TX | \
224 LL_AHB5_GRP1_PERIPH_ETH1RX | LL_AHB5_GRP1_PERIPH_FMC | \
225 LL_AHB5_GRP1_PERIPH_GFXMMU | LL_AHB5_GRP1_PERIPH_GPU2D | \
226 LL_AHB5_GRP1_PERIPH_HPDMA1 | LL_AHB5_GRP1_PERIPH_XSPI1 | \
227 LL_AHB5_GRP1_PERIPH_XSPI2 | LL_AHB5_GRP1_PERIPH_XSPI3 | \
228 LL_AHB5_GRP1_PERIPH_XSPIM | LL_AHB5_GRP1_PERIPH_JPEG | \
229 LL_AHB5_GRP1_PERIPH_MCE1 | LL_AHB5_GRP1_PERIPH_MCE2 | \
230 LL_AHB5_GRP1_PERIPH_MCE3 | LL_AHB5_GRP1_PERIPH_MCE4 | \
231 LL_AHB5_GRP1_PERIPH_CACHEAXI | LL_AHB5_GRP1_PERIPH_NPU | \
232 LL_AHB5_GRP1_PERIPH_OTG1 | LL_AHB5_GRP1_PERIPH_OTG2 | \
233 LL_AHB5_GRP1_PERIPH_OTGPHY1 | LL_AHB5_GRP1_PERIPH_OTGPHY2 | \
234 LL_AHB5_GRP1_PERIPH_PSSI | LL_AHB5_GRP1_PERIPH_SDMMC1 | \
235 LL_AHB5_GRP1_PERIPH_SDMMC2)
236 /**
237 * @}
238 */
239
240 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
241 * @{
242 */
243 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
244 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
245 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
246 #define LL_APB1_GRP1_PERIPH_I3C1 RCC_APB1ENR1_I3C1EN
247 #define LL_APB1_GRP1_PERIPH_I3C2 RCC_APB1ENR1_I3C2EN
248 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
249 #define LL_APB1_GRP1_PERIPH_SPDIFRX1 RCC_APB1ENR1_SPDIFRX1EN
250 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
251 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
252 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
253 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
254 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
255 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
256 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
257 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
258 #define LL_APB1_GRP1_PERIPH_TIM10 RCC_APB1ENR1_TIM10EN
259 #define LL_APB1_GRP1_PERIPH_TIM11 RCC_APB1ENR1_TIM11EN
260 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR1_TIM12EN
261 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR1_TIM13EN
262 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR1_TIM14EN
263 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
264 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
265 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
266 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
267 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR1_UART7EN
268 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR1_UART8EN
269 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
270 #define LL_APB1_GRP1_PERIPH_ALL (LL_APB1_GRP1_PERIPH_I2C1 | LL_APB1_GRP1_PERIPH_I2C2 | \
271 LL_APB1_GRP1_PERIPH_I2C3 | LL_APB1_GRP1_PERIPH_I3C1 | \
272 LL_APB1_GRP1_PERIPH_I3C2 | LL_APB1_GRP1_PERIPH_LPTIM1 | \
273 LL_APB1_GRP1_PERIPH_SPDIFRX1 | LL_APB1_GRP1_PERIPH_SPI2 | \
274 LL_APB1_GRP1_PERIPH_SPI3 | LL_APB1_GRP1_PERIPH_TIM2 | \
275 LL_APB1_GRP1_PERIPH_TIM3 | LL_APB1_GRP1_PERIPH_TIM4 | \
276 LL_APB1_GRP1_PERIPH_TIM5 | LL_APB1_GRP1_PERIPH_TIM6 | \
277 LL_APB1_GRP1_PERIPH_TIM7 | LL_APB1_GRP1_PERIPH_TIM10 | \
278 LL_APB1_GRP1_PERIPH_TIM11 | LL_APB1_GRP1_PERIPH_TIM12 | \
279 LL_APB1_GRP1_PERIPH_TIM13 | LL_APB1_GRP1_PERIPH_TIM14 | \
280 LL_APB1_GRP1_PERIPH_USART2 | LL_APB1_GRP1_PERIPH_USART3 | \
281 LL_APB1_GRP1_PERIPH_UART4 | LL_APB1_GRP1_PERIPH_UART5 | \
282 LL_APB1_GRP1_PERIPH_UART7 | LL_APB1_GRP1_PERIPH_UART8 | \
283 LL_APB1_GRP1_PERIPH_WWDG)
284 /**
285 * @}
286 */
287
288 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
289 * @{
290 */
291 #define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1ENR2_FDCANEN
292 #define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1ENR2_MDIOSEN
293 #define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
294 #define LL_APB1_GRP2_PERIPH_ALL (LL_APB1_GRP2_PERIPH_FDCAN | LL_APB1_GRP2_PERIPH_MDIOS | \
295 LL_APB1_GRP2_PERIPH_UCPD1)
296 /**
297 * @}
298 */
299
300 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
301 * @{
302 */
303 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
304 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
305 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
306 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
307 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
308 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
309 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
310 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
311 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
312 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
313 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
314 #define LL_APB2_GRP1_PERIPH_TIM18 RCC_APB2ENR_TIM18EN
315 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
316 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
317 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
318 #define LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN
319 #define LL_APB2_GRP1_PERIPH_ALL (LL_APB2_GRP1_PERIPH_SAI1 | LL_APB2_GRP1_PERIPH_SAI2 | \
320 LL_APB2_GRP1_PERIPH_SPI1 | LL_APB2_GRP1_PERIPH_SPI4 | \
321 LL_APB2_GRP1_PERIPH_SPI5 | LL_APB2_GRP1_PERIPH_TIM1 | \
322 LL_APB2_GRP1_PERIPH_TIM8 | LL_APB2_GRP1_PERIPH_TIM9 | \
323 LL_APB2_GRP1_PERIPH_TIM15 | LL_APB2_GRP1_PERIPH_TIM16 | \
324 LL_APB2_GRP1_PERIPH_TIM17 | LL_APB2_GRP1_PERIPH_TIM18 | \
325 LL_APB2_GRP1_PERIPH_USART1 | LL_APB2_GRP1_PERIPH_USART6 | \
326 LL_APB2_GRP1_PERIPH_UART9 | LL_APB2_GRP1_PERIPH_USART10)
327 /**
328 * @}
329 */
330
331 /** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH
332 * @{
333 */
334 #define LL_APB4_GRP1_PERIPH_HDP RCC_APB4ENR1_HDPEN
335 #define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR1_I2C4EN
336 #define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR1_LPTIM2EN
337 #define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR1_LPTIM3EN
338 #define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR1_LPTIM4EN
339 #define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR1_LPTIM5EN
340 #define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR1_LPUART1EN
341 #define LL_APB4_GRP1_PERIPH_RTC RCC_APB4ENR1_RTCEN
342 #define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR1_RTCAPBEN
343 #define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR1_SPI6EN
344 #define LL_APB4_GRP1_PERIPH_VREFBUF RCC_APB4ENR1_VREFBUFEN
345 #define LL_APB4_GRP1_PERIPH_ALL (LL_APB4_GRP1_PERIPH_HDP | LL_APB4_GRP1_PERIPH_I2C4 | \
346 LL_APB4_GRP1_PERIPH_LPTIM2 | LL_APB4_GRP1_PERIPH_LPTIM3 | \
347 LL_APB4_GRP1_PERIPH_LPTIM4 | LL_APB4_GRP1_PERIPH_LPTIM5 | \
348 LL_APB4_GRP1_PERIPH_LPUART1 | LL_APB4_GRP1_PERIPH_RTC | \
349 LL_APB4_GRP1_PERIPH_RTCAPB | LL_APB4_GRP1_PERIPH_SPI6 | \
350 LL_APB4_GRP1_PERIPH_VREFBUF)
351 /**
352 * @}
353 */
354
355 /** @defgroup BUS_LL_EC_APB4_GRP2_PERIPH APB4 GRP2 PERIPH
356 * @{
357 */
358 #define LL_APB4_GRP2_PERIPH_BSEC RCC_APB4ENR2_BSECEN
359 #define LL_APB4_GRP2_PERIPH_DTS RCC_APB4ENR2_DTSEN
360 #define LL_APB4_GRP2_PERIPH_SYSCFG RCC_APB4ENR2_SYSCFGEN
361 #define LL_APB4_GRP2_PERIPH_ALL (LL_APB4_GRP2_PERIPH_BSEC | LL_APB4_GRP2_PERIPH_DTS | \
362 LL_APB4_GRP2_PERIPH_SYSCFG)
363 /**
364 * @}
365 */
366
367 /** @defgroup BUS_LL_EC_APB5_GRP1_PERIPH APB5 GRP1 PERIPH
368 * @{
369 */
370 #define LL_APB5_GRP1_PERIPH_CSI RCC_APB5ENR_CSIEN
371 #define LL_APB5_GRP1_PERIPH_DCMIPP RCC_APB5ENR_DCMIPPEN
372 #define LL_APB5_GRP1_PERIPH_GFXTIM RCC_APB5ENR_GFXTIMEN
373 #define LL_APB5_GRP1_PERIPH_LTDC RCC_APB5ENR_LTDCEN
374 #if defined(VENC)
375 #define LL_APB5_GRP1_PERIPH_VENC RCC_APB5ENR_VENCEN
376 #else
377 #define LL_APB5_GRP1_PERIPH_VENC
378 #endif /* VENC */
379 #define LL_APB5_GRP1_PERIPH_ALL (LL_APB5_GRP1_PERIPH_CSI | LL_APB5_GRP1_PERIPH_DCMIPP | \
380 LL_APB5_GRP1_PERIPH_GFXTIM | LL_APB5_GRP1_PERIPH_LTDC | \
381 LL_APB5_GRP1_PERIPH_VENC)
382 /**
383 * @}
384 */
385
386 /** @defgroup BUS_LL_EC_MISC MISC
387 * @{
388 */
389 #define LL_DBG RCC_MISCENR_DBGEN
390 #define LL_MCO1 RCC_MISCENR_MCO1EN
391 #define LL_MCO2 RCC_MISCENR_MCO2EN
392 #define LL_XSPIPHYCOMP RCC_MISCENR_XSPIPHYCOMPEN
393 #define LL_XSPIPHY1 RCC_MISCRSTR_XSPIPHY1RST
394 #define LL_XSPIPHY2 RCC_MISCRSTR_XSPIPHY2RST
395 #define LL_PER RCC_MISCENR_PEREN
396 #define LL_SDMMC1DLL RCC_MISCRSTR_SDMMC1DLLRST
397 #define LL_SDMMC2DLL RCC_MISCRSTR_SDMMC2DLLRST
398 /**
399 * @}
400 */
401
402 /**
403 * @}
404 */
405
406 /* Exported macros -----------------------------------------------------------*/
407
408 /* Exported functions --------------------------------------------------------*/
409
410 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
411 * @{
412 */
413
414 /** @defgroup BUS_LL_EF_BUS BUS
415 * @{
416 */
417
418 /**
419 * @brief Enable AXI bus clock.
420 * @rmtoll BUSENSR ACLKNENS LL_BUS_EnableClock\n
421 * BUSENSR ACLKNCENS LL_BUS_EnableClock\n
422 * BUSENSR AHBMENS LL_BUS_EnableClock\n
423 * BUSENSR AHB1ENS LL_BUS_EnableClock\n
424 * BUSENSR AHB2ENS LL_BUS_EnableClock\n
425 * BUSENSR AHB3ENS LL_BUS_EnableClock\n
426 * BUSENSR AHB4ENS LL_BUS_EnableClock\n
427 * BUSENSR AHB5ENS LL_BUS_EnableClock\n
428 * BUSENSR APB1ENS LL_BUS_EnableClock\n
429 * BUSENSR APB2ENS LL_BUS_EnableClock\n
430 * BUSENSR APB3ENS LL_BUS_EnableClock\n
431 * BUSENSR APB4ENS LL_BUS_EnableClock\n
432 * BUSENSR APB5ENS LL_BUS_EnableClock
433 * @param Bus This parameter can be a combination of the following values:
434 * @arg @ref LL_ACLKN
435 * @arg @ref LL_ACLKNC
436 * @arg @ref LL_AHBM
437 * @arg @ref LL_AHB1
438 * @arg @ref LL_AHB2
439 * @arg @ref LL_AHB3
440 * @arg @ref LL_AHB4
441 * @arg @ref LL_AHB5
442 * @arg @ref LL_APB1
443 * @arg @ref LL_APB2
444 * @arg @ref LL_APB3
445 * @arg @ref LL_APB4
446 * @arg @ref LL_APB5
447 * @retval None
448 */
LL_BUS_EnableClock(uint32_t Bus)449 __STATIC_INLINE void LL_BUS_EnableClock(uint32_t Bus)
450 {
451 __IO uint32_t tmpreg;
452 WRITE_REG(RCC->BUSENSR, Bus);
453 /* Delay after an RCC bus clock enabling */
454 tmpreg = READ_REG(RCC->BUSENR);
455 (void)tmpreg;
456 }
457
458 /**
459 * @brief Check if AXI bus clock is enabled or not
460 * @rmtoll BUSENR ACLKNEN LL_BUS_IsEnabledClock\n
461 * BUSENR ACLKNCEN LL_BUS_IsEnabledClock\n
462 * BUSENR AHBMEN LL_BUS_IsEnabledClock\n
463 * BUSENR AHB1EN LL_BUS_IsEnabledClock\n
464 * BUSENR AHB2EN LL_BUS_IsEnabledClock\n
465 * BUSENR AHB3EN LL_BUS_IsEnabledClock\n
466 * BUSENR AHB4EN LL_BUS_IsEnabledClock\n
467 * BUSENR AHB5EN LL_BUS_IsEnabledClock\n
468 * BUSENR APB1EN LL_BUS_IsEnabledClock\n
469 * BUSENR APB2EN LL_BUS_IsEnabledClock\n
470 * BUSENR APB3EN LL_BUS_IsEnabledClock\n
471 * BUSENR APB4EN LL_BUS_IsEnabledClock\n
472 * BUSENR APB5EN LL_BUS_IsEnabledClock
473 * @param Bus This parameter can be a combination of the following values:
474 * @arg @ref LL_ACLKN
475 * @arg @ref LL_ACLKNC
476 * @arg @ref LL_AHBM
477 * @arg @ref LL_AHB1
478 * @arg @ref LL_AHB2
479 * @arg @ref LL_AHB3
480 * @arg @ref LL_AHB4
481 * @arg @ref LL_AHB5
482 * @arg @ref LL_APB1
483 * @arg @ref LL_APB2
484 * @arg @ref LL_APB3
485 * @arg @ref LL_APB4
486 * @arg @ref LL_APB5
487 * @retval uint32_t
488 */
LL_BUS_IsEnabledClock(uint32_t Bus)489 __STATIC_INLINE uint32_t LL_BUS_IsEnabledClock(uint32_t Bus)
490 {
491 return ((READ_BIT(RCC->BUSENR, Bus) == Bus) ? 1UL : 0UL);
492 }
493
494 /**
495 * @brief Disable AXI bus clock.
496 * @rmtoll BUSENCR ACLKNENC LL_BUS_DisableClock\n
497 * BUSENCR ACLKNCENC LL_BUS_DisableClock\n
498 * BUSENCR AHBMENC LL_BUS_DisableClock\n
499 * BUSENCR AHB1ENC LL_BUS_DisableClock\n
500 * BUSENCR AHB2ENC LL_BUS_DisableClock\n
501 * BUSENCR AHB3ENC LL_BUS_DisableClock\n
502 * BUSENCR AHB4ENC LL_BUS_DisableClock\n
503 * BUSENCR AHB5ENC LL_BUS_DisableClock\n
504 * BUSENCR APB1ENC LL_BUS_DisableClock\n
505 * BUSENCR APB2ENC LL_BUS_DisableClock\n
506 * BUSENCR APB3ENC LL_BUS_DisableClock\n
507 * BUSENCR APB4ENC LL_BUS_DisableClock\n
508 * BUSENCR APB5ENC LL_BUS_DisableClock
509 * @param Bus This parameter can be a combination of the following values:
510 * @arg @ref LL_ACLKN
511 * @arg @ref LL_ACLKNC
512 * @arg @ref LL_AHBM
513 * @arg @ref LL_AHB1
514 * @arg @ref LL_AHB2
515 * @arg @ref LL_AHB3
516 * @arg @ref LL_AHB4
517 * @arg @ref LL_AHB5
518 * @arg @ref LL_APB1
519 * @arg @ref LL_APB2
520 * @arg @ref LL_APB3
521 * @arg @ref LL_APB4
522 * @arg @ref LL_APB5
523 * @retval None
524 */
LL_BUS_DisableClock(uint32_t Bus)525 __STATIC_INLINE void LL_BUS_DisableClock(uint32_t Bus)
526 {
527 WRITE_REG(RCC->BUSENCR, Bus);
528 }
529
530 /**
531 * @brief Enable AXI bus clock during Low Power mode.
532 * @rmtoll BUSLPENSR ACLKNLPENS LL_BUS_EnableClockLowPower\n
533 * BUSLPENSR ACLKNCLPENS LL_BUS_EnableClockLowPower\n
534 * BUSLPENSR AHBMLPENS LL_BUS_EnableClockLowPower\n
535 * BUSLPENSR AHB1LPENS LL_BUS_EnableClockLowPower\n
536 * BUSLPENSR AHB2LPENS LL_BUS_EnableClockLowPower\n
537 * BUSLPENSR AHB3LPENS LL_BUS_EnableClockLowPower\n
538 * BUSLPENSR AHB4LPENS LL_BUS_EnableClockLowPower\n
539 * BUSLPENSR AHB5LPENS LL_BUS_EnableClockLowPower\n
540 * BUSLPENSR APB1LPENS LL_BUS_EnableClockLowPower\n
541 * BUSLPENSR APB2LPENS LL_BUS_EnableClockLowPower\n
542 * BUSLPENSR APB3LPENS LL_BUS_EnableClockLowPower\n
543 * BUSLPENSR APB4LPENS LL_BUS_EnableClockLowPower\n
544 * BUSLPENSR APB5LPENS LL_BUS_EnableClockLowPower
545 * @param Bus This parameter can be a combination of the following values:
546 * @arg @ref LL_ACLKN
547 * @arg @ref LL_ACLKNC
548 * @arg @ref LL_AHBM
549 * @arg @ref LL_AHB1
550 * @arg @ref LL_AHB2
551 * @arg @ref LL_AHB3
552 * @arg @ref LL_AHB4
553 * @arg @ref LL_AHB5
554 * @arg @ref LL_APB1
555 * @arg @ref LL_APB2
556 * @arg @ref LL_APB3
557 * @arg @ref LL_APB4
558 * @arg @ref LL_APB5
559 * @retval None
560 */
LL_BUS_EnableClockLowPower(uint32_t Bus)561 __STATIC_INLINE void LL_BUS_EnableClockLowPower(uint32_t Bus)
562 {
563 __IO uint32_t tmpreg;
564 WRITE_REG(RCC->BUSLPENSR, Bus);
565 /* Delay after an RCC bus clock enabling */
566 tmpreg = READ_REG(RCC->BUSLPENR);
567 (void)tmpreg;
568 }
569
570 /**
571 * @brief Check if AXI bus clock during Low Power mode is enabled or not
572 * @rmtoll BUSLPENR ACLKNLPEN LL_BUS_IsEnabledClockLowPower\n
573 * BUSLPENR ACLKNCLPEN LL_BUS_IsEnabledClockLowPower\n
574 * BUSLPENR AHBMLPEN LL_BUS_IsEnabledClockLowPower\n
575 * BUSLPENR AHB1LPEN LL_BUS_IsEnabledClockLowPower\n
576 * BUSLPENR AHB2LPEN LL_BUS_IsEnabledClockLowPower\n
577 * BUSLPENR AHB3LPEN LL_BUS_IsEnabledClockLowPower\n
578 * BUSLPENR AHB4LPEN LL_BUS_IsEnabledClockLowPower\n
579 * BUSLPENR AHB5LPEN LL_BUS_IsEnabledClockLowPower\n
580 * BUSLPENR APB1LPEN LL_BUS_IsEnabledClockLowPower\n
581 * BUSLPENR APB2LPEN LL_BUS_IsEnabledClockLowPower\n
582 * BUSLPENR APB3LPEN LL_BUS_IsEnabledClockLowPower\n
583 * BUSLPENR APB4LPEN LL_BUS_IsEnabledClockLowPower\n
584 * BUSLPENR APB5LPEN LL_BUS_IsEnabledClockLowPower
585 * @param Bus This parameter can be a combination of the following values:
586 * @arg @ref LL_ACLKN
587 * @arg @ref LL_ACLKNC
588 * @arg @ref LL_AHBM
589 * @arg @ref LL_AHB1
590 * @arg @ref LL_AHB2
591 * @arg @ref LL_AHB3
592 * @arg @ref LL_AHB4
593 * @arg @ref LL_AHB5
594 * @arg @ref LL_APB1
595 * @arg @ref LL_APB2
596 * @arg @ref LL_APB3
597 * @arg @ref LL_APB4
598 * @arg @ref LL_APB5
599 * @retval uint32_t
600 */
LL_BUS_IsEnabledClockLowPower(uint32_t Bus)601 __STATIC_INLINE uint32_t LL_BUS_IsEnabledClockLowPower(uint32_t Bus)
602 {
603 return ((READ_BIT(RCC->BUSLPENR, Bus) == Bus) ? 1UL : 0UL);
604 }
605
606 /**
607 * @brief Disable AXI bus clock during Low Power mode.
608 * @rmtoll BUSLPENCR ACLKNLPENC LL_BUS_DisableClockLowPower\n
609 * BUSLPENCR ACLKNCLPENC LL_BUS_DisableClockLowPower\n
610 * BUSLPENCR AHBMLPENC LL_BUS_DisableClockLowPower\n
611 * BUSLPENCR AHB1LPENC LL_BUS_DisableClockLowPower\n
612 * BUSLPENCR AHB2LPENC LL_BUS_DisableClockLowPower\n
613 * BUSLPENCR AHB3LPENC LL_BUS_DisableClockLowPower\n
614 * BUSLPENCR AHB4LPENC LL_BUS_DisableClockLowPower\n
615 * BUSLPENCR AHB5LPENC LL_BUS_DisableClockLowPower\n
616 * BUSLPENCR APB1LPENC LL_BUS_DisableClockLowPower\n
617 * BUSLPENCR APB2LPENC LL_BUS_DisableClockLowPower\n
618 * BUSLPENCR APB3LPENC LL_BUS_DisableClockLowPower\n
619 * BUSLPENCR APB4LPENC LL_BUS_DisableClockLowPower\n
620 * BUSLPENCR APB5LPENC LL_BUS_DisableClockLowPower
621 * @param Bus This parameter can be a combination of the following values:
622 * @arg @ref LL_ACLKN
623 * @arg @ref LL_ACLKNC
624 * @arg @ref LL_AHBM
625 * @arg @ref LL_AHB1
626 * @arg @ref LL_AHB2
627 * @arg @ref LL_AHB3
628 * @arg @ref LL_AHB4
629 * @arg @ref LL_AHB5
630 * @arg @ref LL_APB1
631 * @arg @ref LL_APB2
632 * @arg @ref LL_APB3
633 * @arg @ref LL_APB4
634 * @arg @ref LL_APB5
635 * @retval None
636 */
LL_BUS_DisableClockLowPower(uint32_t Bus)637 __STATIC_INLINE void LL_BUS_DisableClockLowPower(uint32_t Bus)
638 {
639 WRITE_REG(RCC->BUSLPENCR, Bus);
640 }
641
642 /**
643 * @}
644 */
645
646 /** @defgroup BUS_LL_EF_MEM MEM
647 * @{
648 */
649
650 /**
651 * @brief Enable memories clock.
652 * @rmtoll MEMENSR AXISRAM1ENS LL_MEM_EnableClock\n
653 * MEMENSR AXISRAM2ENS LL_MEM_EnableClock\n
654 * MEMENSR AXISRAM3ENS LL_MEM_EnableClock\n
655 * MEMENSR AXISRAM4ENS LL_MEM_EnableClock\n
656 * MEMENSR AXISRAM5ENS LL_MEM_EnableClock\n
657 * MEMENSR AXISRAM6ENS LL_MEM_EnableClock\n
658 * MEMENSR AHBSRAM1ENS LL_MEM_EnableClock\n
659 * MEMENSR AHBSRAM2ENS LL_MEM_EnableClock\n
660 * MEMENSR BKPSRAMENS LL_MEM_EnableClock\n
661 * MEMENSR FLEXRAMENS LL_MEM_EnableClock\n
662 * MEMENSR CACHEAXIRAMENS LL_MEM_EnableClock\n
663 * MEMENSR VENCRAMENS LL_MEM_EnableClock
664 * @param Memories This parameter can be a combination of the following values:
665 * @arg @ref LL_MEM_AXISRAM1
666 * @arg @ref LL_MEM_AXISRAM2
667 * @arg @ref LL_MEM_AXISRAM3
668 * @arg @ref LL_MEM_AXISRAM4
669 * @arg @ref LL_MEM_AXISRAM5
670 * @arg @ref LL_MEM_AXISRAM6
671 * @arg @ref LL_MEM_AHBSRAM1
672 * @arg @ref LL_MEM_AHBSRAM2
673 * @arg @ref LL_MEM_BKPSRAM
674 * @arg @ref LL_MEM_FLEXRAM
675 * @arg @ref LL_MEM_CACHEAXIRAM
676 * @arg @ref LL_MEM_VENCRAM
677 * @retval None
678 */
LL_MEM_EnableClock(uint32_t Memories)679 __STATIC_INLINE void LL_MEM_EnableClock(uint32_t Memories)
680 {
681 __IO uint32_t tmpreg;
682 WRITE_REG(RCC->MEMENSR, Memories);
683 /* Delay after an RCC memories clock enabling */
684 tmpreg = READ_REG(RCC->MEMENR);
685 (void)tmpreg;
686 }
687
688 /**
689 * @brief Check if memory clock is enabled or not
690 * @rmtoll MEMENR AXISRAM1EN LL_MEM_IsEnabledClock\n
691 * MEMENR AXISRAM2EN LL_MEM_IsEnabledClock\n
692 * MEMENR AXISRAM3EN LL_MEM_IsEnabledClock\n
693 * MEMENR AXISRAM4EN LL_MEM_IsEnabledClock\n
694 * MEMENR AXISRAM5EN LL_MEM_IsEnabledClock\n
695 * MEMENR AXISRAM6EN LL_MEM_IsEnabledClock\n
696 * MEMENR AHBSRAM1EN LL_MEM_IsEnabledClock\n
697 * MEMENR AHBSRAM2EN LL_MEM_IsEnabledClock\n
698 * MEMENR BKPSRAMEN LL_MEM_IsEnabledClock\n
699 * MEMENR FLEXRAMEN LL_MEM_IsEnabledClock\n
700 * MEMENR CACHEAXIRAMEN LL_MEM_IsEnabledClock\n
701 * MEMENR VENCRAMEN LL_MEM_IsEnabledClock
702 * @param Memories This parameter can be a combination of the following values:
703 * @arg @ref LL_MEM_AXISRAM1
704 * @arg @ref LL_MEM_AXISRAM2
705 * @arg @ref LL_MEM_AXISRAM3
706 * @arg @ref LL_MEM_AXISRAM4
707 * @arg @ref LL_MEM_AXISRAM5
708 * @arg @ref LL_MEM_AXISRAM6
709 * @arg @ref LL_MEM_AHBSRAM1
710 * @arg @ref LL_MEM_AHBSRAM2
711 * @arg @ref LL_MEM_BKPSRAM
712 * @arg @ref LL_MEM_FLEXRAM
713 * @arg @ref LL_MEM_CACHEAXIRAM
714 * @arg @ref LL_MEM_VENCRAM
715 * @retval uint32_t
716 */
LL_MEM_IsEnabledClock(uint32_t Memories)717 __STATIC_INLINE uint32_t LL_MEM_IsEnabledClock(uint32_t Memories)
718 {
719 return ((READ_BIT(RCC->MEMENR, Memories) == Memories) ? 1UL : 0UL);
720 }
721
722 /**
723 * @brief Disable memories clock.
724 * @rmtoll MEMENCR AXISRAM1ENC LL_MEM_DisableClock\n
725 * MEMENCR AXISRAM2ENC LL_MEM_DisableClock\n
726 * MEMENCR AXISRAM3ENC LL_MEM_DisableClock\n
727 * MEMENCR AXISRAM4ENC LL_MEM_DisableClock\n
728 * MEMENCR AXISRAM5ENC LL_MEM_DisableClock\n
729 * MEMENCR AXISRAM6ENC LL_MEM_DisableClock\n
730 * MEMENCR AHBSRAM1ENC LL_MEM_DisableClock\n
731 * MEMENCR AHBSRAM2ENC LL_MEM_DisableClock\n
732 * MEMENCR BKPSRAMENC LL_MEM_DisableClock\n
733 * MEMENCR FLEXRAMENC LL_MEM_DisableClock\n
734 * MEMENCR CACHEAXIRAMENC LL_MEM_DisableClock\n
735 * MEMENCR VENCRAMENC LL_MEM_DisableClock
736 * @param Memories This parameter can be a combination of the following values:
737 * @arg @ref LL_MEM_AXISRAM1
738 * @arg @ref LL_MEM_AXISRAM2
739 * @arg @ref LL_MEM_AXISRAM3
740 * @arg @ref LL_MEM_AXISRAM4
741 * @arg @ref LL_MEM_AXISRAM5
742 * @arg @ref LL_MEM_AXISRAM6
743 * @arg @ref LL_MEM_AHBSRAM1
744 * @arg @ref LL_MEM_AHBSRAM2
745 * @arg @ref LL_MEM_BKPSRAM
746 * @arg @ref LL_MEM_FLEXRAM
747 * @arg @ref LL_MEM_CACHEAXIRAM
748 * @arg @ref LL_MEM_VENCRAM
749 * @retval None
750 */
LL_MEM_DisableClock(uint32_t Memories)751 __STATIC_INLINE void LL_MEM_DisableClock(uint32_t Memories)
752 {
753 WRITE_REG(RCC->MEMENCR, Memories);
754 }
755
756 /**
757 * @brief Enable memories clock during Low Power mode.
758 * @rmtoll MEMLPENSR AXISRAM1LPENS LL_MEM_EnableClockLowPower\n
759 * MEMLPENSR AXISRAM2LPENS LL_MEM_EnableClockLowPower\n
760 * MEMLPENSR AXISRAM3LPENS LL_MEM_EnableClockLowPower\n
761 * MEMLPENSR AXISRAM4LPENS LL_MEM_EnableClockLowPower\n
762 * MEMLPENSR AXISRAM5LPENS LL_MEM_EnableClockLowPower\n
763 * MEMLPENSR AXISRAM6LPENS LL_MEM_EnableClockLowPower\n
764 * MEMLPENSR AHBSRAM1LPENS LL_MEM_EnableClockLowPower\n
765 * MEMLPENSR AHBSRAM2LPENS LL_MEM_EnableClockLowPower\n
766 * MEMLPENSR BKPSRAMLPENS LL_MEM_EnableClockLowPower\n
767 * MEMLPENSR FLEXRAMLPENS LL_MEM_EnableClockLowPower\n
768 * MEMLPENSR CACHEAXIRAMLPENS LL_MEM_EnableClockLowPower\n
769 * MEMLPENSR VENCRAMLPENS LL_MEM_EnableClockLowPower
770 * @param Memories This parameter can be a combination of the following values:
771 * @arg @ref LL_MEM_AXISRAM1
772 * @arg @ref LL_MEM_AXISRAM2
773 * @arg @ref LL_MEM_AXISRAM3
774 * @arg @ref LL_MEM_AXISRAM4
775 * @arg @ref LL_MEM_AXISRAM5
776 * @arg @ref LL_MEM_AXISRAM6
777 * @arg @ref LL_MEM_AHBSRAM1
778 * @arg @ref LL_MEM_AHBSRAM2
779 * @arg @ref LL_MEM_BKPSRAM
780 * @arg @ref LL_MEM_FLEXRAM
781 * @arg @ref LL_MEM_CACHEAXIRAM
782 * @arg @ref LL_MEM_VENCRAM
783 * @retval None
784 */
LL_MEM_EnableClockLowPower(uint32_t Memories)785 __STATIC_INLINE void LL_MEM_EnableClockLowPower(uint32_t Memories)
786 {
787 __IO uint32_t tmpreg;
788 WRITE_REG(RCC->MEMLPENSR, Memories);
789 /* Delay after an RCC memories clock enabling */
790 tmpreg = READ_REG(RCC->MEMLPENR);
791 (void)tmpreg;
792 }
793
794 /**
795 * @brief Check if memories clock during Low Power mode is enabled or not .
796 * @rmtoll MEMLPENR AXISRAM1LPEN LL_MEM_IsEnabledClockLowPower\n
797 * MEMLPENR AXISRAM2LPEN LL_MEM_IsEnabledClockLowPower\n
798 * MEMLPENR AXISRAM3LPEN LL_MEM_IsEnabledClockLowPower\n
799 * MEMLPENR AXISRAM4LPEN LL_MEM_IsEnabledClockLowPower\n
800 * MEMLPENR AXISRAM5LPEN LL_MEM_IsEnabledClockLowPower\n
801 * MEMLPENR AXISRAM6LPEN LL_MEM_IsEnabledClockLowPower\n
802 * MEMLPENR AHBSRAM1LPEN LL_MEM_IsEnabledClockLowPower\n
803 * MEMLPENR AHBSRAM2LPEN LL_MEM_IsEnabledClockLowPower\n
804 * MEMLPENR BKPSRAMLPEN LL_MEM_IsEnabledClockLowPower\n
805 * MEMLPENR FLEXRAMLPEN LL_MEM_IsEnabledClockLowPower\n
806 * MEMLPENR CACHEAXIRAMLPEN LL_MEM_IsEnabledClockLowPower\n
807 * MEMLPENR VENCRAMLPEN LL_MEM_IsEnabledClockLowPower
808 * @param Memories This parameter can be a combination of the following values:
809 * @arg @ref LL_MEM_AXISRAM1
810 * @arg @ref LL_MEM_AXISRAM2
811 * @arg @ref LL_MEM_AXISRAM3
812 * @arg @ref LL_MEM_AXISRAM4
813 * @arg @ref LL_MEM_AXISRAM5
814 * @arg @ref LL_MEM_AXISRAM6
815 * @arg @ref LL_MEM_AHBSRAM1
816 * @arg @ref LL_MEM_AHBSRAM2
817 * @arg @ref LL_MEM_BKPSRAM
818 * @arg @ref LL_MEM_FLEXRAM
819 * @arg @ref LL_MEM_CACHEAXIRAM
820 * @arg @ref LL_MEM_VENCRAM
821 * @retval None
822 */
LL_MEM_IsEnabledClockLowPower(uint32_t Memories)823 __STATIC_INLINE uint32_t LL_MEM_IsEnabledClockLowPower(uint32_t Memories)
824 {
825 return ((READ_BIT(RCC->MEMLPENR, Memories) == Memories) ? 1UL : 0UL);
826 }
827
828 /**
829 * @brief Disable memories clock during Low Power mode.
830 * @rmtoll MEMLPENCR AXISRAM1LPENC LL_MEM_DisableClockLowPower\n
831 * MEMLPENCR AXISRAM2LPENC LL_MEM_DisableClockLowPower\n
832 * MEMLPENCR AXISRAM3LPENC LL_MEM_DisableClockLowPower\n
833 * MEMLPENCR AXISRAM4LPENC LL_MEM_DisableClockLowPower\n
834 * MEMLPENCR AXISRAM5LPENC LL_MEM_DisableClockLowPower\n
835 * MEMLPENCR AXISRAM6LPENC LL_MEM_DisableClockLowPower\n
836 * MEMLPENCR AHBSRAM1LPENC LL_MEM_DisableClockLowPower\n
837 * MEMLPENCR AHBSRAM2LPENC LL_MEM_DisableClockLowPower\n
838 * MEMLPENCR BKPSRAMLPENC LL_MEM_DisableClockLowPower\n
839 * MEMLPENCR FLEXRAMLPENC LL_MEM_DisableClockLowPower\n
840 * MEMLPENCR CACHEAXIRAMLPENC LL_MEM_DisableClockLowPower\n
841 * MEMLPENCR VENCRAMLPENC LL_MEM_DisableClockLowPower
842 * @param Memories This parameter can be a combination of the following values:
843 * @arg @ref LL_MEM_AXISRAM1
844 * @arg @ref LL_MEM_AXISRAM2
845 * @arg @ref LL_MEM_AXISRAM3
846 * @arg @ref LL_MEM_AXISRAM4
847 * @arg @ref LL_MEM_AXISRAM5
848 * @arg @ref LL_MEM_AXISRAM6
849 * @arg @ref LL_MEM_AHBSRAM1
850 * @arg @ref LL_MEM_AHBSRAM2
851 * @arg @ref LL_MEM_BKPSRAM
852 * @arg @ref LL_MEM_FLEXRAM
853 * @arg @ref LL_MEM_CACHEAXIRAM
854 * @arg @ref LL_MEM_VENCRAM
855 * @retval None
856 */
LL_MEM_DisableClockLowPower(uint32_t Memories)857 __STATIC_INLINE void LL_MEM_DisableClockLowPower(uint32_t Memories)
858 {
859 WRITE_REG(RCC->MEMLPENCR, Memories);
860 }
861
862 /**
863 * @}
864 */
865
866 /** @defgroup BUS_LL_EF_AHB1 AHB1
867 * @{
868 */
869
870 /**
871 * @brief Enable AHB1 peripherals clock.
872 * @rmtoll AHB1ENSR GPDMA1ENS LL_AHB1_GRP1_EnableClock\n
873 * AHB1ENSR ADC12ENS LL_AHB1_GRP1_EnableClock
874 * @param Periphs This parameter can be a combination of the following values:
875 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
876 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
877 * @retval None
878 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)879 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
880 {
881 __IO uint32_t tmpreg;
882 WRITE_REG(RCC->AHB1ENSR, Periphs);
883 /* Delay after an RCC peripheral clock enabling */
884 tmpreg = READ_REG(RCC->AHB1ENR);
885 (void)tmpreg;
886 }
887
888 /**
889 * @brief Check if AHB1 peripheral clock is enabled or not
890 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n
891 * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock
892 * @param Periphs This parameter can be a combination of the following values:
893 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
894 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
895 * @retval uint32_t
896 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)897 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
898 {
899 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
900 }
901
902 /**
903 * @brief Disable AHB1 peripherals clock.
904 * @rmtoll AHB1ENCR GPDMA1ENC LL_AHB1_GRP1_DisableClock\n
905 * AHB1ENCR ADC12ENC LL_AHB1_GRP1_DisableClock
906 * @param Periphs This parameter can be a combination of the following values:
907 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
908 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
909 * @retval None
910 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)911 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
912 {
913 WRITE_REG(RCC->AHB1ENCR, Periphs);
914 }
915
916 /**
917 * @brief Force AHB1 peripherals reset.
918 * @rmtoll AHB1RSTSR GPDMA1RSTS LL_AHB1_GRP1_ForceReset\n
919 * AHB1RSTSR ADC12RSTS LL_AHB1_GRP1_ForceReset
920 * @param Periphs This parameter can be a combination of the following values:
921 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
922 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
923 * @retval None
924 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)925 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
926 {
927 WRITE_REG(RCC->AHB1RSTSR, Periphs);
928 }
929
930 /**
931 * @brief Release AHB1 peripherals reset.
932 * @rmtoll AHB1RSTCR GPDMA1RSTC LL_AHB1_GRP1_ReleaseReset\n
933 * AHB1RSTCR ADC12RSTC LL_AHB1_GRP1_ReleaseReset
934 * @param Periphs This parameter can be a combination of the following values:
935 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
936 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
937 * @retval None
938 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)939 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
940 {
941 WRITE_REG(RCC->AHB1RSTCR, Periphs);
942 }
943
944 /**
945 * @brief Enable AHB1 peripherals clock during Low Power mode.
946 * @rmtoll AHB1LPENSR GPDMA1LPENS LL_AHB1_GRP1_EnableClockLowPower\n
947 * AHB1LPENSR ADC12LPENS LL_AHB1_GRP1_EnableClockLowPower
948 * @param Periphs This parameter can be a combination of the following values:
949 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
950 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
951 * @retval None
952 */
LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)953 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
954 {
955 __IO uint32_t tmpreg;
956 WRITE_REG(RCC->AHB1LPENSR, Periphs);
957 /* Delay after an RCC peripheral clock enabling */
958 tmpreg = READ_REG(RCC->AHB1LPENR);
959 (void)tmpreg;
960 }
961
962 /**
963 * @brief Check if AHB1 peripheral clock during Low Power mode is enabled or not .
964 * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_IsEnabledClockLowPower\n
965 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_IsEnabledClockLowPower
966 * @param Periphs This parameter can be a combination of the following values:
967 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
968 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
969 * @retval uint32_t
970 */
LL_AHB1_GRP1_IsEnabledClockLowPower(uint32_t Periphs)971 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
972 {
973 return ((READ_BIT(RCC->AHB1LPENR, Periphs) == Periphs) ? 1UL : 0UL);
974 }
975
976 /**
977 * @brief Disable AHB1 peripherals clock during Low Power mode.
978 * @rmtoll AHB1LPENCR GPDMA1LPENC LL_AHB1_GRP1_DisableClockLowPower\n
979 * AHB1LPENCR ADC12LPENC LL_AHB1_GRP1_DisableClockLowPower
980 * @param Periphs This parameter can be a combination of the following values:
981 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
982 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
983 * @retval None
984 */
LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)985 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
986 {
987 WRITE_REG(RCC->AHB1LPENCR, Periphs);
988 }
989
990 /**
991 * @}
992 */
993
994 /** @defgroup BUS_LL_EF_AHB2 AHB2
995 * @{
996 */
997
998 /**
999 * @brief Enable AHB2 peripherals clock.
1000 * @rmtoll AHB2ENSR RAMCFGENS LL_AHB2_GRP1_EnableClock\n
1001 * AHB2ENSR MDF1ENS LL_AHB2_GRP1_EnableClock\n
1002 * AHB2ENSR ADF1ENS LL_AHB2_GRP1_EnableClock
1003 * @param Periphs This parameter can be a combination of the following values:
1004 * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
1005 * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
1006 * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
1007 * @retval None
1008 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)1009 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
1010 {
1011 __IO uint32_t tmpreg;
1012 WRITE_REG(RCC->AHB2ENSR, Periphs);
1013 /* Delay after an RCC peripheral clock enabling */
1014 tmpreg = READ_REG(RCC->AHB2ENR);
1015 (void)tmpreg;
1016 }
1017
1018 /**
1019 * @brief Check if AHB2 peripheral clock is enabled or not
1020 * @rmtoll AHB2ENR RAMCFGEN LL_AHB2_GRP1_IsEnabledClock\n
1021 * AHB2ENR MDF1EN LL_AHB2_GRP1_IsEnabledClock\n
1022 * AHB2ENR ADF1EN LL_AHB2_GRP1_IsEnabledClock
1023 * @param Periphs This parameter can be a combination of the following values:
1024 * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
1025 * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
1026 * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
1027 * @retval uint32_t
1028 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)1029 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
1030 {
1031 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
1032 }
1033
1034 /**
1035 * @brief Disable AHB2 peripherals clock.
1036 * @rmtoll AHB2ENCR RAMCFGENC LL_AHB2_GRP1_DisableClock\n
1037 * AHB2ENCR MDF1ENC LL_AHB2_GRP1_DisableClock\n
1038 * AHB2ENCR ADF1ENC LL_AHB2_GRP1_DisableClock
1039 * @param Periphs This parameter can be a combination of the following values:
1040 * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
1041 * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
1042 * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
1043 * @retval None
1044 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)1045 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
1046 {
1047 WRITE_REG(RCC->AHB2ENCR, Periphs);
1048 }
1049
1050 /**
1051 * @brief Force AHB2 peripherals reset.
1052 * @rmtoll AHB2RSTSR RAMCFGRSTS LL_AHB2_GRP1_ForceReset\n
1053 * AHB2RSTSR MDF1RSTS LL_AHB2_GRP1_ForceReset\n
1054 * AHB2RSTSR ADF1RSTS LL_AHB2_GRP1_ForceReset
1055 * @param Periphs This parameter can be a combination of the following values:
1056 * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
1057 * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
1058 * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
1059 * @retval None
1060 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)1061 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
1062 {
1063 WRITE_REG(RCC->AHB2RSTSR, Periphs);
1064 }
1065
1066 /**
1067 * @brief Release AHB2 peripherals reset.
1068 * @rmtoll AHB2RSTCR RAMCFGRSTC LL_AHB2_GRP1_ReleaseReset\n
1069 * AHB2RSTCR MDF1RSTC LL_AHB2_GRP1_ReleaseReset\n
1070 * AHB2RSTCR ADF1RSTC LL_AHB2_GRP1_ReleaseReset
1071 * @param Periphs This parameter can be a combination of the following values:
1072 * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
1073 * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
1074 * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
1075 * @retval None
1076 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)1077 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
1078 {
1079 WRITE_REG(RCC->AHB2RSTCR, Periphs);
1080 }
1081
1082 /**
1083 * @brief Enable AHB2 peripherals clock during Low Power mode.
1084 * @rmtoll AHB2LPENSR RAMCFGLPENC LL_AHB2_GRP1_EnableClockLowPower\n
1085 * AHB2LPENSR MDF1LPENC LL_AHB2_GRP1_EnableClockLowPower\n
1086 * AHB2LPENSR ADF1LPENC LL_AHB2_GRP1_EnableClockLowPower
1087 * @param Periphs This parameter can be a combination of the following values:
1088 * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
1089 * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
1090 * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
1091 * @retval None
1092 */
LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)1093 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
1094 {
1095 __IO uint32_t tmpreg;
1096 WRITE_REG(RCC->AHB2LPENSR, Periphs);
1097 /* Delay after an RCC peripheral clock enabling */
1098 tmpreg = READ_REG(RCC->AHB2LPENR);
1099 (void)tmpreg;
1100 }
1101
1102 /**
1103 * @brief Check if AHB2 peripheral clock during Low Power mode is enabled or not .
1104 * @rmtoll AHB2LPENR RAMCFGLPEN LL_AHB2_GRP1_IsEnabledClockLowPower\n
1105 * AHB2LPENR MDF1LPEN LL_AHB2_GRP1_IsEnabledClockLowPower\n
1106 * AHB2LPENR ADF1LPEN LL_AHB2_GRP1_IsEnabledClockLowPower
1107 * @param Periphs This parameter can be a combination of the following values:
1108 * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
1109 * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
1110 * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
1111 * @retval uint32_t
1112 */
LL_AHB2_GRP1_IsEnabledClockLowPower(uint32_t Periphs)1113 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
1114 {
1115 return ((READ_BIT(RCC->AHB2LPENR, Periphs) == Periphs) ? 1UL : 0UL);
1116 }
1117
1118 /**
1119 * @brief Disable AHB2 peripherals clock during Low Power mode.
1120 * @rmtoll AHB2LPENCR RAMCFGLPENC LL_AHB2_GRP1_DisableClockLowPower\n
1121 * AHB2LPENCR MDF1LPENC LL_AHB2_GRP1_DisableClockLowPower\n
1122 * AHB2LPENCR ADF1LPENC LL_AHB2_GRP1_DisableClockLowPower
1123 * @param Periphs This parameter can be a combination of the following values:
1124 * @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
1125 * @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
1126 * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
1127 * @retval None
1128 */
LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)1129 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
1130 {
1131 WRITE_REG(RCC->AHB2LPENCR, Periphs);
1132 }
1133
1134 /**
1135 * @}
1136 */
1137
1138 /** @defgroup BUS_LL_EF_AHB3 AHB3
1139 * @{
1140 */
1141
1142 /**
1143 * @brief Enable AHB3 peripherals clock.
1144 * @rmtoll AHB3ENSR RNGENS LL_AHB3_GRP1_EnableClock\n
1145 * AHB3ENSR HASHENS LL_AHB3_GRP1_EnableClock\n
1146 * AHB3ENSR CRYPENS LL_AHB3_GRP1_EnableClock\n (*)
1147 * AHB3ENSR SAESENS LL_AHB3_GRP1_EnableClock\n (*)
1148 * AHB3ENSR PKAENS LL_AHB3_GRP1_EnableClock\n
1149 * AHB3ENSR RIFSCENS LL_AHB3_GRP1_EnableClock\n
1150 * AHB3ENSR RISAFENS LL_AHB3_GRP1_EnableClock\n
1151 * AHB3ENSR IACENS LL_AHB3_GRP1_EnableClock
1152 * @param Periphs This parameter can be a combination of the following values:
1153 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
1154 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
1155 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
1156 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
1157 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
1158 * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
1159 * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
1160 * @arg @ref LL_AHB3_GRP1_PERIPH_IAC
1161 *
1162 * (*) value not defined in all devices.
1163 * @retval None
1164 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)1165 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
1166 {
1167 __IO uint32_t tmpreg;
1168 WRITE_REG(RCC->AHB3ENSR, Periphs);
1169 /* Delay after an RCC peripheral clock enabling */
1170 tmpreg = READ_REG(RCC->AHB3ENR);
1171 (void)tmpreg;
1172 }
1173
1174 /**
1175 * @brief Check if AHB3 peripheral clock is enabled or not
1176 * @rmtoll AHB3ENR RNGEN LL_AHB3_GRP1_IsEnabledClock\n
1177 * AHB3ENR HASHEN LL_AHB3_GRP1_IsEnabledClock\n
1178 * AHB3ENR CRYPEN LL_AHB3_GRP1_IsEnabledClock\n (*)
1179 * AHB3ENR SAESEN LL_AHB3_GRP1_IsEnabledClock\n (*)
1180 * AHB3ENR PKAEN LL_AHB3_GRP1_IsEnabledClock\n
1181 * AHB3ENR RIFSCEN LL_AHB3_GRP1_IsEnabledClock\n
1182 * AHB3ENR RISAFEN LL_AHB3_GRP1_IsEnabledClock\n
1183 * AHB3ENR IACEN LL_AHB3_GRP1_IsEnabledClock
1184 * @param Periphs This parameter can be a combination of the following values:
1185 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
1186 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
1187 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
1188 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
1189 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
1190 * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
1191 * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
1192 * @arg @ref LL_AHB3_GRP1_PERIPH_IAC
1193 *
1194 * (*) value not defined in all devices.
1195 * @retval uint32_t
1196 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)1197 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
1198 {
1199 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
1200 }
1201
1202 /**
1203 * @brief Disable AHB3 peripherals clock.
1204 * @rmtoll AHB3ENCR RNGENC LL_AHB3_GRP1_DisableClock\n
1205 * AHB3ENCR HASHENC LL_AHB3_GRP1_DisableClock\n
1206 * AHB3ENCR CRYPENC LL_AHB3_GRP1_DisableClock\n (*)
1207 * AHB3ENCR SAESENC LL_AHB3_GRP1_DisableClock\n (*)
1208 * AHB3ENCR PKAENC LL_AHB3_GRP1_DisableClock\n
1209 * AHB3ENCR RIFSCENC LL_AHB3_GRP1_DisableClock\n
1210 * AHB3ENCR RISAFENC LL_AHB3_GRP1_DisableClock\n
1211 * AHB3ENCR IACENC LL_AHB3_GRP1_DisableClock
1212 * @param Periphs This parameter can be a combination of the following values:
1213 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
1214 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
1215 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
1216 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
1217 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
1218 * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
1219 * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
1220 * @arg @ref LL_AHB3_GRP1_PERIPH_IAC
1221 *
1222 * (*) value not defined in all devices.
1223 * @retval None
1224 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)1225 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
1226 {
1227 WRITE_REG(RCC->AHB3ENCR, Periphs);
1228 }
1229
1230 /**
1231 * @brief Force AHB3 peripherals reset.
1232 * @rmtoll AHB3RSTSR RNGRSTS LL_AHB3_GRP1_ForceReset\n
1233 * AHB3RSTSR HASHRSTS LL_AHB3_GRP1_ForceReset\n
1234 * AHB3RSTSR CRYPRSTS LL_AHB3_GRP1_ForceReset\n (*)
1235 * AHB3RSTSR SAESRSTS LL_AHB3_GRP1_ForceReset\n (*)
1236 * AHB3RSTSR PKARSTS LL_AHB3_GRP1_ForceReset\n
1237 * AHB3RSTSR IACRSTS LL_AHB3_GRP1_ForceReset
1238 * @param Periphs This parameter can be a combination of the following values:
1239 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
1240 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
1241 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
1242 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
1243 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
1244 * @arg @ref LL_AHB3_GRP1_PERIPH_IAC
1245 *
1246 * (*) value not defined in all devices.
1247 * @retval None
1248 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)1249 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
1250 {
1251 WRITE_REG(RCC->AHB3RSTSR, Periphs);
1252 }
1253
1254 /**
1255 * @brief Release AHB3 peripherals reset.
1256 * @rmtoll AHB3RSTCR RNGRSTC LL_AHB3_GRP1_ReleaseReset\n
1257 * AHB3RSTCR HASHRSTC LL_AHB3_GRP1_ReleaseReset\n
1258 * AHB3RSTCR CRYPRSTC LL_AHB3_GRP1_ReleaseReset\n (*)
1259 * AHB3RSTCR SAESRSTC LL_AHB3_GRP1_ReleaseReset\n (*)
1260 * AHB3RSTCR PKARSTC LL_AHB3_GRP1_ReleaseReset\n
1261 * AHB3RSTCR IACRSTC LL_AHB3_GRP1_ReleaseReset
1262 * @param Periphs This parameter can be a combination of the following values:
1263 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
1264 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
1265 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
1266 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
1267 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
1268 * @arg @ref LL_AHB3_GRP1_PERIPH_IAC
1269 *
1270 * (*) value not defined in all devices.
1271 * @retval None
1272 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)1273 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
1274 {
1275 WRITE_REG(RCC->AHB3RSTCR, Periphs);
1276 }
1277
1278 /**
1279 * @brief Enable AHB3 peripherals clock during Low Power mode.
1280 * @rmtoll AHB3LPENSR RNGLPENS LL_AHB3_GRP1_EnableClockLowPower\n
1281 * AHB3LPENSR HASHLPENS LL_AHB3_GRP1_EnableClockLowPower\n
1282 * AHB3LPENSR CRYPLPENS LL_AHB3_GRP1_EnableClockLowPower\n (*)
1283 * AHB3LPENSR SAESLPENS LL_AHB3_GRP1_EnableClockLowPower\n (*)
1284 * AHB3LPENSR PKALPENS LL_AHB3_GRP1_EnableClockLowPower\n
1285 * AHB3LPENSR RIFSCLPENS LL_AHB3_GRP1_EnableClockLowPower\n
1286 * AHB3LPENSR RISAFLPENS LL_AHB3_GRP1_EnableClockLowPower\n
1287 * AHB3LPENSR IACLPENS LL_AHB3_GRP1_EnableClockLowPower
1288 * @param Periphs This parameter can be a combination of the following values:
1289 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
1290 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
1291 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
1292 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
1293 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
1294 * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
1295 * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
1296 * @arg @ref LL_AHB3_GRP1_PERIPH_IAC
1297 *
1298 * (*) value not defined in all devices.
1299 * @retval None
1300 */
LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)1301 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
1302 {
1303 __IO uint32_t tmpreg;
1304 WRITE_REG(RCC->AHB3LPENSR, Periphs);
1305 /* Delay after an RCC peripheral clock enabling */
1306 tmpreg = READ_REG(RCC->AHB3LPENR);
1307 (void)tmpreg;
1308 }
1309
1310 /**
1311 * @brief Check if AHB3 peripheral clock during Low Power mode is enabled or not .
1312 * @rmtoll AHB3LPENR RNGLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n
1313 * AHB3LPENR HASHLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n
1314 * AHB3LPENR CRYPLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n (*)
1315 * AHB3LPENR SAESLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n (*)
1316 * AHB3LPENR PKALPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n
1317 * AHB3LPENR RIFSCLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n
1318 * AHB3LPENR RISAFLPEN LL_AHB3_GRP1_IsEnabledClockLowPower\n
1319 * AHB3LPENR IACLPEN LL_AHB3_GRP1_IsEnabledClockLowPower
1320 * @param Periphs This parameter can be a combination of the following values:
1321 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
1322 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
1323 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
1324 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
1325 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
1326 * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
1327 * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
1328 * @arg @ref LL_AHB3_GRP1_PERIPH_IAC
1329 *
1330 * (*) value not defined in all devices.
1331 * @retval uint32_t
1332 */
LL_AHB3_GRP1_IsEnabledClockLowPower(uint32_t Periphs)1333 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
1334 {
1335 return ((READ_BIT(RCC->AHB3LPENR, Periphs) == Periphs) ? 1UL : 0UL);
1336 }
1337
1338 /**
1339 * @brief Disable AHB3 peripherals clock during Low Power mode.
1340 * @rmtoll AHB3LPENCR RNGLPENC LL_AHB3_GRP1_DisableClockLowPower\n
1341 * AHB3LPENCR HASHLPENC LL_AHB3_GRP1_DisableClockLowPower\n
1342 * AHB3LPENCR CRYPLPENC LL_AHB3_GRP1_DisableClockLowPower\n (*)
1343 * AHB3LPENCR SAESLPENC LL_AHB3_GRP1_DisableClockLowPower\n (*)
1344 * AHB3LPENCR PKALPENC LL_AHB3_GRP1_DisableClockLowPower\n
1345 * AHB3LPENCR RIFSCLPENC LL_AHB3_GRP1_DisableClockLowPower\n
1346 * AHB3LPENCR RISAFLPENC LL_AHB3_GRP1_DisableClockLowPower\n
1347 * AHB3LPENCR IACLPENC LL_AHB3_GRP1_DisableClockLowPower
1348 * @param Periphs This parameter can be a combination of the following values:
1349 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
1350 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
1351 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
1352 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
1353 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
1354 * @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
1355 * @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
1356 * @arg @ref LL_AHB3_GRP1_PERIPH_IAC
1357 *
1358 * (*) value not defined in all devices.
1359 * @retval None
1360 */
LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)1361 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
1362 {
1363 WRITE_REG(RCC->AHB3LPENCR, Periphs);
1364 }
1365
1366 /**
1367 * @}
1368 */
1369
1370 /** @defgroup BUS_LL_EF_AHB4 AHB4
1371 * @{
1372 */
1373
1374 /**
1375 * @brief Enable AHB4 peripherals clock.
1376 * @rmtoll AHB4ENSR GPIOAENS LL_AHB4_GRP1_EnableClock\n
1377 * AHB4ENSR GPIOBENS LL_AHB4_GRP1_EnableClock\n
1378 * AHB4ENSR GPIOCENS LL_AHB4_GRP1_EnableClock\n
1379 * AHB4ENSR GPIODENS LL_AHB4_GRP1_EnableClock\n
1380 * AHB4ENSR GPIOEENS LL_AHB4_GRP1_EnableClock\n
1381 * AHB4ENSR GPIOFENS LL_AHB4_GRP1_EnableClock\n
1382 * AHB4ENSR GPIOGENS LL_AHB4_GRP1_EnableClock\n
1383 * AHB4ENSR GPIOHENS LL_AHB4_GRP1_EnableClock\n
1384 * AHB4ENSR GPIONENS LL_AHB4_GRP1_EnableClock\n
1385 * AHB4ENSR GPIOOENS LL_AHB4_GRP1_EnableClock\n
1386 * AHB4ENSR GPIOPENS LL_AHB4_GRP1_EnableClock\n
1387 * AHB4ENSR GPIOQENS LL_AHB4_GRP1_EnableClock\n
1388 * AHB4ENSR PWRENS LL_AHB4_GRP1_EnableClock\n
1389 * AHB4ENSR CRCENS LL_AHB4_GRP1_EnableClock
1390 * @param Periphs This parameter can be a combination of the following values:
1391 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1392 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1393 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1394 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1395 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1396 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1397 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1398 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1399 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
1400 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
1401 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
1402 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
1403 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
1404 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
1405 * @retval None
1406 */
LL_AHB4_GRP1_EnableClock(uint32_t Periphs)1407 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
1408 {
1409 __IO uint32_t tmpreg;
1410 WRITE_REG(RCC->AHB4ENSR, Periphs);
1411 /* Delay after an RCC peripheral clock enabling */
1412 tmpreg = READ_REG(RCC->AHB4ENR);
1413 (void)tmpreg;
1414 }
1415
1416 /**
1417 * @brief Check if AHB4 peripheral clock is enabled or not
1418 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n
1419 * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n
1420 * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n
1421 * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n
1422 * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n
1423 * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n
1424 * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n
1425 * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n
1426 * AHB4ENR GPIONEN LL_AHB4_GRP1_IsEnabledClock\n
1427 * AHB4ENR GPIOOEN LL_AHB4_GRP1_IsEnabledClock\n
1428 * AHB4ENR GPIOPEN LL_AHB4_GRP1_IsEnabledClock\n
1429 * AHB4ENR GPIOQEN LL_AHB4_GRP1_IsEnabledClock\n
1430 * AHB4ENR PWREN LL_AHB4_GRP1_IsEnabledClock\n
1431 * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock
1432 * @param Periphs This parameter can be a combination of the following values:
1433 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1434 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1435 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1436 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1437 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1438 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1439 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1440 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1441 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
1442 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
1443 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
1444 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
1445 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
1446 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
1447 * @retval uint32_t
1448 */
LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)1449 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
1450 {
1451 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1UL : 0UL);
1452 }
1453
1454 /**
1455 * @brief Disable AHB4 peripherals clock.
1456 * @rmtoll AHB4ENCR GPIOAENC LL_AHB4_GRP1_DisableClock\n
1457 * AHB4ENCR GPIOBENC LL_AHB4_GRP1_DisableClock\n
1458 * AHB4ENCR GPIOCENC LL_AHB4_GRP1_DisableClock\n
1459 * AHB4ENCR GPIODENC LL_AHB4_GRP1_DisableClock\n
1460 * AHB4ENCR GPIOEENC LL_AHB4_GRP1_DisableClock\n
1461 * AHB4ENCR GPIOFENC LL_AHB4_GRP1_DisableClock\n
1462 * AHB4ENCR GPIOGENC LL_AHB4_GRP1_DisableClock\n
1463 * AHB4ENCR GPIOHENC LL_AHB4_GRP1_DisableClock\n
1464 * AHB4ENCR GPIONENC LL_AHB4_GRP1_DisableClock\n
1465 * AHB4ENCR GPIOOENC LL_AHB4_GRP1_DisableClock\n
1466 * AHB4ENCR GPIOPENC LL_AHB4_GRP1_DisableClock\n
1467 * AHB4ENCR GPIOQENC LL_AHB4_GRP1_DisableClock\n
1468 * AHB4ENCR PWRENC LL_AHB4_GRP1_DisableClock\n
1469 * AHB4ENCR CRCENC LL_AHB4_GRP1_DisableClock
1470 * @param Periphs This parameter can be a combination of the following values:
1471 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1472 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1473 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1474 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1475 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1476 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1477 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1478 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1479 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
1480 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
1481 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
1482 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
1483 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
1484 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
1485 * @retval None
1486 */
LL_AHB4_GRP1_DisableClock(uint32_t Periphs)1487 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
1488 {
1489 WRITE_REG(RCC->AHB4ENCR, Periphs);
1490 }
1491
1492 /**
1493 * @brief Force AHB4 peripherals reset.
1494 * @rmtoll AHB4RSTSR GPIOARSTS LL_AHB4_GRP1_ForceReset\n
1495 * AHB4RSTSR GPIOBRSTS LL_AHB4_GRP1_ForceReset\n
1496 * AHB4RSTSR GPIOCRSTS LL_AHB4_GRP1_ForceReset\n
1497 * AHB4RSTSR GPIODRSTS LL_AHB4_GRP1_ForceReset\n
1498 * AHB4RSTSR GPIOERSTS LL_AHB4_GRP1_ForceReset\n
1499 * AHB4RSTSR GPIOFRSTS LL_AHB4_GRP1_ForceReset\n
1500 * AHB4RSTSR GPIOGRSTS LL_AHB4_GRP1_ForceReset\n
1501 * AHB4RSTSR GPIOHRSTS LL_AHB4_GRP1_ForceReset\n
1502 * AHB4RSTSR GPIONRSTS LL_AHB4_GRP1_ForceReset\n
1503 * AHB4RSTSR GPIOORSTS LL_AHB4_GRP1_ForceReset\n
1504 * AHB4RSTSR GPIOPRSTS LL_AHB4_GRP1_ForceReset\n
1505 * AHB4RSTSR GPIOQRSTS LL_AHB4_GRP1_ForceReset\n
1506 * AHB4RSTSR CRCRSTS LL_AHB4_GRP1_ForceReset\n
1507 * AHB4RSTSR BKPRAMRSTS LL_AHB4_GRP1_ForceReset
1508 * @param Periphs This parameter can be a combination of the following values:
1509 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1510 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1511 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1512 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1513 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1514 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1515 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1516 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1517 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
1518 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
1519 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
1520 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
1521 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
1522 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
1523 * @retval None
1524 */
LL_AHB4_GRP1_ForceReset(uint32_t Periphs)1525 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
1526 {
1527 WRITE_REG(RCC->AHB4RSTSR, Periphs);
1528 }
1529
1530 /**
1531 * @brief Release AHB4 peripherals reset.
1532 * @rmtoll AHB4RSTCR GPIOARSTC LL_AHB4_GRP1_ReleaseReset\n
1533 * AHB4RSTCR GPIOBRSTC LL_AHB4_GRP1_ReleaseReset\n
1534 * AHB4RSTCR GPIOCRSTC LL_AHB4_GRP1_ReleaseReset\n
1535 * AHB4RSTCR GPIODRSTC LL_AHB4_GRP1_ReleaseReset\n
1536 * AHB4RSTCR GPIOERSTC LL_AHB4_GRP1_ReleaseReset\n
1537 * AHB4RSTCR GPIOFRSTC LL_AHB4_GRP1_ReleaseReset\n
1538 * AHB4RSTCR GPIOGRSTC LL_AHB4_GRP1_ReleaseReset\n
1539 * AHB4RSTCR GPIOHRSTC LL_AHB4_GRP1_ReleaseReset\n
1540 * AHB4RSTCR GPIONRSTC LL_AHB4_GRP1_ReleaseReset\n
1541 * AHB4RSTCR GPIOORSTC LL_AHB4_GRP1_ReleaseReset\n
1542 * AHB4RSTCR GPIOPRSTC LL_AHB4_GRP1_ReleaseReset\n
1543 * AHB4RSTCR GPIOQRSTC LL_AHB4_GRP1_ReleaseReset\n
1544 * AHB4RSTCR CRCRSTC LL_AHB4_GRP1_ReleaseReset\n
1545 * AHB4RSTCR BKPRAMRSTC LL_AHB4_GRP1_ReleaseReset
1546 * @param Periphs This parameter can be a combination of the following values:
1547 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1548 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1549 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1550 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1551 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1552 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1553 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1554 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1555 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
1556 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
1557 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
1558 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
1559 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
1560 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
1561 * @retval None
1562 */
LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)1563 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
1564 {
1565 WRITE_REG(RCC->AHB4RSTCR, Periphs);
1566 }
1567
1568 /**
1569 * @brief Enable AHB4 peripherals clock during Low Power mode.
1570 * @rmtoll AHB4LPENSR GPIOALPENS LL_AHB4_GRP1_EnableClockLowPower\n
1571 * AHB4LPENSR GPIOBLPENS LL_AHB4_GRP1_EnableClockLowPower\n
1572 * AHB4LPENSR GPIOCLPENS LL_AHB4_GRP1_EnableClockLowPower\n
1573 * AHB4LPENSR GPIODLPENS LL_AHB4_GRP1_EnableClockLowPower\n
1574 * AHB4LPENSR GPIOELPENS LL_AHB4_GRP1_EnableClockLowPower\n
1575 * AHB4LPENSR GPIOFLPENS LL_AHB4_GRP1_EnableClockLowPower\n
1576 * AHB4LPENSR GPIOGLPENS LL_AHB4_GRP1_EnableClockLowPower\n
1577 * AHB4LPENSR GPIOHLPENS LL_AHB4_GRP1_EnableClockLowPower\n
1578 * AHB4LPENSR GPIONLPENS LL_AHB4_GRP1_EnableClockLowPower\n
1579 * AHB4LPENSR GPIOOLPENS LL_AHB4_GRP1_EnableClockLowPower\n
1580 * AHB4LPENSR GPIOPLPENS LL_AHB4_GRP1_EnableClockLowPower\n
1581 * AHB4LPENSR GPIOQLPENS LL_AHB4_GRP1_EnableClockLowPower\n
1582 * AHB4LPENSR CRCLPENS LL_AHB4_GRP1_EnableClockLowPower\n
1583 * AHB4LPENSR BKPRAMLPENS LL_AHB4_GRP1_EnableClockLowPower
1584 * @param Periphs This parameter can be a combination of the following values:
1585 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1586 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1587 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1588 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1589 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1590 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1591 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1592 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1593 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
1594 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
1595 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
1596 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
1597 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
1598 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
1599 * @retval None
1600 */
LL_AHB4_GRP1_EnableClockLowPower(uint32_t Periphs)1601 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockLowPower(uint32_t Periphs)
1602 {
1603 __IO uint32_t tmpreg;
1604 WRITE_REG(RCC->AHB4LPENSR, Periphs);
1605 /* Delay after an RCC peripheral clock enabling */
1606 tmpreg = READ_REG(RCC->AHB4LPENR);
1607 (void)tmpreg;
1608 }
1609
1610 /**
1611 * @brief Check if AHB4 peripheral clock during Low Power mode is enabled or not .
1612 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1613 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1614 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1615 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1616 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1617 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1618 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1619 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1620 * AHB4LPENR GPIONLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1621 * AHB4LPENR GPIOOLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1622 * AHB4LPENR GPIOPLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1623 * AHB4LPENR GPIOQLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1624 * AHB4LPENR PWRLPEN LL_AHB4_GRP1_IsEnabledClockLowPower\n
1625 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_IsEnabledClockLowPower
1626 * @param Periphs This parameter can be a combination of the following values:
1627 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1628 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1629 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1630 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1631 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1632 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1633 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1634 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1635 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
1636 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
1637 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
1638 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
1639 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
1640 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
1641 * @retval uint32_t
1642 */
LL_AHB4_GRP1_IsEnabledClockLowPower(uint32_t Periphs)1643 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
1644 {
1645 return ((READ_BIT(RCC->AHB4LPENR, Periphs) == Periphs) ? 1UL : 0UL);
1646 }
1647
1648 /**
1649 * @brief Disable AHB4 peripherals clock during Low Power mode.
1650 * @rmtoll AHB4LPENCR GPIOALPENC LL_AHB4_GRP1_DisableClockLowPower\n
1651 * AHB4LPENCR GPIOBLPENC LL_AHB4_GRP1_DisableClockLowPower\n
1652 * AHB4LPENCR GPIOCLPENC LL_AHB4_GRP1_DisableClockLowPower\n
1653 * AHB4LPENCR GPIODLPENC LL_AHB4_GRP1_DisableClockLowPower\n
1654 * AHB4LPENCR GPIOELPENC LL_AHB4_GRP1_DisableClockLowPower\n
1655 * AHB4LPENCR GPIOFLPENC LL_AHB4_GRP1_DisableClockLowPower\n
1656 * AHB4LPENCR GPIOGLPENC LL_AHB4_GRP1_DisableClockLowPower\n
1657 * AHB4LPENCR GPIOHLPENC LL_AHB4_GRP1_DisableClockLowPower\n
1658 * AHB4LPENCR GPIONLPENC LL_AHB4_GRP1_DisableClockLowPower\n
1659 * AHB4LPENCR GPIOOLPENC LL_AHB4_GRP1_DisableClockLowPower\n
1660 * AHB4LPENCR GPIOPLPENC LL_AHB4_GRP1_DisableClockLowPower\n
1661 * AHB4LPENCR GPIOQLPENC LL_AHB4_GRP1_DisableClockLowPower\n
1662 * AHB4LPENCR PWRLPENC LL_AHB4_GRP1_DisableClockLowPower\n
1663 * AHB4LPENCR CRCLPENC LL_AHB4_GRP1_DisableClockLowPower
1664 * @param Periphs This parameter can be a combination of the following values:
1665 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1666 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1667 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1668 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1669 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1670 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1671 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1672 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1673 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
1674 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
1675 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
1676 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
1677 * @arg @ref LL_AHB4_GRP1_PERIPH_PWR
1678 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
1679 * @retval None
1680 */
LL_AHB4_GRP1_DisableClockLowPower(uint32_t Periphs)1681 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockLowPower(uint32_t Periphs)
1682 {
1683 WRITE_REG(RCC->AHB4LPENCR, Periphs);
1684 }
1685
1686 /**
1687 * @}
1688 */
1689
1690 /** @defgroup BUS_LL_EF_AHB5 AHB5
1691 * @{
1692 */
1693
1694 /**
1695 * @brief Enable AHB5 peripherals clock.
1696 * @rmtoll AHB5ENSR HPDMA1ENS LL_AHB5_GRP1_EnableClock\n
1697 * AHB5ENSR DMA2DENS LL_AHB5_GRP1_EnableClock\n
1698 * AHB5ENSR JPEGENS LL_AHB5_GRP1_EnableClock\n
1699 * AHB5ENSR FMCENS LL_AHB5_GRP1_EnableClock\n
1700 * AHB5ENSR XSPI1ENS LL_AHB5_GRP1_EnableClock\n
1701 * AHB5ENSR PSSIENS LL_AHB5_GRP1_EnableClock\n
1702 * AHB5ENSR SDMMC2ENS LL_AHB5_GRP1_EnableClock\n
1703 * AHB5ENSR SDMMC1ENS LL_AHB5_GRP1_EnableClock\n
1704 * AHB5ENSR XSPI2ENS LL_AHB5_GRP1_EnableClock\n
1705 * AHB5ENSR XSPIMENS LL_AHB5_GRP1_EnableClock\n
1706 * AHB5ENSR MCE1ENS LL_AHB5_GRP1_EnableClock\n (*)
1707 * AHB5ENSR MCE2ENS LL_AHB5_GRP1_EnableClock\n (*)
1708 * AHB5ENSR MCE3ENS LL_AHB5_GRP1_EnableClock\n (*)
1709 * AHB5ENSR XSPI3ENS LL_AHB5_GRP1_EnableClock\n
1710 * AHB5ENSR MCE4ENS LL_AHB5_GRP1_EnableClock\n (*)
1711 * AHB5ENSR GFXMMUENS LL_AHB5_GRP1_EnableClock\n
1712 * AHB5ENSR GPU2DENS LL_AHB5_GRP1_EnableClock\n
1713 * AHB5ENSR ETH1MACENS LL_AHB5_GRP1_EnableClock\n
1714 * AHB5ENSR ETH1TXENS LL_AHB5_GRP1_EnableClock\n
1715 * AHB5ENSR ETH1RXENS LL_AHB5_GRP1_EnableClock\n
1716 * AHB5ENSR ETH1ENS LL_AHB5_GRP1_EnableClock\n
1717 * AHB5ENSR OTG1ENS LL_AHB5_GRP1_EnableClock\n
1718 * AHB5ENSR OTGPHY1ENS LL_AHB5_GRP1_EnableClock\n
1719 * AHB5ENSR OTGPHY2ENS LL_AHB5_GRP1_EnableClock\n
1720 * AHB5ENSR OTG2ENS LL_AHB5_GRP1_EnableClock\n
1721 * AHB5ENSR CACHEAXIENS LL_AHB5_GRP1_EnableClock\n
1722 * AHB5ENSR NPUENS LL_AHB5_GRP1_EnableClock
1723 * @param Periphs This parameter can be a combination of the following values:
1724 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1725 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1726 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
1727 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1728 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1729 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1730 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
1731 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1732 * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
1733 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1734 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
1735 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
1736 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
1737 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
1738 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
1739 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
1740 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
1741 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
1742 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
1743 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
1744 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
1745 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
1746 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
1747 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
1748 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
1749 * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
1750 * @arg @ref LL_AHB5_GRP1_PERIPH_NPU
1751 *
1752 * (*) value not defined in all devices.
1753 * @retval None
1754 */
LL_AHB5_GRP1_EnableClock(uint32_t Periphs)1755 __STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs)
1756 {
1757 __IO uint32_t tmpreg;
1758 WRITE_REG(RCC->AHB5ENSR, Periphs);
1759 /* Delay after an RCC peripheral clock enabling */
1760 tmpreg = READ_REG(RCC->AHB5ENR);
1761 (void)tmpreg;
1762 }
1763
1764 /**
1765 * @brief Check if AHB5 peripheral clock is enabled or not
1766 * @rmtoll AHB5ENR HPDMA1EN LL_AHB5_GRP1_IsEnabledClock\n
1767 * AHB5ENR DMA2DEN LL_AHB5_GRP1_IsEnabledClock\n
1768 * AHB5ENR JPEGEN LL_AHB5_GRP1_IsEnabledClock\n
1769 * AHB5ENR FMCEN LL_AHB5_GRP1_IsEnabledClock\n
1770 * AHB5ENR XSPI1EN LL_AHB5_GRP1_IsEnabledClock\n
1771 * AHB5ENR PSSIEN LL_AHB5_GRP1_IsEnabledClock\n
1772 * AHB5ENR SDMMC2EN LL_AHB5_GRP1_IsEnabledClock\n
1773 * AHB5ENR SDMMC1EN LL_AHB5_GRP1_IsEnabledClock\n
1774 * AHB5ENR XSPI2EN LL_AHB5_GRP1_IsEnabledClock\n
1775 * AHB5ENR XSPIMEN LL_AHB5_GRP1_IsEnabledClock\n
1776 * AHB5ENR MCE1EN LL_AHB5_GRP1_IsEnabledClock\n (*)
1777 * AHB5ENR MCE2EN LL_AHB5_GRP1_IsEnabledClock\n (*)
1778 * AHB5ENR MCE3EN LL_AHB5_GRP1_IsEnabledClock\n (*)
1779 * AHB5ENR XSPI3EN LL_AHB5_GRP1_IsEnabledClock\n
1780 * AHB5ENR MCE4EN LL_AHB5_GRP1_IsEnabledClock\n (*)
1781 * AHB5ENR GFXMMUEN LL_AHB5_GRP1_IsEnabledClock\n
1782 * AHB5ENR GPU2DEN LL_AHB5_GRP1_IsEnabledClock\n
1783 * AHB5ENR ETH1MACEN LL_AHB5_GRP1_IsEnabledClock\n
1784 * AHB5ENR ETH1TXEN LL_AHB5_GRP1_IsEnabledClock\n
1785 * AHB5ENR ETH1RXEN LL_AHB5_GRP1_IsEnabledClock\n
1786 * AHB5ENR ETH1EN LL_AHB5_GRP1_IsEnabledClock\n
1787 * AHB5ENR OTG1EN LL_AHB5_GRP1_IsEnabledClock\n
1788 * AHB5ENR OTGPHY1EN LL_AHB5_GRP1_IsEnabledClock\n
1789 * AHB5ENR OTGPHY2EN LL_AHB5_GRP1_IsEnabledClock\n
1790 * AHB5ENR OTG2EN LL_AHB5_GRP1_IsEnabledClock\n
1791 * AHB5ENR CACHEAXIEN LL_AHB5_GRP1_IsEnabledClock\n
1792 * AHB5ENR NPUEN LL_AHB5_GRP1_IsEnabledClock
1793 * @param Periphs This parameter can be a combination of the following values:
1794 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1795 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1796 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
1797 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1798 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1799 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1800 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
1801 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1802 * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
1803 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1804 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
1805 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
1806 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
1807 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
1808 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
1809 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
1810 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
1811 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
1812 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
1813 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
1814 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
1815 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
1816 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
1817 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
1818 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
1819 * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
1820 * @arg @ref LL_AHB5_GRP1_PERIPH_NPU
1821 *
1822 * (*) value not defined in all devices.
1823 * @retval uint32_t
1824 */
LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)1825 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)
1826 {
1827 return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1UL : 0UL);
1828 }
1829
1830 /**
1831 * @brief Disable AHB5 peripherals clock.
1832 * @rmtoll AHB5ENCR HPDMA1ENC LL_AHB5_GRP1_DisableClock\n
1833 * AHB5ENCR DMA2DENC LL_AHB5_GRP1_DisableClock\n
1834 * AHB5ENCR JPEGENC LL_AHB5_GRP1_DisableClock\n
1835 * AHB5ENCR FMCENC LL_AHB5_GRP1_DisableClock\n
1836 * AHB5ENCR XSPI1ENC LL_AHB5_GRP1_DisableClock\n
1837 * AHB5ENCR PSSIENC LL_AHB5_GRP1_DisableClock\n
1838 * AHB5ENCR SDMMC2ENC LL_AHB5_GRP1_DisableClock\n
1839 * AHB5ENCR SDMMC1ENC LL_AHB5_GRP1_DisableClock\n
1840 * AHB5ENCR XSPI2ENC LL_AHB5_GRP1_DisableClock\n
1841 * AHB5ENCR XSPIMENC LL_AHB5_GRP1_DisableClock\n
1842 * AHB5ENCR MCE1ENC LL_AHB5_GRP1_DisableClock\n (*)
1843 * AHB5ENCR MCE2ENC LL_AHB5_GRP1_DisableClock\n (*)
1844 * AHB5ENCR MCE3ENC LL_AHB5_GRP1_DisableClock\n (*)
1845 * AHB5ENCR XSPI3ENC LL_AHB5_GRP1_DisableClock\n
1846 * AHB5ENCR MCE4ENC LL_AHB5_GRP1_DisableClock\n (*)
1847 * AHB5ENCR GFXMMUENC LL_AHB5_GRP1_DisableClock\n
1848 * AHB5ENCR GPU2DENC LL_AHB5_GRP1_DisableClock\n
1849 * AHB5ENCR ETH1MACENC LL_AHB5_GRP1_DisableClock\n
1850 * AHB5ENCR ETH1TXENC LL_AHB5_GRP1_DisableClock\n
1851 * AHB5ENCR ETH1RXENC LL_AHB5_GRP1_DisableClock\n
1852 * AHB5ENCR ETH1ENC LL_AHB5_GRP1_DisableClock\n
1853 * AHB5ENCR OTG1ENC LL_AHB5_GRP1_DisableClock\n
1854 * AHB5ENCR OTGPHY1ENC LL_AHB5_GRP1_DisableClock\n
1855 * AHB5ENCR OTGPHY2ENC LL_AHB5_GRP1_DisableClock\n
1856 * AHB5ENCR OTG2ENC LL_AHB5_GRP1_DisableClock\n
1857 * AHB5ENCR CACHEAXIENC LL_AHB5_GRP1_DisableClock\n
1858 * AHB5ENCR NPUENC LL_AHB5_GRP1_DisableClock
1859 * @param Periphs This parameter can be a combination of the following values:
1860 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1861 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1862 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
1863 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1864 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1865 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1866 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
1867 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1868 * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
1869 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1870 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
1871 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
1872 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
1873 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
1874 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
1875 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
1876 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
1877 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
1878 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
1879 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
1880 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
1881 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
1882 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
1883 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
1884 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
1885 * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
1886 * @arg @ref LL_AHB5_GRP1_PERIPH_NPU
1887 *
1888 * (*) value not defined in all devices.
1889 * @retval None
1890 */
LL_AHB5_GRP1_DisableClock(uint32_t Periphs)1891 __STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs)
1892 {
1893 WRITE_REG(RCC->AHB5ENCR, Periphs);
1894 }
1895
1896 /**
1897 * @brief Force AHB5 peripherals reset.
1898 * @rmtoll AHB5RSTSR HPDMA1RSTS LL_AHB5_GRP1_ForceReset\n
1899 * AHB5RSTSR DMA2DRSTS LL_AHB5_GRP1_ForceReset\n
1900 * AHB5RSTSR JPEGRSTS LL_AHB5_GRP1_ForceReset\n
1901 * AHB5RSTSR FMCRSTS LL_AHB5_GRP1_ForceReset\n
1902 * AHB5RSTSR XSPI1RSTS LL_AHB5_GRP1_ForceReset\n
1903 * AHB5RSTSR PSSIRSTS LL_AHB5_GRP1_ForceReset\n
1904 * AHB5RSTSR SDMMC2RSTS LL_AHB5_GRP1_ForceReset\n
1905 * AHB5RSTSR SDMMC1RSTS LL_AHB5_GRP1_ForceReset\n
1906 * AHB5RSTSR XSPI2RSTS LL_AHB5_GRP1_ForceReset\n
1907 * AHB5RSTSR XSPIMRSTS LL_AHB5_GRP1_ForceReset\n
1908 * AHB5RSTSR XSPI3RSTS LL_AHB5_GRP1_ForceReset\n
1909 * AHB5RSTSR GFXMMURSTS LL_AHB5_GRP1_ForceReset\n
1910 * AHB5RSTSR GPU2DRSTS LL_AHB5_GRP1_ForceReset\n
1911 * AHB5RSTSR OTG1PHYCTLRSTS LL_AHB5_GRP1_ForceReset\n
1912 * AHB5RSTSR OTG2PHYCTLRSTS LL_AHB5_GRP1_ForceReset\n
1913 * AHB5RSTSR ETH1RSTS LL_AHB5_GRP1_ForceReset\n
1914 * AHB5RSTSR OTG1RSTS LL_AHB5_GRP1_ForceReset\n
1915 * AHB5RSTSR OTGPHY1RSTS LL_AHB5_GRP1_ForceReset\n
1916 * AHB5RSTSR OTGPHY2RSTS LL_AHB5_GRP1_ForceReset\n
1917 * AHB5RSTSR OTG2RSTS LL_AHB5_GRP1_ForceReset\n
1918 * AHB5RSTSR CACHEAXIRSTS LL_AHB5_GRP1_ForceReset\n
1919 * AHB5RSTSR NPURSTS LL_AHB5_GRP1_ForceReset
1920 * @param Periphs This parameter can be a combination of the following values:
1921 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1922 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1923 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
1924 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1925 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1926 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1927 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
1928 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1929 * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
1930 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1931 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
1932 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
1933 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
1934 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1PHYCTL
1935 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2PHYCTL
1936 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
1937 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
1938 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
1939 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
1940 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
1941 * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
1942 * @arg @ref LL_AHB5_GRP1_PERIPH_NPU
1943 * @retval None
1944 */
LL_AHB5_GRP1_ForceReset(uint32_t Periphs)1945 __STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs)
1946 {
1947 WRITE_REG(RCC->AHB5RSTSR, Periphs);
1948 }
1949
1950 /**
1951 * @brief Release AHB5 peripherals reset.
1952 * @rmtoll AHB5RSTCR HPDMA1RSTC LL_AHB5_GRP1_ReleaseReset\n
1953 * AHB5RSTCR DMA2DRSTC LL_AHB5_GRP1_ReleaseReset\n
1954 * AHB5RSTCR JPEGRSTC LL_AHB5_GRP1_ReleaseReset\n
1955 * AHB5RSTCR FMCRSTC LL_AHB5_GRP1_ReleaseReset\n
1956 * AHB5RSTCR XSPI1RSTC LL_AHB5_GRP1_ReleaseReset\n
1957 * AHB5RSTCR PSSIRSTC LL_AHB5_GRP1_ReleaseReset\n
1958 * AHB5RSTCR SDMMC2RSTC LL_AHB5_GRP1_ReleaseReset\n
1959 * AHB5RSTCR SDMMC1RSTC LL_AHB5_GRP1_ReleaseReset\n
1960 * AHB5RSTCR XSPI2RSTC LL_AHB5_GRP1_ReleaseReset\n
1961 * AHB5RSTCR XSPIMRSTC LL_AHB5_GRP1_ReleaseReset\n
1962 * AHB5RSTCR XSPI3RSTC LL_AHB5_GRP1_ReleaseReset\n
1963 * AHB5RSTCR GFXMMURSTC LL_AHB5_GRP1_ReleaseReset\n
1964 * AHB5RSTCR GPU2DRSTC LL_AHB5_GRP1_ReleaseReset\n
1965 * AHB5RSTCR OTG1PHYCTLRSTC LL_AHB5_GRP1_ReleaseReset\n
1966 * AHB5RSTCR OTG2PHYCTLRSTC LL_AHB5_GRP1_ReleaseReset\n
1967 * AHB5RSTCR ETH1RSTC LL_AHB5_GRP1_ReleaseReset\n
1968 * AHB5RSTCR OTG1RSTC LL_AHB5_GRP1_ReleaseReset\n
1969 * AHB5RSTCR OTGPHY1RSTC LL_AHB5_GRP1_ReleaseReset\n
1970 * AHB5RSTCR OTGPHY2RSTC LL_AHB5_GRP1_ReleaseReset\n
1971 * AHB5RSTCR OTG2RSTC LL_AHB5_GRP1_ReleaseReset\n
1972 * AHB5RSTCR CACHEAXIRSTC LL_AHB5_GRP1_ReleaseReset\n
1973 * AHB5RSTCR NPURSTS LL_AHB5_GRP1_ReleaseReset
1974 * @param Periphs This parameter can be a combination of the following values:
1975 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1976 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1977 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
1978 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1979 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1980 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1981 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
1982 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1983 * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
1984 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1985 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
1986 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
1987 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
1988 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1PHYCTL
1989 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2PHYCTL
1990 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
1991 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
1992 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
1993 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
1994 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
1995 * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
1996 * @arg @ref LL_AHB5_GRP1_PERIPH_NPU
1997 * @retval None
1998 */
LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)1999 __STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)
2000 {
2001 WRITE_REG(RCC->AHB5RSTCR, Periphs);
2002 }
2003
2004 /**
2005 * @brief Enable AHB5 peripherals clock during Low Power mode.
2006 * @rmtoll AHB5LPENSR HPDMA1LPENS LL_AHB5_GRP1_EnableClockLowPower\n
2007 * AHB5LPENSR DMA2DLPENS LL_AHB5_GRP1_EnableClockLowPower\n
2008 * AHB5LPENSR JPEGLPENS LL_AHB5_GRP1_EnableClockLowPower\n
2009 * AHB5LPENSR FMCLPENS LL_AHB5_GRP1_EnableClockLowPower\n
2010 * AHB5LPENSR XSPI1LPENS LL_AHB5_GRP1_EnableClockLowPower\n
2011 * AHB5LPENSR PSSILPENS LL_AHB5_GRP1_EnableClockLowPower\n
2012 * AHB5LPENSR SDMMC2LPENS LL_AHB5_GRP1_EnableClockLowPower\n
2013 * AHB5LPENSR SDMMC1LPENS LL_AHB5_GRP1_EnableClockLowPower\n
2014 * AHB5LPENSR XSPI2LPENS LL_AHB5_GRP1_EnableClockLowPower\n
2015 * AHB5LPENSR XSPIMLPENS LL_AHB5_GRP1_EnableClockLowPower\n
2016 * AHB5LPENSR MCE1LPENS LL_AHB5_GRP1_EnableClockLowPower\n (*)
2017 * AHB5LPENSR MCE2LPENS LL_AHB5_GRP1_EnableClockLowPower\n (*)
2018 * AHB5LPENSR MCE3LPENS LL_AHB5_GRP1_EnableClockLowPower\n (*)
2019 * AHB5LPENSR XSPI3LPENS LL_AHB5_GRP1_EnableClockLowPower\n
2020 * AHB5LPENSR MCE4LPENS LL_AHB5_GRP1_EnableClockLowPower\n (*)
2021 * AHB5LPENSR GFXMMULPENS LL_AHB5_GRP1_EnableClockLowPower\n
2022 * AHB5LPENSR GPU2DLPENS LL_AHB5_GRP1_EnableClockLowPower\n
2023 * AHB5LPENSR ETH1MACLPENS LL_AHB5_GRP1_EnableClockLowPower\n
2024 * AHB5LPENSR ETH1TXLPENS LL_AHB5_GRP1_EnableClockLowPower\n
2025 * AHB5LPENSR ETH1RXLPENS LL_AHB5_GRP1_EnableClockLowPower\n
2026 * AHB5LPENSR ETH1LPENS LL_AHB5_GRP1_EnableClockLowPower\n
2027 * AHB5LPENSR OTG1LPENS LL_AHB5_GRP1_EnableClockLowPower\n
2028 * AHB5LPENSR OTGPHY1LPENS LL_AHB5_GRP1_EnableClockLowPower\n
2029 * AHB5LPENSR OTGPHY2LPENS LL_AHB5_GRP1_EnableClockLowPower\n
2030 * AHB5LPENSR OTG2LPENS LL_AHB5_GRP1_EnableClockLowPower\n
2031 * AHB5LPENSR CACHEAXILPENS LL_AHB5_GRP1_EnableClockLowPower\n
2032 * AHB5LPENSR NPULPENS LL_AHB5_GRP1_EnableClockLowPower
2033 * @param Periphs This parameter can be a combination of the following values:
2034 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
2035 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
2036 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
2037 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
2038 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
2039 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
2040 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
2041 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
2042 * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
2043 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
2044 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
2045 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
2046 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
2047 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
2048 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
2049 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
2050 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
2051 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
2052 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
2053 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
2054 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
2055 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
2056 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
2057 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
2058 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
2059 * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
2060 * @arg @ref LL_AHB5_GRP1_PERIPH_NPU
2061 *
2062 * (*) value not defined in all devices.
2063 * @retval None
2064 */
LL_AHB5_GRP1_EnableClockLowPower(uint32_t Periphs)2065 __STATIC_INLINE void LL_AHB5_GRP1_EnableClockLowPower(uint32_t Periphs)
2066 {
2067 __IO uint32_t tmpreg;
2068 WRITE_REG(RCC->AHB5LPENSR, Periphs);
2069 /* Delay after an RCC peripheral clock enabling */
2070 tmpreg = READ_REG(RCC->AHB5LPENR);
2071 (void)tmpreg;
2072 }
2073
2074 /**
2075 * @brief Check if AHB5 peripheral clock during Low Power mode is enabled or not .
2076 * @rmtoll AHB5LPENR HPDMA1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2077 * AHB5LPENR DMA2DLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2078 * AHB5LPENR JPEGLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2079 * AHB5LPENR FMCLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2080 * AHB5LPENR XSPI1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2081 * AHB5LPENR PSSILPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2082 * AHB5LPENR SDMMC2LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2083 * AHB5LPENR SDMMC1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2084 * AHB5LPENR XSPI2LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2085 * AHB5LPENR XSPIMLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2086 * AHB5LPENR MCE1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n (*)
2087 * AHB5LPENR MCE2LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n (*)
2088 * AHB5LPENR MCE3LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n (*)
2089 * AHB5LPENR XSPI3LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2090 * AHB5LPENR MCE4LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n (*)
2091 * AHB5LPENR GFXMMULPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2092 * AHB5LPENR GPU2DLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2093 * AHB5LPENR ETH1MACLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2094 * AHB5LPENR ETH1TXLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2095 * AHB5LPENR ETH1RXLPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2096 * AHB5LPENR ETH1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2097 * AHB5LPENR OTG1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2098 * AHB5LPENR OTGPHY1LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2099 * AHB5LPENR OTGPHY2LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2100 * AHB5LPENR OTG2LPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2101 * AHB5LPENR CACHEAXILPEN LL_AHB5_GRP1_IsEnabledClockLowPower\n
2102 * AHB5LPENR NPULPEN LL_AHB5_GRP1_IsEnabledClockLowPower
2103 * @param Periphs This parameter can be a combination of the following values:
2104 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
2105 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
2106 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
2107 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
2108 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
2109 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
2110 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
2111 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
2112 * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
2113 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
2114 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
2115 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
2116 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
2117 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
2118 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
2119 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
2120 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
2121 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
2122 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
2123 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
2124 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
2125 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
2126 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
2127 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
2128 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
2129 * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
2130 * @arg @ref LL_AHB5_GRP1_PERIPH_NPU
2131 *
2132 * (*) value not defined in all devices.
2133 * @retval uint32_t
2134 */
LL_AHB5_GRP1_IsEnabledClockLowPower(uint32_t Periphs)2135 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
2136 {
2137 return ((READ_BIT(RCC->AHB5LPENR, Periphs) == Periphs) ? 1UL : 0UL);
2138 }
2139
2140 /**
2141 * @brief Disable AHB5 peripherals clock during Low Power mode.
2142 * @rmtoll AHB5LPENCR HPDMA1LPENC LL_AHB5_GRP1_DisableClockLowPower\n
2143 * AHB5LPENCR DMA2DLPENC LL_AHB5_GRP1_DisableClockLowPower\n
2144 * AHB5LPENCR JPEGLPENC LL_AHB5_GRP1_DisableClockLowPower\n
2145 * AHB5LPENCR FMCLPENC LL_AHB5_GRP1_DisableClockLowPower\n
2146 * AHB5LPENCR XSPI1LPENC LL_AHB5_GRP1_DisableClockLowPower\n
2147 * AHB5LPENCR PSSILPENC LL_AHB5_GRP1_DisableClockLowPower\n
2148 * AHB5LPENCR SDMMC2LPENC LL_AHB5_GRP1_DisableClockLowPower\n
2149 * AHB5LPENCR SDMMC1LPENC LL_AHB5_GRP1_DisableClockLowPower\n
2150 * AHB5LPENCR XSPI2LPENC LL_AHB5_GRP1_DisableClockLowPower\n
2151 * AHB5LPENCR XSPIMLPENC LL_AHB5_GRP1_DisableClockLowPower\n
2152 * AHB5LPENCR MCE1LPENC LL_AHB5_GRP1_DisableClockLowPower\n (*)
2153 * AHB5LPENCR MCE2LPENC LL_AHB5_GRP1_DisableClockLowPower\n (*)
2154 * AHB5LPENCR MCE3LPENC LL_AHB5_GRP1_DisableClockLowPower\n (*)
2155 * AHB5LPENCR XSPI3LPENC LL_AHB5_GRP1_DisableClockLowPower\n
2156 * AHB5LPENCR MCE4LPENC LL_AHB5_GRP1_DisableClockLowPower\n (*)
2157 * AHB5LPENCR GFXMMULPENC LL_AHB5_GRP1_DisableClockLowPower\n
2158 * AHB5LPENCR GPU2DLPENC LL_AHB5_GRP1_DisableClockLowPower\n
2159 * AHB5LPENCR ETH1MACLPENC LL_AHB5_GRP1_DisableClockLowPower\n
2160 * AHB5LPENCR ETH1TXLPENC LL_AHB5_GRP1_DisableClockLowPower\n
2161 * AHB5LPENCR ETH1RXLPENC LL_AHB5_GRP1_DisableClockLowPower\n
2162 * AHB5LPENCR ETH1LPENC LL_AHB5_GRP1_DisableClockLowPower\n
2163 * AHB5LPENCR OTG1LPENC LL_AHB5_GRP1_DisableClockLowPower\n
2164 * AHB5LPENCR OTGPHY1LPENC LL_AHB5_GRP1_DisableClockLowPower\n
2165 * AHB5LPENCR OTGPHY2LPENC LL_AHB5_GRP1_DisableClockLowPower\n
2166 * AHB5LPENCR OTG2LPENC LL_AHB5_GRP1_DisableClockLowPower\n
2167 * AHB5LPENCR CACHEAXILPENC LL_AHB5_GRP1_DisableClockLowPower\n
2168 * AHB5LPENCR NPULPENC LL_AHB5_GRP1_DisableClockLowPower
2169 * @param Periphs This parameter can be a combination of the following values:
2170 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
2171 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
2172 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
2173 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
2174 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
2175 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
2176 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
2177 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
2178 * @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
2179 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
2180 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
2181 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
2182 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
2183 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
2184 * @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
2185 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
2186 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
2187 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
2188 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
2189 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
2190 * @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
2191 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
2192 * @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
2193 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
2194 * @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
2195 * @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
2196 * @arg @ref LL_AHB5_GRP1_PERIPH_NPU
2197 *
2198 * (*) value not defined in all devices.
2199 * @retval None
2200 */
LL_AHB5_GRP1_DisableClockLowPower(uint32_t Periphs)2201 __STATIC_INLINE void LL_AHB5_GRP1_DisableClockLowPower(uint32_t Periphs)
2202 {
2203 WRITE_REG(RCC->AHB5LPENCR, Periphs);
2204 }
2205
2206 /**
2207 * @}
2208 */
2209
2210 /** @defgroup BUS_LL_EF_APB1 APB1
2211 * @{
2212 */
2213
2214 /**
2215 * @brief Enable APB1 peripherals clock.
2216 * @rmtoll APB1ENSR1 TIM2ENS LL_APB1_GRP1_EnableClock\n
2217 * APB1ENSR1 TIM3ENS LL_APB1_GRP1_EnableClock\n
2218 * APB1ENSR1 TIM4ENS LL_APB1_GRP1_EnableClock\n
2219 * APB1ENSR1 TIM5ENS LL_APB1_GRP1_EnableClock\n
2220 * APB1ENSR1 TIM6ENS LL_APB1_GRP1_EnableClock\n
2221 * APB1ENSR1 TIM7ENS LL_APB1_GRP1_EnableClock\n
2222 * APB1ENSR1 TIM12ENS LL_APB1_GRP1_EnableClock\n
2223 * APB1ENSR1 TIM13ENS LL_APB1_GRP1_EnableClock\n
2224 * APB1ENSR1 TIM14ENS LL_APB1_GRP1_EnableClock\n
2225 * APB1ENSR1 LPTIM1ENS LL_APB1_GRP1_EnableClock\n
2226 * APB1ENSR1 WWDGENS LL_APB1_GRP1_EnableClock\n
2227 * APB1ENSR1 TIM10ENS LL_APB1_GRP1_EnableClock\n
2228 * APB1ENSR1 TIM11ENS LL_APB1_GRP1_EnableClock\n
2229 * APB1ENSR1 SPI2ENS LL_APB1_GRP1_EnableClock\n
2230 * APB1ENSR1 SPI3ENS LL_APB1_GRP1_EnableClock\n
2231 * APB1ENSR1 SPDIFRX1ENS LL_APB1_GRP1_EnableClock\n
2232 * APB1ENSR1 USART2ENS LL_APB1_GRP1_EnableClock\n
2233 * APB1ENSR1 USART3ENS LL_APB1_GRP1_EnableClock\n
2234 * APB1ENSR1 UART4ENS LL_APB1_GRP1_EnableClock\n
2235 * APB1ENSR1 UART5ENS LL_APB1_GRP1_EnableClock\n
2236 * APB1ENSR1 I2C1ENS LL_APB1_GRP1_EnableClock\n
2237 * APB1ENSR1 I2C2ENS LL_APB1_GRP1_EnableClock\n
2238 * APB1ENSR1 I2C3ENS LL_APB1_GRP1_EnableClock\n
2239 * APB1ENSR1 I3C1ENS LL_APB1_GRP1_EnableClock\n
2240 * APB1ENSR1 I3C2ENS LL_APB1_GRP1_EnableClock\n
2241 * APB1ENSR1 UART7ENS LL_APB1_GRP1_EnableClock\n
2242 * APB1ENSR1 UART8ENS LL_APB1_GRP1_EnableClock
2243 * @param Periphs This parameter can be a combination of the following values:
2244 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2245 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2246 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2247 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
2248 * @arg @ref LL_APB1_GRP1_PERIPH_I3C2
2249 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2250 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
2251 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2252 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2253 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2254 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2255 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2256 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2257 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2258 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2259 * @arg @ref LL_APB1_GRP1_PERIPH_TIM10
2260 * @arg @ref LL_APB1_GRP1_PERIPH_TIM11
2261 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2262 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2263 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2264 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2265 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2266 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2267 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2268 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2269 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2270 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
2271 * @retval None
2272 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)2273 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
2274 {
2275 __IO uint32_t tmpreg;
2276 WRITE_REG(RCC->APB1ENSR1, Periphs);
2277 /* Delay after an RCC peripheral clock enabling */
2278 tmpreg = READ_REG(RCC->APB1ENR1);
2279 (void)tmpreg;
2280 }
2281
2282 /**
2283 * @brief Check if APB1 peripheral clock is enabled or not
2284 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
2285 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
2286 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
2287 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
2288 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
2289 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
2290 * APB1ENR1 TIM12EN LL_APB1_GRP1_IsEnabledClock\n
2291 * APB1ENR1 TIM13EN LL_APB1_GRP1_IsEnabledClock\n
2292 * APB1ENR1 TIM14EN LL_APB1_GRP1_IsEnabledClock\n
2293 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
2294 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
2295 * APB1ENR1 TIM10EN LL_APB1_GRP1_IsEnabledClock\n
2296 * APB1ENR1 TIM11EN LL_APB1_GRP1_IsEnabledClock\n
2297 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
2298 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
2299 * APB1ENR1 SPDIFRX1EN LL_APB1_GRP1_IsEnabledClock\n
2300 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
2301 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
2302 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
2303 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
2304 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
2305 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
2306 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
2307 * APB1ENR1 I3C1EN LL_APB1_GRP1_IsEnabledClock\n
2308 * APB1ENR1 I3C2EN LL_APB1_GRP1_IsEnabledClock\n
2309 * APB1ENR1 UART7EN LL_APB1_GRP1_IsEnabledClock\n
2310 * APB1ENR1 UART8EN LL_APB1_GRP1_IsEnabledClock
2311 * @param Periphs This parameter can be a combination of the following values:
2312 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2313 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2314 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2315 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
2316 * @arg @ref LL_APB1_GRP1_PERIPH_I3C2
2317 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2318 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
2319 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2320 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2321 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2322 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2323 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2324 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2325 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2326 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2327 * @arg @ref LL_APB1_GRP1_PERIPH_TIM10
2328 * @arg @ref LL_APB1_GRP1_PERIPH_TIM11
2329 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2330 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2331 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2332 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2333 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2334 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2335 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2336 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2337 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2338 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
2339 * @retval uint32_t
2340 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)2341 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
2342 {
2343 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
2344 }
2345
2346 /**
2347 * @brief Disable APB1 peripherals clock.
2348 * @rmtoll APB1ENCR1 TIM2ENC LL_APB1_GRP1_DisableClock\n
2349 * APB1ENCR1 TIM3ENC LL_APB1_GRP1_DisableClock\n
2350 * APB1ENCR1 TIM4ENC LL_APB1_GRP1_DisableClock\n
2351 * APB1ENCR1 TIM5ENC LL_APB1_GRP1_DisableClock\n
2352 * APB1ENCR1 TIM6ENC LL_APB1_GRP1_DisableClock\n
2353 * APB1ENCR1 TIM7ENC LL_APB1_GRP1_DisableClock\n
2354 * APB1ENCR1 TIM12ENC LL_APB1_GRP1_DisableClock\n
2355 * APB1ENCR1 TIM13ENC LL_APB1_GRP1_DisableClock\n
2356 * APB1ENCR1 TIM14ENC LL_APB1_GRP1_DisableClock\n
2357 * APB1ENCR1 LPTIM1ENC LL_APB1_GRP1_DisableClock\n
2358 * APB1ENCR1 TIM10ENC LL_APB1_GRP1_DisableClock\n
2359 * APB1ENCR1 TIM11ENC LL_APB1_GRP1_DisableClock\n
2360 * APB1ENCR1 SPI2ENC LL_APB1_GRP1_DisableClock\n
2361 * APB1ENCR1 SPI3ENC LL_APB1_GRP1_DisableClock\n
2362 * APB1ENCR1 SPDIFRX1ENC LL_APB1_GRP1_DisableClock\n
2363 * APB1ENCR1 USART2ENC LL_APB1_GRP1_DisableClock\n
2364 * APB1ENCR1 USART3ENC LL_APB1_GRP1_DisableClock\n
2365 * APB1ENCR1 UART4ENC LL_APB1_GRP1_DisableClock\n
2366 * APB1ENCR1 UART5ENC LL_APB1_GRP1_DisableClock\n
2367 * APB1ENCR1 I2C1ENC LL_APB1_GRP1_DisableClock\n
2368 * APB1ENCR1 I2C2ENC LL_APB1_GRP1_DisableClock\n
2369 * APB1ENCR1 I2C3ENC LL_APB1_GRP1_DisableClock\n
2370 * APB1ENCR1 I3C1ENC LL_APB1_GRP1_DisableClock\n
2371 * APB1ENCR1 I3C2ENC LL_APB1_GRP1_DisableClock\n
2372 * APB1ENCR1 UART7ENC LL_APB1_GRP1_DisableClock\n
2373 * APB1ENCR1 UART8ENC LL_APB1_GRP1_DisableClock
2374 * @param Periphs This parameter can be a combination of the following values:
2375 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2376 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2377 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2378 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
2379 * @arg @ref LL_APB1_GRP1_PERIPH_I3C2
2380 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2381 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
2382 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2383 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2384 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2385 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2386 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2387 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2388 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2389 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2390 * @arg @ref LL_APB1_GRP1_PERIPH_TIM10
2391 * @arg @ref LL_APB1_GRP1_PERIPH_TIM11
2392 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2393 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2394 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2395 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2396 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2397 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2398 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2399 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2400 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2401 * @retval None
2402 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)2403 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
2404 {
2405 WRITE_REG(RCC->APB1ENCR1, Periphs);
2406 }
2407
2408 /**
2409 * @brief Force APB1 peripherals reset.
2410 * @rmtoll APB1RSTSR1 TIM2RSTS LL_APB1_GRP1_ForceReset\n
2411 * APB1RSTSR1 TIM3RSTS LL_APB1_GRP1_ForceReset\n
2412 * APB1RSTSR1 TIM4RSTS LL_APB1_GRP1_ForceReset\n
2413 * APB1RSTSR1 TIM5RSTS LL_APB1_GRP1_ForceReset\n
2414 * APB1RSTSR1 TIM6RSTS LL_APB1_GRP1_ForceReset\n
2415 * APB1RSTSR1 TIM7RSTS LL_APB1_GRP1_ForceReset\n
2416 * APB1RSTSR1 TIM12RSTS LL_APB1_GRP1_ForceReset\n
2417 * APB1RSTSR1 TIM13RSTS LL_APB1_GRP1_ForceReset\n
2418 * APB1RSTSR1 TIM14RSTS LL_APB1_GRP1_ForceReset\n
2419 * APB1RSTSR1 LPTIM1RSTS LL_APB1_GRP1_ForceReset\n
2420 * APB1RSTSR1 TIM10RSTS LL_APB1_GRP1_ForceReset\n
2421 * APB1RSTSR1 TIM11RSTS LL_APB1_GRP1_ForceReset\n
2422 * APB1RSTSR1 SPI2RSTS LL_APB1_GRP1_ForceReset\n
2423 * APB1RSTSR1 SPI3RSTS LL_APB1_GRP1_ForceReset\n
2424 * APB1RSTSR1 SPDIFRX1RSTS LL_APB1_GRP1_ForceReset\n
2425 * APB1RSTSR1 USART2RSTS LL_APB1_GRP1_ForceReset\n
2426 * APB1RSTSR1 USART3RSTS LL_APB1_GRP1_ForceReset\n
2427 * APB1RSTSR1 UART4RSTS LL_APB1_GRP1_ForceReset\n
2428 * APB1RSTSR1 UART5RSTS LL_APB1_GRP1_ForceReset\n
2429 * APB1RSTSR1 I2C1RSTS LL_APB1_GRP1_ForceReset\n
2430 * APB1RSTSR1 I2C2RSTS LL_APB1_GRP1_ForceReset\n
2431 * APB1RSTSR1 I2C3RSTS LL_APB1_GRP1_ForceReset\n
2432 * APB1RSTSR1 I3C1RSTS LL_APB1_GRP1_ForceReset\n
2433 * APB1RSTSR1 I3C2RSTS LL_APB1_GRP1_ForceReset\n
2434 * APB1RSTSR1 UART7RSTS LL_APB1_GRP1_ForceReset\n
2435 * APB1RSTSR1 UART8RSTS LL_APB1_GRP1_ForceReset
2436 * @param Periphs This parameter can be a combination of the following values:
2437 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2438 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2439 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2440 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
2441 * @arg @ref LL_APB1_GRP1_PERIPH_I3C2
2442 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2443 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
2444 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2445 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2446 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2447 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2448 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2449 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2450 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2451 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2452 * @arg @ref LL_APB1_GRP1_PERIPH_TIM10
2453 * @arg @ref LL_APB1_GRP1_PERIPH_TIM11
2454 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2455 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2456 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2457 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2458 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2459 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2460 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2461 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2462 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2463 * @retval None
2464 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)2465 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
2466 {
2467 WRITE_REG(RCC->APB1RSTSR1, Periphs);
2468 }
2469
2470 /**
2471 * @brief Release APB1 peripherals reset.
2472 * @rmtoll APB1RSTCR1 TIM2RSTC LL_APB1_GRP1_ReleaseReset\n
2473 * APB1RSTCR1 TIM3RSTC LL_APB1_GRP1_ReleaseReset\n
2474 * APB1RSTCR1 TIM4RSTC LL_APB1_GRP1_ReleaseReset\n
2475 * APB1RSTCR1 TIM5RSTC LL_APB1_GRP1_ReleaseReset\n
2476 * APB1RSTCR1 TIM6RSTC LL_APB1_GRP1_ReleaseReset\n
2477 * APB1RSTCR1 TIM7RSTC LL_APB1_GRP1_ReleaseReset\n
2478 * APB1RSTCR1 TIM12RSTC LL_APB1_GRP1_ReleaseReset\n
2479 * APB1RSTCR1 TIM13RSTC LL_APB1_GRP1_ReleaseReset\n
2480 * APB1RSTCR1 TIM14RSTC LL_APB1_GRP1_ReleaseReset\n
2481 * APB1RSTCR1 LPTIM1RSTC LL_APB1_GRP1_ReleaseReset\n
2482 * APB1RSTCR1 TIM10RSTC LL_APB1_GRP1_ReleaseReset\n
2483 * APB1RSTCR1 TIM11RSTC LL_APB1_GRP1_ReleaseReset\n
2484 * APB1RSTCR1 SPI2RSTC LL_APB1_GRP1_ReleaseReset\n
2485 * APB1RSTCR1 SPI3RSTC LL_APB1_GRP1_ReleaseReset\n
2486 * APB1RSTCR1 SPDIFRX1RSTC LL_APB1_GRP1_ReleaseReset\n
2487 * APB1RSTCR1 USART2RSTC LL_APB1_GRP1_ReleaseReset\n
2488 * APB1RSTCR1 USART3RSTC LL_APB1_GRP1_ReleaseReset\n
2489 * APB1RSTCR1 UART4RSTC LL_APB1_GRP1_ReleaseReset\n
2490 * APB1RSTCR1 UART5RSTC LL_APB1_GRP1_ReleaseReset\n
2491 * APB1RSTCR1 I2C1RSTC LL_APB1_GRP1_ReleaseReset\n
2492 * APB1RSTCR1 I2C2RSTC LL_APB1_GRP1_ReleaseReset\n
2493 * APB1RSTCR1 I2C3RSTC LL_APB1_GRP1_ReleaseReset\n
2494 * APB1RSTCR1 I3C1RSTC LL_APB1_GRP1_ReleaseReset\n
2495 * APB1RSTCR1 I3C2RSTC LL_APB1_GRP1_ReleaseReset\n
2496 * APB1RSTCR1 UART7RSTC LL_APB1_GRP1_ReleaseReset\n
2497 * APB1RSTCR1 UART8RSTC LL_APB1_GRP1_ReleaseReset
2498 * @param Periphs This parameter can be a combination of the following values:
2499 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2500 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2501 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2502 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
2503 * @arg @ref LL_APB1_GRP1_PERIPH_I3C2
2504 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2505 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
2506 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2507 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2508 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2509 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2510 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2511 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2512 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2513 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2514 * @arg @ref LL_APB1_GRP1_PERIPH_TIM10
2515 * @arg @ref LL_APB1_GRP1_PERIPH_TIM11
2516 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2517 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2518 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2519 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2520 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2521 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2522 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2523 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2524 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2525 * @retval None
2526 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)2527 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
2528 {
2529 WRITE_REG(RCC->APB1RSTCR1, Periphs);
2530 }
2531
2532 /**
2533 * @brief Enable APB1 peripherals clock during Low Power mode.
2534 * @rmtoll APB1LPENSR1 TIM2LPENS LL_APB1_GRP1_EnableClockLowPower\n
2535 * APB1LPENSR1 TIM3LPENS LL_APB1_GRP1_EnableClockLowPower\n
2536 * APB1LPENSR1 TIM4LPENS LL_APB1_GRP1_EnableClockLowPower\n
2537 * APB1LPENSR1 TIM5LPENS LL_APB1_GRP1_EnableClockLowPower\n
2538 * APB1LPENSR1 TIM6LPENS LL_APB1_GRP1_EnableClockLowPower\n
2539 * APB1LPENSR1 TIM7LPENS LL_APB1_GRP1_EnableClockLowPower\n
2540 * APB1LPENSR1 TIM12LPENS LL_APB1_GRP1_EnableClockLowPower\n
2541 * APB1LPENSR1 TIM13LPENS LL_APB1_GRP1_EnableClockLowPower\n
2542 * APB1LPENSR1 TIM14LPENS LL_APB1_GRP1_EnableClockLowPower\n
2543 * APB1LPENSR1 LPTIM1LPENS LL_APB1_GRP1_EnableClockLowPower\n
2544 * APB1LPENSR1 WWDGLPENS LL_APB1_GRP1_EnableClockLowPower\n
2545 * APB1LPENSR1 TIM10LPENS LL_APB1_GRP1_EnableClockLowPower\n
2546 * APB1LPENSR1 TIM11LPENS LL_APB1_GRP1_EnableClockLowPower\n
2547 * APB1LPENSR1 SPI2LPENS LL_APB1_GRP1_EnableClockLowPower\n
2548 * APB1LPENSR1 SPI3LPENS LL_APB1_GRP1_EnableClockLowPower\n
2549 * APB1LPENSR1 SPDIFRX1LPENS LL_APB1_GRP1_EnableClockLowPower\n
2550 * APB1LPENSR1 USART2LPENS LL_APB1_GRP1_EnableClockLowPower\n
2551 * APB1LPENSR1 USART3LPENS LL_APB1_GRP1_EnableClockLowPower\n
2552 * APB1LPENSR1 UART4LPENS LL_APB1_GRP1_EnableClockLowPower\n
2553 * APB1LPENSR1 UART5LPENS LL_APB1_GRP1_EnableClockLowPower\n
2554 * APB1LPENSR1 I2C1LPENS LL_APB1_GRP1_EnableClockLowPower\n
2555 * APB1LPENSR1 I2C2LPENS LL_APB1_GRP1_EnableClockLowPower\n
2556 * APB1LPENSR1 I2C3LPENS LL_APB1_GRP1_EnableClockLowPower\n
2557 * APB1LPENSR1 I3C1LPENS LL_APB1_GRP1_EnableClockLowPower\n
2558 * APB1LPENSR1 I3C2LPENS LL_APB1_GRP1_EnableClockLowPower\n
2559 * APB1LPENSR1 UART7LPENS LL_APB1_GRP1_EnableClockLowPower\n
2560 * APB1LPENSR1 UART8LPENS LL_APB1_GRP1_EnableClockLowPower
2561 * @param Periphs This parameter can be a combination of the following values:
2562 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2563 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2564 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2565 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
2566 * @arg @ref LL_APB1_GRP1_PERIPH_I3C2
2567 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2568 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
2569 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2570 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2571 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2572 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2573 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2574 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2575 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2576 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2577 * @arg @ref LL_APB1_GRP1_PERIPH_TIM10
2578 * @arg @ref LL_APB1_GRP1_PERIPH_TIM11
2579 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2580 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2581 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2582 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2583 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2584 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2585 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2586 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2587 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2588 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
2589 * @retval None
2590 */
LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)2591 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
2592 {
2593 __IO uint32_t tmpreg;
2594 WRITE_REG(RCC->APB1LPENSR1, Periphs);
2595 /* Delay after an RCC peripheral clock enabling */
2596 tmpreg = READ_REG(RCC->APB1LPENR1);
2597 (void)tmpreg;
2598 }
2599
2600 /**
2601 * @brief Check if APB1 peripheral clock during Low Power mode is enabled or not .
2602 * @rmtoll APB1LPENR1 TIM2LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2603 * APB1LPENR1 TIM3LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2604 * APB1LPENR1 TIM4LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2605 * APB1LPENR1 TIM5LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2606 * APB1LPENR1 TIM6LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2607 * APB1LPENR1 TIM7LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2608 * APB1LPENR1 TIM12LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2609 * APB1LPENR1 TIM13LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2610 * APB1LPENR1 TIM14LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2611 * APB1LPENR1 LPTIM1LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2612 * APB1LPENR1 WWDGLPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2613 * APB1LPENR1 TIM10LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2614 * APB1LPENR1 TIM11LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2615 * APB1LPENR1 SPI2LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2616 * APB1LPENR1 SPI3LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2617 * APB1LPENR1 SPDIFRX1LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2618 * APB1LPENR1 USART2LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2619 * APB1LPENR1 USART3LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2620 * APB1LPENR1 UART4LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2621 * APB1LPENR1 UART5LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2622 * APB1LPENR1 I2C1LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2623 * APB1LPENR1 I2C2LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2624 * APB1LPENR1 I2C3LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2625 * APB1LPENR1 I3C1LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2626 * APB1LPENR1 I3C2LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2627 * APB1LPENR1 UART7LPEN LL_APB1_GRP1_IsEnabledClockLowPower\n
2628 * APB1LPENR1 UART8LPEN LL_APB1_GRP1_IsEnabledClockLowPower
2629 * @param Periphs This parameter can be a combination of the following values:
2630 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2631 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2632 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2633 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
2634 * @arg @ref LL_APB1_GRP1_PERIPH_I3C2
2635 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2636 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
2637 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2638 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2639 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2640 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2641 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2642 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2643 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2644 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2645 * @arg @ref LL_APB1_GRP1_PERIPH_TIM10
2646 * @arg @ref LL_APB1_GRP1_PERIPH_TIM11
2647 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2648 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2649 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2650 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2651 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2652 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2653 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2654 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2655 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2656 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
2657 * @retval uint32_t
2658 */
LL_APB1_GRP1_IsEnabledClockLowPower(uint32_t Periphs)2659 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
2660 {
2661 return ((READ_BIT(RCC->APB1LPENR1, Periphs) == Periphs) ? 1UL : 0UL);
2662 }
2663
2664 /**
2665 * @brief Disable APB1 peripherals clock during Low Power mode.
2666 * @rmtoll APB1LPENCR1 TIM2LPENC LL_APB1_GRP1_DisableClockLowPower\n
2667 * APB1LPENCR1 TIM3LPENC LL_APB1_GRP1_DisableClockLowPower\n
2668 * APB1LPENCR1 TIM4LPENC LL_APB1_GRP1_DisableClockLowPower\n
2669 * APB1LPENCR1 TIM5LPENC LL_APB1_GRP1_DisableClockLowPower\n
2670 * APB1LPENCR1 TIM6LPENC LL_APB1_GRP1_DisableClockLowPower\n
2671 * APB1LPENCR1 TIM7LPENC LL_APB1_GRP1_DisableClockLowPower\n
2672 * APB1LPENCR1 TIM12LPENC LL_APB1_GRP1_DisableClockLowPower\n
2673 * APB1LPENCR1 TIM13LPENC LL_APB1_GRP1_DisableClockLowPower\n
2674 * APB1LPENCR1 TIM14LPENC LL_APB1_GRP1_DisableClockLowPower\n
2675 * APB1LPENCR1 LPTIM1LPENC LL_APB1_GRP1_DisableClockLowPower\n
2676 * APB1LPENCR1 WWDGLPENC LL_APB1_GRP1_DisableClockLowPower\n
2677 * APB1LPENCR1 TIM10LPENC LL_APB1_GRP1_DisableClockLowPower\n
2678 * APB1LPENCR1 TIM11LPENC LL_APB1_GRP1_DisableClockLowPower\n
2679 * APB1LPENCR1 SPI2LPENC LL_APB1_GRP1_DisableClockLowPower\n
2680 * APB1LPENCR1 SPI3LPENC LL_APB1_GRP1_DisableClockLowPower\n
2681 * APB1LPENCR1 SPDIFRX1LPENC LL_APB1_GRP1_DisableClockLowPower\n
2682 * APB1LPENCR1 USART2LPENC LL_APB1_GRP1_DisableClockLowPower\n
2683 * APB1LPENCR1 USART3LPENC LL_APB1_GRP1_DisableClockLowPower\n
2684 * APB1LPENCR1 UART4LPENC LL_APB1_GRP1_DisableClockLowPower\n
2685 * APB1LPENCR1 UART5LPENC LL_APB1_GRP1_DisableClockLowPower\n
2686 * APB1LPENCR1 I2C1LPENC LL_APB1_GRP1_DisableClockLowPower\n
2687 * APB1LPENCR1 I2C2LPENC LL_APB1_GRP1_DisableClockLowPower\n
2688 * APB1LPENCR1 I2C3LPENC LL_APB1_GRP1_DisableClockLowPower\n
2689 * APB1LPENCR1 I3C1LPENC LL_APB1_GRP1_DisableClockLowPower\n
2690 * APB1LPENCR1 I3C2LPENC LL_APB1_GRP1_DisableClockLowPower\n
2691 * APB1LPENCR1 UART7LPENC LL_APB1_GRP1_DisableClockLowPower\n
2692 * APB1LPENCR1 UART8LPENC LL_APB1_GRP1_DisableClockLowPower
2693 * @param Periphs This parameter can be a combination of the following values:
2694 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2695 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2696 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2697 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
2698 * @arg @ref LL_APB1_GRP1_PERIPH_I3C2
2699 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2700 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
2701 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2702 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2703 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2704 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2705 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2706 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2707 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2708 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2709 * @arg @ref LL_APB1_GRP1_PERIPH_TIM10
2710 * @arg @ref LL_APB1_GRP1_PERIPH_TIM11
2711 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2712 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2713 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2714 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2715 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2716 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2717 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2718 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2719 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2720 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
2721 * @retval None
2722 */
LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)2723 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
2724 {
2725 WRITE_REG(RCC->APB1LPENCR1, Periphs);
2726 }
2727
2728 /**
2729 * @brief Enable APB1 peripherals clock.
2730 * @rmtoll APB1ENSR2 MDIOSENS LL_APB1_GRP2_EnableClock\n
2731 * APB1ENSR2 FDCANENS LL_APB1_GRP2_EnableClock\n
2732 * APB1ENSR2 UCPD1ENS LL_APB1_GRP2_EnableClock
2733 * @param Periphs This parameter can be a combination of the following values:
2734 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2735 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2736 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2737 * @retval None
2738 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)2739 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
2740 {
2741 __IO uint32_t tmpreg;
2742 WRITE_REG(RCC->APB1ENSR2, Periphs);
2743 /* Delay after an RCC peripheral clock enabling */
2744 tmpreg = READ_REG(RCC->APB1ENR2);
2745 (void)tmpreg;
2746 }
2747
2748 /**
2749 * @brief Check if APB1 peripheral clock is enabled or not
2750 * @rmtoll APB1ENR2 MDIOSEN LL_APB1_GRP2_IsEnabledClock\n
2751 * APB1ENR2 FDCANEN LL_APB1_GRP2_IsEnabledClock\n
2752 * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
2753 * @param Periphs This parameter can be a combination of the following values:
2754 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2755 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2756 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2757 * @retval uint32_t
2758 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)2759 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
2760 {
2761 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
2762 }
2763
2764 /**
2765 * @brief Disable APB1 peripherals clock.
2766 * @rmtoll APB1ENCR2 MDIOSENC LL_APB1_GRP2_DisableClock\n
2767 * APB1ENCR2 FDCANENC LL_APB1_GRP2_DisableClock\n
2768 * APB1ENCR2 UCPD1ENC LL_APB1_GRP2_DisableClock
2769 * @param Periphs This parameter can be a combination of the following values:
2770 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2771 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2772 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2773 * @retval None
2774 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)2775 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
2776 {
2777 WRITE_REG(RCC->APB1ENCR2, Periphs);
2778 }
2779
2780 /**
2781 * @brief Force APB1 peripherals reset.
2782 * @rmtoll APB1RSTSR2 MDIOSRSTS LL_APB1_GRP2_ForceReset\n
2783 * APB1RSTSR2 FDCANRSTS LL_APB1_GRP2_ForceReset\n
2784 * APB1RSTSR2 UCPD1RSTS LL_APB1_GRP2_ForceReset
2785 * @param Periphs This parameter can be a combination of the following values:
2786 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2787 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2788 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2789 * @retval None
2790 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)2791 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
2792 {
2793 WRITE_REG(RCC->APB1RSTSR2, Periphs);
2794 }
2795
2796 /**
2797 * @brief Release APB1 peripherals reset.
2798 * @rmtoll APB1RSTCR2 MDIOSRSTC LL_APB1_GRP2_ReleaseReset\n
2799 * APB1RSTCR2 FDCANRSTC LL_APB1_GRP2_ReleaseReset\n
2800 * APB1RSTCR2 UCPD1RSTC LL_APB1_GRP2_ReleaseReset
2801 * @param Periphs This parameter can be a combination of the following values:
2802 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2803 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2804 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2805 * @retval None
2806 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)2807 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
2808 {
2809 WRITE_REG(RCC->APB1RSTCR2, Periphs);
2810 }
2811
2812 /**
2813 * @brief Enable APB1 peripherals clock during Low Power mode.
2814 * @rmtoll APB1LPENSR2 MDIOSLPENS LL_APB1_GRP2_EnableClockLowPower\n
2815 * APB1LPENSR2 FDCANLPENS LL_APB1_GRP2_EnableClockLowPower\n
2816 * APB1LPENSR2 UCPD1LPENS LL_APB1_GRP2_EnableClockLowPower
2817 * @param Periphs This parameter can be a combination of the following values:
2818 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2819 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2820 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2821 * @retval None
2822 */
LL_APB1_GRP2_EnableClockLowPower(uint32_t Periphs)2823 __STATIC_INLINE void LL_APB1_GRP2_EnableClockLowPower(uint32_t Periphs)
2824 {
2825 __IO uint32_t tmpreg;
2826 WRITE_REG(RCC->APB1LPENSR2, Periphs);
2827 /* Delay after an RCC peripheral clock enabling */
2828 tmpreg = READ_REG(RCC->APB1LPENR2);
2829 (void)tmpreg;
2830 }
2831
2832 /**
2833 * @brief Check if APB1 peripheral clock during Low Power mode is enabled or not .
2834 * @rmtoll APB1LPENR2 MDIOSLPEN LL_APB1_GRP2_IsEnabledClockLowPower\n
2835 * APB1LPENR2 FDCANLPEN LL_APB1_GRP2_IsEnabledClockLowPower\n
2836 * APB1LPENR2 UCPD1LPEN LL_APB1_GRP2_IsEnabledClockLowPower
2837 * @param Periphs This parameter can be a combination of the following values:
2838 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2839 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2840 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2841 * @retval uint32_t
2842 */
LL_APB1_GRP2_IsEnabledClockLowPower(uint32_t Periphs)2843 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockLowPower(uint32_t Periphs)
2844 {
2845 return ((READ_BIT(RCC->APB1LPENR2, Periphs) == Periphs) ? 1UL : 0UL);
2846 }
2847
2848 /**
2849 * @brief Disable APB1 peripherals clock during Low Power mode.
2850 * @rmtoll APB1LPENCR2 MDIOSLPENC LL_APB1_GRP2_DisableClockLowPower\n
2851 * APB1LPENCR2 FDCANLPENC LL_APB1_GRP2_DisableClockLowPower\n
2852 * APB1LPENCR2 UCPD1LPENC LL_APB1_GRP2_DisableClockLowPower
2853 * @param Periphs This parameter can be a combination of the following values:
2854 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2855 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2856 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2857 * @retval None
2858 */
LL_APB1_GRP2_DisableClockLowPower(uint32_t Periphs)2859 __STATIC_INLINE void LL_APB1_GRP2_DisableClockLowPower(uint32_t Periphs)
2860 {
2861 WRITE_REG(RCC->APB1LPENCR2, Periphs);
2862 }
2863
2864 /**
2865 * @}
2866 */
2867
2868 /** @defgroup BUS_LL_EF_APB2 APB2
2869 * @{
2870 */
2871
2872 /**
2873 * @brief Enable APB2 peripherals clock.
2874 * @rmtoll APB2ENSR TIM1ENS LL_APB2_GRP1_EnableClock\n
2875 * APB2ENSR TIM8ENS LL_APB2_GRP1_EnableClock\n
2876 * APB2ENSR USART1ENS LL_APB2_GRP1_EnableClock\n
2877 * APB2ENSR USART6ENS LL_APB2_GRP1_EnableClock\n
2878 * APB2ENSR UART9ENS LL_APB2_GRP1_EnableClock\n
2879 * APB2ENSR USART10ENS LL_APB2_GRP1_EnableClock\n
2880 * APB2ENSR SPI1ENS LL_APB2_GRP1_EnableClock\n
2881 * APB2ENSR SPI4ENS LL_APB2_GRP1_EnableClock\n
2882 * APB2ENSR TIM18ENS LL_APB2_GRP1_EnableClock\n
2883 * APB2ENSR TIM15ENS LL_APB2_GRP1_EnableClock\n
2884 * APB2ENSR TIM16ENS LL_APB2_GRP1_EnableClock\n
2885 * APB2ENSR TIM17ENS LL_APB2_GRP1_EnableClock\n
2886 * APB2ENSR TIM9ENS LL_APB2_GRP1_EnableClock\n
2887 * APB2ENSR SPI5ENS LL_APB2_GRP1_EnableClock\n
2888 * APB2ENSR SAI1ENS LL_APB2_GRP1_EnableClock\n
2889 * APB2ENSR SAI2ENS LL_APB2_GRP1_EnableClock
2890 * @param Periphs This parameter can be a combination of the following values:
2891 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2892 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2893 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2894 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2895 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2896 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2897 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2898 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2899 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2900 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2901 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2902 * @arg @ref LL_APB2_GRP1_PERIPH_TIM18
2903 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2904 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2905 * @arg @ref LL_APB2_GRP1_PERIPH_UART9
2906 * @arg @ref LL_APB2_GRP1_PERIPH_USART10
2907 * @retval None
2908 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)2909 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
2910 {
2911 __IO uint32_t tmpreg;
2912 WRITE_REG(RCC->APB2ENSR, Periphs);
2913 /* Delay after an RCC peripheral clock enabling */
2914 tmpreg = READ_REG(RCC->APB2ENR);
2915 (void)tmpreg;
2916 }
2917
2918 /**
2919 * @brief Check if APB2 peripheral clock is enabled or not
2920 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
2921 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
2922 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
2923 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
2924 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n
2925 * APB2ENR USART10EN LL_APB2_GRP1_IsEnabledClock\n
2926 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
2927 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
2928 * APB2ENR TIM18EN LL_APB2_GRP1_IsEnabledClock\n
2929 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
2930 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
2931 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
2932 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
2933 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
2934 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
2935 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock
2936 * @param Periphs This parameter can be a combination of the following values:
2937 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2938 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2939 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2940 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2941 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2942 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2943 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2944 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2945 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2946 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2947 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2948 * @arg @ref LL_APB2_GRP1_PERIPH_TIM18
2949 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2950 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2951 * @arg @ref LL_APB2_GRP1_PERIPH_UART9
2952 * @arg @ref LL_APB2_GRP1_PERIPH_USART10
2953 * @retval uint32_t
2954 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)2955 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
2956 {
2957 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
2958 }
2959
2960 /**
2961 * @brief Disable APB2 peripherals clock.
2962 * @rmtoll APB2ENCR TIM1ENC LL_APB2_GRP1_DisableClock\n
2963 * APB2ENCR TIM8ENC LL_APB2_GRP1_DisableClock\n
2964 * APB2ENCR USART1ENC LL_APB2_GRP1_DisableClock\n
2965 * APB2ENCR USART6ENC LL_APB2_GRP1_DisableClock\n
2966 * APB2ENCR UART9ENC LL_APB2_GRP1_DisableClock\n
2967 * APB2ENCR USART10ENC LL_APB2_GRP1_DisableClock\n
2968 * APB2ENCR SPI1ENC LL_APB2_GRP1_DisableClock\n
2969 * APB2ENCR SPI4ENC LL_APB2_GRP1_DisableClock\n
2970 * APB2ENCR TIM18ENC LL_APB2_GRP1_DisableClock\n
2971 * APB2ENCR TIM15ENC LL_APB2_GRP1_DisableClock\n
2972 * APB2ENCR TIM16ENC LL_APB2_GRP1_DisableClock\n
2973 * APB2ENCR TIM17ENC LL_APB2_GRP1_DisableClock\n
2974 * APB2ENCR TIM9ENC LL_APB2_GRP1_DisableClock\n
2975 * APB2ENCR SPI5ENC LL_APB2_GRP1_DisableClock\n
2976 * APB2ENCR SAI1ENC LL_APB2_GRP1_DisableClock\n
2977 * APB2ENCR SAI2ENC LL_APB2_GRP1_DisableClock
2978 * @param Periphs This parameter can be a combination of the following values:
2979 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2980 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2981 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2982 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2983 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2984 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2985 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2986 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2987 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2988 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2989 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2990 * @arg @ref LL_APB2_GRP1_PERIPH_TIM18
2991 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2992 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2993 * @arg @ref LL_APB2_GRP1_PERIPH_UART9
2994 * @arg @ref LL_APB2_GRP1_PERIPH_USART10
2995 * @retval None
2996 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)2997 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
2998 {
2999 WRITE_REG(RCC->APB2ENCR, Periphs);
3000 }
3001
3002 /**
3003 * @brief Force APB2 peripherals reset.
3004 * @rmtoll APB2RSTSR TIM1RSTS LL_APB2_GRP1_ForceReset\n
3005 * APB2RSTSR TIM8RSTS LL_APB2_GRP1_ForceReset\n
3006 * APB2RSTSR USART1RSTS LL_APB2_GRP1_ForceReset\n
3007 * APB2RSTSR USART6RSTS LL_APB2_GRP1_ForceReset\n
3008 * APB2RSTSR UART9RSTS LL_APB2_GRP1_ForceReset\n
3009 * APB2RSTSR USART10RSTS LL_APB2_GRP1_ForceReset\n
3010 * APB2RSTSR SPI1RSTS LL_APB2_GRP1_ForceReset\n
3011 * APB2RSTSR SPI4RSTS LL_APB2_GRP1_ForceReset\n
3012 * APB2RSTSR TIM18RSTS LL_APB2_GRP1_ForceReset\n
3013 * APB2RSTSR TIM15RSTS LL_APB2_GRP1_ForceReset\n
3014 * APB2RSTSR TIM16RSTS LL_APB2_GRP1_ForceReset\n
3015 * APB2RSTSR TIM17RSTS LL_APB2_GRP1_ForceReset\n
3016 * APB2RSTSR TIM9RSTS LL_APB2_GRP1_ForceReset\n
3017 * APB2RSTSR SPI5RSTS LL_APB2_GRP1_ForceReset\n
3018 * APB2RSTSR SAI1RSTS LL_APB2_GRP1_ForceReset\n
3019 * APB2RSTSR SAI2RSTS LL_APB2_GRP1_ForceReset
3020 * @param Periphs This parameter can be a combination of the following values:
3021 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
3022 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
3023 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
3024 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
3025 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
3026 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
3027 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
3028 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
3029 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
3030 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
3031 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
3032 * @arg @ref LL_APB2_GRP1_PERIPH_TIM18
3033 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
3034 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
3035 * @arg @ref LL_APB2_GRP1_PERIPH_UART9
3036 * @arg @ref LL_APB2_GRP1_PERIPH_USART10
3037 * @retval None
3038 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)3039 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
3040 {
3041 WRITE_REG(RCC->APB2RSTSR, Periphs);
3042 }
3043
3044 /**
3045 * @brief Release APB2 peripherals reset.
3046 * @rmtoll APB2RSTCR TIM1RSTC LL_APB2_GRP1_ReleaseReset\n
3047 * APB2RSTCR TIM8RSTC LL_APB2_GRP1_ReleaseReset\n
3048 * APB2RSTCR USART1RSTC LL_APB2_GRP1_ReleaseReset\n
3049 * APB2RSTCR USART6RSTC LL_APB2_GRP1_ReleaseReset\n
3050 * APB2RSTCR UART9RSTC LL_APB2_GRP1_ReleaseReset\n
3051 * APB2RSTCR USART10RSTC LL_APB2_GRP1_ReleaseReset\n
3052 * APB2RSTCR SPI1RSTC LL_APB2_GRP1_ReleaseReset\n
3053 * APB2RSTCR SPI4RSTC LL_APB2_GRP1_ReleaseReset\n
3054 * APB2RSTCR TIM18RSTC LL_APB2_GRP1_ReleaseReset\n
3055 * APB2RSTCR TIM15RSTC LL_APB2_GRP1_ReleaseReset\n
3056 * APB2RSTCR TIM16RSTC LL_APB2_GRP1_ReleaseReset\n
3057 * APB2RSTCR TIM17RSTC LL_APB2_GRP1_ReleaseReset\n
3058 * APB2RSTCR TIM9RSTC LL_APB2_GRP1_ReleaseReset\n
3059 * APB2RSTCR SPI5RSTC LL_APB2_GRP1_ReleaseReset\n
3060 * APB2RSTCR SAI1RSTC LL_APB2_GRP1_ReleaseReset\n
3061 * APB2RSTCR SAI2RSTC LL_APB2_GRP1_ReleaseReset
3062 * @param Periphs This parameter can be a combination of the following values:
3063 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
3064 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
3065 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
3066 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
3067 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
3068 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
3069 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
3070 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
3071 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
3072 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
3073 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
3074 * @arg @ref LL_APB2_GRP1_PERIPH_TIM18
3075 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
3076 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
3077 * @arg @ref LL_APB2_GRP1_PERIPH_UART9
3078 * @arg @ref LL_APB2_GRP1_PERIPH_USART10
3079 * @retval None
3080 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)3081 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
3082 {
3083 WRITE_REG(RCC->APB2RSTCR, Periphs);
3084 }
3085
3086 /**
3087 * @brief Enable APB2 peripherals clock during Low Power mode.
3088 * @rmtoll APB2LPENSR TIM1LPENS LL_APB2_GRP1_EnableClockLowPower\n
3089 * APB2LPENSR TIM8LPENS LL_APB2_GRP1_EnableClockLowPower\n
3090 * APB2LPENSR USART1LPENS LL_APB2_GRP1_EnableClockLowPower\n
3091 * APB2LPENSR USART6LPENS LL_APB2_GRP1_EnableClockLowPower\n
3092 * APB2LPENSR UART9LPENS LL_APB2_GRP1_EnableClockLowPower\n
3093 * APB2LPENSR USART10LPENS LL_APB2_GRP1_EnableClockLowPower\n
3094 * APB2LPENSR SPI1LPENS LL_APB2_GRP1_EnableClockLowPower\n
3095 * APB2LPENSR SPI4LPENS LL_APB2_GRP1_EnableClockLowPower\n
3096 * APB2LPENSR TIM18LPENS LL_APB2_GRP1_EnableClockLowPower\n
3097 * APB2LPENSR TIM15LPENS LL_APB2_GRP1_EnableClockLowPower\n
3098 * APB2LPENSR TIM16LPENS LL_APB2_GRP1_EnableClockLowPower\n
3099 * APB2LPENSR TIM17LPENS LL_APB2_GRP1_EnableClockLowPower\n
3100 * APB2LPENSR TIM9LPENS LL_APB2_GRP1_EnableClockLowPower\n
3101 * APB2LPENSR SPI5LPENS LL_APB2_GRP1_EnableClockLowPower\n
3102 * APB2LPENSR SAI1LPENS LL_APB2_GRP1_EnableClockLowPower\n
3103 * APB2LPENSR SAI2LPENS LL_APB2_GRP1_EnableClockLowPower
3104 * @param Periphs This parameter can be a combination of the following values:
3105 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
3106 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
3107 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
3108 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
3109 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
3110 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
3111 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
3112 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
3113 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
3114 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
3115 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
3116 * @arg @ref LL_APB2_GRP1_PERIPH_TIM18
3117 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
3118 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
3119 * @arg @ref LL_APB2_GRP1_PERIPH_UART9
3120 * @arg @ref LL_APB2_GRP1_PERIPH_USART10
3121 * @retval None
3122 */
LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)3123 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
3124 {
3125 __IO uint32_t tmpreg;
3126 WRITE_REG(RCC->APB2LPENSR, Periphs);
3127 /* Delay after an RCC peripheral clock enabling */
3128 tmpreg = READ_REG(RCC->APB2LPENR);
3129 (void)tmpreg;
3130 }
3131
3132 /**
3133 * @brief Check if APB2 peripheral clock during Low Power mode is enabled or not .
3134 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3135 * APB2LPENR TIM8LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3136 * APB2LPENR USART1LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3137 * APB2LPENR USART6LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3138 * APB2LPENR UART9LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3139 * APB2LPENR USART10LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3140 * APB2LPENR SPI1LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3141 * APB2LPENR SPI4LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3142 * APB2LPENR TIM18LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3143 * APB2LPENR TIM15LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3144 * APB2LPENR TIM16LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3145 * APB2LPENR TIM17LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3146 * APB2LPENR TIM9LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3147 * APB2LPENR SPI5LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3148 * APB2LPENR SAI1LPEN LL_APB2_GRP1_IsEnabledClockLowPower\n
3149 * APB2LPENR SAI2LPEN LL_APB2_GRP1_IsEnabledClockLowPower
3150 * @param Periphs This parameter can be a combination of the following values:
3151 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
3152 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
3153 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
3154 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
3155 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
3156 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
3157 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
3158 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
3159 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
3160 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
3161 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
3162 * @arg @ref LL_APB2_GRP1_PERIPH_TIM18
3163 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
3164 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
3165 * @arg @ref LL_APB2_GRP1_PERIPH_UART9
3166 * @arg @ref LL_APB2_GRP1_PERIPH_USART10
3167 * @retval uint32_t
3168 */
LL_APB2_GRP1_IsEnabledClockLowPower(uint32_t Periphs)3169 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
3170 {
3171 return ((READ_BIT(RCC->APB2LPENR, Periphs) == Periphs) ? 1UL : 0UL);
3172 }
3173
3174 /**
3175 * @brief Disable APB2 peripherals clock during Low Power mode.
3176 * @rmtoll APB2LPENCR TIM1LPENC LL_APB2_GRP1_DisableClockLowPower\n
3177 * APB2LPENCR TIM8LPENC LL_APB2_GRP1_DisableClockLowPower\n
3178 * APB2LPENCR USART1LPENC LL_APB2_GRP1_DisableClockLowPower\n
3179 * APB2LPENCR USART6LPENC LL_APB2_GRP1_DisableClockLowPower\n
3180 * APB2LPENCR UART9LPENC LL_APB2_GRP1_DisableClockLowPower\n
3181 * APB2LPENCR USART10LPENC LL_APB2_GRP1_DisableClockLowPower\n
3182 * APB2LPENCR SPI1LPENC LL_APB2_GRP1_DisableClockLowPower\n
3183 * APB2LPENCR SPI4LPENC LL_APB2_GRP1_DisableClockLowPower\n
3184 * APB2LPENCR TIM18LPENC LL_APB2_GRP1_DisableClockLowPower\n
3185 * APB2LPENCR TIM15LPENC LL_APB2_GRP1_DisableClockLowPower\n
3186 * APB2LPENCR TIM16LPENC LL_APB2_GRP1_DisableClockLowPower\n
3187 * APB2LPENCR TIM17LPENC LL_APB2_GRP1_DisableClockLowPower\n
3188 * APB2LPENCR TIM9LPENC LL_APB2_GRP1_DisableClockLowPower\n
3189 * APB2LPENCR SPI5LPENC LL_APB2_GRP1_DisableClockLowPower\n
3190 * APB2LPENCR SAI1LPENC LL_APB2_GRP1_DisableClockLowPower\n
3191 * APB2LPENCR SAI2LPENC LL_APB2_GRP1_DisableClockLowPower
3192 * @param Periphs This parameter can be a combination of the following values:
3193 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
3194 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
3195 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
3196 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
3197 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
3198 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
3199 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
3200 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
3201 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
3202 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
3203 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
3204 * @arg @ref LL_APB2_GRP1_PERIPH_TIM18
3205 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
3206 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
3207 * @arg @ref LL_APB2_GRP1_PERIPH_UART9
3208 * @arg @ref LL_APB2_GRP1_PERIPH_USART10
3209 * @retval None
3210 */
LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)3211 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
3212 {
3213 WRITE_REG(RCC->APB2LPENCR, Periphs);
3214 }
3215
3216 /**
3217 * @}
3218 */
3219
3220 /** @defgroup BUS_LL_EF_APB4 APB4
3221 * @{
3222 */
3223
3224 /**
3225 * @brief Enable APB4 peripherals clock.
3226 * @rmtoll APB4ENSR1 HDPENS LL_APB4_GRP1_EnableClock\n
3227 * APB4ENSR1 LPUART1ENS LL_APB4_GRP1_EnableClock\n
3228 * APB4ENSR1 SPI6ENS LL_APB4_GRP1_EnableClock\n
3229 * APB4ENSR1 I2C4ENS LL_APB4_GRP1_EnableClock\n
3230 * APB4ENSR1 LPTIM2ENS LL_APB4_GRP1_EnableClock\n
3231 * APB4ENSR1 LPTIM3ENS LL_APB4_GRP1_EnableClock\n
3232 * APB4ENSR1 LPTIM4ENS LL_APB4_GRP1_EnableClock\n
3233 * APB4ENSR1 LPTIM5ENS LL_APB4_GRP1_EnableClock\n
3234 * APB4ENSR1 VREFBUFENS LL_APB4_GRP1_EnableClock\n
3235 * APB4ENSR1 RTCENS LL_APB4_GRP1_EnableClock\n
3236 * APB4ENSR1 RTCAPBENS LL_APB4_GRP1_EnableClock
3237 * @param Periphs This parameter can be a combination of the following values:
3238 * @arg @ref LL_APB4_GRP1_PERIPH_HDP
3239 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3240 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3241 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3242 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
3243 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
3244 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3245 * @arg @ref LL_APB4_GRP1_PERIPH_RTC
3246 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3247 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3248 * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
3249 * @retval None
3250 */
LL_APB4_GRP1_EnableClock(uint32_t Periphs)3251 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
3252 {
3253 __IO uint32_t tmpreg;
3254 WRITE_REG(RCC->APB4ENSR1, Periphs);
3255 /* Delay after an RCC peripheral clock enabling */
3256 tmpreg = READ_REG(RCC->APB4ENR1);
3257 (void)tmpreg;
3258 }
3259
3260 /**
3261 * @brief Check if APB4 peripheral clock is enabled or not
3262 * @rmtoll APB4ENR1 HDPEN LL_APB4_GRP1_IsEnabledClock\n
3263 * APB4ENR1 LPUART1EN LL_APB4_GRP1_IsEnabledClock\n
3264 * APB4ENR1 SPI6EN LL_APB4_GRP1_IsEnabledClock\n
3265 * APB4ENR1 I2C4EN LL_APB4_GRP1_IsEnabledClock\n
3266 * APB4ENR1 LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n
3267 * APB4ENR1 LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n
3268 * APB4ENR1 LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n
3269 * APB4ENR1 LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n
3270 * APB4ENR1 VREFBUFEN LL_APB4_GRP1_IsEnabledClock\n
3271 * APB4ENR1 RTCEN LL_APB4_GRP1_IsEnabledClock\n
3272 * APB4ENR1 RTCAPBEN LL_APB4_GRP1_IsEnabledClock
3273 * @param Periphs This parameter can be a combination of the following values:
3274 * @arg @ref LL_APB4_GRP1_PERIPH_HDP
3275 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3276 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3277 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3278 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
3279 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
3280 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3281 * @arg @ref LL_APB4_GRP1_PERIPH_RTC
3282 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3283 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3284 * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
3285 * @retval uint32_t
3286 */
LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)3287 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
3288 {
3289 return ((READ_BIT(RCC->APB4ENR1, Periphs) == Periphs) ? 1UL : 0UL);
3290 }
3291
3292 /**
3293 * @brief Disable APB4 peripherals clock.
3294 * @rmtoll APB4ENCR1 HDPENC LL_APB4_GRP1_DisableClock\n
3295 * APB4ENCR1 LPUART1ENC LL_APB4_GRP1_DisableClock\n
3296 * APB4ENCR1 SPI6ENC LL_APB4_GRP1_DisableClock\n
3297 * APB4ENCR1 I2C4ENC LL_APB4_GRP1_DisableClock\n
3298 * APB4ENCR1 LPTIM2ENC LL_APB4_GRP1_DisableClock\n
3299 * APB4ENCR1 LPTIM3ENC LL_APB4_GRP1_DisableClock\n
3300 * APB4ENCR1 LPTIM4ENC LL_APB4_GRP1_DisableClock\n
3301 * APB4ENCR1 LPTIM5ENC LL_APB4_GRP1_DisableClock\n
3302 * APB4ENCR1 VREFBUFENC LL_APB4_GRP1_DisableClock\n
3303 * APB4ENCR1 RTCENC LL_APB4_GRP1_DisableClock\n
3304 * APB4ENCR1 RTCAPBENC LL_APB4_GRP1_DisableClock
3305 * @param Periphs This parameter can be a combination of the following values:
3306 * @arg @ref LL_APB4_GRP1_PERIPH_HDP
3307 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3308 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3309 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3310 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
3311 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
3312 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3313 * @arg @ref LL_APB4_GRP1_PERIPH_RTC
3314 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3315 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3316 * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
3317 * @retval None
3318 */
LL_APB4_GRP1_DisableClock(uint32_t Periphs)3319 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
3320 {
3321 WRITE_REG(RCC->APB4ENCR1, Periphs);
3322 }
3323
3324 /**
3325 * @brief Force APB4 peripherals reset.
3326 * @rmtoll APB4RSTSR1 HDPRSTS LL_APB4_GRP1_ForceReset\n
3327 * APB4RSTSR1 LPUART1RSTS LL_APB4_GRP1_ForceReset\n
3328 * APB4RSTSR1 SPI6RSTS LL_APB4_GRP1_ForceReset\n
3329 * APB4RSTSR1 I2C4RSTS LL_APB4_GRP1_ForceReset\n
3330 * APB4RSTSR1 LPTIM2RSTS LL_APB4_GRP1_ForceReset\n
3331 * APB4RSTSR1 LPTIM3RSTS LL_APB4_GRP1_ForceReset\n
3332 * APB4RSTSR1 LPTIM4RSTS LL_APB4_GRP1_ForceReset\n
3333 * APB4RSTSR1 LPTIM5RSTS LL_APB4_GRP1_ForceReset\n
3334 * APB4RSTSR1 VREFBUFRSTS LL_APB4_GRP1_ForceReset\n
3335 * APB4RSTSR1 RTCAPBRSTS LL_APB4_GRP1_ForceReset
3336 * @param Periphs This parameter can be a combination of the following values:
3337 * @arg @ref LL_APB4_GRP1_PERIPH_HDP
3338 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3339 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3340 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3341 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
3342 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
3343 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3344 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3345 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3346 * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
3347 * @retval None
3348 */
LL_APB4_GRP1_ForceReset(uint32_t Periphs)3349 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
3350 {
3351 WRITE_REG(RCC->APB4RSTSR1, Periphs);
3352 }
3353
3354 /**
3355 * @brief Release APB4 peripherals reset.
3356 * @rmtoll APB4RSTCR1 HDPRSTC LL_APB4_GRP1_ReleaseReset\n
3357 * APB4RSTCR1 LPUART1RSTC LL_APB4_GRP1_ReleaseReset\n
3358 * APB4RSTCR1 SPI6RSTC LL_APB4_GRP1_ReleaseReset\n
3359 * APB4RSTCR1 I2C4RSTC LL_APB4_GRP1_ReleaseReset\n
3360 * APB4RSTCR1 LPTIM2RSTC LL_APB4_GRP1_ReleaseReset\n
3361 * APB4RSTCR1 LPTIM3RSTC LL_APB4_GRP1_ReleaseReset\n
3362 * APB4RSTCR1 LPTIM4RSTC LL_APB4_GRP1_ReleaseReset\n
3363 * APB4RSTCR1 LPTIM5RSTC LL_APB4_GRP1_ReleaseReset\n
3364 * APB4RSTCR1 VREFBUFRSTC LL_APB4_GRP1_ReleaseReset\n
3365 * APB4RSTCR1 RTCAPBRSTC LL_APB4_GRP1_ReleaseReset
3366 * @param Periphs This parameter can be a combination of the following values:
3367 * @arg @ref LL_APB4_GRP1_PERIPH_HDP
3368 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3369 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3370 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3371 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
3372 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
3373 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3374 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3375 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3376 * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
3377 * @retval None
3378 */
LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)3379 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
3380 {
3381 WRITE_REG(RCC->APB4RSTCR1, Periphs);
3382 }
3383
3384 /**
3385 * @brief Enable APB4 peripherals clock during Low Power mode.
3386 * @rmtoll APB4LPENSR1 HDPLPENS LL_APB4_GRP1_EnableClockLowPower\n
3387 * APB4LPENSR1 LPUART1LPENS LL_APB4_GRP1_EnableClockLowPower\n
3388 * APB4LPENSR1 SPI6LPENS LL_APB4_GRP1_EnableClockLowPower\n
3389 * APB4LPENSR1 I2C4LPENS LL_APB4_GRP1_EnableClockLowPower\n
3390 * APB4LPENSR1 LPTIM2LPENS LL_APB4_GRP1_EnableClockLowPower\n
3391 * APB4LPENSR1 LPTIM3LPENS LL_APB4_GRP1_EnableClockLowPower\n
3392 * APB4LPENSR1 LPTIM4LPENS LL_APB4_GRP1_EnableClockLowPower\n
3393 * APB4LPENSR1 LPTIM5LPENS LL_APB4_GRP1_EnableClockLowPower\n
3394 * APB4LPENSR1 VREFBUFLPENS LL_APB4_GRP1_EnableClockLowPower\n
3395 * APB4LPENSR1 RTCLPENS LL_APB4_GRP1_EnableClockLowPower\n
3396 * APB4LPENSR1 RTCAPBLPENS LL_APB4_GRP1_EnableClockLowPower
3397 * @param Periphs This parameter can be a combination of the following values:
3398 * @arg @ref LL_APB4_GRP1_PERIPH_HDP
3399 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3400 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3401 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3402 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
3403 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
3404 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3405 * @arg @ref LL_APB4_GRP1_PERIPH_RTC
3406 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3407 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3408 * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
3409 * @retval None
3410 */
LL_APB4_GRP1_EnableClockLowPower(uint32_t Periphs)3411 __STATIC_INLINE void LL_APB4_GRP1_EnableClockLowPower(uint32_t Periphs)
3412 {
3413 __IO uint32_t tmpreg;
3414 WRITE_REG(RCC->APB4LPENSR1, Periphs);
3415 /* Delay after an RCC peripheral clock enabling */
3416 tmpreg = READ_REG(RCC->APB4LPENR1);
3417 (void)tmpreg;
3418 }
3419
3420 /**
3421 * @brief Check if APB4 peripheral clock during Low Power mode is enabled or not .
3422 * @rmtoll APB4LPENR1 HDPLPEN LL_APB4_GRP1_IsEnabledClockLowPower\n
3423 * APB4LPENR1 LPUART1LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n
3424 * APB4LPENR1 SPI6LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n
3425 * APB4LPENR1 I2C4LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n
3426 * APB4LPENR1 LPTIM2LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n
3427 * APB4LPENR1 LPTIM3LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n
3428 * APB4LPENR1 LPTIM4LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n
3429 * APB4LPENR1 LPTIM5LPEN LL_APB4_GRP1_IsEnabledClockLowPower\n
3430 * APB4LPENR1 VREFBUFLPEN LL_APB4_GRP1_IsEnabledClockLowPower\n
3431 * APB4LPENR1 RTCLPEN LL_APB4_GRP1_IsEnabledClockLowPower\n
3432 * APB4LPENR1 RTCAPBLPEN LL_APB4_GRP1_IsEnabledClockLowPower
3433 * @param Periphs This parameter can be a combination of the following values:
3434 * @arg @ref LL_APB4_GRP1_PERIPH_HDP
3435 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3436 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3437 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3438 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
3439 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
3440 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3441 * @arg @ref LL_APB4_GRP1_PERIPH_RTC
3442 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3443 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3444 * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
3445 * @retval uint32_t
3446 */
LL_APB4_GRP1_IsEnabledClockLowPower(uint32_t Periphs)3447 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
3448 {
3449 return ((READ_BIT(RCC->APB4LPENR1, Periphs) == Periphs) ? 1UL : 0UL);
3450 }
3451
3452 /**
3453 * @brief Disable APB4 peripherals clock during Low Power mode.
3454 * @rmtoll APB4LPENCR1 HDPLPENC LL_APB4_GRP1_DisableClockLowPower\n
3455 * APB4LPENCR1 LPUART1LPENC LL_APB4_GRP1_DisableClockLowPower\n
3456 * APB4LPENCR1 SPI6LPENC LL_APB4_GRP1_DisableClockLowPower\n
3457 * APB4LPENCR1 I2C4LPENC LL_APB4_GRP1_DisableClockLowPower\n
3458 * APB4LPENCR1 LPTIM2LPENC LL_APB4_GRP1_DisableClockLowPower\n
3459 * APB4LPENCR1 LPTIM3LPENC LL_APB4_GRP1_DisableClockLowPower\n
3460 * APB4LPENCR1 LPTIM4LPENC LL_APB4_GRP1_DisableClockLowPower\n
3461 * APB4LPENCR1 LPTIM5LPENC LL_APB4_GRP1_DisableClockLowPower\n
3462 * APB4LPENCR1 VREFBUFLPENC LL_APB4_GRP1_DisableClockLowPower\n
3463 * APB4LPENCR1 RTCLPENC LL_APB4_GRP1_DisableClockLowPower\n
3464 * APB4LPENCR1 RTCAPBLPENC LL_APB4_GRP1_DisableClockLowPower
3465 * @param Periphs This parameter can be a combination of the following values:
3466 * @arg @ref LL_APB4_GRP1_PERIPH_HDP
3467 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3468 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3469 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3470 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
3471 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
3472 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3473 * @arg @ref LL_APB4_GRP1_PERIPH_RTC
3474 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3475 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3476 * @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
3477 * @retval None
3478 */
LL_APB4_GRP1_DisableClockLowPower(uint32_t Periphs)3479 __STATIC_INLINE void LL_APB4_GRP1_DisableClockLowPower(uint32_t Periphs)
3480 {
3481 WRITE_REG(RCC->APB4LPENCR1, Periphs);
3482 }
3483
3484 /**
3485 * @brief Enable APB4 peripherals clock.
3486 * @rmtoll APB4ENSR2 SYSCFGENS LL_APB4_GRP2_EnableClock\n
3487 * APB4ENSR2 BSECENS LL_APB4_GRP2_EnableClock\n
3488 * APB4ENSR2 DTSENS LL_APB4_GRP2_EnableClock
3489 * @param Periphs This parameter can be a combination of the following values:
3490 * @arg @ref LL_APB4_GRP2_PERIPH_BSEC
3491 * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
3492 * @arg @ref LL_APB4_GRP2_PERIPH_DTS
3493 * @retval None
3494 */
LL_APB4_GRP2_EnableClock(uint32_t Periphs)3495 __STATIC_INLINE void LL_APB4_GRP2_EnableClock(uint32_t Periphs)
3496 {
3497 __IO uint32_t tmpreg;
3498 WRITE_REG(RCC->APB4ENSR2, Periphs);
3499 /* Delay after an RCC peripheral clock enabling */
3500 tmpreg = READ_REG(RCC->APB4ENR2);
3501 (void)tmpreg;
3502 }
3503
3504 /**
3505 * @brief Check if APB4 peripheral clock is enabled or not
3506 * @rmtoll APB4ENR2 SYSCFGEN LL_APB4_GRP2_IsEnabledClock\n
3507 * APB4ENR2 BSECEN LL_APB4_GRP2_IsEnabledClock\n
3508 * APB4ENR2 DTSEN LL_APB4_GRP2_IsEnabledClock
3509 * @param Periphs This parameter can be a combination of the following values:
3510 * @arg @ref LL_APB4_GRP2_PERIPH_BSEC
3511 * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
3512 * @arg @ref LL_APB4_GRP2_PERIPH_DTS
3513 * @retval uint32_t
3514 */
LL_APB4_GRP2_IsEnabledClock(uint32_t Periphs)3515 __STATIC_INLINE uint32_t LL_APB4_GRP2_IsEnabledClock(uint32_t Periphs)
3516 {
3517 return ((READ_BIT(RCC->APB4ENR2, Periphs) == Periphs) ? 1UL : 0UL);
3518 }
3519
3520 /**
3521 * @brief Disable APB4 peripherals clock.
3522 * @rmtoll APB4ENCR2 SYSCFGENC LL_APB4_GRP2_DisableClock\n
3523 * APB4ENCR2 BSECENC LL_APB4_GRP2_DisableClock\n
3524 * APB4ENCR2 DTSENC LL_APB4_GRP2_DisableClock
3525 * @param Periphs This parameter can be a combination of the following values:
3526 * @arg @ref LL_APB4_GRP2_PERIPH_BSEC
3527 * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
3528 * @arg @ref LL_APB4_GRP2_PERIPH_DTS
3529 * @retval None
3530 */
LL_APB4_GRP2_DisableClock(uint32_t Periphs)3531 __STATIC_INLINE void LL_APB4_GRP2_DisableClock(uint32_t Periphs)
3532 {
3533 WRITE_REG(RCC->APB4ENCR2, Periphs);
3534 }
3535
3536 /**
3537 * @brief Force APB4 peripherals reset.
3538 * @rmtoll APB4RSTR2 SYSCFGRSTS LL_APB4_GRP2_ForceReset\n
3539 * APB4RSTR2 DTSRSTS LL_APB4_GRP2_ForceReset
3540 * @param Periphs This parameter can be a combination of the following values:
3541 * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
3542 * @arg @ref LL_APB4_GRP2_PERIPH_DTS
3543 * @retval None
3544 */
LL_APB4_GRP2_ForceReset(uint32_t Periphs)3545 __STATIC_INLINE void LL_APB4_GRP2_ForceReset(uint32_t Periphs)
3546 {
3547 WRITE_REG(RCC->APB4RSTSR2, Periphs);
3548 }
3549
3550 /**
3551 * @brief Release APB4 peripherals reset.
3552 * @rmtoll APB4RSTCR2 SYSCFGRSTC LL_APB4_GRP2_ReleaseReset\n
3553 * APB4RSTCR2 DTSRSTC LL_APB4_GRP2_ReleaseReset
3554 * @param Periphs This parameter can be a combination of the following values:
3555 * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
3556 * @arg @ref LL_APB4_GRP2_PERIPH_DTS
3557 * @retval None
3558 */
LL_APB4_GRP2_ReleaseReset(uint32_t Periphs)3559 __STATIC_INLINE void LL_APB4_GRP2_ReleaseReset(uint32_t Periphs)
3560 {
3561 WRITE_REG(RCC->APB4RSTCR2, Periphs);
3562 }
3563
3564 /**
3565 * @brief Enable APB4 peripherals clock during Low Power mode.
3566 * @rmtoll APB4LPENSR2 SYSCFGLPENS LL_APB4_GRP2_EnableClockLowPower\n
3567 * APB4LPENSR2 BSECLPENS LL_APB4_GRP2_EnableClockLowPower\n
3568 * APB4LPENSR2 DTSLPENS LL_APB4_GRP2_EnableClockLowPower
3569 * @param Periphs This parameter can be a combination of the following values:
3570 * @arg @ref LL_APB4_GRP2_PERIPH_BSEC
3571 * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
3572 * @arg @ref LL_APB4_GRP2_PERIPH_DTS
3573 * @retval None
3574 */
LL_APB4_GRP2_EnableClockLowPower(uint32_t Periphs)3575 __STATIC_INLINE void LL_APB4_GRP2_EnableClockLowPower(uint32_t Periphs)
3576 {
3577 __IO uint32_t tmpreg;
3578 WRITE_REG(RCC->APB4LPENSR2, Periphs);
3579 /* Delay after an RCC peripheral clock enabling */
3580 tmpreg = READ_REG(RCC->APB4LPENR2);
3581 (void)tmpreg;
3582 }
3583
3584 /**
3585 * @brief Check if APB4 peripheral clock during Low Power mode is enabled or not .
3586 * @rmtoll APB4LPENR2 SYSCFGLPEN LL_APB4_GRP2_IsEnabledClockLowPower\n
3587 * APB4LPENR2 BSECLPEN LL_APB4_GRP2_IsEnabledClockLowPower\n
3588 * APB4LPENR2 DTSLPEN LL_APB4_GRP2_IsEnabledClockLowPower
3589 * @param Periphs This parameter can be a combination of the following values:
3590 * @arg @ref LL_APB4_GRP2_PERIPH_BSEC
3591 * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
3592 * @arg @ref LL_APB4_GRP2_PERIPH_DTS
3593 * @retval uint32_t
3594 */
LL_APB4_GRP2_IsEnabledClockLowPower(uint32_t Periphs)3595 __STATIC_INLINE uint32_t LL_APB4_GRP2_IsEnabledClockLowPower(uint32_t Periphs)
3596 {
3597 return ((READ_BIT(RCC->APB4LPENR2, Periphs) == Periphs) ? 1UL : 0UL);
3598 }
3599
3600 /**
3601 * @brief Disable APB4 peripherals clock during Low Power mode.
3602 * @rmtoll APB4LPENCR2 SYSCFGLPENC LL_APB4_GRP2_DisableClockLowPower\n
3603 * APB4LPENCR2 BSECLPENC LL_APB4_GRP2_DisableClockLowPower\n
3604 * APB4LPENCR2 DTSLPENC LL_APB4_GRP2_DisableClockLowPower
3605 * @param Periphs This parameter can be a combination of the following values:
3606 * @arg @ref LL_APB4_GRP2_PERIPH_BSEC
3607 * @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
3608 * @arg @ref LL_APB4_GRP2_PERIPH_DTS
3609 * @retval None
3610 */
LL_APB4_GRP2_DisableClockLowPower(uint32_t Periphs)3611 __STATIC_INLINE void LL_APB4_GRP2_DisableClockLowPower(uint32_t Periphs)
3612 {
3613 WRITE_REG(RCC->APB4LPENCR2, Periphs);
3614 }
3615
3616 /**
3617 * @}
3618 */
3619
3620 /** @defgroup BUS_LL_EF_APB5 APB5
3621 * @{
3622 */
3623
3624 /**
3625 * @brief Enable APB5 peripherals clock.
3626 * @rmtoll APB5ENSR LTDCENS LL_APB5_GRP1_EnableClock\n
3627 * APB5ENSR DCMIPPENS LL_APB5_GRP1_EnableClock\n
3628 * APB5ENSR GFXTIMENS LL_APB5_GRP1_EnableClock\n
3629 * APB5ENSR VENCENS LL_APB5_GRP1_EnableClock\n (*)
3630 * APB5ENSR CSIENS LL_APB5_GRP1_EnableClock
3631 * @param Periphs This parameter can be a combination of the following values:
3632 * @arg @ref LL_APB5_GRP1_PERIPH_CSI
3633 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
3634 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
3635 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC
3636 * @arg @ref LL_APB5_GRP1_PERIPH_VENC
3637 * @retval None
3638 */
LL_APB5_GRP1_EnableClock(uint32_t Periphs)3639 __STATIC_INLINE void LL_APB5_GRP1_EnableClock(uint32_t Periphs)
3640 {
3641 __IO uint32_t tmpreg;
3642 WRITE_REG(RCC->APB5ENSR, Periphs);
3643 /* Delay after an RCC peripheral clock enabling */
3644 tmpreg = READ_REG(RCC->APB5ENR);
3645 (void)tmpreg;
3646 }
3647
3648 /**
3649 * @brief Check if APB5 peripheral clock is enabled or not
3650 * @rmtoll APB5ENR LTDCEN LL_APB5_GRP1_IsEnabledClock\n
3651 * APB5ENR DCMIPPEN LL_APB5_GRP1_IsEnabledClock\n
3652 * APB5ENR GFXTIMEN LL_APB5_GRP1_IsEnabledClock\n
3653 * APB5ENR VENCEN LL_APB5_GRP1_IsEnabledClock\n (*)
3654 * APB5ENR CSIEN LL_APB5_GRP1_IsEnabledClock
3655 * @param Periphs This parameter can be a combination of the following values:
3656 * @arg @ref LL_APB5_GRP1_PERIPH_CSI
3657 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
3658 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
3659 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC
3660 * @arg @ref LL_APB5_GRP1_PERIPH_VENC
3661 * @retval uint32_t
3662 */
LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs)3663 __STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs)
3664 {
3665 return ((READ_BIT(RCC->APB5ENR, Periphs) == Periphs) ? 1UL : 0UL);
3666 }
3667
3668 /**
3669 * @brief Disable APB5 peripherals clock.
3670 * @rmtoll APB5ENCR LTDCENC LL_APB5_GRP1_DisableClock\n
3671 * APB5ENCR DCMIPPENC LL_APB5_GRP1_DisableClock\n
3672 * APB5ENCR GFXTIMENC LL_APB5_GRP1_DisableClock\n
3673 * APB5ENCR VENCENC LL_APB5_GRP1_DisableClock\n (*)
3674 * APB5ENCR CSIENC LL_APB5_GRP1_DisableClock
3675 * @param Periphs This parameter can be a combination of the following values:
3676 * @arg @ref LL_APB5_GRP1_PERIPH_CSI
3677 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
3678 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
3679 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC
3680 * @arg @ref LL_APB5_GRP1_PERIPH_VENC
3681 * @retval None
3682 */
LL_APB5_GRP1_DisableClock(uint32_t Periphs)3683 __STATIC_INLINE void LL_APB5_GRP1_DisableClock(uint32_t Periphs)
3684 {
3685 WRITE_REG(RCC->APB5ENCR, Periphs);
3686 }
3687
3688 /**
3689 * @brief Force APB5 peripherals reset.
3690 * @rmtoll APB5RSTSR LTDCRSTS LL_APB5_GRP1_ForceReset\n
3691 * APB5RSTSR DCMIPPRSTS LL_APB5_GRP1_ForceReset\n
3692 * APB5RSTSR GFXTIMRSTS LL_APB5_GRP1_ForceReset\n
3693 * APB5RSTSR VENCRSTS LL_APB5_GRP1_ForceReset\n (*)
3694 * APB5RSTSR CSIRSTS LL_APB5_GRP1_ForceReset
3695 * @param Periphs This parameter can be a combination of the following values:
3696 * @arg @ref LL_APB5_GRP1_PERIPH_CSI
3697 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
3698 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
3699 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC
3700 * @arg @ref LL_APB5_GRP1_PERIPH_VENC
3701 * @retval None
3702 */
LL_APB5_GRP1_ForceReset(uint32_t Periphs)3703 __STATIC_INLINE void LL_APB5_GRP1_ForceReset(uint32_t Periphs)
3704 {
3705 WRITE_REG(RCC->APB5RSTSR, Periphs);
3706 }
3707
3708 /**
3709 * @brief Release APB5 peripherals reset.
3710 * @rmtoll APB5RSTCR LTDCRSTC LL_APB5_GRP1_ReleaseReset\n
3711 * APB5RSTCR DCMIPPRSTC LL_APB5_GRP1_ReleaseReset\n
3712 * APB5RSTCR GFXTIMRSTC LL_APB5_GRP1_ReleaseReset\n
3713 * APB5RSTCR VENCRSTC LL_APB5_GRP1_ReleaseReset\n (*)
3714 * APB5RSTCR CSIRSTC LL_APB5_GRP1_ReleaseReset
3715 * @param Periphs This parameter can be a combination of the following values:
3716 * @arg @ref LL_APB5_GRP1_PERIPH_CSI
3717 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
3718 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
3719 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC
3720 * @arg @ref LL_APB5_GRP1_PERIPH_VENC
3721 * @retval None
3722 */
LL_APB5_GRP1_ReleaseReset(uint32_t Periphs)3723 __STATIC_INLINE void LL_APB5_GRP1_ReleaseReset(uint32_t Periphs)
3724 {
3725 WRITE_REG(RCC->APB5RSTCR, Periphs);
3726 }
3727
3728 /**
3729 * @brief Enable APB5 peripherals clock during Low Power mode.
3730 * @rmtoll APB5LPENSR LTDCLPENS LL_APB5_GRP1_EnableClockLowPower\n
3731 * APB5LPENSR DCMIPPLPENS LL_APB5_GRP1_EnableClockLowPower\n
3732 * APB5LPENSR GFXTIMLPENS LL_APB5_GRP1_EnableClockLowPower\n
3733 * APB5LPENSR VENCLPENS LL_APB5_GRP1_EnableClockLowPower\n (*)
3734 * APB5LPENSR CSILPENS LL_APB5_GRP1_EnableClockLowPower
3735 * @param Periphs This parameter can be a combination of the following values:
3736 * @arg @ref LL_APB5_GRP1_PERIPH_CSI
3737 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
3738 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
3739 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC
3740 * @arg @ref LL_APB5_GRP1_PERIPH_VENC
3741 * @retval None
3742 */
LL_APB5_GRP1_EnableClockLowPower(uint32_t Periphs)3743 __STATIC_INLINE void LL_APB5_GRP1_EnableClockLowPower(uint32_t Periphs)
3744 {
3745 __IO uint32_t tmpreg;
3746 WRITE_REG(RCC->APB5LPENSR, Periphs);
3747 /* Delay after an RCC peripheral clock enabling */
3748 tmpreg = READ_REG(RCC->APB5LPENR);
3749 (void)tmpreg;
3750 }
3751
3752 /**
3753 * @brief Check if APB5 peripheral clock during Low Power mode is enabled or not .
3754 * @rmtoll APB5LPENR LTDCLPEN LL_APB5_GRP1_IsEnabledClockLowPower\n
3755 * APB5LPENR DCMIPPLPEN LL_APB5_GRP1_IsEnabledClockLowPower\n
3756 * APB5LPENR GFXTIMLPEN LL_APB5_GRP1_IsEnabledClockLowPower\n
3757 * APB5LPENR VENCLPEN LL_APB5_GRP1_IsEnabledClockLowPower\n (*)
3758 * APB5LPENR CSILPEN LL_APB5_GRP1_IsEnabledClockLowPower
3759 * @param Periphs This parameter can be a combination of the following values:
3760 * @arg @ref LL_APB5_GRP1_PERIPH_CSI
3761 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
3762 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
3763 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC
3764 * @arg @ref LL_APB5_GRP1_PERIPH_VENC
3765 * @retval uint32_t
3766 */
LL_APB5_GRP1_IsEnabledClockLowPower(uint32_t Periphs)3767 __STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
3768 {
3769 return ((READ_BIT(RCC->APB5LPENR, Periphs) == Periphs) ? 1UL : 0UL);
3770 }
3771
3772 /**
3773 * @brief Disable APB5 peripherals clock during Low Power mode.
3774 * @rmtoll APB5LPENCR LTDCLPENC LL_APB5_GRP1_DisableClockLowPower\n
3775 * APB5LPENCR DCMIPPLPENC LL_APB5_GRP1_DisableClockLowPower\n
3776 * APB5LPENCR GFXTIMLPENC LL_APB5_GRP1_DisableClockLowPower\n
3777 * APB5LPENCR VENCLPENC LL_APB5_GRP1_DisableClockLowPower\n (*)
3778 * APB5LPENCR CSILPENC LL_APB5_GRP1_DisableClockLowPower
3779 * @param Periphs This parameter can be a combination of the following values:
3780 * @arg @ref LL_APB5_GRP1_PERIPH_CSI
3781 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
3782 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
3783 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC
3784 * @arg @ref LL_APB5_GRP1_PERIPH_VENC
3785 * @retval None
3786 */
LL_APB5_GRP1_DisableClockLowPower(uint32_t Periphs)3787 __STATIC_INLINE void LL_APB5_GRP1_DisableClockLowPower(uint32_t Periphs)
3788 {
3789 WRITE_REG(RCC->APB5LPENCR, Periphs);
3790 }
3791
3792 /**
3793 * @}
3794 */
3795
3796 /** @defgroup BUS_LL_EF_MISC MISC
3797 * @{
3798 */
3799
3800 /**
3801 * @brief Enable miscellaneous clock.
3802 * @rmtoll MISCENSR DBGENS LL_MISC_EnableClock\n
3803 * MISCENSR MCO1ENS LL_MISC_EnableClock\n
3804 * MISCENSR MCO2ENS LL_MISC_EnableClock\n
3805 * MISCENSR XSPIPHYCOMPENS LL_MISC_EnableClock\n
3806 * MISCENSR PERENS LL_MISC_EnableClock
3807 * @param Misc This parameter can be a combination of the following values:
3808 * @arg @ref LL_DBG
3809 * @arg @ref LL_MCO1
3810 * @arg @ref LL_MCO2
3811 * @arg @ref LL_XSPIPHYCOMP
3812 * @arg @ref LL_PER
3813 * @retval None
3814 */
LL_MISC_EnableClock(uint32_t Misc)3815 __STATIC_INLINE void LL_MISC_EnableClock(uint32_t Misc)
3816 {
3817 __IO uint32_t tmpreg;
3818 WRITE_REG(RCC->MISCENSR, Misc);
3819 /* Delay after an RCC miscellaneous clock enabling */
3820 tmpreg = READ_REG(RCC->MISCENR);
3821 (void)tmpreg;
3822 }
3823
3824 /**
3825 * @brief Check if miscellaneous clock is enabled or not
3826 * @rmtoll MISCENR DBGEN LL_MISC_IsEnabledClock\n
3827 * MISCENR MCO1EN LL_MISC_IsEnabledClock\n
3828 * MISCENR MCO2EN LL_MISC_IsEnabledClock\n
3829 * MISCENR XSPIPHYCOMPEN LL_MISC_IsEnabledClock\n
3830 * MISCENR PEREN LL_MISC_IsEnabledClock
3831 * @param Misc This parameter can be a combination of the following values:
3832 * @arg @ref LL_DBG
3833 * @arg @ref LL_MCO1
3834 * @arg @ref LL_MCO2
3835 * @arg @ref LL_XSPIPHYCOMP
3836 * @arg @ref LL_PER
3837 * @retval uint32_t
3838 */
LL_MISC_IsEnabledClock(uint32_t Misc)3839 __STATIC_INLINE uint32_t LL_MISC_IsEnabledClock(uint32_t Misc)
3840 {
3841 return ((READ_BIT(RCC->MISCENR, Misc) == Misc) ? 1UL : 0UL);
3842 }
3843
3844 /**
3845 * @brief Disable miscellaneous clock.
3846 * @rmtoll MISCENCR DBGENC LL_MISC_DisableClock\n
3847 * MISCENCR MCO1ENC LL_MISC_DisableClock\n
3848 * MISCENCR MCO2ENC LL_MISC_DisableClock\n
3849 * MISCENCR XSPIPHYCOMPENC LL_MISC_DisableClock\n
3850 * MISCENCR PERENC LL_MISC_DisableClock
3851 * @param Misc This parameter can be a combination of the following values:
3852 * @arg @ref LL_DBG
3853 * @arg @ref LL_MCO1
3854 * @arg @ref LL_MCO2
3855 * @arg @ref LL_XSPIPHYCOMP
3856 * @arg @ref LL_PER
3857 * @retval None
3858 */
LL_MISC_DisableClock(uint32_t Misc)3859 __STATIC_INLINE void LL_MISC_DisableClock(uint32_t Misc)
3860 {
3861 WRITE_REG(RCC->MISCENCR, Misc);
3862 }
3863
3864 /**
3865 * @brief Force miscellaneous reset.
3866 * @rmtoll MISCRSTSR DBGRSTS LL_MISC_ForceReset\n
3867 * MISCRSTSR XSPIPHY1RSTS LL_MISC_ForceReset\n
3868 * MISCRSTSR XSPIPHY2RSTS LL_MISC_ForceReset\n
3869 * MISCRSTSR SDMMC1DLLRSTS LL_MISC_ForceReset\n
3870 * MISCRSTSR SDMMC2DLLRSTS LL_MISC_ForceReset
3871 * @param Misc This parameter can be a combination of the following values:
3872 * @arg @ref LL_DBG
3873 * @arg @ref LL_XSPIPHY1
3874 * @arg @ref LL_XSPIPHY2
3875 * @arg @ref LL_SDMMC1DLL
3876 * @arg @ref LL_SDMMC2DLL
3877 * @retval None
3878 */
LL_MISC_ForceReset(uint32_t Misc)3879 __STATIC_INLINE void LL_MISC_ForceReset(uint32_t Misc)
3880 {
3881 WRITE_REG(RCC->MISCRSTSR, Misc);
3882 }
3883
3884 /**
3885 * @brief Release miscellaneous reset.
3886 * @rmtoll MISCRSTCR DBGRSTC LL_MISC_ReleaseReset\n
3887 * MISCRSTCR XSPIPHY1RSTC LL_MISC_ReleaseReset\n
3888 * MISCRSTCR XSPIPHY2RSTC LL_MISC_ReleaseReset\n
3889 * MISCRSTCR SDMMC1DLLRSTC LL_MISC_ReleaseReset\n
3890 * MISCRSTCR SDMMC2DLLRSTC LL_MISC_ReleaseReset
3891 * @param Misc This parameter can be a combination of the following values:
3892 * @arg @ref LL_DBG
3893 * @arg @ref LL_XSPIPHY1
3894 * @arg @ref LL_XSPIPHY2
3895 * @arg @ref LL_SDMMC1DLL
3896 * @arg @ref LL_SDMMC2DLL
3897 * @retval None
3898 */
LL_MISC_ReleaseReset(uint32_t Misc)3899 __STATIC_INLINE void LL_MISC_ReleaseReset(uint32_t Misc)
3900 {
3901 WRITE_REG(RCC->MISCRSTCR, Misc);
3902 }
3903
3904 /**
3905 * @brief Enable bus clock during Low Power mode.
3906 * @rmtoll MISCLPENSR DBGLPENS LL_MISC_EnableClockLowPower\n
3907 * MISCLPENSR XSPIPHYCOMPLPENS LL_MISC_EnableClockLowPower\n
3908 * MISCLPENSR PERLPENS LL_MISC_EnableClockLowPower
3909 * @param Misc This parameter can be a combination of the following values:
3910 * @arg @ref LL_DBG
3911 * @arg @ref LL_XSPIPHYCOMP
3912 * @arg @ref LL_PER
3913 * @retval None
3914 */
LL_MISC_EnableClockLowPower(uint32_t Misc)3915 __STATIC_INLINE void LL_MISC_EnableClockLowPower(uint32_t Misc)
3916 {
3917 __IO uint32_t tmpreg;
3918 WRITE_REG(RCC->MISCLPENSR, Misc);
3919 /* Delay after an RCC miscellaneous clock enabling */
3920 tmpreg = READ_REG(RCC->MISCLPENR);
3921 (void)tmpreg;
3922 }
3923
3924 /**
3925 * @brief Disable bus clock during Low Power mode.
3926 * @rmtoll MISCLPENCR DBGLPENC LL_MISC_DisableClockLowPower\n
3927 * MISCLPENCR XSPIPHYCOMPLPENC LL_MISC_DisableClockLowPower\n
3928 * MISCLPENCR PERLPENC LL_MISC_DisableClockLowPower
3929 * @param Misc This parameter can be a combination of the following values:
3930 * @arg @ref LL_DBG
3931 * @arg @ref LL_XSPIPHYCOMP
3932 * @arg @ref LL_PER
3933 * @retval None
3934 */
LL_MISC_DisableClockLowPower(uint32_t Misc)3935 __STATIC_INLINE void LL_MISC_DisableClockLowPower(uint32_t Misc)
3936 {
3937 WRITE_REG(RCC->MISCLPENCR, Misc);
3938 }
3939
3940 /**
3941 * @}
3942 */
3943
3944 /**
3945 * @}
3946 */
3947
3948 /**
3949 * @}
3950 */
3951
3952 #endif /* defined(RCC) */
3953
3954 /**
3955 * @}
3956 */
3957
3958 #ifdef __cplusplus
3959 }
3960 #endif
3961
3962 #endif /* STM32N6xx_LL_BUS_H */
3963
