1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB , APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB , APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2023 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file
30 * in the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32H5xx_LL_BUS_H
38 #define __STM32H5xx_LL_BUS_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32h5xx.h"
46
47 /** @addtogroup STM32H5xx_LL_Driver
48 * @{
49 */
50
51 #if defined(RCC)
52
53 /** @defgroup BUS_LL BUS
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private constants ---------------------------------------------------------*/
60 /* Private macros ------------------------------------------------------------*/
61
62 /* Exported types ------------------------------------------------------------*/
63 /* Exported constants --------------------------------------------------------*/
64 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
65 * @{
66 */
67
68 /** @defgroup BUS_LL_AHB_BRANCH_CLK_AHBx BRANCH CLK AHBx
69 * @{
70 */
71 #define LL_AHB_BRANCH_CLK_AHB1 RCC_CFGR2_AHB1DIS
72 #define LL_AHB_BRANCH_CLK_AHB2 RCC_CFGR2_AHB2DIS
73 #if defined(AHB4PERIPH_BASE)
74 #define LL_AHB_BRANCH_CLK_AHB4 RCC_CFGR2_AHB4DIS
75 #endif /* AHB4PERIPH_BASE */
76 /**
77 * @}
78 */
79
80 /** @defgroup BUS_LL_APB_BRANCH_CLK_APBx BRANCH CLK APBx
81 * @{
82 */
83 #define LL_APB_BRANCH_CLK_APB1 RCC_CFGR2_APB1DIS
84 #define LL_APB_BRANCH_CLK_APB2 RCC_CFGR2_APB2DIS
85 #define LL_APB_BRANCH_CLK_APB3 RCC_CFGR2_APB3DIS
86 /**
87 * @}
88 */
89
90 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
91 * @{
92 */
93 #if defined(CORDIC)
94 #define LL_AHB1_GRP1_PERIPH_ALL 0xF13AD103U
95 #elif defined(DCACHE)
96 #define LL_AHB1_GRP1_PERIPH_ALL 0xF1021103U
97 #else
98 #define LL_AHB1_GRP1_PERIPH_ALL 0x91021103U
99 #endif /* CORDIC */
100 #define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN
101 #define LL_AHB1_GRP1_PERIPH_GPDMA2 RCC_AHB1ENR_GPDMA2EN
102 #if defined(CORDIC)
103 #define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
104 #endif /* CORDIC */
105 #if defined(FMAC)
106 #define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
107 #endif /* FMAC */
108 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLITFEN
109 #if defined(ETH)
110 #define LL_AHB1_GRP1_PERIPH_ETH RCC_AHB1ENR_ETHEN
111 #define LL_AHB1_GRP1_PERIPH_ETHTX RCC_AHB1ENR_ETHTXEN
112 #define LL_AHB1_GRP1_PERIPH_ETHRX RCC_AHB1ENR_ETHRXEN
113 #endif /* ETH */
114 #if defined(RCC_AHB1ENR_ETHCKEN)
115 #define LL_AHB1_GRP1_PERIPH_ETHINTERN RCC_AHB1ENR_ETHCKEN
116 #endif /* RCC_AHB1ENR_ETHCKEN */
117 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
118 #define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN
119 #define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_TZSC1EN
120 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPRAMEN
121 #define LL_AHB1_GRP1_PERIPH_ICACHE RCC_AHB1LPENR_ICACHELPEN
122 #if defined(DCACHE1)
123 #define LL_AHB1_GRP1_PERIPH_DCACHE1 RCC_AHB1ENR_DCACHE1EN
124 #endif /* DCACHE1 */
125 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN
126 /**
127 * @}
128 */
129
130 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
131 * @{
132 */
133 #if defined(GPIOI)
134 #define LL_AHB2_GRP1_PERIPH_ALL 0xC01F1DFFU
135 #elif defined(GPIOE)
136 #define LL_AHB2_GRP1_PERIPH_ALL 0xC01F1CFFU
137 #else
138 #define LL_AHB2_GRP1_PERIPH_ALL 0x40060C8FU
139 #endif /* GPIOE */
140 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
141 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
142 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
143 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
144 #if defined(GPIOE)
145 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
146 #endif /* GPIOE */
147 #if defined(GPIOF)
148 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
149 #endif /* GPIOF */
150 #if defined(GPIOG)
151 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
152 #endif /* GPIOG */
153 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
154 #if defined(GPIOI)
155 #define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN
156 #endif /* GPIOI */
157 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
158 #define LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN
159 #if defined(DCMI)
160 #define LL_AHB2_GRP1_PERIPH_DCMI_PSSI RCC_AHB2ENR_DCMI_PSSIEN
161 #endif /* DCMI */
162 #if defined(AES)
163 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
164 #endif /* AES */
165 #if defined(HASH)
166 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
167 #endif /* HASH */
168 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
169 #if defined(PKA)
170 #define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN
171 #endif /* PKA */
172 #if defined(SAES)
173 #define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR_SAESEN
174 #endif /* SAES */
175 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR_SRAM2EN
176 #if defined(SRAM3_BASE)
177 #define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2ENR_SRAM3EN
178 #endif /* SRAM3_BASE */
179 /**
180 * @}
181 */
182 #if defined(AHB4PERIPH_BASE)
183 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH
184 * @{
185 */
186 #define LL_AHB4_GRP1_PERIPH_ALL 0x00111880U
187 #define LL_AHB4_GRP1_PERIPH_OTFDEC RCC_AHB4ENR_OTFDEC1EN
188 #define LL_AHB4_GRP1_PERIPH_SDMMC1 RCC_AHB4ENR_SDMMC1EN
189 #if defined(SDMMC2)
190 #define LL_AHB4_GRP1_PERIPH_SDMMC2 RCC_AHB4ENR_SDMMC2EN
191 #endif /* SDMMC2*/
192 #define LL_AHB4_GRP1_PERIPH_FMC RCC_AHB4ENR_FMCEN
193 #define LL_AHB4_GRP1_PERIPH_OSPI1 RCC_AHB4ENR_OCTOSPI1EN
194 /**
195 * @}
196 */
197 #endif /* AHB4PERIPH_BASE */
198
199 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
200 * @{
201 */
202 #if defined(USART11)
203 #define LL_APB1_GRP1_PERIPH_ALL 0xDFFEC9FFU
204 #elif defined(USART6)
205 #define LL_APB1_GRP1_PERIPH_ALL 0x13FEC87FU
206 #else
207 #define LL_APB1_GRP1_PERIPH_ALL 0x01E7E833U
208 #endif /* TIM4 */
209 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN
210 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN
211 #if defined(TIM4)
212 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN
213 #endif /* TIM4*/
214 #if defined(TIM5)
215 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN
216 #endif /* TIM5*/
217 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN
218 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN
219 #if defined(TIM12)
220 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN
221 #endif /* TIM12*/
222 #if defined(TIM13)
223 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN
224 #endif /* TIM13*/
225 #if defined(TIM14)
226 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN
227 #endif /* TIM14*/
228 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1LENR_WWDGEN
229 #if defined(OPAMP1)
230 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1LENR_OPAMPEN
231 #endif /* OPAMP1 */
232 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN
233 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN
234 #if defined(COMP1)
235 #define LL_APB1_GRP1_PERIPH_COMP RCC_APB1LENR_COMPEN
236 #endif /* COMP1 */
237 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN
238 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN
239 #if defined(UART4)
240 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN
241 #endif /* UART4*/
242 #if defined(UART5)
243 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN
244 #endif /* UART5*/
245 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN
246 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN
247 #define LL_APB1_GRP1_PERIPH_I3C1 RCC_APB1LENR_I3C1EN
248 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1LENR_CRSEN
249 #if defined(USART6)
250 #define LL_APB1_GRP1_PERIPH_USART6 RCC_APB1LENR_USART6EN
251 #endif /* USART6*/
252 #if defined(USART10)
253 #define LL_APB1_GRP1_PERIPH_USART10 RCC_APB1LENR_USART10EN
254 #endif /* USART10*/
255 #if defined(USART11)
256 #define LL_APB1_GRP1_PERIPH_USART11 RCC_APB1LENR_USART11EN
257 #endif /* USART11*/
258 #if defined(CEC)
259 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN
260 #endif /* CEC*/
261 #if defined(UART7)
262 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN
263 #endif /* UART7 */
264 #if defined(UART8)
265 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN
266 #endif /* UART8 */
267 /**
268 * @}
269 */
270
271
272 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
273 * @{
274 */
275 #if defined(UART9)
276 #define LL_APB1_GRP2_PERIPH_ALL 0x0080022BU
277 #else
278 #define LL_APB1_GRP2_PERIPH_ALL 0x00000228U
279 #endif /* UART9 */
280 #if defined(UART9)
281 #define LL_APB1_GRP2_PERIPH_UART9 RCC_APB1HENR_UART9EN
282 #endif /* UART9 */
283 #if defined(UART12)
284 #define LL_APB1_GRP2_PERIPH_UART12 RCC_APB1HENR_UART12EN
285 #endif /* UART12*/
286 #define LL_APB1_GRP2_PERIPH_DTS RCC_APB1HENR_DTSEN
287 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1HENR_LPTIM2EN
288 #define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN
289 #if defined(UCPD1)
290 #define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1HENR_UCPD1EN
291 #endif /* UCPD1 */
292 /**
293 * @}
294 */
295
296 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
297 * @{
298 */
299 #if defined(TIM16)
300 #define LL_APB2_GRP1_PERIPH_ALL 0x017F7800U
301 #elif defined(TIM8)
302 #define LL_APB2_GRP1_PERIPH_ALL 0x01097800U
303 #else
304 #define LL_APB2_GRP1_PERIPH_ALL 0x01005800U
305 #endif /* TIM8 */
306 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
307 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
308 #if defined(TIM8)
309 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
310 #endif /* TIM8 */
311 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
312 #if defined(TIM15)
313 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
314 #endif /* TIM15 */
315 #if defined(TIM16)
316 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
317 #endif /* TIM16 */
318 #if defined(TIM17)
319 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
320 #endif /* TIM17 */
321 #if defined(SPI4)
322 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
323 #endif /* SPI4 */
324 #if defined(SPI6)
325 #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
326 #endif /* SPI6 */
327 #if defined(SAI1)
328 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
329 #endif /* SAI1 */
330 #if defined(SAI2)
331 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
332 #endif /* SAI2 */
333 #if defined(USB_DRD_FS)
334 #define LL_APB2_GRP1_PERIPH_USB RCC_APB2ENR_USBEN
335 #endif /* USB_DRD_FS */
336 /**
337 * @}
338 */
339
340 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
341 * @{
342 */
343 #if defined(SPI5)
344 #define LL_APB3_GRP1_PERIPH_ALL 0x0030F9E2U
345 #elif defined(I2C4)
346 #define LL_APB3_GRP1_PERIPH_ALL 0x00300AC2U
347 #else
348 #define LL_APB3_GRP1_PERIPH_ALL 0x00200A42U
349 #endif /* SPI5 */
350 #define LL_APB3_GRP1_PERIPH_SBS RCC_APB3ENR_SBSEN
351 #if defined(SPI5)
352 #define LL_APB3_GRP1_PERIPH_SPI5 RCC_APB3ENR_SPI5EN
353 #endif /* SPI5 */
354 #define LL_APB3_GRP1_PERIPH_LPUART1 RCC_APB3ENR_LPUART1EN
355 #if defined(I2C3)
356 #define LL_APB3_GRP1_PERIPH_I2C3 RCC_APB3ENR_I2C3EN
357 #endif /* I2C3 */
358 #if defined(I2C4)
359 #define LL_APB3_GRP1_PERIPH_I2C4 RCC_APB3ENR_I2C4EN
360 #endif /* I2C4 */
361 #if defined(I3C2)
362 #define LL_APB3_GRP1_PERIPH_I3C2 RCC_APB3ENR_I3C2EN
363 #endif /* I3C2 */
364 #define LL_APB3_GRP1_PERIPH_LPTIM1 RCC_APB3ENR_LPTIM1EN
365 #if defined(LPTIM3)
366 #define LL_APB3_GRP1_PERIPH_LPTIM3 RCC_APB3ENR_LPTIM3EN
367 #endif /* LPTIM3 */
368 #if defined(LPTIM4)
369 #define LL_APB3_GRP1_PERIPH_LPTIM4 RCC_APB3ENR_LPTIM4EN
370 #endif /* LPTIM4 */
371 #if defined(LPTIM5)
372 #define LL_APB3_GRP1_PERIPH_LPTIM5 RCC_APB3ENR_LPTIM5EN
373 #endif /* LPTIM5 */
374 #if defined(LPTIM6)
375 #define LL_APB3_GRP1_PERIPH_LPTIM6 RCC_APB3ENR_LPTIM6EN
376 #endif /* LPTIM6 */
377 #define LL_APB3_GRP1_PERIPH_VREF RCC_APB3ENR_VREFEN
378 #define LL_APB3_GRP1_PERIPH_RTCAPB RCC_APB3ENR_RTCAPBEN
379 /**
380 * @}
381 */
382
383 /**
384 * @}
385 */
386
387 /* Exported macro ------------------------------------------------------------*/
388 /* Exported functions --------------------------------------------------------*/
389 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
390 * @{
391 */
392
393 /** @defgroup BUS_LL_EF_AHBx AHBx Branch
394 * @{
395 */
396 /**
397 * @brief Disable of AHBx Clock Branch
398 * @rmtoll CFGR2 AHB1DIS LL_AHB_DisableClock\n
399 * CFGR2 AHB2DIS LL_AHB_DisableClock\n
400 * CFGR2 AHB4DIS LL_AHB_DisableClock
401 * @param AHBx This parameter can be a combination of the following values:
402 * @arg @ref LL_AHB_BRANCH_CLK_AHB1
403 * @arg @ref LL_AHB_BRANCH_CLK_AHB2
404 * @arg @ref LL_AHB_BRANCH_CLK_AHB4 (*)
405 *
406 * (*) : Not available for all stm32h5xxxx family lines.
407 * @retval None
408 */
LL_AHB_DisableClock(uint32_t AHBx)409 __STATIC_INLINE void LL_AHB_DisableClock(uint32_t AHBx)
410 {
411 SET_BIT(RCC->CFGR2, AHBx);
412 }
413
414 /**
415 * @brief Enable of AHBx Clock Branch
416 * @rmtoll CFGR2 AHB1DIS LL_AHB_EnableClock\n
417 * CFGR2 AHB2DIS LL_AHB_EnableClock\n
418 * CFGR2 AHB4DIS LL_AHB_EnableClock
419 * @param AHBx This parameter can be a combination of the following values:
420 * @arg @ref LL_AHB_BRANCH_CLK_AHB1
421 * @arg @ref LL_AHB_BRANCH_CLK_AHB2
422 * @arg @ref LL_AHB_BRANCH_CLK_AHB4 (*)
423 *
424 * (*) : Not available for all stm32h5xxxx family lines.
425 * @retval None
426 */
LL_AHB_EnableClock(uint32_t AHBx)427 __STATIC_INLINE void LL_AHB_EnableClock(uint32_t AHBx)
428 {
429 __IO uint32_t tmpreg;
430 CLEAR_BIT(RCC->CFGR2, AHBx);
431 /* Delay after AHBx clock branch enabling */
432 tmpreg = READ_BIT(RCC->CFGR2, AHBx);
433 (void)tmpreg;
434 }
435
436 /**
437 * @brief Check if AHBx clock branch is disabled or not
438 * @rmtoll CFGR2 AHB1DIS LL_AHB_IsDisabledClock\n
439 * CFGR2 AHB2DIS LL_AHB_IsDisabledClock\n
440 * CFGR2 AHB4DIS LL_AHB_IsDisabledClock
441 * @param AHBx This parameter can be a combination of the following values:
442 * @arg @ref LL_AHB_BRANCH_CLK_AHB1
443 * @arg @ref LL_AHB_BRANCH_CLK_AHB2
444 * @arg @ref LL_AHB_BRANCH_CLK_AHB4 (*)
445 *
446 * (*) : Not available for all stm32h5xxxx family lines.
447 * @retval State of AHBx bus (1 or 0).
448 */
LL_AHB_IsDisabledClock(uint32_t AHBx)449 __STATIC_INLINE uint32_t LL_AHB_IsDisabledClock(uint32_t AHBx)
450 {
451 return ((READ_BIT(RCC->CFGR2, AHBx) == AHBx) ? 1UL : 0UL);
452 }
453
454 /**
455 * @}
456 */
457
458 /** @defgroup BUS_LL_EF_APBx APBx Branch
459 * @{
460 */
461 /**
462 * @brief Disable APBx Clock Branch
463 * @rmtoll CFGR2 APB1DIS LL_APB_DisableClock\n
464 * CFGR2 APB2DIS LL_APB_DisableClock\n
465 * CFGR2 APB3DIS LL_APB_DisableClock
466 * @param APBx This parameter can be a combination of the following values:
467 * @arg @ref LL_APB_BRANCH_CLK_APB1
468 * @arg @ref LL_APB_BRANCH_CLK_APB2
469 * @arg @ref LL_APB_BRANCH_CLK_APB3
470 * @retval None
471 */
LL_APB_DisableClock(uint32_t APBx)472 __STATIC_INLINE void LL_APB_DisableClock(uint32_t APBx)
473 {
474 SET_BIT(RCC->CFGR2, APBx);
475 }
476
477 /**
478 * @brief Enable of APBx Clock Branch
479 * @rmtoll CFGR2 APB1DIS LL_APB_EnableClock\n
480 * CFGR2 APB2DIS LL_APB_EnableClock\n
481 * CFGR2 APB3DIS LL_APB_EnableClock
482 * @param APBx This parameter can be a combination of the following values:
483 * @arg @ref LL_APB_BRANCH_CLK_APB1
484 * @arg @ref LL_APB_BRANCH_CLK_APB2
485 * @arg @ref LL_APB_BRANCH_CLK_APB3
486 * @retval None
487 */
LL_APB_EnableClock(uint32_t APBx)488 __STATIC_INLINE void LL_APB_EnableClock(uint32_t APBx)
489 {
490 __IO uint32_t tmpreg;
491 CLEAR_BIT(RCC->CFGR2, APBx);
492 /* Delay after APBx clock branch enabling */
493 tmpreg = READ_BIT(RCC->CFGR2, APBx);
494 (void)tmpreg;
495 }
496
497 /**
498 * @brief Check if APBx clock branch is disabled or not
499 * @rmtoll CFGR2 APB1DIS LL_APB_IsDisabledClock\n
500 * CFGR2 APB2DIS LL_APB_IsDisabledClock\n
501 * CFGR2 APB3DIS LL_APB_IsDisabledClock
502 * @param APBx This parameter can be a combination of the following values:
503 * @arg @ref LL_APB_BRANCH_CLK_APB1
504 * @arg @ref LL_APB_BRANCH_CLK_APB2
505 * @arg @ref LL_APB_BRANCH_CLK_APB3
506 * @retval State of APBx bus (1 or 0).
507 */
LL_APB_IsDisabledClock(uint32_t APBx)508 __STATIC_INLINE uint32_t LL_APB_IsDisabledClock(uint32_t APBx)
509 {
510 return ((READ_BIT(RCC->CFGR2, APBx) == APBx) ? 1UL : 0UL);
511 }
512
513 /**
514 * @}
515 */
516
517 /**
518 * @}
519 */
520
521 /** @defgroup BUS_LL_EF_AHB1 AHB1 Peripherals
522 * @{
523 */
524 /**
525 * @brief Enable AHB1 peripherals clock.
526 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n
527 * AHB1ENR GPDMA2EN LL_AHB1_GRP1_EnableClock\n
528 * AHB1ENR FLITFEN LL_AHB1_GRP1_EnableClock\n
529 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
530 * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n
531 * AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n
532 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n
533 * AHB1ENR ETHEN LL_AHB1_GRP1_EnableClock\n
534 * AHB1ENR ETHTXEN LL_AHB1_GRP1_EnableClock\n
535 * AHB1ENR ETHRXEN LL_AHB1_GRP1_EnableClock\n
536 * AHB1ENR TZSC1EN LL_AHB1_GRP1_EnableClock\n
537 * AHB1ENR BKPRAMEN LL_AHB1_GRP1_EnableClock\n
538 * AHB1ENR DCACHE1EN LL_AHB1_GRP1_EnableClock\n
539 * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock
540 * @param Periphs This parameter can be a combination of the following values:
541 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
542 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
543 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
544 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
545 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
546 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
547 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
548 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
549 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
550 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
551 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
552 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
553 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
554 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*)
555 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
556 *
557 * (*) : Not available for all stm32h5xxxx family lines.
558 * @retval None
559 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)560 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
561 {
562 __IO uint32_t tmpreg;
563 SET_BIT(RCC->AHB1ENR, Periphs);
564 /* Delay after an RCC peripheral clock enabling */
565 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
566 (void)tmpreg;
567 }
568
569 /**
570 * @brief Check if AHB1 peripheral clock is enabled or not
571 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n
572 * AHB1ENR GPDMA2EN LL_AHB1_GRP1_IsEnabledClock\n
573 * AHB1ENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
574 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
575 * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n
576 * AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n
577 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n
578 * AHB1ENR ETHEN LL_AHB1_GRP1_IsEnabledClock\n
579 * AHB1ENR ETHTXEN LL_AHB1_GRP1_IsEnabledClock\n
580 * AHB1ENR ETHRXEN LL_AHB1_GRP1_IsEnabledClock\n
581 * AHB1ENR TZSC1EN LL_AHB1_GRP1_IsEnabledClock\n
582 * AHB1ENR BKPRAMEN LL_AHB1_GRP1_IsEnabledClock\n
583 * AHB1ENR DCACHE1EN LL_AHB1_GRP1_IsEnabledClock\n
584 * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock
585 * @param Periphs This parameter can be a combination of the following values:
586 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
587 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
588 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
589 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
590 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
591 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
592 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
593 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
594 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
595 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
596 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
597 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
598 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
599 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*)
600 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
601 *
602 * (*) : Not available for all stm32h5xxxx family lines.
603 * @retval State of Periphs (1 or 0).
604 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)605 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
606 {
607 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
608 }
609
610 /**
611 * @brief Disable AHB1 peripherals clock.
612 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n
613 * AHB1ENR GPDMA2EN LL_AHB1_GRP1_DisableClock\n
614 * AHB1ENR FLITFEN LL_AHB1_GRP1_DisableClock\n
615 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
616 * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n
617 * AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n
618 * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n
619 * AHB1ENR ETHEN LL_AHB1_GRP1_DisableClock\n
620 * AHB1ENR ETHTXEN LL_AHB1_GRP1_DisableClock\n
621 * AHB1ENR ETHRXEN LL_AHB1_GRP1_DisableClock\n
622 * AHB1ENR TZSC1EN LL_AHB1_GRP1_DisableClock\n
623 * AHB1ENR BKPRAMEN LL_AHB1_GRP1_DisableClock\n
624 * AHB1ENR DCACHE1EN LL_AHB1_GRP1_DisableClock\n
625 * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock
626 * @param Periphs This parameter can be a combination of the following values:
627 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
628 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
629 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
630 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
631 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
632 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
633 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
634 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
635 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
636 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
637 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
638 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
639 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
640 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*)
641 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
642 *
643 * (*) : Not available for all stm32h5xxxx family lines.
644 * @retval None
645 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)646 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
647 {
648 CLEAR_BIT(RCC->AHB1ENR, Periphs);
649 }
650
651 /**
652 * @brief Force AHB1 peripherals reset.
653 * @rmtoll AHB1RSTR GPDMA1RST LL_AHB1_GRP1_ForceReset\n
654 * AHB1RSTR GPDMA2RST LL_AHB1_GRP1_ForceReset\n
655 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
656 * AHB1RSTR CORDICRST LL_AHB1_GRP1_ForceReset\n
657 * AHB1RSTR FMACRST LL_AHB1_GRP1_ForceReset\n
658 * AHB1RSTR RAMCFGRST LL_AHB1_GRP1_ForceReset\n
659 * AHB1RSTR ETHRST LL_AHB1_GRP1_ForceReset\n
660 * AHB1RSTR TZSC1RST LL_AHB1_GRP1_ForceReset
661 * @param Periphs This parameter can be a combination of the following values:
662 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
663 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
664 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
665 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
666 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
667 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
668 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
669 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
670 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
671 *
672 * (*) : Not available for all stm32h5xxxx family lines.
673 * @retval None
674 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)675 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
676 {
677 SET_BIT(RCC->AHB1RSTR, Periphs);
678 }
679
680 /**
681 * @brief Release AHB1 peripherals reset.
682 * @rmtoll AHB1RSTR GPDMA1RST LL_AHB1_GRP1_ReleaseReset\n
683 * AHB1RSTR GPDMA2RST LL_AHB1_GRP1_ReleaseReset\n
684 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
685 * AHB1RSTR CORDICRST LL_AHB1_GRP1_ReleaseReset\n
686 * AHB1RSTR FMACRST LL_AHB1_GRP1_ReleaseReset\n
687 * AHB1RSTR RAMCFGRST LL_AHB1_GRP1_ReleaseReset\n
688 * AHB1RSTR ETHRST LL_AHB1_GRP1_ReleaseReset\n
689 * AHB1RSTR TZSC1RST LL_AHB1_GRP1_ReleaseReset
690 * @param Periphs This parameter can be a combination of the following values:
691 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
692 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
693 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
694 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
695 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
696 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
697 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
698 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
699 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
700 *
701 * (*) : Not available for all stm32h5xxxx family lines.
702 * @retval None
703 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)704 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
705 {
706 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
707 }
708
709 /**
710 * @brief Enable AHB1 peripheral clocks in Sleep mode
711 * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
712 * AHB1LPENR GPDMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
713 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockSleep\n
714 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n
715 * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_EnableClockSleep\n
716 * AHB1LPENR FMACLPEN LL_AHB1_GRP1_EnableClockSleep\n
717 * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_EnableClockSleep\n
718 * AHB1LPENR ETHLPEN LL_AHB1_GRP1_EnableClockSleep\n
719 * AHB1LPENR ETHTXLPEN LL_AHB1_GRP1_EnableClockSleep\n
720 * AHB1LPENR ETHRXLPEN LL_AHB1_GRP1_EnableClockSleep\n
721 * AHB1LPENR TZSC1LPEN LL_AHB1_GRP1_EnableClockSleep\n
722 * AHB1LPENR BKPRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n
723 * AHB1LPENR DCACHE1LPEN LL_AHB1_GRP1_EnableClockSleep\n
724 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockSleep
725 * @param Periphs This parameter can be a combination of the following values:
726 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
727 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
728 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
729 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
730 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
731 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
732 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
733 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
734 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
735 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
736 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
737 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
738 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
739 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*)
740 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
741 *
742 * (*) : Not available for all stm32h5xxxx family lines.
743 * @retval None
744 */
LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)745 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
746 {
747 __IO uint32_t tmpreg;
748 SET_BIT(RCC->AHB1LPENR, Periphs);
749 /* Delay after an RCC peripheral clock enabling */
750 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
751 (void)tmpreg;
752 }
753
754 /**
755 * @brief Check if AHB1 peripheral clocks in Sleep mode is enabled or not
756 * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
757 * AHB1LPENR GPDMA2LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
758 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
759 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
760 * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
761 * AHB1LPENR FMACLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
762 * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
763 * AHB1LPENR ETHLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
764 * AHB1LPENR ETHTXLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
765 * AHB1LPENR ETHRXLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
766 * AHB1LPENR TZSC1LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
767 * AHB1LPENR BKPRAMLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
768 * AHB1LPENR DCACHE1LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n
769 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_IsEnabledClockSleep
770 * @param Periphs This parameter can be a combination of the following values:
771 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
772 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
773 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
774 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
775 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
776 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
777 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
778 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
779 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
780 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
781 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
782 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
783 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
784 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*)
785 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
786 *
787 * (*) : Not available for all stm32h5xxxx family lines.
788 * @retval State of Periphs (1 or 0).
789 */
LL_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)790 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)
791 {
792 return ((READ_BIT(RCC->AHB1LPENR, Periphs) == Periphs) ? 1UL : 0UL);
793 }
794
795 /**
796 * @brief Disable AHB1 peripheral clocks in Sleep mode
797 * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
798 * AHB1LPENR GPDMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
799 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockSleep\n
800 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n
801 * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_DisableClockSleep\n
802 * AHB1LPENR FMACLPEN LL_AHB1_GRP1_DisableClockSleep\n
803 * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_DisableClockSleep\n
804 * AHB1LPENR ETHLPEN LL_AHB1_GRP1_DisableClockSleep\n
805 * AHB1LPENR ETHTXLPEN LL_AHB1_GRP1_DisableClockSleep\n
806 * AHB1LPENR ETHRXLPEN LL_AHB1_GRP1_DisableClockSleep\n
807 * AHB1LPENR TZSC1LPEN LL_AHB1_GRP1_DisableClockSleep\n
808 * AHB1LPENR BKPRAMLPEN LL_AHB1_GRP1_DisableClockSleep\n
809 * AHB1LPENR DCACHE1LPEN LL_AHB1_GRP1_DisableClockSleep\n
810 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockSleep
811 * @param Periphs This parameter can be a combination of the following values:
812 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
813 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
814 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2
815 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
816 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
817 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*)
818 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*)
819 * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
820 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*)
821 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*)
822 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*)
823 * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
824 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
825 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*)
826 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
827 *
828 * (*) : Not available for all stm32h5xxxx family lines.
829 * @retval None
830 */
LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)831 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
832 {
833 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
834 }
835
836 /**
837 * @}
838 */
839
840 /** @defgroup BUS_LL_EF_AHB2 AHB2 Peripherals
841 * @{
842 */
843 /**
844 * @brief Enable AHB2 peripherals clock.
845 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
846 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
847 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
848 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
849 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
850 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
851 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
852 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
853 * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n
854 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
855 * AHB2ENR DAC1EN LL_AHB2_GRP1_EnableClock\n
856 * AHB2ENR DCMI_PSSIEN LL_AHB2_GRP1_EnableClock\n
857 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
858 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
859 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
860 * AHB2ENR PKAEN LL_AHB2_GRP1_EnableClock\n
861 * AHB2ENR SAESEN LL_AHB2_GRP1_EnableClock\n
862 * AHB2ENR SRAM2EN LL_AHB2_GRP1_EnableClock\n
863 * AHB2ENR SRAM3EN LL_AHB2_GRP1_EnableClock
864 * @param Periphs This parameter can be a combination of the following values:
865 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
866 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
867 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
868 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
869 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
870 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
871 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
872 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
873 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
874 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
875 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
876 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
877 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
878 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
879 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
880 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
881 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
882 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
883 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
884 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
885 *
886 * (*) : Not available for all stm32h5xxxx family lines.
887 * @retval None
888 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)889 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
890 {
891 __IO uint32_t tmpreg;
892 SET_BIT(RCC->AHB2ENR, Periphs);
893 /* Delay after an RCC peripheral clock enabling */
894 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
895 (void)tmpreg;
896 }
897
898 /**
899 * @brief Check if AHB2 peripheral clock is enabled or not
900 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
901 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
902 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
903 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
904 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
905 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
906 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
907 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
908 * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
909 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
910 * AHB2ENR DAC1EN LL_AHB2_GRP1_IsEnabledClock\n
911 * AHB2ENR DCMI_PSSIEN LL_AHB2_GRP1_IsEnabledClock\n
912 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
913 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
914 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
915 * AHB2ENR PKAEN LL_AHB2_GRP1_IsEnabledClock\n
916 * AHB2ENR SAESEN LL_AHB2_GRP1_IsEnabledClock\n
917 * AHB2ENR SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n
918 * AHB2ENR SRAM3EN LL_AHB2_GRP1_IsEnabledClock
919 * @param Periphs This parameter can be a combination of the following values:
920 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
921 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
922 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
923 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
924 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
925 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
926 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
927 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
928 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
929 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
930 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
931 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
932 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
933 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
934 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
935 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
936 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
937 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
938 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
939 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
940 *
941 * (*) : Not available for all stm32h5xxxx family lines.
942 * @retval State of Periphs (1 or 0).
943 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)944 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
945 {
946 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
947 }
948
949 /**
950 * @brief Disable AHB2 peripherals clock.
951 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
952 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
953 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
954 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
955 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
956 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
957 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
958 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
959 * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n
960 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
961 * AHB2ENR DAC1EN LL_AHB2_GRP1_DisableClock\n
962 * AHB2ENR DCMI_PSSIEN LL_AHB2_GRP1_DisableClock\n
963 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
964 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
965 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
966 * AHB2ENR PKAEN LL_AHB2_GRP1_DisableClock\n
967 * AHB2ENR SAESEN LL_AHB2_GRP1_DisableClock\n
968 * AHB2ENR SRAM2EN LL_AHB2_GRP1_DisableClock\n
969 * AHB2ENR SRAM3EN LL_AHB2_GRP1_DisableClock
970 * @param Periphs This parameter can be a combination of the following values:
971 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
972 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
973 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
974 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
975 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
976 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
977 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
978 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
979 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
980 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
981 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
982 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
983 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
984 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
985 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
986 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
987 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
988 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
989 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
990 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
991 *
992 * (*) : Not available for all stm32h5xxxx family lines.
993 * @retval None
994 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)995 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
996 {
997 CLEAR_BIT(RCC->AHB2ENR, Periphs);
998 }
999
1000 /**
1001 * @brief Force AHB2 peripherals reset.
1002 * @rmtoll AHB2RST GPIOARST LL_AHB2_GRP1_ForceReset\n
1003 * AHB2RST GPIOBRST LL_AHB2_GRP1_ForceReset\n
1004 * AHB2RST GPIOCRST LL_AHB2_GRP1_ForceReset\n
1005 * AHB2RST GPIODRST LL_AHB2_GRP1_ForceReset\n
1006 * AHB2RST GPIOERST LL_AHB2_GRP1_ForceReset\n
1007 * AHB2RST GPIOFRST LL_AHB2_GRP1_ForceReset\n
1008 * AHB2RST GPIOGRST LL_AHB2_GRP1_ForceReset\n
1009 * AHB2RST GPIOHRST LL_AHB2_GRP1_ForceReset\n
1010 * AHB2RST GPIOIRST LL_AHB2_GRP1_ForceReset\n
1011 * AHB2RST ADCRST LL_AHB2_GRP1_ForceReset\n
1012 * AHB2RST DAC1RST LL_AHB2_GRP1_ForceReset\n
1013 * AHB2RST DCMI_PSSIRST LL_AHB2_GRP1_ForceReset\n
1014 * AHB2RST AESRST LL_AHB2_GRP1_ForceReset\n
1015 * AHB2RST HASHRST LL_AHB2_GRP1_ForceReset\n
1016 * AHB2RST RNGRST LL_AHB2_GRP1_ForceReset\n
1017 * AHB2RST PKARST LL_AHB2_GRP1_ForceReset\n
1018 * AHB2RST SAESRST LL_AHB2_GRP1_ForceReset
1019 * @param Periphs This parameter can be a combination of the following values:
1020 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1021 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1022 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1023 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1024 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1025 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
1026 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1027 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
1028 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1029 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1030 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
1031 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
1032 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
1033 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
1034 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1035 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1036 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
1037 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1038 *
1039 * (*) : Not available for all stm32h5xxxx family lines.
1040 * @retval None
1041 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)1042 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
1043 {
1044 SET_BIT(RCC->AHB2RSTR, Periphs);
1045 }
1046
1047 /**
1048 * @brief Release AHB2 peripherals reset.
1049 * @rmtoll AHB2RST GPIOARST LL_AHB2_GRP1_ReleaseReset\n
1050 * AHB2RST GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
1051 * AHB2RST GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
1052 * AHB2RST GPIODRST LL_AHB2_GRP1_ReleaseReset\n
1053 * AHB2RST GPIOERST LL_AHB2_GRP1_ReleaseReset\n
1054 * AHB2RST GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
1055 * AHB2RST GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
1056 * AHB2RST GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
1057 * AHB2RST GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
1058 * AHB2RST ADCRST LL_AHB2_GRP1_ReleaseReset\n
1059 * AHB2RST DAC1RST LL_AHB2_GRP1_ReleaseReset\n
1060 * AHB2RST DCMI_PSSIRST LL_AHB2_GRP1_ReleaseReset\n
1061 * AHB2RST AESRST LL_AHB2_GRP1_ReleaseReset\n
1062 * AHB2RST HASHRST LL_AHB2_GRP1_ReleaseReset\n
1063 * AHB2RST RNGRST LL_AHB2_GRP1_ReleaseReset\n
1064 * AHB2RST PKARST LL_AHB2_GRP1_ReleaseReset\n
1065 * AHB2RST SAESRST LL_AHB2_GRP1_ReleaseReset
1066 * @param Periphs This parameter can be a combination of the following values:
1067 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1068 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1069 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1070 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1071 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1072 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
1073 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1074 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
1075 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1076 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1077 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
1078 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
1079 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
1080 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
1081 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1082 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1083 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
1084 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1085 *
1086 * (*) : Not available for all stm32h5xxxx family lines.
1087 * @retval None
1088 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)1089 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
1090 {
1091 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
1092 }
1093
1094 /**
1095 * @brief Enable AHB2 peripheral clocks in Sleep mode
1096 * @rmtoll AHB2LPENR GPIOALPEN LL_AHB2_GRP1_EnableClockSleep\n
1097 * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_EnableClockSleep\n
1098 * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_EnableClockSleep\n
1099 * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_EnableClockSleep\n
1100 * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_EnableClockSleep\n
1101 * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_EnableClockSleep\n
1102 * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_EnableClockSleep\n
1103 * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_EnableClockSleep\n
1104 * AHB2LPENR GPIOILPEN LL_AHB2_GRP1_EnableClockSleep\n
1105 * AHB2LPENR ADCLPEN LL_AHB2_GRP1_EnableClockSleep\n
1106 * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_EnableClockSleep\n
1107 * AHB2LPENR DCMI_PSSILPEN LL_AHB2_GRP1_EnableClockSleep\n
1108 * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockSleep\n
1109 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n
1110 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n
1111 * AHB2LPENR PKALPEN LL_AHB2_GRP1_EnableClockSleep\n
1112 * AHB2LPENR SAESLPEN LL_AHB2_GRP1_EnableClockSleep\n
1113 * AHB2LPENR SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n
1114 * AHB2LPENR SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep
1115 * @param Periphs This parameter can be a combination of the following values:
1116 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1117 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1118 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1119 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1120 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1121 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
1122 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1123 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
1124 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1125 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1126 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
1127 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
1128 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
1129 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
1130 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1131 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1132 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
1133 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1134 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
1135 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
1136 *
1137 * (*) : Not available for all stm32h5xxxx family lines.
1138 * @retval None
1139 */
LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)1140 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
1141 {
1142 __IO uint32_t tmpreg;
1143 SET_BIT(RCC->AHB2LPENR, Periphs);
1144 /* Delay after an RCC peripheral clock enabling */
1145 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
1146 (void)tmpreg;
1147 }
1148
1149 /**
1150 * @brief Check if AHB2 peripheral clocks in Sleep mode is enabled or not
1151 * @rmtoll AHB2LPENR GPIOALPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1152 * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1153 * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1154 * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1155 * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1156 * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1157 * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1158 * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1159 * AHB2LPENR GPIOILPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1160 * AHB2LPENR ADCLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1161 * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1162 * AHB2LPENR DCMI_PSSILPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1163 * AHB2LPENR AESLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1164 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1165 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1166 * AHB2LPENR PKALPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1167 * AHB2LPENR SAESLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1168 * AHB2LPENR SRAM2LPEN LL_AHB2_GRP1_IsEnabledClockSleep\n
1169 * AHB2LPENR SRAM3LPEN LL_AHB2_GRP1_IsEnabledClockSleep
1170 * @param Periphs This parameter can be a combination of the following values:
1171 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1172 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1173 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1174 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1175 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1176 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
1177 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1178 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
1179 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1180 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1181 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
1182 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
1183 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
1184 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
1185 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1186 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1187 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
1188 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1189 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
1190 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
1191 *
1192 * (*) : Not available for all stm32h5xxxx family lines.
1193 * @retval State of Periphs (1 or 0).
1194 */
LL_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)1195 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)
1196 {
1197 return ((READ_BIT(RCC->AHB2LPENR, Periphs) == Periphs) ? 1UL : 0UL);
1198 }
1199
1200 /**
1201 * @brief Disable AHB2 peripheral clocks in Sleep mode
1202 * @rmtoll AHB2LPENR GPIOALPEN LL_AHB2_GRP1_DisableClockSleep\n
1203 * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_DisableClockSleep\n
1204 * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_DisableClockSleep\n
1205 * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_DisableClockSleep\n
1206 * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_DisableClockSleep\n
1207 * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_DisableClockSleep\n
1208 * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_DisableClockSleep\n
1209 * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_DisableClockSleep\n
1210 * AHB2LPENR GPIOILPEN LL_AHB2_GRP1_DisableClockSleep\n
1211 * AHB2LPENR ADCLPEN LL_AHB2_GRP1_DisableClockSleep\n
1212 * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_DisableClockSleep\n
1213 * AHB2LPENR DCMI_PSSILPEN LL_AHB2_GRP1_DisableClockSleep\n
1214 * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockSleep\n
1215 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n
1216 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n
1217 * AHB2LPENR PKALPEN LL_AHB2_GRP1_DisableClockSleep\n
1218 * AHB2LPENR SAESLPEN LL_AHB2_GRP1_DisableClockSleep\n
1219 * AHB2LPENR SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n
1220 * AHB2LPENR SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep
1221 * @param Periphs This parameter can be a combination of the following values:
1222 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1223 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
1224 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
1225 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
1226 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
1227 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
1228 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
1229 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
1230 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
1231 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
1232 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
1233 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
1234 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*)
1235 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
1236 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1237 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1238 * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*)
1239 * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*)
1240 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*)
1241 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
1242 *
1243 * (*) : Not available for all stm32h5xxxx family lines.
1244 * @retval None
1245 */
LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)1246 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
1247 {
1248 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
1249 }
1250
1251 /**
1252 * @}
1253 */
1254
1255 #if defined(AHB4PERIPH_BASE)
1256 /** @defgroup BUS_LL_EF_AHB4 AHB4 Peripherals
1257 * @{
1258 */
1259 /**
1260 * @brief Enable AHB4 peripherals clock.
1261 * @rmtoll AHB4ENR OTFDEC1EN LL_AHB4_GRP1_EnableClock\n
1262 * AHB4ENR SDMMC1EN LL_AHB4_GRP1_EnableClock\n
1263 * AHB4ENR SDMMC2EN LL_AHB4_GRP1_EnableClock\n
1264 * AHB4ENR FMCEN LL_AHB4_GRP1_EnableClock\n
1265 * AHB4ENR OCTOSPI1EN LL_AHB4_GRP1_EnableClock
1266 * @param Periphs This parameter can be a combination of the following values:
1267 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1268 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1269 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1270 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 (*)
1271 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1272 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1273 *
1274 * (*) : Not available for all stm32h5xxxx family lines.
1275 * @retval None
1276 */
LL_AHB4_GRP1_EnableClock(uint32_t Periphs)1277 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
1278 {
1279 __IO uint32_t tmpreg;
1280 SET_BIT(RCC->AHB4ENR, Periphs);
1281 /* Delay after an RCC peripheral clock enabling */
1282 tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
1283 (void)tmpreg;
1284 }
1285
1286 /**
1287 * @brief Check if AHB4 peripheral clock is enabled or not
1288 * @rmtoll AHB4ENR OTFDEC1EN LL_AHB4_GRP1_IsEnabledClock\n
1289 * AHB4ENR SDMMC1EN LL_AHB4_GRP1_IsEnabledClock\n
1290 * AHB4ENR SDMMC2EN LL_AHB4_GRP1_IsEnabledClock\n
1291 * AHB4ENR FMCEN LL_AHB4_GRP1_IsEnabledClock\n
1292 * AHB4ENR OCTOSPI1EN LL_AHB4_GRP1_IsEnabledClock
1293 * @param Periphs This parameter can be a combination of the following values:
1294 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1295 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1296 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1297 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1298 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1299 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1300 * @retval State of Periphs (1 or 0).
1301 */
LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)1302 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
1303 {
1304 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1UL : 0UL);
1305 }
1306
1307 /**
1308 * @brief Disable AHB4 peripherals clock.
1309 * @rmtoll AHB4ENR OTFDEC1EN LL_AHB4_GRP1_DisableClock\n
1310 * AHB4ENR SDMMC1EN LL_AHB4_GRP1_DisableClock\n
1311 * AHB4ENR SDMMC2EN LL_AHB4_GRP1_DisableClock\n
1312 * AHB4ENR FMCEN LL_AHB4_GRP1_DisableClock\n
1313 * AHB4ENR OCTOSPI1EN LL_AHB4_GRP1_DisableClock
1314 * @param Periphs This parameter can be a combination of the following values:
1315 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1316 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1317 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1318 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1319 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1320 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1321 * @retval None
1322 */
LL_AHB4_GRP1_DisableClock(uint32_t Periphs)1323 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
1324 {
1325 CLEAR_BIT(RCC->AHB4ENR, Periphs);
1326 }
1327
1328 /**
1329 * @brief Force AHB4 peripherals reset.
1330 * @rmtoll AHB4RSTR OTFDEC1RST LL_AHB4_GRP1_ForceReset\n
1331 * AHB4RSTR SDMMC1RST LL_AHB4_GRP1_ForceReset\n
1332 * AHB4RSTR SDMMC2RST LL_AHB4_GRP1_ForceReset\n
1333 * AHB4RSTR FMCRST LL_AHB4_GRP1_ForceReset\n
1334 * AHB4RSTR OCTOSPI1RST LL_AHB4_GRP1_ForceReset
1335 * @param Periphs This parameter can be a combination of the following values:
1336 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1337 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1338 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1339 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1340 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1341 * @retval None
1342 */
LL_AHB4_GRP1_ForceReset(uint32_t Periphs)1343 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
1344 {
1345 SET_BIT(RCC->AHB4RSTR, Periphs);
1346 }
1347
1348 /**
1349 * @brief Release AHB4 peripherals reset.
1350 * @rmtoll AHB4RSTR OTFDEC1RST LL_AHB4_GRP1_ReleaseReset\n
1351 * AHB4RSTR SDMMC1RST LL_AHB4_GRP1_ReleaseReset\n
1352 * AHB4RSTR SDMMC2RST LL_AHB4_GRP1_ReleaseReset\n
1353 * AHB4RSTR FMCRST LL_AHB4_GRP1_ReleaseReset\n
1354 * AHB4RSTR OCTOSPI1RST LL_AHB4_GRP1_ReleaseReset
1355 * @param Periphs This parameter can be a combination of the following values:
1356 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1357 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1358 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1359 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1360 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1361 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1362 * @retval None
1363 */
LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)1364 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
1365 {
1366 CLEAR_BIT(RCC->AHB4RSTR, Periphs);
1367 }
1368
1369 /**
1370 * @brief Enable AHB4 peripheral clocks in Sleep mode
1371 * @rmtoll AHB4LPENR OTFDEC1LPEN LL_AHB4_GRP1_EnableClockSleep\n
1372 * AHB4LPENR SDMMC1LPEN LL_AHB4_GRP1_EnableClockSleep\n
1373 * AHB4LPENR SDMMC2LPEN LL_AHB4_GRP1_EnableClockSleep\n
1374 * AHB4LPENR FMCLPEN LL_AHB4_GRP1_EnableClockSleep\n
1375 * AHB4LPENR OCTOSPI1LPEN LL_AHB4_GRP1_EnableClockSleep
1376 * @param Periphs This parameter can be a combination of the following values:
1377 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1378 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1379 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1380 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1381 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1382 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1383 * @retval None
1384 */
LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)1385 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
1386 {
1387 __IO uint32_t tmpreg;
1388 SET_BIT(RCC->AHB4LPENR, Periphs);
1389 /* Delay after an RCC peripheral clock enabling */
1390 tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
1391 (void)tmpreg;
1392 }
1393
1394 /**
1395 * @brief Check if AHB4 peripheral clocks in Sleep mode is enabled or not
1396 * @rmtoll AHB4LPENR OTFDEC1LPEN LL_AHB4_GRP1_IsEnabledClockSleep\n
1397 * AHB4LPENR SDMMC1LPEN LL_AHB4_GRP1_IsEnabledClockSleep\n
1398 * AHB4LPENR SDMMC2LPEN LL_AHB4_GRP1_IsEnabledClockSleep\n
1399 * AHB4LPENR FMCLPEN LL_AHB4_GRP1_IsEnabledClockSleep\n
1400 * AHB4LPENR OCTOSPI1LPEN LL_AHB4_GRP1_IsEnabledClockSleep
1401 * @param Periphs This parameter can be a combination of the following values:
1402 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1403 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1404 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1405 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1406 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1407 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1408 * @retval State of Periphs (1 or 0).
1409 */
LL_AHB4_GRP1_IsEnabledClockSleep(uint32_t Periphs)1410 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockSleep(uint32_t Periphs)
1411 {
1412 return ((READ_BIT(RCC->AHB4LPENR, Periphs) == Periphs) ? 1UL : 0UL);
1413 }
1414
1415 /**
1416 * @brief Disable AHB4 peripheral clocks in Sleep and Stop modes
1417 * @rmtoll AHB4LPENR OTFDEC1LPEN LL_AHB4_GRP1_DisableClockSleep\n
1418 * AHB4LPENR SDMMC1LPEN LL_AHB4_GRP1_DisableClockSleep\n
1419 * AHB4LPENR SDMMC2LPEN LL_AHB4_GRP1_DisableClockSleep\n
1420 * AHB4LPENR FMCLPEN LL_AHB4_GRP1_DisableClockSleep\n
1421 * AHB4LPENR OCTOSPI1LPEN LL_AHB4_GRP1_DisableClockSleep
1422 * @param Periphs This parameter can be a combination of the following values:
1423 * @arg @ref LL_AHB4_GRP1_PERIPH_ALL
1424 * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC
1425 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1
1426 * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2
1427 * @arg @ref LL_AHB4_GRP1_PERIPH_FMC
1428 * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1
1429 * @retval None
1430 */
LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)1431 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
1432 {
1433 CLEAR_BIT(RCC->AHB4LPENR, Periphs);
1434 }
1435
1436 /**
1437 * @}
1438 */
1439 #endif /* AHB4PERIPH_BASE */
1440
1441 /** @defgroup BUS_LL_EF_APB1 APB1 Peripherals
1442 * @{
1443 */
1444
1445 /**
1446 * @brief Enable APB1 peripherals clock.
1447 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n
1448 * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n
1449 * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n
1450 * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n
1451 * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n
1452 * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n
1453 * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n
1454 * APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n
1455 * APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n
1456 * APB1LENR WWDGEN LL_APB1_GRP1_EnableClock\n
1457 * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n
1458 * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n
1459 * APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n
1460 * APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n
1461 * APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n
1462 * APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n
1463 * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n
1464 * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n
1465 * APB1LENR I3C1EN LL_APB1_GRP1_EnableClock\n
1466 * APB1LENR CRSEN LL_APB1_GRP1_EnableClock\n
1467 * APB1LENR USART6EN LL_APB1_GRP1_EnableClock\n
1468 * APB1LENR USART10EN LL_APB1_GRP1_EnableClock\n
1469 * APB1LENR USART11EN LL_APB1_GRP1_EnableClock\n
1470 * APB1LENR CECEN LL_APB1_GRP1_EnableClock\n
1471 * APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n
1472 * APB1LENR UART8EN LL_APB1_GRP1_EnableClock
1473 * @param Periphs This parameter can be a combination of the following values:
1474 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1475 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1476 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1477 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1478 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1479 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1480 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1481 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1482 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1483 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1484 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1485 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1486 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1487 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1488 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1489 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1490 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1491 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1492 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1493 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1494 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1495 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1496 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1497 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1498 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1499 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1500 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1501 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1502 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1503 *
1504 * (*) : Not available for all stm32h5xxxx family lines.
1505 * @retval None
1506 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1507 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1508 {
1509 __IO uint32_t tmpreg;
1510 SET_BIT(RCC->APB1LENR, Periphs);
1511 /* Delay after an RCC peripheral clock enabling */
1512 tmpreg = READ_BIT(RCC->APB1LENR, Periphs);
1513 (void)tmpreg;
1514 }
1515
1516 /**
1517 * @brief Enable APB1 peripherals clock.
1518 * @rmtoll APB1HENR UART9EN LL_APB1_GRP2_EnableClock\n
1519 * APB1HENR UART12EN LL_APB1_GRP2_EnableClock\n
1520 * APB1HENR DTSEN LL_APB1_GRP2_EnableClock\n
1521 * APB1HENR LPTIM2EN LL_APB1_GRP2_EnableClock\n
1522 * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock\n
1523 * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock\n
1524 * APB1HENR UCPD1EN LL_APB1_GRP2_EnableClock
1525 * @param Periphs This parameter can be a combination of the following values:
1526 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1527 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
1528 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
1529 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
1530 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1531 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1532 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1533 *
1534 * (*) : Not available for all stm32h5xxxx family lines.
1535 * @retval None
1536 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)1537 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
1538 {
1539 __IO uint32_t tmpreg;
1540 SET_BIT(RCC->APB1HENR, Periphs);
1541 /* Delay after an RCC peripheral clock enabling */
1542 tmpreg = READ_BIT(RCC->APB1HENR, Periphs);
1543 (void)tmpreg;
1544 }
1545
1546 /**
1547 * @brief Check if APB1 peripheral clock is enabled or not
1548 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1549 * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1550 * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1551 * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1552 * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1553 * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1554 * APB1LENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1555 * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1556 * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1557 * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1558 * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1559 * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1560 * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1561 * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1562 * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1563 * APB1LENR I3C1EN LL_APB1_GRP1_IsEnabledClock\n
1564 * APB1LENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
1565 * APB1LENR USART6EN LL_APB1_GRP1_IsEnabledClock\n
1566 * APB1LENR USART10EN LL_APB1_GRP1_IsEnabledClock\n
1567 * APB1LENR USART11EN LL_APB1_GRP1_IsEnabledClock\n
1568 * APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1569 * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1570 * APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock
1571 * @param Periphs This parameter can be a combination of the following values:
1572 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1573 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1574 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1575 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1576 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1577 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1578 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1579 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1580 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1581 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1582 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1583 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1584 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1585 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1586 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1587 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1588 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1589 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1590 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1591 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1592 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1593 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1594 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1595 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1596 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1597 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1598 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1599 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1600 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1601 *
1602 * (*) : Not available for all stm32h5xxxx family lines.
1603 * @retval State of Periphs (1 or 0).
1604 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1605 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1606 {
1607 return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs) ? 1UL : 0UL);
1608 }
1609
1610 /**
1611 * @brief Check if APB1 peripheral clock is enabled or not
1612 * @rmtoll APB1HENR UART9EN LL_APB1_GRP2_IsEnabledClock\n
1613 * APB1HENR UART12EN LL_APB1_GRP2_IsEnabledClock\n
1614 * APB1HENR DTSEN LL_APB1_GRP2_IsEnabledClock\n
1615 * APB1HENR LPTIM2EN LL_APB1_GRP2_IsEnabledClock\n
1616 * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock\n
1617 * APB1HENR UCPD1EN LL_APB1_GRP2_IsEnabledClock
1618 * @param Periphs This parameter can be a combination of the following values:
1619 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1620 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
1621 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
1622 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
1623 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1624 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1625 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1626 *
1627 * (*) : Not available for all stm32h5xxxx family lines.
1628 * @retval State of Periphs (1 or 0).
1629 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1630 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1631 {
1632 return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs) ? 1UL : 0UL);
1633 }
1634
1635 /**
1636 * @brief Disable APB1 peripherals clock.
1637 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n
1638 * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n
1639 * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n
1640 * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n
1641 * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n
1642 * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n
1643 * APB1LENR WWDGEN LL_APB1_GRP1_DisableClock\n
1644 * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n
1645 * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n
1646 * APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n
1647 * APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n
1648 * APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n
1649 * APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n
1650 * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n
1651 * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n
1652 * APB1LENR I3C1EN LL_APB1_GRP1_DisableClock\n
1653 * APB1LENR CRSEN LL_APB1_GRP1_DisableClock\n
1654 * APB1LENR USART6EN LL_APB1_GRP1_DisableClock\n
1655 * APB1LENR USART10EN LL_APB1_GRP1_DisableClock\n
1656 * APB1LENR USART11EN LL_APB1_GRP1_DisableClock\n
1657 * APB1LENR CECEN LL_APB1_GRP1_DisableClock\n
1658 * APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n
1659 * APB1LENR UART8EN LL_APB1_GRP1_DisableClock
1660 * @param Periphs This parameter can be a combination of the following values:
1661 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1662 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1663 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1664 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1665 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1666 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1667 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1668 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1669 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1670 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1671 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1672 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1673 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1674 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1675 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1676 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1677 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1678 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1679 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1680 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1681 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1682 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1683 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1684 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1685 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1686 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1687 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1688 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1689 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1690 *
1691 * (*) : Not available for all stm32h5xxxx family lines.
1692 * @retval None
1693 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1694 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1695 {
1696 CLEAR_BIT(RCC->APB1LENR, Periphs);
1697 }
1698
1699 /**
1700 * @brief Disable APB1 peripherals clock.
1701 * @rmtoll APB1HENR UART9EN LL_APB1_GRP2_DisableClock\n
1702 * APB1HENR UART12EN LL_APB1_GRP2_DisableClock\n
1703 * APB1HENR DTSEN LL_APB1_GRP2_DisableClock\n
1704 * APB1HENR LPTIM2EN LL_APB1_GRP2_DisableClock\n
1705 * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock\n
1706 * APB1HENR UCPD1EN LL_APB1_GRP2_DisableClock
1707 * @param Periphs This parameter can be a combination of the following values:
1708 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1709 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
1710 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
1711 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
1712 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1713 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1714 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1715 *
1716 * (*) : Not available for all stm32h5xxxx family lines.
1717 * @retval None
1718 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1719 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1720 {
1721 CLEAR_BIT(RCC->APB1HENR, Periphs);
1722 }
1723
1724 /**
1725 * @brief Force APB1 peripherals reset.
1726 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n
1727 * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n
1728 * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n
1729 * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n
1730 * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n
1731 * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n
1732 * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n
1733 * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n
1734 * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n
1735 * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n
1736 * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n
1737 * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n
1738 * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n
1739 * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n
1740 * APB1LRSTR I3C1RST LL_APB1_GRP1_ForceReset\n
1741 * APB1LRSTR CRSRST LL_APB1_GRP1_ForceReset\n
1742 * APB1LRSTR USART6RST LL_APB1_GRP1_ForceReset\n
1743 * APB1LRSTR USART10RST LL_APB1_GRP1_ForceReset\n
1744 * APB1LRSTR USART11RST LL_APB1_GRP1_ForceReset\n
1745 * APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n
1746 * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n
1747 * APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset
1748 * @param Periphs This parameter can be a combination of the following values:
1749 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1750 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1751 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1752 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1753 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1754 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1755 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1756 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1757 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1758 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1759 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1760 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1761 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1762 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1763 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1764 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1765 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1766 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1767 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1768 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1769 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1770 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1771 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1772 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1773 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1774 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1775 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1776 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1777 *
1778 * (*) : Not available for all stm32h5xxxx family lines.
1779 * @retval None
1780 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1781 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1782 {
1783 SET_BIT(RCC->APB1LRSTR, Periphs);
1784 }
1785
1786 /**
1787 * @brief Force APB1 peripherals reset.
1788 * @rmtoll APB1HRSTR UART9RST LL_APB1_GRP2_ForceReset\n
1789 * APB1HRSTR UART12RST LL_APB1_GRP2_ForceReset\n
1790 * APB1HRSTR DTSRST LL_APB1_GRP2_ForceReset\n
1791 * APB1HRSTR LPTIM2RST LL_APB1_GRP2_ForceReset\n
1792 * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset\n
1793 * APB1HRSTR UCPD1RST LL_APB1_GRP2_ForceReset
1794 * @param Periphs This parameter can be a combination of the following values:
1795 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1796 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
1797 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
1798 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
1799 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1800 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1801 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1802 *
1803 * (*) : Not available for all stm32h5xxxx family lines.
1804 * @retval None
1805 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1806 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1807 {
1808 SET_BIT(RCC->APB1HRSTR, Periphs);
1809 }
1810
1811 /**
1812 * @brief Release APB1 peripherals reset.
1813 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
1814 * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
1815 * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
1816 * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
1817 * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
1818 * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
1819 * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
1820 * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
1821 * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
1822 * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
1823 * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
1824 * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
1825 * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
1826 * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
1827 * APB1LRSTR I3C1RST LL_APB1_GRP1_ReleaseReset\n
1828 * APB1LRSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
1829 * APB1LRSTR USART6RST LL_APB1_GRP1_ReleaseReset\n
1830 * APB1LRSTR USART10RST LL_APB1_GRP1_ReleaseReset\n
1831 * APB1LRSTR USART11RST LL_APB1_GRP1_ReleaseReset\n
1832 * APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n
1833 * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
1834 * APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset
1835 * @param Periphs This parameter can be a combination of the following values:
1836 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1837 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1838 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1839 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1840 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1841 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1842 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1843 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1844 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1845 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1846 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1847 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1848 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1849 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1850 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1851 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1852 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1853 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1854 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1855 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1856 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1857 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1858 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1859 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1860 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1861 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1862 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1863 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1864 *
1865 * (*) : Not available for all stm32h5xxxx family lines.
1866 * @retval None
1867 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1868 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1869 {
1870 CLEAR_BIT(RCC->APB1LRSTR, Periphs);
1871 }
1872
1873 /**
1874 * @brief Release APB1 peripherals reset.
1875 * @rmtoll APB1HRSTR UART9RST LL_APB1_GRP2_ReleaseReset\n
1876 * APB1HRSTR UART12RST LL_APB1_GRP2_ReleaseReset\n
1877 * APB1HRSTR DTSRST LL_APB1_GRP2_ReleaseReset\n
1878 * APB1HRSTR LPTIM2RST LL_APB1_GRP2_ReleaseReset\n
1879 * APB1HRSTR FDCAN LL_APB1_GRP2_ReleaseReset\n
1880 * APB1HRSTR UCPD1RST LL_APB1_GRP2_ReleaseReset
1881 * @param Periphs This parameter can be a combination of the following values:
1882 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1883 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
1884 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
1885 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
1886 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1887 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1888 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1889 *
1890 * (*) : Not available for all stm32h5xxxx family lines.
1891 * @retval None
1892 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1893 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1894 {
1895 CLEAR_BIT(RCC->APB1HRSTR, Periphs);
1896 }
1897
1898 /**
1899 * @brief Enable APB1 peripheral clocks in Sleep mode
1900 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
1901 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
1902 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
1903 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
1904 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
1905 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
1906 * APB1LLPENR WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n
1907 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
1908 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
1909 * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
1910 * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
1911 * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
1912 * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
1913 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
1914 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
1915 * APB1LLPENR I3C1LPEN LL_APB1_GRP1_EnableClockSleep\n
1916 * APB1LLPENR CRSLPEN LL_APB1_GRP1_EnableClockSleep\n
1917 * APB1LLPENR USART6LPEN LL_APB1_GRP1_EnableClockSleep\n
1918 * APB1LLPENR USART10LPEN LL_APB1_GRP1_EnableClockSleep\n
1919 * APB1LLPENR USART11LPEN LL_APB1_GRP1_EnableClockSleep\n
1920 * APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n
1921 * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n
1922 * APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep
1923 * @param Periphs This parameter can be a combination of the following values:
1924 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1925 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1926 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1927 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1928 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1929 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1930 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1931 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1932 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1933 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1934 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1935 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1936 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1937 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
1938 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
1939 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1940 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1941 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1942 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1943 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1944 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1945 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1946 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1947 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
1948 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
1949 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
1950 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1951 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1952 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1953 *
1954 * (*) : Not available for all stm32h5xxxx family lines.
1955 * @retval None
1956 */
LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)1957 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
1958 {
1959 __IO uint32_t tmpreg;
1960 SET_BIT(RCC->APB1LLPENR, Periphs);
1961 /* Delay after an RCC peripheral clock enabling */
1962 tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);
1963 (void)tmpreg;
1964 }
1965
1966 /**
1967 * @brief Check if APB1 peripheral clocks in Sleep mode is enabled or not
1968 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1969 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1970 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1971 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1972 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1973 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1974 * APB1LLPENR WWDGLPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1975 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1976 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1977 * APB1LLPENR USART2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1978 * APB1LLPENR USART3LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1979 * APB1LLPENR UART4LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1980 * APB1LLPENR UART5LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1981 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1982 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1983 * APB1LLPENR I3C1LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1984 * APB1LLPENR CRSLPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1985 * APB1LLPENR USART6LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1986 * APB1LLPENR USART10LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1987 * APB1LLPENR USART11LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1988 * APB1LLPENR CECLPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1989 * APB1LLPENR UART7LPEN LL_APB1_GRP1_IsEnabledClockSleep\n
1990 * APB1LLPENR UART8LPEN LL_APB1_GRP1_IsEnabledClockSleep
1991 * @param Periphs This parameter can be a combination of the following values:
1992 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1993 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1994 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1995 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1996 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1997 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1998 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1999 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
2000 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
2001 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2002 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
2003 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2004 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2005 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
2006 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
2007 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2008 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2009 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
2010 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
2011 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2012 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2013 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
2014 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
2015 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
2016 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
2017 * @arg @ref LL_APB1_GRP1_PERIPH_USART11
2018 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
2019 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
2020 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
2021 *
2022 * (*) : Not available for all stm32h5xxxx family lines.
2023 * @retval State of Periphs (1 or 0).
2024 */
LL_APB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)2025 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockSleep(uint32_t Periphs)
2026 {
2027 return ((READ_BIT(RCC->APB1LLPENR, Periphs) == Periphs) ? 1UL : 0UL);
2028 }
2029
2030 /**
2031 * @brief Disable APB1 peripheral clocks in Sleep mode
2032 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
2033 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
2034 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
2035 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
2036 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
2037 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
2038 * APB1LLPENR WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n
2039 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
2040 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
2041 * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
2042 * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
2043 * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
2044 * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
2045 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
2046 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
2047 * APB1LLPENR I3C1LPEN LL_APB1_GRP1_DisableClockSleep\n
2048 * APB1LLPENR CRSLPEN LL_APB1_GRP1_DisableClockSleep\n
2049 * APB1LLPENR USART6LPEN LL_APB1_GRP1_DisableClockSleep\n
2050 * APB1LLPENR USART10LPEN LL_APB1_GRP1_DisableClockSleep\n
2051 * APB1LLPENR USART11LPEN LL_APB1_GRP1_DisableClockSleep\n
2052 * APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n
2053 * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n
2054 * APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep
2055 * @param Periphs This parameter can be a combination of the following values:
2056 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
2057 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2058 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2059 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
2060 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
2061 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2062 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2063 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
2064 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
2065 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
2066 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
2067 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2068 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2069 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
2070 * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*)
2071 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2072 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2073 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
2074 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
2075 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2076 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2077 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
2078 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
2079 * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
2080 * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*)
2081 * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*)
2082 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
2083 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
2084 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
2085 *
2086 * (*) : Not available for all stm32h5xxxx family lines.
2087 * @retval None
2088 */
LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)2089 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
2090 {
2091 CLEAR_BIT(RCC->APB1LLPENR, Periphs);
2092 }
2093
2094 /**
2095 * @brief Enable APB1 peripheral clocks in Sleep mode
2096 * @rmtoll APB1HLPENR UART9LPEN LL_APB1_GRP2_EnableClockSleep\n
2097 * APB1HLPENR UART12LPEN LL_APB1_GRP2_EnableClockSleep\n
2098 * APB1HLPENR DTSLPEN LL_APB1_GRP2_EnableClockSleep\n
2099 * APB1HLPENR LPTIM2LPEN LL_APB1_GRP2_EnableClockSleep\n
2100 * APB1HLPENR FDCAN12LPEN LL_APB1_GRP2_EnableClockSleep\n
2101 * APB1HLPENR FDCAN1LPEN LL_APB1_GRP2_EnableClockSleep\n
2102 * APB1HLPENR UCPD1LPEN LL_APB1_GRP2_EnableClockSleep
2103 * @param Periphs This parameter can be a combination of the following values:
2104 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2105 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
2106 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
2107 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
2108 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2109 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2110 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2111 *
2112 * (*) : Not available for all stm32h5xxxx family lines.
2113 * @retval None
2114 */
LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)2115 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
2116 {
2117 __IO uint32_t tmpreg;
2118 SET_BIT(RCC->APB1HLPENR, Periphs);
2119 /* Delay after an RCC peripheral clock enabling */
2120 tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);
2121 (void)tmpreg;
2122 }
2123
2124 /**
2125 * @brief Check if APB1 peripheral clocks in Sleep mode is enabled or not
2126 * @rmtoll APB1HLPENR UART9LPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2127 * APB1HLPENR UART12LPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2128 * APB1HLPENR DTSLPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2129 * APB1HLPENR LPTIM2LPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2130 * APB1HLPENR FDCAN12LPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2131 * APB1HLPENR FDCAN1LPEN LL_APB1_GRP2_IsEnabledClockSleep\n
2132 * APB1HLPENR UCPD1LPEN LL_APB1_GRP2_IsEnabledClockSleep
2133 * @param Periphs This parameter can be a combination of the following values:
2134 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2135 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
2136 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
2137 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
2138 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2139 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2140 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2141 *
2142 * (*) : Not available for all stm32h5xxxx family lines.
2143 * @retval State of Periphs (1 or 0).
2144 */
LL_APB1_GRP2_IsEnabledClockSleep(uint32_t Periphs)2145 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockSleep(uint32_t Periphs)
2146 {
2147 return ((READ_BIT(RCC->APB1HLPENR, Periphs) == Periphs) ? 1UL : 0UL);
2148 }
2149
2150 /**
2151 * @brief Disable APB1 peripheral clocks in Sleep mode
2152 * @rmtoll APB1HLPENR UART9LPEN LL_APB1_GRP2_DisableClockSleep\n
2153 * APB1HLPENR UART12LPEN LL_APB1_GRP2_DisableClockSleep\n
2154 * APB1HLPENR DTSLPEN LL_APB1_GRP2_DisableClockSleep\n
2155 * APB1HLPENR LPTIM2LPEN LL_APB1_GRP2_DisableClockSleep\n
2156 * APB1HLPENR FDCAN12LPEN LL_APB1_GRP2_DisableClockSleep\n
2157 * APB1HLPENR FDCAN1LPEN LL_APB1_GRP2_DisableClockSleep\n
2158 * APB1HLPENR UCPD1LPEN LL_APB1_GRP2_DisableClockSleep
2159 * @param Periphs This parameter can be a combination of the following values:
2160 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
2161 * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*)
2162 * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*)
2163 * @arg @ref LL_APB1_GRP2_PERIPH_DTS
2164 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
2165 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2166 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
2167 *
2168 * (*) : Not available for all stm32h5xxxx family lines.
2169 * @retval None
2170 */
LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)2171 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
2172 {
2173 CLEAR_BIT(RCC->APB1HLPENR, Periphs);
2174 }
2175
2176 /**
2177 * @}
2178 */
2179
2180 /** @defgroup BUS_LL_EF_APB2 APB2 Peripherals
2181 * @{
2182 */
2183
2184 /**
2185 * @brief Enable APB2 peripherals clock.
2186 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
2187 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
2188 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
2189 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
2190 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
2191 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
2192 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
2193 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
2194 * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
2195 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
2196 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
2197 * APB2ENR USBEN LL_APB2_GRP1_EnableClock
2198 * @param Periphs This parameter can be a combination of the following values:
2199 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2200 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2201 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2202 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2203 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2204 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2205 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2206 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2207 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2208 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2209 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2210 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2211 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2212 *
2213 * (*) : Not available for all stm32h5xxxx family lines.
2214 * @retval None
2215 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)2216 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
2217 {
2218 __IO uint32_t tmpreg;
2219 SET_BIT(RCC->APB2ENR, Periphs);
2220 /* Delay after an RCC peripheral clock enabling */
2221 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
2222 (void)tmpreg;
2223 }
2224
2225 /**
2226 * @brief Check if APB2 peripheral clock is enabled or not
2227 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
2228 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
2229 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
2230 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
2231 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
2232 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
2233 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
2234 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
2235 * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
2236 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
2237 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
2238 * APB2ENR USBEN LL_APB2_GRP1_IsEnabledClock
2239 * @param Periphs This parameter can be a combination of the following values:
2240 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2241 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2242 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2243 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2244 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2245 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2246 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2247 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2248 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2249 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2250 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2251 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2252 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2253 *
2254 * (*) : Not available for all stm32h5xxxx family lines.
2255 * @retval State of Periphs (1 or 0).
2256 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)2257 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
2258 {
2259 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
2260 }
2261
2262 /**
2263 * @brief Disable APB2 peripherals clock.
2264 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
2265 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
2266 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
2267 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
2268 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
2269 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
2270 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
2271 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
2272 * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
2273 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
2274 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
2275 * APB2ENR USBEN LL_APB2_GRP1_DisableClock
2276 * @param Periphs This parameter can be a combination of the following values:
2277 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2278 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2279 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2280 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2281 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2282 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2283 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2284 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2285 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2286 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2287 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2288 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2289 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2290 *
2291 * (*) : Not available for all stm32h5xxxx family lines.
2292 * @retval None
2293 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)2294 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
2295 {
2296 CLEAR_BIT(RCC->APB2ENR, Periphs);
2297 }
2298
2299 /**
2300 * @brief Force APB2 peripherals reset.
2301 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
2302 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
2303 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
2304 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
2305 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
2306 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
2307 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
2308 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
2309 * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
2310 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
2311 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
2312 * APB2RSTR USBRST LL_APB2_GRP1_ForceReset
2313 * @param Periphs This parameter can be a combination of the following values:
2314 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2315 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2316 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2317 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2318 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2319 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2320 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2321 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2322 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2323 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2324 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2325 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2326 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2327 *
2328 * (*) : Not available for all stm32h5xxxx family lines.
2329 * @retval None
2330 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)2331 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
2332 {
2333 SET_BIT(RCC->APB2RSTR, Periphs);
2334 }
2335
2336 /**
2337 * @brief Release APB2 peripherals reset.
2338 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
2339 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
2340 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
2341 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
2342 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
2343 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
2344 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
2345 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
2346 * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
2347 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
2348 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
2349 * APB2RSTR USBRST LL_APB2_GRP1_ReleaseReset
2350 * @param Periphs This parameter can be a combination of the following values:
2351 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2352 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2353 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2354 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2355 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
2356 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2357 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2358 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2359 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2360 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2361 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2362 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2363 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2364 *
2365 * (*) : Not available for all stm32h5xxxx family lines.
2366 * @retval None
2367 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)2368 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
2369 {
2370 CLEAR_BIT(RCC->APB2RSTR, Periphs);
2371 }
2372
2373 /**
2374 * @brief Enable APB2 peripheral clocks in Sleep mode
2375 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n
2376 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2377 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n
2378 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n
2379 * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n
2380 * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n
2381 * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n
2382 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n
2383 * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockSleep\n
2384 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2385 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n
2386 * APB2LPENR USBLPEN LL_APB2_GRP1_EnableClockSleep
2387 * @param Periphs This parameter can be a combination of the following values:
2388 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2389 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2390 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2391 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2392 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2393 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2394 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2395 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2396 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2397 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2398 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2399 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2400 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2401 *
2402 * (*) : Not available for all stm32h5xxxx family lines.
2403 * @retval None
2404 */
LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)2405 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
2406 {
2407 __IO uint32_t tmpreg;
2408 SET_BIT(RCC->APB2LPENR, Periphs);
2409 /* Delay after an RCC peripheral clock enabling */
2410 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
2411 (void)tmpreg;
2412 }
2413
2414
2415 /**
2416 * @brief Check if APB2 peripheral clocks in Sleep and Stop modes is enabled or not
2417 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2418 * APB2LPENR SPI1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2419 * APB2LPENR TIM8LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2420 * APB2LPENR USART1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2421 * APB2LPENR TIM15LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2422 * APB2LPENR TIM16LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2423 * APB2LPENR TIM17LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2424 * APB2LPENR SPI4LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2425 * APB2LPENR SPI6LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2426 * APB2LPENR SAI1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2427 * APB2LPENR SAI2LPEN LL_APB2_GRP1_IsEnabledClockSleep\n
2428 * APB2LPENR USBLPEN LL_APB2_GRP1_IsEnabledClockSleep
2429 * @param Periphs This parameter can be a combination of the following values:
2430 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2431 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2432 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2433 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2434 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2435 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2436 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2437 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2438 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2439 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2440 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2441 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2442 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2443 *
2444 * (*) : Not available for all stm32h5xxxx family lines.
2445 * @retval State of Periphs (1 or 0).
2446 */
LL_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)2447 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs)
2448 {
2449 return ((READ_BIT(RCC->APB2LPENR, Periphs) == Periphs) ? 1UL : 0UL);
2450 }
2451
2452 /**
2453 * @brief Disable APB2 peripheral clocks in Sleep mode
2454 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n
2455 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2456 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n
2457 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n
2458 * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n
2459 * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n
2460 * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n
2461 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n
2462 * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockSleep\n
2463 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2464 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n
2465 * APB2LPENR USBLPEN LL_APB2_GRP1_DisableClockSleep
2466 * @param Periphs This parameter can be a combination of the following values:
2467 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
2468 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2469 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2470 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2471 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2472 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
2473 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
2474 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
2475 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2476 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2477 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2478 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2479 * @arg @ref LL_APB2_GRP1_PERIPH_USB
2480 *
2481 * (*) : Not available for all stm32h5xxxx family lines.
2482 * @retval None
2483 */
LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)2484 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
2485 {
2486 CLEAR_BIT(RCC->APB2LPENR, Periphs);
2487 }
2488
2489 /**
2490 * @}
2491 */
2492
2493
2494 /** @defgroup BUS_LL_EF_APB3 APB3 Peripherals
2495 */
2496
2497 /**
2498 * @brief Enable APB3 peripherals clock.
2499 * @rmtoll APB3ENR SBSEN LL_APB3_GRP1_EnableClock\n
2500 * APB3ENR SPI5EN LL_APB3_GRP1_EnableClock\n
2501 * APB3ENR LPUART1EN LL_APB3_GRP1_EnableClock\n
2502 * APB3ENR I2C3EN LL_APB3_GRP1_EnableClock\n
2503 * APB3ENR I2C4EN LL_APB3_GRP1_EnableClock\n
2504 * APB3ENR LPTIM1EN LL_APB3_GRP1_EnableClock\n
2505 * APB3ENR LPTIM3EN LL_APB3_GRP1_EnableClock\n
2506 * APB3ENR LPTIM4EN LL_APB3_GRP1_EnableClock\n
2507 * APB3ENR LPTIM5EN LL_APB3_GRP1_EnableClock\n
2508 * APB3ENR LPTIM6EN LL_APB3_GRP1_EnableClock\n
2509 * APB3ENR VREFEN LL_APB3_GRP1_EnableClock\n
2510 * APB3ENR RTCAPBEN LL_APB3_GRP1_EnableClock
2511 * @param Periphs This parameter can be a combination of the following values:
2512 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2513 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2514 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2515 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2516 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2517 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2518 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2519 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2520 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2521 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2522 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2523 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2524 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2525 *
2526 * (*) : Not available for all stm32h5xxxx family lines.
2527 * @retval None
2528 */
LL_APB3_GRP1_EnableClock(uint32_t Periphs)2529 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
2530 {
2531 __IO uint32_t tmpreg;
2532 SET_BIT(RCC->APB3ENR, Periphs);
2533 /* Delay after an RCC peripheral clock enabling */
2534 tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
2535 (void)tmpreg;
2536 }
2537
2538 /**
2539 * @brief Check if APB3 peripheral clock is enabled or not
2540 * @rmtoll APB3ENR SBSEN LL_APB3_GRP1_IsEnabledClock\n
2541 * APB3ENR SPI5EN LL_APB3_GRP1_IsEnabledClock\n
2542 * APB3ENR LPUART1EN LL_APB3_GRP1_IsEnabledClock\n
2543 * APB3ENR I2C3EN LL_APB3_GRP1_IsEnabledClock\n
2544 * APB3ENR I2C4EN LL_APB3_GRP1_IsEnabledClock\n
2545 * APB3ENR LPTIM1EN LL_APB3_GRP1_IsEnabledClock\n
2546 * APB3ENR LPTIM3EN LL_APB3_GRP1_IsEnabledClock\n
2547 * APB3ENR LPTIM4EN LL_APB3_GRP1_IsEnabledClock\n
2548 * APB3ENR LPTIM5EN LL_APB3_GRP1_IsEnabledClock\n
2549 * APB3ENR LPTIM6EN LL_APB3_GRP1_IsEnabledClock\n
2550 * APB3ENR VREFEN LL_APB3_GRP1_IsEnabledClock\n
2551 * APB3ENR RTCAPBEN LL_APB3_GRP1_IsEnabledClock
2552 * @param Periphs This parameter can be a combination of the following values:
2553 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2554 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2555 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2556 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2557 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2558 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2559 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2560 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2561 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2562 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2563 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2564 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2565 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2566 *
2567 * (*) : Not available for all stm32h5xxxx family lines.
2568 * @retval State of Periphs (1 or 0).
2569 */
LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)2570 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
2571 {
2572 return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
2573 }
2574
2575 /**
2576 * @brief Disable APB2 peripherals clock.
2577 * @rmtoll APB3ENR SBSEN LL_APB3_GRP1_DisableClock\n
2578 * APB3ENR SPI5EN LL_APB3_GRP1_DisableClock\n
2579 * APB3ENR LPUART1EN LL_APB3_GRP1_DisableClock\n
2580 * APB3ENR I2C3EN LL_APB3_GRP1_DisableClock\n
2581 * APB3ENR I2C4EN LL_APB3_GRP1_DisableClock\n
2582 * APB3ENR LPTIM1EN LL_APB3_GRP1_DisableClock\n
2583 * APB3ENR LPTIM3EN LL_APB3_GRP1_DisableClock\n
2584 * APB3ENR LPTIM4EN LL_APB3_GRP1_DisableClock\n
2585 * APB3ENR LPTIM5EN LL_APB3_GRP1_DisableClock\n
2586 * APB3ENR LPTIM6EN LL_APB3_GRP1_DisableClock\n
2587 * APB3ENR VREFEN LL_APB3_GRP1_DisableClock\n
2588 * APB3ENR RTCAPBEN LL_APB3_GRP1_DisableClock
2589 * @param Periphs This parameter can be a combination of the following values:
2590 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2591 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2592 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2593 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2594 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2595 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2596 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2597 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2598 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2599 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2600 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2601 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2602 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2603 *
2604 * (*) : Not available for all stm32h5xxxx family lines.
2605 * @retval None
2606 */
LL_APB3_GRP1_DisableClock(uint32_t Periphs)2607 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
2608 {
2609 CLEAR_BIT(RCC->APB3ENR, Periphs);
2610 }
2611
2612 /**
2613 * @brief Force APB3 peripherals reset.
2614 * @rmtoll APB3RSTR SPI5RST LL_APB3_GRP1_ForceReset\n
2615 * APB3RSTR LPUART1RST LL_APB3_GRP1_ForceReset\n
2616 * APB3RSTR I2C3RST LL_APB3_GRP1_ForceReset\n
2617 * APB3RSTR I2C4RST LL_APB3_GRP1_ForceReset\n
2618 * APB3RSTR LPTIM1RST LL_APB3_GRP1_ForceReset\n
2619 * APB3RSTR LPTIM3RST LL_APB3_GRP1_ForceReset\n
2620 * APB3RSTR LPTIM4RST LL_APB3_GRP1_ForceReset\n
2621 * APB3RSTR LPTIM5RST LL_APB3_GRP1_ForceReset\n
2622 * APB3RSTR LPTIM6RST LL_APB3_GRP1_ForceReset\n
2623 * APB3RSTR VREFRST LL_APB3_GRP1_ForceReset
2624 * @param Periphs This parameter can be a combination of the following values:
2625 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2626 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2627 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2628 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2629 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2630 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2631 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2632 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2633 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2634 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2635 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2636 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2637 *
2638 * (*) : Not available for all stm32h5xxxx family lines.
2639 * @retval None
2640 */
LL_APB3_GRP1_ForceReset(uint32_t Periphs)2641 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
2642 {
2643 SET_BIT(RCC->APB3RSTR, Periphs);
2644 }
2645
2646 /**
2647 * @brief Release APB3 peripherals reset.
2648 * @rmtoll APB3RSTR SPI5RST LL_APB3_GRP1_ReleaseReset\n
2649 * APB3RSTR LPUART1RST LL_APB3_GRP1_ReleaseReset\n
2650 * APB3RSTR I2C3RST LL_APB3_GRP1_ReleaseReset\n
2651 * APB3RSTR I2C4RST LL_APB3_GRP1_ReleaseReset\n
2652 * APB3RSTR LPTIM1RST LL_APB3_GRP1_ReleaseReset\n
2653 * APB3RSTR LPTIM3RST LL_APB3_GRP1_ReleaseReset\n
2654 * APB3RSTR LPTIM4RST LL_APB3_GRP1_ReleaseReset\n
2655 * APB3RSTR LPTIM5RST LL_APB3_GRP1_ReleaseReset\n
2656 * APB3RSTR LPTIM6RST LL_APB3_GRP1_ReleaseReset\n
2657 * APB3RSTR VREFRST LL_APB3_GRP1_ReleaseReset
2658 * @param Periphs This parameter can be a combination of the following values:
2659 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2660 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2661 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2662 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2663 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2664 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2665 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2666 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2667 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2668 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2669 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2670 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2671 *
2672 * (*) : Not available for all stm32h5xxxx family lines.
2673 * @retval None
2674 */
LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)2675 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
2676 {
2677 CLEAR_BIT(RCC->APB3RSTR, Periphs);
2678 }
2679
2680 /**
2681 * @brief Enable APB3 peripheral clocks in Sleep mode
2682 * @rmtoll APB3LPENR SBSLPEN LL_APB3_GRP1_EnableClockSleep\n
2683 * APB3LPENR SPI5LPEN LL_APB3_GRP1_EnableClockSleep\n
2684 * APB3LPENR LPUART1LPEN LL_APB3_GRP1_EnableClockSleep\n
2685 * APB3LPENR I2C3LPEN LL_APB3_GRP1_EnableClockSleep\n
2686 * APB3LPENR I2C4LPEN LL_APB3_GRP1_EnableClockSleep\n
2687 * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_EnableClockSleep\n
2688 * APB3LPENR LPTIM3LPEN LL_APB3_GRP1_EnableClockSleep\n
2689 * APB3LPENR LPTIM4LPEN LL_APB3_GRP1_EnableClockSleep\n
2690 * APB3LPENR LPTIM5LPEN LL_APB3_GRP1_EnableClockSleep\n
2691 * APB3LPENR LPTIM6LPEN LL_APB3_GRP1_EnableClockSleep\n
2692 * APB3LPENR VREFLPEN LL_APB3_GRP1_EnableClockSleep\n
2693 * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_EnableClockSleep
2694 * @param Periphs This parameter can be a combination of the following values:
2695 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2696 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2697 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2698 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2699 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2700 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2701 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2702 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2703 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2704 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2705 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2706 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2707 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2708 *
2709 * (*) : Not available for all stm32h5xxxx family lines.
2710 * @retval None
2711 */
LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)2712 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
2713 {
2714 __IO uint32_t tmpreg;
2715 SET_BIT(RCC->APB3LPENR, Periphs);
2716 /* Delay after an RCC peripheral clock enabling */
2717 tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);
2718 (void)tmpreg;
2719 }
2720
2721
2722 /**
2723 * @brief Check if APB3 peripheral clocks in Sleep mode is enabled or not
2724 * @rmtoll APB3LPENR SBSLPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2725 * APB3LPENR SPI5LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2726 * APB3LPENR LPUART1LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2727 * APB3LPENR I2C3LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2728 * APB3LPENR I2C4LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2729 * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2730 * APB3LPENR LPTIM3LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2731 * APB3LPENR LPTIM4LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2732 * APB3LPENR LPTIM5LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2733 * APB3LPENR LPTIM6LPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2734 * APB3LPENR VREFLPEN LL_APB3_GRP1_IsEnabledClockSleep\n
2735 * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_IsEnabledClockSleep
2736 * @param Periphs This parameter can be a combination of the following values:
2737 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2738 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2739 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2740 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2741 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2742 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2743 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2744 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2745 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2746 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2747 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2748 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2749 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2750 *
2751 * (*) : Not available for all stm32h5xxxx family lines.
2752 * @retval State of Periphs (1 or 0).
2753 */
LL_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)2754 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs)
2755 {
2756 return ((READ_BIT(RCC->APB3LPENR, Periphs) == Periphs) ? 1UL : 0UL);
2757 }
2758
2759 /**
2760 * @brief Disable APB3 peripheral clocks in Sleep mode
2761 * @rmtoll APB3LPENR SBSLPEN LL_APB3_GRP1_DisableClockSleep\n
2762 * APB3LPENR SPI5LPEN LL_APB3_GRP1_DisableClockSleep\n
2763 * APB3LPENR LPUART1LPEN LL_APB3_GRP1_DisableClockSleep\n
2764 * APB3LPENR I2C3LPEN LL_APB3_GRP1_DisableClockSleep\n
2765 * APB3LPENR I2C4LPEN LL_APB3_GRP1_DisableClockSleep\n
2766 * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_DisableClockSleep\n
2767 * APB3LPENR LPTIM3LPEN LL_APB3_GRP1_DisableClockSleep\n
2768 * APB3LPENR LPTIM4LPEN LL_APB3_GRP1_DisableClockSleep\n
2769 * APB3LPENR LPTIM5LPEN LL_APB3_GRP1_DisableClockSleep\n
2770 * APB3LPENR LPTIM6LPEN LL_APB3_GRP1_DisableClockSleep\n
2771 * APB3LPENR VREFLPEN LL_APB3_GRP1_DisableClockSleep\n
2772 * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_DisableClockSleep
2773 * @param Periphs This parameter can be a combination of the following values:
2774 * @arg @ref LL_APB3_GRP1_PERIPH_ALL
2775 * @arg @ref LL_APB3_GRP1_PERIPH_SBS
2776 * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*)
2777 * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
2778 * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*)
2779 * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*)
2780 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
2781 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*)
2782 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*)
2783 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*)
2784 * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*)
2785 * @arg @ref LL_APB3_GRP1_PERIPH_VREF
2786 * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
2787 *
2788 * (*) : Not available for all stm32h5xxxx family lines.
2789 * @retval None
2790 */
LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)2791 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
2792 {
2793 CLEAR_BIT(RCC->APB3LPENR, Periphs);
2794 }
2795
2796 /**
2797 * @}
2798 */
2799
2800 /**
2801 * @}
2802 */
2803 #endif /* defined(RCC) */
2804
2805 /**
2806 * @}
2807 */
2808
2809 #ifdef __cplusplus
2810 }
2811 #endif
2812
2813 #endif /* __STM32H5xx_LL_BUS_H */
2814
