1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2022 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ##### RCC Limitations #####
20 ==============================================================================
21 [..]
22 A delay between an RCC peripheral clock enable and the effective peripheral
23 enabling should be taken into account in order to manage the peripheral read/write
24 from/to registers.
25 (+) This delay depends on the peripheral mapping.
26 (++) AHB & APB peripherals, 1 dummy read is necessary
27
28 [..]
29 Workarounds:
30 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
31 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
32
33 @endverbatim
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef STM32H7RSxx_LL_BUS_H
38 #define STM32H7RSxx_LL_BUS_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32h7rsxx.h"
46
47 /** @addtogroup STM32H7RSxx_LL_Driver
48 * @{
49 */
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private variables ---------------------------------------------------------*/
57
58 /* Private constants ---------------------------------------------------------*/
59
60 /* Private macros ------------------------------------------------------------*/
61
62 /* Exported types ------------------------------------------------------------*/
63
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN
73 #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN
74 #define LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN
75 #define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN
76 #define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN
77 #define LL_AHB1_GRP1_PERIPH_USBOTGHS RCC_AHB1ENR_OTGHSEN
78 #define LL_AHB1_GRP1_PERIPH_USBOTGFS RCC_AHB1ENR_OTGFSEN
79 #define LL_AHB1_GRP1_PERIPH_USBPHYC RCC_AHB1ENR_USBPHYCEN
80 #define LL_AHB1_GRP1_PERIPH_ADF1 RCC_AHB1ENR_ADF1EN
81 /**
82 * @}
83 */
84
85 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
86 * @{
87 */
88 #define LL_AHB2_GRP1_PERIPH_PSSI RCC_AHB2ENR_PSSIEN
89 #define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN
90 #define LL_AHB2_GRP1_PERIPH_CORDIC RCC_AHB2ENR_CORDICEN
91 #define LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_SRAM1EN
92 #define LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_SRAM2EN
93 /**
94 * @}
95 */
96
97 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
98 * @{
99 */
100 #define LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN
101 #define LL_AHB3_GRP1_PERIPH_HASH RCC_AHB3ENR_HASHEN
102 #if defined(CRYP)
103 #define LL_AHB3_GRP1_PERIPH_CRYP RCC_AHB3ENR_CRYPEN
104 #endif /* CRYP */
105 #if defined(SAES)
106 #define LL_AHB3_GRP1_PERIPH_SAES RCC_AHB3ENR_SAESEN
107 #endif /* SAES */
108 #define LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN
109 /**
110 * @}
111 */
112
113 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH
114 * @{
115 */
116 #define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN
117 #define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN
118 #define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN
119 #define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN
120 #define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN
121 #define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN
122 #define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN
123 #define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN
124 #define LL_AHB4_GRP1_PERIPH_GPIOM RCC_AHB4ENR_GPIOMEN
125 #define LL_AHB4_GRP1_PERIPH_GPION RCC_AHB4ENR_GPIONEN
126 #define LL_AHB4_GRP1_PERIPH_GPIOO RCC_AHB4ENR_GPIOOEN
127 #define LL_AHB4_GRP1_PERIPH_GPIOP RCC_AHB4ENR_GPIOPEN
128 #define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN
129 #define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN
130 /**
131 * @}
132 */
133
134 /** @defgroup BUS_LL_EC_AHB5_GRP1_PERIPH AHB5 GRP1 PERIPH
135 * @{
136 */
137 #define LL_AHB5_GRP1_PERIPH_HPDMA1 RCC_AHB5ENR_HPDMA1EN
138 #define LL_AHB5_GRP1_PERIPH_DMA2D RCC_AHB5ENR_DMA2DEN
139 #define LL_AHB5_GRP1_PERIPH_JPEG RCC_AHB5ENR_JPEGEN
140 #define LL_AHB5_GRP1_PERIPH_FMC RCC_AHB5ENR_FMCEN
141 #define LL_AHB5_GRP1_PERIPH_XSPI1 RCC_AHB5ENR_XSPI1EN
142 #define LL_AHB5_GRP1_PERIPH_XSPI2 RCC_AHB5ENR_XSPI2EN
143 #define LL_AHB5_GRP1_PERIPH_XSPIM RCC_AHB5ENR_XSPIMEN
144 #define LL_AHB5_GRP1_PERIPH_SDMMC1 RCC_AHB5ENR_SDMMC1EN
145 #define LL_AHB5_GRP1_PERIPH_GFXMMU RCC_AHB5ENR_GFXMMUEN
146 #if defined(GPU2D)
147 #define LL_AHB5_GRP1_PERIPH_GPU2D RCC_AHB5ENR_GPU2DEN
148 #endif /* GPU2D */
149
150 #define LL_AHB5_GRP1_PERIPH_FLASH RCC_AHB5LPENR_FLASHLPEN
151 #define LL_AHB5_GRP1_PERIPH_AXISRAM RCC_AHB5LPENR_AXISRAMLPEN
152 #define LL_AHB5_GRP1_PERIPH_DTCM1 RCC_AHB5LPENR_DTCM1LPEN
153 #define LL_AHB5_GRP1_PERIPH_DTCM2 RCC_AHB5LPENR_DTCM2LPEN
154 #define LL_AHB5_GRP1_PERIPH_ITCM RCC_AHB5LPENR_ITCMLPEN
155 /**
156 * @}
157 */
158
159 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
160 * @{
161 */
162 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
163 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
164 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
165 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
166 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
167 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
168 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR1_TIM12EN
169 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR1_TIM13EN
170 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR1_TIM14EN
171 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
172 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
173 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
174 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
175 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR1_SPDIFRXEN
176 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
177 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
178 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
179 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
180 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1_I3C1EN
181 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
182 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
183 #define LL_APB1_GRP1_PERIPH_I3C1 RCC_APB1ENR1_I2C1_I3C1EN
184 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR1_CECEN
185 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR1_UART7EN
186 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR1_UART8EN
187 /**
188 * @}
189 */
190
191 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
192 * @{
193 */
194 #define LL_APB1_GRP2_PERIPH_CRS RCC_APB1ENR2_CRSEN
195 #define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1ENR2_MDIOSEN
196 #define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1ENR2_FDCANEN
197 #define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
198 /**
199 * @}
200 */
201
202 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
203 * @{
204 */
205 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
206 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
207 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
208 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
209 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
210 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
211 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
212 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
213 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
214 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
215 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
216 /**
217 * @}
218 */
219
220 /** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH
221 * @{
222 */
223 #define LL_APB4_GRP1_PERIPH_SBS RCC_APB4ENR_SBSEN
224 #define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN
225 #define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN
226 #define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN
227 #define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN
228 #define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN
229 #define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN
230 #define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN
231 #define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN
232 #define LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN
233 /**
234 * @}
235 */
236
237 /** @defgroup BUS_LL_EC_APB5_GRP1_PERIPH APB5 GRP1 PERIPH
238 * @{
239 */
240 #if defined(LTDC)
241 #define LL_APB5_GRP1_PERIPH_LTDC RCC_APB5ENR_LTDCEN
242 #endif /* LTDC */
243 #define LL_APB5_GRP1_PERIPH_DCMIPP RCC_APB5ENR_DCMIPPEN
244 #define LL_APB5_GRP1_PERIPH_GFXTIM RCC_APB5ENR_GFXTIMEN
245 /**
246 * @}
247 */
248
249 /** @defgroup BUS_LL_EC_CKGA_PERIPH CKGA (AXI Clocks Gating) PERIPH
250 * @{
251 */
252 #define LL_CKGA_PERIPH_AXI RCC_CKGDISR_AXICKG
253 #define LL_CKGA_PERIPH_AHBM RCC_CKGDISR_AHBMCKG
254 #define LL_CKGA_PERIPH_SDMMC1 RCC_CKGDISR_SDMMC1CKG
255 #define LL_CKGA_PERIPH_HPDMA1 RCC_CKGDISR_HPDMA1CKG
256 #define LL_CKGA_PERIPH_CPU RCC_CKGDISR_CPUCKG
257 #if defined(GPU2D)
258 #define LL_CKGA_PERIPH_GPU2DS1 RCC_CKGDISR_GPU2DS1CKG
259 #define LL_CKGA_PERIPH_GPU2DS0 RCC_CKGDISR_GPU2DS0CKG
260 #define LL_CKGA_PERIPH_GPU2DCL RCC_CKGDISR_GPU2DCLCKG
261 #endif /* GPU2D */
262 #define LL_CKGA_PERIPH_DCMIPP RCC_CKGDISR_DCMIPPCKG
263 #define LL_CKGA_PERIPH_DMA2D RCC_CKGDISR_DMA2DCKG
264 #define LL_CKGA_PERIPH_GFXMMUS RCC_CKGDISR_GFXMMUSCKG
265 #if defined(LTDC)
266 #define LL_CKGA_PERIPH_LTDC RCC_CKGDISR_LTDCCKG
267 #endif /* LTDC */
268 #define LL_CKGA_PERIPH_GFXMMUM RCC_CKGDISR_GFXMMUMCKG
269 #define LL_CKGA_PERIPH_AHBS RCC_CKGDISR_AHBSCKG
270 #define LL_CKGA_PERIPH_FMC RCC_CKGDISR_FMCCKG
271 #define LL_CKGA_PERIPH_XSPI1 RCC_CKGDISR_XSPI1CKG
272 #define LL_CKGA_PERIPH_XSPI2 RCC_CKGDISR_XSPI2CKG
273 #define LL_CKGA_PERIPH_AXIRAM1 RCC_CKGDISR_AXISRAM1CKG
274 #define LL_CKGA_PERIPH_AXIRAM2 RCC_CKGDISR_AXISRAM2CKG
275 #define LL_CKGA_PERIPH_AXIRAM3 RCC_CKGDISR_AXISRAM3CKG
276 #define LL_CKGA_PERIPH_AXIRAM4 RCC_CKGDISR_AXISRAM4CKG
277 #define LL_CKGA_PERIPH_FLASH RCC_CKGDISR_FLASHCKG
278 #define LL_CKGA_PERIPH_EXTI RCC_CKGDISR_EXTICKG
279 #define LL_CKGA_PERIPH_JTAG RCC_CKGDISR_JTAGCKG
280 /**
281 * @}
282 */
283
284 /**
285 * @}
286 */
287 /* Exported macro ------------------------------------------------------------*/
288
289 /* Exported functions --------------------------------------------------------*/
290
291 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
292 * @{
293 */
294
295 /** @defgroup BUS_LL_EF_AHB1 AHB1
296 * @{
297 */
298
299 /**
300 * @brief Enable AHB1 peripherals clock.
301 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n
302 * AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n
303 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n
304 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n
305 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n
306 * AHB1ENR OTGFSEN LL_AHB1_GRP1_EnableClock\n
307 * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
308 * AHB1ENR USBPHYCEN LL_AHB1_GRP1_EnableClock\n
309 * AHB1ENR ADF1EN LL_AHB1_GRP1_EnableClock
310 * @param Periphs This parameter can be a combination of the following values:
311 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
312 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
313 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
314 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
315 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
316 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS
317 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS
318 * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC
319 * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1
320 * @retval None
321 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)322 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
323 {
324 __IO uint32_t tmpreg;
325 SET_BIT(RCC->AHB1ENR, Periphs);
326 /* Delay after an RCC peripheral clock enabling */
327 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
328 (void)tmpreg;
329 }
330
331 /**
332 * @brief Check if AHB1 peripheral clock is enabled or not
333 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n
334 * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n
335 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock\n
336 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock\n
337 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock\n
338 * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
339 * AHB1ENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n
340 * AHB1ENR USBPHYCEN LL_AHB1_GRP1_IsEnabledClock\n
341 * AHB1ENR ADF1EN LL_AHB1_GRP1_IsEnabledClock
342 * @param Periphs This parameter can be a combination of the following values:
343 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
344 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
345 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
346 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
347 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
348 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS
349 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS
350 * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC
351 * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1
352 * @retval uint32_t
353 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)354 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
355 {
356 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U);
357 }
358
359 /**
360 * @brief Disable AHB1 peripherals clock.
361 * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n
362 * AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n
363 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n
364 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n
365 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n
366 * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
367 * AHB1ENR OTGFSEN LL_AHB1_GRP1_DisableClock\n
368 * AHB1ENR USBPHYCEN LL_AHB1_GRP1_DisableClock\n
369 * AHB1ENR ADF1EN LL_AHB1_GRP1_DisableClock
370 * @param Periphs This parameter can be a combination of the following values:
371 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
372 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
373 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
374 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
375 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
376 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS
377 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS
378 * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC
379 * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1
380 * @retval None
381 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)382 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
383 {
384 CLEAR_BIT(RCC->AHB1ENR, Periphs);
385 }
386
387 /**
388 * @brief Force AHB1 peripherals reset.
389 * @rmtoll AHB1RSTR GPDMA1RST LL_AHB1_GRP1_ForceReset\n
390 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset\n
391 * AHB1RSTR ETH1RST LL_AHB1_GRP1_ForceReset\n
392 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset\n
393 * AHB1RSTR OTGFSRST LL_AHB1_GRP1_ForceReset\n
394 * AHB1RSTR USBPHYCRST LL_AHB1_GRP1_ForceReset\n
395 * AHB1RSTR ADF1RST LL_AHB1_GRP1_ForceReset
396 * @param Periphs This parameter can be a combination of the following values:
397 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
398 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
399 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
400 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS
401 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS
402 * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC
403 * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1
404 * @retval None
405 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)406 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
407 {
408 SET_BIT(RCC->AHB1RSTR, Periphs);
409 }
410
411 /**
412 * @brief Release AHB1 peripherals reset.
413 * @rmtoll AHB1RSTR GPDMA1RST LL_AHB1_GRP1_ReleaseReset\n
414 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n
415 * AHB1RSTR ETH1RST LL_AHB1_GRP1_ReleaseReset\n
416 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset\n
417 * AHB1RSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset\n
418 * AHB1RSTR USBPHYCRST LL_AHB1_GRP1_ReleaseReset\n
419 * AHB1RSTR ADF1RST LL_AHB1_GRP1_ReleaseReset
420 * @param Periphs This parameter can be a combination of the following values:
421 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
422 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
423 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
424 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS
425 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS
426 * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC
427 * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1
428 * @retval None
429 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)430 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
431 {
432 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
433 }
434
435 /**
436 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
437 * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
438 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep\n
439 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep\n
440 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep\n
441 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep\n
442 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n
443 * AHB1LPENR OTGFSLPEN LL_AHB1_GRP1_EnableClockSleep\n
444 * AHB1LPENR USBPHYCLPEN LL_AHB1_GRP1_EnableClockSleep\n
445 * AHB1LPENR ADF1LPEN LL_AHB1_GRP1_EnableClockSleep
446 * @param Periphs This parameter can be a combination of the following values:
447 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
448 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
449 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
450 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
451 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
452 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS
453 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS
454 * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC
455 * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1
456 * @retval None
457 */
LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)458 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
459 {
460 __IO uint32_t tmpreg;
461 SET_BIT(RCC->AHB1LPENR, Periphs);
462 /* Delay after an RCC peripheral clock enabling */
463 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
464 (void)tmpreg;
465 }
466
467 /**
468 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
469 * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
470 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep\n
471 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep\n
472 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep\n
473 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep\n
474 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n
475 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n
476 * AHB1LPENR USBPHYCLPEN LL_AHB1_GRP1_DisableClockSleep\n
477 * AHB1LPENR ADF1LPEN LL_AHB1_GRP1_DisableClockSleep
478 * @param Periphs This parameter can be a combination of the following values:
479 * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
480 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
481 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
482 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
483 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
484 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS
485 * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS
486 * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC
487 * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1
488 * @retval None
489 */
LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)490 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
491 {
492 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
493 }
494
495 /**
496 * @}
497 */
498
499 /** @defgroup BUS_LL_EF_AHB2 AHB2
500 * @{
501 */
502
503 /**
504 * @brief Enable AHB2 peripherals clock.
505 * @rmtoll AHB2ENR PSSIEN LL_AHB2_GRP1_EnableClock\n
506 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n
507 * AHB2ENR CORDICEN LL_AHB2_GRP1_EnableClock\n
508 * AHB2ENR AHBSRAM1EN LL_AHB2_GRP1_EnableClock\n
509 * AHB2ENR AHBSRAM2EN LL_AHB2_GRP1_EnableClock
510 * @param Periphs This parameter can be a combination of the following values:
511 * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI
512 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
513 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC
514 * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM1
515 * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM2
516 * @retval None
517 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)518 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
519 {
520 __IO uint32_t tmpreg;
521 SET_BIT(RCC->AHB2ENR, Periphs);
522 /* Delay after an RCC peripheral clock enabling */
523 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
524 (void)tmpreg;
525 }
526
527 /**
528 * @brief Check if AHB2 peripheral clock is enabled or not
529 * @rmtoll AHB2ENR PSSIEN LL_AHB2_GRP1_IsEnabledClock\n
530 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n
531 * AHB2ENR CORDICEN LL_AHB2_GRP1_IsEnabledClock\n
532 * AHB2ENR AHBSRAM1EN LL_AHB2_GRP1_IsEnabledClock\n
533 * AHB2ENR AHBSRAM2EN LL_AHB2_GRP1_IsEnabledClock
534 * @param Periphs This parameter can be a combination of the following values:
535 * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI
536 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
537 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC
538 * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM1
539 * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM2
540 * @retval uint32_t
541 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)542 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
543 {
544 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U);
545 }
546
547 /**
548 * @brief Disable AHB2 peripherals clock.
549 * @rmtoll AHB2ENR PSSIEN LL_AHB2_GRP1_DisableClock\n
550 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n
551 * AHB2ENR CORDICEN LL_AHB2_GRP1_DisableClock\n
552 * AHB2ENR AHBSRAM1EN LL_AHB2_GRP1_DisableClock\n
553 * AHB2ENR AHBSRAM2EN LL_AHB2_GRP1_DisableClock
554 * @param Periphs This parameter can be a combination of the following values:
555 * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI
556 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
557 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC
558 * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM1
559 * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM2
560 * @retval None
561 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)562 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
563 {
564 CLEAR_BIT(RCC->AHB2ENR, Periphs);
565 }
566
567 /**
568 * @brief Force AHB2 peripherals reset.
569 * @rmtoll AHB2RSTR PSSIRST LL_AHB2_GRP1_ForceReset\n
570 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n
571 * AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset
572 * @param Periphs This parameter can be a combination of the following values:
573 * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI
574 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
575 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC
576 * @retval None
577 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)578 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
579 {
580 SET_BIT(RCC->AHB2RSTR, Periphs);
581 }
582
583 /**
584 * @brief Release AHB2 peripherals reset.
585 * @rmtoll AHB2RSTR PSSIRST LL_AHB2_GRP1_ReleaseReset\n
586 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n
587 * AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset
588 * @param Periphs This parameter can be a combination of the following values:
589 * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI
590 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
591 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC
592 * @retval None
593 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)594 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
595 {
596 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
597 }
598
599 /**
600 * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode.
601 * @rmtoll AHB2LPENR PSSILPEN LL_AHB2_GRP1_EnableClockSleep\n
602 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n
603 * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_EnableClockSleep\n
604 * AHB2LPENR AHBSRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n
605 * AHB2LPENR AHBSRAM2LPEN LL_AHB2_GRP1_EnableClockSleep
606 * @param Periphs This parameter can be a combination of the following values:
607 * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI
608 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
609 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC
610 * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM1
611 * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM2
612 * @retval None
613 */
LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)614 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
615 {
616 __IO uint32_t tmpreg;
617 SET_BIT(RCC->AHB2LPENR, Periphs);
618 /* Delay after an RCC peripheral clock enabling */
619 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
620 (void)tmpreg;
621 }
622
623 /**
624 * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode.
625 * @rmtoll AHB2LPENR PSSILPEN LL_AHB2_GRP1_DisableClockSleep\n
626 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep\n
627 * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_DisableClockSleep\n
628 * AHB2LPENR AHBSRAM1LPEN LL_AHB2_GRP1_DisableClockSleep\n
629 * AHB2LPENR AHBSRAM2LPEN LL_AHB2_GRP1_DisableClockSleep
630 * @param Periphs This parameter can be a combination of the following values:
631 * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI
632 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
633 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC
634 * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM1
635 * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM2
636 * @retval None
637 */
LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)638 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
639 {
640 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
641 }
642
643 /**
644 * @}
645 */
646
647 /** @defgroup BUS_LL_EF_AHB3 AHB3
648 * @{
649 */
650
651 /**
652 * @brief Enable AHB3 peripherals clock.
653 * @rmtoll AHB3ENR RNGEN LL_AHB3_GRP1_EnableClock\n
654 * AHB3ENR HASHEN LL_AHB3_GRP1_EnableClock\n
655 * AHB3ENR CRYPEN LL_AHB3_GRP1_EnableClock\n
656 * AHB3ENR SAESEN LL_AHB3_GRP1_EnableClock\n
657 * AHB3ENR PKAEN LL_AHB3_GRP1_EnableClock
658 * @param Periphs This parameter can be a combination of the following values:
659 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
660 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
661 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
662 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
663 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
664 *
665 * (*) value not defined in all devices.
666 * @retval None
667 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)668 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
669 {
670 __IO uint32_t tmpreg;
671 SET_BIT(RCC->AHB3ENR, Periphs);
672 /* Delay after an RCC peripheral clock enabling */
673 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
674 (void)tmpreg;
675 }
676
677 /**
678 * @brief Check if AHB3 peripheral clock is enabled or not
679 * @rmtoll AHB3ENR RNGEN LL_AHB3_GRP1_IsEnabledClock\n
680 * AHB3ENR HASHEN LL_AHB3_GRP1_IsEnabledClock\n
681 * AHB3ENR CRYPEN LL_AHB3_GRP1_IsEnabledClock\n
682 * AHB3ENR SAESEN LL_AHB3_GRP1_IsEnabledClock\n
683 * AHB3ENR PKAEN LL_AHB3_GRP1_IsEnabledClock
684 * @param Periphs This parameter can be a combination of the following values:
685 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
686 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
687 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
688 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
689 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
690 *
691 * (*) value not defined in all devices.
692 * @retval uint32_t
693 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)694 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
695 {
696 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U);
697 }
698
699 /**
700 * @brief Disable AHB3 peripherals clock.
701 * @rmtoll AHB3ENR RNGEN LL_AHB3_GRP1_DisableClock\n
702 * AHB3ENR HASHEN LL_AHB3_GRP1_DisableClock\n
703 * AHB3ENR CRYPEN LL_AHB3_GRP1_DisableClock\n
704 * AHB3ENR SAESEN LL_AHB3_GRP1_DisableClock\n
705 * AHB3ENR PKAEN LL_AHB3_GRP1_DisableClock
706 * @param Periphs This parameter can be a combination of the following values:
707 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
708 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
709 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
710 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
711 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
712 *
713 * (*) value not defined in all devices.
714 * @retval None
715 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)716 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
717 {
718 CLEAR_BIT(RCC->AHB3ENR, Periphs);
719 }
720
721 /**
722 * @brief Enable AHB3 peripherals clock.
723 * @rmtoll AHB3RSTR RNGRST LL_AHB3_GRP1_ForceReset\n
724 * AHB3RSTR HASHRST LL_AHB3_GRP1_ForceReset\n
725 * AHB3RSTR CRYPRST LL_AHB3_GRP1_ForceReset\n
726 * AHB3RSTR SAESRST LL_AHB3_GRP1_ForceReset\n
727 * AHB3RSTR PKARST LL_AHB3_GRP1_ForceReset
728 * @param Periphs This parameter can be a combination of the following values:
729 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
730 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
731 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
732 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
733 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
734 *
735 * (*) value not defined in all devices.
736 * @retval None
737 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)738 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
739 {
740 SET_BIT(RCC->AHB3RSTR, Periphs);
741 }
742
743 /**
744 * @brief Release AHB3 peripherals reset.
745 * @rmtoll AHB3RSTR RNGRST LL_AHB3_GRP1_ReleaseReset\n
746 * AHB3RSTR HASHRST LL_AHB3_GRP1_ReleaseReset\n
747 * AHB3RSTR CRYPRST LL_AHB3_GRP1_ReleaseReset\n
748 * AHB3RSTR SAESRST LL_AHB3_GRP1_ReleaseReset\n
749 * AHB3RSTR PKARST LL_AHB3_GRP1_ReleaseReset
750 * @param Periphs This parameter can be a combination of the following values:
751 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
752 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
753 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
754 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
755 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
756 *
757 * (*) value not defined in all devices.
758 * @retval None
759 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)760 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
761 {
762 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
763 }
764
765 /**
766 * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode.
767 * @rmtoll AHB3LPENR RNGLPEN LL_AHB3_GRP1_EnableClockSleep\n
768 * AHB3LPENR HASHLPEN LL_AHB3_GRP1_EnableClockSleep\n
769 * AHB3LPENR CRYPLPEN LL_AHB3_GRP1_EnableClockSleep\n
770 * AHB3LPENR SAESLPEN LL_AHB3_GRP1_EnableClockSleep\n
771 * AHB3LPENR PKALPEN LL_AHB3_GRP1_EnableClockSleep
772 * @param Periphs This parameter can be a combination of the following values:
773 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
774 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
775 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
776 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
777 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
778 *
779 * (*) value not defined in all devices.
780 * @retval None
781 */
LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)782 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
783 {
784 __IO uint32_t tmpreg;
785 SET_BIT(RCC->AHB3LPENR, Periphs);
786 /* Delay after an RCC peripheral clock enabling */
787 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
788 (void)tmpreg;
789 }
790
791 /**
792 * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode.
793 * @rmtoll AHB3LPENR RNGLPEN LL_AHB3_GRP1_DisableClockSleep\n
794 * AHB3LPENR HASHLPEN LL_AHB3_GRP1_DisableClockSleep\n
795 * AHB3LPENR CRYPLPEN LL_AHB3_GRP1_DisableClockSleep\n
796 * AHB3LPENR SAESLPEN LL_AHB3_GRP1_DisableClockSleep\n
797 * AHB3LPENR PKALPEN LL_AHB3_GRP1_DisableClockSleep
798 * @param Periphs This parameter can be a combination of the following values:
799 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
800 * @arg @ref LL_AHB3_GRP1_PERIPH_HASH
801 * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
802 * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
803 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
804 *
805 * (*) value not defined in all devices.
806 * @retval None
807 */
LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)808 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
809 {
810 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
811 }
812
813 /**
814 * @}
815 */
816
817 /** @defgroup BUS_LL_EF_AHB4 AHB4
818 * @{
819 */
820
821 /**
822 * @brief Enable AHB4 peripherals clock.
823 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock\n
824 * AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock\n
825 * AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock\n
826 * AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock\n
827 * AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock\n
828 * AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n
829 * AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n
830 * AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n
831 * AHB4ENR GPIOMEN LL_AHB4_GRP1_EnableClock\n
832 * AHB4ENR GPIONEN LL_AHB4_GRP1_EnableClock\n
833 * AHB4ENR GPIOOEN LL_AHB4_GRP1_EnableClock\n
834 * AHB4ENR GPIOPEN LL_AHB4_GRP1_EnableClock\n
835 * AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n
836 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock
837 * @param Periphs This parameter can be a combination of the following values:
838 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
839 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
840 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
841 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
842 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
843 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
844 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
845 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
846 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM
847 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
848 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
849 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
850 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
851 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
852 * @retval None
853 */
LL_AHB4_GRP1_EnableClock(uint32_t Periphs)854 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
855 {
856 __IO uint32_t tmpreg;
857 SET_BIT(RCC->AHB4ENR, Periphs);
858 /* Delay after an RCC peripheral clock enabling */
859 tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
860 (void)tmpreg;
861 }
862
863 /**
864 * @brief Check if AHB4 peripheral clock is enabled or not
865 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n
866 * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n
867 * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n
868 * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n
869 * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n
870 * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n
871 * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n
872 * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n
873 * AHB4ENR GPIOMEN LL_AHB4_GRP1_IsEnabledClock\n
874 * AHB4ENR GPIONEN LL_AHB4_GRP1_IsEnabledClock\n
875 * AHB4ENR GPIOOEN LL_AHB4_GRP1_IsEnabledClock\n
876 * AHB4ENR GPIOPEN LL_AHB4_GRP1_IsEnabledClock\n
877 * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n
878 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock
879 * @param Periphs This parameter can be a combination of the following values:
880 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
881 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
882 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
883 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
884 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
885 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
886 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
887 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
888 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM
889 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
890 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
891 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
892 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
893 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
894 * @retval uint32_t
895 */
LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)896 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
897 {
898 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1U : 0U);
899 }
900
901 /**
902 * @brief Disable AHB4 peripherals clock.
903 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock\n
904 * AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock\n
905 * AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock\n
906 * AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock\n
907 * AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock\n
908 * AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n
909 * AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n
910 * AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n
911 * AHB4ENR GPIOMEN LL_AHB4_GRP1_DisableClock\n
912 * AHB4ENR GPIONEN LL_AHB4_GRP1_DisableClock\n
913 * AHB4ENR GPIOOEN LL_AHB4_GRP1_DisableClock\n
914 * AHB4ENR GPIOPEN LL_AHB4_GRP1_DisableClock\n
915 * AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n
916 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock
917 * @param Periphs This parameter can be a combination of the following values:
918 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
919 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
920 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
921 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
922 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
923 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
924 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
925 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
926 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM
927 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
928 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
929 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
930 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
931 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
932 * @retval None
933 */
LL_AHB4_GRP1_DisableClock(uint32_t Periphs)934 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
935 {
936 CLEAR_BIT(RCC->AHB4ENR, Periphs);
937 }
938
939 /**
940 * @brief Force AHB4 peripherals reset.
941 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset\n
942 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset\n
943 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset\n
944 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset\n
945 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset\n
946 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n
947 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n
948 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n
949 * AHB4RSTR GPIOMRST LL_AHB4_GRP1_ForceReset\n
950 * AHB4RSTR GPIONRST LL_AHB4_GRP1_ForceReset\n
951 * AHB4RSTR GPIOORST LL_AHB4_GRP1_ForceReset\n
952 * AHB4RSTR GPIOPRST LL_AHB4_GRP1_ForceReset\n
953 * AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n
954 * AHB4RSTR BKPRAMRST LL_AHB4_GRP1_ForceReset
955 * @param Periphs This parameter can be a combination of the following values:
956 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
957 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
958 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
959 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
960 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
961 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
962 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
963 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
964 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM
965 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
966 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
967 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
968 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
969 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
970 * @retval None
971 */
LL_AHB4_GRP1_ForceReset(uint32_t Periphs)972 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
973 {
974 SET_BIT(RCC->AHB4RSTR, Periphs);
975 }
976
977 /**
978 * @brief Release AHB4 peripherals reset.
979 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset\n
980 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset\n
981 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset\n
982 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset\n
983 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset\n
984 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n
985 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n
986 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n
987 * AHB4RSTR GPIOMRST LL_AHB4_GRP1_ReleaseReset\n
988 * AHB4RSTR GPIONRST LL_AHB4_GRP1_ReleaseReset\n
989 * AHB4RSTR GPIOORST LL_AHB4_GRP1_ReleaseReset\n
990 * AHB4RSTR GPIOPRST LL_AHB4_GRP1_ReleaseReset\n
991 * AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset
992 * @param Periphs This parameter can be a combination of the following values:
993 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
994 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
995 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
996 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
997 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
998 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
999 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1000 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1001 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM
1002 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
1003 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
1004 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
1005 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
1006 * @retval None
1007 */
LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)1008 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
1009 {
1010 CLEAR_BIT(RCC->AHB4RSTR, Periphs);
1011 }
1012
1013 /**
1014 * @brief Enable AHB4 peripherals clock during Low Power (Sleep) mode.
1015 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep\n
1016 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep\n
1017 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep\n
1018 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep\n
1019 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep\n
1020 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n
1021 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n
1022 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n
1023 * AHB4LPENR GPIOMLPEN LL_AHB4_GRP1_EnableClockSleep\n
1024 * AHB4LPENR GPIONLPEN LL_AHB4_GRP1_EnableClockSleep\n
1025 * AHB4LPENR GPIOOLPEN LL_AHB4_GRP1_EnableClockSleep\n
1026 * AHB4LPENR GPIOPLPEN LL_AHB4_GRP1_EnableClockSleep\n
1027 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n
1028 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep
1029 * @param Periphs This parameter can be a combination of the following values:
1030 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1031 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1032 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1033 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1034 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1035 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1036 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1037 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1038 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM
1039 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
1040 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
1041 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
1042 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
1043 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1044 * @retval None
1045 */
LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)1046 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
1047 {
1048 __IO uint32_t tmpreg;
1049 SET_BIT(RCC->AHB4LPENR, Periphs);
1050 /* Delay after an RCC peripheral clock enabling */
1051 tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
1052 (void)tmpreg;
1053 }
1054
1055 /**
1056 * @brief Disable AHB4 peripherals clock during Low Power (Sleep) mode.
1057 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep\n
1058 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep\n
1059 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep\n
1060 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep\n
1061 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep\n
1062 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n
1063 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n
1064 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n
1065 * AHB4LPENR GPIOMLPEN LL_AHB4_GRP1_DisableClockSleep\n
1066 * AHB4LPENR GPIONLPEN LL_AHB4_GRP1_DisableClockSleep\n
1067 * AHB4LPENR GPIOOLPEN LL_AHB4_GRP1_DisableClockSleep\n
1068 * AHB4LPENR GPIOPLPEN LL_AHB4_GRP1_DisableClockSleep\n
1069 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n
1070 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep
1071 * @param Periphs This parameter can be a combination of the following values:
1072 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1073 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1074 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1075 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1076 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1077 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1078 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1079 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1080 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM
1081 * @arg @ref LL_AHB4_GRP1_PERIPH_GPION
1082 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
1083 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
1084 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
1085 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1086 * @retval None
1087 */
LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)1088 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
1089 {
1090 CLEAR_BIT(RCC->AHB4LPENR, Periphs);
1091 }
1092
1093 /**
1094 * @}
1095 */
1096
1097 /** @defgroup BUS_LL_EF_AHB5 AHB5
1098 * @{
1099 */
1100
1101 /**
1102 * @brief Enable AHB5 peripherals clock.
1103 * @rmtoll AHB5ENR HPDMA1EN LL_AHB5_GRP1_EnableClock\n
1104 * AHB5ENR DMA2DEN LL_AHB5_GRP1_EnableClock\n
1105 * AHB5ENR JPEGEN LL_AHB5_GRP1_EnableClock\n
1106 * AHB5ENR FMCEN LL_AHB5_GRP1_EnableClock\n
1107 * AHB5ENR XSPI1EN LL_AHB5_GRP1_EnableClock\n
1108 * AHB5ENR XSPI2EN LL_AHB5_GRP1_EnableClock\n
1109 * AHB5ENR XSPIMEN LL_AHB5_GRP1_EnableClock\n
1110 * AHB5ENR SDMMC1EN LL_AHB5_GRP1_EnableClock\n
1111 * AHB5ENR GFXMMUEN LL_AHB5_GRP1_EnableClock\n
1112 * AHB5ENR GPU2DEN LL_AHB5_GRP1_EnableClock
1113 * @param Periphs This parameter can be a combination of the following values:
1114 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1115 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1116 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*)
1117 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1118 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1119 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1120 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1121 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1122 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*)
1123 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*)
1124 *
1125 * (*) value not defined in all devices.
1126 * @retval None
1127 */
LL_AHB5_GRP1_EnableClock(uint32_t Periphs)1128 __STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs)
1129 {
1130 __IO uint32_t tmpreg;
1131 SET_BIT(RCC->AHB5ENR, Periphs);
1132 /* Delay after an RCC peripheral clock enabling */
1133 tmpreg = READ_BIT(RCC->AHB5ENR, Periphs);
1134 (void)tmpreg;
1135 }
1136
1137 /**
1138 * @brief Check if AHB5 peripheral clock is enabled or not
1139 * @rmtoll AHB5ENR HPDMA1EN LL_AHB5_GRP1_IsEnabledClock\n
1140 * AHB5ENR DMA2DEN LL_AHB5_GRP1_IsEnabledClock\n
1141 * AHB5ENR JPEGEN LL_AHB5_GRP1_IsEnabledClock\n
1142 * AHB5ENR FMCEN LL_AHB5_GRP1_IsEnabledClock\n
1143 * AHB5ENR XSPI1EN LL_AHB5_GRP1_IsEnabledClock\n
1144 * AHB5ENR XSPI2EN LL_AHB5_GRP1_IsEnabledClock\n
1145 * AHB5ENR XSPIMEN LL_AHB5_GRP1_IsEnabledClock\n
1146 * AHB5ENR SDMMC1EN LL_AHB5_GRP1_IsEnabledClock\n
1147 * AHB5ENR GFXMMUEN LL_AHB5_GRP1_IsEnabledClock\n
1148 * AHB5ENR GPU2DEN LL_AHB5_GRP1_IsEnabledClock
1149 * @param Periphs This parameter can be a combination of the following values:
1150 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1151 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1152 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*)
1153 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1154 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1155 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1156 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1157 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1158 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*)
1159 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*)
1160 *
1161 * (*) value not defined in all devices.
1162 * @retval uint32_t
1163 */
LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)1164 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)
1165 {
1166 return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1U : 0U);
1167 }
1168
1169 /**
1170 * @brief Disable AHB5 peripherals clock.
1171 * @rmtoll AHB5ENR HPDMA1EN LL_AHB5_GRP1_DisableClock\n
1172 * AHB5ENR DMA2DEN LL_AHB5_GRP1_DisableClock\n
1173 * AHB5ENR JPEGEN LL_AHB5_GRP1_DisableClock\n
1174 * AHB5ENR FMCEN LL_AHB5_GRP1_DisableClock\n
1175 * AHB5ENR XSPI1EN LL_AHB5_GRP1_DisableClock\n
1176 * AHB5ENR XSPI2EN LL_AHB5_GRP1_DisableClock\n
1177 * AHB5ENR XSPIMEN LL_AHB5_GRP1_DisableClock\n
1178 * AHB5ENR SDMMC1EN LL_AHB5_GRP1_DisableClock\n
1179 * AHB5ENR GFXMMUEN LL_AHB5_GRP1_DisableClock\n
1180 * AHB5ENR GPU2DEN LL_AHB5_GRP1_DisableClock
1181 * @param Periphs This parameter can be a combination of the following values:
1182 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1183 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1184 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*)
1185 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1186 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1187 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1188 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1189 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1190 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*)
1191 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*)
1192 *
1193 * (*) value not defined in all devices.
1194 * @retval None
1195 */
LL_AHB5_GRP1_DisableClock(uint32_t Periphs)1196 __STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs)
1197 {
1198 CLEAR_BIT(RCC->AHB5ENR, Periphs);
1199 }
1200
1201 /**
1202 * @brief Force AHB5 peripherals reset.
1203 * @rmtoll AHB5RSTR HPDMA1RST LL_AHB5_GRP1_ForceReset\n
1204 * AHB5RSTR DMA2DRST LL_AHB5_GRP1_ForceReset\n
1205 * AHB5RSTR JPEGRST LL_AHB5_GRP1_ForceReset\n
1206 * AHB5RSTR FMCRST LL_AHB5_GRP1_ForceReset\n
1207 * AHB5RSTR XSPI1RST LL_AHB5_GRP1_ForceReset\n
1208 * AHB5RSTR XSPI2RST LL_AHB5_GRP1_ForceReset\n
1209 * AHB5RSTR XSPIMRST LL_AHB5_GRP1_ForceReset\n
1210 * AHB5RSTR SDMMC1RST LL_AHB5_GRP1_ForceReset\n
1211 * AHB5RSTR GFXMMURST LL_AHB5_GRP1_ForceReset\n
1212 * AHB5RSTR GPU2DRST LL_AHB5_GRP1_ForceReset
1213 * @param Periphs This parameter can be a combination of the following values:
1214 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1215 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1216 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*)
1217 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1218 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1219 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1220 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1221 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1222 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*)
1223 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*)
1224 *
1225 * (*) value not defined in all devices.
1226 * @retval None
1227 */
LL_AHB5_GRP1_ForceReset(uint32_t Periphs)1228 __STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs)
1229 {
1230 SET_BIT(RCC->AHB5RSTR, Periphs);
1231 }
1232
1233 /**
1234 * @brief Release AHB5 peripherals reset.
1235 * @rmtoll AHB5RSTR HPDMA1RST LL_AHB5_GRP1_ReleaseReset\n
1236 * AHB5RSTR DMA2DRST LL_AHB5_GRP1_ReleaseReset\n
1237 * AHB5RSTR JPEGRST LL_AHB5_GRP1_ReleaseReset\n
1238 * AHB5RSTR FMCRST LL_AHB5_GRP1_ReleaseReset\n
1239 * AHB5RSTR XSPI1RST LL_AHB5_GRP1_ReleaseReset\n
1240 * AHB5RSTR XSPI2RST LL_AHB5_GRP1_ReleaseReset\n
1241 * AHB5RSTR XSPIMRST LL_AHB5_GRP1_ReleaseReset\n
1242 * AHB5RSTR SDMMC1RST LL_AHB5_GRP1_ReleaseReset\n
1243 * AHB5RSTR GFXMMURST LL_AHB5_GRP1_ReleaseReset\n
1244 * AHB5RSTR GPU2DRST LL_AHB5_GRP1_ReleaseReset
1245 * @param Periphs This parameter can be a combination of the following values:
1246 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1247 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1248 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*)
1249 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1250 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1251 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1252 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1253 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1254 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*)
1255 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*)
1256 *
1257 * (*) value not defined in all devices.
1258 * @retval None
1259 */
LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)1260 __STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)
1261 {
1262 CLEAR_BIT(RCC->AHB5RSTR, Periphs);
1263 }
1264
1265 /**
1266 * @brief Enable AHB5 peripherals clock during Low Power (Sleep) mode.
1267 * @rmtoll AHB5LPENR HPDMA1LPEN LL_AHB5_GRP1_EnableClockSleep\n
1268 * AHB5LPENR DMA2DLPEN LL_AHB5_GRP1_EnableClockSleep\n
1269 * AHB5LPENR JPEGLPEN LL_AHB5_GRP1_EnableClockSleep\n
1270 * AHB5LPENR FMCLPEN LL_AHB5_GRP1_EnableClockSleep\n
1271 * AHB5LPENR XSPI1LPEN LL_AHB5_GRP1_EnableClockSleep\n
1272 * AHB5LPENR XSPI2LPEN LL_AHB5_GRP1_EnableClockSleep\n
1273 * AHB5LPENR XSPIMLPEN LL_AHB5_GRP1_EnableClockSleep\n
1274 * AHB5LPENR SDMMC1LPEN LL_AHB5_GRP1_EnableClockSleep\n
1275 * AHB5LPENR GFXMMULPEN LL_AHB5_GRP1_EnableClockSleep\n
1276 * AHB5LPENR GPU2DLPEN LL_AHB5_GRP1_EnableClockSleep\n
1277 * AHB5LPENR AXISRAMPLEN LL_AHB5_GRP1_EnableClockSleep\n
1278 * AHB5LPENR DTCM1PLEN LL_AHB5_GRP1_EnableClockSleep\n
1279 * AHB5LPENR DTCM2PLEN LL_AHB5_GRP1_EnableClockSleep\n
1280 * AHB5LPENR ITCMPLEN LL_AHB5_GRP1_EnableClockSleep
1281 * @param Periphs This parameter can be a combination of the following values:
1282 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1283 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1284 * @arg @ref LL_AHB5_GRP1_PERIPH_FLASH
1285 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*)
1286 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1287 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1288 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1289 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1290 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1291 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*)
1292 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*)
1293 * @arg @ref LL_AHB5_GRP1_PERIPH_AXISRAM
1294 * @arg @ref LL_AHB5_GRP1_PERIPH_DTCM1
1295 * @arg @ref LL_AHB5_GRP1_PERIPH_DTCM2
1296 * @arg @ref LL_AHB5_GRP1_PERIPH_ITCM
1297 *
1298 * (*) value not defined in all devices.
1299 * @retval None
1300 */
LL_AHB5_GRP1_EnableClockSleep(uint32_t Periphs)1301 __STATIC_INLINE void LL_AHB5_GRP1_EnableClockSleep(uint32_t Periphs)
1302 {
1303 __IO uint32_t tmpreg;
1304 SET_BIT(RCC->AHB5LPENR, Periphs);
1305 /* Delay after an RCC peripheral clock enabling */
1306 tmpreg = READ_BIT(RCC->AHB5LPENR, Periphs);
1307 (void)tmpreg;
1308 }
1309
1310 /**
1311 * @brief Disable AHB5 peripherals clock during Low Power (Sleep) mode.
1312 * @rmtoll AHB5LPENR HPDMA1LPEN LL_AHB5_GRP1_DisableClockSleep\n
1313 * AHB5LPENR DMA2DLPEN LL_AHB5_GRP1_DisableClockSleep\n
1314 * AHB5LPENR FLASHLPEN LL_AHB5_GRP1_DisableClockSleep\n
1315 * AHB5LPENR JPEGLPEN LL_AHB5_GRP1_DisableClockSleep\n
1316 * AHB5LPENR FMCLPEN LL_AHB5_GRP1_DisableClockSleep\n
1317 * AHB5LPENR XSPI1LPEN LL_AHB5_GRP1_DisableClockSleep\n
1318 * AHB5LPENR XSPI2LPEN LL_AHB5_GRP1_DisableClockSleep\n
1319 * AHB5LPENR XSPIMLPEN LL_AHB5_GRP1_DisableClockSleep\n
1320 * AHB5LPENR SDMMC1LPEN LL_AHB5_GRP1_DisableClockSleep\n
1321 * AHB5LPENR GFXMMULPEN LL_AHB5_GRP1_DisableClockSleep\n
1322 * AHB5LPENR GPU2DLPEN LL_AHB5_GRP1_DisableClockSleep\n
1323 * AHB5LPENR AXISRAMPLEN LL_AHB5_GRP1_DisableClockSleep\n
1324 * AHB5LPENR DTCM1PLEN LL_AHB5_GRP1_DisableClockSleep\n
1325 * AHB5LPENR DTCM2PLEN LL_AHB5_GRP1_DisableClockSleep\n
1326 * AHB5LPENR ITCMPLEN LL_AHB5_GRP1_DisableClockSleep
1327 * @param Periphs This parameter can be a combination of the following values:
1328 * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
1329 * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
1330 * @arg @ref LL_AHB5_GRP1_PERIPH_FLASH
1331 * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*)
1332 * @arg @ref LL_AHB5_GRP1_PERIPH_FMC
1333 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
1334 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
1335 * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
1336 * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
1337 * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*)
1338 * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*)
1339 * @arg @ref LL_AHB5_GRP1_PERIPH_AXISRAM
1340 * @arg @ref LL_AHB5_GRP1_PERIPH_DTCM1
1341 * @arg @ref LL_AHB5_GRP1_PERIPH_DTCM2
1342 * @arg @ref LL_AHB5_GRP1_PERIPH_ITCM
1343 *
1344 * (*) value not defined in all devices.
1345 * @retval None
1346 */
LL_AHB5_GRP1_DisableClockSleep(uint32_t Periphs)1347 __STATIC_INLINE void LL_AHB5_GRP1_DisableClockSleep(uint32_t Periphs)
1348 {
1349 CLEAR_BIT(RCC->AHB5LPENR, Periphs);
1350 }
1351
1352 /**
1353 * @}
1354 */
1355
1356 /** @defgroup BUS_LL_EF_APB1 APB1
1357 * @{
1358 */
1359
1360 /**
1361 * @brief Enable APB1 peripherals clock.
1362 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
1363 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
1364 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
1365 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
1366 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
1367 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
1368 * APB1ENR1 TIM12EN LL_APB1_GRP1_EnableClock\n
1369 * APB1ENR1 TIM13EN LL_APB1_GRP1_EnableClock\n
1370 * APB1ENR1 TIM14EN LL_APB1_GRP1_EnableClock\n
1371 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock\n
1372 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
1373 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
1374 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
1375 * APB1ENR1 SPDIFRXEN LL_APB1_GRP1_EnableClock\n
1376 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
1377 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
1378 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
1379 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
1380 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
1381 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
1382 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
1383 * APB1ENR1 I3C1EN LL_APB1_GRP1_EnableClock\n
1384 * APB1ENR1 CECEN LL_APB1_GRP1_EnableClock\n
1385 * APB1ENR1 UART7EN LL_APB1_GRP1_EnableClock\n
1386 * APB1ENR1 UART8EN LL_APB1_GRP1_EnableClock
1387 * @param Periphs This parameter can be a combination of the following values:
1388 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1389 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1390 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1391 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1392 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1393 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1394 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1395 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1396 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1397 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1398 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1399 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1400 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1401 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1402 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1403 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1404 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1405 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1406 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1407 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1408 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1409 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1410 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1411 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1412 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1413 * @retval None
1414 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1415 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1416 {
1417 __IO uint32_t tmpreg;
1418 SET_BIT(RCC->APB1ENR1, Periphs);
1419 /* Delay after an RCC peripheral clock enabling */
1420 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
1421 (void)tmpreg;
1422 }
1423
1424 /**
1425 * @brief Check if APB1 peripheral clock is enabled or not
1426 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1427 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1428 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1429 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1430 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1431 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1432 * APB1ENR1 TIM12EN LL_APB1_GRP1_IsEnabledClock\n
1433 * APB1ENR1 TIM13EN LL_APB1_GRP1_IsEnabledClock\n
1434 * APB1ENR1 TIM14EN LL_APB1_GRP1_IsEnabledClock\n
1435 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
1436 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1437 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1438 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1439 * APB1ENR1 SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
1440 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
1441 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
1442 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
1443 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
1444 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1445 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1446 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1447 * APB1ENR1 I3C1EN LL_APB1_GRP1_IsEnabledClock\n
1448 * APB1ENR1 CECEN LL_APB1_GRP1_IsEnabledClock\n
1449 * APB1ENR1 UART7EN LL_APB1_GRP1_IsEnabledClock\n
1450 * APB1ENR1 UART8EN LL_APB1_GRP1_IsEnabledClock
1451 * @param Periphs This parameter can be a combination of the following values:
1452 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1453 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1454 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1455 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1456 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1457 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1458 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1459 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1460 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1461 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1462 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1463 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1464 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1465 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1466 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1467 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1468 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1469 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1470 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1471 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1472 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1473 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1474 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1475 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1476 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1477 * @retval uint32_t
1478 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1479 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1480 {
1481 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1U : 0U);
1482 }
1483
1484 /**
1485 * @brief Disable APB1 peripherals clock.
1486 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
1487 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
1488 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
1489 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
1490 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
1491 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
1492 * APB1ENR1 TIM12EN LL_APB1_GRP1_DisableClock\n
1493 * APB1ENR1 TIM13EN LL_APB1_GRP1_DisableClock\n
1494 * APB1ENR1 TIM14EN LL_APB1_GRP1_DisableClock\n
1495 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock\n
1496 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
1497 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
1498 * APB1ENR1 SPDIFRXEN LL_APB1_GRP1_DisableClock\n
1499 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
1500 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
1501 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
1502 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
1503 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
1504 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
1505 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
1506 * APB1ENR1 I3C1EN LL_APB1_GRP1_DisableClock\n
1507 * APB1ENR1 CECEN LL_APB1_GRP1_DisableClock\n
1508 * APB1ENR1 UART7EN LL_APB1_GRP1_DisableClock\n
1509 * APB1ENR1 UART8EN LL_APB1_GRP1_DisableClock
1510 * @param Periphs This parameter can be a combination of the following values:
1511 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1512 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1513 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1514 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1515 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1516 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1517 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1518 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1519 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1520 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1521 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1522 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1523 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1524 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1525 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1526 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1527 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1528 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1529 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1530 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1531 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1532 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1533 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1534 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1535 * @retval None
1536 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1537 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1538 {
1539 CLEAR_BIT(RCC->APB1ENR1, Periphs);
1540 }
1541
1542 /**
1543 * @brief Force APB1 peripherals reset.
1544 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1545 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
1546 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
1547 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
1548 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
1549 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
1550 * APB1RSTR1 TIM12RST LL_APB1_GRP1_ForceReset\n
1551 * APB1RSTR1 TIM13RST LL_APB1_GRP1_ForceReset\n
1552 * APB1RSTR1 TIM14RST LL_APB1_GRP1_ForceReset\n
1553 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset\n
1554 * APB1RSTR1 WWDGRST LL_APB1_GRP1_ForceReset\n
1555 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
1556 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
1557 * APB1RSTR1 SPDIFRXRST LL_APB1_GRP1_ForceReset\n
1558 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
1559 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
1560 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
1561 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
1562 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
1563 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
1564 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
1565 * APB1RSTR1 I3C1RST LL_APB1_GRP1_ForceReset\n
1566 * APB1RSTR1 CECRST LL_APB1_GRP1_ForceReset\n
1567 * APB1RSTR1 UART7RST LL_APB1_GRP1_ForceReset\n
1568 * APB1RSTR1 UART8RST LL_APB1_GRP1_ForceReset
1569 * @param Periphs This parameter can be a combination of the following values:
1570 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1571 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1572 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1573 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1574 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1575 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1576 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1577 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1578 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1579 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1580 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1581 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1582 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1583 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1584 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1585 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1586 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1587 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1588 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1589 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1590 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1591 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1592 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1593 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1594 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1595 * @retval None
1596 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1597 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1598 {
1599 SET_BIT(RCC->APB1RSTR1, Periphs);
1600 }
1601
1602 /**
1603 * @brief Release APB1 peripherals reset.
1604 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1605 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
1606 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
1607 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
1608 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
1609 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
1610 * APB1RSTR1 TIM12RST LL_APB1_GRP1_ReleaseReset\n
1611 * APB1RSTR1 TIM13RST LL_APB1_GRP1_ReleaseReset\n
1612 * APB1RSTR1 TIM14RST LL_APB1_GRP1_ReleaseReset\n
1613 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
1614 * APB1RSTR1 WWDGRST LL_APB1_GRP1_ReleaseReset\n
1615 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
1616 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
1617 * APB1RSTR1 SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
1618 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
1619 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
1620 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
1621 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
1622 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
1623 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
1624 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
1625 * APB1RSTR1 I3C1RST LL_APB1_GRP1_ReleaseReset\n
1626 * APB1RSTR1 CECRST LL_APB1_GRP1_ReleaseReset\n
1627 * APB1RSTR1 UART7RST LL_APB1_GRP1_ReleaseReset\n
1628 * APB1RSTR1 UART8RST LL_APB1_GRP1_ReleaseReset
1629 * @param Periphs This parameter can be a combination of the following values:
1630 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1631 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1632 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1633 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1634 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1635 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1636 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1637 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1638 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1639 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1640 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1641 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1642 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1643 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1644 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1645 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1646 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1647 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1648 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1649 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1650 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1651 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1652 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1653 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1654 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1655 * @retval None
1656 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1657 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1658 {
1659 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1660 }
1661
1662 /**
1663 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
1664 * @rmtoll APB1LPENR1 TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
1665 * APB1LPENR1 TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
1666 * APB1LPENR1 TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
1667 * APB1LPENR1 TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
1668 * APB1LPENR1 TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
1669 * APB1LPENR1 TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
1670 * APB1LPENR1 TIM12LPEN LL_APB1_GRP1_EnableClockSleep\n
1671 * APB1LPENR1 TIM13LPEN LL_APB1_GRP1_EnableClockSleep\n
1672 * APB1LPENR1 TIM14LPEN LL_APB1_GRP1_EnableClockSleep\n
1673 * APB1LPENR1 LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep\n
1674 * APB1LPENR1 WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n
1675 * APB1LPENR1 SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
1676 * APB1LPENR1 SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
1677 * APB1LPENR1 SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep\n
1678 * APB1LPENR1 USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
1679 * APB1LPENR1 USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
1680 * APB1LPENR1 UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
1681 * APB1LPENR1 UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
1682 * APB1LPENR1 I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
1683 * APB1LPENR1 I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
1684 * APB1LPENR1 I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n
1685 * APB1LPENR1 I3C1LPEN LL_APB1_GRP1_EnableClockSleep\n
1686 * APB1LPENR1 CECLPEN LL_APB1_GRP1_EnableClockSleep\n
1687 * APB1LPENR1 DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n
1688 * APB1LPENR1 UART7LPEN LL_APB1_GRP1_EnableClockSleep\n
1689 * APB1LPENR1 UART8LPEN LL_APB1_GRP1_EnableClockSleep
1690 * @param Periphs This parameter can be a combination of the following values:
1691 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1692 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1693 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1694 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1695 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1696 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1697 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1698 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1699 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1700 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1701 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1702 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1703 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1704 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1705 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1706 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1707 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1708 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1709 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1710 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1711 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1712 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1713 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1714 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1715 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1716 * @retval None
1717 */
LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)1718 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
1719 {
1720 __IO uint32_t tmpreg;
1721 SET_BIT(RCC->APB1LPENR1, Periphs);
1722 /* Delay after an RCC peripheral clock enabling */
1723 tmpreg = READ_BIT(RCC->APB1LPENR1, Periphs);
1724 (void)tmpreg;
1725 }
1726
1727 /**
1728 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
1729 * @rmtoll APB1LPENR1 TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
1730 * APB1LPENR1 TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
1731 * APB1LPENR1 TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
1732 * APB1LPENR1 TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
1733 * APB1LPENR1 TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
1734 * APB1LPENR1 TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
1735 * APB1LPENR1 TIM12LPEN LL_APB1_GRP1_DisableClockSleep\n
1736 * APB1LPENR1 TIM13LPEN LL_APB1_GRP1_DisableClockSleep\n
1737 * APB1LPENR1 TIM14LPEN LL_APB1_GRP1_DisableClockSleep\n
1738 * APB1LPENR1 LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep\n
1739 * APB1LPENR1 WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n
1740 * APB1LPENR1 SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
1741 * APB1LPENR1 SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
1742 * APB1LPENR1 SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep\n
1743 * APB1LPENR1 USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
1744 * APB1LPENR1 USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
1745 * APB1LPENR1 UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
1746 * APB1LPENR1 UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
1747 * APB1LPENR1 I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
1748 * APB1LPENR1 I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
1749 * APB1LPENR1 I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n
1750 * APB1LPENR1 I3C1LPEN LL_APB1_GRP1_DisableClockSleep\n
1751 * APB1LPENR1 CECLPEN LL_APB1_GRP1_DisableClockSleep\n
1752 * APB1LPENR1 UART7LPEN LL_APB1_GRP1_DisableClockSleep\n
1753 * APB1LPENR1 UART8LPEN LL_APB1_GRP1_DisableClockSleep
1754 * @param Periphs This parameter can be a combination of the following values:
1755 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1756 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1757 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1758 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1759 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1760 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1761 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1762 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1763 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1764 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1765 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1766 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1767 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1768 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1769 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1770 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1771 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1772 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1773 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1774 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1775 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1776 * @arg @ref LL_APB1_GRP1_PERIPH_I3C1
1777 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1778 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1779 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1780 * @retval None
1781 */
LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)1782 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
1783 {
1784 CLEAR_BIT(RCC->APB1LPENR1, Periphs);
1785 }
1786
1787 /**
1788 * @brief Enable APB1 peripherals clock.
1789 * @rmtoll APB1ENR2 CRSEN LL_APB1_GRP2_EnableClock\n
1790 * APB1ENR2 MDIOSEN LL_APB1_GRP2_EnableClock\n
1791 * APB1ENR2 FDCANEN LL_APB1_GRP2_EnableClock\n
1792 * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock
1793 * @param Periphs This parameter can be a combination of the following values:
1794 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
1795 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
1796 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1797 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1798 * @retval None
1799 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)1800 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
1801 {
1802 __IO uint32_t tmpreg;
1803 SET_BIT(RCC->APB1ENR2, Periphs);
1804 /* Delay after an RCC peripheral clock enabling */
1805 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
1806 (void)tmpreg;
1807 }
1808
1809 /**
1810 * @brief Check if APB1 peripheral clock is enabled or not
1811 * @rmtoll APB1ENR2 CRSEN LL_APB1_GRP2_IsEnabledClock\n
1812 * APB1ENR2 MDIOSEN LL_APB1_GRP2_IsEnabledClock\n
1813 * APB1ENR2 FDCANEN LL_APB1_GRP2_IsEnabledClock\n
1814 * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
1815 * @param Periphs This parameter can be a combination of the following values:
1816 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
1817 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
1818 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1819 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1820 * @retval uint32_t
1821 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1822 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1823 {
1824 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1U : 0U);
1825 }
1826
1827 /**
1828 * @brief Disable APB1 peripherals clock.
1829 * @rmtoll APB1ENR2 CRSEN LL_APB1_GRP2_DisableClock\n
1830 * APB1ENR2 MDIOSEN LL_APB1_GRP2_DisableClock\n
1831 * APB1ENR2 FDCANEN LL_APB1_GRP2_DisableClock\n
1832 * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock
1833 * @param Periphs This parameter can be a combination of the following values:
1834 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
1835 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
1836 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1837 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1838 * @retval None
1839 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1840 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1841 {
1842 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1843 }
1844
1845 /**
1846 * @brief Force APB1 peripherals reset.
1847 * @rmtoll APB1RSTR2 CRSRST LL_APB1_GRP2_ForceReset\n
1848 * APB1ENR2 MDIOSRST LL_APB1_GRP2_ForceReset\n
1849 * APB1ENR2 FDCANRST LL_APB1_GRP2_ForceReset\n
1850 * APB1ENR2 UCPD1RST LL_APB1_GRP2_ForceReset
1851 * @param Periphs This parameter can be a combination of the following values:
1852 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
1853 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
1854 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1855 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1856 * @retval None
1857 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1858 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1859 {
1860 SET_BIT(RCC->APB1RSTR2, Periphs);
1861 }
1862
1863 /**
1864 * @brief Release APB1 peripherals reset.
1865 * @rmtoll APB1RSTR2 CRSRST LL_APB1_GRP2_ReleaseReset\n
1866 * APB1ENR2 MDIOSRST LL_APB1_GRP2_ReleaseReset\n
1867 * APB1ENR2 FDCANRST LL_APB1_GRP2_ReleaseReset\n
1868 * APB1ENR2 UCPD1RST LL_APB1_GRP2_ReleaseReset
1869 * @param Periphs This parameter can be a combination of the following values:
1870 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
1871 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
1872 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1873 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1874 * @retval None
1875 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1876 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1877 {
1878 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1879 }
1880
1881 /**
1882 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
1883 * @rmtoll APB1LPENR2 CRSLPEN LL_APB1_GRP2_EnableClockSleep\n
1884 * APB1LPENR2 MDIOSLPEN LL_APB1_GRP2_EnableClockSleep\n
1885 * APB1LPENR2 FDCANLPEN LL_APB1_GRP2_EnableClockSleep\n
1886 * APB1LPENR2 UCPD1LPEN LL_APB1_GRP2_EnableClockSleep
1887 * @param Periphs This parameter can be a combination of the following values:
1888 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
1889 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
1890 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1891 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1892 * @retval None
1893 */
LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)1894 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
1895 {
1896 __IO uint32_t tmpreg;
1897 SET_BIT(RCC->APB1LPENR2, Periphs);
1898 /* Delay after an RCC peripheral clock enabling */
1899 tmpreg = READ_BIT(RCC->APB1LPENR2, Periphs);
1900 (void)tmpreg;
1901 }
1902
1903 /**
1904 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
1905 * @rmtoll APB1LPENR2 CRSLPEN LL_APB1_GRP2_DisableClockSleep\n
1906 * APB1LPENR2 MDIOSLPEN LL_APB1_GRP2_DisableClockSleep\n
1907 * APB1LPENR2 FDCANLPEN LL_APB1_GRP2_DisableClockSleep\n
1908 * APB1LPENR2 UCPD1LPEN LL_APB1_GRP2_DisableClockSleep
1909 * @param Periphs This parameter can be a combination of the following values:
1910 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
1911 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
1912 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
1913 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1914 * @retval None
1915 */
LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)1916 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
1917 {
1918 CLEAR_BIT(RCC->APB1LPENR2, Periphs);
1919 }
1920
1921 /**
1922 * @}
1923 */
1924
1925 /** @defgroup BUS_LL_EF_APB2 APB2
1926 * @{
1927 */
1928
1929 /**
1930 * @brief Enable APB2 peripherals clock.
1931 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1932 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1933 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1934 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
1935 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
1936 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1937 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1938 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
1939 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
1940 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1941 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock
1942 * @param Periphs This parameter can be a combination of the following values:
1943 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1944 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1945 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1946 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1947 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1948 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1949 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1950 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1951 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1952 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1953 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1954 * @retval None
1955 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1956 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1957 {
1958 __IO uint32_t tmpreg;
1959 SET_BIT(RCC->APB2ENR, Periphs);
1960 /* Delay after an RCC peripheral clock enabling */
1961 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1962 (void)tmpreg;
1963 }
1964
1965 /**
1966 * @brief Check if APB2 peripheral clock is enabled or not
1967 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1968 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1969 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1970 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
1971 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
1972 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1973 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1974 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
1975 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
1976 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1977 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock
1978 * @param Periphs This parameter can be a combination of the following values:
1979 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1980 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1981 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1982 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1983 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1984 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1985 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1986 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1987 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1988 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1989 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1990 * @retval uint32_t
1991 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1992 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1993 {
1994 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1U : 0U);
1995 }
1996
1997 /**
1998 * @brief Disable APB2 peripherals clock.
1999 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
2000 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
2001 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
2002 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
2003 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
2004 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
2005 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
2006 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
2007 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
2008 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
2009 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock
2010 * @param Periphs This parameter can be a combination of the following values:
2011 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2012 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2013 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2014 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2015 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2016 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2017 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2018 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2019 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2020 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2021 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2022 * @retval None
2023 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)2024 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
2025 {
2026 CLEAR_BIT(RCC->APB2ENR, Periphs);
2027 }
2028
2029 /**
2030 * @brief Force APB2 peripherals reset.
2031 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
2032 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
2033 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
2034 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
2035 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
2036 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
2037 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
2038 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
2039 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
2040 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
2041 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset
2042 * @param Periphs This parameter can be a combination of the following values:
2043 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2044 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2045 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2046 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2047 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2048 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2049 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2050 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2051 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2052 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2053 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2054 * @retval None
2055 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)2056 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
2057 {
2058 SET_BIT(RCC->APB2RSTR, Periphs);
2059 }
2060
2061 /**
2062 * @brief Release APB2 peripherals reset.
2063 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
2064 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
2065 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
2066 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
2067 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
2068 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
2069 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
2070 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
2071 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
2072 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
2073 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset
2074 * @param Periphs This parameter can be a combination of the following values:
2075 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2076 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2077 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2078 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2079 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2080 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2081 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2082 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2083 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2084 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2085 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2086 * @retval None
2087 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)2088 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
2089 {
2090 CLEAR_BIT(RCC->APB2RSTR, Periphs);
2091 }
2092
2093 /**
2094 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
2095 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n
2096 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n
2097 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2098 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n
2099 * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n
2100 * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n
2101 * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n
2102 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockSleep\n
2103 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep\n
2104 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2105 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep
2106 * @param Periphs This parameter can be a combination of the following values:
2107 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2108 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2109 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2110 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2111 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2112 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2113 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2114 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2115 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2116 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2117 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2118 * @retval None
2119 */
LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)2120 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
2121 {
2122 __IO uint32_t tmpreg;
2123 SET_BIT(RCC->APB2LPENR, Periphs);
2124 /* Delay after an RCC peripheral clock enabling */
2125 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
2126 (void)tmpreg;
2127 }
2128
2129 /**
2130 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
2131 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n
2132 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n
2133 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2134 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n
2135 * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n
2136 * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n
2137 * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n
2138 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockSleep\n
2139 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep\n
2140 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2141 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep
2142 * @param Periphs This parameter can be a combination of the following values:
2143 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2144 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2145 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2146 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2147 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2148 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2149 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2150 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2151 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2152 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2153 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2154 * @retval None
2155 */
LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)2156 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
2157 {
2158 CLEAR_BIT(RCC->APB2LPENR, Periphs);
2159 }
2160
2161 /**
2162 * @}
2163 */
2164
2165 /** @defgroup BUS_LL_EF_APB4 APB4
2166 * @{
2167 */
2168
2169 /**
2170 * @brief Enable APB4 peripherals clock.
2171 * @rmtoll APB4ENR SBSEN LL_APB4_GRP1_EnableClock\n
2172 * APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock\n
2173 * APB4ENR SPI6EN LL_APB4_GRP1_EnableClock\n
2174 * APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock\n
2175 * APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock\n
2176 * APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock\n
2177 * APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock\n
2178 * APB4ENR VREFEN LL_APB4_GRP1_EnableClock\n
2179 * APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock\n
2180 * APB4ENR DTSEN LL_APB4_GRP1_EnableClock
2181 * @param Periphs This parameter can be a combination of the following values:
2182 * @arg @ref LL_APB4_GRP1_PERIPH_SBS
2183 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2184 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2185 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2186 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2187 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
2188 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
2189 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2190 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2191 * @arg @ref LL_APB4_GRP1_PERIPH_DTS
2192 * @retval None
2193 */
LL_APB4_GRP1_EnableClock(uint32_t Periphs)2194 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
2195 {
2196 __IO uint32_t tmpreg;
2197 SET_BIT(RCC->APB4ENR, Periphs);
2198 /* Delay after an RCC peripheral clock enabling */
2199 tmpreg = READ_BIT(RCC->APB4ENR, Periphs);
2200 (void)tmpreg;
2201 }
2202
2203 /**
2204 * @brief Check if APB4 peripheral clock is enabled or not
2205 * @rmtoll APB4ENR SBSEN LL_APB4_GRP1_IsEnabledClock\n
2206 * APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock\n
2207 * APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock\n
2208 * APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n
2209 * APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n
2210 * APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n
2211 * APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n
2212 * APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock\n
2213 * APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock\n
2214 * APB4ENR DTSEN LL_APB4_GRP1_IsEnabledClock
2215 * @param Periphs This parameter can be a combination of the following values:
2216 * @arg @ref LL_APB4_GRP1_PERIPH_SBS
2217 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2218 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2219 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2220 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2221 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
2222 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
2223 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2224 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2225 * @arg @ref LL_APB4_GRP1_PERIPH_DTS
2226 * @retval uint32_t
2227 */
LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)2228 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
2229 {
2230 return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs) ? 1U : 0U);
2231 }
2232
2233 /**
2234 * @brief Disable APB4 peripherals clock.
2235 * @rmtoll APB4ENR SBSEN LL_APB4_GRP1_DisableClock\n
2236 * APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock\n
2237 * APB4ENR SPI6EN LL_APB4_GRP1_DisableClock\n
2238 * APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock\n
2239 * APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock\n
2240 * APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock\n
2241 * APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock\n
2242 * APB4ENR VREFEN LL_APB4_GRP1_DisableClock\n
2243 * APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock\n
2244 * APB4ENR DTSEN LL_APB4_GRP1_DisableClock
2245 * @param Periphs This parameter can be a combination of the following values:
2246 * @arg @ref LL_APB4_GRP1_PERIPH_SBS
2247 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2248 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2249 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2250 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2251 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
2252 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
2253 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2254 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2255 * @arg @ref LL_APB4_GRP1_PERIPH_DTS
2256 * @retval None
2257 */
LL_APB4_GRP1_DisableClock(uint32_t Periphs)2258 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
2259 {
2260 CLEAR_BIT(RCC->APB4ENR, Periphs);
2261 }
2262
2263 /**
2264 * @brief Force APB4 peripherals reset.
2265 * @rmtoll APB4RSTR SBSRST LL_APB4_GRP1_ForceReset\n
2266 * APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset\n
2267 * APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset\n
2268 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset\n
2269 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset\n
2270 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset\n
2271 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset\n
2272 * APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n
2273 * APB4RSTR DTSRST LL_APB4_GRP1_ForceReset
2274 * @param Periphs This parameter can be a combination of the following values:
2275 * @arg @ref LL_APB4_GRP1_PERIPH_SBS
2276 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2277 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2278 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2279 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2280 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
2281 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
2282 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2283 * @arg @ref LL_APB4_GRP1_PERIPH_DTS
2284 * @retval None
2285 */
LL_APB4_GRP1_ForceReset(uint32_t Periphs)2286 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
2287 {
2288 SET_BIT(RCC->APB4RSTR, Periphs);
2289 }
2290
2291 /**
2292 * @brief Release APB4 peripherals reset.
2293 * @rmtoll APB4RSTR SBSRST LL_APB4_GRP1_ReleaseReset\n
2294 * APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset\n
2295 * APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset\n
2296 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset\n
2297 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset\n
2298 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset\n
2299 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset\n
2300 * APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset\n
2301 * APB4RSTR DTSRST LL_APB4_GRP1_ReleaseReset
2302 * @param Periphs This parameter can be a combination of the following values:
2303 * @arg @ref LL_APB4_GRP1_PERIPH_SBS
2304 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2305 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2306 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2307 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2308 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
2309 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
2310 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2311 * @arg @ref LL_APB4_GRP1_PERIPH_DTS
2312 * @retval None
2313 */
LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)2314 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
2315 {
2316 CLEAR_BIT(RCC->APB4RSTR, Periphs);
2317 }
2318
2319 /**
2320 * @brief Enable APB4 peripherals clock during Low Power (Sleep) mode.
2321 * @rmtoll APB4LPENR SBSLPEN LL_APB4_GRP1_EnableClockSleep\n
2322 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep\n
2323 * APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep\n
2324 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep\n
2325 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep\n
2326 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep\n
2327 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep\n
2328 * APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep\n
2329 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep\n
2330 * APB4LPENR DTSLPEN LL_APB4_GRP1_EnableClockSleep
2331 * @param Periphs This parameter can be a combination of the following values:
2332 * @arg @ref LL_APB4_GRP1_PERIPH_SBS
2333 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2334 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2335 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2336 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2337 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
2338 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
2339 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2340 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2341 * @arg @ref LL_APB4_GRP1_PERIPH_DTS
2342 * @retval None
2343 */
LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)2344 __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
2345 {
2346 __IO uint32_t tmpreg;
2347 SET_BIT(RCC->APB4LPENR, Periphs);
2348 /* Delay after an RCC peripheral clock enabling */
2349 tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);
2350 (void)tmpreg;
2351 }
2352
2353 /**
2354 * @brief Disable APB4 peripherals clock during Low Power (Sleep) mode.
2355 * @rmtoll APB4LPENR SBSLPEN LL_APB4_GRP1_DisableClockSleep\n
2356 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep\n
2357 * APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep\n
2358 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep\n
2359 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep\n
2360 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep\n
2361 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep\n
2362 * APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep\n
2363 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep\n
2364 * APB4LPENR DTSLPEN LL_APB4_GRP1_DisableClockSleep
2365 * @param Periphs This parameter can be a combination of the following values:
2366 * @arg @ref LL_APB4_GRP1_PERIPH_SBS
2367 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2368 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2369 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2370 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2371 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
2372 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
2373 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2374 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2375 * @arg @ref LL_APB4_GRP1_PERIPH_DTS
2376 * @retval None
2377 */
LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)2378 __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
2379 {
2380 CLEAR_BIT(RCC->APB4LPENR, Periphs);
2381 }
2382
2383 /**
2384 * @}
2385 */
2386
2387 /** @defgroup BUS_LL_EF_APB5 APB5
2388 * @{
2389 */
2390
2391 /**
2392 * @brief Enable APB5 peripherals clock.
2393 * @rmtoll APB5ENR LTDCEN LL_APB5_GRP1_EnableClock\n
2394 * APB5ENR DCMIPPEN LL_APB5_GRP1_EnableClock\n
2395 * APB5ENR GFXTIMEN LL_APB5_GRP1_EnableClock
2396 * @param Periphs This parameter can be a combination of the following values:
2397 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*)
2398 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
2399 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
2400 *
2401 * (*) value not defined in all devices.
2402 * @retval None
2403 */
LL_APB5_GRP1_EnableClock(uint32_t Periphs)2404 __STATIC_INLINE void LL_APB5_GRP1_EnableClock(uint32_t Periphs)
2405 {
2406 __IO uint32_t tmpreg;
2407 SET_BIT(RCC->APB5ENR, Periphs);
2408 /* Delay after an RCC peripheral clock enabling */
2409 tmpreg = READ_BIT(RCC->APB5ENR, Periphs);
2410 (void)tmpreg;
2411 }
2412
2413 /**
2414 * @brief Check if APB5 peripheral clock is enabled or not
2415 * @rmtoll APB5ENR LTDCEN LL_APB5_GRP1_IsEnabledClock\n
2416 * APB5ENR DCMIPPEN LL_APB5_GRP1_IsEnabledClock\n
2417 * APB5ENR GFXTIMEN LL_APB5_GRP1_IsEnabledClock
2418 * @param Periphs This parameter can be a combination of the following values:
2419 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*)
2420 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
2421 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
2422 *
2423 * (*) value not defined in all devices.
2424 * @retval uint32_t
2425 */
LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs)2426 __STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs)
2427 {
2428 return ((READ_BIT(RCC->APB5ENR, Periphs) == Periphs) ? 1U : 0U);
2429 }
2430
2431 /**
2432 * @brief Disable APB5 peripherals clock.
2433 * @rmtoll APB5ENR LTDCEN LL_APB5_GRP1_DisableClock\n
2434 * APB5ENR DCMIPPEN LL_APB5_GRP1_DisableClock\n
2435 * APB5ENR GFXTIMEN LL_APB5_GRP1_DisableClock
2436 * @param Periphs This parameter can be a combination of the following values:
2437 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*)
2438 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
2439 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
2440 *
2441 * (*) value not defined in all devices.
2442 * @retval None
2443 */
LL_APB5_GRP1_DisableClock(uint32_t Periphs)2444 __STATIC_INLINE void LL_APB5_GRP1_DisableClock(uint32_t Periphs)
2445 {
2446 CLEAR_BIT(RCC->APB5ENR, Periphs);
2447 }
2448
2449 /**
2450 * @brief Force APB5 peripherals reset.
2451 * @rmtoll APB5RSTR LTDCRST LL_APB5_GRP1_ForceReset\n
2452 * APB5RSTR DCMIPPRST LL_APB5_GRP1_ForceReset\n
2453 * APB5RSTR GFXTIMRST LL_APB5_GRP1_ForceReset
2454 * @param Periphs This parameter can be a combination of the following values:
2455 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*)
2456 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
2457 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
2458 *
2459 * (*) value not defined in all devices.
2460 * @retval None
2461 */
LL_APB5_GRP1_ForceReset(uint32_t Periphs)2462 __STATIC_INLINE void LL_APB5_GRP1_ForceReset(uint32_t Periphs)
2463 {
2464 SET_BIT(RCC->APB5RSTR, Periphs);
2465 }
2466
2467 /**
2468 * @brief Release APB5 peripherals reset.
2469 * @rmtoll APB5RSTR LTDCRST LL_APB5_GRP1_ReleaseReset\n
2470 * APB5RSTR DCMIPPRST LL_APB5_GRP1_ForceReset\n
2471 * APB5RSTR GFXTIMRST LL_APB5_GRP1_ForceReset
2472 * @param Periphs This parameter can be a combination of the following values:
2473 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*)
2474 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
2475 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
2476 *
2477 * (*) value not defined in all devices.
2478 * @retval None
2479 */
LL_APB5_GRP1_ReleaseReset(uint32_t Periphs)2480 __STATIC_INLINE void LL_APB5_GRP1_ReleaseReset(uint32_t Periphs)
2481 {
2482 CLEAR_BIT(RCC->APB5RSTR, Periphs);
2483 }
2484
2485 /**
2486 * @brief Enable APB5 peripherals clock during Low Power (Sleep) mode.
2487 * @rmtoll APB5LPENR LTDCLPEN LL_APB5_GRP1_EnableClockSleep\n
2488 * APB5LPENR DCMIPPLPEN LL_APB5_GRP1_EnableClockSleep\n
2489 * APB5LPENR GFXTIMLPEN LL_APB5_GRP1_EnableClockSleep
2490 * @param Periphs This parameter can be a combination of the following values:
2491 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*)
2492 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
2493 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
2494 *
2495 * (*) value not defined in all devices.
2496 * @retval None
2497 */
LL_APB5_GRP1_EnableClockSleep(uint32_t Periphs)2498 __STATIC_INLINE void LL_APB5_GRP1_EnableClockSleep(uint32_t Periphs)
2499 {
2500 __IO uint32_t tmpreg;
2501 SET_BIT(RCC->APB5LPENR, Periphs);
2502 /* Delay after an RCC peripheral clock enabling */
2503 tmpreg = READ_BIT(RCC->APB5LPENR, Periphs);
2504 (void)tmpreg;
2505 }
2506
2507 /**
2508 * @brief Disable APB5 peripherals clock during Low Power (Sleep) mode.
2509 * @rmtoll APB5LPENR LTDCLPEN LL_APB5_GRP1_DisableClockSleep\n
2510 * APB5LPENR DCMIPPLPEN LL_APB5_GRP1_DisableClockSleep\n
2511 * APB5LPENR GFXTIMLPEN LL_APB5_GRP1_DisableClockSleep
2512 * @param Periphs This parameter can be a combination of the following values:
2513 * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*)
2514 * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
2515 * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
2516 *
2517 * (*) value not defined in all devices.
2518 * @retval None
2519 */
LL_APB5_GRP1_DisableClockSleep(uint32_t Periphs)2520 __STATIC_INLINE void LL_APB5_GRP1_DisableClockSleep(uint32_t Periphs)
2521 {
2522 CLEAR_BIT(RCC->APB5LPENR, Periphs);
2523 }
2524
2525 /**
2526 * @}
2527 */
2528
2529 /** @defgroup BUS_LL_EF_CKGA CKGA (AXI Clocks Gating)
2530 * @{
2531 */
2532
2533 /**
2534 * @brief Enable clock gating for AXI bus peripherals.
2535 * @rmtoll CKGDISR AXICKG LL_CKGA_Enable\n
2536 * CKGDISR AHBMCKG LL_CKGA_Enable\n
2537 * CKGDISR SDMMC1CKG LL_CKGA_Enable\n
2538 * CKGDISR HPDMA1CKG LL_CKGA_Enable\n
2539 * CKGDISR CPUCKG LL_CKGA_Enable\n
2540 * CKGDISR GPU2DS0CKG LL_CKGA_Enable\n
2541 * CKGDISR GPU2DS1CKG LL_CKGA_Enable\n
2542 * CKGDISR GPUCLCKG LL_CKGA_Enable\n
2543 * CKGDISR DCMIPPCKG LL_CKGA_Enable\n
2544 * CKGDISR DMA2DCKG LL_CKGA_Enable\n
2545 * CKGDISR GFXMMUSCKG LL_CKGA_Enable\n
2546 * CKGDISR LTDCCKG LL_CKGA_Enable\n
2547 * CKGDISR GFXMMUMCKG LL_CKGA_Enable\n
2548 * CKGDISR AHBSCKG LL_CKGA_Enable\n
2549 * CKGDISR FMCCKG LL_CKGA_Enable\n
2550 * CKGDISR XSPI2CKG LL_CKGA_Enable\n
2551 * CKGDISR XSPI1CKG LL_CKGA_Enable\n
2552 * CKGDISR AXIRAM1CKG LL_CKGA_Enable\n
2553 * CKGDISR AXIRAM2CKG LL_CKGA_Enable\n
2554 * CKGDISR AXIRAM3CKG LL_CKGA_Enable\n
2555 * CKGDISR AXIRAM4CKG LL_CKGA_Enable\n
2556 * CKGDISR FLASHCKG LL_CKGA_Enable\n
2557 * CKGDISR EXTICKG LL_CKGA_Enable\n
2558 * CKGDISR JTAGCKG LL_CKGA_Enable
2559 * @param Periphs This parameter can be a combination of the following values:
2560 * @arg @ref LL_CKGA_PERIPH_AXI
2561 * @arg @ref LL_CKGA_PERIPH_AHBM
2562 * @arg @ref LL_CKGA_PERIPH_AHBS
2563 * @arg @ref LL_CKGA_PERIPH_SDMMC1
2564 * @arg @ref LL_CKGA_PERIPH_HPDMA1
2565 * @arg @ref LL_CKGA_PERIPH_CPU
2566 * @arg @ref LL_CKGA_PERIPH_GPU2DS0 (*)
2567 * @arg @ref LL_CKGA_PERIPH_GPU2DS1 (*)
2568 * @arg @ref LL_CKGA_PERIPH_GPU2DCL (*)
2569 * @arg @ref LL_CKGA_PERIPH_DMA2D
2570 * @arg @ref LL_CKGA_PERIPH_DCMIPP
2571 * @arg @ref LL_CKGA_PERIPH_LTDC (*)
2572 * @arg @ref LL_CKGA_PERIPH_FLASH
2573 * @arg @ref LL_CKGA_PERIPH_XSPI2
2574 * @arg @ref LL_CKGA_PERIPH_XSPI1
2575 * @arg @ref LL_CKGA_PERIPH_FMC
2576 * @arg @ref LL_CKGA_PERIPH_AXIRAM1
2577 * @arg @ref LL_CKGA_PERIPH_AXIRAM2
2578 * @arg @ref LL_CKGA_PERIPH_AXIRAM3
2579 * @arg @ref LL_CKGA_PERIPH_AXIRAM4
2580 * @arg @ref LL_CKGA_PERIPH_GFXMMUM
2581 * @arg @ref LL_CKGA_PERIPH_GFXMMUS
2582 * @arg @ref LL_CKGA_PERIPH_EXTI
2583 * @arg @ref LL_CKGA_PERIPH_JTAG
2584 *
2585 * (*) value not defined in all devices.
2586 * @retval None
2587 */
LL_CKGA_Enable(uint32_t Periphs)2588 __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)
2589 {
2590 CLEAR_BIT(RCC->CKGDISR, Periphs);
2591 }
2592
2593 /**
2594 * @brief Check if AXI bus peripherals clock gating is enabled or not
2595 * @rmtoll CKGDISR AXICKG LL_CKGA_IsEnabledClock\n
2596 * CKGDISR AHBMCKG LL_CKGA_IsEnabledClock\n
2597 * CKGDISR SDMMC1CKG LL_CKGA_IsEnabledClock\n
2598 * CKGDISR HPDMA1CKG LL_CKGA_IsEnabledClock\n
2599 * CKGDISR CPUCKG LL_CKGA_IsEnabledClock\n
2600 * CKGDISR GPU2DS0CKG LL_CKGA_IsEnabledClock\n
2601 * CKGDISR GPU2DS1CKG LL_CKGA_IsEnabledClock\n
2602 * CKGDISR GPU2DCLCKG LL_CKGA_IsEnabledClock\n
2603 * CKGDISR DCMIPPCKG LL_CKGA_IsEnabledClock\n
2604 * CKGDISR DMA2DCKG LL_CKGA_IsEnabledClock\n
2605 * CKGDISR GFXMMUSCKG LL_CKGA_IsEnabledClock\n
2606 * CKGDISR LTDCCKG LL_CKGA_IsEnabledClock\n
2607 * CKGDISR GFXMMUMCKG LL_CKGA_IsEnabledClock\n
2608 * CKGDISR AHBSCKG LL_CKGA_IsEnabledClock\n
2609 * CKGDISR FMCCKG LL_CKGA_IsEnabledClock\n
2610 * CKGDISR XSPI2CKG LL_CKGA_IsEnabledClock\n
2611 * CKGDISR XSPI1CKG LL_CKGA_IsEnabledClock\n
2612 * CKGDISR AXIRAM1CKG LL_CKGA_IsEnabledClock\n
2613 * CKGDISR AXIRAM2CKG LL_CKGA_IsEnabledClock\n
2614 * CKGDISR AXIRAM3CKG LL_CKGA_IsEnabledClock\n
2615 * CKGDISR AXIRAM4CKG LL_CKGA_IsEnabledClock\n
2616 * CKGDISR FLASHCKG LL_CKGA_IsEnabledClock\n
2617 * CKGDISR EXTICKG LL_CKGA_IsEnabledClock\n
2618 * CKGDISR JTAGCKG LL_CKGA_IsEnabledClock
2619 * @param Periphs This parameter can be a combination of the following values:
2620 * @arg @ref LL_CKGA_PERIPH_AXI
2621 * @arg @ref LL_CKGA_PERIPH_AHBM
2622 * @arg @ref LL_CKGA_PERIPH_AHBS
2623 * @arg @ref LL_CKGA_PERIPH_SDMMC1
2624 * @arg @ref LL_CKGA_PERIPH_HPDMA1
2625 * @arg @ref LL_CKGA_PERIPH_CPU
2626 * @arg @ref LL_CKGA_PERIPH_GPU2DS0 (*)
2627 * @arg @ref LL_CKGA_PERIPH_GPU2DS1 (*)
2628 * @arg @ref LL_CKGA_PERIPH_GPU2DCL (*)
2629 * @arg @ref LL_CKGA_PERIPH_DMA2D
2630 * @arg @ref LL_CKGA_PERIPH_DCMIPP
2631 * @arg @ref LL_CKGA_PERIPH_LTDC (*)
2632 * @arg @ref LL_CKGA_PERIPH_FLASH
2633 * @arg @ref LL_CKGA_PERIPH_XSPI2
2634 * @arg @ref LL_CKGA_PERIPH_XSPI1
2635 * @arg @ref LL_CKGA_PERIPH_FMC
2636 * @arg @ref LL_CKGA_PERIPH_AXIRAM1
2637 * @arg @ref LL_CKGA_PERIPH_AXIRAM2
2638 * @arg @ref LL_CKGA_PERIPH_AXIRAM3
2639 * @arg @ref LL_CKGA_PERIPH_AXIRAM4
2640 * @arg @ref LL_CKGA_PERIPH_GFXMMUM
2641 * @arg @ref LL_CKGA_PERIPH_GFXMMUS
2642 * @arg @ref LL_CKGA_PERIPH_EXTI
2643 * @arg @ref LL_CKGA_PERIPH_JTAG
2644 *
2645 * (*) value not defined in all devices.
2646 * @retval uint32_t
2647 */
LL_CKGA_IsEnabledClock(uint32_t Periphs)2648 __STATIC_INLINE uint32_t LL_CKGA_IsEnabledClock(uint32_t Periphs)
2649 {
2650 return ((READ_BIT(RCC->CKGDISR, Periphs) == 0U) ? 1U : 0U);
2651 }
2652
2653 /**
2654 * @brief Disable clock gating for AXI bus peripherals.
2655 * @rmtoll CKGDISR AXICKG LL_CKGA_Disable\n
2656 * CKGDISR AHBMCKG LL_CKGA_Disable\n
2657 * CKGDISR SDMMC1CKG LL_CKGA_Disable\n
2658 * CKGDISR HPDMA1CKG LL_CKGA_Disable\n
2659 * CKGDISR CPUCKG LL_CKGA_Disable\n
2660 * CKGDISR GPU2DS0CKG LL_CKGA_Disable\n
2661 * CKGDISR GPU2DS1CKG LL_CKGA_Disable\n
2662 * CKGDISR GPUCLCKG LL_CKGA_Disable\n
2663 * CKGDISR DCMIPPCKG LL_CKGA_Disable\n
2664 * CKGDISR DMA2DCKG LL_CKGA_Disable\n
2665 * CKGDISR GFXMMUSCKG LL_CKGA_Disable\n
2666 * CKGDISR LTDCCKG LL_CKGA_Disable\n
2667 * CKGDISR GFXMMUMCKG LL_CKGA_Disable\n
2668 * CKGDISR AHBSCKG LL_CKGA_Disable\n
2669 * CKGDISR FMCCKG LL_CKGA_Disable\n
2670 * CKGDISR XSPI2CKG LL_CKGA_Disable\n
2671 * CKGDISR XSPI1CKG LL_CKGA_Disable\n
2672 * CKGDISR AXIRAM1CKG LL_CKGA_Disable\n
2673 * CKGDISR AXIRAM2CKG LL_CKGA_Disable\n
2674 * CKGDISR AXIRAM3CKG LL_CKGA_Disable\n
2675 * CKGDISR AXIRAM4CKG LL_CKGA_Disable\n
2676 * CKGDISR FLASHCKG LL_CKGA_Disable\n
2677 * CKGDISR EXTICKG LL_CKGA_Disable\n
2678 * CKGDISR JTAGCKG LL_CKGA_Disable
2679 * @param Periphs This parameter can be a combination of the following values:
2680 * @arg @ref LL_CKGA_PERIPH_AXI
2681 * @arg @ref LL_CKGA_PERIPH_AHBM
2682 * @arg @ref LL_CKGA_PERIPH_AHBS
2683 * @arg @ref LL_CKGA_PERIPH_SDMMC1
2684 * @arg @ref LL_CKGA_PERIPH_HPDMA1
2685 * @arg @ref LL_CKGA_PERIPH_CPU
2686 * @arg @ref LL_CKGA_PERIPH_GPU2DS0
2687 * @arg @ref LL_CKGA_PERIPH_GPU2DS1
2688 * @arg @ref LL_CKGA_PERIPH_GPU2DCL
2689 * @arg @ref LL_CKGA_PERIPH_DMA2D
2690 * @arg @ref LL_CKGA_PERIPH_DCMIPP
2691 * @arg @ref LL_CKGA_PERIPH_LTDC
2692 * @arg @ref LL_CKGA_PERIPH_FLASH
2693 * @arg @ref LL_CKGA_PERIPH_XSPI2
2694 * @arg @ref LL_CKGA_PERIPH_XSPI1
2695 * @arg @ref LL_CKGA_PERIPH_FMC
2696 * @arg @ref LL_CKGA_PERIPH_AXIRAM1
2697 * @arg @ref LL_CKGA_PERIPH_AXIRAM2
2698 * @arg @ref LL_CKGA_PERIPH_AXIRAM3
2699 * @arg @ref LL_CKGA_PERIPH_AXIRAM4
2700 * @arg @ref LL_CKGA_PERIPH_GFXMMUM
2701 * @arg @ref LL_CKGA_PERIPH_GFXMMUS
2702 * @arg @ref LL_CKGA_PERIPH_EXTI
2703 * @arg @ref LL_CKGA_PERIPH_JTAG
2704 *
2705 * (*) value not defined in all devices.
2706 * @retval None
2707 */
LL_CKGA_Disable(uint32_t Periphs)2708 __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)
2709 {
2710 SET_BIT(RCC->CKGDISR, Periphs);
2711 }
2712 /**
2713 * @}
2714 */
2715
2716 /**
2717 * @}
2718 */
2719
2720 /**
2721 * @}
2722 */
2723
2724 #endif /* defined(RCC) */
2725
2726 /**
2727 * @}
2728 */
2729
2730 #ifdef __cplusplus
2731 }
2732 #endif
2733
2734 #endif /* STM32H7RSxx_LL_BUS_H */
2735
