1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32N6xx_LL_ADC_H
21 #define STM32N6xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32n6xx.h"
29
30 /** @addtogroup STM32N6xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET (0x00000000UL)
56 #define ADC_SQR2_REGOFFSET (0x00000100UL)
57 #define ADC_SQR3_REGOFFSET (0x00000200UL)
58 #define ADC_SQR4_REGOFFSET (0x00000300UL)
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
61 | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/
63 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_NUMBER_MASK_POSBIT0)
64
65 /* Definition of ADC group regular sequencer bits information to be inserted */
66 /* into ADC group regular sequencer ranks literals definition. */
67 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
68 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
69 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
70 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
71 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)
72 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)
73 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)
74 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
75 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
76 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
77 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
78 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
79 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
80 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
81 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
82 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
83
84
85 /* Internal mask for ADC group injected sequencer: */
86 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
87 /* - data register offset */
88 /* - sequencer rank bits position into the selected register */
89
90 /* Internal register offset for ADC group injected data register */
91 /* (offset placed into a spare area of literal definition) */
92 #define ADC_JDR1_REGOFFSET (0x00000000UL)
93 #define ADC_JDR2_REGOFFSET (0x00000100UL)
94 #define ADC_JDR3_REGOFFSET (0x00000200UL)
95 #define ADC_JDR4_REGOFFSET (0x00000300UL)
96
97 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
98 | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
99 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_NUMBER_MASK_POSBIT0)
100 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/
101
102 /* Definition of ADC group injected sequencer bits information to be inserted */
103 /* into ADC group injected sequencer ranks literals definition. */
104 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
105 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
106 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
107 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
108
109 /* Internal mask for ADC group regular trigger: */
110 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
111 /* - regular trigger source */
112 /* - regular trigger edge */
113 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting
114 for compatibility with some ADC on other STM32
115 series having this setting set by HW default value) */
116
117 /* Mask containing trigger source masks for each of possible */
118 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
119 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
120 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
121 ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
122 ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
123 ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
124
125 /* Mask containing trigger edge masks for each of possible */
126 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
127 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
128 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
129 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
130 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
131 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
132
133 /* Definition of ADC group regular trigger bits information. */
134 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR1_EXTSEL_Pos)
135 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR1_EXTEN_Pos)
136
137
138 /* Internal mask for ADC group injected trigger: */
139 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
140 /* - injected trigger source */
141 /* - injected trigger edge */
142 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
143 compatibility with some ADC on other STM32 series
144 having this setting set by HW default value) */
145
146 /* Mask containing trigger source masks for each of possible */
147 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
148 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
149 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
150 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
151 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
152 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
153
154 /* Mask containing trigger edge masks for each of possible */
155 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
156 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
157 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
158 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
159 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
160 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
161
162 /* Definition of ADC group injected trigger bits information. */
163 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
164 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
165
166
167 /* Internal mask for ADC channel: */
168 /* To select into literal ADC_CHANNEL_LUT[] the relevant bits for: */
169 /* - channel identifier defined by bitfield */
170 /* - channel sampling time defined by SMPRx register offset */
171 /* and SMPx bits positions into SMPRx register */
172
173 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
174 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB */
175 #define ADC_CHANNEL_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
176 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in
177 register]) */
178
179 /* Channel differentiation between external channels (connected to GPIO pins) */
180 /* and internal channels (connected to internal paths) */
181 #define ADC_CHANNEL_EXTERNAL (0x00000000UL) /* Marker of external channel */
182 #define ADC_CHANNEL_INTERNAL_ADC1 (0x00000400UL) /* Marker of internal channel of ADC1 */
183 #define ADC_CHANNEL_INTERNAL_ADC2 (0x00000800UL) /* Marker of internal channel of ADC2 */
184
185 #define ADC_CHANNEL_NONE (0xFFU) /* Channel literal used for non connected channels */
186 #define ADC_CHANNEL_NUMBER_MASK (0x0000001FUL) /* Mask of channel number region in LL_ADC_CHANNEL_X
187 bitfield (values as decimal number in range [0; 255]) */
188 #define ADC_CHANNEL_INTERNAL_MASK (0x0000FF00UL) /* Mask of internal channel region in LL_ADC_CHANNEL_X
189 bitfield (values as bitfield for each config) */
190
191 /* Internal register offset for ADC channel sampling time configuration */
192 /* (offset placed into a spare area of literal definition) */
193 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
194 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
195 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
196 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET
197 in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
198
199 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
200 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK"
201 position in register */
202
203 /* Definition of channels ID bitfield information to be inserted into */
204 /* channels literals definition. */
205 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
206 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
207 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
208 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
209 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
210 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
211 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
212 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
213 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
214 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
215 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
216 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
217 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
218 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
219 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
220 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
221 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
222 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
223 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
224 #define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
225
226 /* Definition of channels sampling time information to be inserted into */
227 /* channels literals definition. */
228 /* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position */
229 /* in register. */
230 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
231 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
232 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
233 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
234 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
235 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
236 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
237 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
238 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
239 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
240 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
241 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
242 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
243 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
244 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
245 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
246 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
247 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
248 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
249 #define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
250
251 /* Definition of ADC channel look up table containing channels information */
252 static const uint32_t ADC_CHANNEL_LUT[] =
253 {
254 (ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD), /*!< ADC channel ADCx_IN0 */
255 (ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD), /*!< ADC channel ADCx_IN1 */
256 (ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD), /*!< ADC channel ADCx_IN2 */
257 (ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD), /*!< ADC channel ADCx_IN3 */
258 (ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD), /*!< ADC channel ADCx_IN4 */
259 (ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD), /*!< ADC channel ADCx_IN5 */
260 (ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD), /*!< ADC channel ADCx_IN6 */
261 (ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD), /*!< ADC channel ADCx_IN7 */
262 (ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD), /*!< ADC channel ADCx_IN9 */
263 (ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD), /*!< ADC channel ADCx_IN8 */
264 (ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD), /*!< ADC channel ADCx_IN10 */
265 (ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD), /*!< ADC channel ADCx_IN11 */
266 (ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD), /*!< ADC channel ADCx_IN12 */
267 (ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD), /*!< ADC channel ADCx_IN13 */
268 (ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD), /*!< ADC channel ADCx_IN14 */
269 (ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD), /*!< ADC channel ADCx_IN15 */
270 (ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD), /*!< ADC channel ADCx_IN16 */
271 (ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD), /*!< ADC channel ADCx_IN17 */
272 (ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD), /*!< ADC channel ADCx_IN18 */
273 (ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD), /*!< ADC channel ADCx_IN19 */
274 };
275
276
277 /* Internal mask for ADC mode single or differential ended: */
278 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
279 /* the relevant bits for: */
280 /* (concatenation of multiple bits used in different registers) */
281 /* - ADC calibration: calibration start, calibration factor get or set */
282 /* - ADC channels: set each ADC channel ending mode */
283 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
284 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
285 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
286 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen
287 to perform of shift when single mode is selected, shift value out of
288 channels bits range. */
289 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
290 mask of bit */
291 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode:
292 position of bit */
293 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
294 ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */
295
296 /* Internal mask for ADC analog watchdog: */
297 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
298 /* (concatenation of multiple bits used in different analog watchdogs, */
299 /* (feature of several watchdogs not available on all STM32 series)). */
300 /* - analog watchdog 1: monitored channel defined by number, */
301 /* selection of ADC group (ADC groups regular and-or injected). */
302 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
303 /* selection on groups. */
304
305 /* Definition of channels ID number information to be inserted into */
306 /* analog watchdog channels literals definition. */
307 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
308 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
309 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
310 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
311 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
312 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
313 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
314 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
315 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
316 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
317 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
318 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
319 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
320 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
321 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
322 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
323 ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
324 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
325 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
326 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
327 #define ADC_CHANNEL_19_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
328
329 #define ADC_AWD_CHANNEL_NUMBER_MASK (ADC_CFGR1_AWD1CH)
330 #define ADC_AWD_CHANNEL_NUMBER_BITOFFSET_POS (ADC_CFGR1_AWD1CH_Pos)
331
332 /* Internal register offset for ADC analog watchdog channel configuration */
333 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
334 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
335 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
336
337 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
338 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
339 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
340 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
341
342 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
343
344 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
345 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
346 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
347
348 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
349 in ADC_AWD_CRX_REGOFFSET_MASK */
350
351 /* Internal register offset for ADC analog watchdog threshold configuration */
352 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
353 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
354 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
355 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
356 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
357 in ADC_AWD_TRX_REGOFFSET_MASK */
358 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
359 threshold high: mask of bit */
360 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
361 threshold high: position of bit */
362 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
363 position to perform a shift of 4 ranks */
364
365 /* Internal mask for ADC offset: */
366 /* Internal register offset for ADC offset instance configuration */
367 #define ADC_OFR1_REGOFFSET (0x00000000UL)
368 #define ADC_OFR2_REGOFFSET (0x00000001UL)
369 #define ADC_OFR3_REGOFFSET (0x00000002UL)
370 #define ADC_OFR4_REGOFFSET (0x00000003UL)
371 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
372 | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
373
374 /* ADC registers bits groups */
375 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADEN | ADC_CR_ADDIS \
376 | ADC_CR_JADSTART | ADC_CR_JADSTP \
377 | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
378 HW property "rs": Software can read as well as set this bit.
379 Writing '0' has no effect on the bit value. */
380
381 /* Internal mask for ADC channel internal path*/
382 #define ADC_COMMON_PATH_INTERNAL_MASK (0x7UL << ADC_CCR_VREFEN_Pos) /*!< ADC measurement path to internal
383 channel mask in LL_ADC_CHANNEL bitfield */
384 #define ADC_PATH_INTERNAL_POS (16UL) /*!< ADC measurement path to internal
385 channel position in LL_ADC_CHANNEL bitfield */
386 #define ADC_PATH_INTERNAL_MASK (0x3UL << ADC_PATH_INTERNAL_POS) /*!< ADC measurement path to internal
387 channel mask in LL_ADC_CHANNEL bitfield */
388
389 /* ADC internal channels related definitions */
390 /* Internal voltage reference VrefInt */
391 #define VREFINT_CAL_ADDR ((uint16_t*) (0x460091B8UL)) /* Internal voltage reference, address of
392 parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
393 (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV).
394 On this STM32 series, it is required to load the OTP110 word before reading
395 this address.
396 In case of usage with HAL driver, refer to HAL_BSEC_OTP_Reload() */
397 #define VREFINT_CAL_VREF (1800UL) /* Analog voltage reference (Vref+) value
398 with which VrefInt has been calibrated in production
399 (tolerance: +-10 mV) (unit: mV). */
400
401 /**
402 * @}
403 */
404
405
406 /* Private macros ------------------------------------------------------------*/
407 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
408 * @{
409 */
410 /* Macro reserved for internal LL driver usage, not intended to be used in */
411 /* code of final user. */
412
413 /**
414 * @brief Driver macro reserved for internal use: set a pointer to
415 * a register from a register basis from which an offset
416 * is applied.
417 * @param __REG__ Register basis from which the offset is applied.
418 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
419 * @retval Pointer to register address
420 */
421 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
422 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
423
424 /**
425 * @brief Getter to access the ADC instance corresponding index in
426 * differential channel look up table
427 * @param __INSTANCE__ ADC instance
428 * @retval Look-up table index related to __INSTANCE__
429 */
430 #define __ADC_INSTANCE_INDEX(__INSTANCE__) \
431 ( ((__INSTANCE__) == ADC1) \
432 ? \
433 (0UL) \
434 : \
435 (1UL) \
436 )
437
438 #define __ADC_CHANNEL_INDEX(__CHANNEL__) \
439 ((__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_0 )) ? 0UL : \
440 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_1 )) ? 1UL : \
441 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_2 )) ? 2UL : \
442 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_3 )) ? 3UL : \
443 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_4 )) ? 4UL : \
444 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_5 )) ? 5UL : \
445 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_6 )) ? 6UL : \
446 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_7 )) ? 7UL : \
447 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_8 )) ? 8UL : \
448 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_9 )) ? 9UL : \
449 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_10)) ? 10UL : \
450 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_11)) ? 11UL : \
451 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_12)) ? 12UL : \
452 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_13)) ? 13UL : \
453 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_14)) ? 14UL : \
454 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_15)) ? 15UL : \
455 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_16)) ? 16UL : \
456 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_17)) ? 17UL : \
457 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_18)) ? 18UL : \
458 (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_19)) ? 19UL : 0UL)
459
460 /**
461 * @}
462 */
463
464
465 /* Exported types ------------------------------------------------------------*/
466 #if defined(USE_FULL_LL_DRIVER)
467 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
468 * @{
469 */
470
471 /**
472 * @brief Structure definition of some features of ADC common parameters
473 * and multimode
474 * (all ADC instances belonging to the same ADC common instance).
475 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
476 * is conditioned to ADC instances state (all ADC instances
477 * sharing the same ADC common instance):
478 * All ADC instances sharing the same ADC common instance must be
479 * disabled.
480 */
481 typedef struct
482 {
483 #if defined(ADC_MULTIMODE_SUPPORT)
484 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode
485 (for devices with several ADC instances).
486 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
487 This feature can be modified afterwards using unitary function
488 @ref LL_ADC_SetMultimode(). */
489
490 uint32_t MultiDataFormat; /*!< Set ADC multimode conversion data format of ADC group regular: conversion
491 data in data register of each ADC instance or ADC common instance.
492 This parameter can be a value of @ref ADC_LL_EC_MULTI_DATA_FORMAT
493 This feature can be modified afterwards using unitary function
494 @ref LL_ADC_SetMultiDataFormat(). */
495
496 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
497 Relevant only for multimode modes: interleaved based modes.
498 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
499 This feature can be modified afterwards using unitary function
500 @ref LL_ADC_SetMultiTwoSamplingDelay(). */
501 #endif /* ADC_MULTIMODE_SUPPORT */
502
503 } LL_ADC_CommonInitTypeDef;
504
505 /**
506 * @brief Structure definition of some features of ADC instance.
507 * @note These parameters have an impact on ADC scope: ADC instance.
508 * Affects both group regular and group injected (availability
509 * of ADC group injected depends on STM32 series).
510 * Refer to corresponding unitary functions into
511 * @ref ADC_LL_EF_Configuration_ADC_Instance .
512 * @note The setting of these parameters by function @ref LL_ADC_Init()
513 * is conditioned to ADC state:
514 * ADC instance must be disabled.
515 * This condition is applied to all ADC features, for efficiency
516 * and compatibility over all STM32 series. However, the different
517 * features can be set under different ADC state conditions
518 * (setting possible with ADC enabled without conversion on going,
519 * ADC enabled with conversion on going, ...)
520 * Each feature can be updated afterwards with a unitary function
521 * and potentially with ADC in a different state than disabled,
522 * refer to description of each function for setting
523 * conditioned to ADC state.
524 */
525 typedef struct
526 {
527 uint32_t Resolution; /*!< Set ADC resolution.
528 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
529 This feature can be modified afterwards using unitary function
530 @ref LL_ADC_SetResolution(). */
531
532 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without
533 oversampling.
534 This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
535
536 uint32_t LowPowerMode; /*!< Set ADC low power mode.
537 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
538 This feature can be modified afterwards using unitary function
539 @ref LL_ADC_SetLPModeAutoWait(). */
540
541 } LL_ADC_InitTypeDef;
542
543 /**
544 * @brief Structure definition of some features of ADC group regular.
545 * @note These parameters have an impact on ADC scope: ADC group regular.
546 * Refer to corresponding unitary functions into
547 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
548 * (functions with prefix "REG").
549 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
550 * is conditioned to ADC state:
551 * ADC instance must be disabled.
552 * This condition is applied to all ADC features, for efficiency
553 * and compatibility over all STM32 series. However, the different
554 * features can be set under different ADC state conditions
555 * (setting possible with ADC enabled without conversion on going,
556 * ADC enabled with conversion on going, ...)
557 * Each feature can be updated afterwards with a unitary function
558 * and potentially with ADC in a different state than disabled,
559 * refer to description of each function for setting
560 * conditioned to ADC state.
561 */
562 typedef struct
563 {
564 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
565 from external peripheral (timer event, external interrupt line).
566 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
567 @note On this STM32 series, setting trigger source to external trigger also
568 set trigger polarity to rising edge(default setting for compatibility
569 with some ADC on other STM32 series having this setting set by HW
570 default value).
571 In case of need to modify trigger edge, use function
572 @ref LL_ADC_REG_SetTriggerEdge().
573 This feature can be modified afterwards using unitary function
574 @ref LL_ADC_REG_SetTriggerSource(). */
575
576 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
577 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
578 This feature can be modified afterwards using unitary function
579 @ref LL_ADC_REG_SetSequencerLength(). */
580
581 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
582 and scan conversions interrupted every selected number of ranks.
583 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
584 @note This parameter has an effect only if group regular sequencer is
585 enabled (scan length of 2 ranks or more).
586 This feature can be modified afterwards using unitary function
587 @ref LL_ADC_REG_SetSequencerDiscont(). */
588
589 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
590 conversions are performed in single mode (one conversion per trigger) or in
591 continuous mode (after the first trigger, following conversions launched
592 successively automatically).
593 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
594 Note: It is not possible to enable both ADC group regular continuous mode
595 and discontinuous mode.
596 This feature can be modified afterwards using unitary function
597 @ref LL_ADC_REG_SetContinuousMode(). */
598
599 uint32_t DataTransferMode; /*!< Set ADC group regular conversion data transfer: no transfer, transfer
600 by DMA or other peripherals.
601 This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER
602 This feature can be modified afterwards using unitary function
603 @ref LL_ADC_REG_SetDataTransferMode(). */
604
605 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
606 data preserved or overwritten.
607 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
608 This feature can be modified afterwards using unitary function
609 @ref LL_ADC_REG_SetOverrun(). */
610
611 } LL_ADC_REG_InitTypeDef;
612
613 /**
614 * @brief Structure definition of some features of ADC group injected.
615 * @note These parameters have an impact on ADC scope: ADC group injected.
616 * Refer to corresponding unitary functions into
617 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
618 * (functions with prefix "INJ").
619 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
620 * is conditioned to ADC state:
621 * ADC instance must be disabled.
622 * This condition is applied to all ADC features, for efficiency
623 * and compatibility over all STM32 series. However, the different
624 * features can be set under different ADC state conditions
625 * (setting possible with ADC enabled without conversion on going,
626 * ADC enabled with conversion on going, ...)
627 * Each feature can be updated afterwards with a unitary function
628 * and potentially with ADC in a different state than disabled,
629 * refer to description of each function for setting
630 * conditioned to ADC state.
631 */
632 typedef struct
633 {
634 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start)
635 or from external peripheral (timer event, external interrupt line).
636 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
637 @note On this STM32 series, setting trigger source to external trigger also
638 set trigger polarity to rising edge (default setting for
639 compatibility with some ADC on other STM32 series having this
640 setting set by HW default value).
641 In case of need to modify trigger edge, use function
642 @ref LL_ADC_INJ_SetTriggerEdge().
643 This feature can be modified afterwards using unitary function
644 @ref LL_ADC_INJ_SetTriggerSource(). */
645
646 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
647 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
648 This feature can be modified afterwards using unitary function
649 @ref LL_ADC_INJ_SetSequencerLength(). */
650
651 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
652 and scan conversions interrupted every selected number of ranks.
653 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
654 @note This parameter has an effect only if group injected sequencer is
655 enabled (scan length of 2 ranks or more).
656 This feature can be modified afterwards using unitary function
657 @ref LL_ADC_INJ_SetSequencerDiscont(). */
658
659 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group
660 regular.
661 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
662 Note: This parameter must be set to set to independent trigger if injected
663 trigger source is set to an external trigger.
664 This feature can be modified afterwards using unitary function
665 @ref LL_ADC_INJ_SetTrigAuto(). */
666
667 } LL_ADC_INJ_InitTypeDef;
668
669 /**
670 * @}
671 */
672 #endif /* USE_FULL_LL_DRIVER */
673
674 /* Exported constants --------------------------------------------------------*/
675 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
676 * @{
677 */
678
679 /** @defgroup ADC_LL_EC_FLAG ADC flags
680 * @brief Flags defines which can be used with LL_ADC_ReadReg function
681 * @{
682 */
683 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
684 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
685 conversion */
686 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
687 conversions */
688 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
689 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
690 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary
691 conversion */
692 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence
693 conversions */
694 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
695 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
696 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
697 #if defined(ADC_MULTIMODE_SUPPORT)
698 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
699 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
700 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of
701 unitary conversion */
702 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of
703 unitary conversion */
704 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of
705 sequence conversions */
706 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of
707 sequence conversions */
708 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular
709 overrun */
710 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular
711 overrun */
712 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of
713 sampling phase */
714 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of
715 sampling phase */
716 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of
717 unitary conversion */
718 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of
719 unitary conversion */
720 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of
721 sequence conversions */
722 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of
723 sequence conversions */
724 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1
725 of the ADC master */
726 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1
727 of the ADC slave */
728 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2
729 of the ADC master */
730 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2
731 of the ADC slave */
732 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3
733 of the ADC master */
734 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3
735 of the ADC slave */
736 #endif /* ADC_MULTIMODE_SUPPORT */
737 /**
738 * @}
739 */
740
741 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
742 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
743 * @{
744 */
745 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
746 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
747 conversion */
748 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
749 conversions */
750 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
751 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
752 phase */
753 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary
754 conversion */
755 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence
756 conversions */
757 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
758 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
759 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
760
761 /**
762 * @}
763 */
764
765 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
766 * @{
767 */
768 /* List of ADC registers intended to be used (most commonly) with */
769 /* DMA transfer. */
770 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
771 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /*!< ADC group regular conversion data register
772 (corresponding to register DR) to be used with ADC configured in independent
773 mode. Without DMA transfer, register accessed by LL function
774 @ref LL_ADC_REG_ReadConversionData32() */
775 #if defined(ADC_MULTIMODE_SUPPORT)
776 #define LL_ADC_DMA_REG_REGULAR_MULTI_NO_PACKING (0x00000001UL) /*!< ADC group regular conversion data register
777 to be used with ADC configured in multimode (available on STM32 devices
778 with several ADC instances), without data packing.
779 Register used is CDR2, compliant with all ADC multimode data format
780 and data width, refer to description of literals in
781 @ref ADC_LL_EC_MULTI_DATA_FORMAT.
782 Without DMA transfer, register accessed by LL function
783 @ref LL_ADC_REG_ReadMultiConvNoPacking() */
784 #define LL_ADC_DMA_REG_REGULAR_MULTI_PACKING (0x00000002UL) /*!< ADC group regular conversion data register
785 to be used with ADC configured in multimode (available on STM32 devices
786 with several ADC instances), with data packing.
787 Register used is CDR, usable under conditions of ADC multimode data format
788 selected and data width, refer to description of literals in
789 @ref ADC_LL_EC_MULTI_DATA_FORMAT.
790 Without DMA transfer, register accessed by LL function
791 @ref LL_ADC_REG_ReadMultiConvPacking() */
792 #endif /* ADC_MULTIMODE_SUPPORT */
793 /**
794 * @}
795 */
796
797 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
798 * @{
799 */
800 /* Note: Other measurement paths to internal channels may be available */
801 /* (connections to other peripherals). */
802 /* If they are not listed below, they do not require any specific */
803 /* path enable. In this case, Access to measurement path is done */
804 /* only by selecting the corresponding ADC internal channel. */
805 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
806 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
807 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
808 /**
809 * @}
810 */
811
812 /** @defgroup ADC_LL_EC_PATH_INTERNAL ADC instance - Measurement path to internal channels
813 * @{
814 */
815 /* Note: Other measurement paths to internal channels may be available */
816 /* (connections to other peripherals). */
817 /* If they are not listed below, they do not require any specific */
818 /* path enable. In this case, Access to measurement path is done */
819 /* only by selecting the corresponding ADC internal channel. */
820 #define LL_ADC_PATH_INTERNAL_VDDCORE (ADC_OR_OP2 << ADC_PATH_INTERNAL_POS) /*!< ADC measurement path
821 to internal channel VddCore */
822 /**
823 * @}
824 */
825
826 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
827 * @{
828 */
829 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
830 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
831 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
832 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
833 /**
834 * @}
835 */
836
837 /** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
838 * @{
839 */
840 #define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC conversion data */
841 #define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC conversion data */
842 #define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC conversion data */
843 #define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC conversion data */
844 #define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC conversion data */
845 #define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC conversion data */
846 #define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC conversion data */
847 #define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC conversion data */
848 #define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC conversion data */
849 #define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC conversion data */
850 #define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC conversion data */
851 #define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC conversion data */
852 #define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC conversion data */
853 #define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC conversion data */
854 #define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC conversion data */
855 #define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC conversion data */
856 /**
857 * @}
858 */
859
860 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
861 * @{
862 */
863 #define LL_ADC_LP_AUTOWAIT_DISABLE (0x00000000UL) /*!< ADC low power mode auto delay disabled. */
864 #define LL_ADC_LP_AUTOWAIT_ENABLE (ADC_CFGR1_AUTDLY) /*!< ADC low power mode auto delay enabled: dynamic
865 low power mode, ADC conversions are performed only when necessary
866 (when previous ADC conversion data is read).
867 See description with function @ref LL_ADC_SetLPModeAutoWait(). */
868 /**
869 * @}
870 */
871 /* Definitions for backward compatibility with legacy STM32 series */
872 #define LL_ADC_LP_MODE_NONE LL_ADC_LP_AUTOWAIT_DISABLE
873 #define LL_ADC_LP_AUTOWAIT LL_ADC_LP_AUTOWAIT_ENABLE
874
875 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset instance
876 * @{
877 */
878 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level
879 to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */
880 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level
881 to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */
882 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level
883 to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */
884 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level
885 to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */
886 /**
887 * @}
888 */
889
890 /** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode
891 * @{
892 */
893 #define LL_ADC_OFFSET_SIGNED_SAT_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled */
894 #define LL_ADC_OFFSET_SIGNED_SAT_ENABLE (ADC_OFCFGR1_SSAT) /*!< ADC offset signed saturation is enabled */
895 /**
896 * @}
897 */
898
899 /** @defgroup ADC_LL_EC_OFFSET_UNSIGNED_SATURATION ADC instance - Offset unsigned saturation mode
900 * @{
901 */
902 #define LL_ADC_OFFSET_UNSIGNED_SAT_DISABLE (0x00000000UL) /*!< ADC offset unsigned saturation is disabled */
903 #define LL_ADC_OFFSET_UNSIGNED_SAT_ENABLE (ADC_OFCFGR1_USAT) /*!< ADC offset unsigned saturation is enabled */
904 /**
905 * @}
906 */
907
908 /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
909 * @{
910 */
911 #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative */
912 #define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFCFGR1_POSOFF) /*!< ADC offset is positive */
913 /**
914 * @}
915 */
916
917 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
918 * @{
919 */
920 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
921 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32
922 devices)*/
923 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
924 /**
925 * @}
926 */
927
928 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
929 * @{
930 */
931 #define LL_ADC_CHANNEL_0 ( 0UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN0 */
932 #define LL_ADC_CHANNEL_1 ( 1UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN1 */
933 #define LL_ADC_CHANNEL_2 ( 2UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN2 */
934 #define LL_ADC_CHANNEL_3 ( 3UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN3 */
935 #define LL_ADC_CHANNEL_4 ( 4UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN4 */
936 #define LL_ADC_CHANNEL_5 ( 5UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN5 */
937 #define LL_ADC_CHANNEL_6 ( 6UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN6 */
938 #define LL_ADC_CHANNEL_7 ( 7UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN7 */
939 #define LL_ADC_CHANNEL_8 ( 8UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN8 */
940 #define LL_ADC_CHANNEL_9 ( 9UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN9 */
941 #define LL_ADC_CHANNEL_10 (10UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN10 */
942 #define LL_ADC_CHANNEL_11 (11UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN11 */
943 #define LL_ADC_CHANNEL_12 (12UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN12 */
944 #define LL_ADC_CHANNEL_13 (13UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN13 */
945 #define LL_ADC_CHANNEL_14 (14UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN14 */
946 #define LL_ADC_CHANNEL_15 (15UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN15 */
947 #define LL_ADC_CHANNEL_16 (16UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN16 */
948 #define LL_ADC_CHANNEL_17 (17UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN17 */
949 #define LL_ADC_CHANNEL_18 (18UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN18 */
950 #define LL_ADC_CHANNEL_19 (19UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE) /*!< Channel ADCx_IN19 */
951 #define LL_ADC_CHANNEL_VREFINT (17UL \
952 | ADC_CHANNEL_INTERNAL_ADC1 \
953 | LL_ADC_PATH_INTERNAL_VREFINT) /*!< ADC internal channel
954 connected to VrefInt: Internal voltage reference.
955 On this STM32 series, ADC channel available only on ADC instance: ADC1. */
956 #define LL_ADC_CHANNEL_VBAT (16UL \
957 | ADC_CHANNEL_INTERNAL_ADC2 \
958 | LL_ADC_PATH_INTERNAL_VBAT) /*!< ADC internal channel
959 connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have
960 channel voltage always below Vdda.
961 On this STM32 series, ADC channel available only on ADC instance: ADC2. */
962 #define LL_ADC_CHANNEL_VDDCORE (17UL \
963 | ADC_CHANNEL_INTERNAL_ADC2 \
964 | LL_ADC_PATH_INTERNAL_VDDCORE) /*!< ADC internal channel
965 connected to VddCore.
966 On this STM32 series, ADC channel available only on ADC instance: ADC2. */
967 static const uint8_t ADC_CHANNEL_DIFF_LUT[2][20] =
968 {
969 {
970 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN0 -> VREF- */
971 (uint8_t)(LL_ADC_CHANNEL_0), /*!< Channel ADCx_INN1 -> ADCx_INP0 */
972 (uint8_t)(LL_ADC_CHANNEL_6), /*!< Channel ADCx_INN2 -> ADCx_INP6 */
973 (uint8_t)(LL_ADC_CHANNEL_7), /*!< Channel ADCx_INN3 -> ADCx_INP7 */
974 (uint8_t)(LL_ADC_CHANNEL_8), /*!< Channel ADCx_INN4 -> ADCx_INP8 */
975 (uint8_t)(LL_ADC_CHANNEL_9), /*!< Channel ADCx_INN5 -> ADCx_INP9 */
976 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN6 -> VREF- */
977 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN7 -> VREF- */
978 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN8 -> VREF- */
979 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN9 -> VREF- */
980 (uint8_t)(LL_ADC_CHANNEL_11), /*!< Channel ADCx_INN10 -> ADCx_INP11 */
981 (uint8_t)(LL_ADC_CHANNEL_12), /*!< Channel ADCx_INN11 -> ADCx_INP12 */
982 (uint8_t)(LL_ADC_CHANNEL_13), /*!< Channel ADCx_INN12 -> ADCx_INP13 */
983 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN13 -> VREF- */
984 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN14 -> VREF- */
985 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN15 -> VREF- */
986 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN16 -> VREF- */
987 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN17 -> VREF- */
988 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN18 -> VREF- */
989 (uint8_t)(ADC_CHANNEL_NONE) /*!< Channel ADCx_INN19 -> VREF- */
990 },
991 {
992 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN0 -> VREF- */
993 (uint8_t)(LL_ADC_CHANNEL_0), /*!< Channel ADCx_INN1 -> ADCx_INP0 */
994 (uint8_t)(LL_ADC_CHANNEL_6), /*!< Channel ADCx_INN2 -> ADCx_INP6 */
995 (uint8_t)(LL_ADC_CHANNEL_7), /*!< Channel ADCx_INN3 -> ADCx_INP7 */
996 (uint8_t)(LL_ADC_CHANNEL_8), /*!< Channel ADCx_INN4 -> ADCx_INP8 */
997 (uint8_t)(LL_ADC_CHANNEL_9), /*!< Channel ADCx_INN5 -> ADCx_INP9 */
998 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN6 -> VREF- */
999 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN7 -> VREF- */
1000 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN8 -> VREF- */
1001 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN9 -> VREF- */
1002 (uint8_t)(LL_ADC_CHANNEL_11), /*!< Channel ADCx_INN10 -> ADCx_INP11 */
1003 (uint8_t)(LL_ADC_CHANNEL_12), /*!< Channel ADCx_INN11 -> ADCx_INP12 */
1004 (uint8_t)(LL_ADC_CHANNEL_13), /*!< Channel ADCx_INN12 -> ADCx_INP13 */
1005 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN13 -> VREF- */
1006 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN14 -> VREF- */
1007 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN15 -> VREF- */
1008 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN16 -> VREF- */
1009 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN17 -> VREF- */
1010 (uint8_t)(ADC_CHANNEL_NONE), /*!< Channel ADCx_INN18 -> VREF- */
1011 (uint8_t)(ADC_CHANNEL_NONE) /*!< Channel ADCx_INN19 -> VREF- */
1012 }
1013 };
1014 /**
1015 * @}
1016 */
1017
1018 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
1019 * @{
1020 */
1021 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular
1022 conversion trigger internal: SW start. */
1023 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1024 conversion trigger from external peripheral: external interrupt line 11.
1025 Trigger edge set to rising edge (default setting). */
1026 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1027 conversion trigger from external peripheral: TIM1 channel 1 event
1028 (capture compare: input capture or output capture).
1029 Trigger edge set to rising edge (default setting). */
1030 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1031 conversion trigger from external peripheral: TIM1 channel 2 event
1032 (capture compare: input capture or output capture).
1033 Trigger edge set to rising edge (default setting). */
1034 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
1035 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1036 conversion trigger from external peripheral: TIM1 channel 3 event
1037 (capture compare: input capture or output capture).
1038 Trigger edge set to rising edge (default setting). */
1039 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1040 conversion trigger from external peripheral: TIM1 TRGO event.
1041 Trigger edge set to rising edge (default setting). */
1042 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
1043 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1044 conversion trigger from external peripheral: TIM1 TRGO2 event.
1045 Trigger edge set to rising edge (default setting). */
1046 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
1047 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1048 conversion trigger from external peripheral: TIM2 channel 2 event
1049 (capture compare: input capture or output capture).
1050 Trigger edge set to rising edge (default setting). */
1051 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
1052 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1053 conversion trigger from external peripheral: TIM2 TRGO event.
1054 Trigger edge set to rising edge (default setting). */
1055 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 \
1056 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1057 conversion trigger from external peripheral: TIM3 channel 4 event
1058 (capture compare: input capture or output capture).
1059 Trigger edge set to rising edge (default setting). */
1060 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 \
1061 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1062 conversion trigger from external peripheral: TIM3 TRGO event.
1063 Trigger edge set to rising edge (default setting). */
1064 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 \
1065 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1066 conversion trigger from external peripheral: TIM4 channel 4 event
1067 (capture compare: input capture or output capture).
1068 Trigger edge set to rising edge (default setting). */
1069 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 \
1070 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1071 conversion trigger from external peripheral: TIM4 TRGO event.
1072 Trigger edge set to rising edge (default setting). */
1073 #define LL_ADC_REG_TRIG_EXT_TIM5_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 \
1074 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1075 conversion trigger from external peripheral: TIM5 TRGO event.
1076 Trigger edge set to rising edge (default setting). */
1077 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 \
1078 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
1079 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1080 conversion trigger from external peripheral: TIM6 TRGO event.
1081 Trigger edge set to rising edge (default setting). */
1082 #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR1_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1083 conversion trigger from external peripheral: TIM7 TRGO event. Trigger edge
1084 set to rising edge (default setting). */
1085 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_0 \
1086 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1087 conversion trigger from external peripheral: TIM8 TRGO event.
1088 Trigger edge set to rising edge (default setting). */
1089 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 \
1090 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1091 conversion trigger from external peripheral: TIM8 TRGO2 event.
1092 Trigger edge set to rising edge (default setting). */
1093 #define LL_ADC_REG_TRIG_EXT_TIM9_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 \
1094 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1095 conversion trigger from external peripheral: TIM9 channel 1 event
1096 (capture compare: input capture or output capture).
1097 Trigger edge set to rising edge (default setting). */
1098 #define LL_ADC_REG_TRIG_EXT_TIM9_TRGO (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 \
1099 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1100 conversion trigger from external peripheral: TIM9 TRGO event.
1101 Trigger edge set to rising edge (default setting). */
1102 #define LL_ADC_REG_TRIG_EXT_TIM12_TRGO (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 \
1103 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1104 conversion trigger from external peripheral: TIM12 TRGO event.
1105 Trigger edge set to rising edge (default setting). */
1106 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 \
1107 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1108 conversion trigger from external peripheral: TIM15 TRGO event.
1109 Trigger edge set to rising edge (default setting). */
1110 #define LL_ADC_REG_TRIG_EXT_TIM18_TRGO (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 \
1111 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
1112 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1113 conversion trigger from external peripheral: TIM18 TRGO event.
1114 Trigger edge set to rising edge (default setting). */
1115 #define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_3 \
1116 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1117 conversion trigger from external peripheral: LPTIM1 channel 1 event.
1118 Trigger edge set to rising edge (default setting). */
1119 #define LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_3 \
1120 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1121 conversion trigger from external peripheral: LPTIM2 channel 2 event.
1122 Trigger edge set to rising edge (default setting). */
1123 #define LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_3 \
1124 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1125 conversion trigger from external peripheral: LPTIM3 channel 3 event.
1126 Trigger edge set to rising edge (default setting). */
1127 /**
1128 * @}
1129 */
1130
1131 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
1132 * @{
1133 */
1134 #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
1135 trigger polarity set to rising edge */
1136 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion
1137 trigger polarity set to falling edge */
1138 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
1139 trigger polarity set to both rising and falling edges */
1140 /**
1141 * @}
1142 */
1143
1144 /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
1145 * @{
1146 */
1147 #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration
1148 is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME. */
1149 #define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately
1150 after end of conversion, and stops upon trigger event.
1151 Note: First conversion is using minimal sampling time
1152 (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME). */
1153 #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG)/*!< ADC conversions sampling phase is controlled
1154 by trigger events: Trigger rising edge = start sampling,
1155 Trigger falling edge = stop sampling and start conversion. */
1156 /**
1157 * @}
1158 */
1159
1160 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
1161 * @{
1162 */
1163 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
1164 one conversion per trigger */
1165 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode:
1166 after the first trigger, following conversions launched successively
1167 automatically */
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup ADC_LL_EC_REG_DATA_TRANSFER ADC group regular - Data transfer mode of ADC conversion data
1173 * @{
1174 */
1175 #define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions data are available
1176 in ADC data register only */
1177 #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA,
1178 in limited mode (one shot mode): DMA transfer requests are stopped when
1179 number of DMA data transfers (number of ADC conversions) is reached.
1180 This ADC mode is intended to be used with DMA mode non-circular. */
1181 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMNGT_1 \
1182 | ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA,
1183 in unlimited mode: DMA transfer requests are unlimited, whatever
1184 number of DMA data transferred (number of ADC conversions).
1185 This ADC mode is intended to be used with DMA mode circular. */
1186 #define LL_ADC_REG_MDF_TRANSFER (ADC_CFGR1_DMNGT_1) /*!< ADC conversion data are transferred to MDF */
1187 /**
1188 * @}
1189 */
1190
1191 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
1192 * @{
1193 */
1194 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
1195 data preserved */
1196 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun:
1197 data overwritten */
1198 /**
1199 * @}
1200 */
1201
1202 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1203 * @{
1204 */
1205 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable
1206 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1207 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1208 with 2 ranks in the sequence */
1209 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1210 with 3 ranks in the sequence */
1211 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1212 with 4 ranks in the sequence */
1213 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1214 with 5 ranks in the sequence */
1215 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1216 with 6 ranks in the sequence */
1217 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1218 with 7 ranks in the sequence */
1219 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1 \
1220 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1221 with 8 ranks in the sequence */
1222 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3) /*!< ADC group regular sequencer enable
1223 with 9 ranks in the sequence */
1224 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1225 with 10 ranks in the sequence */
1226 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1227 with 11 ranks in the sequence */
1228 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \
1229 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1230 with 12 ranks in the sequence */
1231 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1232 with 13 ranks in the sequence */
1233 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1234 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1235 with 14 ranks in the sequence */
1236 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1237 | ADC_SQR1_L_1) /*!< ADC group regular sequencerenable
1238 with 15 ranks in the sequence */
1239 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1240 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1241 with 16 ranks in the sequence */
1242 /**
1243 * @}
1244 */
1245
1246 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1247 * @{
1248 */
1249 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
1250 discontinuous mode disable */
1251 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
1252 discontinuous mode enable with sequence interruption every rank */
1253 #define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
1254 discontinuous mode enabled with sequence interruption every 2 ranks */
1255 #define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
1256 discontinuous mode enable with sequence interruption every 3 ranks */
1257 #define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 \
1258 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
1259 discontinuous mode enable with sequence interruption every 4 ranks */
1260 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
1261 discontinuous mode enable with sequence interruption every 5 ranks */
1262 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_0 \
1263 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
1264 discontinuous mode enable with sequence interruption every 6 ranks */
1265 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 \
1266 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
1267 discontinuous mode enable with sequence interruption every 7 ranks */
1268 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 \
1269 | ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
1270 discontinuous mode enable with sequence interruption every 8 ranks */
1271 /**
1272 * @}
1273 */
1274
1275 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1276 * @{
1277 */
1278 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group
1279 regular sequencer rank 1 */
1280 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group
1281 regular sequencer rank 2 */
1282 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group
1283 regular sequencer rank 3 */
1284 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group
1285 regular sequencer rank 4 */
1286 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group
1287 regular sequencer rank 5 */
1288 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group
1289 regular sequencer rank 6 */
1290 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group
1291 regular sequencer rank 7 */
1292 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group
1293 regular sequencer rank 8 */
1294 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group
1295 regular sequencer rank 9 */
1296 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group
1297 regular sequencer rank 10 */
1298 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group
1299 regular sequencer rank 11 */
1300 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group
1301 regular sequencer rank 12 */
1302 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group
1303 regular sequencer rank 13 */
1304 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group
1305 regular sequencer rank 14 */
1306 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group
1307 regular sequencer rank 15 */
1308 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group
1309 regular sequencer rank 16 */
1310 /**
1311 * @}
1312 */
1313
1314 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1315 * @{
1316 */
1317 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group inject.
1318 conversion trigger internal: SW start. */
1319 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1320 conversion trigger from external peripheral: external interrupt line 15.
1321 Trigger edge set to rising edge (default setting). */
1322 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1323 conversion trigger from external peripheral: TIM1 channel 4 event
1324 (capture compare: input capture or output capture).
1325 Trigger edge set to rising edge (default setting). */
1326 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1327 conversion trigger from external peripheral: TIM1 TRGO event.
1328 Trigger edge set to rising edge (default setting). */
1329 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
1330 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1331 conversion trigger from external peripheral: TIM1 TRGO2 event.
1332 Trigger edge set to rising edge (default setting). */
1333 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
1334 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1335 conversion trigger from external peripheral: TIM2 channel 1 event
1336 (capture compare: input capture or output capture).
1337 Trigger edge set to rising edge (default setting). */
1338 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
1339 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1340 conversion trigger from external peripheral: TIM2 TRGO event.
1341 Trigger edge set to rising edge (default setting). */
1342 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1343 conversion trigger from external peripheral: TIM3 channel 1 event
1344 (capture compare: input capture or output capture).
1345 Trigger edge set to rising edge (default setting). */
1346 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 \
1347 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1348 conversion trigger from external peripheral: TIM3 channel 3 event
1349 (capture compare: input capture or output capture).
1350 Trigger edge set to rising edge (default setting). */
1351 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \
1352 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1353 conversion trigger from external peripheral: TIM3 channel 4 event
1354 (capture compare: input capture or output capture).
1355 Trigger edge set to rising edge (default setting). */
1356 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \
1357 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1358 conversion trigger from external peripheral: TIM3 TRGO event.
1359 Trigger edge set to rising edge (default setting). */
1360 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
1361 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1362 conversion trigger from external peripheral: TIM4 TRGO event.
1363 Trigger edge set to rising edge (default setting). */
1364 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
1365 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1366 conversion trigger from external peripheral: TIM5 TRGO event.
1367 Trigger edge set to rising edge (default setting). */
1368 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
1369 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1370 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1371 conversion trigger from external peripheral: TIM6 TRGO event.
1372 Trigger edge set to rising edge (default setting). */
1373 #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1374 conversion trigger from external peripheral: TIM7 TRGO event.
1375 Trigger edge set to rising edge (default setting). */
1376 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 \
1377 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1378 conversion trigger from external peripheral: TIM8 TRGO event.
1379 Trigger edge set to rising edge (default setting). */
1380 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \
1381 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1382 conversion trigger from external peripheral: TIM8 TRGO2 event.
1383 Trigger edge set to rising edge (default setting). */
1384 #define LL_ADC_INJ_TRIG_EXT_TIM9_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \
1385 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1386 conversion trigger from external peripheral: TIM9 channel 2 event
1387 (capture compare: input capture or output capture).
1388 Trigger edge set to rising edge (default setting). */
1389 #define LL_ADC_INJ_TRIG_EXT_TIM9_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \
1390 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1391 conversion trigger from external peripheral: TIM9 TRGO event.
1392 Trigger edge set to rising edge (default setting). */
1393 #define LL_ADC_INJ_TRIG_EXT_TIM12_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \
1394 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1395 conversion trigger from external peripheral: TIM12 TRGO event.
1396 Trigger edge set to rising edge (default setting). */
1397 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \
1398 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1399 conversion trigger from external peripheral: TIM12 TRGO event.
1400 Trigger edge set to rising edge (default setting). */
1401 #define LL_ADC_INJ_TRIG_EXT_TIM18_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \
1402 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1403 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1404 conversion trigger from external peripheral: TIM12 TRGO event.
1405 Trigger edge set to rising edge (default setting). */
1406 #define LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 \
1407 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1408 conversion trigger from external peripheral: LPTIM1 channel 2 event.
1409 Trigger edge set to rising edge (default setting). */
1410 #define LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 \
1411 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1412 conversion trigger from external peripheral: LPTIM2 channel 2 event.
1413 Trigger edge set to rising edge (default setting). */
1414 #define LL_ADC_INJ_TRIG_EXT_LPTIM3_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 \
1415 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
1416 conversion trigger from external peripheral: LPTIM3 channel 2 event.
1417 Trigger edge set to rising edge (default setting). */
1418
1419 /**
1420 * @}
1421 */
1422
1423 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1424 * @{
1425 */
1426 #define LL_ADC_INJ_TRIG_EXT_RISING (ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity
1427 set to rising edge */
1428 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1) /*!< ADC group injected conversion trigger polarity
1429 set to falling edge */
1430 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 \
1431 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity
1432 set to both rising and falling edges */
1433 /**
1434 * @}
1435 */
1436
1437 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1438 * @{
1439 */
1440 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent.
1441 Setting mandatory if ADC group injected injected trigger source is set to
1442 an external trigger. */
1443 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group
1444 regular. Setting compliant only with group injected trigger source set to
1445 SW start, without any further action on ADC group injected conversion start
1446 or stop: in this case, ADC group injected is controlled only from ADC group
1447 regular. */
1448 /**
1449 * @}
1450 */
1451
1452 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1453 * @{
1454 */
1455 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable
1456 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1457 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS (ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks
1458 in the sequence */
1459 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1) /*!< ADC group injected sequencer enable with 3 ranks
1460 in the sequence */
1461 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 \
1462 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks
1463 in the sequence */
1464 /**
1465 * @}
1466 */
1467
1468 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1469 * @{
1470 */
1471 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode
1472 disable */
1473 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode
1474 enable with sequence interruption every rank */
1475 /**
1476 * @}
1477 */
1478
1479 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1480 * @{
1481 */
1482 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \
1483 | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer
1484 rank 1 */
1485 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \
1486 | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer
1487 rank 2 */
1488 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \
1489 | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer
1490 rank 3 */
1491 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \
1492 | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer
1493 rank 4 */
1494 /**
1495 * @}
1496 */
1497
1498 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1499 * @{
1500 */
1501 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
1502 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
1503 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_1) /*!< Sampling time 6.5 ADC clock cycles */
1504 #define LL_ADC_SAMPLINGTIME_11CYCLES_5 (ADC_SMPR2_SMP10_1 \
1505 | ADC_SMPR2_SMP10_0) /*!< Sampling time 11.5 ADC clock cycles */
1506 #define LL_ADC_SAMPLINGTIME_23CYCLES_5 (ADC_SMPR2_SMP10_2) /*!< Sampling time 23.5 ADC clock cycles */
1507 #define LL_ADC_SAMPLINGTIME_46CYCLES_5 (ADC_SMPR2_SMP10_2 \
1508 | ADC_SMPR2_SMP10_0) /*!< Sampling time 46.5 ADC clock cycles */
1509 #define LL_ADC_SAMPLINGTIME_246CYCLES_5 (ADC_SMPR2_SMP10_2 \
1510 | ADC_SMPR2_SMP10_1) /*!< Sampling time 246.5 ADC clock cycles */
1511 #define LL_ADC_SAMPLINGTIME_1499CYCLES_5 (ADC_SMPR2_SMP10_2 \
1512 | ADC_SMPR2_SMP10_1 \
1513 | ADC_SMPR2_SMP10_0) /*!< Sampling time 1499.5 ADC clock cycles */
1514 /**
1515 * @}
1516 */
1517
1518 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1519 * @{
1520 */
1521
1522 #define LL_ADC_SINGLE_ENDED (ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to
1523 single ended (literal also used to set calibration mode) */
1524 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to
1525 differential (literal also used to set calibration mode) */
1526 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED \
1527 | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single
1528 ended and differential (literal used only to set calibration factors) */
1529 /**
1530 * @}
1531 */
1532
1533 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1534 * @{
1535 */
1536 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
1537 | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1538 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
1539 | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1540 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
1541 | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1542 /**
1543 * @}
1544 */
1545
1546 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1547 * @{
1548 */
1549 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
1550 disabled */
1551 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
1552 | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring
1553 of all channels, converted by group regular only */
1554 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1555 | ADC_CFGR1_JAWD1EN) /*!< ADC analog watchdog monitoring
1556 of all channels, converted by group injected only */
1557 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1558 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring
1559 of all channels, converted by either group regular or injected */
1560 #define LL_ADC_AWD_CHANNEL_0_REG (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD \
1561 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1562 of ADC channel ADCx_IN0, converted by group regular only */
1563 #define LL_ADC_AWD_CHANNEL_0_INJ (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD \
1564 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1565 of ADC channel ADCx_IN0, converted by group injected only */
1566 #define LL_ADC_AWD_CHANNEL_0_REG_INJ (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD \
1567 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1568 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1569 of ADC channel ADCx_IN0, converted by either group regular or injected */
1570 #define LL_ADC_AWD_CHANNEL_1_REG (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD \
1571 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1572 of ADC channel ADCx_IN1, converted by group regular only */
1573 #define LL_ADC_AWD_CHANNEL_1_INJ (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD \
1574 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1575 of ADC channel ADCx_IN1, converted by group injected only */
1576 #define LL_ADC_AWD_CHANNEL_1_REG_INJ (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD \
1577 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1578 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1579 of ADC channel ADCx_IN1, converted by either group regular or injected */
1580 #define LL_ADC_AWD_CHANNEL_2_REG (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD \
1581 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1582 of ADC channel ADCx_IN2, converted by group regular only */
1583 #define LL_ADC_AWD_CHANNEL_2_INJ (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD \
1584 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1585 of ADC channel ADCx_IN2, converted by group injected only */
1586 #define LL_ADC_AWD_CHANNEL_2_REG_INJ (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD \
1587 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1588 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1589 of ADC channel ADCx_IN2, converted by either group regular or injected */
1590 #define LL_ADC_AWD_CHANNEL_3_REG (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD \
1591 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1592 of ADC channel ADCx_IN3, converted by group regular only */
1593 #define LL_ADC_AWD_CHANNEL_3_INJ (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD \
1594 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1595 of ADC channel ADCx_IN3, converted by group injected only */
1596 #define LL_ADC_AWD_CHANNEL_3_REG_INJ (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD \
1597 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1598 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1599 of ADC channel ADCx_IN3, converted by either group regular or injected */
1600 #define LL_ADC_AWD_CHANNEL_4_REG (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD \
1601 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1602 of ADC channel ADCx_IN4, converted by group regular only */
1603 #define LL_ADC_AWD_CHANNEL_4_INJ (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD \
1604 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1605 of ADC channel ADCx_IN4, converted by group injected only */
1606 #define LL_ADC_AWD_CHANNEL_4_REG_INJ (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD \
1607 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1608 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1609 of ADC channel ADCx_IN4, converted by either group regular or injected */
1610 #define LL_ADC_AWD_CHANNEL_5_REG (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD \
1611 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1612 of ADC channel ADCx_IN5, converted by group regular only */
1613 #define LL_ADC_AWD_CHANNEL_5_INJ (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD \
1614 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1615 of ADC channel ADCx_IN5, converted by group injected only */
1616 #define LL_ADC_AWD_CHANNEL_5_REG_INJ (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD \
1617 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1618 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1619 of ADC channel ADCx_IN5, converted by either group regular or injected */
1620 #define LL_ADC_AWD_CHANNEL_6_REG (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD \
1621 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1622 of ADC channel ADCx_IN6, converted by group regular only */
1623 #define LL_ADC_AWD_CHANNEL_6_INJ (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD \
1624 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1625 of ADC channel ADCx_IN6, converted by group injected only */
1626 #define LL_ADC_AWD_CHANNEL_6_REG_INJ (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD \
1627 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1628 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1629 of ADC channel ADCx_IN6, converted by either group regular or injected */
1630 #define LL_ADC_AWD_CHANNEL_7_REG (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD \
1631 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1632 of ADC channel ADCx_IN7, converted by group regular only */
1633 #define LL_ADC_AWD_CHANNEL_7_INJ (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD \
1634 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1635 of ADC channel ADCx_IN7, converted by group injected only */
1636 #define LL_ADC_AWD_CHANNEL_7_REG_INJ (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD \
1637 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1638 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1639 of ADC channel ADCx_IN7, converted by either group regular or injected */
1640 #define LL_ADC_AWD_CHANNEL_8_REG (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD \
1641 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1642 of ADC channel ADCx_IN8, converted by group regular only */
1643 #define LL_ADC_AWD_CHANNEL_8_INJ (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD \
1644 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1645 of ADC channel ADCx_IN8, converted by group injected only */
1646 #define LL_ADC_AWD_CHANNEL_8_REG_INJ (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD \
1647 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1648 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1649 of ADC channel ADCx_IN8, converted by either group regular or injected */
1650 #define LL_ADC_AWD_CHANNEL_9_REG (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD \
1651 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1652 of ADC channel ADCx_IN9, converted by group regular only */
1653 #define LL_ADC_AWD_CHANNEL_9_INJ (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD \
1654 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1655 of ADC channel ADCx_IN9, converted by group injected only */
1656 #define LL_ADC_AWD_CHANNEL_9_REG_INJ (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD \
1657 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1658 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1659 of ADC channel ADCx_IN9, converted by either group regular or injected */
1660 #define LL_ADC_AWD_CHANNEL_10_REG (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD \
1661 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1662 of ADC channel ADCx_IN10, converted by group regular only */
1663 #define LL_ADC_AWD_CHANNEL_10_INJ (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD \
1664 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1665 of ADC channel ADCx_IN10, converted by group injected only */
1666 #define LL_ADC_AWD_CHANNEL_10_REG_INJ (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD\
1667 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1668 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1669 of ADC channel ADCx_IN10, converted by either group regular or injected */
1670 #define LL_ADC_AWD_CHANNEL_11_REG (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD \
1671 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1672 of ADC channel ADCx_IN11, converted by group regular only */
1673 #define LL_ADC_AWD_CHANNEL_11_INJ (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD \
1674 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1675 of ADC channel ADCx_IN11, converted by group injected only */
1676 #define LL_ADC_AWD_CHANNEL_11_REG_INJ (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD \
1677 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1678 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1679 of ADC channel ADCx_IN11, converted by either group regular or injected */
1680 #define LL_ADC_AWD_CHANNEL_12_REG (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD \
1681 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1682 of ADC channel ADCx_IN12, converted by group regular only */
1683 #define LL_ADC_AWD_CHANNEL_12_INJ (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD \
1684 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1685 of ADC channel ADCx_IN12, converted by group injected only */
1686 #define LL_ADC_AWD_CHANNEL_12_REG_INJ (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD \
1687 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1688 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1689 of ADC channel ADCx_IN12, converted by either group regular or injected */
1690 #define LL_ADC_AWD_CHANNEL_13_REG (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD \
1691 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1692 of ADC channel ADCx_IN13, converted by group regular only */
1693 #define LL_ADC_AWD_CHANNEL_13_INJ (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD \
1694 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1695 of ADC channel ADCx_IN13, converted by group injected only */
1696 #define LL_ADC_AWD_CHANNEL_13_REG_INJ (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD \
1697 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1698 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1699 of ADC channel ADCx_IN13, converted by either group regular or injected */
1700 #define LL_ADC_AWD_CHANNEL_14_REG (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD \
1701 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1702 of ADC channel ADCx_IN14, converted by group regular only */
1703 #define LL_ADC_AWD_CHANNEL_14_INJ (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD \
1704 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1705 of ADC channel ADCx_IN14, converted by group only */
1706 #define LL_ADC_AWD_CHANNEL_14_REG_INJ (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD \
1707 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1708 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1709 of ADC channel ADCx_IN14, converted by either group regular or injected */
1710 #define LL_ADC_AWD_CHANNEL_15_REG (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD \
1711 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1712 monitoring of ADC channel ADCx_IN15, converted by group regular only */
1713 #define LL_ADC_AWD_CHANNEL_15_INJ (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD \
1714 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1715 of ADC channel ADCx_IN15, converted by group injected only */
1716 #define LL_ADC_AWD_CHANNEL_15_REG_INJ (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD \
1717 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1718 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1719 of ADC channel ADCx_IN15, converted by either group
1720 regular or injected */
1721 #define LL_ADC_AWD_CHANNEL_16_REG (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD \
1722 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1723 of ADC channel ADCx_IN16, converted by group regular only */
1724 #define LL_ADC_AWD_CHANNEL_16_INJ (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD \
1725 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1726 of ADC channel ADCx_IN16, converted by group injected only */
1727 #define LL_ADC_AWD_CHANNEL_16_REG_INJ (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD \
1728 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1729 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1730 of ADC channel ADCx_IN16, converted by either group regular or injected */
1731 #define LL_ADC_AWD_CHANNEL_17_REG (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD \
1732 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1733 of ADC channel ADCx_IN17, converted by group regular only */
1734 #define LL_ADC_AWD_CHANNEL_17_INJ (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD \
1735 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1736 of ADC channel ADCx_IN17, converted by group injected only */
1737 #define LL_ADC_AWD_CHANNEL_17_REG_INJ (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD \
1738 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1739 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1740 of ADC channel ADCx_IN17, converted by either group regular or injected */
1741 #define LL_ADC_AWD_CHANNEL_18_REG (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD \
1742 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1743 of ADC channel ADCx_IN18, converted by group regular only */
1744 #define LL_ADC_AWD_CHANNEL_18_INJ (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD \
1745 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1746 of ADC channel ADCx_IN18, converted by group injected only */
1747 #define LL_ADC_AWD_CHANNEL_18_REG_INJ (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD \
1748 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1749 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1750 of ADC channel ADCx_IN18, converted by either group regular or injected */
1751 #define LL_ADC_AWD_CHANNEL_19_REG (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_BITFIELD \
1752 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1753 of ADC channel ADCx_IN19, converted by group regular only */
1754 #define LL_ADC_AWD_CHANNEL_19_INJ (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_BITFIELD \
1755 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1756 of ADC channel ADCx_IN19, converted by group injected only */
1757 #define LL_ADC_AWD_CHANNEL_19_REG_INJ (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_BITFIELD \
1758 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
1759 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1760 of ADC channel ADCx_IN19, converted by either group regular or injected */
1761 #define LL_ADC_AWD_CH_VREFINT_REG LL_ADC_AWD_CHANNEL_17_REG /*!< ADC analog watchdog monitoring
1762 of ADC internal channel connected to VrefInt: Internal voltage reference,
1763 converted by group regular only */
1764 #define LL_ADC_AWD_CH_VREFINT_INJ LL_ADC_AWD_CHANNEL_17_INJ /*!< ADC analog watchdog monitoring
1765 of ADC internal channel connected to VrefInt: Internal voltage reference,
1766 converted by group injected only */
1767 #define LL_ADC_AWD_CH_VREFINT_REG_INJ LL_ADC_AWD_CHANNEL_17_REG_INJ /*!< ADC analog watchdog monitoring
1768 of ADC internal channel connected to VrefInt: Internal voltage reference,
1769 converted by either group regular or injected */
1770 #define LL_ADC_AWD_CH_VBAT_REG LL_ADC_AWD_CHANNEL_16_REG /*!< ADC analog watchdog monitoring
1771 of ADC internal channel connected to Vbat/4: Vbat voltage through
1772 a divider ladder of factor 1/4 to have Vbat always below Vdda,
1773 converted by group regular only */
1774 #define LL_ADC_AWD_CH_VBAT_INJ LL_ADC_AWD_CHANNEL_16_INJ /*!< ADC analog watchdog monitoring
1775 of ADC internal channel connected to Vbat/4: Vbat voltage through
1776 a divider ladder of factor 1/4 to have Vbat always below Vdda,
1777 converted by group injected only */
1778 #define LL_ADC_AWD_CH_VBAT_REG_INJ LL_ADC_AWD_CHANNEL_16_REG_INJ /*!< ADC analog watchdog monitoring
1779 of ADC internal channel connected to Vbat/4: Vbat voltage through
1780 a divider ladder of factor 1/4 to have Vbat always below Vdda */
1781 #define LL_ADC_AWD_CH_VDDCORE_REG LL_ADC_AWD_CHANNEL_17_REG /*!< ADC analog watchdog monitoring
1782 of ADC internal channel connected to VddCore,
1783 converted by group regular only */
1784 #define LL_ADC_AWD_CH_VDDCORE_INJ LL_ADC_AWD_CHANNEL_17_INJ /*!< ADC analog watchdog monitoring
1785 of ADC internal channel connected to VddCore,
1786 converted by group injected only */
1787 #define LL_ADC_AWD_CH_VDDCORE_REG_INJ LL_ADC_AWD_CHANNEL_17_REG_INJ /*!< ADC analog watchdog monitoring
1788 of ADC internal channel connected to VddCore,
1789 converted by either group regular or injected */
1790 /**
1791 * @}
1792 */
1793
1794 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1795 * @{
1796 */
1797 #define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */
1798 #define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */
1799 /**
1800 * @}
1801 */
1802
1803 /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
1804 * @{
1805 */
1806 #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog filtering disabled:
1807 one out-of-window sample is needed to raise flag or interrupt */
1808 #define LL_ADC_AWD_FILTERING_2SAMPLES (ADC_AWD1HTR_AWDFILT_0) /*!< ADC analog watchdog filtering enabled: 2
1809 out-of-window samples are needed to raise flag or interrupt */
1810 #define LL_ADC_AWD_FILTERING_3SAMPLES (ADC_AWD1HTR_AWDFILT_1) /*!< ADC analog watchdog filtering enabled: 3
1811 out-of-window samples are needed to raise flag or interrupt */
1812 #define LL_ADC_AWD_FILTERING_4SAMPLES (ADC_AWD1HTR_AWDFILT_1 \
1813 | ADC_AWD1HTR_AWDFILT_0) /*!< ADC analog watchdog filtering enabled: 4
1814 out-of-window samples are needed to raise flag or interrupt */
1815 #define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_AWD1HTR_AWDFILT_2) /*!< ADC analog watchdog filtering enabled: 5
1816 out-of-window samples are needed to raise flag or interrupt */
1817 #define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_AWD1HTR_AWDFILT_2 \
1818 | ADC_AWD1HTR_AWDFILT_0) /*!< ADC analog watchdog filtering enabled: 6
1819 out-of-window samples are needed to raise flag or interrupt */
1820 #define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_AWD1HTR_AWDFILT_2 \
1821 | ADC_AWD1HTR_AWDFILT_1) /*!< ADC analog watchdog filtering enabled: 7
1822 out-of-window samples are needed to raise flag or interrupt */
1823 #define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_AWD1HTR_AWDFILT_2 \
1824 | ADC_AWD1HTR_AWDFILT_1 \
1825 | ADC_AWD1HTR_AWDFILT_0) /*!< ADC analog watchdog filtering enabled: 8
1826 out-of-window samples are needed to raise flag or interrupt */
1827 /**
1828 * @}
1829 */
1830
1831 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1832 * @{
1833 */
1834 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1835 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1836 ADC group regular. If group injected interrupts group regular:
1837 when ADC group injected is triggered, the oversampling on ADC group regular
1838 is temporary stopped and continued afterwards. */
1839 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1840 ADC group regular. If group injected interrupts group regular:
1841 when ADC group injected is triggered, the oversampling on ADC group regular
1842 is resumed from start (oversampler buffer reset). */
1843 #define LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of
1844 ADC group injected. */
1845 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1846 both ADC groups regular and injected. If group injected interrupting group
1847 regular: when ADC group injected is triggered, the oversampling on ADC group
1848 regular is resumed from start (oversampler buffer reset). */
1849 /**
1850 * @}
1851 */
1852
1853 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1854 * @{
1855 */
1856 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
1857 (all conversions of oversampling ratio are done from 1 trigger) */
1858 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous
1859 mode (each conversion of oversampling ratio needs a trigger) */
1860 /**
1861 * @}
1862 */
1863
1864 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
1865 * @{
1866 */
1867 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
1868 (sum of the ADC conversions data is not divided to result as oversampling
1869 conversion data) */
1870 #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
1871 (sum of the ADC conversions data (after OVS ratio) is divided by 2
1872 to result as oversampling conversion data) */
1873 #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
1874 (sum of the ADC conversions data (after OVS ratio) is divided by 4
1875 to result as oversampling conversion data) */
1876 #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
1877 (sum of the ADC conversions data (after OVS ratio) is divided by 8
1878 to result as oversampling conversion data) */
1879 #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
1880 (sum of the ADC conversions data (after OVS ratio) is divided by 16
1881 to result as oversampling conversion data) */
1882 #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
1883 (sum of the ADC conversions data (after OVS ratio) is divided by 32
1884 to result as oversampling conversion data) */
1885 #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
1886 (sum of the ADC conversions data (after OVS ratio) is divided by 64
1887 to result as oversampling conversion data) */
1888 #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
1889 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
1890 (sum of the ADC conversions data (after OVS ratio) is divided by 128
1891 to result as oversampling conversion data) */
1892 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
1893 (sum of the ADC conversions data (after OVS ratio) is divided by 256
1894 to result as oversampling conversion data) */
1895 #define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 8
1896 (sum of the ADC conversions data (after OVS ratio) is divided by 512
1897 to result as oversampling conversion data) */
1898 #define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 8
1899 (sum of the ADC conversions data (after OVS ratio) is divided by 1024
1900 to result as oversampling conversion data) */
1901 /**
1902 * @}
1903 */
1904
1905 #if defined(ADC_MULTIMODE_SUPPORT)
1906 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1907 * @{
1908 */
1909 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC
1910 independent mode) */
1911 #define LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular
1912 simultaneous */
1913 #define LL_ADC_MULTI_DUAL_REG_INTERL (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \
1914 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1915 regular interleaved */
1916 #define LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
1917 simultaneous */
1918 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
1919 alternate trigger. Works only with external triggers (not SW start) */
1920 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1921 regular simultaneous + group injected simultaneous */
1922 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group
1923 regular simultaneous + group injected alternate trigger */
1924 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1925 regular interleaved + group injected simultaneous */
1926 /**
1927 * @}
1928 */
1929
1930 /** @defgroup ADC_LL_EC_MULTI_DATA_FORMAT Multimode - Data format
1931 * @{
1932 */
1933 #define LL_ADC_MULTI_REG_DATA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular
1934 data format: conversion data in data register of each ADC instance.
1935 If ADC data transfer by DMA is used: each ADC uses its own DMA channel,
1936 with its individual DMA transfer settings. */
1937 #define LL_ADC_MULTI_REG_DATA_COMMON_32B (ADC_CCR_DAMDF_1) /*!< ADC multimode group regular
1938 data format: conversion data in two ADC common instance data registers
1939 (CDR, CDR2) with packing option on 32 bit. In register CDR,
1940 data packing on 32 bit: ADC master and slave data are concatenated
1941 (data master in [15; 0], data slave in [31; 16]), therefore data width
1942 must be lower than 16 bit (even with ADC resolution 12 bit,
1943 higher width reachable by post processing: oversampling, offset, ...).
1944 In register CDR2, data of master and slave are alternatively set in full
1945 register width 32 bit, therefore no constraint on data width.
1946 In case of usage with DMA, CDR generate ones transfer request
1947 and CDR2 two transfer requests per conversion. */
1948 #define LL_ADC_MULTI_REG_DATA_COMMON_16B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular
1949 data format: conversion data in two ADC common instance data registers
1950 (CDR, CDR2) with packing option on 16 bit. In register CDR,
1951 data packing on 16 bit: ADC master and slave data are concatenated
1952 (data master in [7; 0], data slave in [15; 8]), therefore data width
1953 must be lower than 8 bit (even with ADC resolution 8 bit,
1954 higher width reachable by post processing: oversampling, offset, ...).
1955 In register CDR2, data of master and slave are alternatively set in full
1956 register width 32 bit, therefore no constraint on data width.
1957 In case of usage with DMA, CDR generate ones transfer request
1958 and CDR2 two transfer requests per conversion. */
1959
1960 /* Legacy literals */
1961 #define LL_ADC_MULTI_REG_DMA_EACH_ADC LL_ADC_MULTI_REG_DATA_EACH_ADC
1962 #define LL_ADC_MULTI_REG_DMA_RES_32B LL_ADC_MULTI_REG_DATA_COMMON_32B
1963 #define LL_ADC_MULTI_REG_DMA_RES_16B LL_ADC_MULTI_REG_DATA_COMMON_16B
1964 /**
1965 * @}
1966 */
1967
1968 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1969 * @{
1970 */
1971 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode interleaved delay
1972 between two sampling phases: 1 ADC clock cycle */
1973 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0) /*!< ADC multimode interleaved delay
1974 between two sampling phases: 2 ADC clock cycles */
1975 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1) /*!< ADC multimode interleaved delay
1976 between two sampling phases: 3 ADC clock cycles */
1977 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode interleaved delay
1978 between two sampling phases: 4 ADC clock cycles */
1979 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2) /*!< ADC multimode interleaved delay
1980 between two sampling phases: 5 ADC clock cycles */
1981 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode interleaved delay
1982 between two sampling phases: 6 ADC clock cycles */
1983 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode interleaved delay
1984 between two sampling phases: 7 ADC clock cycles */
1985 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \
1986 | ADC_CCR_DELAY_0) /*!< ADC multimode interleaved delay
1987 between two sampling phases: 8 ADC clock cycles */
1988 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3) /*!< ADC multimode interleaved delay
1989 between two sampling phases: 9 ADC clock cycles */
1990 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode interleaved delay
1991 between two sampling phases: 10 ADC clock cycles */
1992 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode interleaved delay
1993 between two sampling phases: 11 ADC clock cycles */
1994 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \
1995 | ADC_CCR_DELAY_0) /*!< ADC multimode interleaved delay
1996 between two sampling phases: 12 ADC clock cycles */
1997 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2) /*!< ADC multimode interleaved delay
1998 between two sampling phases: 13 ADC clock cycles */
1999 /**
2000 * @}
2001 */
2002
2003 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
2004 * @{
2005 */
2006 #define LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
2007 instances: ADC master */
2008 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC
2009 instances: ADC slave */
2010 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \
2011 | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
2012 instances: both ADC master and ADC slave */
2013 /**
2014 * @}
2015 */
2016
2017 #endif /* ADC_MULTIMODE_SUPPORT */
2018
2019 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
2020 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
2021 * not timeout values.
2022 * For details on delays values, refer to descriptions in source code
2023 * above each literal definition.
2024 * @{
2025 */
2026
2027 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
2028 /* not timeout values. */
2029 /* Timeout values for ADC operations are dependent to device clock */
2030 /* configuration (system clock versus ADC clock), */
2031 /* and therefore must be defined in user application. */
2032 /* Indications for estimation of ADC timeout delays, for this */
2033 /* STM32 series: */
2034 /* - ADC calibration time: maximum delay is 16384/fADC. */
2035 /* (refer to device datasheet, parameter "tCAL") */
2036 /* - ADC enable time: maximum delay is 1 conversion cycle. */
2037 /* (refer to device datasheet, parameter "tSTAB") */
2038 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
2039 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
2040 /* cycles */
2041 /* - ADC conversion time: duration depending on ADC clock and ADC */
2042 /* configuration. */
2043 /* (refer to device reference manual, section "Timing") */
2044
2045 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
2046 /* Delay set to maximum value (refer to device datasheet, */
2047 /* parameter "tADCVREG_STUP"). */
2048 /* Unit: us */
2049 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage
2050 regulator start-up time) */
2051
2052 /* Delay for internal voltage reference stabilization time. */
2053 /* Delay set to maximum value (refer to device datasheet, */
2054 /* parameter "tstart_vrefint"). */
2055 /* Unit: us */
2056 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
2057 time */
2058
2059 /* Delay required between ADC end of calibration and ADC enable. */
2060 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
2061 /* are required between ADC end of calibration and ADC enable. */
2062 /* Wait time can be computed in user application by waiting for the */
2063 /* equivalent number of CPU cycles, by taking into account */
2064 /* ratio of CPU clock versus ADC clock prescalers. */
2065 /* Unit: ADC clock cycles. */
2066 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration
2067 and ADC enable */
2068
2069 /**
2070 * @}
2071 */
2072
2073 /**
2074 * @}
2075 */
2076
2077
2078 /* Exported macro ------------------------------------------------------------*/
2079 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
2080 * @{
2081 */
2082
2083 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
2084 * @{
2085 */
2086
2087 /**
2088 * @brief Write a value in ADC register
2089 * @param __INSTANCE__ ADC Instance
2090 * @param __REG__ Register to be written
2091 * @param __VALUE__ Value to be written in the register
2092 * @retval None
2093 */
2094 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2095
2096 /**
2097 * @brief Read a value in ADC register
2098 * @param __INSTANCE__ ADC Instance
2099 * @param __REG__ Register to be read
2100 * @retval Register value
2101 */
2102 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2103 /**
2104 * @}
2105 */
2106
2107 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
2108 * @{
2109 */
2110
2111 /**
2112 * @brief Helper macro to get ADC channel number in decimal format
2113 * from literals LL_ADC_CHANNEL_x.
2114 * @note Example:
2115 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
2116 * will return decimal number "4".
2117 * @note The input can be a value from functions where a channel
2118 * number is returned, either defined with number
2119 * or with bitfield (only one bit must be set).
2120 * @param __CHANNEL__ This parameter can be one of the following values:
2121 * @arg @ref LL_ADC_CHANNEL_0
2122 * @arg @ref LL_ADC_CHANNEL_1
2123 * @arg @ref LL_ADC_CHANNEL_2
2124 * @arg @ref LL_ADC_CHANNEL_3
2125 * @arg @ref LL_ADC_CHANNEL_4
2126 * @arg @ref LL_ADC_CHANNEL_5
2127 * @arg @ref LL_ADC_CHANNEL_6
2128 * @arg @ref LL_ADC_CHANNEL_7
2129 * @arg @ref LL_ADC_CHANNEL_8
2130 * @arg @ref LL_ADC_CHANNEL_9
2131 * @arg @ref LL_ADC_CHANNEL_10
2132 * @arg @ref LL_ADC_CHANNEL_11
2133 * @arg @ref LL_ADC_CHANNEL_12
2134 * @arg @ref LL_ADC_CHANNEL_13
2135 * @arg @ref LL_ADC_CHANNEL_14
2136 * @arg @ref LL_ADC_CHANNEL_15
2137 * @arg @ref LL_ADC_CHANNEL_16
2138 * @arg @ref LL_ADC_CHANNEL_17
2139 * @arg @ref LL_ADC_CHANNEL_18
2140 * @arg @ref LL_ADC_CHANNEL_19
2141 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2142 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
2143 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
2144 *
2145 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
2146 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
2147 * @retval Value between Min_Data=0 and Max_Data=18
2148 */
2149 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) ((__CHANNEL__) & ADC_CHANNEL_NUMBER_MASK)
2150
2151
2152 /**
2153 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
2154 * from number in decimal format.
2155 * @note Example:
2156 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
2157 * will return a data equivalent to "LL_ADC_CHANNEL_4".
2158 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
2159 * @retval Returned value can be one of the following values:
2160 * @arg @ref LL_ADC_CHANNEL_0
2161 * @arg @ref LL_ADC_CHANNEL_1
2162 * @arg @ref LL_ADC_CHANNEL_2
2163 * @arg @ref LL_ADC_CHANNEL_3
2164 * @arg @ref LL_ADC_CHANNEL_4
2165 * @arg @ref LL_ADC_CHANNEL_5
2166 * @arg @ref LL_ADC_CHANNEL_6
2167 * @arg @ref LL_ADC_CHANNEL_7
2168 * @arg @ref LL_ADC_CHANNEL_8
2169 * @arg @ref LL_ADC_CHANNEL_9
2170 * @arg @ref LL_ADC_CHANNEL_10
2171 * @arg @ref LL_ADC_CHANNEL_11
2172 * @arg @ref LL_ADC_CHANNEL_12
2173 * @arg @ref LL_ADC_CHANNEL_13
2174 * @arg @ref LL_ADC_CHANNEL_14
2175 * @arg @ref LL_ADC_CHANNEL_15
2176 * @arg @ref LL_ADC_CHANNEL_16
2177 * @arg @ref LL_ADC_CHANNEL_17
2178 * @arg @ref LL_ADC_CHANNEL_18
2179 * @arg @ref LL_ADC_CHANNEL_19
2180 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
2181 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(3)
2182 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(3)
2183 *
2184 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
2185 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
2186 * (3) For ADC channel read back from ADC register,
2187 * comparison with internal channel parameter to be done
2188 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2189 */
2190 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) (__DECIMAL_NB__)
2191
2192 /**
2193 * @brief Helper macro to determine whether the selected channel
2194 * corresponds to literal definitions of driver.
2195 * @note The different literal definitions of ADC channels are:
2196 * - ADC internal channel:
2197 * LL_ADC_CHANNEL_VREFINT, ...
2198 * - ADC external channel (channel connected to a GPIO pin):
2199 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
2200 * @note The channel parameter must be a value defined from literal
2201 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, ...),
2202 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
2203 * must not be a value from functions where a channel number is
2204 * returned from ADC registers,
2205 * because internal and external channels share the same channel
2206 * number in ADC registers. The differentiation is made only with
2207 * parameters definitions of driver.
2208 * @param __CHANNEL__ This parameter can be one of the following values:
2209 * @arg @ref LL_ADC_CHANNEL_0
2210 * @arg @ref LL_ADC_CHANNEL_1
2211 * @arg @ref LL_ADC_CHANNEL_2
2212 * @arg @ref LL_ADC_CHANNEL_3
2213 * @arg @ref LL_ADC_CHANNEL_4
2214 * @arg @ref LL_ADC_CHANNEL_5
2215 * @arg @ref LL_ADC_CHANNEL_6
2216 * @arg @ref LL_ADC_CHANNEL_7
2217 * @arg @ref LL_ADC_CHANNEL_8
2218 * @arg @ref LL_ADC_CHANNEL_9
2219 * @arg @ref LL_ADC_CHANNEL_10
2220 * @arg @ref LL_ADC_CHANNEL_11
2221 * @arg @ref LL_ADC_CHANNEL_12
2222 * @arg @ref LL_ADC_CHANNEL_13
2223 * @arg @ref LL_ADC_CHANNEL_14
2224 * @arg @ref LL_ADC_CHANNEL_15
2225 * @arg @ref LL_ADC_CHANNEL_16
2226 * @arg @ref LL_ADC_CHANNEL_17
2227 * @arg @ref LL_ADC_CHANNEL_18
2228 * @arg @ref LL_ADC_CHANNEL_19
2229 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2230 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
2231 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
2232 *
2233 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
2234 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
2235 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
2236 * (channel connected to a GPIO pin).
2237 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
2238 */
2239 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_INTERNAL_MASK) != 0UL)
2240 /**
2241 * @brief Helper macro to convert a channel defined from parameter
2242 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, ...),
2243 * to its equivalent parameter definition of a ADC external channel
2244 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
2245 * @note The channel parameter can be, additionally to a value
2246 * defined from parameter definition of a ADC internal channel
2247 * (LL_ADC_CHANNEL_VREFINT, ...),
2248 * a value defined from parameter definition of
2249 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2250 * or a value from functions where a channel number is returned
2251 * from ADC registers.
2252 * @param __CHANNEL__ This parameter can be one of the following values:
2253 * @arg @ref LL_ADC_CHANNEL_0
2254 * @arg @ref LL_ADC_CHANNEL_1
2255 * @arg @ref LL_ADC_CHANNEL_2
2256 * @arg @ref LL_ADC_CHANNEL_3
2257 * @arg @ref LL_ADC_CHANNEL_4
2258 * @arg @ref LL_ADC_CHANNEL_5
2259 * @arg @ref LL_ADC_CHANNEL_6
2260 * @arg @ref LL_ADC_CHANNEL_7
2261 * @arg @ref LL_ADC_CHANNEL_8
2262 * @arg @ref LL_ADC_CHANNEL_9
2263 * @arg @ref LL_ADC_CHANNEL_10
2264 * @arg @ref LL_ADC_CHANNEL_11
2265 * @arg @ref LL_ADC_CHANNEL_12
2266 * @arg @ref LL_ADC_CHANNEL_13
2267 * @arg @ref LL_ADC_CHANNEL_14
2268 * @arg @ref LL_ADC_CHANNEL_15
2269 * @arg @ref LL_ADC_CHANNEL_16
2270 * @arg @ref LL_ADC_CHANNEL_17
2271 * @arg @ref LL_ADC_CHANNEL_18
2272 * @arg @ref LL_ADC_CHANNEL_19
2273 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2274 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
2275 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
2276 *
2277 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
2278 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
2279 * @retval Returned value can be one of the following values:
2280 * @arg @ref LL_ADC_CHANNEL_0
2281 * @arg @ref LL_ADC_CHANNEL_1
2282 * @arg @ref LL_ADC_CHANNEL_2
2283 * @arg @ref LL_ADC_CHANNEL_3
2284 * @arg @ref LL_ADC_CHANNEL_4
2285 * @arg @ref LL_ADC_CHANNEL_5
2286 * @arg @ref LL_ADC_CHANNEL_6
2287 * @arg @ref LL_ADC_CHANNEL_7
2288 * @arg @ref LL_ADC_CHANNEL_8
2289 * @arg @ref LL_ADC_CHANNEL_9
2290 * @arg @ref LL_ADC_CHANNEL_10
2291 * @arg @ref LL_ADC_CHANNEL_11
2292 * @arg @ref LL_ADC_CHANNEL_12
2293 * @arg @ref LL_ADC_CHANNEL_13
2294 * @arg @ref LL_ADC_CHANNEL_14
2295 * @arg @ref LL_ADC_CHANNEL_15
2296 * @arg @ref LL_ADC_CHANNEL_16
2297 * @arg @ref LL_ADC_CHANNEL_17
2298 * @arg @ref LL_ADC_CHANNEL_18
2299 * @arg @ref LL_ADC_CHANNEL_19
2300 */
2301 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ADC_CHANNEL_NUMBER_MASK)
2302
2303 /**
2304 * @brief Helper macro to determine whether the internal channel
2305 * selected is available on the ADC instance selected.
2306 * @note The channel parameter must be a value defined from parameter
2307 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, ...),
2308 * must not be a value defined from parameter definition of
2309 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2310 * or a value from functions where a channel number is
2311 * returned from ADC registers,
2312 * because internal and external channels share the same channel
2313 * number in ADC registers. The differentiation is made only with
2314 * parameters definitions of driver.
2315 * @param __ADC_INSTANCE__ ADC instance
2316 * @param __CHANNEL__ This parameter can be one of the following values:
2317 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2318 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
2319 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
2320 *
2321 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
2322 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.
2323 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
2324 * Value "1" if the internal channel selected is available on the ADC instance selected.
2325 */
2326 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2327 ((((__ADC_INSTANCE__) == ADC1) \
2328 &&(((__CHANNEL__ & ADC_CHANNEL_INTERNAL_ADC1) == ADC_CHANNEL_INTERNAL_ADC1)) \
2329 ) \
2330 || \
2331 (((__ADC_INSTANCE__) == ADC2) \
2332 &&(((__CHANNEL__ & ADC_CHANNEL_INTERNAL_ADC2) == ADC_CHANNEL_INTERNAL_ADC2)) \
2333 ) \
2334 )
2335
2336 /**
2337 * @brief Helper macro to determine the selected channel corresponding
2338 * negative input on the ADC instance selected.
2339 * @param __ADC_INSTANCE__ ADC instance
2340 * @param __CHANNEL__ This parameter can be one of the following values:
2341 * @arg @ref LL_ADC_CHANNEL_0
2342 * @arg @ref LL_ADC_CHANNEL_1
2343 * @arg @ref LL_ADC_CHANNEL_2
2344 * @arg @ref LL_ADC_CHANNEL_3
2345 * @arg @ref LL_ADC_CHANNEL_4
2346 * @arg @ref LL_ADC_CHANNEL_5
2347 * @arg @ref LL_ADC_CHANNEL_6
2348 * @arg @ref LL_ADC_CHANNEL_7
2349 * @arg @ref LL_ADC_CHANNEL_8
2350 * @arg @ref LL_ADC_CHANNEL_9
2351 * @arg @ref LL_ADC_CHANNEL_10
2352 * @arg @ref LL_ADC_CHANNEL_11
2353 * @arg @ref LL_ADC_CHANNEL_12
2354 * @arg @ref LL_ADC_CHANNEL_13
2355 * @arg @ref LL_ADC_CHANNEL_14
2356 * @arg @ref LL_ADC_CHANNEL_15
2357 * @arg @ref LL_ADC_CHANNEL_16
2358 * @arg @ref LL_ADC_CHANNEL_17
2359 * @arg @ref LL_ADC_CHANNEL_18
2360 * @arg @ref LL_ADC_CHANNEL_19
2361 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2362 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
2363 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
2364 *
2365 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
2366 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
2367 * @retval Returned value can be one of the following values:
2368 * @arg @ref LL_ADC_CHANNEL_0
2369 * @arg @ref LL_ADC_CHANNEL_1
2370 * @arg @ref LL_ADC_CHANNEL_2
2371 * @arg @ref LL_ADC_CHANNEL_3
2372 * @arg @ref LL_ADC_CHANNEL_4
2373 * @arg @ref LL_ADC_CHANNEL_5
2374 * @arg @ref LL_ADC_CHANNEL_6
2375 * @arg @ref LL_ADC_CHANNEL_7
2376 * @arg @ref LL_ADC_CHANNEL_8
2377 * @arg @ref LL_ADC_CHANNEL_9
2378 * @arg @ref LL_ADC_CHANNEL_10
2379 * @arg @ref LL_ADC_CHANNEL_11
2380 * @arg @ref LL_ADC_CHANNEL_12
2381 * @arg @ref LL_ADC_CHANNEL_13
2382 * @arg @ref LL_ADC_CHANNEL_14
2383 * @arg @ref LL_ADC_CHANNEL_15
2384 * @arg @ref LL_ADC_CHANNEL_16
2385 * @arg @ref LL_ADC_CHANNEL_17
2386 * @arg @ref LL_ADC_CHANNEL_18
2387 * @arg @ref LL_ADC_CHANNEL_19
2388 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
2389 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(3)
2390 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(3)
2391 *
2392 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
2393 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
2394 * (3) For ADC channel read back from ADC register,
2395 * comparison with internal channel parameter to be done
2396 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2397 */
2398 #define __LL_ADC_CHANNEL_DIFF_NEG_INPUT(__ADC_INSTANCE__, __CHANNEL__) \
2399 __LL_ADC_DECIMAL_NB_TO_CHANNEL(ADC_CHANNEL_DIFF_LUT[__ADC_INSTANCE_INDEX(__ADC_INSTANCE__)][(uint8_t)(__CHANNEL__)]) \
2400
2401 /**
2402 * @brief Helper macro to define ADC analog watchdog parameter:
2403 * define a single channel to monitor with analog watchdog
2404 * from sequencer channel and groups definition.
2405 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2406 * Example:
2407 * LL_ADC_SetAnalogWDMonitChannels(
2408 * ADC1, LL_ADC_AWD1,
2409 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
2410 * @param __CHANNEL__ This parameter can be one of the following values:
2411 * @arg @ref LL_ADC_CHANNEL_0
2412 * @arg @ref LL_ADC_CHANNEL_1
2413 * @arg @ref LL_ADC_CHANNEL_2
2414 * @arg @ref LL_ADC_CHANNEL_3
2415 * @arg @ref LL_ADC_CHANNEL_4
2416 * @arg @ref LL_ADC_CHANNEL_5
2417 * @arg @ref LL_ADC_CHANNEL_6
2418 * @arg @ref LL_ADC_CHANNEL_7
2419 * @arg @ref LL_ADC_CHANNEL_8
2420 * @arg @ref LL_ADC_CHANNEL_9
2421 * @arg @ref LL_ADC_CHANNEL_10
2422 * @arg @ref LL_ADC_CHANNEL_11
2423 * @arg @ref LL_ADC_CHANNEL_12
2424 * @arg @ref LL_ADC_CHANNEL_13
2425 * @arg @ref LL_ADC_CHANNEL_14
2426 * @arg @ref LL_ADC_CHANNEL_15
2427 * @arg @ref LL_ADC_CHANNEL_16
2428 * @arg @ref LL_ADC_CHANNEL_17
2429 * @arg @ref LL_ADC_CHANNEL_18
2430 * @arg @ref LL_ADC_CHANNEL_19
2431 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
2432 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(3)
2433 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(3)
2434 *
2435 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
2436 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
2437 * (3) For ADC channel read back from ADC register,
2438 * comparison with internal channel parameter to be done
2439 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2440 * @param __GROUP__ This parameter can be one of the following values:
2441 * @arg @ref LL_ADC_GROUP_REGULAR
2442 * @arg @ref LL_ADC_GROUP_INJECTED
2443 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
2444 * @retval Returned value can be one of the following values:
2445 * @arg @ref LL_ADC_AWD_DISABLE
2446 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
2447 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
2448 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
2449 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
2450 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
2451 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
2452 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
2453 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
2454 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
2455 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
2456 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
2457 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
2458 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
2459 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
2460 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
2461 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
2462 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
2463 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
2464 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
2465 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
2466 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
2467 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
2468 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
2469 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
2470 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
2471 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
2472 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2473 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
2474 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
2475 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2476 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2477 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2478 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2479 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2480 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2481 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2482 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2483 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2484 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2485 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2486 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2487 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2488 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2489 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2490 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2491 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2492 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2493 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2494 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2495 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2496 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2497 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2498 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2499 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2500 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2501 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2502 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2503 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2504 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2505 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2506 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
2507 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
2508 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
2509 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
2510 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
2511 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
2512 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
2513 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
2514 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
2515 * @arg @ref LL_ADC_AWD_CH_VDDCORE_REG (0)(1)
2516 * @arg @ref LL_ADC_AWD_CH_VDDCORE_INJ (0)(1)
2517 * @arg @ref LL_ADC_AWD_CH_VDDCORE_REG_INJ (1)
2518 *
2519 * (0) On this STM32 series, parameter available only on analog watchdog instance: AWD1.\n
2520 * (1) On this STM32 series, parameter available only on ADC instance: ADC2, ADC3.
2521 */
2522 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2523 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2524 ? ((((__CHANNEL__) & ADC_CHANNEL_NUMBER_MASK) << ADC_AWD_CHANNEL_NUMBER_BITOFFSET_POS) \
2525 | (ADC_CHANNEL_LUT[(uint8_t)(__CHANNEL__)] & ADC_CHANNEL_ID_BITFIELD_MASK) \
2526 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) \
2527 : \
2528 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2529 ? ((((__CHANNEL__) & ADC_CHANNEL_NUMBER_MASK) << ADC_AWD_CHANNEL_NUMBER_BITOFFSET_POS) \
2530 | (ADC_CHANNEL_LUT[(uint8_t)(__CHANNEL__)] & ADC_CHANNEL_ID_BITFIELD_MASK) \
2531 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) \
2532 : \
2533 ((((__CHANNEL__) & ADC_CHANNEL_NUMBER_MASK) << ADC_AWD_CHANNEL_NUMBER_BITOFFSET_POS) \
2534 | (ADC_CHANNEL_LUT[(uint8_t)(__CHANNEL__)] & ADC_CHANNEL_ID_BITFIELD_MASK) \
2535 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) \
2536 )
2537
2538 /**
2539 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2540 * or low in function of ADC resolution when ADC resolution is different of 12 bit.
2541 * @note In case of ADC resolution different of 12 bits, this macro performs the required data formatting:
2542 * - analog watchdog thresholds data aligned to left side (bit 11).
2543 * - bits out of resolution range (LSB) set to value "0".
2544 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
2545 * Example, with a ADC resolution of 8 bits, to set the value of
2546 * analog watchdog threshold high (on 8 bits):
2547 * LL_ADC_SetAnalogWDThresholds
2548 * (< ADCx param >,
2549 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_data_8_bits>)
2550 * );
2551 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2552 * @arg @ref LL_ADC_RESOLUTION_12B
2553 * @arg @ref LL_ADC_RESOLUTION_10B
2554 * @arg @ref LL_ADC_RESOLUTION_8B
2555 * @arg @ref LL_ADC_RESOLUTION_6B
2556 * @param __AWD_THRESHOLD_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2557 * (or tigher range for data corresponding to lower ADC resolution)
2558 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2559 */
2560 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_DATA__) \
2561 ((__AWD_THRESHOLD_DATA__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1U )))
2562
2563 /**
2564 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2565 * or low in function of ADC resolution, when ADC resolution is
2566 * different of 12 bits.
2567 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2568 * Example, with a ADC resolution of 8 bits, to get the value of
2569 * analog watchdog threshold high (on 8 bits):
2570 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2571 * (LL_ADC_RESOLUTION_8B,
2572 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2573 * );
2574 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2575 * @arg @ref LL_ADC_RESOLUTION_12B
2576 * @arg @ref LL_ADC_RESOLUTION_10B
2577 * @arg @ref LL_ADC_RESOLUTION_8B
2578 * @arg @ref LL_ADC_RESOLUTION_6B
2579 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
2580 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2581 */
2582 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
2583 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1U )))
2584
2585 /**
2586 * @brief Helper macro to set the ADC calibration value with both single ended
2587 * and differential modes calibration factors concatenated.
2588 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2589 * Example, to set calibration factors single ended to 0x55
2590 * and differential ended to 0x2A:
2591 * LL_ADC_SetCalibrationFactor(
2592 * ADC1,
2593 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2594 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x1FF
2595 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x1FF
2596 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2597 */
2598 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2599 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2600
2601 #if defined(ADC_MULTIMODE_SUPPORT)
2602 /**
2603 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2604 * or ADC slave from raw value with both ADC conversion data concatenated.
2605 * @note This macro is intended to be used when multimode transfer by DMA
2606 * is enabled: refer to function @ref LL_ADC_SetMultiDataFormat().
2607 * In this case the transferred data need to processed with this macro
2608 * to separate the conversion data of ADC master and ADC slave.
2609 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2610 * @arg @ref LL_ADC_MULTI_MASTER
2611 * @arg @ref LL_ADC_MULTI_SLAVE
2612 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2613 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2614 */
2615 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2616 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2617 #endif /* ADC_MULTIMODE_SUPPORT */
2618
2619 #if defined(ADC_MULTIMODE_SUPPORT)
2620 /**
2621 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2622 * it has a dependence in multimode (ADC master of the corresponding
2623 * ADC common instance).
2624 * @note In case of device with multimode available and a mix of
2625 * ADC instances compliant and not compliant with multimode feature,
2626 * ADC instances not compliant with multimode feature are
2627 * considered as master instances (do not depend to
2628 * any other ADC instance).
2629 * @param __ADCx__ ADC instance
2630 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2631 */
2632 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2633 ( ( ((__ADCx__) == ADC2) \
2634 )? \
2635 (ADC1) \
2636 : \
2637 (__ADCx__) \
2638 )
2639 #endif /* ADC_MULTIMODE_SUPPORT */
2640
2641 /**
2642 * @brief Helper macro to select the ADC common instance
2643 * to which is belonging the selected ADC instance.
2644 * @note ADC common register instance can be used for:
2645 * - Set parameters common to several ADC instances
2646 * - Multimode (for devices with several ADC instances)
2647 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2648 * @param __ADCx__ ADC instance
2649 * @retval ADC common register instance
2650 */
2651 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
2652
2653 /**
2654 * @brief Helper macro to check if all ADC instances sharing the same
2655 * ADC common instance are disabled.
2656 * @note This check is required by functions with setting conditioned to
2657 * ADC state:
2658 * All ADC instances of the ADC common group must be disabled.
2659 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2660 * @note On devices with only 1 ADC common instance, parameter of this macro
2661 * is useless and can be ignored (parameter kept for compatibility
2662 * with devices featuring several ADC common instances).
2663 * @param __ADCXY_COMMON__ ADC common instance
2664 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2665 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2666 * are disabled.
2667 * Value "1" if at least one ADC instance sharing the same ADC common instance
2668 * is enabled.
2669 */
2670 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2671 (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
2672 /**
2673 * @brief Helper macro to define the ADC conversion data full-scale digital
2674 * value corresponding to the selected ADC resolution.
2675 * @note ADC conversion data full-scale corresponds to voltage range
2676 * determined by analog voltage references Vref+ and Vref-
2677 * (refer to reference manual).
2678 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2679 * @arg @ref LL_ADC_RESOLUTION_12B
2680 * @arg @ref LL_ADC_RESOLUTION_10B
2681 * @arg @ref LL_ADC_RESOLUTION_8B
2682 * @arg @ref LL_ADC_RESOLUTION_6B
2683 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2684 */
2685 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2686 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1UL)))
2687
2688 /**
2689 * @brief Helper macro to convert the ADC conversion data from
2690 * a resolution to another resolution.
2691 * @param __DATA__ ADC conversion data to be converted
2692 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2693 * This parameter can be one of the following values:
2694 * @arg @ref LL_ADC_RESOLUTION_12B
2695 * @arg @ref LL_ADC_RESOLUTION_10B
2696 * @arg @ref LL_ADC_RESOLUTION_8B
2697 * @arg @ref LL_ADC_RESOLUTION_6B
2698 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2699 * This parameter can be one of the following values:
2700 * @arg @ref LL_ADC_RESOLUTION_12B
2701 * @arg @ref LL_ADC_RESOLUTION_10B
2702 * @arg @ref LL_ADC_RESOLUTION_8B
2703 * @arg @ref LL_ADC_RESOLUTION_6B
2704 * @retval ADC conversion data to the requested resolution
2705 */
2706 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2707 __ADC_RESOLUTION_CURRENT__,\
2708 __ADC_RESOLUTION_TARGET__) \
2709 (((__DATA__) \
2710 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_Pos - 1UL))) \
2711 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_Pos - 1UL)) \
2712 )
2713
2714 /**
2715 * @brief Helper macro to calculate the voltage (unit: mVolt)
2716 * corresponding to a ADC conversion data (unit: digital value).
2717 * @note Analog reference voltage (Vref+) must be either known from
2718 * user board environment or can be calculated using ADC measurement
2719 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2720 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2721 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2722 * (unit: digital value).
2723 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2724 * @arg @ref LL_ADC_RESOLUTION_12B
2725 * @arg @ref LL_ADC_RESOLUTION_10B
2726 * @arg @ref LL_ADC_RESOLUTION_8B
2727 * @arg @ref LL_ADC_RESOLUTION_6B
2728 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2729 */
2730 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2731 __ADC_DATA__,\
2732 __ADC_RESOLUTION__) \
2733 ((__ADC_DATA__) * (int32_t)(__VREFANALOG_VOLTAGE__) \
2734 / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2735 )
2736
2737 /**
2738 * @brief Helper macro to calculate the voltage (unit: mVolt)
2739 * corresponding to a ADC conversion data (unit: digital value) in
2740 * differential ended mode.
2741 * @note ADC data from ADC data register is unsigned and centered around
2742 * middle code in. Converted voltage can be positive or negative
2743 * depending on differential input voltages.
2744 * @note Analog reference voltage (Vref+) must be either known from
2745 * user board environment or can be calculated using ADC measurement
2746 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2747 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2748 * @param __ADC_DATA__ ADC conversion data (unit: digital value).
2749 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2750 * @arg @ref LL_ADC_RESOLUTION_12B
2751 * @arg @ref LL_ADC_RESOLUTION_10B
2752 * @arg @ref LL_ADC_RESOLUTION_8B
2753 * @arg @ref LL_ADC_RESOLUTION_6B
2754 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2755 */
2756 #define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2757 __ADC_DATA__,\
2758 __ADC_RESOLUTION__)\
2759 ((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\
2760 / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\
2761 - (int32_t)(__VREFANALOG_VOLTAGE__))
2762
2763
2764 /**
2765 * @}
2766 */
2767
2768 /**
2769 * @}
2770 */
2771
2772
2773 /* Exported functions --------------------------------------------------------*/
2774 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2775 * @{
2776 */
2777
2778 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2779 * @{
2780 */
2781 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2782 /* configuration of ADC instance, groups and multimode (if available): */
2783 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2784
2785 /**
2786 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2787 * ADC register address from ADC instance and a list of ADC registers
2788 * intended to be used (most commonly) with DMA transfer.
2789 * @note These ADC registers are data registers:
2790 * when ADC conversion data is available in ADC data registers,
2791 * ADC generates a DMA transfer request.
2792 * @note This macro is intended to be used with LL DMA driver, refer to
2793 * function "LL_DMA_ConfigAddresses()".
2794 * Example:
2795 * LL_DMA_ConfigAddresses(DMA1,
2796 * LL_DMA_CHANNEL_1,
2797 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2798 * (uint32_t)&< array or variable >,
2799 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2800 * @note For devices with several ADC: in multimode, some devices
2801 * use a different data register outside of ADC instance scope
2802 * (common data register). This macro manages this register difference,
2803 * only ADC instance has to be set as parameter.
2804 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2805 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2806 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2807 * @param ADCx ADC instance
2808 * @param Register This parameter can be one of the following values:
2809 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2810 * @arg @ref LL_ADC_DMA_REG_REGULAR_MULTI_NO_PACKING (1)
2811 * @arg @ref LL_ADC_DMA_REG_REGULAR_MULTI_PACKING (1)
2812 *
2813 * (1) Available on devices with several ADC instances.
2814 * @retval ADC register address
2815 */
2816 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)2817 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
2818 {
2819 uint32_t data_reg_addr;
2820
2821 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2822 {
2823 /* Retrieve address of register DR */
2824 data_reg_addr = (uint32_t)(&(ADCx->DR));
2825 }
2826 else /* (Register == LL_ADC_DMA_REG_REGULAR_MULTI_NO_PACKING || LL_ADC_DMA_REG_REGULAR_MULTI_PACKING) */
2827 {
2828 /* Retrieve address of register CDR */
2829 data_reg_addr = (uint32_t)(&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR));
2830 }
2831
2832 return data_reg_addr;
2833 }
2834 #else
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)2835 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
2836 {
2837 /* Prevent unused argument(s) compilation warning */
2838 (void)(Register);
2839
2840 /* Retrieve address of register DR */
2841 return (uint32_t)(&(ADCx->DR));
2842 }
2843 #endif /* ADC_MULTIMODE_SUPPORT */
2844
2845 /**
2846 * @}
2847 */
2848
2849 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
2850 * ADC instances
2851 * @{
2852 */
2853
2854 /**
2855 * @brief Set parameter common to several ADC: measurement path to
2856 * internal channels (VrefInt, temperature sensor, ...).
2857 * Configure all paths (overwrite current configuration).
2858 * @note One or several values can be selected.
2859 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2860 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2861 * The values not selected are removed from configuration.
2862 * @note Stabilization time of measurement path to internal channel:
2863 * After enabling internal paths, before starting ADC conversion,
2864 * a delay is required for internal voltage reference and
2865 * temperature sensor stabilization time.
2866 * Refer to device datasheet.
2867 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2868 * @note ADC internal channel sampling time constraint:
2869 * For ADC conversion of internal channels,
2870 * a sampling time minimum value is required.
2871 * Refer to device datasheet.
2872 * @note On this STM32 series, setting of this feature is conditioned to
2873 * ADC state:
2874 * All ADC instances of the ADC common group must be disabled.
2875 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2876 * ADC instance or by using helper macro helper macro
2877 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2878 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2879 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2880 * @param ADCxy_COMMON ADC common instance
2881 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2882 * @param PathInternal This parameter can be a combination of the following values:
2883 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2884 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2885 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2886 * @retval None
2887 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2888 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2889 {
2890 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VBATEN, PathInternal);
2891 }
2892
2893 /**
2894 * @brief Set parameter common to several ADC: measurement path to
2895 * internal channels (VrefInt, temperature sensor, ...).
2896 * Add paths to the current configuration.
2897 * @note One or several values can be selected.
2898 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2899 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2900 * @note Stabilization time of measurement path to internal channel:
2901 * After enabling internal paths, before starting ADC conversion,
2902 * a delay is required for internal voltage reference and
2903 * temperature sensor stabilization time.
2904 * Refer to device datasheet.
2905 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2906 * @note ADC internal channel sampling time constraint:
2907 * For ADC conversion of internal channels,
2908 * a sampling time minimum value is required.
2909 * Refer to device datasheet.
2910 * @note On this STM32 series, setting of this feature is conditioned to
2911 * ADC state:
2912 * All ADC instances of the ADC common group must be disabled.
2913 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2914 * ADC instance or by using helper macro helper macro
2915 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2916 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
2917 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
2918 * @param ADCxy_COMMON ADC common instance
2919 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2920 * @param PathInternal This parameter can be a combination of the following values:
2921 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2922 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2923 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2924 * @retval None
2925 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2926 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2927 {
2928 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2929 }
2930
2931 /**
2932 * @brief Set parameter common to several ADC: measurement path to
2933 * internal channels (VrefInt, temperature sensor, ...).
2934 * Remove paths to the current configuration.
2935 * @note One or several values can be selected.
2936 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2937 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2938 * @note On this STM32 series, setting of this feature is conditioned to
2939 * ADC state:
2940 * All ADC instances of the ADC common group must be disabled.
2941 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2942 * ADC instance or by using helper macro helper macro
2943 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2944 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
2945 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
2946 * @param ADCxy_COMMON ADC common instance
2947 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2948 * @param PathInternal This parameter can be a combination of the following values:
2949 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2950 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2951 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2952 * @retval None
2953 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2954 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2955 {
2956 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2957 }
2958
2959 /**
2960 * @brief Get parameter common to several ADC: measurement path to internal
2961 * channels (VrefInt, temperature sensor, ...).
2962 * @note One or several values can be selected.
2963 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2964 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2965 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2966 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2967 * @param ADCxy_COMMON ADC common instance
2968 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2969 * @retval Returned value can be a combination of the following values:
2970 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2971 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2972 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2973 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)2974 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
2975 {
2976 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VBATEN));
2977 }
2978
2979 /**
2980 * @}
2981 */
2982
2983 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2984 * @{
2985 */
2986
2987 /**
2988 * @brief Set parameter on ADC instance scope: measurement path to
2989 * internal channels (Vcore, Vcpu...).
2990 * Configure all paths (overwrite current configuration).
2991 * @note One or several values can be selected.
2992 * Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
2993 * LL_ADC_PATH_INTERNAL_...)
2994 * The values not selected are removed from configuration.
2995 * @note Stabilization time of measurement path to internal channel:
2996 * After enabling internal paths, before starting ADC conversion,
2997 * a delay may be required required for analog stabilization.
2998 * Refer to device datasheet.
2999 * @note ADC internal channel sampling time constraint:
3000 * For ADC conversion of internal channels,
3001 * a sampling time minimum value is required.
3002 * Refer to device datasheet.
3003 * @rmtoll OR OP2 LL_ADC_SetPathInternalCh
3004 * @param ADCx ADC instance
3005 * @param PathInternal This parameter can be a combination of the following values:
3006 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3007 * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
3008 * @retval None
3009 */
LL_ADC_SetPathInternalCh(ADC_TypeDef * ADCx,uint32_t PathInternal)3010 __STATIC_INLINE void LL_ADC_SetPathInternalCh(ADC_TypeDef *ADCx, uint32_t PathInternal)
3011 {
3012 MODIFY_REG(ADCx->OR, ADC_OR_OP2, (PathInternal >> ADC_PATH_INTERNAL_POS));
3013 }
3014
3015 /**
3016 * @brief Set parameter on ADC instance scope: measurement path to
3017 * internal channels (Vcore, Vcpu...).
3018 * Add paths to the current configuration.
3019 * @note One or several values can be selected.
3020 * Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
3021 * LL_ADC_PATH_INTERNAL_...)
3022 * The values not selected are removed from configuration.
3023 * @note Stabilization time of measurement path to internal channel:
3024 * After enabling internal paths, before starting ADC conversion,
3025 * a delay may be required required for analog stabilization.
3026 * Refer to device datasheet.
3027 * @note ADC internal channel sampling time constraint:
3028 * For ADC conversion of internal channels,
3029 * a sampling time minimum value is required.
3030 * Refer to device datasheet.
3031 * @rmtoll OR OP2 LL_ADC_SetPathInternalChAdd
3032 * @param ADCx ADC instance
3033 * @param PathInternal This parameter can be a combination of the following values:
3034 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3035 * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
3036 * @retval None
3037 */
LL_ADC_SetPathInternalChAdd(ADC_TypeDef * ADCx,uint32_t PathInternal)3038 __STATIC_INLINE void LL_ADC_SetPathInternalChAdd(ADC_TypeDef *ADCx, uint32_t PathInternal)
3039 {
3040 SET_BIT(ADCx->OR, (PathInternal >> ADC_PATH_INTERNAL_POS));
3041 }
3042
3043 /**
3044 * @brief Set parameter on ADC instance scope: measurement path to
3045 * internal channels (Vcore, Vcpu...).
3046 * Remove paths to the current configuration.
3047 * @note One or several values can be selected.
3048 * Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
3049 * LL_ADC_PATH_INTERNAL_...)
3050 * The values not selected are removed from configuration.
3051 * @note Stabilization time of measurement path to internal channel:
3052 * After enabling internal paths, before starting ADC conversion,
3053 * a delay may be required required for analog stabilization.
3054 * Refer to device datasheet.
3055 * @note ADC internal channel sampling time constraint:
3056 * For ADC conversion of internal channels,
3057 * a sampling time minimum value is required.
3058 * Refer to device datasheet.
3059 * @rmtoll OR OP2 LL_ADC_SetPathInternalChRem
3060 * @param ADCx ADC instance
3061 * @param PathInternal This parameter can be a combination of the following values:
3062 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3063 * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
3064 * @retval None
3065 */
LL_ADC_SetPathInternalChRem(ADC_TypeDef * ADCx,uint32_t PathInternal)3066 __STATIC_INLINE void LL_ADC_SetPathInternalChRem(ADC_TypeDef *ADCx, uint32_t PathInternal)
3067 {
3068 CLEAR_BIT(ADCx->OR, (PathInternal >> ADC_PATH_INTERNAL_POS));
3069 }
3070
3071 /**
3072 * @brief Get parameter on ADC instance scope: measurement path to
3073 * internal channels (Vcore, Vcpu...).
3074 * @note One or several values can be selected.
3075 * Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
3076 * LL_ADC_PATH_INTERNAL_...)
3077 * @rmtoll OR OP2 LL_ADC_GetPathInternalCh
3078 * @param ADCx ADC instance
3079 * @retval Returned value can be one of the following values:
3080 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3081 * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
3082 */
LL_ADC_GetPathInternalCh(const ADC_TypeDef * ADCx)3083 __STATIC_INLINE uint32_t LL_ADC_GetPathInternalCh(const ADC_TypeDef *ADCx)
3084 {
3085 return (uint32_t)(READ_BIT(ADCx->OR, ADC_OR_OP2)) << ADC_PATH_INTERNAL_POS;
3086 }
3087
3088 /**
3089 * @brief Set ADC calibration factor in the mode single-ended
3090 * or differential (for devices with differential mode available).
3091 * @note This function is intended to set calibration parameters
3092 * without having to perform a new calibration using
3093 * @ref LL_ADC_StartCalibration().
3094 * @note In case of setting calibration factors of both modes single ended
3095 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
3096 * both calibration factors must be concatenated.
3097 * To perform this processing, use helper macro
3098 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
3099 * @note On this STM32 series, setting of this feature is conditioned to
3100 * ADC state:
3101 * ADC must be enabled, without calibration on going, without conversion
3102 * on going on group regular and group injected.
3103 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
3104 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
3105 * @param ADCx ADC instance
3106 * @param SingleDiff This parameter can be one of the following values:
3107 * @arg @ref LL_ADC_SINGLE_ENDED
3108 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3109 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
3110 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
3111 * @retval None
3112 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)3113 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
3114 {
3115 MODIFY_REG(ADCx->CALFACT,
3116 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
3117 (CalibrationFactor << (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS & ~(SingleDiff & ADC_CALFACT_CALFACT_S)))
3118 & SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK);
3119 }
3120 /**
3121 * @brief Get ADC calibration factor in the mode single-ended
3122 * or differential (for devices with differential mode available).
3123 * @note Calibration factors are set by hardware after performing
3124 * a calibration run using function @ref LL_ADC_StartCalibration().
3125 * @note For devices with differential mode available:
3126 * Calibration of offset is specific to each of
3127 * single-ended and differential modes
3128 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
3129 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
3130 * @param ADCx ADC instance
3131 * @param SingleDiff This parameter can be one of the following values:
3132 * @arg @ref LL_ADC_SINGLE_ENDED
3133 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3134 * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
3135 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx,uint32_t SingleDiff)3136 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
3137 {
3138 /* Retrieve bits with position in register depending on parameter */
3139 /* "SingleDiff". */
3140 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
3141 /* containing other bits reserved for other purpose. */
3142 return (uint32_t)(READ_BIT(ADCx->CALFACT,
3143 (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK))
3144 >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
3145 ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
3146 }
3147 /**
3148 * @brief Set ADC resolution.
3149 * Refer to reference manual for alignments formats
3150 * dependencies to ADC resolutions.
3151 * @note On this STM32 series, setting of this feature is conditioned to
3152 * ADC state:
3153 * ADC must be disabled or enabled without conversion on going
3154 * on either groups regular or injected.
3155 * @rmtoll CFGR1 RES LL_ADC_SetResolution
3156 * @param ADCx ADC instance
3157 * @param Resolution This parameter can be one of the following values:
3158 * @arg @ref LL_ADC_RESOLUTION_12B
3159 * @arg @ref LL_ADC_RESOLUTION_10B
3160 * @arg @ref LL_ADC_RESOLUTION_8B
3161 * @arg @ref LL_ADC_RESOLUTION_6B
3162 * @retval None
3163 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)3164 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
3165 {
3166 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
3167 }
3168
3169 /**
3170 * @brief Get ADC resolution.
3171 * Refer to reference manual for alignments formats
3172 * dependencies to ADC resolutions.
3173 * @rmtoll CFGR1 RES LL_ADC_GetResolution
3174 * @param ADCx ADC instance
3175 * @retval Returned value can be one of the following values:
3176 * @arg @ref LL_ADC_RESOLUTION_12B
3177 * @arg @ref LL_ADC_RESOLUTION_10B
3178 * @arg @ref LL_ADC_RESOLUTION_8B
3179 * @arg @ref LL_ADC_RESOLUTION_6B
3180 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)3181 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
3182 {
3183 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
3184 }
3185
3186 /**
3187 * @brief Set ADC low power mode.
3188 * @note Description of ADC low power modes:
3189 * - ADC low power mode "auto wait": Dynamic low power mode,
3190 * ADC conversions occurrences are limited to the minimum necessary
3191 * in order to reduce power consumption.
3192 * New ADC conversion starts only when the previous
3193 * unitary conversion data (for ADC group regular)
3194 * or previous sequence conversions data (for ADC group injected)
3195 * has been retrieved by user software.
3196 * In the meantime, ADC remains idle: does not performs any
3197 * other conversion.
3198 * This mode allows to automatically adapt the ADC conversions
3199 * triggers to the speed of the software that reads the data.
3200 * Moreover, this avoids risk of overrun for low frequency
3201 * applications.
3202 * How to use this low power mode:
3203 * - It is not recommended to use with interruption or DMA
3204 * since these modes have to clear immediately the EOC flag
3205 * (by CPU to free the IRQ pending event or by DMA).
3206 * Auto wait will work but fort a very short time, discarding
3207 * its intended benefit (except specific case of high load of CPU
3208 * or DMA transfers which can justify usage of auto wait).
3209 * - Do use with polling: 1. Start conversion,
3210 * 2. Later on, when conversion data is needed: poll for end of
3211 * conversion to ensure that conversion is completed and
3212 * retrieve ADC conversion data. This will trig another
3213 * ADC conversion start.
3214 * - ADC low power mode "auto power-off" (feature available on
3215 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3216 * the ADC automatically powers-off after a conversion and
3217 * automatically wakes up when a new conversion is triggered
3218 * (with startup time between trigger and start of sampling).
3219 * This feature can be combined with low power mode "auto wait".
3220 * @note With ADC low power mode "auto wait", the ADC conversion data read
3221 * is corresponding to previous ADC conversion start, independently
3222 * of delay during which ADC was idle.
3223 * Therefore, the ADC conversion data may be outdated: does not
3224 * correspond to the current voltage level on the selected
3225 * ADC channel.
3226 * @note On this STM32 series, setting of this feature is conditioned to
3227 * ADC state:
3228 * ADC must be disabled or enabled without conversion on going
3229 * on either groups regular or injected.
3230 * @rmtoll CFGR1 AUTDLY LL_ADC_SetLPModeAutoWait
3231 * @param ADCx ADC instance
3232 * @param LowPowerMode This parameter can be one of the following values:
3233 * @arg @ref LL_ADC_LP_AUTOWAIT_DISABLE
3234 * @arg @ref LL_ADC_LP_AUTOWAIT_ENABLE
3235 * @retval None
3236 */
LL_ADC_SetLPModeAutoWait(ADC_TypeDef * ADCx,uint32_t LowPowerMode)3237 __STATIC_INLINE void LL_ADC_SetLPModeAutoWait(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3238 {
3239 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_AUTDLY), LowPowerMode);
3240 }
3241
3242 /**
3243 * @brief Get ADC low power mode:
3244 * @note Description of ADC low power modes:
3245 * - ADC low power mode "auto wait": Dynamic low power mode,
3246 * ADC conversions occurrences are limited to the minimum necessary
3247 * in order to reduce power consumption.
3248 * New ADC conversion starts only when the previous
3249 * unitary conversion data (for ADC group regular)
3250 * or previous sequence conversions data (for ADC group injected)
3251 * has been retrieved by user software.
3252 * In the meantime, ADC remains idle: does not performs any
3253 * other conversion.
3254 * This mode allows to automatically adapt the ADC conversions
3255 * triggers to the speed of the software that reads the data.
3256 * Moreover, this avoids risk of overrun for low frequency
3257 * applications.
3258 * How to use this low power mode:
3259 * - It is not recommended to use with interruption or DMA
3260 * since these modes have to clear immediately the EOC flag
3261 * (by CPU to free the IRQ pending event or by DMA).
3262 * Auto wait will work but fort a very short time, discarding
3263 * its intended benefit (except specific case of high load of CPU
3264 * or DMA transfers which can justify usage of auto wait).
3265 * - Do use with polling: 1. Start conversion,
3266 * 2. Later on, when conversion data is needed: poll for end of
3267 * conversion to ensure that conversion is completed and
3268 * retrieve ADC conversion data. This will trig another
3269 * ADC conversion start.
3270 * - ADC low power mode "auto power-off" (feature available on
3271 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3272 * the ADC automatically powers-off after a conversion and
3273 * automatically wakes up when a new conversion is triggered
3274 * (with startup time between trigger and start of sampling).
3275 * This feature can be combined with low power mode "auto wait".
3276 * @note With ADC low power mode "auto wait", the ADC conversion data read
3277 * is corresponding to previous ADC conversion start, independently
3278 * of delay during which ADC was idle.
3279 * Therefore, the ADC conversion data may be outdated: does not
3280 * correspond to the current voltage level on the selected
3281 * ADC channel.
3282 * @rmtoll CFGR1 AUTDLY LL_ADC_GetLPModeAutoWait
3283 * @param ADCx ADC instance
3284 * @retval Returned value can be one of the following values:
3285 * @arg @ref LL_ADC_LP_AUTOWAIT_DISABLE
3286 * @arg @ref LL_ADC_LP_AUTOWAIT_ENABLE
3287 */
LL_ADC_GetLPModeAutoWait(const ADC_TypeDef * ADCx)3288 __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoWait(const ADC_TypeDef *ADCx)
3289 {
3290 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_AUTDLY));
3291 }
3292
3293 /**
3294 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3295 * Channel to which the offset programmed will be applied
3296 * (independently of channel mapped on ADC group regular
3297 * or group injected)
3298 * @note If a channel is mapped on several offsets numbers, only the offset
3299 * with the lowest value is considered for the subtraction.
3300 * @note On this STM32 series, setting of this feature is conditioned to
3301 * ADC state:
3302 * ADC must be disabled or enabled without conversion on going
3303 * on either groups regular or injected.
3304 * @rmtoll OFR1 OFFSET_CH LL_ADC_SetOffsetChannel\n
3305 * OFR2 OFFSET_CH LL_ADC_SetOffsetChannel\n
3306 * OFR3 OFFSET_CH LL_ADC_SetOffsetChannel\n
3307 * OFR4 OFFSET_CH LL_ADC_SetOffsetChannel
3308 * @param ADCx ADC instance
3309 * @param Offsety This parameter can be one of the following values:
3310 * @arg @ref LL_ADC_OFFSET_1
3311 * @arg @ref LL_ADC_OFFSET_2
3312 * @arg @ref LL_ADC_OFFSET_3
3313 * @arg @ref LL_ADC_OFFSET_4
3314 * @param Channel This parameter can be one of the following values:
3315 * @arg @ref LL_ADC_CHANNEL_0
3316 * @arg @ref LL_ADC_CHANNEL_1
3317 * @arg @ref LL_ADC_CHANNEL_2
3318 * @arg @ref LL_ADC_CHANNEL_3
3319 * @arg @ref LL_ADC_CHANNEL_4
3320 * @arg @ref LL_ADC_CHANNEL_5
3321 * @arg @ref LL_ADC_CHANNEL_6
3322 * @arg @ref LL_ADC_CHANNEL_7
3323 * @arg @ref LL_ADC_CHANNEL_8
3324 * @arg @ref LL_ADC_CHANNEL_9
3325 * @arg @ref LL_ADC_CHANNEL_10
3326 * @arg @ref LL_ADC_CHANNEL_11
3327 * @arg @ref LL_ADC_CHANNEL_12
3328 * @arg @ref LL_ADC_CHANNEL_13
3329 * @arg @ref LL_ADC_CHANNEL_14
3330 * @arg @ref LL_ADC_CHANNEL_15
3331 * @arg @ref LL_ADC_CHANNEL_16
3332 * @arg @ref LL_ADC_CHANNEL_17
3333 * @arg @ref LL_ADC_CHANNEL_18
3334 * @arg @ref LL_ADC_CHANNEL_19
3335 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3336 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
3337 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
3338 *
3339 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
3340 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
3341 * @retval None
3342 */
LL_ADC_SetOffsetChannel(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel)3343 __STATIC_INLINE void LL_ADC_SetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel)
3344 {
3345 __IO uint32_t *preg_offset_cfg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
3346
3347 MODIFY_REG(*preg_offset_cfg,
3348 ADC_OFCFGR1_OFFSET_CH,
3349 (Channel & ADC_CHANNEL_NUMBER_MASK) << ADC_OFCFGR1_OFFSET_CH_Pos);
3350 }
3351
3352 /**
3353 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3354 * Channel to which the offset programmed will be applied
3355 * (independently of channel mapped on ADC group regular
3356 * or group injected)
3357 * @note Usage of the returned channel number:
3358 * - To reinject this channel into another function LL_ADC_xxx:
3359 * the returned channel number is only partly formatted on definition
3360 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3361 * with parts of literals LL_ADC_CHANNEL_x or using
3362 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3363 * Then the selected literal LL_ADC_CHANNEL_x can be used
3364 * as parameter for another function.
3365 * - To get the channel number in decimal format:
3366 * process the returned value with the helper macro
3367 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3368 * @rmtoll OFR1 OFFSET_CH LL_ADC_SetOffsetChannel\n
3369 * OFR2 OFFSET_CH LL_ADC_SetOffsetChannel\n
3370 * OFR3 OFFSET_CH LL_ADC_SetOffsetChannel\n
3371 * OFR4 OFFSET_CH LL_ADC_SetOffsetChannel
3372 * @param ADCx ADC instance
3373 * @param Offsety This parameter can be one of the following values:
3374 * @arg @ref LL_ADC_OFFSET_1
3375 * @arg @ref LL_ADC_OFFSET_2
3376 * @arg @ref LL_ADC_OFFSET_3
3377 * @arg @ref LL_ADC_OFFSET_4
3378 * @retval Returned value can be one of the following values:
3379 * @arg @ref LL_ADC_CHANNEL_0
3380 * @arg @ref LL_ADC_CHANNEL_1
3381 * @arg @ref LL_ADC_CHANNEL_2
3382 * @arg @ref LL_ADC_CHANNEL_3
3383 * @arg @ref LL_ADC_CHANNEL_4
3384 * @arg @ref LL_ADC_CHANNEL_5
3385 * @arg @ref LL_ADC_CHANNEL_6
3386 * @arg @ref LL_ADC_CHANNEL_7
3387 * @arg @ref LL_ADC_CHANNEL_8
3388 * @arg @ref LL_ADC_CHANNEL_9
3389 * @arg @ref LL_ADC_CHANNEL_10
3390 * @arg @ref LL_ADC_CHANNEL_11
3391 * @arg @ref LL_ADC_CHANNEL_12
3392 * @arg @ref LL_ADC_CHANNEL_13
3393 * @arg @ref LL_ADC_CHANNEL_14
3394 * @arg @ref LL_ADC_CHANNEL_15
3395 * @arg @ref LL_ADC_CHANNEL_16
3396 * @arg @ref LL_ADC_CHANNEL_17
3397 * @arg @ref LL_ADC_CHANNEL_18
3398 * @arg @ref LL_ADC_CHANNEL_19
3399 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
3400 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(3)
3401 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(3)
3402 *
3403 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
3404 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
3405 * (3) For ADC channel read back from ADC register,
3406 * comparison with internal channel parameter to be done
3407 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3408 */
LL_ADC_GetOffsetChannel(const ADC_TypeDef * ADCx,uint32_t Offsety)3409 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3410 {
3411 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
3412
3413 return (uint32_t) __LL_ADC_DECIMAL_NB_TO_CHANNEL(READ_BIT(*preg, ADC_OFCFGR1_OFFSET_CH) >> ADC_OFCFGR1_OFFSET_CH_Pos);
3414 }
3415
3416 /**
3417 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3418 * Offset level (offset to be subtracted from the raw
3419 * converted data).
3420 * @note Caution: Offset format is dependent to ADC resolution:
3421 * offset has to be left-aligned on bit 11, the LSB (right bits)
3422 * are set to 0.
3423 * @note On this STM32 series, setting of this feature is conditioned to
3424 * ADC state:
3425 * ADC must be disabled or enabled without conversion on going
3426 * on either groups regular or injected.
3427 * @rmtoll OFR1 OFFSET1 LL_ADC_SetOffsetLevel\n
3428 * OFR2 OFFSET2 LL_ADC_SetOffsetLevel\n
3429 * OFR3 OFFSET3 LL_ADC_SetOffsetLevel\n
3430 * OFR4 OFFSET4 LL_ADC_SetOffsetLevel
3431 * @param ADCx ADC instance
3432 * @param Offsety This parameter can be one of the following values:
3433 * @arg @ref LL_ADC_OFFSET_1
3434 * @arg @ref LL_ADC_OFFSET_2
3435 * @arg @ref LL_ADC_OFFSET_3
3436 * @arg @ref LL_ADC_OFFSET_4
3437 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x00FFFFFF
3438 * @retval None
3439 */
LL_ADC_SetOffsetLevel(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetLevel)3440 __STATIC_INLINE void LL_ADC_SetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetLevel)
3441 {
3442 __IO uint32_t *preg_offset_val = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3443
3444 MODIFY_REG(*preg_offset_val,
3445 ADC_OFR1_OFFSET,
3446 OffsetLevel);
3447 }
3448
3449 /**
3450 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3451 * Offset level (offset to be subtracted from the raw
3452 * converted data).
3453 * @note Caution: Offset format is dependent to ADC resolution:
3454 * offset has to be left-aligned on bit 11, the LSB (right bits)
3455 * are set to 0.
3456 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3457 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3458 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3459 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3460 * @param ADCx ADC instance
3461 * @param Offsety This parameter can be one of the following values:
3462 * @arg @ref LL_ADC_OFFSET_1
3463 * @arg @ref LL_ADC_OFFSET_2
3464 * @arg @ref LL_ADC_OFFSET_3
3465 * @arg @ref LL_ADC_OFFSET_4
3466 * @retval Value between Min_Data=0x000 and Max_Data=0x00FFFFFF
3467 */
LL_ADC_GetOffsetLevel(const ADC_TypeDef * ADCx,uint32_t Offsety)3468 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3469 {
3470 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3471
3472 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET);
3473 }
3474
3475 /**
3476 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
3477 * force offset state disable or enable
3478 * without modifying offset channel or offset value.
3479 * @note This function should be needed only in case of offset to be
3480 * enabled-disabled dynamically, and should not be needed in other cases:
3481 * function LL_ADC_SetOffset() automatically enables the offset.
3482 * @note On this STM32 series, setting of this feature is conditioned to
3483 * ADC state:
3484 * ADC must be disabled or enabled without conversion on going
3485 * on either groups regular or injected.
3486 * @rmtoll OFCFGR1 OFFSETPOS LL_ADC_SetOffsetSign\n
3487 * OFCFGR2 OFFSETPOS LL_ADC_SetOffsetSign\n
3488 * OFCFGR3 OFFSETPOS LL_ADC_SetOffsetSign\n
3489 * OFCFGR4 OFFSETPOS LL_ADC_SetOffsetSign
3490 * @param ADCx ADC instance
3491 * @param Offsety This parameter can be one of the following values:
3492 * @arg @ref LL_ADC_OFFSET_1
3493 * @arg @ref LL_ADC_OFFSET_2
3494 * @arg @ref LL_ADC_OFFSET_3
3495 * @arg @ref LL_ADC_OFFSET_4
3496 * @param OffsetSign This parameter can be one of the following values:
3497 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3498 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3499 * @retval None
3500 */
LL_ADC_SetOffsetSign(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSign)3501 __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
3502 {
3503 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
3504
3505 MODIFY_REG(*preg,
3506 ADC_OFCFGR1_POSOFF,
3507 OffsetSign);
3508 }
3509
3510 /**
3511 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3512 * offset sign if positive or negative.
3513 * @rmtoll OFCFGR1 OFFSETPOS LL_ADC_GetOffsetSign\n
3514 * OFCFGR2 OFFSETPOS LL_ADC_GetOffsetSign\n
3515 * OFCFGR3 OFFSETPOS LL_ADC_GetOffsetSign\n
3516 * OFCFGR4 OFFSETPOS LL_ADC_GetOffsetSign
3517 * @param ADCx ADC instance
3518 * @param Offsety This parameter can be one of the following values:
3519 * @arg @ref LL_ADC_OFFSET_1
3520 * @arg @ref LL_ADC_OFFSET_2
3521 * @arg @ref LL_ADC_OFFSET_3
3522 * @arg @ref LL_ADC_OFFSET_4
3523 * @retval Returned value can be one of the following values:
3524 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3525 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3526 */
LL_ADC_GetOffsetSign(const ADC_TypeDef * ADCx,uint32_t Offsety)3527 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety)
3528 {
3529 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
3530
3531 return (uint32_t) READ_BIT(*preg, ADC_OFCFGR1_POSOFF);
3532 }
3533
3534 /**
3535 * @brief Set Signed saturation for the ADC selected offset instance 1, 2, 3 or 4:
3536 * signed offset saturation if enabled or disabled.
3537 * @rmtoll OFCFGR1 SSAT LL_ADC_SetOffsetSignedSaturation\n
3538 * OFCFGR2 SSAT LL_ADC_SetOffsetSignedSaturation\n
3539 * OFCFGR3 SSAT LL_ADC_SetOffsetSignedSaturation\n
3540 * OFCFGR4 SSAT LL_ADC_SetOffsetSignedSaturation
3541 * @param ADCx ADC instance
3542 * @param Offsety This parameter can be one of the following values:
3543 * @arg @ref LL_ADC_OFFSET_1
3544 * @arg @ref LL_ADC_OFFSET_2
3545 * @arg @ref LL_ADC_OFFSET_3
3546 * @arg @ref LL_ADC_OFFSET_4
3547 * @param OffsetSignedSaturation This parameter can be one of the following values:
3548 * @arg @ref LL_ADC_OFFSET_SIGNED_SAT_ENABLE
3549 * @arg @ref LL_ADC_OFFSET_SIGNED_SAT_DISABLE
3550 * @retval None
3551 */
LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSignedSaturation)3552 __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
3553 uint32_t OffsetSignedSaturation)
3554 {
3555 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
3556 MODIFY_REG(*preg, ADC_OFCFGR1_SSAT, OffsetSignedSaturation);
3557 }
3558
3559 /**
3560 * @brief Get Signed saturation for the ADC selected offset number 1, 2, 3 or 4:
3561 * signed offset saturation if enabled or disabled.
3562 * @rmtoll OFCFGR1 SSAT LL_ADC_GetOffsetSignedSaturation\n
3563 * OFCFGR2 SSAT LL_ADC_GetOffsetSignedSaturation\n
3564 * OFCFGR3 SSAT LL_ADC_GetOffsetSignedSaturation\n
3565 * OFCFGR4 SSAT LL_ADC_GetOffsetSignedSaturation
3566 * @param ADCx ADC instance
3567 * @param Offsety This parameter can be one of the following values:
3568 * @arg @ref LL_ADC_OFFSET_1
3569 * @arg @ref LL_ADC_OFFSET_2
3570 * @arg @ref LL_ADC_OFFSET_3
3571 * @arg @ref LL_ADC_OFFSET_4
3572 * @retval Returned value can be one of the following values:
3573 * @arg @ref LL_ADC_OFFSET_SIGNED_SAT_ENABLE
3574 * @arg @ref LL_ADC_OFFSET_SIGNED_SAT_DISABLE
3575 */
LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef * ADCx,uint32_t Offsety)3576 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
3577 {
3578 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
3579 return (uint32_t) READ_BIT(*preg, ADC_OFCFGR1_SSAT);
3580 }
3581
3582 /**
3583 * @brief Set Unsigned saturation for the ADC selected offset instance 1, 2, 3 or 4:
3584 * signed offset saturation if enabled or disabled.
3585 * @rmtoll OFCFGR1 USAT LL_ADC_SetOffsetUnsignedSaturation\n
3586 * OFCFGR2 USAT LL_ADC_SetOffsetUnsignedSaturation\n
3587 * OFCFGR3 USAT LL_ADC_SetOffsetUnsignedSaturation\n
3588 * OFCFGR4 USAT LL_ADC_SetOffsetUnsignedSaturation
3589 * @param ADCx ADC instance
3590 * @param Offsety This parameter can be one of the following values:
3591 * @arg @ref LL_ADC_OFFSET_1
3592 * @arg @ref LL_ADC_OFFSET_2
3593 * @arg @ref LL_ADC_OFFSET_3
3594 * @arg @ref LL_ADC_OFFSET_4
3595 * @param OffsetUnsignedSaturation This parameter can be one of the following values:
3596 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SAT_ENABLE
3597 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SAT_DISABLE
3598 * @retval None
3599 */
LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetUnsignedSaturation)3600 __STATIC_INLINE void LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
3601 uint32_t OffsetUnsignedSaturation)
3602 {
3603 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
3604 MODIFY_REG(*preg, ADC_OFCFGR1_USAT, OffsetUnsignedSaturation);
3605 }
3606
3607 /**
3608 * @brief Get Unsigned saturation for the ADC selected offset instance 1, 2, 3 or 4:
3609 * signed offset saturation if enabled or disabled.
3610 * @rmtoll OFCFGR1 USAT LL_ADC_GetOffsetUnsignedSaturation\n
3611 * OFCFGR2 USAT LL_ADC_GetOffsetUnsignedSaturation\n
3612 * OFCFGR3 USAT LL_ADC_GetOffsetUnsignedSaturation\n
3613 * OFCFGR4 USAT LL_ADC_GetOffsetUnsignedSaturation
3614 * @param ADCx ADC instance
3615 * @param Offsety This parameter can be one of the following values:
3616 * @arg @ref LL_ADC_OFFSET_1
3617 * @arg @ref LL_ADC_OFFSET_2
3618 * @arg @ref LL_ADC_OFFSET_3
3619 * @arg @ref LL_ADC_OFFSET_4
3620 * @retval Returned value can be one of the following values:
3621 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SAT_ENABLE
3622 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SAT_DISABLE
3623 */
LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef * ADCx,uint32_t Offsety)3624 __STATIC_INLINE uint32_t LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
3625 {
3626 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
3627 return (uint32_t) READ_BIT(*preg, ADC_OFCFGR1_USAT);
3628 }
3629
3630 /**
3631 * @brief Set ADC gain compensation.
3632 * @note This function set the gain compensation coefficient
3633 * that is applied to raw converted data using the formula:
3634 * DATA = DATA(raw) * (gain compensation coef) / 4096
3635 * @note This function enables the gain compensation if given
3636 * coefficient is above 0, otherwise it disables it.
3637 * @note Gain compensation when enabled is applied to all channels.
3638 * @note On this STM32 series, setting of this feature is conditioned to
3639 * ADC state:
3640 * ADC must be disabled or enabled without conversion on going
3641 * on either groups regular or injected.
3642 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n
3643 * CFGR2 GCOMP LL_ADC_SetGainCompensation
3644 * @param ADCx ADC instance
3645 * @param GainCompensation This parameter can be:
3646 * 0 Gain compensation will be disabled and value set to 0
3647 * 1 -> 16393 Gain compensation will be enabled with specified value
3648 * @retval None
3649 */
LL_ADC_SetGainCompensation(ADC_TypeDef * ADCx,uint32_t GainCompensation)3650 __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
3651 {
3652 MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
3653 MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_GCOMP_GCOMP_Pos);
3654 }
3655
3656 /**
3657 * @brief Get the ADC gain compensation value
3658 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n
3659 * CFGR2 GCOMP LL_ADC_GetGainCompensation
3660 * @param ADCx ADC instance
3661 * @retval Returned value can be:
3662 * 0 Gain compensation is disabled
3663 * 1 -> 16393 Gain compensation is enabled with returned value
3664 */
LL_ADC_GetGainCompensation(const ADC_TypeDef * ADCx)3665 __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx)
3666 {
3667 return ((READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMP) == ADC_GCOMP_GCOMP) \
3668 ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
3669 }
3670
3671 /**
3672 * @}
3673 */
3674
3675 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3676 * @{
3677 */
3678
3679 /**
3680 * @brief Set ADC group regular conversion trigger source:
3681 * internal (SW start) or from external peripheral (timer event,
3682 * external interrupt line).
3683 * @note On this STM32 series, setting trigger source to external trigger
3684 * also set trigger polarity to rising edge
3685 * (default setting for compatibility with some ADC on other
3686 * STM32 series having this setting set by HW default value).
3687 * In case of need to modify trigger edge, use
3688 * function @ref LL_ADC_REG_SetTriggerEdge().
3689 * @note Availability of parameters of trigger sources from timer
3690 * depends on timers availability on the selected device.
3691 * @note On this STM32 series, setting of this feature is conditioned to
3692 * ADC state:
3693 * ADC must be disabled or enabled without conversion on going
3694 * on group regular.
3695 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
3696 * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
3697 * @param ADCx ADC instance
3698 * @param TriggerSource This parameter can be one of the following values:
3699 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3700 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3701 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3702 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3703 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3704 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3705 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3706 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3707 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3708 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3709 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3710 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3711 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3712 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
3713 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3714 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
3715 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3716 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3717 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH1
3718 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
3719 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM12_TRGO
3720 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3721 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM18_TRGO
3722 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
3723 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
3724 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
3725 * @retval None
3726 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3727 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3728 {
3729 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
3730 }
3731
3732 /**
3733 * @brief Get ADC group regular conversion trigger source:
3734 * internal (SW start) or from external peripheral (timer event,
3735 * external interrupt line).
3736 * @note To determine whether group regular trigger source is
3737 * internal (SW start) or external, without detail
3738 * of which peripheral is selected as external trigger,
3739 * (equivalent to
3740 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3741 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3742 * @note Availability of parameters of trigger sources from timer
3743 * depends on timers availability on the selected device.
3744 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
3745 * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
3746 * @param ADCx ADC instance
3747 * @retval Returned value can be one of the following values:
3748 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3749 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3750 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3751 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3752 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3753 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3754 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3755 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3756 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3757 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3758 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3759 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3760 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3761 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
3762 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3763 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
3764 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3765 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3766 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH1
3767 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
3768 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM12_TRGO
3769 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3770 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM18_TRGO
3771 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
3772 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
3773 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
3774 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)3775 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
3776 {
3777 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
3778
3779 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3780 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
3781 uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3782
3783 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
3784 /* to match with triggers literals definition. */
3785 return ((trigger_source
3786 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
3787 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
3788 );
3789 }
3790
3791 /**
3792 * @brief Get ADC group regular conversion trigger source internal (SW start)
3793 * or external.
3794 * @note In case of group regular trigger source set to external trigger,
3795 * to determine which peripheral is selected as external trigger,
3796 * use function @ref LL_ADC_REG_GetTriggerSource().
3797 * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3798 * @param ADCx ADC instance
3799 * @retval Value "0" if trigger source external trigger
3800 * Value "1" if trigger source SW start.
3801 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)3802 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
3803 {
3804 return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
3805 }
3806
3807 /**
3808 * @brief Set ADC group regular conversion trigger polarity.
3809 * @note Applicable only for trigger source set to external trigger.
3810 * @note On this STM32 series, setting of this feature is conditioned to
3811 * ADC state:
3812 * ADC must be disabled or enabled without conversion on going
3813 * on group regular.
3814 * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
3815 * @param ADCx ADC instance
3816 * @param ExternalTriggerEdge This parameter can be one of the following values:
3817 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3818 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3819 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3820 * @retval None
3821 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3822 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3823 {
3824 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
3825 }
3826
3827 /**
3828 * @brief Get ADC group regular conversion trigger polarity.
3829 * @note Applicable only for trigger source set to external trigger.
3830 * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
3831 * @param ADCx ADC instance
3832 * @retval Returned value can be one of the following values:
3833 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3834 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3835 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3836 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)3837 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
3838 {
3839 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
3840 }
3841
3842 /**
3843 * @brief Set ADC sampling mode.
3844 * @note This function set the ADC conversion sampling mode
3845 * @note This mode applies to regular group only.
3846 * @note Set sampling mode is applied to all conversion of regular group.
3847 * @note On this STM32 series, setting of this feature is conditioned to
3848 * ADC state:
3849 * ADC must be disabled or enabled without conversion on going
3850 * on group regular.
3851 * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
3852 * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
3853 * @param ADCx ADC instance
3854 * @param SamplingMode This parameter can be one of the following values:
3855 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
3856 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
3857 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
3858 * @retval None
3859 */
LL_ADC_REG_SetSamplingMode(ADC_TypeDef * ADCx,uint32_t SamplingMode)3860 __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
3861 {
3862 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
3863 }
3864
3865 /**
3866 * @brief Get the ADC sampling mode
3867 * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n
3868 * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
3869 * @param ADCx ADC instance
3870 * @retval Returned value can be one of the following values:
3871 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
3872 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
3873 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
3874 */
LL_ADC_REG_GetSamplingMode(const ADC_TypeDef * ADCx)3875 __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx)
3876 {
3877 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
3878 }
3879
3880 /**
3881 * @brief Start ADC sampling phase for sampling time trigger mode
3882 * @note This function is relevant only when
3883 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
3884 * using @ref LL_ADC_REG_SetSamplingMode
3885 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
3886 * @note On this STM32 series, setting of this feature is conditioned to
3887 * ADC state:
3888 * ADC must be enabled without conversion on going on group regular,
3889 * without conversion stop command on going on group regular,
3890 * without ADC disable command on going.
3891 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
3892 * @param ADCx ADC instance
3893 * @retval None
3894 */
LL_ADC_REG_StartSamplingPhase(ADC_TypeDef * ADCx)3895 __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
3896 {
3897 SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
3898 }
3899
3900 /**
3901 * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion
3902 * @note This function is relevant only when
3903 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
3904 * using @ref LL_ADC_REG_SetSamplingMode
3905 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
3906 * - @ref LL_ADC_REG_StartSamplingPhase has been called to start
3907 * the sampling phase
3908 * @note On this STM32 series, setting of this feature is conditioned to
3909 * ADC state:
3910 * ADC must be enabled without conversion on going on group regular,
3911 * without conversion stop command on going on group regular,
3912 * without ADC disable command on going.
3913 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
3914 * @param ADCx ADC instance
3915 * @retval None
3916 */
LL_ADC_REG_StopSamplingPhase(ADC_TypeDef * ADCx)3917 __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
3918 {
3919 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
3920 }
3921
3922 /**
3923 * @brief Set ADC group regular sequencer length and scan direction.
3924 * @note Description of ADC group regular sequencer features:
3925 * - For devices with sequencer fully configurable
3926 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3927 * sequencer length and each rank affectation to a channel
3928 * are configurable.
3929 * This function performs configuration of:
3930 * - Sequence length: Number of ranks in the scan sequence.
3931 * - Sequence direction: Unless specified in parameters, sequencer
3932 * scan direction is forward (from rank 1 to rank n).
3933 * Sequencer ranks are selected using
3934 * function "LL_ADC_REG_SetSequencerRanks()".
3935 * - For devices with sequencer not fully configurable
3936 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3937 * sequencer length and each rank affectation to a channel
3938 * are defined by channel number.
3939 * This function performs configuration of:
3940 * - Sequence length: Number of ranks in the scan sequence is
3941 * defined by number of channels set in the sequence,
3942 * rank of each channel is fixed by channel HW number.
3943 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3944 * - Sequence direction: Unless specified in parameters, sequencer
3945 * scan direction is forward (from lowest channel number to
3946 * highest channel number).
3947 * Sequencer ranks are selected using
3948 * function "LL_ADC_REG_SetSequencerChannels()".
3949 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3950 * ADC conversion on only 1 channel.
3951 * @note On this STM32 series, setting of this feature is conditioned to
3952 * ADC state:
3953 * ADC must be disabled or enabled without conversion on going
3954 * on group regular.
3955 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
3956 * @param ADCx ADC instance
3957 * @param SequencerNbRanks This parameter can be one of the following values:
3958 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3959 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3960 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3961 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3962 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3963 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3964 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3965 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3966 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3967 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3968 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3969 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3970 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3971 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3972 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3973 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3974 * @retval None
3975 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)3976 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3977 {
3978 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3979 }
3980
3981 /**
3982 * @brief Get ADC group regular sequencer length and scan direction.
3983 * @note Description of ADC group regular sequencer features:
3984 * - For devices with sequencer fully configurable
3985 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3986 * sequencer length and each rank affectation to a channel
3987 * are configurable.
3988 * This function retrieves:
3989 * - Sequence length: Number of ranks in the scan sequence.
3990 * - Sequence direction: Unless specified in parameters, sequencer
3991 * scan direction is forward (from rank 1 to rank n).
3992 * Sequencer ranks are selected using
3993 * function "LL_ADC_REG_SetSequencerRanks()".
3994 * - For devices with sequencer not fully configurable
3995 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3996 * sequencer length and each rank affectation to a channel
3997 * are defined by channel number.
3998 * This function retrieves:
3999 * - Sequence length: Number of ranks in the scan sequence is
4000 * defined by number of channels set in the sequence,
4001 * rank of each channel is fixed by channel HW number.
4002 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4003 * - Sequence direction: Unless specified in parameters, sequencer
4004 * scan direction is forward (from lowest channel number to
4005 * highest channel number).
4006 * Sequencer ranks are selected using
4007 * function "LL_ADC_REG_SetSequencerChannels()".
4008 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4009 * ADC conversion on only 1 channel.
4010 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
4011 * @param ADCx ADC instance
4012 * @retval Returned value can be one of the following values:
4013 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4014 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4015 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4016 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4017 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4018 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4019 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4020 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4021 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4022 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4023 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4024 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4025 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4026 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4027 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4028 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4029 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)4030 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
4031 {
4032 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
4033 }
4034
4035 /**
4036 * @brief Set ADC group regular sequencer discontinuous mode:
4037 * sequence subdivided and scan conversions interrupted every selected
4038 * number of ranks.
4039 * @note It is not possible to enable both ADC group regular
4040 * continuous mode and sequencer discontinuous mode.
4041 * @note It is not possible to enable both ADC auto-injected mode
4042 * and ADC group regular sequencer discontinuous mode.
4043 * @note On this STM32 series, setting of this feature is conditioned to
4044 * ADC state:
4045 * ADC must be disabled or enabled without conversion on going
4046 * on group regular.
4047 * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
4048 * CFGR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
4049 * @param ADCx ADC instance
4050 * @param SeqDiscont This parameter can be one of the following values:
4051 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4052 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4053 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4054 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4055 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4056 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4057 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4058 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4059 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4060 * @retval None
4061 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4062 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4063 {
4064 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM, SeqDiscont);
4065 }
4066
4067 /**
4068 * @brief Get ADC group regular sequencer discontinuous mode:
4069 * sequence subdivided and scan conversions interrupted every selected
4070 * number of ranks.
4071 * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
4072 * CFGR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
4073 * @param ADCx ADC instance
4074 * @retval Returned value can be one of the following values:
4075 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4076 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4077 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4078 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4079 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4080 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4081 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4082 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4083 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4084 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)4085 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4086 {
4087 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM));
4088 }
4089
4090 /**
4091 * @brief Set ADC group regular sequence: channel on the selected
4092 * scan sequence rank.
4093 * @note This function performs configuration of:
4094 * - Channels ordering into each rank of scan sequence:
4095 * whatever channel can be placed into whatever rank.
4096 * @note On this STM32 series, ADC group regular sequencer is
4097 * fully configurable: sequencer length and each rank
4098 * affectation to a channel are configurable.
4099 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4100 * @note Depending on devices and packages, some channels may not be available.
4101 * Refer to device datasheet for channels availability.
4102 * @note On this STM32 series, to measure internal channels (VrefInt,
4103 * TempSensor, ...), measurement paths to internal channels must be
4104 * enabled separately.
4105 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4106 * @note On this STM32 series, setting of this feature is conditioned to
4107 * ADC state:
4108 * ADC must be disabled or enabled without conversion on going
4109 * on group regular.
4110 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
4111 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
4112 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
4113 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
4114 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
4115 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
4116 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
4117 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
4118 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
4119 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
4120 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
4121 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
4122 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
4123 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
4124 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
4125 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
4126 * @param ADCx ADC instance
4127 * @param Rank This parameter can be one of the following values:
4128 * @arg @ref LL_ADC_REG_RANK_1
4129 * @arg @ref LL_ADC_REG_RANK_2
4130 * @arg @ref LL_ADC_REG_RANK_3
4131 * @arg @ref LL_ADC_REG_RANK_4
4132 * @arg @ref LL_ADC_REG_RANK_5
4133 * @arg @ref LL_ADC_REG_RANK_6
4134 * @arg @ref LL_ADC_REG_RANK_7
4135 * @arg @ref LL_ADC_REG_RANK_8
4136 * @arg @ref LL_ADC_REG_RANK_9
4137 * @arg @ref LL_ADC_REG_RANK_10
4138 * @arg @ref LL_ADC_REG_RANK_11
4139 * @arg @ref LL_ADC_REG_RANK_12
4140 * @arg @ref LL_ADC_REG_RANK_13
4141 * @arg @ref LL_ADC_REG_RANK_14
4142 * @arg @ref LL_ADC_REG_RANK_15
4143 * @arg @ref LL_ADC_REG_RANK_16
4144 * @param Channel This parameter can be one of the following values:
4145 * @arg @ref LL_ADC_CHANNEL_0
4146 * @arg @ref LL_ADC_CHANNEL_1
4147 * @arg @ref LL_ADC_CHANNEL_2
4148 * @arg @ref LL_ADC_CHANNEL_3
4149 * @arg @ref LL_ADC_CHANNEL_4
4150 * @arg @ref LL_ADC_CHANNEL_5
4151 * @arg @ref LL_ADC_CHANNEL_6
4152 * @arg @ref LL_ADC_CHANNEL_7
4153 * @arg @ref LL_ADC_CHANNEL_8
4154 * @arg @ref LL_ADC_CHANNEL_9
4155 * @arg @ref LL_ADC_CHANNEL_10
4156 * @arg @ref LL_ADC_CHANNEL_11
4157 * @arg @ref LL_ADC_CHANNEL_12
4158 * @arg @ref LL_ADC_CHANNEL_13
4159 * @arg @ref LL_ADC_CHANNEL_14
4160 * @arg @ref LL_ADC_CHANNEL_15
4161 * @arg @ref LL_ADC_CHANNEL_16
4162 * @arg @ref LL_ADC_CHANNEL_17
4163 * @arg @ref LL_ADC_CHANNEL_18
4164 * @arg @ref LL_ADC_CHANNEL_19
4165 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4166 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
4167 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
4168 *
4169 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
4170 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
4171 * @retval None
4172 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4173 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4174 {
4175 /* Set bits with content of parameter "Channel" with bits position */
4176 /* in register and register position depending on parameter "Rank". */
4177 /* Parameters "Rank" and "Channel" are used with masks because containing */
4178 /* other bits reserved for other purpose. */
4179 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
4180 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4181
4182 MODIFY_REG(*preg,
4183 ADC_CHANNEL_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4184 (Channel & ADC_CHANNEL_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4185 }
4186
4187 /**
4188 * @brief Get ADC group regular sequence: channel on the selected
4189 * scan sequence rank.
4190 * @note On this STM32 series, ADC group regular sequencer is
4191 * fully configurable: sequencer length and each rank
4192 * affectation to a channel are configurable.
4193 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4194 * @note Depending on devices and packages, some channels may not be available.
4195 * Refer to device datasheet for channels availability.
4196 * @note Usage of the returned channel number:
4197 * - To reinject this channel into another function LL_ADC_xxx:
4198 * the returned channel number is only partly formatted on definition
4199 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4200 * with parts of literals LL_ADC_CHANNEL_x or using
4201 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4202 * Then the selected literal LL_ADC_CHANNEL_x can be used
4203 * as parameter for another function.
4204 * - To get the channel number in decimal format:
4205 * process the returned value with the helper macro
4206 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4207 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
4208 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
4209 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
4210 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
4211 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
4212 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
4213 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
4214 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
4215 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
4216 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
4217 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
4218 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
4219 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
4220 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
4221 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
4222 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4223 * @param ADCx ADC instance
4224 * @param Rank This parameter can be one of the following values:
4225 * @arg @ref LL_ADC_REG_RANK_1
4226 * @arg @ref LL_ADC_REG_RANK_2
4227 * @arg @ref LL_ADC_REG_RANK_3
4228 * @arg @ref LL_ADC_REG_RANK_4
4229 * @arg @ref LL_ADC_REG_RANK_5
4230 * @arg @ref LL_ADC_REG_RANK_6
4231 * @arg @ref LL_ADC_REG_RANK_7
4232 * @arg @ref LL_ADC_REG_RANK_8
4233 * @arg @ref LL_ADC_REG_RANK_9
4234 * @arg @ref LL_ADC_REG_RANK_10
4235 * @arg @ref LL_ADC_REG_RANK_11
4236 * @arg @ref LL_ADC_REG_RANK_12
4237 * @arg @ref LL_ADC_REG_RANK_13
4238 * @arg @ref LL_ADC_REG_RANK_14
4239 * @arg @ref LL_ADC_REG_RANK_15
4240 * @arg @ref LL_ADC_REG_RANK_16
4241 * @retval Returned value can be one of the following values:
4242 * @arg @ref LL_ADC_CHANNEL_0
4243 * @arg @ref LL_ADC_CHANNEL_1
4244 * @arg @ref LL_ADC_CHANNEL_2
4245 * @arg @ref LL_ADC_CHANNEL_3
4246 * @arg @ref LL_ADC_CHANNEL_4
4247 * @arg @ref LL_ADC_CHANNEL_5
4248 * @arg @ref LL_ADC_CHANNEL_6
4249 * @arg @ref LL_ADC_CHANNEL_7
4250 * @arg @ref LL_ADC_CHANNEL_8
4251 * @arg @ref LL_ADC_CHANNEL_9
4252 * @arg @ref LL_ADC_CHANNEL_10
4253 * @arg @ref LL_ADC_CHANNEL_11
4254 * @arg @ref LL_ADC_CHANNEL_12
4255 * @arg @ref LL_ADC_CHANNEL_13
4256 * @arg @ref LL_ADC_CHANNEL_14
4257 * @arg @ref LL_ADC_CHANNEL_15
4258 * @arg @ref LL_ADC_CHANNEL_16
4259 * @arg @ref LL_ADC_CHANNEL_17
4260 * @arg @ref LL_ADC_CHANNEL_18
4261 * @arg @ref LL_ADC_CHANNEL_19
4262 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
4263 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(3)
4264 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(3)
4265 *
4266 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
4267 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
4268 * (3) For ADC channel read back from ADC register,
4269 * comparison with internal channel parameter to be done
4270 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4271 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4272 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4273 {
4274 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
4275 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4276
4277 return (uint32_t)((READ_BIT(*preg,
4278 ADC_CHANNEL_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4279 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4280 );
4281 }
4282
4283 /**
4284 * @brief Set ADC Channel Preselection to LL_ADC_CHANNEL_x, x = 0 to 19.
4285 * @note This function set the the value for the channel preselection register
4286 * corresponding to ADC channel to be selected.
4287 * @rmtoll PCSEL PCSEL LL_ADC_SetChannelPreselection
4288 * @param ADCx ADC instance.
4289 * @param Channel This parameter can be one of the following values:
4290 * @arg @ref LL_ADC_CHANNEL_0
4291 * @arg @ref LL_ADC_CHANNEL_1
4292 * @arg @ref LL_ADC_CHANNEL_2
4293 * @arg @ref LL_ADC_CHANNEL_3
4294 * @arg @ref LL_ADC_CHANNEL_4
4295 * @arg @ref LL_ADC_CHANNEL_5
4296 * @arg @ref LL_ADC_CHANNEL_6
4297 * @arg @ref LL_ADC_CHANNEL_7
4298 * @arg @ref LL_ADC_CHANNEL_8
4299 * @arg @ref LL_ADC_CHANNEL_9
4300 * @arg @ref LL_ADC_CHANNEL_10
4301 * @arg @ref LL_ADC_CHANNEL_11
4302 * @arg @ref LL_ADC_CHANNEL_12
4303 * @arg @ref LL_ADC_CHANNEL_13
4304 * @arg @ref LL_ADC_CHANNEL_14
4305 * @arg @ref LL_ADC_CHANNEL_15
4306 * @arg @ref LL_ADC_CHANNEL_16
4307 * @arg @ref LL_ADC_CHANNEL_17
4308 * @arg @ref LL_ADC_CHANNEL_18
4309 * @arg @ref LL_ADC_CHANNEL_19
4310 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4311 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
4312 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
4313 *
4314 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
4315 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
4316 * @retval None
4317 */
LL_ADC_SetChannelPreselection(ADC_TypeDef * ADCx,uint32_t Channel)4318 __STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
4319 {
4320 __IO uint32_t channel_preselectione = READ_REG(ADCx->PCSEL);
4321 WRITE_REG(ADCx->PCSEL,
4322 channel_preselectione | (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)Channel) & 0x1FUL)));
4323 }
4324
4325 /**
4326 * @brief Get ADC Channel Preselection register value.
4327 * @note This function set the the value for the channel preselection register
4328 * corresponding to ADC channel to be selected.
4329 * @rmtoll PCSEL PCSEL LL_ADC_GetChannelPreselection
4330 * @param ADCx ADC instance.
4331 *
4332 * @retval Returned decimal value that can correspend to one or multiple channels:
4333 */
LL_ADC_GetChannelPreselection(const ADC_TypeDef * ADCx)4334 __STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *ADCx)
4335 {
4336 return (uint32_t)(READ_BIT(ADCx->PCSEL, ADC_PCSEL_PCSEL));
4337 }
4338
4339 /**
4340 * @brief Set ADC continuous conversion mode on ADC group regular.
4341 * @note Description of ADC continuous conversion mode:
4342 * - single mode: one conversion per trigger
4343 * - continuous mode: after the first trigger, following
4344 * conversions launched successively automatically.
4345 * @note It is not possible to enable both ADC group regular
4346 * continuous mode and sequencer discontinuous mode.
4347 * @note On this STM32 series, setting of this feature is conditioned to
4348 * ADC state:
4349 * ADC must be disabled or enabled without conversion on going
4350 * on group regular.
4351 * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
4352 * @param ADCx ADC instance
4353 * @param Continuous This parameter can be one of the following values:
4354 * @arg @ref LL_ADC_REG_CONV_SINGLE
4355 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4356 * @retval None
4357 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)4358 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4359 {
4360 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
4361 }
4362
4363 /**
4364 * @brief Get ADC continuous conversion mode on ADC group regular.
4365 * @note Description of ADC continuous conversion mode:
4366 * - single mode: one conversion per trigger
4367 * - continuous mode: after the first trigger, following
4368 * conversions launched successively automatically.
4369 * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
4370 * @param ADCx ADC instance
4371 * @retval Returned value can be one of the following values:
4372 * @arg @ref LL_ADC_REG_CONV_SINGLE
4373 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4374 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)4375 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
4376 {
4377 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
4378 }
4379
4380 /**
4381 * @brief Set ADC data transfer mode
4382 * @note Conversion data can be either:
4383 * - Available in Data Register
4384 * - Transferred by DMA in one shot mode
4385 * - Transferred by DMA in circular mode
4386 * - Transferred to MDF data register
4387 * @rmtoll CFGR1 DMNGT LL_ADC_REG_SetDataTransferMode
4388 * @param ADCx ADC instance
4389 * @param DataTransferMode Select Data Management configuration
4390 * @arg @ref LL_ADC_REG_DR_TRANSFER
4391 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4392 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4393 * @arg @ref LL_ADC_REG_MDF_TRANSFER
4394 * @retval None
4395 */
LL_ADC_REG_SetDataTransferMode(ADC_TypeDef * ADCx,uint32_t DataTransferMode)4396 __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
4397 {
4398 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMNGT, DataTransferMode);
4399 }
4400
4401 /**
4402 * @brief Get ADC data transfer mode
4403 * @note Conversion data can be either:
4404 * - Available in Data Register
4405 * - Transferred by DMA in one shot mode
4406 * - Transferred by DMA in circular mode
4407 * - Transferred to DFSDM data register
4408 * @rmtoll CFGR1 DMNGT LL_ADC_REG_GetDataTransferMode
4409 * @param ADCx ADC instance
4410 * @retval Returned value can be one of the following values:
4411 * @arg @ref LL_ADC_REG_DR_TRANSFER
4412 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4413 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4414 * @arg @ref LL_ADC_REG_MDF_TRANSFER
4415 */
LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef * ADCx)4416 __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx)
4417 {
4418 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMNGT));
4419 }
4420
4421 /**
4422 * @brief Set ADC group regular behavior in case of overrun:
4423 * data preserved or overwritten.
4424 * @note Compatibility with devices without feature overrun:
4425 * other devices without this feature have a behavior
4426 * equivalent to data overwritten.
4427 * The default setting of overrun is data preserved.
4428 * Therefore, for compatibility with all devices, parameter
4429 * overrun should be set to data overwritten.
4430 * @note On this STM32 series, setting of this feature is conditioned to
4431 * ADC state:
4432 * ADC must be disabled or enabled without conversion on going
4433 * on group regular.
4434 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
4435 * @param ADCx ADC instance
4436 * @param Overrun This parameter can be one of the following values:
4437 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4438 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4439 * @retval None
4440 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)4441 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4442 {
4443 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
4444 }
4445
4446 /**
4447 * @brief Get ADC group regular behavior in case of overrun:
4448 * data preserved or overwritten.
4449 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
4450 * @param ADCx ADC instance
4451 * @retval Returned value can be one of the following values:
4452 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4453 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4454 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)4455 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
4456 {
4457 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
4458 }
4459
4460 /**
4461 * @}
4462 */
4463
4464 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
4465 * @{
4466 */
4467
4468 /**
4469 * @brief Set ADC group injected conversion trigger source:
4470 * internal (SW start) or from external peripheral (timer event,
4471 * external interrupt line).
4472 * @note On this STM32 series, setting trigger source to external trigger
4473 * also set trigger polarity to rising edge
4474 * (default setting for compatibility with some ADC on other
4475 * STM32 series having this setting set by HW default value).
4476 * In case of need to modify trigger edge, use
4477 * function @ref LL_ADC_INJ_SetTriggerEdge().
4478 * @note Availability of parameters of trigger sources from timer
4479 * depends on timers availability on the selected device.
4480 * @note On this STM32 series, setting of this feature is conditioned to
4481 * ADC state:
4482 * ADC must not be disabled. Can be enabled with or without conversion
4483 * on going on either groups regular or injected.
4484 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
4485 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
4486 * @param ADCx ADC instance
4487 * @param TriggerSource This parameter can be one of the following values:
4488 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4489 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4490 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4491 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4492 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4493 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4494 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4495 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4496 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4497 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4498 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4499 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4500 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
4501 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4502 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
4503 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4504 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4505 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH2
4506 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
4507 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM12_TRGO
4508 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4509 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM18_TRGO
4510 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
4511 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
4512 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH2
4513 * @retval None
4514 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)4515 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4516 {
4517 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4518 }
4519
4520 /**
4521 * @brief Get ADC group injected conversion trigger source:
4522 * internal (SW start) or from external peripheral (timer event,
4523 * external interrupt line).
4524 * @note To determine whether group injected trigger source is
4525 * internal (SW start) or external, without detail
4526 * of which peripheral is selected as external trigger,
4527 * (equivalent to
4528 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
4529 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
4530 * @note Availability of parameters of trigger sources from timer
4531 * depends on timers availability on the selected device.
4532 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
4533 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
4534 * @param ADCx ADC instance
4535 * @retval Returned value can be one of the following values:
4536 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4537 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4538 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4539 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4540 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4541 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4542 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4543 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4544 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4545 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4546 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4547 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4548 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
4549 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4550 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
4551 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4552 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4553 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH2
4554 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
4555 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM12_TRGO
4556 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4557 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM18_TRGO
4558 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
4559 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
4560 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH2
4561 */
LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef * ADCx)4562 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
4563 {
4564 __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4565
4566 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4567 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4568 uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4569
4570 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4571 /* to match with triggers literals definition. */
4572 return ((trigger_source
4573 & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
4574 | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
4575 );
4576 }
4577
4578 /**
4579 * @brief Get ADC group injected conversion trigger source internal (SW start)
4580 or external
4581 * @note In case of group injected trigger source set to external trigger,
4582 * to determine which peripheral is selected as external trigger,
4583 * use function @ref LL_ADC_INJ_GetTriggerSource.
4584 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4585 * @param ADCx ADC instance
4586 * @retval Value "0" if trigger source external trigger
4587 * Value "1" if trigger source SW start.
4588 */
LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)4589 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4590 {
4591 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4592 }
4593
4594 /**
4595 * @brief Set ADC group injected conversion trigger polarity.
4596 * Applicable only for trigger source set to external trigger.
4597 * @note On this STM32 series, setting of this feature is conditioned to
4598 * ADC state:
4599 * ADC must not be disabled. Can be enabled with or without conversion
4600 * on going on either groups regular or injected.
4601 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4602 * @param ADCx ADC instance
4603 * @param ExternalTriggerEdge This parameter can be one of the following values:
4604 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4605 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4606 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4607 * @retval None
4608 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4609 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4610 {
4611 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4612 }
4613
4614 /**
4615 * @brief Get ADC group injected conversion trigger polarity.
4616 * Applicable only for trigger source set to external trigger.
4617 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4618 * @param ADCx ADC instance
4619 * @retval Returned value can be one of the following values:
4620 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4621 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4622 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4623 */
LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef * ADCx)4624 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
4625 {
4626 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4627 }
4628
4629 /**
4630 * @brief Set ADC group injected sequencer length and scan direction.
4631 * @note This function performs configuration of:
4632 * - Sequence length: Number of ranks in the scan sequence.
4633 * - Sequence direction: Unless specified in parameters, sequencer
4634 * scan direction is forward (from rank 1 to rank n).
4635 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4636 * ADC conversion on only 1 channel.
4637 * @note On this STM32 series, setting of this feature is conditioned to
4638 * ADC state:
4639 * ADC must not be disabled. Can be enabled with or without conversion
4640 * on going on either groups regular or injected.
4641 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4642 * @param ADCx ADC instance
4643 * @param SequencerNbRanks This parameter can be one of the following values:
4644 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4645 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4646 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4647 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4648 * @retval None
4649 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4650 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4651 {
4652 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4653 }
4654
4655 /**
4656 * @brief Get ADC group injected sequencer length and scan direction.
4657 * @note This function retrieves:
4658 * - Sequence length: Number of ranks in the scan sequence.
4659 * - Sequence direction: Unless specified in parameters, sequencer
4660 * scan direction is forward (from rank 1 to rank n).
4661 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4662 * ADC conversion on only 1 channel.
4663 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4664 * @param ADCx ADC instance
4665 * @retval Returned value can be one of the following values:
4666 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4667 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4668 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4669 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4670 */
LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef * ADCx)4671 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
4672 {
4673 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4674 }
4675
4676 /**
4677 * @brief Set ADC group injected sequencer discontinuous mode:
4678 * sequence subdivided and scan conversions interrupted every selected
4679 * number of ranks.
4680 * @note It is not possible to enable both ADC group injected
4681 * auto-injected mode and sequencer discontinuous mode.
4682 * @rmtoll CFGR1 JDISCEN LL_ADC_INJ_SetSequencerDiscont
4683 * @param ADCx ADC instance
4684 * @param SeqDiscont This parameter can be one of the following values:
4685 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4686 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4687 * @retval None
4688 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4689 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4690 {
4691 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JDISCEN, SeqDiscont);
4692 }
4693
4694 /**
4695 * @brief Get ADC group injected sequencer discontinuous mode:
4696 * sequence subdivided and scan conversions interrupted every selected
4697 * number of ranks.
4698 * @rmtoll CFGR1 JDISCEN LL_ADC_INJ_GetSequencerDiscont
4699 * @param ADCx ADC instance
4700 * @retval Returned value can be one of the following values:
4701 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4702 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4703 */
LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef * ADCx)4704 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4705 {
4706 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JDISCEN));
4707 }
4708
4709 /**
4710 * @brief Set ADC group injected sequence: channel on the selected
4711 * sequence rank.
4712 * @note Depending on devices and packages, some channels may not be available.
4713 * Refer to device datasheet for channels availability.
4714 * @note On this STM32 series, to measure internal channels (VrefInt,
4715 * TempSensor, ...), measurement paths to internal channels must be
4716 * enabled separately.
4717 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4718 * @note On this STM32 series, setting of this feature is conditioned to
4719 * ADC state:
4720 * ADC must not be disabled. Can be enabled with or without conversion
4721 * on going on either groups regular or injected.
4722 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4723 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4724 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4725 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4726 * @param ADCx ADC instance
4727 * @param Rank This parameter can be one of the following values:
4728 * @arg @ref LL_ADC_INJ_RANK_1
4729 * @arg @ref LL_ADC_INJ_RANK_2
4730 * @arg @ref LL_ADC_INJ_RANK_3
4731 * @arg @ref LL_ADC_INJ_RANK_4
4732 * @param Channel This parameter can be one of the following values:
4733 * @arg @ref LL_ADC_CHANNEL_0
4734 * @arg @ref LL_ADC_CHANNEL_1
4735 * @arg @ref LL_ADC_CHANNEL_2
4736 * @arg @ref LL_ADC_CHANNEL_3
4737 * @arg @ref LL_ADC_CHANNEL_4
4738 * @arg @ref LL_ADC_CHANNEL_5
4739 * @arg @ref LL_ADC_CHANNEL_6
4740 * @arg @ref LL_ADC_CHANNEL_7
4741 * @arg @ref LL_ADC_CHANNEL_8
4742 * @arg @ref LL_ADC_CHANNEL_9
4743 * @arg @ref LL_ADC_CHANNEL_10
4744 * @arg @ref LL_ADC_CHANNEL_11
4745 * @arg @ref LL_ADC_CHANNEL_12
4746 * @arg @ref LL_ADC_CHANNEL_13
4747 * @arg @ref LL_ADC_CHANNEL_14
4748 * @arg @ref LL_ADC_CHANNEL_15
4749 * @arg @ref LL_ADC_CHANNEL_16
4750 * @arg @ref LL_ADC_CHANNEL_17
4751 * @arg @ref LL_ADC_CHANNEL_18
4752 * @arg @ref LL_ADC_CHANNEL_19
4753 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4754 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
4755 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
4756 *
4757 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
4758 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
4759 * @retval None
4760 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4761 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4762 {
4763 /* Set bits with content of parameter "Channel" with bits position */
4764 /* in register depending on parameter "Rank". */
4765 /* Parameters "Rank" and "Channel" are used with masks because containing */
4766 /* other bits reserved for other purpose. */
4767 MODIFY_REG(ADCx->JSQR,
4768 (ADC_CHANNEL_NUMBER_MASK >> ADC_AWD_CHANNEL_NUMBER_BITOFFSET_POS)
4769 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4770 (Channel & ADC_CHANNEL_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4771 }
4772
4773 /**
4774 * @brief Get ADC group injected sequence: channel on the selected
4775 * sequence rank.
4776 * @note Depending on devices and packages, some channels may not be available.
4777 * Refer to device datasheet for channels availability.
4778 * @note Usage of the returned channel number:
4779 * - To reinject this channel into another function LL_ADC_xxx:
4780 * the returned channel number is only partly formatted on definition
4781 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4782 * with parts of literals LL_ADC_CHANNEL_x or using
4783 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4784 * Then the selected literal LL_ADC_CHANNEL_x can be used
4785 * as parameter for another function.
4786 * - To get the channel number in decimal format:
4787 * process the returned value with the helper macro
4788 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4789 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4790 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4791 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4792 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4793 * @param ADCx ADC instance
4794 * @param Rank This parameter can be one of the following values:
4795 * @arg @ref LL_ADC_INJ_RANK_1
4796 * @arg @ref LL_ADC_INJ_RANK_2
4797 * @arg @ref LL_ADC_INJ_RANK_3
4798 * @arg @ref LL_ADC_INJ_RANK_4
4799 * @retval Returned value can be one of the following values:
4800 * @arg @ref LL_ADC_CHANNEL_0
4801 * @arg @ref LL_ADC_CHANNEL_1
4802 * @arg @ref LL_ADC_CHANNEL_2
4803 * @arg @ref LL_ADC_CHANNEL_3
4804 * @arg @ref LL_ADC_CHANNEL_4
4805 * @arg @ref LL_ADC_CHANNEL_5
4806 * @arg @ref LL_ADC_CHANNEL_6
4807 * @arg @ref LL_ADC_CHANNEL_7
4808 * @arg @ref LL_ADC_CHANNEL_8
4809 * @arg @ref LL_ADC_CHANNEL_9
4810 * @arg @ref LL_ADC_CHANNEL_10
4811 * @arg @ref LL_ADC_CHANNEL_11
4812 * @arg @ref LL_ADC_CHANNEL_12
4813 * @arg @ref LL_ADC_CHANNEL_13
4814 * @arg @ref LL_ADC_CHANNEL_14
4815 * @arg @ref LL_ADC_CHANNEL_15
4816 * @arg @ref LL_ADC_CHANNEL_16
4817 * @arg @ref LL_ADC_CHANNEL_17
4818 * @arg @ref LL_ADC_CHANNEL_18
4819 * @arg @ref LL_ADC_CHANNEL_19
4820 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
4821 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(3)
4822 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(3)
4823 *
4824 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
4825 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
4826 * (3) For ADC channel read back from ADC register,
4827 * comparison with internal channel parameter to be done
4828 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4829 */
LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4830 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4831 {
4832 return (uint32_t)((READ_BIT(ADCx->JSQR,
4833 ADC_CHANNEL_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4834 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4835 );
4836 }
4837
4838 /**
4839 * @brief Set ADC group injected conversion trigger:
4840 * independent or from ADC group regular.
4841 * @note This mode can be used to extend number of data registers
4842 * updated after one ADC conversion trigger and with data
4843 * permanently kept (not erased by successive conversions of scan of
4844 * ADC sequencer ranks), up to 5 data registers:
4845 * 1 data register on ADC group regular, 4 data registers
4846 * on ADC group injected.
4847 * @note If ADC group injected injected trigger source is set to an
4848 * external trigger, this feature must be must be set to
4849 * independent trigger.
4850 * ADC group injected automatic trigger is compliant only with
4851 * group injected trigger source set to SW start, without any
4852 * further action on ADC group injected conversion start or stop:
4853 * in this case, ADC group injected is controlled only
4854 * from ADC group regular.
4855 * @note It is not possible to enable both ADC group injected
4856 * auto-injected mode and sequencer discontinuous mode.
4857 * @note On this STM32 series, setting of this feature is conditioned to
4858 * ADC state:
4859 * ADC must be disabled or enabled without conversion on going
4860 * on either groups regular or injected.
4861 * @rmtoll CFGR1 JAUTO LL_ADC_INJ_SetTrigAuto
4862 * @param ADCx ADC instance
4863 * @param TrigAuto This parameter can be one of the following values:
4864 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4865 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4866 * @retval None
4867 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)4868 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4869 {
4870 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JAUTO, TrigAuto);
4871 }
4872
4873 /**
4874 * @brief Get ADC group injected conversion trigger:
4875 * independent or from ADC group regular.
4876 * @rmtoll CFGR1 JAUTO LL_ADC_INJ_GetTrigAuto
4877 * @param ADCx ADC instance
4878 * @retval Returned value can be one of the following values:
4879 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4880 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4881 */
LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef * ADCx)4882 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
4883 {
4884 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JAUTO));
4885 }
4886
4887 /**
4888 * @}
4889 */
4890
4891 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
4892 * @{
4893 */
4894
4895 /**
4896 * @brief Set sampling time of the selected ADC channel
4897 * Unit: ADC clock cycles.
4898 * @note On this device, sampling time is on channel scope: independently
4899 * of channel mapped on ADC group regular or injected.
4900 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
4901 * converted:
4902 * sampling time constraints must be respected (sampling time can be
4903 * adjusted in function of ADC clock frequency and sampling time
4904 * setting).
4905 * Refer to device datasheet for timings values (parameters TS_vrefint,
4906 * TS_temp, ...).
4907 * @note Conversion time is the addition of sampling time and processing time.
4908 * On this STM32 series, ADC processing time is:
4909 * - 13.5 ADC clock cycles at ADC resolution 12 bits
4910 * - 11.5 ADC clock cycles at ADC resolution 10 bits
4911 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4912 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4913 * @note In case of ADC conversion of internal channel (VrefInt,
4914 * temperature sensor, ...), a sampling time minimum value
4915 * is required.
4916 * Refer to device datasheet.
4917 * @note On this STM32 series, setting of this feature is conditioned to
4918 * ADC state:
4919 * ADC must be disabled or enabled without conversion on going
4920 * on either groups regular or injected.
4921 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
4922 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
4923 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
4924 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
4925 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
4926 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
4927 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
4928 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
4929 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
4930 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
4931 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
4932 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
4933 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
4934 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
4935 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
4936 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
4937 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
4938 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
4939 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
4940 * @param ADCx ADC instance
4941 * @param Channel This parameter can be one of the following values:
4942 * @arg @ref LL_ADC_CHANNEL_0
4943 * @arg @ref LL_ADC_CHANNEL_1
4944 * @arg @ref LL_ADC_CHANNEL_2
4945 * @arg @ref LL_ADC_CHANNEL_3
4946 * @arg @ref LL_ADC_CHANNEL_4
4947 * @arg @ref LL_ADC_CHANNEL_5
4948 * @arg @ref LL_ADC_CHANNEL_6
4949 * @arg @ref LL_ADC_CHANNEL_7
4950 * @arg @ref LL_ADC_CHANNEL_8
4951 * @arg @ref LL_ADC_CHANNEL_9
4952 * @arg @ref LL_ADC_CHANNEL_10
4953 * @arg @ref LL_ADC_CHANNEL_11
4954 * @arg @ref LL_ADC_CHANNEL_12
4955 * @arg @ref LL_ADC_CHANNEL_13
4956 * @arg @ref LL_ADC_CHANNEL_14
4957 * @arg @ref LL_ADC_CHANNEL_15
4958 * @arg @ref LL_ADC_CHANNEL_16
4959 * @arg @ref LL_ADC_CHANNEL_17
4960 * @arg @ref LL_ADC_CHANNEL_18
4961 * @arg @ref LL_ADC_CHANNEL_19
4962 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4963 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
4964 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
4965 *
4966 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
4967 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
4968 * @param SamplingTime This parameter can be one of the following values:
4969 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
4970 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
4971 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
4972 * @arg @ref LL_ADC_SAMPLINGTIME_11CYCLES_5
4973 * @arg @ref LL_ADC_SAMPLINGTIME_23CYCLES_5
4974 * @arg @ref LL_ADC_SAMPLINGTIME_46CYCLES_5
4975 * @arg @ref LL_ADC_SAMPLINGTIME_246CYCLES_5
4976 * @arg @ref LL_ADC_SAMPLINGTIME_1499CYCLES_5
4977 * @retval None
4978 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)4979 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
4980 {
4981 /* Set bits with content of parameter "SamplingTime" with bits position */
4982 /* in register and register position depending on parameter "Channel". */
4983 /* Parameter "Channel" is used with masks because containing */
4984 /* other bits reserved for other purpose. */
4985 const uint32_t iChannel = __ADC_CHANNEL_INDEX(Channel);
4986 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
4987 ((ADC_CHANNEL_LUT[iChannel]
4988 & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
4989 MODIFY_REG(*preg,
4990 ADC_SMPR1_SMP0 << ((ADC_CHANNEL_LUT[iChannel] & ADC_CHANNEL_SMPx_BITOFFSET_MASK)
4991 >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
4992 SamplingTime << ((ADC_CHANNEL_LUT[iChannel] & ADC_CHANNEL_SMPx_BITOFFSET_MASK)
4993 >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
4994 }
4995
4996 /**
4997 * @brief Get sampling time of the selected ADC channel
4998 * Unit: ADC clock cycles.
4999 * @note On this device, sampling time is on channel scope: independently
5000 * of channel mapped on ADC group regular or injected.
5001 * @note Conversion time is the addition of sampling time and processing time.
5002 * On this STM32 series, ADC processing time is:
5003 * - 13.5 ADC clock cycles at ADC resolution 12 bits
5004 * - 11.5 ADC clock cycles at ADC resolution 10 bits
5005 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5006 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5007 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
5008 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
5009 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
5010 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
5011 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
5012 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
5013 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
5014 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
5015 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
5016 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
5017 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
5018 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
5019 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
5020 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
5021 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
5022 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
5023 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
5024 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
5025 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
5026 * @param ADCx ADC instance
5027 * @param Channel This parameter can be one of the following values:
5028 * @arg @ref LL_ADC_CHANNEL_0
5029 * @arg @ref LL_ADC_CHANNEL_1
5030 * @arg @ref LL_ADC_CHANNEL_2
5031 * @arg @ref LL_ADC_CHANNEL_3
5032 * @arg @ref LL_ADC_CHANNEL_4
5033 * @arg @ref LL_ADC_CHANNEL_5
5034 * @arg @ref LL_ADC_CHANNEL_6
5035 * @arg @ref LL_ADC_CHANNEL_7
5036 * @arg @ref LL_ADC_CHANNEL_8
5037 * @arg @ref LL_ADC_CHANNEL_9
5038 * @arg @ref LL_ADC_CHANNEL_10
5039 * @arg @ref LL_ADC_CHANNEL_11
5040 * @arg @ref LL_ADC_CHANNEL_12
5041 * @arg @ref LL_ADC_CHANNEL_13
5042 * @arg @ref LL_ADC_CHANNEL_14
5043 * @arg @ref LL_ADC_CHANNEL_15
5044 * @arg @ref LL_ADC_CHANNEL_16
5045 * @arg @ref LL_ADC_CHANNEL_17
5046 * @arg @ref LL_ADC_CHANNEL_18
5047 * @arg @ref LL_ADC_CHANNEL_19
5048 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
5049 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(3)
5050 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(3)
5051 *
5052 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
5053 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
5054 * (3) For ADC channel read back from ADC register,
5055 * comparison with internal channel parameter to be done
5056 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
5057 * @retval Returned value can be one of the following values:
5058 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
5059 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
5060 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5061 * @arg @ref LL_ADC_SAMPLINGTIME_11CYCLES_5
5062 * @arg @ref LL_ADC_SAMPLINGTIME_23CYCLES_5
5063 * @arg @ref LL_ADC_SAMPLINGTIME_46CYCLES_5
5064 * @arg @ref LL_ADC_SAMPLINGTIME_246CYCLES_5
5065 * @arg @ref LL_ADC_SAMPLINGTIME_1499CYCLES_5
5066 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)5067 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
5068 {
5069 const uint32_t iChannel = __ADC_CHANNEL_INDEX(Channel);
5070 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
5071 ((ADC_CHANNEL_LUT[iChannel]
5072 & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5073 return (uint32_t)(READ_BIT(*preg,
5074 ADC_SMPR1_SMP0
5075 << ((ADC_CHANNEL_LUT[iChannel]
5076 & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5077 >> ((ADC_CHANNEL_LUT[iChannel] & ADC_CHANNEL_SMPx_BITOFFSET_MASK)
5078 >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5079 );
5080 }
5081
5082 /**
5083 * @brief Set mode single-ended or differential input of the selected
5084 * ADC channel.
5085 * @note Channel ending is on channel scope: independently of channel mapped
5086 * on ADC group regular or injected.
5087 * In differential mode: Differential measurement is carried out
5088 * between the selected channel (positive input) and another
5089 * channel (negative input).
5090 * Only selected channel has to be configured, the other channel
5091 * is configured automatically.
5092 * @note The selected channel and the other other channel have
5093 * not necessarily contiguous channel number.
5094 * To get the other channel number, refer to reference manual
5095 * in section of ADC instance connectivity.
5096 * @note Refer to Reference Manual to ensure the selected channel is
5097 * available in differential mode.
5098 * For example, internal channels (VrefInt, TempSensor, ...) are
5099 * not available in differential mode.
5100 * @note When configuring a channel 'inp' in differential mode,
5101 * the channel 'inn' is not usable separately.
5102 * @note Some channels are internally fixed to single-ended inputs
5103 * configuration, refer to device datasheet for more details.
5104 * @note For ADC channels configured in differential mode, both inputs
5105 * should be biased at (Vref+)/2 +/-200mV.
5106 * (Vref+ is the analog voltage reference)
5107 * @note On this STM32 series, setting of this feature is conditioned to
5108 * ADC state:
5109 * ADC must be ADC disabled.
5110 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
5111 * @param ADCx ADC instance
5112 * @param Channel This parameter can be one of the following values:
5113 * @arg @ref LL_ADC_CHANNEL_1
5114 * @arg @ref LL_ADC_CHANNEL_2
5115 * @arg @ref LL_ADC_CHANNEL_3
5116 * @arg @ref LL_ADC_CHANNEL_4
5117 * @arg @ref LL_ADC_CHANNEL_5
5118 * @arg @ref LL_ADC_CHANNEL_6
5119 * @arg @ref LL_ADC_CHANNEL_7
5120 * @arg @ref LL_ADC_CHANNEL_8
5121 * @arg @ref LL_ADC_CHANNEL_9
5122 * @arg @ref LL_ADC_CHANNEL_10
5123 * @arg @ref LL_ADC_CHANNEL_11
5124 * @arg @ref LL_ADC_CHANNEL_12
5125 * @arg @ref LL_ADC_CHANNEL_13
5126 * @arg @ref LL_ADC_CHANNEL_14
5127 * @arg @ref LL_ADC_CHANNEL_15
5128 * @arg @ref LL_ADC_CHANNEL_16
5129 * @arg @ref LL_ADC_CHANNEL_17
5130 * @arg @ref LL_ADC_CHANNEL_18
5131 * @arg @ref LL_ADC_CHANNEL_19
5132 * @param SingleDiff This parameter can be a combination of the following values:
5133 * @arg @ref LL_ADC_SINGLE_ENDED
5134 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5135 * @retval None
5136 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)5137 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5138 {
5139 /* Bits of channels in single or differential mode are set only for */
5140 /* differential mode (for single mode, mask of bits allowed to be set is */
5141 /* shifted out of range of bits of channels in single or differential mode. */
5142 const uint32_t iChannel = __ADC_CHANNEL_INDEX(Channel);
5143 MODIFY_REG(ADCx->DIFSEL,
5144 ADC_CHANNEL_LUT[iChannel] & ADC_SINGLEDIFF_CHANNEL_MASK,
5145 (ADC_CHANNEL_LUT[iChannel] & ADC_SINGLEDIFF_CHANNEL_MASK)
5146 & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5147 }
5148
5149 /**
5150 * @brief Get mode single-ended or differential input of the selected
5151 * ADC channel.
5152 * @note Channel ending is on channel scope: independently of channel mapped
5153 * on ADC group regular or injected.
5154 * In differential mode: Differential measurement is carried out
5155 * between the selected channel (positive input) and another
5156 * channel (negative input).
5157 * Only selected channel has to be configured, the other channel
5158 * is configured automatically.
5159 * @note The selected channel and the other other channel have
5160 * not necessarily contiguous channel number.
5161 * To get the other channel number, refer to reference manual
5162 * in section of ADC instance connectivity.
5163 * @note Refer to Reference Manual to ensure the selected channel is
5164 * available in differential mode.
5165 * For example, internal channels (VrefInt, TempSensor, ...) are
5166 * not available in differential mode.
5167 * @note When configuring a channel 'i' in differential mode,
5168 * the channel 'i+1' is not usable separately.
5169 * @note Some channels are internally fixed to single-ended inputs
5170 * configuration, refer to device datasheet for more details.
5171 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
5172 * @param ADCx ADC instance
5173 * @param Channel This parameter can be a combination of the following values:
5174 * @arg @ref LL_ADC_CHANNEL_1
5175 * @arg @ref LL_ADC_CHANNEL_2
5176 * @arg @ref LL_ADC_CHANNEL_3
5177 * @arg @ref LL_ADC_CHANNEL_4
5178 * @arg @ref LL_ADC_CHANNEL_5
5179 * @arg @ref LL_ADC_CHANNEL_6
5180 * @arg @ref LL_ADC_CHANNEL_7
5181 * @arg @ref LL_ADC_CHANNEL_8
5182 * @arg @ref LL_ADC_CHANNEL_9
5183 * @arg @ref LL_ADC_CHANNEL_10
5184 * @arg @ref LL_ADC_CHANNEL_11
5185 * @arg @ref LL_ADC_CHANNEL_12
5186 * @arg @ref LL_ADC_CHANNEL_13
5187 * @arg @ref LL_ADC_CHANNEL_14
5188 * @arg @ref LL_ADC_CHANNEL_15
5189 * @arg @ref LL_ADC_CHANNEL_16
5190 * @arg @ref LL_ADC_CHANNEL_17
5191 * @arg @ref LL_ADC_CHANNEL_18
5192 * @arg @ref LL_ADC_CHANNEL_19
5193 * @retval 0: channel in single-ended mode, else: channel in differential mode
5194 */
LL_ADC_GetChannelSingleDiff(const ADC_TypeDef * ADCx,uint32_t Channel)5195 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
5196 {
5197 const uint32_t iChannel = __ADC_CHANNEL_INDEX(Channel);
5198 return (uint32_t)(READ_BIT(ADCx->DIFSEL,
5199 (ADC_CHANNEL_LUT[iChannel] & ADC_SINGLEDIFF_CHANNEL_MASK)));
5200 }
5201
5202 /**
5203 * @}
5204 */
5205
5206 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5207 * @{
5208 */
5209
5210 /**
5211 * @brief Set ADC analog watchdog monitored channels:
5212 * a single channel, multiple channels or all channels,
5213 * on ADC groups regular and-or injected.
5214 * @note Once monitored channels are selected, analog watchdog
5215 * is enabled.
5216 * @note In case of need to define a single channel to monitor
5217 * with analog watchdog from sequencer channel definition,
5218 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5219 * @note On this STM32 series, there are 2 kinds of analog watchdog
5220 * instance:
5221 * - AWD standard (instance AWD1):
5222 * - channels monitored: can monitor 1 channel or all channels.
5223 * - groups monitored: ADC groups regular and-or injected.
5224 * - AWD flexible (instances AWD2, AWD3):
5225 * - channels monitored: flexible on channels monitored, selection is
5226 * channel wise, from from 1 to all channels.
5227 * Specificity of this analog watchdog: Multiple channels can
5228 * be selected. For example:
5229 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5230 * - groups monitored: not selection possible (monitoring on both
5231 * groups regular and injected).
5232 * Channels selected are monitored on groups regular and injected:
5233 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5234 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5235 * @note On this STM32 series, setting of this feature is conditioned to
5236 * ADC state:
5237 * ADC must be disabled or enabled without conversion on going
5238 * on either groups regular or injected.
5239 * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5240 * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5241 * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5242 * CFGR1 JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5243 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5244 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5245 * @param ADCx ADC instance
5246 * @param AWDy This parameter can be one of the following values:
5247 * @arg @ref LL_ADC_AWD1
5248 * @arg @ref LL_ADC_AWD2
5249 * @arg @ref LL_ADC_AWD3
5250 * @param AWDChannelGroup This parameter can be one of the following values:
5251 * @arg @ref LL_ADC_AWD_DISABLE
5252 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5253 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5254 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5255 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5256 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5257 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5258 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5259 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5260 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5261 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5262 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5263 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5264 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5265 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5266 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5267 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5268 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5269 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5270 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5271 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5272 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5273 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5274 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5275 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5276 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5277 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5278 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5279 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5280 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5281 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5282 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5283 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5284 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5285 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5286 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5287 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5288 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5289 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5290 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5291 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5292 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5293 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5294 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5295 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5296 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5297 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5298 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5299 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5300 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5301 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5302 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5303 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5304 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5305 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5306 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5307 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5308 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5309 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5310 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5311 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5312 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
5313 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
5314 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
5315 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
5316 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
5317 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
5318 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
5319 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
5320 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
5321 * @arg @ref LL_ADC_AWD_CH_VDDCORE_REG (0)(1)
5322 * @arg @ref LL_ADC_AWD_CH_VDDCORE_INJ (0)(1)
5323 * @arg @ref LL_ADC_AWD_CH_VDDCORE_REG_INJ (1)
5324 *
5325 * (0) On this STM32 series, parameter available only on analog watchdog instance: AWD1.\n
5326 * (1) On this STM32 series, parameter available only on ADC instance: ADC2, ADC3.
5327 * @retval None
5328 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)5329 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5330 {
5331 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5332 /* in register and register position depending on parameter "AWDy". */
5333 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5334 /* containing other bits reserved for other purpose. */
5335 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,
5336 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5337 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
5338 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5339
5340 MODIFY_REG(*preg,
5341 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5342 AWDChannelGroup & AWDy);
5343 }
5344
5345 /**
5346 * @brief Get ADC analog watchdog monitored channel.
5347 * @note Usage of the returned channel number:
5348 * - To reinject this channel into another function LL_ADC_xxx:
5349 * the returned channel number is only partly formatted on definition
5350 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5351 * with parts of literals LL_ADC_CHANNEL_x or using
5352 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5353 * Then the selected literal LL_ADC_CHANNEL_x can be used
5354 * as parameter for another function.
5355 * - To get the channel number in decimal format:
5356 * process the returned value with the helper macro
5357 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5358 * Applicable only when the analog watchdog is set to monitor
5359 * one channel.
5360 * @note On this STM32 series, there are 2 kinds of analog watchdog
5361 * instance:
5362 * - AWD standard (instance AWD1):
5363 * - channels monitored: can monitor 1 channel or all channels.
5364 * - groups monitored: ADC groups regular and-or injected.
5365 * - AWD flexible (instances AWD2, AWD3):
5366 * - channels monitored: flexible on channels monitored, selection is
5367 * channel wise, from from 1 to all channels.
5368 * Specificity of this analog watchdog: Multiple channels can
5369 * be selected. For example:
5370 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5371 * - groups monitored: not selection possible (monitoring on both
5372 * groups regular and injected).
5373 * Channels selected are monitored on groups regular and injected:
5374 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5375 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5376 * @note On this STM32 series, setting of this feature is conditioned to
5377 * ADC state:
5378 * ADC must be disabled or enabled without conversion on going
5379 * on either groups regular or injected.
5380 * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5381 * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5382 * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5383 * CFGR1 JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5384 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5385 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5386 * @param ADCx ADC instance
5387 * @param AWDy This parameter can be one of the following values:
5388 * @arg @ref LL_ADC_AWD1
5389 * @arg @ref LL_ADC_AWD2 (1)
5390 * @arg @ref LL_ADC_AWD3 (1)
5391 *
5392 * (1) On this AWD number, monitored channel can be retrieved
5393 * if only 1 channel is programmed (or none or all channels).
5394 * This function cannot retrieve monitored channel if
5395 * multiple channels are programmed simultaneously
5396 * by bitfield.
5397 * @retval Returned value can be one of the following values:
5398 * @arg @ref LL_ADC_AWD_DISABLE
5399 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5400 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5401 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5402 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5403 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5404 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5405 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5406 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5407 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5408 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5409 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5410 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5411 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5412 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5413 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5414 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5415 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5416 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5417 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5418 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5419 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5420 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5421 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5422 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5423 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5424 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5425 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5426 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5427 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5428 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5429 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5430 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5431 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5432 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5433 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5434 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5435 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5436 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5437 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5438 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5439 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5440 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5441 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5442 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5443 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5444 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5445 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5446 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5447 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5448 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5449 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5450 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5451 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5452 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5453 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5454 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5455 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5456 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5457 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5458 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5459 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
5460 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
5461 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
5462 *
5463 * (0) On this STM32 series, parameter available only on analog watchdog number: AWD1.
5464 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)5465 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
5466 {
5467 const __IO uint32_t *preg;
5468
5469 if (AWDy == LL_ADC_AWD1)
5470 {
5471 /* Set pointer to register of selected analog watchdog */
5472 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
5473 }
5474 else
5475 {
5476 /* Set pointer to register of selected analog watchdog */
5477 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) \
5478 >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL));
5479 }
5480
5481 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5482
5483 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
5484 /* (parameter value LL_ADC_AWD_DISABLE). */
5485 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5486 /* or a single channel. */
5487 if (analog_wd_monit_channels != 0UL)
5488 {
5489 if (AWDy == LL_ADC_AWD1)
5490 {
5491 if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
5492 {
5493 /* AWD monitoring a group of channels */
5494 analog_wd_monit_channels = ((analog_wd_monit_channels
5495 | (ADC_AWD_CR23_CHANNEL_MASK)
5496 )
5497 & (~(ADC_CFGR1_AWD1CH))
5498 );
5499 }
5500 else
5501 {
5502 /* AWD monitoring a single channel */
5503 analog_wd_monit_channels = (analog_wd_monit_channels
5504 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR1_AWD1CH_Pos))
5505 );
5506 }
5507 }
5508 else
5509 {
5510 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5511 {
5512 /* AWD monitoring a group of channels */
5513 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
5514 | ((ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN))
5515 );
5516 }
5517 else
5518 {
5519 /* AWD monitoring a single channel */
5520 /* AWD monitoring a group of channels */
5521 analog_wd_monit_channels = (analog_wd_monit_channels
5522 | (ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
5523 | (((uint32_t)(POSITION_VAL(analog_wd_monit_channels))) << ADC_CFGR1_AWD1CH_Pos)
5524 );
5525 }
5526 }
5527 }
5528
5529 return analog_wd_monit_channels;
5530 }
5531
5532 /**
5533 * @brief Set ADC analog watchdog threshold value of threshold
5534 * high or low.
5535 * @note In case of ADC resolution different of 12 bits, specific threshold data formatting is required:
5536 * - analog watchdog thresholds data must be aligned to left side (bit 11).
5537 * - bits out of resolution range (LSB) must be set to value "0".
5538 * To perform this formatting automatically, use helper
5539 * macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5540 * @note On this STM32 series, there are 2 kinds of analog watchdog
5541 * instance:
5542 * - AWD standard (instance AWD1):
5543 * - channels monitored: can monitor 1 channel or all channels.
5544 * - groups monitored: ADC groups regular and-or injected.
5545 * - resolution: resolution is not limited (corresponds to
5546 * ADC resolution configured).
5547 * - AWD flexible (instances AWD2, AWD3):
5548 * - channels monitored: flexible on channels monitored, selection is
5549 * channel wise, from from 1 to all channels.
5550 * Specificity of this analog watchdog: Multiple channels can
5551 * be selected. For example:
5552 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5553 * - groups monitored: not selection possible (monitoring on both
5554 * groups regular and injected).
5555 * Channels selected are monitored on groups regular and injected:
5556 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5557 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5558 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5559 * impacted: the comparison of analog watchdog thresholds is done
5560 * on oversampling intermediate computation (after ratio, before shift
5561 * application): intermediate register bitfield [32:7]
5562 * (26 most significant bits).
5563 * @note On this STM32 series, setting of this feature is conditioned to
5564 * ADC state:
5565 * ADC can be disabled, enabled with or without conversion on going
5566 * on either ADC groups regular or injected.
5567 * @rmtoll AWD1LTR LTR LL_ADC_SetAnalogWDThresholds\n
5568 * AWD1HTR HTR LL_ADC_SetAnalogWDThresholds\n
5569 * AWD2LTR LTR LL_ADC_SetAnalogWDThresholds\n
5570 * AWD2HTR HTR LL_ADC_SetAnalogWDThresholds\n
5571 * AWD3LTR LTR LL_ADC_SetAnalogWDThresholds\n
5572 * AWD3HTR HTR LL_ADC_SetAnalogWDThresholds
5573 * @param ADCx ADC instance
5574 * @param AWDy This parameter can be one of the following values:
5575 * @arg @ref LL_ADC_AWD1
5576 * @arg @ref LL_ADC_AWD2
5577 * @arg @ref LL_ADC_AWD3
5578 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5579 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5580 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5581 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
5582 * @retval None
5583 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)5584 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
5585 uint32_t AWDThresholdValue)
5586 {
5587 __IO uint32_t *preg;
5588
5589 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5590 /* position in register and register position depending on parameters */
5591 /* "AWDThresholdsHighLow" and "AWDy". */
5592 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5593 /* containing other bits reserved for other purpose. */
5594 if (AWDy == LL_ADC_AWD1)
5595 {
5596 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1LTR, (AWDThresholdsHighLow));
5597 }
5598 else
5599 {
5600 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1LTR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)
5601 >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
5602 + (AWDThresholdsHighLow));
5603 }
5604
5605 MODIFY_REG(*preg, ADC_AWD1LTR_LTR, AWDThresholdValue);
5606 }
5607
5608 /**
5609 * @brief Get ADC analog watchdog threshold value of threshold high,
5610 * threshold low or raw data with ADC thresholds high and low
5611 * concatenated.
5612 * @note In case of ADC resolution different of 12 bits, specific threshold data formatting is required:
5613 * - analog watchdog thresholds data must be aligned to left side (bit 11).
5614 * - bits out of resolution range (LSB) must be set to value "0".
5615 * To perform this formatting automatically, use helper
5616 * macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5617 * @rmtoll AWD1LTR LTR LL_ADC_GetAnalogWDThresholds\n
5618 * AWD1HTR HTR LL_ADC_GetAnalogWDThresholds\n
5619 * AWD2LTR LTR LL_ADC_GetAnalogWDThresholds\n
5620 * AWD2HTR HTR LL_ADC_GetAnalogWDThresholds\n
5621 * AWD3LTR LTR LL_ADC_GetAnalogWDThresholds\n
5622 * AWD3HTR HTR LL_ADC_GetAnalogWDThresholds
5623 * @param ADCx ADC instance
5624 * @param AWDy This parameter can be one of the following values:
5625 * @arg @ref LL_ADC_AWD1
5626 * @arg @ref LL_ADC_AWD2
5627 * @arg @ref LL_ADC_AWD3
5628 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5629 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5630 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5631 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
5632 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)5633 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
5634 uint32_t AWDy, uint32_t AWDThresholdsHighLow)
5635 {
5636 const __IO uint32_t *preg;
5637
5638 if (AWDy == LL_ADC_AWD1)
5639 {
5640 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1LTR, (AWDThresholdsHighLow));
5641 }
5642 else
5643 {
5644 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1LTR,
5645 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
5646 + (AWDThresholdsHighLow));
5647 }
5648
5649 return (uint32_t)(READ_BIT(*preg, ADC_AWD1LTR_LTR));
5650 }
5651
5652 /**
5653 * @brief Set ADC analog watchdog filtering configuration
5654 * @note On this STM32 series, setting of this feature is conditioned to
5655 * ADC state:
5656 * ADC must be disabled or enabled without conversion on going
5657 * on either groups regular or injected.
5658 * @note On this STM32 series, this feature is only available on first
5659 * analog watchdog (AWD1)
5660 * @rmtoll AWD1HTR AWDFILT LL_ADC_SetAWDFilteringConfiguration
5661 * @param ADCx ADC instance
5662 * @param AWDy This parameter can be one of the following values:
5663 * @arg @ref LL_ADC_AWD1
5664 * @param FilteringConfig This parameter can be one of the following values:
5665 * @arg @ref LL_ADC_AWD_FILTERING_NONE
5666 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
5667 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
5668 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
5669 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
5670 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
5671 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
5672 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
5673 * @retval None
5674 */
LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t FilteringConfig)5675 __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
5676 {
5677 /* Prevent unused argument(s) compilation warning */
5678 (void)(AWDy);
5679 MODIFY_REG(ADCx->AWD1HTR, ADC_AWD1HTR_AWDFILT, FilteringConfig);
5680 }
5681
5682 /**
5683 * @brief Get ADC analog watchdog filtering configuration
5684 * @note On this STM32 series, this feature is only available on first
5685 * analog watchdog (AWD1)
5686 * @rmtoll AWD1HTR AWDFILT LL_ADC_GetAWDFilteringConfiguration
5687 * @param ADCx ADC instance
5688 * @param AWDy This parameter can be one of the following values:
5689 * @arg @ref LL_ADC_AWD1
5690 * @retval Returned value can be:
5691 * @arg @ref LL_ADC_AWD_FILTERING_NONE
5692 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
5693 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
5694 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
5695 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
5696 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
5697 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
5698 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
5699 */
LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef * ADCx,uint32_t AWDy)5700 __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy)
5701 {
5702 /* Prevent unused argument(s) compilation warning */
5703 (void)(AWDy);
5704 return (uint32_t)(READ_BIT(ADCx->AWD1HTR, ADC_AWD1HTR_AWDFILT));
5705 }
5706
5707 /**
5708 * @}
5709 */
5710
5711 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
5712 * @{
5713 */
5714
5715 /**
5716 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
5717 * (availability of ADC group injected depends on STM32 series).
5718 * @note If both groups regular and injected are selected,
5719 * specify behavior of ADC group injected interrupting
5720 * group regular: when ADC group injected is triggered,
5721 * the oversampling on ADC group regular is either
5722 * temporary stopped and continued, or resumed from start
5723 * (oversampler buffer reset).
5724 * @note On this STM32 series, setting of this feature is conditioned to
5725 * ADC state:
5726 * ADC must be disabled or enabled without conversion on going
5727 * on either groups regular or injected.
5728 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
5729 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
5730 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
5731 * @param ADCx ADC instance
5732 * @param OvsScope This parameter can be one of the following values:
5733 * @arg @ref LL_ADC_OVS_DISABLE
5734 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5735 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5736 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5737 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5738 * @retval None
5739 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)5740 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
5741 {
5742 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
5743 }
5744
5745 /**
5746 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
5747 * (availability of ADC group injected depends on STM32 series).
5748 * @note If both groups regular and injected are selected,
5749 * specify behavior of ADC group injected interrupting
5750 * group regular: when ADC group injected is triggered,
5751 * the oversampling on ADC group regular is either
5752 * temporary stopped and continued, or resumed from start
5753 * (oversampler buffer reset).
5754 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
5755 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
5756 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
5757 * @param ADCx ADC instance
5758 * @retval Returned value can be one of the following values:
5759 * @arg @ref LL_ADC_OVS_DISABLE
5760 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5761 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5762 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5763 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5764 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)5765 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
5766 {
5767 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
5768 }
5769
5770 /**
5771 * @brief Set ADC oversampling discontinuous mode (triggered mode)
5772 * on the selected ADC group.
5773 * @note Number of oversampled conversions are done either in:
5774 * - continuous mode (all conversions of oversampling ratio
5775 * are done from 1 trigger)
5776 * - discontinuous mode (each conversion of oversampling ratio
5777 * needs a trigger)
5778 * @note On this STM32 series, setting of this feature is conditioned to
5779 * ADC state:
5780 * ADC must be disabled or enabled without conversion on going
5781 * on group regular.
5782 * @note On this STM32 series, oversampling discontinuous mode
5783 * (triggered mode) can be used only when oversampling is
5784 * set on group regular only and in resumed mode.
5785 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
5786 * @param ADCx ADC instance
5787 * @param OverSamplingDiscont This parameter can be one of the following values:
5788 * @arg @ref LL_ADC_OVS_REG_CONT
5789 * @arg @ref LL_ADC_OVS_REG_DISCONT
5790 * @retval None
5791 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)5792 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
5793 {
5794 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
5795 }
5796
5797 /**
5798 * @brief Get ADC oversampling discontinuous mode (triggered mode)
5799 * on the selected ADC group.
5800 * @note Number of oversampled conversions are done either in:
5801 * - continuous mode (all conversions of oversampling ratio
5802 * are done from 1 trigger)
5803 * - discontinuous mode (each conversion of oversampling ratio
5804 * needs a trigger)
5805 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
5806 * @param ADCx ADC instance
5807 * @retval Returned value can be one of the following values:
5808 * @arg @ref LL_ADC_OVS_REG_CONT
5809 * @arg @ref LL_ADC_OVS_REG_DISCONT
5810 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)5811 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
5812 {
5813 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
5814 }
5815
5816 /**
5817 * @brief Set ADC oversampling
5818 * (impacting both ADC groups regular and injected)
5819 * @note This function set the 2 items of oversampling configuration:
5820 * - ratio
5821 * - shift
5822 * @note On this STM32 series, setting of this feature is conditioned to
5823 * ADC state:
5824 * ADC must be disabled or enabled without conversion on going
5825 * on either groups regular or injected.
5826 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
5827 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
5828 * @param ADCx ADC instance
5829 * @param Ratio This parameter can be in the range from 1 to 1024
5830 * @param Shift This parameter can be one of the following values:
5831 * @arg @ref LL_ADC_OVS_SHIFT_NONE
5832 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
5833 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
5834 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
5835 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
5836 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
5837 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
5838 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
5839 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
5840 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
5841 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
5842 * @retval None
5843 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)5844 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
5845 {
5846 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
5847 }
5848
5849 /**
5850 * @brief Get ADC oversampling ratio
5851 * (impacting both ADC groups regular and injected)
5852 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
5853 * @param ADCx ADC instance
5854 * @retval Ratio This parameter can be in the from 1 to 1024.
5855 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)5856 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
5857 {
5858 return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
5859 }
5860
5861 /**
5862 * @brief Get ADC oversampling shift
5863 * (impacting both ADC groups regular and injected)
5864 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
5865 * @param ADCx ADC instance
5866 * @retval Shift This parameter can be one of the following values:
5867 * @arg @ref LL_ADC_OVS_SHIFT_NONE
5868 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
5869 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
5870 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
5871 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
5872 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
5873 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
5874 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
5875 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
5876 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
5877 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
5878 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)5879 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
5880 {
5881 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
5882 }
5883
5884 /**
5885 * @}
5886 */
5887
5888 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
5889 * @{
5890 */
5891
5892 #if defined(ADC_MULTIMODE_SUPPORT)
5893 /**
5894 * @brief Set ADC multimode configuration to operate in independent mode
5895 * or multimode (for devices with several ADC instances).
5896 * @note If multimode configuration: the selected ADC instance is
5897 * either master or slave depending on hardware.
5898 * Refer to reference manual.
5899 * @note On this STM32 series, setting of this feature is conditioned to
5900 * ADC state:
5901 * All ADC instances of the ADC common group must be disabled.
5902 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5903 * ADC instance or by using helper macro
5904 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5905 * @rmtoll CCR DUAL LL_ADC_SetMultimode
5906 * @param ADCxy_COMMON ADC common instance
5907 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5908 * @param Multimode This parameter can be one of the following values:
5909 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5910 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5911 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5912 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5913 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5914 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5915 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5916 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5917 * @retval None
5918 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)5919 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
5920 {
5921 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
5922 }
5923
5924 /**
5925 * @brief Get ADC multimode configuration to operate in independent mode
5926 * or multimode (for devices with several ADC instances).
5927 * @note If multimode configuration: the selected ADC instance is
5928 * either master or slave depending on hardware.
5929 * Refer to reference manual.
5930 * @rmtoll CCR DUAL LL_ADC_GetMultimode
5931 * @param ADCxy_COMMON ADC common instance
5932 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5933 * @retval Returned value can be one of the following values:
5934 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5935 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5936 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5937 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5938 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5939 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5940 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5941 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5942 */
LL_ADC_GetMultimode(const ADC_Common_TypeDef * ADCxy_COMMON)5943 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
5944 {
5945 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
5946 }
5947
5948 /**
5949 * @brief Set ADC multimode conversion data format: conversion data in data
5950 * register of each ADC instance or ADC common instance.
5951 * @note If ADC data transfer by DMA is used: data register as DMA source
5952 * and number of DMA requests is impacted, refer to description
5953 * of parameters of this function.
5954 * @note How to retrieve multimode conversion data:
5955 * For multimode data transfer setting 16 bit resolution or less,
5956 * using functions @ref LL_ADC_REG_ReadMultiConvPacking() or @ref LL_ADC_REG_ReadMultiConvNoPacking().
5957 * Conversion data is a raw data with ADC master and slave
5958 * concatenated.
5959 * A macro is available to get the conversion data of
5960 * ADC master or ADC slave: see helper macro
5961 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5962 * @note On this STM32 series, setting of this feature is conditioned to
5963 * ADC state:
5964 * All ADC instances of the ADC common group must be disabled
5965 * or enabled without conversion on going on group regular.
5966 * @rmtoll CCR DAMDF LL_ADC_SetMultiDataFormat
5967 * @param ADCxy_COMMON ADC common instance
5968 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5969 * @param MultiDataFormat This parameter can be one of the following values:
5970 * @arg @ref LL_ADC_MULTI_REG_DATA_EACH_ADC
5971 * @arg @ref LL_ADC_MULTI_REG_DATA_COMMON_32B
5972 * @arg @ref LL_ADC_MULTI_REG_DATA_COMMON_16B
5973 * @retval None
5974 */
LL_ADC_SetMultiDataFormat(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDataFormat)5975 __STATIC_INLINE void LL_ADC_SetMultiDataFormat(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDataFormat)
5976 {
5977 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDataFormat);
5978 }
5979
5980 /**
5981 * @brief Get ADC multimode conversion data format: conversion data in data
5982 * register of each ADC instance or ADC common instance.
5983 * @note If ADC data transfer by DMA is used: data register as DMA source
5984 * and number of DMA requests is impacted, refer to description
5985 * of parameters of this function.
5986 * @note How to retrieve multimode conversion data:
5987 * For multimode data transfer setting 16 bit resolution or less,
5988 * using functions @ref LL_ADC_REG_ReadMultiConvPacking() or @ref LL_ADC_REG_ReadMultiConvNoPacking().
5989 * Conversion data is a raw data with ADC master and slave
5990 * concatenated.
5991 * A macro is available to get the conversion data of
5992 * ADC master or ADC slave: see helper macro
5993 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5994 * @rmtoll CCR DAMDF LL_ADC_GetMultiDataFormat
5995 * @param ADCxy_COMMON ADC common instance
5996 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5997 * @retval Returned value can be one of the following values:
5998 * @arg @ref LL_ADC_MULTI_REG_DATA_EACH_ADC
5999 * @arg @ref LL_ADC_MULTI_REG_DATA_COMMON_32B
6000 * @arg @ref LL_ADC_MULTI_REG_DATA_COMMON_16B
6001 */
LL_ADC_GetMultiDataFormat(const ADC_Common_TypeDef * ADCxy_COMMON)6002 __STATIC_INLINE uint32_t LL_ADC_GetMultiDataFormat(const ADC_Common_TypeDef *ADCxy_COMMON)
6003 {
6004 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
6005 }
6006
6007 /**
6008 * @brief Set ADC multimode delay between 2 sampling phases.
6009 * @note The sampling delay range depends on ADC resolution:
6010 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
6011 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
6012 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
6013 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
6014 * @note On this STM32 series, setting of this feature is conditioned to
6015 * ADC state:
6016 * All ADC instances of the ADC common group must be disabled.
6017 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6018 * ADC instance or by using helper macro helper macro
6019 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6020 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
6021 * @param ADCxy_COMMON ADC common instance
6022 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6023 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
6024 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6025 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6026 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6027 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6028 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6029 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
6030 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
6031 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
6032 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
6033 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
6034 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
6035 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
6036 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
6037 * @retval None
6038 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)6039 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
6040 {
6041 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
6042 }
6043
6044 /**
6045 * @brief Get ADC multimode delay between 2 sampling phases.
6046 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
6047 * @param ADCxy_COMMON ADC common instance
6048 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6049 * @retval Returned value can be one of the following values:
6050 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6051 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6052 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6053 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6054 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6055 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
6056 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
6057 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
6058 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
6059 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
6060 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
6061 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
6062 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
6063 */
LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef * ADCxy_COMMON)6064 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
6065 {
6066 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
6067 }
6068 #endif /* ADC_MULTIMODE_SUPPORT */
6069
6070 /**
6071 * @}
6072 */
6073 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
6074 * @{
6075 */
6076
6077 /**
6078 * @brief Put ADC instance in deep power down state.
6079 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6080 * state, the internal analog calibration is lost. After exiting from
6081 * deep power down, calibration must be relaunched or calibration factor
6082 * (preliminarily saved) must be set back into calibration register.
6083 * @note On this STM32 series, setting of this feature is conditioned to
6084 * ADC state:
6085 * ADC must be ADC disabled.
6086 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
6087 * @param ADCx ADC instance
6088 * @retval None
6089 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)6090 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6091 {
6092 /* Note: Write register with some additional bits forced to state reset */
6093 /* instead of modifying only the selected bit for this function, */
6094 /* to not interfere with bits with HW property "rs". */
6095 MODIFY_REG(ADCx->CR,
6096 ADC_CR_BITS_PROPERTY_RS,
6097 ADC_CR_DEEPPWD);
6098 }
6099
6100 /**
6101 * @brief Disable ADC deep power down mode.
6102 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6103 * state, the internal analog calibration is lost. After exiting from
6104 * deep power down, calibration must be relaunched or calibration factor
6105 * (preliminarily saved) must be set back into calibration register.
6106 * @note On this STM32 series, setting of this feature is conditioned to
6107 * ADC state:
6108 * ADC must be ADC disabled.
6109 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
6110 * @param ADCx ADC instance
6111 * @retval None
6112 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)6113 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6114 {
6115 /* Note: Write register with some additional bits forced to state reset */
6116 /* instead of modifying only the selected bit for this function, */
6117 /* to not interfere with bits with HW property "rs". */
6118 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6119 }
6120
6121 /**
6122 * @brief Get the selected ADC instance deep power down state.
6123 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
6124 * @param ADCx ADC instance
6125 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
6126 */
LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef * ADCx)6127 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
6128 {
6129 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6130 }
6131
6132
6133 /**
6134 * @brief Enable the selected ADC instance.
6135 * @note On this STM32 series, after ADC enable, a delay for
6136 * ADC internal analog stabilization is required before performing a
6137 * ADC conversion start.
6138 * Refer to device datasheet, parameter tSTAB.
6139 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6140 * is enabled and when conversion clock is active.
6141 * (not only core clock: this ADC has a dual clock domain)
6142 * @note On this STM32 series, setting of this feature is conditioned to
6143 * ADC state:
6144 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
6145 * @rmtoll CR ADEN LL_ADC_Enable
6146 * @param ADCx ADC instance
6147 * @retval None
6148 */
LL_ADC_Enable(ADC_TypeDef * ADCx)6149 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6150 {
6151 /* Note: Write register with some additional bits forced to state reset */
6152 /* instead of modifying only the selected bit for this function, */
6153 /* to not interfere with bits with HW property "rs". */
6154 MODIFY_REG(ADCx->CR,
6155 ADC_CR_BITS_PROPERTY_RS,
6156 ADC_CR_ADEN);
6157 }
6158
6159 /**
6160 * @brief Disable the selected ADC instance.
6161 * @note On this STM32 series, setting of this feature is conditioned to
6162 * ADC state:
6163 * ADC must be not disabled. Must be enabled without conversion on going
6164 * on either groups regular or injected.
6165 * @rmtoll CR ADDIS LL_ADC_Disable
6166 * @param ADCx ADC instance
6167 * @retval None
6168 */
LL_ADC_Disable(ADC_TypeDef * ADCx)6169 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6170 {
6171 /* Note: Write register with some additional bits forced to state reset */
6172 /* instead of modifying only the selected bit for this function, */
6173 /* to not interfere with bits with HW property "rs". */
6174 MODIFY_REG(ADCx->CR,
6175 ADC_CR_BITS_PROPERTY_RS,
6176 ADC_CR_ADDIS);
6177 }
6178
6179 /**
6180 * @brief Get the selected ADC instance enable state.
6181 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6182 * is enabled and when conversion clock is active.
6183 * (not only core clock: this ADC has a dual clock domain)
6184 * @rmtoll CR ADEN LL_ADC_IsEnabled
6185 * @param ADCx ADC instance
6186 * @retval 0: ADC is disabled, 1: ADC is enabled.
6187 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)6188 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
6189 {
6190 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6191 }
6192
6193 /**
6194 * @brief Get the selected ADC instance disable state.
6195 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6196 * @param ADCx ADC instance
6197 * @retval 0: no ADC disable command on going.
6198 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)6199 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
6200 {
6201 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6202 }
6203
6204 /**
6205 * @brief Start ADC calibration in the mode single-ended
6206 * or differential (for devices with differential mode available).
6207 * @note On this STM32 series, a minimum number of ADC clock cycles
6208 * are required between ADC end of calibration and ADC enable.
6209 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6210 * @note For devices with differential mode available:
6211 * Calibration of offset is specific to each of
6212 * single-ended and differential modes
6213 * (calibration run must be performed for each of these
6214 * differential modes, if used afterwards and if the application
6215 * requires their calibration).
6216 * @note On this STM32 series, setting of this feature is conditioned to
6217 * ADC state:
6218 * ADC must be ADC disabled.
6219 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6220 * CR ADCALDIF LL_ADC_StartCalibration
6221 * @param ADCx ADC instance
6222 * @param SingleDiff This parameter can be one of the following values:
6223 * @arg @ref LL_ADC_SINGLE_ENDED
6224 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6225 * @retval None
6226 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)6227 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6228 {
6229 /* Note: Write register with some additional bits forced to state reset */
6230 /* instead of modifying only the selected bit for this function, */
6231 /* to not interfere with bits with HW property "rs". */
6232 MODIFY_REG(ADCx->CR,
6233 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6234 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6235 }
6236
6237 /**
6238 * @brief Get ADC calibration state.
6239 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6240 * @param ADCx ADC instance
6241 * @retval 0: calibration complete, 1: calibration in progress.
6242 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)6243 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
6244 {
6245 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6246 }
6247
6248 /**
6249 * @brief Stop ADC calibration
6250 * @note On this STM32 series, a minimum number of ADC clock cycles
6251 * are required between ADC end of calibration and ADC enable.
6252 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6253 * @rmtoll CR ADCAL LL_ADC_StopCalibration\n
6254 * CR ADCALDIF LL_ADC_StopCalibration
6255 * @param ADCx ADC instance
6256 * @retval None
6257 */
LL_ADC_StopCalibration(ADC_TypeDef * ADCx)6258 __STATIC_INLINE void LL_ADC_StopCalibration(ADC_TypeDef *ADCx)
6259 {
6260 /* Note: Write register with some additional bits forced to state reset */
6261 /* instead of modifying only the selected bit for this function, */
6262 /* to not interfere with bits with HW property "rs". */
6263 CLEAR_BIT(ADCx->CR, ADC_CR_ADCALDIF | ADC_CR_ADCAL | ADC_CR_BITS_PROPERTY_RS);
6264 }
6265
6266 /**
6267 * @brief Enable calibration additional offset
6268 * @rmtoll CALFACT CALADDOS LL_ADC_EnableCalibrationOffset
6269 * @param ADCx ADC instance
6270 * @retval None
6271 */
LL_ADC_EnableCalibrationOffset(ADC_TypeDef * ADCx)6272 __STATIC_INLINE void LL_ADC_EnableCalibrationOffset(ADC_TypeDef *ADCx)
6273 {
6274 SET_BIT(ADCx->CALFACT, ADC_CALFACT_CALADDOS);
6275 }
6276
6277 /**
6278 * @brief Disable calibration additional offset
6279 * @rmtoll CALFACT CALADDOS LL_ADC_DisableCalibrationOffset
6280 * @param ADCx ADC instance
6281 * @retval None
6282 */
LL_ADC_DisableCalibrationOffset(ADC_TypeDef * ADCx)6283 __STATIC_INLINE void LL_ADC_DisableCalibrationOffset(ADC_TypeDef *ADCx)
6284 {
6285 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALADDOS);
6286 }
6287
6288 /**
6289 * @brief Get calibration additional offset state.
6290 * @rmtoll CALFACT CALADDOS LL_ADC_IsCalibrationOnGoing
6291 * @param ADCx ADC instance
6292 * @retval 0: calibration offset disabled, 1: calibration offset enabled.
6293 */
LL_ADC_IsCalibrationOffsetEnabled(const ADC_TypeDef * ADCx)6294 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOffsetEnabled(const ADC_TypeDef *ADCx)
6295 {
6296 return ((READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALADDOS) == (ADC_CALFACT_CALADDOS)) ? 1UL : 0UL);
6297 }
6298 /**
6299 * @}
6300 */
6301
6302 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6303 * @{
6304 */
6305
6306 /**
6307 * @brief Start ADC group regular conversion.
6308 * @note On this STM32 series, this function is relevant for both
6309 * internal trigger (SW start) and external trigger:
6310 * - If ADC trigger has been set to software start, ADC conversion
6311 * starts immediately.
6312 * - If ADC trigger has been set to external trigger, ADC conversion
6313 * will start at next trigger event (on the selected trigger edge)
6314 * following the ADC start conversion command.
6315 * @note On this STM32 series, setting of this feature is conditioned to
6316 * ADC state:
6317 * ADC must be enabled without conversion on going on group regular,
6318 * without conversion stop command on going on group regular,
6319 * without ADC disable command on going.
6320 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6321 * @param ADCx ADC instance
6322 * @retval None
6323 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)6324 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6325 {
6326 /* Note: Write register with some additional bits forced to state reset */
6327 /* instead of modifying only the selected bit for this function, */
6328 /* to not interfere with bits with HW property "rs". */
6329 MODIFY_REG(ADCx->CR,
6330 ADC_CR_BITS_PROPERTY_RS,
6331 ADC_CR_ADSTART);
6332 }
6333
6334 /**
6335 * @brief Stop ADC group regular conversion.
6336 * @note On this STM32 series, setting of this feature is conditioned to
6337 * ADC state:
6338 * ADC must be enabled with conversion on going on group regular,
6339 * without ADC disable command on going.
6340 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6341 * @param ADCx ADC instance
6342 * @retval None
6343 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)6344 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6345 {
6346 /* Note: Write register with some additional bits forced to state reset */
6347 /* instead of modifying only the selected bit for this function, */
6348 /* to not interfere with bits with HW property "rs". */
6349 MODIFY_REG(ADCx->CR,
6350 ADC_CR_BITS_PROPERTY_RS,
6351 ADC_CR_ADSTP);
6352 }
6353
6354 /**
6355 * @brief Get ADC group regular conversion state.
6356 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6357 * @param ADCx ADC instance
6358 * @retval 0: no conversion is on going on ADC group regular.
6359 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)6360 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
6361 {
6362 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6363 }
6364
6365 /**
6366 * @brief Get ADC group regular command of conversion stop state
6367 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6368 * @param ADCx ADC instance
6369 * @retval 0: no command of conversion stop is on going on ADC group regular.
6370 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)6371 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
6372 {
6373 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6374 }
6375
6376 /**
6377 * @brief Get ADC group regular conversion data, range fit for
6378 * all ADC configurations: all ADC resolutions and
6379 * all oversampling increased data width (for devices
6380 * with feature oversampling).
6381 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6382 * @param ADCx ADC instance
6383 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6384 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)6385 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
6386 {
6387 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6388 }
6389
6390 /**
6391 * @brief Get ADC group regular conversion data, range fit for
6392 * ADC resolution 12 bits.
6393 * @note For devices with feature oversampling: Oversampling
6394 * can increase data width, function for extended range
6395 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6396 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6397 * @param ADCx ADC instance
6398 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6399 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)6400 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
6401 {
6402 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6403 }
6404
6405 /**
6406 * @brief Get ADC group regular conversion data, range fit for
6407 * ADC resolution 10 bits.
6408 * @note For devices with feature oversampling: Oversampling
6409 * can increase data width, function for extended range
6410 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6411 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
6412 * @param ADCx ADC instance
6413 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6414 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)6415 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
6416 {
6417 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6418 }
6419
6420 /**
6421 * @brief Get ADC group regular conversion data, range fit for
6422 * ADC resolution 8 bits.
6423 * @note For devices with feature oversampling: Oversampling
6424 * can increase data width, function for extended range
6425 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6426 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
6427 * @param ADCx ADC instance
6428 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6429 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)6430 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
6431 {
6432 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6433 }
6434
6435 /**
6436 * @brief Get ADC group regular conversion data, range fit for
6437 * ADC resolution 6 bits.
6438 * @note For devices with feature oversampling: Oversampling
6439 * can increase data width, function for extended range
6440 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6441 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
6442 * @param ADCx ADC instance
6443 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6444 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)6445 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
6446 {
6447 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6448 }
6449
6450 #if defined(ADC_MULTIMODE_SUPPORT)
6451 /**
6452 * @brief Get ADC multimode conversion data of ADC master and ADC slave
6453 * concatenated.
6454 * @note Multimode data concatenation is usable under conditions of
6455 * ADC multimode data format selected and data width,
6456 * refer to description of literals in @ref ADC_LL_EC_MULTI_DATA_FORMAT.
6457 * @note From raw data with ADC master and slave concatenated,
6458 * a macro is available to get the conversion data of
6459 * ADC master or ADC slave: see helper macro
6460 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6461 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConvPacking\n
6462 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConvPacking
6463 * @param ADCxy_COMMON ADC common instance
6464 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6465 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6466 */
LL_ADC_REG_ReadMultiConvPacking(const ADC_Common_TypeDef * ADCxy_COMMON)6467 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConvPacking(const ADC_Common_TypeDef *ADCxy_COMMON)
6468 {
6469 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)));
6470 }
6471
6472 /**
6473 * @brief Get ADC multimode conversion data of ADC master or ADC slave
6474 * (data set alternatively in specific data register).
6475 * @note Multimode data without concatenation is compliant with all
6476 * ADC multimode data format and data width,
6477 * refer to description of literals in @ref ADC_LL_EC_MULTI_DATA_FORMAT.
6478 * @note Multimode data without packing is using a unique data register
6479 * (CDR2) for data of ADC master and slave alternatively.
6480 * Therefore, data can be overwritten very quickly, recommended
6481 * method to retrieve data without risk to miss some occurrences
6482 * is to use DMA transfer.
6483 * @rmtoll CDR2 RDATA_ALT LL_ADC_REG_ReadMultiConvNoPacking
6484 * @param ADCxy_COMMON ADC common instance
6485 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6486 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6487 */
LL_ADC_REG_ReadMultiConvNoPacking(const ADC_Common_TypeDef * ADCxy_COMMON)6488 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConvNoPacking(const ADC_Common_TypeDef *ADCxy_COMMON)
6489 {
6490 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR2, ADC_CDR2_RDATA_ALT));
6491 }
6492 #endif /* ADC_MULTIMODE_SUPPORT */
6493
6494 /**
6495 * @}
6496 */
6497
6498 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
6499 * @{
6500 */
6501
6502 /**
6503 * @brief Start ADC group injected conversion.
6504 * @note On this STM32 series, this function is relevant for both
6505 * internal trigger (SW start) and external trigger:
6506 * - If ADC trigger has been set to software start, ADC conversion
6507 * starts immediately.
6508 * - If ADC trigger has been set to external trigger, ADC conversion
6509 * will start at next trigger event (on the selected trigger edge)
6510 * following the ADC start conversion command.
6511 * @note On this STM32 series, setting of this feature is conditioned to
6512 * ADC state:
6513 * ADC must be enabled without conversion on going on group injected,
6514 * without conversion stop command on going on group injected,
6515 * without ADC disable command on going.
6516 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
6517 * @param ADCx ADC instance
6518 * @retval None
6519 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)6520 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
6521 {
6522 /* Note: Write register with some additional bits forced to state reset */
6523 /* instead of modifying only the selected bit for this function, */
6524 /* to not interfere with bits with HW property "rs". */
6525 MODIFY_REG(ADCx->CR,
6526 ADC_CR_BITS_PROPERTY_RS,
6527 ADC_CR_JADSTART);
6528 }
6529
6530 /**
6531 * @brief Stop ADC group injected conversion.
6532 * @note On this STM32 series, setting of this feature is conditioned to
6533 * ADC state:
6534 * ADC must be enabled with conversion on going on group injected,
6535 * without ADC disable command on going.
6536 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
6537 * @param ADCx ADC instance
6538 * @retval None
6539 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)6540 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
6541 {
6542 /* Note: Write register with some additional bits forced to state reset */
6543 /* instead of modifying only the selected bit for this function, */
6544 /* to not interfere with bits with HW property "rs". */
6545 MODIFY_REG(ADCx->CR,
6546 ADC_CR_BITS_PROPERTY_RS,
6547 ADC_CR_JADSTP);
6548 }
6549
6550 /**
6551 * @brief Get ADC group injected conversion state.
6552 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
6553 * @param ADCx ADC instance
6554 * @retval 0: no conversion is on going on ADC group injected.
6555 */
LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef * ADCx)6556 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
6557 {
6558 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
6559 }
6560
6561 /**
6562 * @brief Get ADC group injected command of conversion stop state
6563 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
6564 * @param ADCx ADC instance
6565 * @retval 0: no command of conversion stop is on going on ADC group injected.
6566 */
LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef * ADCx)6567 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
6568 {
6569 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
6570 }
6571
6572 /**
6573 * @brief Get ADC group injected conversion data, range fit for
6574 * all ADC configurations: all ADC resolutions and
6575 * all oversampling increased data width (for devices
6576 * with feature oversampling).
6577 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
6578 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
6579 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
6580 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
6581 * @param ADCx ADC instance
6582 * @param Rank This parameter can be one of the following values:
6583 * @arg @ref LL_ADC_INJ_RANK_1
6584 * @arg @ref LL_ADC_INJ_RANK_2
6585 * @arg @ref LL_ADC_INJ_RANK_3
6586 * @arg @ref LL_ADC_INJ_RANK_4
6587 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6588 */
LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef * ADCx,uint32_t Rank)6589 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
6590 {
6591 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
6592 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6593
6594 return (uint32_t)(READ_BIT(*preg,
6595 ADC_JDR1_JDATA)
6596 );
6597 }
6598
6599 /**
6600 * @brief Get ADC group injected conversion data, range fit for
6601 * ADC resolution 12 bits.
6602 * @note For devices with feature oversampling: Oversampling
6603 * can increase data width, function for extended range
6604 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6605 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
6606 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
6607 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
6608 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
6609 * @param ADCx ADC instance
6610 * @param Rank This parameter can be one of the following values:
6611 * @arg @ref LL_ADC_INJ_RANK_1
6612 * @arg @ref LL_ADC_INJ_RANK_2
6613 * @arg @ref LL_ADC_INJ_RANK_3
6614 * @arg @ref LL_ADC_INJ_RANK_4
6615 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6616 */
LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef * ADCx,uint32_t Rank)6617 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
6618 {
6619 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
6620 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6621
6622 return (uint16_t)(READ_BIT(*preg,
6623 ADC_JDR1_JDATA)
6624 );
6625 }
6626
6627 /**
6628 * @brief Get ADC group injected conversion data, range fit for
6629 * ADC resolution 10 bits.
6630 * @note For devices with feature oversampling: Oversampling
6631 * can increase data width, function for extended range
6632 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6633 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
6634 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
6635 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
6636 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
6637 * @param ADCx ADC instance
6638 * @param Rank This parameter can be one of the following values:
6639 * @arg @ref LL_ADC_INJ_RANK_1
6640 * @arg @ref LL_ADC_INJ_RANK_2
6641 * @arg @ref LL_ADC_INJ_RANK_3
6642 * @arg @ref LL_ADC_INJ_RANK_4
6643 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6644 */
LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef * ADCx,uint32_t Rank)6645 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
6646 {
6647 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
6648 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6649
6650 return (uint16_t)(READ_BIT(*preg,
6651 ADC_JDR1_JDATA)
6652 );
6653 }
6654
6655 /**
6656 * @brief Get ADC group injected conversion data, range fit for
6657 * ADC resolution 8 bits.
6658 * @note For devices with feature oversampling: Oversampling
6659 * can increase data width, function for extended range
6660 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6661 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
6662 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
6663 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
6664 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
6665 * @param ADCx ADC instance
6666 * @param Rank This parameter can be one of the following values:
6667 * @arg @ref LL_ADC_INJ_RANK_1
6668 * @arg @ref LL_ADC_INJ_RANK_2
6669 * @arg @ref LL_ADC_INJ_RANK_3
6670 * @arg @ref LL_ADC_INJ_RANK_4
6671 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6672 */
LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef * ADCx,uint32_t Rank)6673 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
6674 {
6675 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
6676 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6677
6678 return (uint8_t)(READ_BIT(*preg,
6679 ADC_JDR1_JDATA)
6680 );
6681 }
6682
6683 /**
6684 * @brief Get ADC group injected conversion data, range fit for
6685 * ADC resolution 6 bits.
6686 * @note For devices with feature oversampling: Oversampling
6687 * can increase data width, function for extended range
6688 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6689 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
6690 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
6691 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
6692 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
6693 * @param ADCx ADC instance
6694 * @param Rank This parameter can be one of the following values:
6695 * @arg @ref LL_ADC_INJ_RANK_1
6696 * @arg @ref LL_ADC_INJ_RANK_2
6697 * @arg @ref LL_ADC_INJ_RANK_3
6698 * @arg @ref LL_ADC_INJ_RANK_4
6699 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6700 */
LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef * ADCx,uint32_t Rank)6701 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
6702 {
6703 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
6704 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6705
6706 return (uint8_t)(READ_BIT(*preg,
6707 ADC_JDR1_JDATA)
6708 );
6709 }
6710
6711 /**
6712 * @}
6713 */
6714
6715 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
6716 * @{
6717 */
6718
6719 /**
6720 * @brief Get flag ADC ready.
6721 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6722 * is enabled and when conversion clock is active.
6723 * (not only core clock: this ADC has a dual clock domain)
6724 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
6725 * @param ADCx ADC instance
6726 * @retval State of bit (1 or 0).
6727 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)6728 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
6729 {
6730 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
6731 }
6732
6733 /**
6734 * @brief Get flag ADC group regular end of unitary conversion.
6735 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
6736 * @param ADCx ADC instance
6737 * @retval State of bit (1 or 0).
6738 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)6739 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
6740 {
6741 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
6742 }
6743
6744 /**
6745 * @brief Get flag ADC group regular end of sequence conversions.
6746 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
6747 * @param ADCx ADC instance
6748 * @retval State of bit (1 or 0).
6749 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)6750 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
6751 {
6752 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
6753 }
6754
6755 /**
6756 * @brief Get flag ADC group regular overrun.
6757 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
6758 * @param ADCx ADC instance
6759 * @retval State of bit (1 or 0).
6760 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)6761 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
6762 {
6763 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
6764 }
6765
6766 /**
6767 * @brief Get flag ADC group regular end of sampling phase.
6768 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
6769 * @param ADCx ADC instance
6770 * @retval State of bit (1 or 0).
6771 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)6772 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
6773 {
6774 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
6775 }
6776
6777 /**
6778 * @brief Get flag ADC group injected end of unitary conversion.
6779 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
6780 * @param ADCx ADC instance
6781 * @retval State of bit (1 or 0).
6782 */
LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef * ADCx)6783 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
6784 {
6785 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
6786 }
6787
6788 /**
6789 * @brief Get flag ADC group injected end of sequence conversions.
6790 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
6791 * @param ADCx ADC instance
6792 * @retval State of bit (1 or 0).
6793 */
LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef * ADCx)6794 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
6795 {
6796 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
6797 }
6798
6799 /**
6800 * @brief Get flag ADC analog watchdog 1 flag
6801 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
6802 * @param ADCx ADC instance
6803 * @retval State of bit (1 or 0).
6804 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)6805 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
6806 {
6807 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
6808 }
6809
6810 /**
6811 * @brief Get flag ADC analog watchdog 2.
6812 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
6813 * @param ADCx ADC instance
6814 * @retval State of bit (1 or 0).
6815 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)6816 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
6817 {
6818 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
6819 }
6820
6821 /**
6822 * @brief Get flag ADC analog watchdog 3.
6823 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
6824 * @param ADCx ADC instance
6825 * @retval State of bit (1 or 0).
6826 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)6827 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
6828 {
6829 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
6830 }
6831
6832 /**
6833 * @brief Clear flag ADC ready.
6834 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6835 * is enabled and when conversion clock is active.
6836 * (not only core clock: this ADC has a dual clock domain)
6837 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
6838 * @param ADCx ADC instance
6839 * @retval None
6840 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)6841 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
6842 {
6843 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
6844 }
6845
6846 /**
6847 * @brief Clear flag ADC group regular end of unitary conversion.
6848 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
6849 * @param ADCx ADC instance
6850 * @retval None
6851 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)6852 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
6853 {
6854 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
6855 }
6856
6857 /**
6858 * @brief Clear flag ADC group regular end of sequence conversions.
6859 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
6860 * @param ADCx ADC instance
6861 * @retval None
6862 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)6863 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
6864 {
6865 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
6866 }
6867
6868 /**
6869 * @brief Clear flag ADC group regular overrun.
6870 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
6871 * @param ADCx ADC instance
6872 * @retval None
6873 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)6874 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
6875 {
6876 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
6877 }
6878
6879 /**
6880 * @brief Clear flag ADC group regular end of sampling phase.
6881 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
6882 * @param ADCx ADC instance
6883 * @retval None
6884 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)6885 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
6886 {
6887 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
6888 }
6889
6890 /**
6891 * @brief Clear flag ADC group injected end of unitary conversion.
6892 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
6893 * @param ADCx ADC instance
6894 * @retval None
6895 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)6896 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
6897 {
6898 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
6899 }
6900
6901 /**
6902 * @brief Clear flag ADC group injected end of sequence conversions.
6903 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
6904 * @param ADCx ADC instance
6905 * @retval None
6906 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)6907 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
6908 {
6909 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
6910 }
6911
6912 /**
6913 * @brief Clear flag ADC analog watchdog 1.
6914 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
6915 * @param ADCx ADC instance
6916 * @retval None
6917 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)6918 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
6919 {
6920 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
6921 }
6922
6923 /**
6924 * @brief Clear flag ADC analog watchdog 2.
6925 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
6926 * @param ADCx ADC instance
6927 * @retval None
6928 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)6929 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
6930 {
6931 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
6932 }
6933
6934 /**
6935 * @brief Clear flag ADC analog watchdog 3.
6936 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
6937 * @param ADCx ADC instance
6938 * @retval None
6939 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)6940 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
6941 {
6942 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
6943 }
6944
6945 #if defined(ADC_MULTIMODE_SUPPORT)
6946 /**
6947 * @brief Get flag multimode ADC ready of the ADC master.
6948 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
6949 * @param ADCxy_COMMON ADC common instance
6950 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6951 * @retval State of bit (1 or 0).
6952 */
LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)6953 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
6954 {
6955 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
6956 }
6957
6958 /**
6959 * @brief Get flag multimode ADC ready of the ADC slave.
6960 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
6961 * @param ADCxy_COMMON ADC common instance
6962 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6963 * @retval State of bit (1 or 0).
6964 */
LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)6965 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
6966 {
6967 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
6968 }
6969
6970 /**
6971 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
6972 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
6973 * @param ADCxy_COMMON ADC common instance
6974 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6975 * @retval State of bit (1 or 0).
6976 */
LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)6977 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
6978 {
6979 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_MST) == (LL_ADC_FLAG_EOC_MST)) ? 1UL : 0UL);
6980 }
6981
6982 /**
6983 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
6984 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
6985 * @param ADCxy_COMMON ADC common instance
6986 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6987 * @retval State of bit (1 or 0).
6988 */
LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)6989 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
6990 {
6991 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
6992 }
6993
6994 /**
6995 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
6996 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
6997 * @param ADCxy_COMMON ADC common instance
6998 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6999 * @retval State of bit (1 or 0).
7000 */
LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)7001 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7002 {
7003 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
7004 }
7005
7006 /**
7007 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
7008 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
7009 * @param ADCxy_COMMON ADC common instance
7010 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7011 * @retval State of bit (1 or 0).
7012 */
LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)7013 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7014 {
7015 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
7016 }
7017
7018 /**
7019 * @brief Get flag multimode ADC group regular overrun of the ADC master.
7020 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
7021 * @param ADCxy_COMMON ADC common instance
7022 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7023 * @retval State of bit (1 or 0).
7024 */
LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)7025 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7026 {
7027 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
7028 }
7029
7030 /**
7031 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
7032 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
7033 * @param ADCxy_COMMON ADC common instance
7034 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7035 * @retval State of bit (1 or 0).
7036 */
LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)7037 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7038 {
7039 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
7040 }
7041
7042 /**
7043 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
7044 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
7045 * @param ADCxy_COMMON ADC common instance
7046 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7047 * @retval State of bit (1 or 0).
7048 */
LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)7049 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7050 {
7051 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
7052 }
7053
7054 /**
7055 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
7056 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
7057 * @param ADCxy_COMMON ADC common instance
7058 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7059 * @retval State of bit (1 or 0).
7060 */
LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)7061 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7062 {
7063 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
7064 }
7065
7066 /**
7067 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
7068 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
7069 * @param ADCxy_COMMON ADC common instance
7070 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7071 * @retval State of bit (1 or 0).
7072 */
LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)7073 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7074 {
7075 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
7076 }
7077
7078 /**
7079 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
7080 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
7081 * @param ADCxy_COMMON ADC common instance
7082 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7083 * @retval State of bit (1 or 0).
7084 */
LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)7085 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7086 {
7087 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
7088 }
7089
7090 /**
7091 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
7092 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
7093 * @param ADCxy_COMMON ADC common instance
7094 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7095 * @retval State of bit (1 or 0).
7096 */
LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)7097 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7098 {
7099 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
7100 }
7101
7102 /**
7103 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
7104 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
7105 * @param ADCxy_COMMON ADC common instance
7106 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7107 * @retval State of bit (1 or 0).
7108 */
LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)7109 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7110 {
7111 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
7112 }
7113
7114 /**
7115 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
7116 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
7117 * @param ADCxy_COMMON ADC common instance
7118 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7119 * @retval State of bit (1 or 0).
7120 */
LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)7121 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7122 {
7123 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
7124 }
7125
7126 /**
7127 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
7128 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
7129 * @param ADCxy_COMMON ADC common instance
7130 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7131 * @retval State of bit (1 or 0).
7132 */
LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)7133 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7134 {
7135 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
7136 }
7137
7138 /**
7139 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
7140 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
7141 * @param ADCxy_COMMON ADC common instance
7142 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7143 * @retval State of bit (1 or 0).
7144 */
LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)7145 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7146 {
7147 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
7148 }
7149
7150 /**
7151 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
7152 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
7153 * @param ADCxy_COMMON ADC common instance
7154 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7155 * @retval State of bit (1 or 0).
7156 */
LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)7157 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7158 {
7159 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
7160 }
7161
7162 /**
7163 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
7164 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
7165 * @param ADCxy_COMMON ADC common instance
7166 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7167 * @retval State of bit (1 or 0).
7168 */
LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)7169 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7170 {
7171 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
7172 }
7173
7174 /**
7175 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
7176 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
7177 * @param ADCxy_COMMON ADC common instance
7178 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7179 * @retval State of bit (1 or 0).
7180 */
LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)7181 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7182 {
7183 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
7184 }
7185 #endif /* ADC_MULTIMODE_SUPPORT */
7186
7187 /**
7188 * @}
7189 */
7190
7191 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
7192 * @{
7193 */
7194
7195 /**
7196 * @brief Enable ADC ready.
7197 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7198 * @param ADCx ADC instance
7199 * @retval None
7200 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)7201 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7202 {
7203 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7204 }
7205
7206 /**
7207 * @brief Enable interruption ADC group regular end of unitary conversion.
7208 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7209 * @param ADCx ADC instance
7210 * @retval None
7211 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)7212 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
7213 {
7214 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
7215 }
7216
7217 /**
7218 * @brief Enable interruption ADC group regular end of sequence conversions.
7219 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
7220 * @param ADCx ADC instance
7221 * @retval None
7222 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)7223 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7224 {
7225 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7226 }
7227
7228 /**
7229 * @brief Enable ADC group regular interruption overrun.
7230 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7231 * @param ADCx ADC instance
7232 * @retval None
7233 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)7234 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7235 {
7236 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7237 }
7238
7239 /**
7240 * @brief Enable interruption ADC group regular end of sampling.
7241 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7242 * @param ADCx ADC instance
7243 * @retval None
7244 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)7245 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7246 {
7247 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7248 }
7249
7250 /**
7251 * @brief Enable interruption ADC group injected end of unitary conversion.
7252 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7253 * @param ADCx ADC instance
7254 * @retval None
7255 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)7256 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7257 {
7258 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7259 }
7260
7261 /**
7262 * @brief Enable interruption ADC group injected end of sequence conversions.
7263 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7264 * @param ADCx ADC instance
7265 * @retval None
7266 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)7267 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7268 {
7269 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7270 }
7271
7272 /**
7273 * @brief Enable interruption ADC analog watchdog 1.
7274 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7275 * @param ADCx ADC instance
7276 * @retval None
7277 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)7278 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7279 {
7280 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7281 }
7282
7283 /**
7284 * @brief Enable interruption ADC analog watchdog 2.
7285 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
7286 * @param ADCx ADC instance
7287 * @retval None
7288 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)7289 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7290 {
7291 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7292 }
7293
7294 /**
7295 * @brief Enable interruption ADC analog watchdog 3.
7296 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
7297 * @param ADCx ADC instance
7298 * @retval None
7299 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)7300 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7301 {
7302 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7303 }
7304
7305 /**
7306 * @brief Disable interruption ADC ready.
7307 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
7308 * @param ADCx ADC instance
7309 * @retval None
7310 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)7311 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7312 {
7313 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7314 }
7315
7316 /**
7317 * @brief Disable interruption ADC group regular end of unitary conversion.
7318 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7319 * @param ADCx ADC instance
7320 * @retval None
7321 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)7322 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7323 {
7324 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7325 }
7326
7327 /**
7328 * @brief Disable interruption ADC group regular end of sequence conversions.
7329 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7330 * @param ADCx ADC instance
7331 * @retval None
7332 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)7333 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7334 {
7335 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7336 }
7337
7338 /**
7339 * @brief Disable interruption ADC group regular overrun.
7340 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7341 * @param ADCx ADC instance
7342 * @retval None
7343 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)7344 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7345 {
7346 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7347 }
7348
7349 /**
7350 * @brief Disable interruption ADC group regular end of sampling.
7351 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7352 * @param ADCx ADC instance
7353 * @retval None
7354 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)7355 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7356 {
7357 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7358 }
7359
7360 /**
7361 * @brief Disable interruption ADC group regular end of unitary conversion.
7362 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7363 * @param ADCx ADC instance
7364 * @retval None
7365 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)7366 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
7367 {
7368 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7369 }
7370
7371 /**
7372 * @brief Disable interruption ADC group injected end of sequence conversions.
7373 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
7374 * @param ADCx ADC instance
7375 * @retval None
7376 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)7377 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
7378 {
7379 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7380 }
7381
7382 /**
7383 * @brief Disable interruption ADC analog watchdog 1.
7384 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7385 * @param ADCx ADC instance
7386 * @retval None
7387 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)7388 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7389 {
7390 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7391 }
7392
7393 /**
7394 * @brief Disable interruption ADC analog watchdog 2.
7395 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
7396 * @param ADCx ADC instance
7397 * @retval None
7398 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)7399 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
7400 {
7401 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7402 }
7403
7404 /**
7405 * @brief Disable interruption ADC analog watchdog 3.
7406 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
7407 * @param ADCx ADC instance
7408 * @retval None
7409 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)7410 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
7411 {
7412 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7413 }
7414
7415 /**
7416 * @brief Get state of interruption ADC ready
7417 * (0: interrupt disabled, 1: interrupt enabled).
7418 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
7419 * @param ADCx ADC instance
7420 * @retval State of bit (1 or 0).
7421 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)7422 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
7423 {
7424 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
7425 }
7426
7427 /**
7428 * @brief Get state of interruption ADC group regular end of unitary conversion
7429 * (0: interrupt disabled, 1: interrupt enabled).
7430 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
7431 * @param ADCx ADC instance
7432 * @retval State of bit (1 or 0).
7433 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)7434 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
7435 {
7436 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
7437 }
7438
7439 /**
7440 * @brief Get state of interruption ADC group regular end of sequence conversions
7441 * (0: interrupt disabled, 1: interrupt enabled).
7442 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
7443 * @param ADCx ADC instance
7444 * @retval State of bit (1 or 0).
7445 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)7446 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
7447 {
7448 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
7449 }
7450
7451 /**
7452 * @brief Get state of interruption ADC group regular overrun
7453 * (0: interrupt disabled, 1: interrupt enabled).
7454 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
7455 * @param ADCx ADC instance
7456 * @retval State of bit (1 or 0).
7457 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)7458 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
7459 {
7460 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
7461 }
7462
7463 /**
7464 * @brief Get state of interruption ADC group regular end of sampling
7465 * (0: interrupt disabled, 1: interrupt enabled).
7466 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
7467 * @param ADCx ADC instance
7468 * @retval State of bit (1 or 0).
7469 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)7470 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
7471 {
7472 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
7473 }
7474
7475 /**
7476 * @brief Get state of interruption ADC group injected end of unitary conversion
7477 * (0: interrupt disabled, 1: interrupt enabled).
7478 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
7479 * @param ADCx ADC instance
7480 * @retval State of bit (1 or 0).
7481 */
LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef * ADCx)7482 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
7483 {
7484 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
7485 }
7486
7487 /**
7488 * @brief Get state of interruption ADC group injected end of sequence conversions
7489 * (0: interrupt disabled, 1: interrupt enabled).
7490 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
7491 * @param ADCx ADC instance
7492 * @retval State of bit (1 or 0).
7493 */
LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef * ADCx)7494 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
7495 {
7496 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
7497 }
7498
7499 /**
7500 * @brief Get state of interruption ADC analog watchdog 1
7501 * (0: interrupt disabled, 1: interrupt enabled).
7502 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
7503 * @param ADCx ADC instance
7504 * @retval State of bit (1 or 0).
7505 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)7506 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
7507 {
7508 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
7509 }
7510
7511 /**
7512 * @brief Get state of interruption Get ADC analog watchdog 2
7513 * (0: interrupt disabled, 1: interrupt enabled).
7514 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
7515 * @param ADCx ADC instance
7516 * @retval State of bit (1 or 0).
7517 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)7518 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
7519 {
7520 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
7521 }
7522
7523 /**
7524 * @brief Get state of interruption Get ADC analog watchdog 3
7525 * (0: interrupt disabled, 1: interrupt enabled).
7526 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
7527 * @param ADCx ADC instance
7528 * @retval State of bit (1 or 0).
7529 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)7530 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
7531 {
7532 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
7533 }
7534
7535 /**
7536 * @}
7537 */
7538
7539 #if defined(USE_FULL_LL_DRIVER)
7540 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
7541 * @{
7542 */
7543
7544 /* Initialization of some features of ADC common parameters and multimode */
7545 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
7546 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
7547 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
7548
7549 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
7550 /* (availability of ADC group injected depends on STM32 series) */
7551 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
7552
7553 /* Initialization of some features of ADC instance */
7554 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
7555 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
7556
7557 /* Initialization of some features of ADC instance and ADC group regular */
7558 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
7559 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
7560
7561 /* Initialization of some features of ADC instance and ADC group injected */
7562 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
7563 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
7564
7565 /**
7566 * @}
7567 */
7568 #endif /* USE_FULL_LL_DRIVER */
7569
7570 /**
7571 * @}
7572 */
7573
7574 /**
7575 * @}
7576 */
7577
7578 #endif /* ADC1 || ADC2 */
7579
7580 /**
7581 * @}
7582 */
7583
7584 #ifdef __cplusplus
7585 }
7586 #endif
7587
7588 #endif /* STM32N6xx_LL_ADC_H */
7589
