1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_ADC_H
21 #define STM32U5xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC4)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC calibration: */
49 /* Internal register offset for ADC calibration factors configuration */
50
51 /* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ... */
52 /* the relevant bits for: */
53 /* (concatenation of multiple bits used in different registers) */
54 /* - ADC calibration configuration: configuration before calibration start */
55 /* - ADC calibration factors: register offset */
56 #define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
57 #define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
58 #define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
59 #define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
60 #define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of
61 calibration mode: 0 for offset,
62 1 for linearity */
63 /* Internal algorithm for resolution parameters */
64 /* ADC instances ADC1, ADC2 and ADC4 do not have same resolution and same bitfield value for equivalent resolution
65 in ADC bitfield ADC_CFGR1_RES_1 */
66 #define ADC_RESOLUTION_ADC4_PROCESSING (1UL) /* Value to be subtracted to literals LL_ADC_RESOLUTION_xB
67 to have equivalent setting for ADC4 */
68
69 /* Internal mask for ADC group regular sequencer: */
70 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
71 /* - sequencer register offset */
72 /* - sequencer rank bits position into the selected register */
73
74 /* Internal register offset for ADC group regular sequencer configuration */
75 /* (offset placed into a spare area of literal definition) */
76 #define ADC_SQR1_REGOFFSET (0x00000000UL)
77 #define ADC_SQR2_REGOFFSET (0x00000100UL)
78 #define ADC_SQR3_REGOFFSET (0x00000200UL)
79 #define ADC_SQR4_REGOFFSET (0x00000300UL)
80
81 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET\
82 | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
83 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
84 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
85
86 /* Definition of ADC group regular sequencer bits information to be inserted */
87 /* into ADC group regular sequencer ranks literals definition. */
88 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR1_SQ1" position in register */
89 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR1_SQ2" position in register */
90 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR1_SQ3" position in register */
91 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR1_SQ4" position in register */
92 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR2_SQ5" position in register */
93 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR2_SQ6" position in register */
94 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR2_SQ7" position in register */
95 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR2_SQ8" position in register */
96 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR2_SQ9" position in register */
97 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR3_SQ10" position in register */
98 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR3_SQ11" position in register */
99 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR3_SQ12" position in register */
100 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR3_SQ13" position in register */
101 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR3_SQ14" position in register */
102 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR4_SQ15" position in register */
103 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR4_SQ16" position in register */
104
105 #define ADC4_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ1" position in register */
106 #define ADC4_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ2" position in register */
107 #define ADC4_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ3" position in register */
108 #define ADC4_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ4" position in register */
109 #define ADC4_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ5" position in register */
110 #define ADC4_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ6" position in register */
111 #define ADC4_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ7" position in register */
112 #define ADC4_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ8" position in register */
113
114 /* Internal mask for ADC group injected sequencer: */
115 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
116 /* - data register offset */
117 /* - sequencer rank bits position into the selected register */
118
119 /* Internal register offset for ADC group injected data register */
120 /* (offset placed into a spare area of literal definition) */
121 #define ADC_JDR1_REGOFFSET (0x00000000UL)
122 #define ADC_JDR2_REGOFFSET (0x00000100UL)
123 #define ADC_JDR3_REGOFFSET (0x00000200UL)
124 #define ADC_JDR4_REGOFFSET (0x00000300UL)
125
126 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET\
127 | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
128 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
129 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
130
131 /* Definition of ADC group injected sequencer bits information to be inserted */
132 /* into ADC group injected sequencer ranks literals definition. */
133 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
134 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
135 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
136 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
137
138 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_TR1_HT1" position in register */
139 #define ADC4_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL0" position in register */
140 #define ADC4_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL1" position in register */
141 #define ADC4_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL2" position in register */
142 #define ADC4_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL3" position in register */
143 #define ADC4_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL4" position in register */
144 #define ADC4_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL5" position in register */
145 #define ADC4_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL6" position in register */
146 #define ADC4_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL7" position in register */
147 #define ADC4_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL8" position in register */
148 #define ADC4_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL9" position in register */
149 #define ADC4_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL10" position in register */
150 #define ADC4_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL11" position in register */
151 #define ADC4_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL12" position in register */
152 #define ADC4_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL13" position in register */
153 #define ADC4_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL14" position in register */
154 #define ADC4_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL15" position in register */
155 #define ADC4_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL16" position in register */
156 #define ADC4_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL17" position in register */
157 #define ADC4_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL18" position in register */
158 #define ADC4_CHSELR_CHSEL19_BITOFFSET_POS (19UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL19" position in register */
159 #define ADC4_CHSELR_CHSEL20_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL20" position in register */
160 #define ADC4_CHSELR_CHSEL21_BITOFFSET_POS (21UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL21" position in register */
161 #define ADC4_CHSELR_CHSEL22_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL22" position in register */
162 #define ADC4_CHSELR_CHSEL23_BITOFFSET_POS (23UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL23" position in register */
163 #define ADC4_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_SMPR_SMP1" position in register */
164 #define ADC4_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_SMPR_SMP2" position in register */
165 #define ADC4_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_SMPR_SMPSEL0" position in register */
166
167 /* Internal mask for ADC group regular trigger: */
168 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
169 /* - regular trigger source */
170 /* - regular trigger edge */
171 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting
172 for compatibility with some ADC on other STM32
173 families having this setting set by HW default value) */
174
175 /* Mask containing trigger source masks for each of possible */
176 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
177 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
178 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
179 ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
180 ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
181 ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
182
183 #define ADC4_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC4_CFGR1_EXTSEL) << (4U * 0UL)) | \
184 ((ADC4_CFGR1_EXTSEL) << (4U * 1UL)) | \
185 ((ADC4_CFGR1_EXTSEL) << (4U * 2UL)) | \
186 ((ADC4_CFGR1_EXTSEL) << (4U * 3UL)) )
187
188 /* Mask containing trigger edge masks for each of possible */
189 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
190 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
191 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
192 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
193 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
194 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
195
196 /* Definition of ADC group regular trigger bits information. */
197 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTSEL"
198 position in register */
199 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTEN"
200 position in register */
201
202 /* Internal mask for ADC group injected trigger: */
203 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
204 /* - injected trigger source */
205 /* - injected trigger edge */
206 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
207 compatibility with some ADC on other STM32 families
208 having this setting set by HW default value) */
209
210 /* Mask containing trigger source masks for each of possible */
211 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
212 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
213 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
214 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
215 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
216 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
217
218 /* Mask containing trigger edge masks for each of possible */
219 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
220 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
221 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
222 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
223 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
224 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
225
226 /* Definition of ADC group injected trigger bits information. */
227 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL"
228 position in register */
229 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN"
230 position in register */
231
232 /* Internal mask for ADC channel: */
233 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
234 /* - channel identifier defined by number */
235 /* - channel identifier defined by bitfield */
236 /* - channel differentiation between external channels (connected to */
237 /* GPIO pins) and internal channels (connected to internal paths) */
238 /* - channel sampling time defined by SMPRx register offset */
239 /* and SMPx bits positions into SMPRx register */
240 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
241 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
242 #define ADC_CHANNEL_ID_OFFSET_NUMBER_MASK (ADC_OFR1_OFFSET1_CH)
243 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
244 position in register */
245 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
246 | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK
247 aligned on register LSB (bit 0) */
248 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >>
249 [Position of bitfield "ADC_CHANNEL_NUMBER_MASK"
250 in register]) */
251
252 /* Channel differentiation between external and internal channels */
253 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
254 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
255
256 /* Internal register offset for ADC channel sampling time configuration */
257 /* (offset placed into a spare area of literal definition) */
258 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
259 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
260 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
261 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in
262 ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
263
264 #define ADC4_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
265 #define ADC4_SAMPLING_TIME_CH_MASK (ADC4_CHANNEL_ID_BITFIELD_MASK << ADC4_SMPR_SMPSEL0_BITOFFSET_POS)
266 #define ADC4_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 \
267 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to
268 ADC_CHANNEL_ID_NUMBER_MASK with
269 reduced range: on this STM32 series,
270 ADC group regular sequencer, if set
271 to mode "fully configurable", can
272 contain channels with a restricted
273 channel number. */
274
275 /* Definition of channels ID number information to be inserted into */
276 /* channels literals definition. */
277 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
278 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
279 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
280 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
281 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
282 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
283 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
284 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
285 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
286 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
287 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
288 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
289 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
290 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
291 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
292 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
293 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
294 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
295 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
296 #define ADC_CHANNEL_19_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
297 #if defined(ADC4)
298 #define ADC_CHANNEL_20_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 )
299 #define ADC_CHANNEL_21_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
300 #define ADC_CHANNEL_22_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
301 #define ADC_CHANNEL_23_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
302 #endif /* ADC4 */
303 /* Definition of channels ID bitfield information to be inserted into */
304 /* channels literals definition. */
305 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
306 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
307 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
308 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
309 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
310 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
311 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
312 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
313 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
314 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
315 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
316 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
317 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
318 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
319 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
320 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
321 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
322 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
323 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
324 #define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
325 #define ADC_CHANNEL_20_BITFIELD (ADC_AWD2CR_AWD2CH_20)
326 #define ADC_CHANNEL_21_BITFIELD (ADC_AWD2CR_AWD2CH_21)
327 #define ADC_CHANNEL_22_BITFIELD (ADC_AWD2CR_AWD2CH_22)
328 #define ADC_CHANNEL_23_BITFIELD (ADC_AWD2CR_AWD2CH_23)
329
330 #define ADC4_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
331 #define ADC4_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
332 #define ADC4_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
333 #define ADC4_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
334 #define ADC4_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
335 #define ADC4_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
336 #define ADC4_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
337 #define ADC4_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
338 #define ADC4_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
339 #define ADC4_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
340 #define ADC4_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
341 #define ADC4_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
342 #define ADC4_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
343 #define ADC4_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
344 #define ADC4_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
345 #define ADC4_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
346 #define ADC4_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
347 #define ADC4_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
348 #define ADC4_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
349 #define ADC4_CHANNEL_19_BITFIELD (ADC_CHSELR_CHSEL19)
350 #define ADC4_CHANNEL_20_BITFIELD (ADC_CHSELR_CHSEL20)
351 #define ADC4_CHANNEL_21_BITFIELD (ADC_CHSELR_CHSEL21)
352 #define ADC4_CHANNEL_22_BITFIELD (ADC_CHSELR_CHSEL22)
353 #define ADC4_CHANNEL_23_BITFIELD (ADC_CHSELR_CHSEL23)
354
355 /* Definition of channels sampling time information to be inserted into */
356 /* channels literals definition. */
357 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP0" register */
358 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP1" register */
359 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP2" register */
360 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP3" register */
361 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP4" register */
362 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP5" register */
363 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP6" register */
364 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP7" register */
365 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP8" register */
366 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP9" register */
367 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP10" register */
368 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP11" register */
369 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP12" register */
370 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP13" register */
371 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP14" register */
372 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP15" register */
373 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP16" register */
374 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP17" register */
375 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP18" register */
376 #define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP19" register */
377 #define ADC_CHANNEL_20_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP20" register */
378 #define ADC_CHANNEL_21_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP21" register */
379 #define ADC_CHANNEL_22_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP22" register */
380 #define ADC_CHANNEL_23_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP23" register */
381
382 /* Internal mask for ADC mode single or differential ended: */
383 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
384 /* the relevant bits for: */
385 /* (concatenation of multiple bits used in different registers) */
386 /* - ADC calibration: calibration start, calibration factor get or set */
387 /* - ADC channels: set each ADC channel ending mode */
388 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT2_CALFACT)
389 #define ADC_CALFACT2_CALFACT_S (0x0000FFFFUL)
390 #define ADC_CALFACT2_CALFACT_D (0xFFFF0000UL)
391 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
392 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_I_APB_ADDR_4 \
393 | ADC_CALFACT_I_APB_ADDR_3) /* Bits chosen to perform of shift when single
394 mode is selected, shift value out of
395 channels bits range. */
396 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
397 mask of bit */
398 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode:
399 position of bit */
400 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
401 ADC_SINGLEDIFF_CALIB_F_BIT_D
402 to position to perform a shift
403 of 4 ranks */
404
405 /* Internal mask for ADC analog watchdog: */
406 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
407 /* (concatenation of multiple bits used in different analog watchdogs, */
408 /* (feature of several watchdogs not available on all STM32 families)). */
409 /* - analog watchdog 1: monitored channel defined by number, */
410 /* selection of ADC group (ADC groups regular and-or injected). */
411 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
412 /* selection on groups. */
413
414 /* Internal register offset for ADC analog watchdog channel configuration */
415 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
416 #define ADC_AWD_CR2_REGOFFSET (0x01000000UL)
417 #define ADC_AWD_CR3_REGOFFSET (0x02000000UL)
418
419 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
420 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
421 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
422 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
423
424 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
425
426 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
427 #define ADC_AWD_CHANNEL_MASK (ADC_CHANNEL_ID_NUMBER_MASK)
428 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
429 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
430
431 #define ADC_AWD_CRX_REGOFFSET_POS (24UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK*/
432
433 /* Internal register offset for ADC analog watchdog threshold configuration */
434 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
435 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
436 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
437 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
438 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in
439 ADC_AWD_TRX_REGOFFSET_MASK */
440
441 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
442 threshold high: mask of bit */
443 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
444 threshold high: position of bit */
445 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH
446 to position to perform a shift of 4 ranks */
447 #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
448
449 /* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
450 /* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
451 #define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
452 #define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
453
454 /* Legacy literals */
455 #define LL_ADC_AWD1_TR LL_ADC_AWD1
456 #define LL_ADC_AWD2_TR LL_ADC_AWD2
457 #define LL_ADC_AWD3_TR LL_ADC_AWD3
458
459 /* Internal mask for ADC offset: */
460 /* Internal register offset for ADC offset number configuration */
461 #define ADC_OFR1_REGOFFSET (0x00000000UL)
462 #define ADC_OFR2_REGOFFSET (0x00000001UL)
463 #define ADC_OFR3_REGOFFSET (0x00000002UL)
464 #define ADC_OFR4_REGOFFSET (0x00000003UL)
465 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET\
466 | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
467
468 /* ADC registers bits positions */
469 #define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR1_RES_Pos)
470 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR1_AWD1SGL_Pos)
471 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR1_AWD1EN_Pos)
472 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR1_JAWD1EN_Pos)
473
474 /* ADC instance differentiation between ADC1 and ADC4 oversampling ratio */
475 #define ADC4_OVERSAMPLING_RATIO_PARAMETER (0x80000000UL)
476 #define ADC4_OVERSAMPLING_RATIO_PARAMETER_MASK (ADC4_OVERSAMPLING_RATIO_PARAMETER)
477
478 /* ADC registers bits groups */
479 #define ADC_CR_BITS_PROPERTY_RS ( ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART \
480 | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs":
481 Software can read as well as set this bit.
482 Writing '0' has no effect on the bit value. */
483
484 /* ADC internal channels related definitions */
485 /* Internal voltage reference VrefInt */
486 #define VREFINT_CAL_ADDR ((uint16_t*) (0x0BFA07A5UL)) /* Internal voltage reference, address of parameter
487 VREFINT_CAL: VrefInt ADC raw data acquired at
488 temperature 30 DegC (tolerance: +-5 DegC),
489 Vref+ = 3.0 V (tolerance: +-10 mV). */
490 #define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which
491 VrefInt has been calibrated in production
492 (tolerance: +-10 mV) (unit: mV). */
493 /* Temperature sensor */
494 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BFA0710UL)) /* Internal temperature sensor, address of parameter
495 TS_CAL1: On STM32U5, temperature sensor ADC raw
496 data acquired at temperature 30 DegC
497 (tolerance: +-5 DegC),Vref+ = 3.0 V
498 (tolerance: +-10 mV). */
499 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BFA0742UL)) /* Internal temperature sensor, address of parameter
500 TS_CAL2: On STM32U5, temperature sensor ADC raw
501 data acquired at temperature 110 DegC
502 (tolerance: +-5 DegC), Vref+ = 3.0 V
503 (tolerance: +-10 mV). */
504 #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which
505 temperature sensor has been calibrated in
506 production for data into TEMPSENSOR_CAL1_ADDR
507 (tolerance: +-5 DegC) (unit: DegC). */
508 #define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which
509 temperature sensor has been calibrated in
510 production for data into TEMPSENSOR_CAL2_ADDR
511 (tolerance: +-5 DegC) (unit: DegC). */
512 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with
513 which temperature sensor has been calibrated in
514 production (+-10 mV) (unit: mV). */
515
516 /**
517 * @}
518 */
519
520 /* Private macros ------------------------------------------------------------*/
521 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
522 * @{
523 */
524
525 /**
526 * @brief Driver macro reserved for internal use: isolate bits with the
527 * selected mask and shift them to the register LSB
528 * (shift mask on register position bit 0).
529 * @param __BITS__ Bits in register 32 bits
530 * @param __MASK__ Mask in register 32 bits
531 * @retval Bits in register 32 bits
532 */
533 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
534 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
535
536 /**
537 * @brief Driver macro reserved for internal use: set a pointer to
538 * a register from a register basis from which an offset
539 * is applied.
540 * @param __REG__ Register basis from which the offset is applied.
541 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
542 * @retval Pointer to register address
543 */
544 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
545 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
546
547 /**
548 * @}
549 */
550
551 /* Exported types ------------------------------------------------------------*/
552 #if defined(USE_FULL_LL_DRIVER)
553 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
554 * @{
555 */
556
557 /**
558 * @brief Structure definition of some features of ADC common parameters
559 * and multimode
560 * (all ADC instances belonging to the same ADC common instance).
561 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
562 * is conditioned to ADC instances state (all ADC instances
563 * sharing the same ADC common instance):
564 * All ADC instances sharing the same ADC common instance must be
565 * disabled.
566 */
567 typedef struct
568 {
569 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
570 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
571 This feature can be modified afterwards using unitary function
572 @ref LL_ADC_SetCommonClock(). */
573
574 #if defined(ADC_MULTIMODE_SUPPORT)
575 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode
576 or multimode (for devices with several ADC instances).
577 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
578
579 This feature can be modified afterwards using unitary function
580 @ref LL_ADC_SetMultimode(). */
581
582 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
583 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
584
585 This feature can be modified afterwards using unitary function
586 @ref LL_ADC_SetMultiDMATransfer(). */
587
588 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
589 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
590
591 This feature can be modified afterwards using unitary function
592 @ref LL_ADC_SetMultiTwoSamplingDelay(). */
593 #endif /* ADC_MULTIMODE_SUPPORT */
594
595 } LL_ADC_CommonInitTypeDef;
596
597 /**
598 * @brief Structure definition of some features of ADC instance.
599 * @note These parameters have an impact on ADC scope: ADC instance.
600 * Affects both group regular and group injected (availability
601 * of ADC group injected depends on STM32 families).
602 * Refer to corresponding unitary functions into
603 * @ref ADC_LL_EF_Configuration_ADC_Instance .
604 * @note The setting of these parameters by function @ref LL_ADC_Init()
605 * is conditioned to ADC state:
606 * ADC instance must be disabled.
607 * This condition is applied to all ADC features, for efficiency
608 * and compatibility over all STM32 families. However, the different
609 * features can be set under different ADC state conditions
610 * (setting possible with ADC enabled without conversion on going,
611 * ADC enabled with conversion on going, ...)
612 * Each feature can be updated afterwards with a unitary function
613 * and potentially with ADC in a different state than disabled,
614 * refer to description of each function for setting
615 * conditioned to ADC state.
616 */
617 typedef struct
618 {
619 uint32_t Resolution; /*!< Set ADC resolution.
620 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
621 This feature can be modified afterwards using unitary function
622 @ref LL_ADC_SetResolution(). */
623
624 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
625 This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
626
627 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
628 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
629 This feature can be modified afterwards using unitary function
630 @ref LL_ADC_SetDataAlignment(). */
631
632 uint32_t LowPowerMode; /*!< Set ADC low power mode.
633 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
634 This feature can be modified afterwards using unitary function
635 @ref LL_ADC_SetLowPowerMode(). */
636
637 } LL_ADC_InitTypeDef;
638
639 /**
640 * @brief Structure definition of some features of ADC group regular.
641 * @note These parameters have an impact on ADC scope: ADC group regular.
642 * Refer to corresponding unitary functions into
643 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
644 * (functions with prefix "REG").
645 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
646 * is conditioned to ADC state:
647 * ADC instance must be disabled.
648 * This condition is applied to all ADC features, for efficiency
649 * and compatibility over all STM32 families. However, the different
650 * features can be set under different ADC state conditions
651 * (setting possible with ADC enabled without conversion on going,
652 * ADC enabled with conversion on going, ...)
653 * Each feature can be updated afterwards with a unitary function
654 * and potentially with ADC in a different state than disabled,
655 * refer to description of each function for setting
656 * conditioned to ADC state.
657 */
658 typedef struct
659 {
660 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start)
661 or from external peripheral (timer event, external interrupt line).
662 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
663 @note On this STM32 series, setting trigger source to external trigger
664 also set trigger polarity to rising edge (default setting for
665 compatibility with some ADC on other STM32 families having this
666 setting set by HW default value).
667 In case of need to modify trigger edge, use function
668 @ref LL_ADC_REG_SetTriggerEdge().
669 This feature can be modified afterwards using unitary function
670 @ref LL_ADC_REG_SetTriggerSource(). */
671
672 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
673 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
674 This feature can be modified afterwards using unitary function
675 @ref LL_ADC_REG_SetSequencerLength(). */
676
677 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
678 and scan conversions interrupted every selected number of ranks.
679 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
680 @note This parameter has an effect only if group regular sequencer is
681 enabled (scan length of 2 ranks or more).
682 This feature can be modified afterwards using unitary function
683 @ref LL_ADC_REG_SetSequencerDiscont(). */
684
685 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular,
686 whether ADC conversions are performed in single mode (one conversion per
687 trigger) or in continuous mode (after the first trigger, following
688 conversions launched successively automatically).
689 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
690 Note: It is not possible to enable both ADC group regular continuous
691 mode and discontinuous mode.
692 This feature can be modified afterwards using unitary function
693 @ref LL_ADC_REG_SetContinuousMode(). */
694
695 uint32_t DataTransferMode; /*!< Set ADC group regular conversion data transfer mode: no transfer,
696 transfer by DMA (Limited/Unlimited) or MDF.
697 This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE
698 This feature can be modified afterwards using unitary function
699 @ref LL_ADC_REG_SetDataTransferMode(). */
700
701 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
702 by DMA, and DMA requests mode.
703 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
704 This feature can be modified afterwards using unitary function
705 @ref LL_ADC_REG_SetDMATransfer(). */
706
707 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
708 data preserved or overwritten.
709 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
710 This feature can be modified afterwards using unitary function
711 @ref LL_ADC_REG_SetOverrun(). */
712
713 } LL_ADC_REG_InitTypeDef;
714
715 /**
716 * @brief Structure definition of some features of ADC group injected.
717 * @note These parameters have an impact on ADC scope: ADC group injected.
718 * Refer to corresponding unitary functions into
719 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
720 * (functions with prefix "INJ").
721 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
722 * is conditioned to ADC state:
723 * ADC instance must be disabled.
724 * This condition is applied to all ADC features, for efficiency
725 * and compatibility over all STM32 families. However, the different
726 * features can be set under different ADC state conditions
727 * (setting possible with ADC enabled without conversion on going,
728 * ADC enabled with conversion on going, ...)
729 * Each feature can be updated afterwards with a unitary function
730 * and potentially with ADC in a different state than disabled,
731 * refer to description of each function for setting
732 * conditioned to ADC state.
733 */
734 typedef struct
735 {
736 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start)
737 or from external peripheral (timer event, external interrupt line).
738 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
739 @note On this STM32 series, setting trigger source to external trigger
740 also set trigger polarity to rising edge (default setting for
741 compatibility with some ADC on other STM32 families having this
742 setting set by HW default value).
743 In case of need to modify trigger edge, use function
744 @ref LL_ADC_INJ_SetTriggerEdge().
745 This feature can be modified afterwards using unitary function
746 @ref LL_ADC_INJ_SetTriggerSource(). */
747
748 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
749 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
750 This feature can be modified afterwards using unitary function
751 @ref LL_ADC_INJ_SetSequencerLength(). */
752
753 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
754 and scan conversions interrupted every selected number of ranks.
755 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
756 @note This parameter has an effect only if group injected sequencer
757 is enabled (scan length of 2 ranks or more).
758 This feature can be modified afterwards using unitary function
759 @ref LL_ADC_INJ_SetSequencerDiscont(). */
760
761 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
762 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
763 Note: This parameter must be set to set to independent trigger if injected
764 trigger source is set to an external trigger.
765 This feature can be modified afterwards using unitary function
766 @ref LL_ADC_INJ_SetTrigAuto(). */
767
768 } LL_ADC_INJ_InitTypeDef;
769
770 /**
771 * @}
772 */
773 #endif /* USE_FULL_LL_DRIVER */
774
775 /* Exported constants --------------------------------------------------------*/
776 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
777 * @{
778 */
779
780 /** @defgroup ADC_LL_EC_FLAG ADC flags
781 * @brief Flags defines which can be used with LL_ADC_ReadReg function
782 * @{
783 */
784 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
785 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
786 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
787 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
788 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
789 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
790 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
791 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
792 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
793 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
794 #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
795 #define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC flag Voltage Regulator (LDO) Ready */
796
797 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
798 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
799 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end
800 of unitary conversion */
801 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end
802 of unitary conversion */
803 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end
804 of sequence conversions */
805 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end
806 of sequence conversions */
807 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
808 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
809 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end
810 of sampling phase */
811 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end
812 of sampling phase */
813 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end
814 of unitary conversion */
815 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end
816 of unitary conversion */
817 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end
818 of sequence conversions */
819 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end
820 of sequence conversions */
821 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1
822 of the ADC master */
823 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1
824 of the ADC slave */
825 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2
826 of the ADC master */
827 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2
828 of the ADC slave */
829 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3
830 of the ADC master */
831 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3
832 of the ADC slave */
833 /**
834 * @}
835 */
836
837 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
838 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
839 * @{
840 */
841 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
842 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of
843 unitary conversion */
844 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of
845 sequence conversions */
846 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
847 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of
848 sampling phase */
849 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of
850 unitary conversion */
851 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of
852 sequence conversions */
853 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
854 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
855 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
856 #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
857 #define LL_ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC interruption ADC Voltage Regulator (LDO) Ready */
858 /**
859 * @}
860 */
861
862 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
863 * @{
864 */
865 /* List of ADC registers intended to be used (most commonly) with */
866 /* DMA transfer. */
867 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
868 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
869 (corresponding to register DR) to be used with ADC
870 configured in independent mode. Without DMA transfer,
871 register accessed by LL function
872 @ref LL_ADC_REG_ReadConversionData32() and
873 other functions @ref LL_ADC_REG_ReadConversionDatax() */
874 #if defined(ADC_MULTIMODE_SUPPORT)
875 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register
876 (corresponding to register CDR) to be used with
877 ADC configured in multimode (available on STM32 devices
878 with several ADC instances). Without DMA transfer,
879 register accessed by LL function
880 @ref LL_ADC_REG_ReadMultiConversionData32() */
881 #endif /* ADC_MULTIMODE_SUPPORT */
882 /**
883 * @}
884 */
885
886 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
887 * @{
888 */
889 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock
890 without prescaler */
891 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
892 with prescaler division
893 by 2 */
894 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
895 with prescaler division
896 by 4 */
897 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
898 with prescaler division
899 by 6 */
900 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock
901 with prescaler division
902 by 8 */
903 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
904 with prescaler division
905 by 10 */
906 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
907 with prescaler division
908 by 12 */
909 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
910 with prescaler division
911 by 16 */
912 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock
913 with prescaler division
914 by 32 */
915 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
916 with prescaler division
917 by 64 */
918 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
919 with prescaler division
920 by 128 */
921 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
922 with prescaler division
923 by 256 */
924 /**
925 * @}
926 */
927
928 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
929 * @{
930 */
931 /* Note: Other measurement paths to internal channels may be available */
932 /* (connections to other peripherals). */
933 /* If they are not listed below, they do not require any specific */
934 /* path enable. In this case, Access to measurement path is done */
935 /* only by selecting the corresponding ADC internal channel. */
936 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
937 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
938 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN) /*!< ADC measurement path to internal channel
939 temperature sensor */
940 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
941
942 #define LL_ADC_PATH_INTERNAL_VCORE (LL_ADC_PATH_INTERNAL_VREFINT \
943 | LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE) /*!< ADC measurement path
944 to internal channel VCore */
945 /**
946 * @}
947 */
948
949 /** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY ADC instance - Calibration mode for offset and linearity
950 * @{
951 */
952 #define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET) /*!< Calibration of ADC offset.
953 Duration of calibration of offset
954 duration: 1280 ADC clock cycles.
955 For devices with differential mode
956 available: Calibration of offset
957 is specific to each of single-ended
958 and differential modes. */
959 #define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)/*!< Calibration of ADC linearity.
960 Duration of calibration of
961 linearity: 15104 ADC clock cycles.
962 For devices with differential mode
963 available: Calibration of linearity
964 is common to both single-ended and
965 differential modes. */
966 #define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET \
967 | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and
968 linearity. Duration of calibration
969 of offset and linearity: 16384 ADC
970 clock cycles. For devices with
971 differential mode available:
972 Calibration of offset is specific
973 to each of single-ended and
974 differential modes, calibration of
975 linearity is common to both
976 single-ended and differential modes. */
977 /**
978 * @}
979 */
980
981 /** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_INDEX ADC indexes for linear calibration
982 * @{
983 */
984 #define LL_ADC_CALIB_OFFSET_INDEX (0x00000000UL) /*!< Offset Calibration Index */
985 #define LL_ADC_CALIB_LINEARITY_INDEX1 (ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 1*/
986 #define LL_ADC_CALIB_LINEARITY_INDEX2 (ADC_CR_CALINDEX1) /*!< Linearity Calibration Index 2*/
987 #define LL_ADC_CALIB_LINEARITY_INDEX3 (ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 3*/
988 #define LL_ADC_CALIB_LINEARITY_INDEX4 (ADC_CR_CALINDEX2) /*!< Linearity Calibration Index 4*/
989 #define LL_ADC_CALIB_LINEARITY_INDEX5 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 5*/
990 #define LL_ADC_CALIB_LINEARITY_INDEX6 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1) /*!< Linearity Calibration Index 6*/
991 #define LL_ADC_CALIB_LINEARITY_INDEX7 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 \
992 | ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 7*/
993 #define LL_ADC_CALIB_INTEROFFSET_INDEX (ADC_CR_CALINDEX3) /*!< Linearity Calibration Index 8*/
994 /**
995 * @}
996 */
997
998 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
999 * @{
1000 */
1001 #define LL_ADC_RESOLUTION_14B (0x00000000UL) /*!< ADC resolution 14 bits (ADC1, ADC2 only) */
1002 #define LL_ADC_RESOLUTION_12B ( ADC_CFGR1_RES_0) /*!< ADC resolution 12 bits */
1003 #define LL_ADC_RESOLUTION_10B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 10 bits */
1004 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 8 bits */
1005 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 \
1006 << ADC_RESOLUTION_ADC4_PROCESSING) /*!< ADC resolution 6 bits (ADC4 only)
1007 (value shift out of ADC_CFGR1_RES range,
1008 post-processing when applied with ADC4) */
1009
1010 /* Legacy literals */
1011 #define LL_ADC_RESOLUTION_12B_ADC4 LL_ADC_RESOLUTION_12B
1012 #define LL_ADC_RESOLUTION_10B_ADC4 LL_ADC_RESOLUTION_10B
1013 #define LL_ADC_RESOLUTION_8B_ADC4 LL_ADC_RESOLUTION_8B
1014 #define LL_ADC_RESOLUTION_6B_ADC4 LL_ADC_RESOLUTION_6B
1015 /**
1016 * @}
1017 */
1018 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
1019 * @{
1020 */
1021 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
1022 (alignment on data register LSB bit 0)*/
1023 #define LL_ADC_DATA_ALIGN_LEFT (ADC4_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned
1024 (alignment on data register MSB bit 15)*/
1025 /**
1026 * @}
1027 */
1028
1029 /** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
1030 * @{
1031 */
1032 #define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC conversion data */
1033 #define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC conversion data */
1034 #define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC conversion data */
1035 #define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC conversion data */
1036 #define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC conversion data */
1037 #define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC conversion data */
1038 #define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC conversion data */
1039 #define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC conversion data */
1040 #define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC conversion data */
1041 #define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC conversion data */
1042 #define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC conversion data */
1043 #define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC conversion data */
1044 #define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC conversion data */
1045 #define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC conversion data */
1046 #define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC conversion data */
1047 #define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC conversion data */
1048 /**
1049 * @}
1050 */
1051
1052 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
1053 * @{
1054 */
1055 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
1056 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
1057 /**
1058 * @}
1059 */
1060
1061 /** @defgroup ADC_LL_EC_AUTOPOWEROFF_MODE ADC instance - Low power mode auto power-off
1062 * @{
1063 */
1064 #define LL_ADC_LP_AUTOPOWEROFF_DISABLE (0x00000000UL) /*!< ADC low power mode auto power-off disabled */
1065 #define LL_ADC_LP_AUTOPOWEROFF_ENABLE (ADC4_PWRR_AUTOFF) /*!< ADC low power mode auto power-off enabled: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLPModeAutoPowerOff(). It can be combined with mode low power mode auto wait. */
1066 /**
1067 * @}
1068 */
1069
1070 /** @defgroup ADC_LL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE ADC instance - Autonomous deep power down mode
1071 * @{
1072 */
1073 #define LL_ADC_LP_AUTONOMOUS_DPD_DISABLE (0x00000000UL) /*!< ADC deep power down in autonomous mode disabled */
1074 #define LL_ADC_LP_AUTONOMOUS_DPD_ENABLE (ADC4_PWRR_DPD) /*!< ADC deep power down in autonomous mode enabled */
1075 /**
1076 * @}
1077 */
1078
1079 /** @defgroup ADC_LL_EC_VREF_PROTECTION_MODE ADC instance - VREF protection mode
1080 * @{
1081 */
1082 #define LL_ADC_VREF_PROT_DISABLE (0x00000000UL) /*!< ADC Vref+ protection disabled */
1083 #define LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE (ADC4_PWRR_VREFPROT) /*!< ADC Vref+ protection enabled: In case of simultaneous sampling phase of ADC4 and ADC1/2, ADC4 is put on hold during one ADC4 clock cycle to avoid noise on Vref+. */
1084 #define LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE (ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP) /*!< ADC Vref+ protection enabled: In case of simultaneous sampling phase of ADC4 and ADC1/2, ADC4 is put on hold during two ADC4 clock cycles to avoid noise on Vref+. */
1085 /**
1086 * @}
1087 */
1088
1089 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
1090 * @{
1091 */
1092 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
1093 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
1094 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
1095 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
1096 /**
1097 * @}
1098 */
1099
1100 /** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode
1101 * @{
1102 */
1103 #define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
1104 #define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSAT) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
1105 /**
1106 * @}
1107 */
1108
1109 /** @defgroup ADC_LL_EC_OFFSET_UNSIGNED_SATURATION ADC instance - Offset unsigned saturation mode
1110 * @{
1111 */
1112 #define LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset unsigned saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
1113 #define LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE (ADC_OFR1_USAT) /*!< ADC offset unsigned saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
1114 /**
1115 * @}
1116 */
1117
1118 /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
1119 * @{
1120 */
1121 #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4) */
1122 #define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4) */
1123 /**
1124 * @}
1125 */
1126
1127 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
1128 * @{
1129 */
1130 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
1131 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
1132 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
1133 /**
1134 * @}
1135 */
1136
1137 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
1138 * @{
1139 */
1140 #define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC4_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
1141 #define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC4_SMPR_SMP2_BITOFFSET_POS | ADC4_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
1142 /* Internal mask for ADC channel sampling time: */
1143 /* To select into literals LL_ADC_SAMPLINGTIME_x */
1144 /* the relevant bits for: */
1145 /* (concatenation of multiple bits used in register SMPR) */
1146 /* - ADC channels sampling time: setting channel wise, to map each channel */
1147 /* on one of the common sampling time available. */
1148 /* - ADC channels common sampling time: set a sampling time into one of the */
1149 /* common sampling time available. */
1150 #define ADC4_SAMPLING_TIME_SMP_MASK (ADC4_SMPR_SMP2 | ADC4_SMPR_SMP1)
1151 #define ADC4_SAMPLING_TIME_SMP_SHIFT_MASK (ADC4_SMPR_SMP2_BITOFFSET_POS | ADC4_SMPR_SMP1_BITOFFSET_POS)
1152
1153 /**
1154 * @}
1155 */
1156
1157 /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
1158 * @{
1159 */
1160 #define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
1161 #define LL_ADC_TRIGGER_FREQ_LOW (ADC4_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
1162 /**
1163 * @}
1164 */
1165
1166 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
1167 * @{
1168 */
1169 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
1170 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
1171 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
1172 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
1173 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
1174 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
1175 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
1176 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
1177 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
1178 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
1179 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
1180 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
1181 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
1182 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
1183 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
1184 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
1185 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
1186 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
1187 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
1188 #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
1189 #define LL_ADC_CHANNEL_20 (ADC_CHANNEL_20_NUMBER | ADC_CHANNEL_20_SMP | ADC_CHANNEL_20_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20 */
1190 #define LL_ADC_CHANNEL_21 (ADC_CHANNEL_21_NUMBER | ADC_CHANNEL_21_SMP | ADC_CHANNEL_21_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21 */
1191 #define LL_ADC_CHANNEL_22 (ADC_CHANNEL_22_NUMBER | ADC_CHANNEL_22_SMP | ADC_CHANNEL_22_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22 */
1192 #define LL_ADC_CHANNEL_23 (ADC_CHANNEL_23_NUMBER | ADC_CHANNEL_23_SMP | ADC_CHANNEL_23_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN23 */
1193
1194 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. . */
1195 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
1196 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. */
1197
1198 #define LL_ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vcore. On STM32U5, ADC channel available only on ADC instance: ADC4. */
1199 #define LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32U5, ADC channel available only on ADC instance: ADC4. */
1200 #define LL_ADC_CHANNEL_VBAT_ADC4 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32U5, ADC channel available only on ADC instance: ADC4. */
1201 #define LL_ADC_CHANNEL_DAC1CH1_ADC4 (LL_ADC_CHANNEL_21 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC4 */
1202 #define LL_ADC_CHANNEL_DAC1CH2_ADC4 (LL_ADC_CHANNEL_DAC1CH1_ADC4 | LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC4 */
1203
1204 #define LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE (0x01000000UL) /*!< Dummy bit for driver internal usage, not used in ADC channel setting registers CHSELR or SQRx */
1205
1206 /**
1207 * @}
1208 */
1209
1210 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
1211 * @{
1212 */
1213 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
1214 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1215 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1216 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1217 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1218 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
1219 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1220 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
1221 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
1222 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
1223 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR1_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
1224 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
1225 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
1226 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
1227 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
1228 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
1229 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
1230 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
1231 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
1232 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
1233 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
1234 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1235 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE15 (ADC_CFGR1_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 15 event. Trigger edge set to rising edge (default setting). */
1236 #define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 channel 1 event. Trigger edge set to rising edge (default setting). */
1237 #define LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
1238 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 channel 1 event. Trigger edge set to rising edge (default setting). */
1239 #define LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 channel 1 event. Trigger edge set to rising edge (default setting). */
1240 #define LL_ADC_REG_TRIG_EXT_LPTIM4_OUT (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
1241 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM4 OUT event. Trigger edge set to rising edge (default setting). */
1242
1243 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
1244 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4 (ADC4_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1245 #if defined(TIM2)
1246 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
1247 #endif /* TIM2 */
1248 #if defined(TIM15)
1249 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_1 | ADC4_CFGR1_EXTSEL_0 \
1250 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
1251 #endif /* TIM5 */
1252 #if defined(TIM6)
1253 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
1254 #endif /* TIM6 */
1255 #if defined(LPTIM1)
1256 #define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_0 \
1257 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: LPTIM1 CH1. Trigger edge set to rising edge (default setting). */
1258 #endif /* LPTIM1 */
1259 #if defined(LPTIM3)
1260 #define LL_ADC_REG_TRIG_EXT_LPTIM3_CH2_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_1 \
1261 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: LPTIM3 CH2. Trigger edge set to rising edge (default setting). */
1262 #endif /* LPTIM3 */
1263 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE15_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_1 \
1264 | ADC4_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1265
1266 /**
1267 * @}
1268 */
1269
1270 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
1271 * @{
1272 */
1273 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
1274 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
1275 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
1276 /**
1277 * @}
1278 */
1279
1280 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
1281 * @{
1282 */
1283 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
1284 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
1285 /**
1286 * @}
1287 */
1288
1289 /** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE ADC group regular - Data transfer mode of ADC conversion data
1290 * @{
1291 */
1292 #define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are transferred to DR rigister */
1293 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversion data are not transferred by DMA but to DR register */
1294 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
1295 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMNGT_1 | ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
1296 #define LL_ADC_REG_MDF_TRANSFER (ADC_CFGR1_DMNGT_1 ) /*!< ADC conversion data are transferred to DFSDM */
1297 /**
1298 * @}
1299 */
1300 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
1301 * @{
1302 */
1303 #define LL_ADC_REG_DMA_TRANSFER_NONE_ADC4 (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
1304 #define LL_ADC_REG_DMA_TRANSFER_LIMITED_ADC4 ( ADC4_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
1305 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED_ADC4 (ADC4_CFGR1_DMACFG | ADC4_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
1306 /**
1307 * @}
1308 */
1309
1310 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
1311 * @{
1312 */
1313 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
1314 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
1315 /**
1316 * @}
1317 */
1318
1319 /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
1320 * @{
1321 */
1322 #define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */
1323 #define LL_ADC_REG_SEQ_CONFIGURABLE (ADC4_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
1324 /**
1325 * @}
1326 */
1327
1328 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1329 * @{
1330 */
1331 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1332 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
1333 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
1334 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
1335 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
1336 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
1337 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
1338 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
1339 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
1340 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
1341 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
1342 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
1343 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
1344 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
1345 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
1346 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
1347 /**
1348 * @}
1349 */
1350 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1351 * @{
1352 */
1353 #define LL_ADC4_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1354 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
1355 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
1356 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
1357 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
1358 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
1359 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
1360 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
1361 /**
1362 * @}
1363 */
1364
1365 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1366 * @{
1367 */
1368 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
1369 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
1370 #define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
1371 #define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
1372 #define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
1373 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
1374 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
1375 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
1376 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 \
1377 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
1378 /**
1379 * @}
1380 */
1381
1382 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
1383 * @{
1384 */
1385 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
1386 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC4_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
1387 /**
1388 * @}
1389 */
1390
1391 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1392 * @{
1393 */
1394 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1395 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1396 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1397 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1398 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1399 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1400 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1401 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1402 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
1403 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
1404 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
1405 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
1406 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
1407 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
1408 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
1409 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
1410
1411 #define LL_ADC_REG_RANK_1_ADC4 (ADC4_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1412 #define LL_ADC_REG_RANK_2_ADC4 (ADC4_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1413 #define LL_ADC_REG_RANK_3_ADC4 (ADC4_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1414 #define LL_ADC_REG_RANK_4_ADC4 (ADC4_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1415 #define LL_ADC_REG_RANK_5_ADC4 (ADC4_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1416 #define LL_ADC_REG_RANK_6_ADC4 (ADC4_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1417 #define LL_ADC_REG_RANK_7_ADC4 (ADC4_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1418 #define LL_ADC_REG_RANK_8_ADC4 (ADC4_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1419 /**
1420 * @}
1421 */
1422
1423 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1424 * @{
1425 */
1426 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */
1427 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
1428 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1429 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
1430 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1431 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1432 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
1433 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1434 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1435 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1436 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
1437 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
1438 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
1439 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1440 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1441 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
1442 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
1443 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1444 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
1445 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
1446 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
1447 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
1448 #define LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
1449 #define LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1450 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
1451 #define LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1452 #define LL_ADC_INJ_TRIG_EXT_LPTIM4_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
1453 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1454
1455 /**
1456 * @}
1457 */
1458
1459 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1460 * @{
1461 */
1462 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
1463 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
1464 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
1465 /**
1466 * @}
1467 */
1468
1469 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1470 * @{
1471 */
1472 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
1473 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
1474 /**
1475 * @}
1476 */
1477
1478 /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
1479 * @{
1480 */
1481 #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME. */
1482 #define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
1483 Note: First conversion is using minimal
1484 sampling time (see @ref
1485 ADC_LL_EC_CHANNEL_SAMPLINGTIME). */
1486 #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG)/*!< ADC conversions sampling phase is controlled by trigger events:
1487 Trigger rising edge = start sampling
1488 Trigger falling edge = stop sampling and
1489 start conversion. */
1490 /**
1491 * @}
1492 */
1493
1494 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1495 * @{
1496 */
1497 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1498 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1499 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1500 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1501 /**
1502 * @}
1503 */
1504
1505 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1506 * @{
1507 */
1508 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
1509 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1510 /**
1511 * @}
1512 */
1513
1514 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1515 * @{
1516 */
1517 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1518 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1519 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1520 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1521 /**
1522 * @}
1523 */
1524
1525 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1526 * @{
1527 */
1528 #define LL_ADC_SAMPLINGTIME_5CYCLES (0x00000000UL) /*!< Sampling time 5 ADC clock cycles */
1529 #define LL_ADC_SAMPLINGTIME_6CYCLES ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6 ADC clock cycles */
1530 #define LL_ADC_SAMPLINGTIME_12CYCLES ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12 ADC clock cycles */
1531 #define LL_ADC_SAMPLINGTIME_20CYCLES ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 20 ADC clock cycles */
1532 #define LL_ADC_SAMPLINGTIME_36CYCLES (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 36 ADC clock cycles */
1533 #define LL_ADC_SAMPLINGTIME_68CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 68 ADC clock cycles */
1534 #define LL_ADC_SAMPLINGTIME_391CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 391 ADC clock cycles */
1535 #define LL_ADC_SAMPLINGTIME_814CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 814 ADC clock cycles */
1536
1537 #define LL_ADC_SAMPLINGTIME_5CYCLE LL_ADC_SAMPLINGTIME_5CYCLES /*!< Keep old definition for compatibility */
1538 #define LL_ADC_SAMPLINGTIME_391CYCLES_5 LL_ADC_SAMPLINGTIME_391CYCLES /*!< Keep old definition for compatibility */
1539 /**
1540 * @}
1541 */
1542
1543 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1544 * @{
1545 */
1546 #define LL_ADC4_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
1547 #define LL_ADC4_SAMPLINGTIME_3CYCLES_5 (ADC4_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
1548 #define LL_ADC4_SAMPLINGTIME_7CYCLES_5 (ADC4_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
1549 #define LL_ADC4_SAMPLINGTIME_12CYCLES_5 (ADC4_SMPR_SMP1_1 | ADC4_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
1550 #define LL_ADC4_SAMPLINGTIME_19CYCLES_5 (ADC4_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
1551 #define LL_ADC4_SAMPLINGTIME_39CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
1552 #define LL_ADC4_SAMPLINGTIME_79CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
1553 #define LL_ADC4_SAMPLINGTIME_814CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1 | ADC4_SMPR_SMP1_0) /*!< Sampling time 814.5 ADC clock cycles */
1554
1555 #define LL_ADC4_SAMPLINGTIME_160CYCLES_5 LL_ADC4_SAMPLINGTIME_814CYCLES_5 /*!< Keep old definition for compatibility */
1556 /**
1557 * @}
1558 */
1559
1560 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1561 * @{
1562 */
1563 #define LL_ADC_SINGLE_ENDED (0x0000FFFFUL) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1564 #define LL_ADC_DIFFERENTIAL_ENDED (0xFFFF0000UL) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1565 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1566 /**
1567 * @}
1568 */
1569
1570 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1571 * @{
1572 */
1573 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1574 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1575 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1576 /**
1577 * @}
1578 */
1579
1580 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1581 * @{
1582 */
1583 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1584 #define LL_ADC_AWD_ALL_CHANNELS_REG ((0x000FFFFFUL) | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1585 #define LL_ADC_AWD_ALL_CHANNELS_INJ ((0x000FFFFFUL) | ADC_CFGR1_JAWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1586 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ((0x000FFFFFUL) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1587 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1588 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1589 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1590 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1591 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1592 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1593 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1594 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1595 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1596 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1597 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1598 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1599 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1600 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1601 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1602 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1603 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1604 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1605 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1606 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1607 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1608 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1609 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1610 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1611 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1612 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1613 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1614 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1615 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1616 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1617 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1618 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1619 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1620 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1621 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1622 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1623 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1624 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1625 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1626 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1627 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1628 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1629 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1630 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1631 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1632 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1633 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1634 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1635 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1636 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1637 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1638 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1639 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1640 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1641 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1642 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1643 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1644 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1645 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1646 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1647 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1648 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1649 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1650 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1651 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1652 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1653 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1654 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1655 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1656 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1657 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1658 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1659 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1660 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1661 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1662 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1663 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1664 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1665 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1666 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1667 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1668 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1669 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1670 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1671 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1672 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1673 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1674 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1675 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1676 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1677 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1678 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1679 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1680 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1681 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1682 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1683 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1684 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1685 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1686 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1687 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1688 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1689 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1690 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1691 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1692 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1693 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1694 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1695 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1696 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1697 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1698 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1699 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1700 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1701 #define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1702 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1703 #define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1704 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1705 #define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1706 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1707 #define LL_ADC_AWD_CHANNEL_20_REG ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1708 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1709 #define LL_ADC_AWD_CHANNEL_20_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1710 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1711 #define LL_ADC_AWD_CHANNEL_20_REG_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1712 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1713 #define LL_ADC_AWD_CHANNEL_21_REG ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1714 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1715 #define LL_ADC_AWD_CHANNEL_21_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1716 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1717 #define LL_ADC_AWD_CHANNEL_21_REG_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1718 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1719 #define LL_ADC_AWD_CHANNEL_22_REG ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1720 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1721 #define LL_ADC_AWD_CHANNEL_22_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1722 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1723 #define LL_ADC_AWD_CHANNEL_22_REG_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1724 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1725 #define LL_ADC_AWD_CHANNEL_23_REG ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1726 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1727 #define LL_ADC_AWD_CHANNEL_23_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1728 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1729 #define LL_ADC_AWD_CHANNEL_23_REG_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1730 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1731 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
1732 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1733 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
1734 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1735 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
1736 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1737 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
1738 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1739 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
1740 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
1741 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
1742 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
1743 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
1744 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */
1745 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
1746 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */
1747 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
1748 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */
1749 #define LL_ADC_AWD_CH_VCORE_REG ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
1750 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1751 #define LL_ADC_AWD_CH_VCORE_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
1752 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1753 #define LL_ADC_AWD_CH_VCORE_REG_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
1754 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1755
1756 #define LL_ADC_AWD_CH_DAC1CH1_ADC4_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
1757 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC4, converted by group regular only */
1758 #define LL_ADC_AWD_CH_DAC1CH2_ADC4_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
1759 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC4, converted by group regular only */
1760 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC4_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
1761 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to emperature sensor, channel specific to ADC4, converted by group regular only */
1762 #define LL_ADC_AWD_CH_VBAT_ADC4_REG ((LL_ADC_CHANNEL_VBAT_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
1763 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC4, converted by group regular only */
1764 /**
1765 * @}
1766 */
1767
1768 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1769 * @{
1770 */
1771 #define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */
1772 #define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */
1773 /**
1774 * @}
1775 */
1776
1777 /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
1778 * @{
1779 */
1780 #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
1781 #define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
1782 #define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_HTR_AWDFILT_1 ) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
1783 #define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
1784 #define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_HTR_AWDFILT_2 ) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
1785 #define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
1786 #define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 ) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
1787 #define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
1788 /**
1789 * @}
1790 */
1791
1792 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1793 * @{
1794 */
1795 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1796 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
1797 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1798 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
1799 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1800 /**
1801 * @}
1802 */
1803
1804 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1805 * @{
1806 */
1807 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
1808 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1809 /**
1810 * @}
1811 */
1812 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1813 * @{
1814 */
1815 #define LL_ADC_OVS_RATIO_2 (ADC4_OVERSAMPLING_RATIO_PARAMETER | 0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1816 #define LL_ADC_OVS_RATIO_4 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1817 #define LL_ADC_OVS_RATIO_8 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1818 #define LL_ADC_OVS_RATIO_16 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1819 #define LL_ADC_OVS_RATIO_32 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1820 #define LL_ADC_OVS_RATIO_64 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1821 #define LL_ADC_OVS_RATIO_128 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1822 #define LL_ADC_OVS_RATIO_256 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1823 /**
1824 * @}
1825 */
1826
1827 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
1828 * @{
1829 */
1830 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
1831 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
1832 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
1833 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
1834 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
1835 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
1836 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
1837 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
1838 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
1839 #define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
1840 #define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
1841 #define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
1842 /**
1843 * @}
1844 */
1845
1846 #if defined(ADC_MULTIMODE_SUPPORT)
1847 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1848 * @{
1849 */
1850 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
1851 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1852 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1853 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1854 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1855 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1856 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1857 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1858 /**
1859 * @}
1860 */
1861
1862 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1863 * @{
1864 */
1865 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1866 #define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */
1867 #define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */
1868 /**
1869 * @}
1870 */
1871
1872 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1873 * @{
1874 */
1875 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle for all resolution */
1876 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles for all resolution */
1877 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles for all resolution */
1878 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles for all resolution */
1879 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles for all resolution */
1880 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for all resolution */
1881 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles for all resolution */
1882 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for all resolution */
1883 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for all resolution */
1884 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles for all resolution */
1885 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles for all resolution */
1886 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles for all resolution */
1887 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles for all resolution */
1888 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles for 8 bits resolution */
1889 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles for all resolution */
1890 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles for all resolution */
1891 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles for 10 bits resolution */
1892 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles for all resolution */
1893 /**
1894 * @}
1895 */
1896
1897 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1898 * @{
1899 */
1900 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1901 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1902 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1903 /**
1904 * @}
1905 */
1906
1907 #endif /* ADC_MULTIMODE_SUPPORT */
1908
1909 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1910 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1911 * not timeout values.
1912 * For details on delays values, refer to descriptions in source code
1913 * above each literal definition.
1914 * @{
1915 */
1916
1917 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1918 /* not timeout values. */
1919 /* Timeout values for ADC operations are dependent to device clock */
1920 /* configuration (system clock versus ADC clock), */
1921 /* and therefore must be defined in user application. */
1922 /* Indications for estimation of ADC timeout delays, for this */
1923 /* STM32 series: */
1924 /* - ADC calibration time: maximum delay is 16384/fADC. */
1925 /* (refer to device datasheet, parameter "tCAL") */
1926 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1927 /* (refer to device datasheet, parameter "tSTAB") */
1928 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1929 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1930 /* cycles */
1931 /* - ADC conversion time: duration depending on ADC clock and ADC */
1932 /* configuration. */
1933 /* (refer to device reference manual, section "Timing") */
1934
1935 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1936 /* Delay set to maximum value (refer to device datasheet, */
1937 /* parameter "tADCVREG_STUP"). */
1938 /* Unit: us */
1939 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1940
1941 /* Delay for internal voltage reference stabilization time. */
1942 /* Delay set to maximum value (refer to device datasheet, */
1943 /* parameter "ts_vrefint"). */
1944 /* Unit: us */
1945 #define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */
1946
1947 /* Delay for temperature sensor stabilization time. */
1948 /* Literal set to maximum value (refer to device datasheet, */
1949 /* parameter "tSTART_RUN"). */
1950 /* Unit: us */
1951 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
1952
1953 /* Delay required between ADC end of calibration and ADC enable. */
1954 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1955 /* are required between ADC end of calibration and ADC enable. */
1956 /* Wait time can be computed in user application by waiting for the */
1957 /* equivalent number of CPU cycles, by taking into account */
1958 /* ratio of CPU clock versus ADC clock prescalers. */
1959 /* Unit: ADC clock cycles. */
1960 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
1961
1962 /* Fixed timeout value for ADC linearity word bit set/clear delay. */
1963 /* Values defined to be higher than worst cases: maximum ratio between ADC */
1964 /* and CPU clock frequencies. */
1965 /* Example of profile low frequency : ADC frequency minimum 140kHz (cf */
1966 /* datasheet for ADC4), CPU frequency 160MHz. */
1967 /* Calibration time max = 25502 / fADC (refer to datasheet) */
1968 /* = 29M CPU cycles */
1969 #define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (29000000UL) /*!< ADC linearity calibration set/clear bit delay */
1970
1971 /**
1972 * @}
1973 */
1974
1975 /**
1976 * @}
1977 */
1978
1979 /* Exported macro ------------------------------------------------------------*/
1980 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1981 * @{
1982 */
1983
1984 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1985 * @{
1986 */
1987
1988 /**
1989 * @brief Write a value in ADC register
1990 * @param __INSTANCE__ ADC Instance
1991 * @param __REG__ Register to be written
1992 * @param __VALUE__ Value to be written in the register
1993 * @retval None
1994 */
1995 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1996
1997 /**
1998 * @brief Read a value in ADC register
1999 * @param __INSTANCE__ ADC Instance
2000 * @param __REG__ Register to be read
2001 * @retval Register value
2002 */
2003 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2004 /**
2005 * @}
2006 */
2007
2008 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
2009 * @{
2010 */
2011
2012 /**
2013 * @brief Helper macro to get ADC channel number in decimal format
2014 * from literals LL_ADC_CHANNEL_x.
2015 * @note Example:
2016 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
2017 * will return decimal number "4".
2018 * @note The input can be a value from functions where a channel
2019 * number is returned, either defined with number
2020 * or with bitfield (only one bit must be set).
2021 * @param __CHANNEL__ This parameter can be one of the following values:
2022 * @arg @ref LL_ADC_CHANNEL_0 (3)
2023 * @arg @ref LL_ADC_CHANNEL_1 (3)
2024 * @arg @ref LL_ADC_CHANNEL_2 (3)
2025 * @arg @ref LL_ADC_CHANNEL_3 (3)
2026 * @arg @ref LL_ADC_CHANNEL_4 (3)
2027 * @arg @ref LL_ADC_CHANNEL_5 (3)
2028 * @arg @ref LL_ADC_CHANNEL_6
2029 * @arg @ref LL_ADC_CHANNEL_7
2030 * @arg @ref LL_ADC_CHANNEL_8
2031 * @arg @ref LL_ADC_CHANNEL_9
2032 * @arg @ref LL_ADC_CHANNEL_10
2033 * @arg @ref LL_ADC_CHANNEL_11
2034 * @arg @ref LL_ADC_CHANNEL_12
2035 * @arg @ref LL_ADC_CHANNEL_13
2036 * @arg @ref LL_ADC_CHANNEL_14
2037 * @arg @ref LL_ADC_CHANNEL_15
2038 * @arg @ref LL_ADC_CHANNEL_16
2039 * @arg @ref LL_ADC_CHANNEL_17
2040 * @arg @ref LL_ADC_CHANNEL_18
2041 * @arg @ref LL_ADC_CHANNEL_19
2042 * @arg @ref LL_ADC_CHANNEL_VREFINT
2043 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2044 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2045 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2046 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2047 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2048 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2049 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2050 *
2051 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2052 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2053 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2054 * Other channels are slow channels (conversion rate: refer to reference manual).
2055 * @retval Value between Min_Data=0 and Max_Data=18
2056 */
2057 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
2058 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
2059 ? ( ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ) \
2060 : ( (uint32_t)POSITION_VAL((__CHANNEL__)) ) \
2061 )
2062
2063 /**
2064 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
2065 * from number in decimal format.
2066 * @note Example:
2067 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
2068 * will return a data equivalent to "LL_ADC_CHANNEL_4".
2069 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
2070 * @retval Returned value can be one of the following values:
2071 * @arg @ref LL_ADC_CHANNEL_0 (3)
2072 * @arg @ref LL_ADC_CHANNEL_1 (3)
2073 * @arg @ref LL_ADC_CHANNEL_2 (3)
2074 * @arg @ref LL_ADC_CHANNEL_3 (3)
2075 * @arg @ref LL_ADC_CHANNEL_4 (3)
2076 * @arg @ref LL_ADC_CHANNEL_5 (3)
2077 * @arg @ref LL_ADC_CHANNEL_6
2078 * @arg @ref LL_ADC_CHANNEL_7
2079 * @arg @ref LL_ADC_CHANNEL_8
2080 * @arg @ref LL_ADC_CHANNEL_9
2081 * @arg @ref LL_ADC_CHANNEL_10
2082 * @arg @ref LL_ADC_CHANNEL_11
2083 * @arg @ref LL_ADC_CHANNEL_12
2084 * @arg @ref LL_ADC_CHANNEL_13
2085 * @arg @ref LL_ADC_CHANNEL_14
2086 * @arg @ref LL_ADC_CHANNEL_15
2087 * @arg @ref LL_ADC_CHANNEL_16
2088 * @arg @ref LL_ADC_CHANNEL_17
2089 * @arg @ref LL_ADC_CHANNEL_18
2090 * @arg @ref LL_ADC_CHANNEL_19
2091 * @arg @ref LL_ADC_CHANNEL_VREFINT
2092 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2093 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2094 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2095 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2096 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2097 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2098 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2099 *
2100 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2101 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2102 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2103 * Other channels are slow channels (conversion rate: refer to reference manual).
2104 * (1, 2) For ADC channel read back from ADC register,
2105 * comparison with internal channel parameter to be done
2106 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2107 */
2108 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
2109 (((__DECIMAL_NB__) <= 9UL) \
2110 ? (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2111 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2112 (ADC_SMPR1_REGOFFSET)) \
2113 : (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2114 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2115 (ADC_SMPR2_REGOFFSET)) \
2116 )
2117
2118 /**
2119 * @brief Helper macro to determine whether the selected channel
2120 * corresponds to literal definitions of driver.
2121 * @note The different literal definitions of ADC channels are:
2122 * - ADC internal channel:
2123 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
2124 * - ADC external channel (channel connected to a GPIO pin):
2125 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
2126 * @note The channel parameter must be a value defined from literal
2127 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2128 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2129 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
2130 * must not be a value from functions where a channel number is
2131 * returned from ADC registers,
2132 * because internal and external channels share the same channel
2133 * number in ADC registers. The differentiation is made only with
2134 * parameters definitions of driver.
2135 * @param __CHANNEL__ This parameter can be one of the following values:
2136 * @arg @ref LL_ADC_CHANNEL_0 (3)
2137 * @arg @ref LL_ADC_CHANNEL_1 (3)
2138 * @arg @ref LL_ADC_CHANNEL_2 (3)
2139 * @arg @ref LL_ADC_CHANNEL_3 (3)
2140 * @arg @ref LL_ADC_CHANNEL_4 (3)
2141 * @arg @ref LL_ADC_CHANNEL_5 (3)
2142 * @arg @ref LL_ADC_CHANNEL_6
2143 * @arg @ref LL_ADC_CHANNEL_7
2144 * @arg @ref LL_ADC_CHANNEL_8
2145 * @arg @ref LL_ADC_CHANNEL_9
2146 * @arg @ref LL_ADC_CHANNEL_10
2147 * @arg @ref LL_ADC_CHANNEL_11
2148 * @arg @ref LL_ADC_CHANNEL_12
2149 * @arg @ref LL_ADC_CHANNEL_13
2150 * @arg @ref LL_ADC_CHANNEL_14
2151 * @arg @ref LL_ADC_CHANNEL_15
2152 * @arg @ref LL_ADC_CHANNEL_16
2153 * @arg @ref LL_ADC_CHANNEL_17
2154 * @arg @ref LL_ADC_CHANNEL_18
2155 * @arg @ref LL_ADC_CHANNEL_19
2156 * @arg @ref LL_ADC_CHANNEL_VREFINT
2157 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2158 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2159 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2160 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2161 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2162 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2163 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2164 *
2165 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2166 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2167 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2168 * Other channels are slow channels (conversion rate: refer to reference manual).
2169 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
2170 * (channel connected to a GPIO pin).
2171 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
2172 */
2173 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
2174 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
2175
2176 /**
2177 * @brief Helper macro to convert a channel defined from parameter
2178 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2179 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2180 * to its equivalent parameter definition of a ADC external channel
2181 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
2182 * @note The channel parameter can be, additionally to a value
2183 * defined from parameter definition of a ADC internal channel
2184 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
2185 * a value defined from parameter definition of
2186 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2187 * or a value from functions where a channel number is returned
2188 * from ADC registers.
2189 * @param __CHANNEL__ This parameter can be one of the following values:
2190 * @arg @ref LL_ADC_CHANNEL_0 (3)
2191 * @arg @ref LL_ADC_CHANNEL_1 (3)
2192 * @arg @ref LL_ADC_CHANNEL_2 (3)
2193 * @arg @ref LL_ADC_CHANNEL_3 (3)
2194 * @arg @ref LL_ADC_CHANNEL_4 (3)
2195 * @arg @ref LL_ADC_CHANNEL_5 (3)
2196 * @arg @ref LL_ADC_CHANNEL_6
2197 * @arg @ref LL_ADC_CHANNEL_7
2198 * @arg @ref LL_ADC_CHANNEL_8
2199 * @arg @ref LL_ADC_CHANNEL_9
2200 * @arg @ref LL_ADC_CHANNEL_10
2201 * @arg @ref LL_ADC_CHANNEL_11
2202 * @arg @ref LL_ADC_CHANNEL_12
2203 * @arg @ref LL_ADC_CHANNEL_13
2204 * @arg @ref LL_ADC_CHANNEL_14
2205 * @arg @ref LL_ADC_CHANNEL_15
2206 * @arg @ref LL_ADC_CHANNEL_16
2207 * @arg @ref LL_ADC_CHANNEL_17
2208 * @arg @ref LL_ADC_CHANNEL_18
2209 * @arg @ref LL_ADC_CHANNEL_19
2210 * @arg @ref LL_ADC_CHANNEL_VREFINT
2211 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2212 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2213 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2214 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2215 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2216 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2217 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2218 *
2219 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2220 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2221 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2222 * Other channels are slow channels (conversion rate: refer to reference manual).
2223 * @retval Returned value can be one of the following values:
2224 * @arg @ref LL_ADC_CHANNEL_0
2225 * @arg @ref LL_ADC_CHANNEL_1
2226 * @arg @ref LL_ADC_CHANNEL_2
2227 * @arg @ref LL_ADC_CHANNEL_3
2228 * @arg @ref LL_ADC_CHANNEL_4
2229 * @arg @ref LL_ADC_CHANNEL_5
2230 * @arg @ref LL_ADC_CHANNEL_6
2231 * @arg @ref LL_ADC_CHANNEL_7
2232 * @arg @ref LL_ADC_CHANNEL_8
2233 * @arg @ref LL_ADC_CHANNEL_9
2234 * @arg @ref LL_ADC_CHANNEL_10
2235 * @arg @ref LL_ADC_CHANNEL_11
2236 * @arg @ref LL_ADC_CHANNEL_12
2237 * @arg @ref LL_ADC_CHANNEL_13
2238 * @arg @ref LL_ADC_CHANNEL_14
2239 * @arg @ref LL_ADC_CHANNEL_15
2240 * @arg @ref LL_ADC_CHANNEL_16
2241 * @arg @ref LL_ADC_CHANNEL_17
2242 * @arg @ref LL_ADC_CHANNEL_18
2243 * @arg @ref LL_ADC_CHANNEL_19
2244 */
2245 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
2246 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
2247
2248 /**
2249 * @brief Helper macro to determine whether the internal channel
2250 * selected is available on the ADC instance selected.
2251 * @note The channel parameter must be a value defined from parameter
2252 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2253 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2254 * must not be a value defined from parameter definition of
2255 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2256 * or a value from functions where a channel number is
2257 * returned from ADC registers,
2258 * because internal and external channels share the same channel
2259 * number in ADC registers. The differentiation is made only with
2260 * parameters definitions of driver.
2261 * @param __ADC_INSTANCE__ ADC instance
2262 * @param __CHANNEL__ This parameter can be one of the following values:
2263 * @arg @ref LL_ADC_CHANNEL_VREFINT
2264 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2265 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2266 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2267 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2268 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2269 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2270 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2271 *
2272 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2273 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2274 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
2275 * Value "1" if the internal channel selected is available on the ADC instance selected.
2276 */
2277 #if defined(ADC2)
2278 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2279 ((((__ADC_INSTANCE__) == ADC4) \
2280 &&(((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2281 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \
2282 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC4) || \
2283 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC4) || \
2284 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC4) ) \
2285 ) \
2286 || \
2287 (((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2) \
2288 &&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
2289 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2290 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) ) \
2291 ) \
2292 )
2293 #else
2294 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2295 ((((__ADC_INSTANCE__) == ADC4) \
2296 &&(((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2297 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \
2298 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC4) || \
2299 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC4) || \
2300 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC4) ) \
2301 ) \
2302 || \
2303 (((__ADC_INSTANCE__) == ADC1) \
2304 &&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
2305 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2306 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) ) \
2307 ) \
2308 )
2309 #endif /* ADC2 */
2310 /**
2311 * @brief Helper macro to define ADC analog watchdog parameter:
2312 * define a single channel to monitor with analog watchdog
2313 * from sequencer channel and groups definition.
2314 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2315 * Example:
2316 * LL_ADC_SetAnalogWDMonitChannels(
2317 * ADC1, LL_ADC_AWD1,
2318 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
2319 * @param __CHANNEL__ This parameter can be one of the following values:
2320 * @arg @ref LL_ADC_CHANNEL_0 (3)
2321 * @arg @ref LL_ADC_CHANNEL_1 (3)
2322 * @arg @ref LL_ADC_CHANNEL_2 (3)
2323 * @arg @ref LL_ADC_CHANNEL_3 (3)
2324 * @arg @ref LL_ADC_CHANNEL_4 (3)
2325 * @arg @ref LL_ADC_CHANNEL_5 (3)
2326 * @arg @ref LL_ADC_CHANNEL_6
2327 * @arg @ref LL_ADC_CHANNEL_7
2328 * @arg @ref LL_ADC_CHANNEL_8
2329 * @arg @ref LL_ADC_CHANNEL_9
2330 * @arg @ref LL_ADC_CHANNEL_10
2331 * @arg @ref LL_ADC_CHANNEL_11
2332 * @arg @ref LL_ADC_CHANNEL_12
2333 * @arg @ref LL_ADC_CHANNEL_13
2334 * @arg @ref LL_ADC_CHANNEL_14
2335 * @arg @ref LL_ADC_CHANNEL_15
2336 * @arg @ref LL_ADC_CHANNEL_16
2337 * @arg @ref LL_ADC_CHANNEL_17
2338 * @arg @ref LL_ADC_CHANNEL_18
2339 * @arg @ref LL_ADC_CHANNEL_19
2340 * @arg @ref LL_ADC_CHANNEL_VREFINT
2341 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2342 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2343 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2344 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2345 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2346 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2347 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2348 *
2349 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2350 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2351 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2352 * Other channels are slow channels (conversion rate: refer to reference manual).
2353 * (1, 2) For ADC channel read back from ADC register,
2354 * comparison with internal channel parameter to be done
2355 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2356 * @param __GROUP__ This parameter can be one of the following values:
2357 * @arg @ref LL_ADC_GROUP_REGULAR
2358 * @arg @ref LL_ADC_GROUP_INJECTED
2359 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
2360 * @retval Returned value can be one of the following values:
2361 * @arg @ref LL_ADC_AWD_DISABLE
2362 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
2363 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
2364 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
2365 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
2366 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
2367 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
2368 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
2369 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
2370 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
2371 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
2372 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
2373 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
2374 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
2375 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
2376 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
2377 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
2378 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
2379 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
2380 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
2381 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
2382 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
2383 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
2384 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
2385 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
2386 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
2387 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
2388 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2389 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
2390 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
2391 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2392 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2393 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2394 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2395 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2396 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2397 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2398 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2399 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2400 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2401 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2402 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2403 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2404 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2405 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2406 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2407 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2408 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2409 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2410 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2411 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2412 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2413 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2414 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2415 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2416 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2417 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2418 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2419 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2420 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2421 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2422 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
2423 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
2424 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
2425 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
2426 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
2427 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
2428 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
2429 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
2430 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
2431 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
2432 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
2433 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
2434 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC4_REG (0)(2)
2435 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC4_REG (0)(2)
2436 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC4_REG (2)
2437 * @arg @ref LL_ADC_AWD_CH_VBAT_ADC4_REG (2)
2438 * @arg @ref LL_ADC_AWD_CH_VCORE_REG (2)
2439 *
2440 * (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
2441 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
2442 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2443 */
2444 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2445 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2446 ? (((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) \
2447 : \
2448 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2449 ? (((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) \
2450 : \
2451 (((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) \
2452 )
2453
2454 /**
2455 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2456 * or low in function of ADC resolution, when ADC resolution is
2457 * different of 14 bits in case of ADC1 or ADC2, 12 bits in case of ADC4.
2458 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
2459 * Example, with a ADC resolution of 8 bits, to set the value of
2460 * analog watchdog threshold high (on 8 bits):
2461 * LL_ADC_SetAnalogWDThresholds
2462 * (< ADCx param >,
2463 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
2464 * );
2465 * @param __ADC_INSTANCE__ ADC instance
2466 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2467 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2468 * @arg @ref LL_ADC_RESOLUTION_12B
2469 * @arg @ref LL_ADC_RESOLUTION_10B
2470 * @arg @ref LL_ADC_RESOLUTION_8B
2471 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2472 * (1): Specific to ADC instance: ADC1, ADC2
2473 * (2): Specific to ADC instance: ADC4
2474 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 instance
2475 * __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 instance
2476 * @retval In case of ADC1 instance, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF
2477 * In case of ADC4 instance, Value between Min_Data=0x000 and Max_Data=0xFFF
2478 */
2479 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2480 (((__ADC_INSTANCE__) == ADC4) \
2481 ? \
2482 ((__AWD_THRESHOLD__) << (((((__ADC_RESOLUTION__) - ADC_RESOLUTION_ADC4_PROCESSING) & ADC_CFGR1_RES)) \
2483 >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
2484 : \
2485 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
2486 )
2487
2488 /**
2489 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2490 * or low in function of ADC resolution, when ADC resolution is
2491 * different of 14 bits in case of ADC1 or ADC2, 12 bits in case of ADC4.
2492 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2493 * Example, with a ADC resolution of 8 bits, to get the value of
2494 * analog watchdog threshold high (on 8 bits):
2495 * < threshold_value_8_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2496 * (LL_ADC_RESOLUTION_8B,
2497 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2498 * );
2499 * @param __ADC_INSTANCE__ ADC instance
2500 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2501 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2502 * @arg @ref LL_ADC_RESOLUTION_12B
2503 * @arg @ref LL_ADC_RESOLUTION_10B
2504 * @arg @ref LL_ADC_RESOLUTION_8B
2505 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2506 * (1): Specific to ADC instance: ADC1, ADC2
2507 * (2): Specific to ADC instance: ADC4
2508 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 instance
2509 * __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 instance
2510 * @retval In case of ADC1 instance, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF
2511 * In case of ADC4 instance, Value between Min_Data=0x000 and Max_Data=0xFFF
2512 */
2513 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2514 (((__ADC_INSTANCE__) == ADC4) \
2515 ? \
2516 ((__AWD_THRESHOLD__) >> (((((__ADC_RESOLUTION__) - ADC_RESOLUTION_ADC4_PROCESSING) & ADC_CFGR1_RES)) \
2517 >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
2518 : \
2519 ((__AWD_THRESHOLD__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
2520 )
2521
2522 /**
2523 * @brief Helper macro to set the ADC calibration value with both single ended
2524 * and differential modes calibration factors concatenated.
2525 * @note To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().
2526 * Example, to set calibration factors single ended to 0x55
2527 * and differential ended to 0x2A:
2528 * LL_ADC_SetCalibrationOffsetFactor(
2529 * ADC1,
2530 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2531 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2532 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2533 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2534 */
2535 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2536 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_SINGLEDIFF_CALIB_F_BIT_D_POS) | (__CALIB_FACTOR_SINGLE_ENDED__))
2537
2538 #if defined(ADC_MULTIMODE_SUPPORT)
2539 /**
2540 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2541 * or ADC slave from raw value with both ADC conversion data concatenated.
2542 * @note This macro is intended to be used when multimode transfer by DMA
2543 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2544 * In this case the transferred data need to processed with this macro
2545 * to separate the conversion data of ADC master and ADC slave.
2546 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2547 * @arg @ref LL_ADC_MULTI_MASTER
2548 * @arg @ref LL_ADC_MULTI_SLAVE
2549 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2550 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2551 */
2552 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2553 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2554 #endif /* ADC_MULTIMODE_SUPPORT */
2555
2556 /**
2557 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2558 * it has a dependence in multimode (ADC master of the corresponding
2559 * ADC common instance).
2560 * @note In case of device with multimode available and a mix of
2561 * ADC instances compliant and not compliant with multimode feature,
2562 * ADC instances not compliant with multimode feature are
2563 * considered as master instances (do not depend to
2564 * any other ADC instance).
2565 * @param __ADCx__ ADC instance
2566 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2567 */
2568 #if defined(ADC2)
2569 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2570 (((__ADCx__) == ADC2) ? (ADC1) : (__ADCx__))
2571 #else
2572 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) (__ADCx__)
2573 #endif /* ADC2 */
2574 /**
2575 * @brief Helper macro to select the ADC common instance
2576 * to which is belonging the selected ADC instance.
2577 * @note ADC common register instance can be used for:
2578 * - Set parameters common to several ADC instances
2579 * - Multimode (for devices with several ADC instances)
2580 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2581 * @param __ADCx__ ADC instance
2582 * @retval ADC common register instance
2583 */
2584 #if defined(ADC2)
2585 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2586 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) ? (ADC12_COMMON) : (ADC4_COMMON))
2587 #else
2588 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2589 (((__ADCx__) == ADC1) ? (ADC12_COMMON) : (ADC4_COMMON))
2590 #endif /* ADC2 */
2591
2592 /**
2593 * @brief Helper macro to check if all ADC instances sharing the same
2594 * ADC common instance are disabled.
2595 * @note This check is required by functions with setting conditioned to
2596 * ADC state:
2597 * All ADC instances of the ADC common group must be disabled.
2598 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2599 * @note On devices with only 1 ADC common instance, parameter of this macro
2600 * is useless and can be ignored (parameter kept for compatibility
2601 * with devices featuring several ADC common instances).
2602 * @param __ADCXY_COMMON__ ADC common instance
2603 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2604 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2605 * are disabled.
2606 * Value "1" if at least one ADC instance sharing the same ADC common instance
2607 * is enabled.
2608 */
2609 #if defined(ADC2)
2610 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2611 (((__ADCXY_COMMON__) == ADC12_COMMON) ? (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2)) : (LL_ADC_IsEnabled(ADC4)))
2612 #else
2613 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2614 (((__ADCXY_COMMON__) == ADC12_COMMON) ? (LL_ADC_IsEnabled(ADC1)) : (LL_ADC_IsEnabled(ADC4)))
2615 #endif /* ADC2 */
2616
2617 /**
2618 * @brief Helper macro to define the ADC conversion data full-scale digital
2619 * value corresponding to the selected ADC resolution.
2620 * @note ADC conversion data full-scale corresponds to voltage range
2621 * determined by analog voltage references Vref+ and Vref-
2622 * (refer to reference manual).
2623 * @param __ADC_INSTANCE__ ADC instance
2624 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2625 * @arg @ref LL_ADC_RESOLUTION_14B
2626 * @arg @ref LL_ADC_RESOLUTION_12B
2627 * @arg @ref LL_ADC_RESOLUTION_10B
2628 * @arg @ref LL_ADC_RESOLUTION_8B
2629 * @arg @ref LL_ADC_RESOLUTION_6B
2630 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2631 */
2632 #define __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \
2633 (0x3FFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2634
2635 /**
2636 * @brief Helper macro to convert the ADC conversion data from
2637 * a resolution to another resolution.
2638 * @param __ADC_INSTANCE__ ADC instance
2639 * @param __DATA__ ADC conversion data to be converted
2640 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2641 * This parameter can be one of the following values:
2642 * @arg @ref LL_ADC_RESOLUTION_14B
2643 * @arg @ref LL_ADC_RESOLUTION_12B
2644 * @arg @ref LL_ADC_RESOLUTION_10B
2645 * @arg @ref LL_ADC_RESOLUTION_8B
2646 * @arg @ref LL_ADC_RESOLUTION_6B
2647 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2648 * This parameter can be one of the following values:
2649 * @arg @ref LL_ADC_RESOLUTION_14B
2650 * @arg @ref LL_ADC_RESOLUTION_12B
2651 * @arg @ref LL_ADC_RESOLUTION_10B
2652 * @arg @ref LL_ADC_RESOLUTION_8B
2653 * @arg @ref LL_ADC_RESOLUTION_6B
2654 * @retval ADC conversion data to the requested resolution
2655 */
2656 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__ADC_INSTANCE__, __DATA__,\
2657 __ADC_RESOLUTION_CURRENT__,\
2658 __ADC_RESOLUTION_TARGET__) \
2659 (((__DATA__) \
2660 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2661 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2662 )
2663
2664 /**
2665 * @brief Helper macro to calculate the voltage (unit: mVolt)
2666 * corresponding to a ADC conversion data (unit: digital value).
2667 * @note Analog reference voltage (Vref+) must be either known from
2668 * user board environment or can be calculated using ADC measurement
2669 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2670 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2671 * @param __ADC_DATA__ ADC conversion data (resolution 16 bits)
2672 * (unit: digital value).
2673 * @param __ADC_INSTANCE__ ADC instance
2674 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2675 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2676 * @arg @ref LL_ADC_RESOLUTION_12B
2677 * @arg @ref LL_ADC_RESOLUTION_10B
2678 * @arg @ref LL_ADC_RESOLUTION_8B
2679 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2680 * (1): Specific to ADC instance: ADC1, ADC2
2681 * (2): Specific to ADC instance: ADC4
2682 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2683 */
2684 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__,\
2685 __ADC_DATA__, \
2686 __ADC_RESOLUTION__) \
2687 ((__ADC_DATA__) * (int32_t)(__VREFANALOG_VOLTAGE__) \
2688 / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__)) \
2689 )
2690
2691 /**
2692 * @brief Helper macro to calculate the voltage (unit: mVolt)
2693 * corresponding to a ADC conversion data (unit: digital value) in
2694 * differential ended mode.
2695 * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2.
2696 * @note ADC data from ADC data register is unsigned and centered around
2697 * middle code in. Converted voltage can be positive or negative
2698 * depending on differential input voltages.
2699 * @note Analog reference voltage (Vref+) must be either known from
2700 * user board environment or can be calculated using ADC measurement
2701 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2702 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2703 * @param __ADC_DATA__ ADC conversion data (unit: digital value).
2704 * @param __ADC_INSTANCE__ ADC instance
2705 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2706 * @arg @ref LL_ADC_RESOLUTION_14B
2707 * @arg @ref LL_ADC_RESOLUTION_12B
2708 * @arg @ref LL_ADC_RESOLUTION_10B
2709 * @arg @ref LL_ADC_RESOLUTION_8B
2710 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2711 */
2712 #define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__, \
2713 __ADC_DATA__, \
2714 __ADC_RESOLUTION__) \
2715 ((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__) \
2716 / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__)) - (int32_t)(__VREFANALOG_VOLTAGE__))
2717
2718 /**
2719 * @brief Helper macro to calculate analog reference voltage (Vref+)
2720 * (unit: mVolt) from ADC conversion data of internal voltage
2721 * reference VrefInt.
2722 * @note Computation is using VrefInt calibration value
2723 * stored in system memory for each device during production.
2724 * @note This voltage depends on user board environment: voltage level
2725 * connected to pin Vref+.
2726 * On devices with small package, the pin Vref+ is not present
2727 * and internally bonded to pin Vdda.
2728 * @note On this STM32 series, calibration data of internal voltage reference
2729 * VrefInt corresponds to a resolution of 16 bits,
2730 * this is the recommended ADC resolution to convert voltage of
2731 * internal voltage reference VrefInt.
2732 * Otherwise, this macro performs the processing to scale
2733 * ADC conversion data to 14 bits.
2734 * @param __ADC_INSTANCE__ ADC instance
2735 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)
2736 * of internal voltage reference VrefInt (unit: digital value).
2737 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2738 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2739 * @arg @ref LL_ADC_RESOLUTION_12B
2740 * @arg @ref LL_ADC_RESOLUTION_10B
2741 * @arg @ref LL_ADC_RESOLUTION_8B
2742 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2743 * (1): Specific to ADC instance: ADC1, ADC2
2744 * (2): Specific to ADC instance: ADC4
2745 * @retval Analog reference voltage (unit: mV)
2746 */
2747 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__ADC_INSTANCE__, __VREFINT_ADC_DATA__, \
2748 __ADC_RESOLUTION__) \
2749 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2750 / __LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), \
2751 (__VREFINT_ADC_DATA__), \
2752 (__ADC_RESOLUTION__), \
2753 LL_ADC_RESOLUTION_14B) \
2754 )
2755
2756 /**
2757 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2758 * from ADC conversion data of internal temperature sensor.
2759 * @note Computation is using temperature sensor calibration values
2760 * stored in system memory for each device during production.
2761 * @note Calculation formula:
2762 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2763 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2764 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2765 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2766 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2767 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2768 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2769 * TEMP_DEGC_CAL1 (calibrated in factory)
2770 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2771 * TEMP_DEGC_CAL2 (calibrated in factory)
2772 * Caution: Calculation relevancy under reserve that calibration
2773 * parameters are correct (address and data).
2774 * To calculate temperature using temperature sensor
2775 * datasheet typical values (generic values less, therefore
2776 * less accurate than calibrated values),
2777 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2778 * @note As calculation input, the analog reference voltage (Vref+) must be
2779 * defined as it impacts the ADC LSB equivalent voltage.
2780 * @note Analog reference voltage (Vref+) must be either known from
2781 * user board environment or can be calculated using ADC measurement
2782 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2783 * @note On this STM32 series, calibration data of temperature sensor
2784 * corresponds to a resolution of 14 bits,
2785 * this is the recommended ADC resolution to convert voltage of
2786 * temperature sensor.
2787 * Otherwise, this macro performs the processing to scale
2788 * ADC conversion data to 14 bits.
2789 * @param __ADC_INSTANCE__ ADC instance
2790 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2791 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2792 * temperature sensor (unit: digital value).
2793 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2794 * sensor voltage has been measured.
2795 * This parameter can be one of the following values:
2796 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2797 * @arg @ref LL_ADC_RESOLUTION_12B
2798 * @arg @ref LL_ADC_RESOLUTION_10B
2799 * @arg @ref LL_ADC_RESOLUTION_8B
2800 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2801 * (1): Specific to ADC instance: ADC1, ADC2
2802 * (2): Specific to ADC instance: ADC4
2803 * @retval Temperature (unit: degree Celsius)
2804 */
2805 #define __LL_ADC_CALC_TEMPERATURE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__,\
2806 __TEMPSENSOR_ADC_DATA__,\
2807 __ADC_RESOLUTION__) \
2808 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), \
2809 (__TEMPSENSOR_ADC_DATA__), \
2810 (__ADC_RESOLUTION__), \
2811 LL_ADC_RESOLUTION_14B) \
2812 * (__VREFANALOG_VOLTAGE__)) \
2813 / TEMPSENSOR_CAL_VREFANALOG) \
2814 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2815 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2816 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2817 ) + TEMPSENSOR_CAL1_TEMP \
2818 )
2819
2820 /**
2821 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2822 * from ADC conversion data of internal temperature sensor.
2823 * @note Computation is using temperature sensor typical values
2824 * (refer to device datasheet).
2825 * @note Calculation formula:
2826 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2827 * / Avg_Slope + CALx_TEMP
2828 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2829 * (unit: digital value)
2830 * Avg_Slope = temperature sensor slope
2831 * (unit: uV/Degree Celsius)
2832 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2833 * temperature CALx_TEMP (unit: mV)
2834 * Caution: Calculation relevancy under reserve the temperature sensor
2835 * of the current device has characteristics in line with
2836 * datasheet typical values.
2837 * If temperature sensor calibration values are available on
2838 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2839 * temperature calculation will be more accurate using
2840 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2841 * @note As calculation input, the analog reference voltage (Vref+) must be
2842 * defined as it impacts the ADC LSB equivalent voltage.
2843 * @note Analog reference voltage (Vref+) must be either known from
2844 * user board environment or can be calculated using ADC measurement
2845 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2846 * @note ADC measurement data must correspond to a resolution of 14 bits
2847 * (full scale digital value 4095). If not the case, the data must be
2848 * preliminarily rescaled to an equivalent resolution of 14 bits.
2849 * @param __ADC_INSTANCE__ ADC instance
2850 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
2851 * (unit: uV/DegCelsius).
2852 * On STM32U5, refer to device datasheet parameter "Avg_Slope".
2853 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
2854 * (at temperature and Vref+ defined in parameters below) (unit: mV).
2855 * On STM32U5, refer to device datasheet parameter "V30"
2856 * (corresponding to TS_CAL1).
2857 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
2858 * see parameter above) is corresponding (unit: mV)
2859 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2860 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2861 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2862 * This parameter can be one of the following values:
2863 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2864 * @arg @ref LL_ADC_RESOLUTION_12B
2865 * @arg @ref LL_ADC_RESOLUTION_10B
2866 * @arg @ref LL_ADC_RESOLUTION_8B
2867 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2868 * (1): Specific to ADC instance: ADC1, ADC2
2869 * (2): Specific to ADC instance: ADC4
2870 * @retval Temperature (unit: degree Celsius)
2871 */
2872 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__ADC_INSTANCE__, __TEMPSENSOR_TYP_AVGSLOPE__, \
2873 __TEMPSENSOR_TYP_CALX_V__, \
2874 __TEMPSENSOR_CALX_TEMP__, \
2875 __VREFANALOG_VOLTAGE__, \
2876 __TEMPSENSOR_ADC_DATA__, \
2877 __ADC_RESOLUTION__) \
2878 ((( ((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2879 / __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__)) \
2880 * 1000UL) \
2881 - \
2882 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2883 * 1000UL) \
2884 ) \
2885 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2886 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2887 )
2888
2889 /**
2890 * @}
2891 */
2892
2893 /**
2894 * @}
2895 */
2896
2897 /* Exported functions --------------------------------------------------------*/
2898 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2899 * @{
2900 */
2901
2902 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2903 * @{
2904 */
2905 #if defined(ADC_MULTIMODE_SUPPORT)
2906 /**
2907 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2908 * ADC register address from ADC instance and a list of ADC registers
2909 * intended to be used (most commonly) with DMA transfer.
2910 * @note These ADC registers are data registers:
2911 * when ADC conversion data is available in ADC data registers,
2912 * ADC generates a DMA transfer request.
2913 * @note This macro is intended to be used with LL DMA driver, refer to
2914 * function "LL_DMA_ConfigAddresses()".
2915 * Example:
2916 * LL_DMA_ConfigAddresses(DMA1,
2917 * LL_DMA_CHANNEL_1,
2918 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2919 * (uint32_t)&< array or variable >,
2920 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2921 * @note For devices with several ADC: in multimode, some devices
2922 * use a different data register outside of ADC instance scope
2923 * (common data register). This macro manages this register difference,
2924 * only ADC instance has to be set as parameter.
2925 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2926 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2927 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2928 * @param ADCx ADC instance
2929 * @param RegisterValue This parameter can be one of the following values:
2930 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2931 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2932 *
2933 * (1) Available on devices with several ADC instances.
2934 * @retval ADC register address
2935 */
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t RegisterValue)2936 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t RegisterValue)
2937 {
2938 uint32_t data_reg_addr;
2939
2940 if (RegisterValue == LL_ADC_DMA_REG_REGULAR_DATA)
2941 {
2942 /* Retrieve address of register DR */
2943 data_reg_addr = (uint32_t) &(ADCx->DR);
2944 }
2945 else /* (RegisterValue == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2946 {
2947 /* Retrieve address of register CDR */
2948 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2949 }
2950
2951 return data_reg_addr;
2952 }
2953 #else
2954 /**
2955 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2956 * ADC register address from ADC instance and a list of ADC registers
2957 * intended to be used (most commonly) with DMA transfer.
2958 * @note These ADC registers are data registers:
2959 * when ADC conversion data is available in ADC data registers,
2960 * ADC generates a DMA transfer request.
2961 * @note This macro is intended to be used with LL DMA driver, refer to
2962 * function "LL_DMA_ConfigAddresses()".
2963 * Example:
2964 * LL_DMA_ConfigAddresses(DMA1,
2965 * LL_DMA_CHANNEL_1,
2966 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2967 * (uint32_t)&< array or variable >,
2968 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2969 * @note For devices with several ADC: in multimode, some devices
2970 * use a different data register outside of ADC instance scope
2971 * (common data register). This macro manages this register difference,
2972 * only ADC instance has to be set as parameter.
2973 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr
2974 * @param ADCx ADC instance
2975 * @param RegisterValue This parameter can be one of the following values:
2976 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2977 * @retval ADC register address
2978 */
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t RegisterValue)2979 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t RegisterValue)
2980 {
2981 /* Prevent unused argument(s) compilation warning */
2982 (void)(RegisterValue);
2983
2984 /* Retrieve address of register DR */
2985 return (uint32_t) &(ADCx->DR);
2986 }
2987 #endif /* ADC_MULTIMODE_SUPPORT */
2988
2989 /**
2990 * @}
2991 */
2992
2993 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope:
2994 * common to several ADC instances
2995 * @{
2996 */
2997
2998 /**
2999 * @brief Set parameter common to several ADC: Clock source and prescaler.
3000 * @note On this STM32 series, if ADC group injected is used, some
3001 * clock ratio constraints between ADC clock and AHB clock
3002 * must be respected.
3003 * Refer to reference manual.
3004 * @note On this STM32 series, setting of this feature is conditioned to
3005 * ADC state:
3006 * All ADC instances of the ADC common group must be disabled.
3007 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3008 * ADC instance or by using helper macro helper macro
3009 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3010 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
3011 * CCR PRESC LL_ADC_SetCommonClock
3012 * @param ADCxy_COMMON ADC common instance
3013 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3014 * @param CommonClock This parameter can be one of the following values:
3015 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
3016 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
3017 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
3018 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
3019 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
3020 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
3021 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
3022 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
3023 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
3024 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
3025 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
3026 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3027 * @retval None
3028 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)3029 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
3030 {
3031 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
3032 }
3033
3034 /**
3035 * @brief Get parameter common to several ADC: Clock source and prescaler.
3036 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
3037 * CCR PRESC LL_ADC_GetCommonClock
3038 * @param ADCxy_COMMON ADC common instance
3039 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3040 * @retval Returned value can be one of the following values:
3041 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
3042 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
3043 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
3044 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
3045 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
3046 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
3047 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
3048 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
3049 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
3050 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
3051 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
3052 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3053 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)3054 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
3055 {
3056 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
3057 }
3058
3059 /**
3060 * @brief Set parameter common to several ADC: measurement path to
3061 * internal channels (VrefInt, temperature sensor, ...).
3062 * Add paths to the current configuration.
3063 * @note One or several values can be selected.
3064 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3065 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3066 * @note Stabilization time of measurement path to internal channel:
3067 * After enabling internal paths, before starting ADC conversion,
3068 * a delay is required for internal voltage reference and
3069 * temperature sensor stabilization time.
3070 * Refer to device datasheet.
3071 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3072 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3073 * @note ADC internal channel sampling time constraint:
3074 * For ADC conversion of internal channels,
3075 * a sampling time minimum value is required.
3076 * Refer to device datasheet.
3077 * @note On this STM32 series, setting of this feature is conditioned to
3078 * ADC state:
3079 * All ADC instances of the ADC common group must be disabled.
3080 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3081 * ADC instance or by using helper macro helper macro
3082 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3083 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
3084 * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n
3085 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
3086 * @param ADCxy_COMMON ADC common instance
3087 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3088 * @param PathInternal This parameter can be a combination of the following values:
3089 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3090 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3091 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3092 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3093 * @retval None
3094 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3095 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3096 {
3097 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
3098 }
3099
3100 /**
3101 * @brief Set parameter common to several ADC: measurement path to
3102 * internal channels (VrefInt, temperature sensor, ...).
3103 * Remove paths to the current configuration.
3104 * @note One or several values can be selected.
3105 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3106 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3107 * @note On this STM32 series, setting of this feature is conditioned to
3108 * ADC state:
3109 * All ADC instances of the ADC common group must be disabled.
3110 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3111 * ADC instance or by using helper macro helper macro
3112 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3113 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
3114 * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n
3115 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
3116 * @param ADCxy_COMMON ADC common instance
3117 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3118 * @param PathInternal This parameter can be a combination of the following values:
3119 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3120 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3121 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3122 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3123 * @retval None
3124 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3125 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3126 {
3127 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
3128 }
3129
3130 /**
3131 * @brief Set parameter common to several ADC: measurement path to internal
3132 * channels (VrefInt, temperature sensor, ...).
3133 * @note One or several values can be selected.
3134 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3135 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3136 * @note Stabilization time of measurement path to internal channel:
3137 * After enabling internal paths, before starting ADC conversion,
3138 * a delay is required for internal voltage reference and
3139 * temperature sensor stabilization time.
3140 * Refer to device datasheet.
3141 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3142 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
3143 * @note ADC internal channel sampling time constraint:
3144 * For ADC conversion of internal channels,
3145 * a sampling time minimum value is required.
3146 * Refer to device datasheet.
3147 * @note On this STM32 series, setting of this feature is conditioned to
3148 * ADC state:
3149 * All ADC instances of the ADC common group must be disabled.
3150 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3151 * ADC instance or by using helper macro helper macro
3152 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3153 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
3154 * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n
3155 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
3156 * @param ADCxy_COMMON ADC common instance
3157 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3158 * @param PathInternal This parameter can be a combination of the following values:
3159 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3160 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3161 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3162 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3163 * @retval None
3164 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3165 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3166 {
3167 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN, PathInternal);
3168 }
3169
3170 /**
3171 * @brief Get parameter common to several ADC: measurement path to internal
3172 * channels (VrefInt, temperature sensor, ...).
3173 * @note One or several values can be selected.
3174 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3175 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3176 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
3177 * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n
3178 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
3179 * @param ADCxy_COMMON ADC common instance
3180 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3181 * @retval Returned value can be a combination of the following values:
3182 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3183 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3184 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3185 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3186 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)3187 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
3188 {
3189 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN));
3190 }
3191
3192 /**
3193 * @}
3194 */
3195
3196 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
3197 * @{
3198 */
3199
3200 /**
3201 * @brief Set ADC calibration factor in the mode single-ended
3202 * or differential (for devices with differential mode available).
3203 * @note This function is intended to set calibration parameters
3204 * without having to perform a new calibration using
3205 * @ref LL_ADC_StartCalibration().
3206 * @note For devices with differential mode available:
3207 * Calibration of offset is specific to each of
3208 * single-ended and differential modes
3209 * (calibration factor must be specified for each of these
3210 * differential modes, if used afterwards and if the application
3211 * requires their calibration).
3212 * Calibration of linearity is common to both
3213 * single-ended and differential modes
3214 * (calibration factor can be specified only once).
3215 * @note In case of setting calibration factors of both modes single ended
3216 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
3217 * both calibration factors must be concatenated.
3218 * To perform this processing, use helper macro
3219 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
3220 * @note On this STM32 series, setting of this feature is conditioned to
3221 * ADC state:
3222 * ADC must be enabled, without calibration on going, without conversion
3223 * on going on group regular.
3224 * @param ADCx ADC instance
3225 * @param SingleDiff This parameter can be one of the following values:
3226 * @arg @ref LL_ADC_SINGLE_ENDED
3227 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3228 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
3229 * @param CalibrationFactor Value between Min_Data=0x0000 and Max_Data=0xFFFF
3230 * @retval None
3231 */
LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)3232 __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff,
3233 uint32_t CalibrationFactor)
3234 {
3235 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
3236 {
3237 /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
3238 therefore they are not cleared in this function. */
3239 MODIFY_REG(ADCx->CR, ADC_CR_CALINDEX, (0UL << ADC_CR_CALINDEX_Pos)); /* CalibIndex == 0 */
3240 MODIFY_REG(ADCx->CALFACT2,
3241 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
3242 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) \
3243 >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) \
3244 & ~(SingleDiff & ADC_CALFACT2_CALFACT_S)));
3245 SET_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
3246 }
3247 else
3248 {
3249 MODIFY_REG(ADCx->CALFACT, ADC4_CALFACT_CALFACT, CalibrationFactor);
3250 }
3251 }
3252
3253 /**
3254 * @brief Get ADC calibration factor in the mode single-ended
3255 * or differential (for devices with differential mode available).
3256 * @note Calibration factors are set by hardware after performing
3257 * a calibration run using function @ref LL_ADC_StartCalibration().
3258 * @note For devices with differential mode available:
3259 * Calibration of offset is specific to each of
3260 * single-ended and differential modes
3261 * Calibration of linearity is common to both
3262 * single-ended and differential modes
3263 * @param ADCx ADC instance
3264 * @param SingleDiff This parameter can be one of the following values:
3265 * @arg @ref LL_ADC_SINGLE_ENDED
3266 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3267 * @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF
3268 */
LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff)3269 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
3270 {
3271 /* Retrieve bits with position in register depending on parameter */
3272 /* "SingleDiff". */
3273 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
3274 /* containing other bits reserved for other purpose. */
3275 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
3276 {
3277 /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
3278 therefore they are not cleared in this function. */
3279 uint32_t temp_CalibOffset;
3280 SET_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
3281 MODIFY_REG(ADCx->CR, ADC_CR_CALINDEX, (0UL << ADC_CR_CALINDEX_Pos)); /* CalibIndex == 0 */
3282 temp_CalibOffset = (READ_BIT(ADCx->CALFACT2, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) \
3283 >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
3284 return temp_CalibOffset;
3285 }
3286 else
3287 {
3288 return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC4_CALFACT_CALFACT));
3289 }
3290 }
3291
3292 /**
3293 * @brief Set ADC Linear calibration factor in the mode single-ended.
3294 * @note This function is intended to set linear calibration parameters
3295 * without having to perform a new calibration using
3296 * @ref LL_ADC_StartCalibration().
3297 * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2.
3298 * @note On this STM32 series, setting of this feature is conditioned to
3299 * ADC state:
3300 * ADC must be enabled, without calibration on going, without conversion
3301 * on going on group regular.
3302 * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor\n
3303 * CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
3304 * @param ADCx ADC instance (on STM32U5, feature available on ADC instances: ADC1, ADC2)
3305 * @param LinearityWord This parameter can be one of the following values:
3306 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX1
3307 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX2
3308 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX3
3309 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX4
3310 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX5
3311 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX6
3312 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX7
3313 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
3314 * @retval None
3315 */
LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef * ADCx,uint32_t LinearityWord,uint32_t CalibrationFactor)3316 __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord,
3317 uint32_t CalibrationFactor)
3318 {
3319 /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
3320 therefore they are not cleared in this function. */
3321 MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX),
3322 LinearityWord); /* LinearityWord == CalibIndex (1 to 7 for linearity reading) */
3323 MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_CALFACT, CalibrationFactor);
3324 SET_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
3325 }
3326
3327 /**
3328 * @brief Get ADC Linear calibration factor in the mode single-ended.
3329 * @note Calibration factors are set by hardware after performing
3330 * a calibration run using function @ref LL_ADC_StartCalibration().
3331 * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2.
3332 * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor\n
3333 * CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
3334 * @param ADCx ADC instance (on STM32U5, feature available on ADC instances: ADC1, ADC2)
3335 * @param LinearityWord This parameter can be one of the following values:
3336 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX1
3337 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX2
3338 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX3
3339 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX4
3340 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX5
3341 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX6
3342 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX7
3343 * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
3344 */
LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef * ADCx,uint32_t LinearityWord)3345 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
3346 {
3347 uint32_t temp_calib_linearity;
3348
3349 /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
3350 therefore they are not cleared in this function. */
3351 SET_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
3352 MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX),
3353 LinearityWord); /* LinearityWord == CalibIndex (1 to 7 for linearity reading) */
3354 temp_calib_linearity = (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_CALFACT_Msk));
3355 return temp_calib_linearity;
3356 }
3357 /**
3358 * @brief Set ADC resolution.
3359 * Refer to reference manual for alignments formats
3360 * dependencies to ADC resolutions.
3361 * @note On this STM32 series, setting of this feature is conditioned to
3362 * ADC state:
3363 * ADC must be disabled or enabled without conversion on going
3364 * on either groups regular or injected.
3365 * @rmtoll CFGR RES LL_ADC_SetResolution
3366 * @param ADCx ADC instance
3367 * @param Resolution This parameter can be one of the following values:
3368 * @arg @ref LL_ADC_RESOLUTION_14B (1)
3369 * @arg @ref LL_ADC_RESOLUTION_12B
3370 * @arg @ref LL_ADC_RESOLUTION_10B
3371 * @arg @ref LL_ADC_RESOLUTION_8B
3372 * @arg @ref LL_ADC_RESOLUTION_6B (2)
3373 * (1): Specific to ADC instance: ADC1, ADC2
3374 * (2): Specific to ADC instance: ADC4
3375 * @retval None
3376 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)3377 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
3378 {
3379 uint32_t tmp_resolution = Resolution;
3380 if (ADCx == ADC4)
3381 {
3382 tmp_resolution = ((tmp_resolution - ADC_RESOLUTION_ADC4_PROCESSING) & ADC_CFGR1_RES);
3383 }
3384
3385 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, tmp_resolution);
3386 }
3387
3388 /**
3389 * @brief Get ADC resolution.
3390 * Refer to reference manual for alignments formats
3391 * dependencies to ADC resolutions.
3392 * @rmtoll CFGR RES LL_ADC_GetResolution
3393 * @param ADCx ADC instance
3394 * @retval Returned value can be one of the following values:
3395 * @arg @ref LL_ADC_RESOLUTION_14B (1)
3396 * @arg @ref LL_ADC_RESOLUTION_12B
3397 * @arg @ref LL_ADC_RESOLUTION_10B
3398 * @arg @ref LL_ADC_RESOLUTION_8B
3399 * @arg @ref LL_ADC_RESOLUTION_6B (2)
3400 * (1): Specific to ADC instance: ADC1, ADC2
3401 * (2): Specific to ADC instance: ADC4
3402 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)3403 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
3404 {
3405 uint32_t tmp_resolution = (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
3406
3407 if (ADCx == ADC4)
3408 {
3409 tmp_resolution = (tmp_resolution + (ADC_RESOLUTION_ADC4_PROCESSING << ADC_CFGR1_RES_Pos));
3410 }
3411
3412 return tmp_resolution;
3413 }
3414
3415 /**
3416 * @brief Set ADC conversion data alignment.
3417 * @note Refer to reference manual for alignments formats
3418 * dependencies to ADC resolutions.
3419 * @note On this STM32 series, setting of this feature is conditioned to
3420 * ADC state:
3421 * ADC must be disabled or enabled without conversion on going
3422 * on group regular.
3423 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
3424 * @param ADCx ADC instance
3425 * @param DataAlignment This parameter can be one of the following values:
3426 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3427 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3428 * @retval None
3429 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)3430 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
3431 {
3432 MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_ALIGN, DataAlignment);
3433 }
3434
3435 /**
3436 * @brief Get ADC conversion data alignment.
3437 * @note Refer to reference manual for alignments formats
3438 * dependencies to ADC resolutions.
3439 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
3440 * @param ADCx ADC instance
3441 * @retval Returned value can be one of the following values:
3442 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3443 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3444 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)3445 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
3446 {
3447 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_ALIGN));
3448 }
3449
3450 /**
3451 * @brief Set ADC low power mode.
3452 * @note Description of ADC low power modes:
3453 * - ADC low power mode "auto wait": Dynamic low power mode,
3454 * ADC conversions occurrences are limited to the minimum necessary
3455 * in order to reduce power consumption.
3456 * New ADC conversion starts only when the previous
3457 * unitary conversion data (for ADC group regular)
3458 * or previous sequence conversions data (for ADC group injected)
3459 * has been retrieved by user software.
3460 * In the meantime, ADC remains idle: does not performs any
3461 * other conversion.
3462 * This mode allows to automatically adapt the ADC conversions
3463 * triggers to the speed of the software that reads the data.
3464 * Moreover, this avoids risk of overrun for low frequency
3465 * applications.
3466 * How to use this low power mode:
3467 * - It is not recommended to use with interruption or DMA
3468 * since these modes have to clear immediately the EOC flag
3469 * (by CPU to free the IRQ pending event or by DMA).
3470 * Auto wait will work but fort a very short time, discarding
3471 * its intended benefit (except specific case of high load of CPU
3472 * or DMA transfers which can justify usage of auto wait).
3473 * - Do use with polling: 1. Start conversion,
3474 * 2. Later on, when conversion data is needed: poll for end of
3475 * conversion to ensure that conversion is completed and
3476 * retrieve ADC conversion data. This will trig another
3477 * ADC conversion start.
3478 * - ADC low power mode "auto power-off" (feature available on
3479 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3480 * the ADC automatically powers-off after a conversion and
3481 * automatically wakes up when a new conversion is triggered
3482 * (with startup time between trigger and start of sampling).
3483 * This feature can be combined with low power mode "auto wait".
3484 * @note With ADC low power mode "auto wait", the ADC conversion data read
3485 * is corresponding to previous ADC conversion start, independently
3486 * of delay during which ADC was idle.
3487 * Therefore, the ADC conversion data may be outdated: does not
3488 * correspond to the current voltage level on the selected
3489 * ADC channel.
3490 * @note On this STM32 series, setting of this feature is conditioned to
3491 * ADC state:
3492 * ADC must be disabled or enabled without conversion on going
3493 * on either groups regular or injected.
3494 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
3495 * @param ADCx ADC instance
3496 * @param LowPowerMode This parameter can be one of the following values:
3497 * @arg @ref LL_ADC_LP_MODE_NONE
3498 * @arg @ref LL_ADC_LP_AUTOWAIT
3499 * @retval None
3500 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)3501 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3502 {
3503 if (ADCx != ADC4) /* ADC1 or ADC2 */
3504 {
3505 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_AUTDLY, LowPowerMode);
3506 }
3507 else
3508 {
3509 MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_WAIT, LowPowerMode);
3510 MODIFY_REG(ADCx->PWRR, ADC4_PWRR_AUTOFF, LowPowerMode);
3511 }
3512 }
3513
3514 /**
3515 * @brief Get ADC low power mode:
3516 * @note Description of ADC low power modes:
3517 * - ADC low power mode "auto wait": Dynamic low power mode,
3518 * ADC conversions occurrences are limited to the minimum necessary
3519 * in order to reduce power consumption.
3520 * New ADC conversion starts only when the previous
3521 * unitary conversion data (for ADC group regular)
3522 * or previous sequence conversions data (for ADC group injected)
3523 * has been retrieved by user software.
3524 * In the meantime, ADC remains idle: does not performs any
3525 * other conversion.
3526 * This mode allows to automatically adapt the ADC conversions
3527 * triggers to the speed of the software that reads the data.
3528 * Moreover, this avoids risk of overrun for low frequency
3529 * applications.
3530 * How to use this low power mode:
3531 * - It is not recommended to use with interruption or DMA
3532 * since these modes have to clear immediately the EOC flag
3533 * (by CPU to free the IRQ pending event or by DMA).
3534 * Auto wait will work but fort a very short time, discarding
3535 * its intended benefit (except specific case of high load of CPU
3536 * or DMA transfers which can justify usage of auto wait).
3537 * - Do use with polling: 1. Start conversion,
3538 * 2. Later on, when conversion data is needed: poll for end of
3539 * conversion to ensure that conversion is completed and
3540 * retrieve ADC conversion data. This will trig another
3541 * ADC conversion start.
3542 * - ADC low power mode "auto power-off" (feature available on
3543 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3544 * the ADC automatically powers-off after a conversion and
3545 * automatically wakes up when a new conversion is triggered
3546 * (with startup time between trigger and start of sampling).
3547 * This feature can be combined with low power mode "auto wait".
3548 * @note With ADC low power mode "auto wait", the ADC conversion data read
3549 * is corresponding to previous ADC conversion start, independently
3550 * of delay during which ADC was idle.
3551 * Therefore, the ADC conversion data may be outdated: does not
3552 * correspond to the current voltage level on the selected
3553 * ADC channel.
3554 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
3555 * @param ADCx ADC instance
3556 * @retval Returned value can be one of the following values:
3557 * @arg @ref LL_ADC_LP_MODE_NONE
3558 * @arg @ref LL_ADC_LP_AUTOWAIT
3559 */
LL_ADC_GetLowPowerMode(const ADC_TypeDef * ADCx)3560 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
3561 {
3562 if (ADCx != ADC4) /* ADC1 or ADC2 */
3563 {
3564 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_AUTDLY));
3565 }
3566 else
3567 {
3568 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_WAIT));
3569 }
3570
3571 }
3572
3573 /**
3574 * @brief Set ADC selected offset number 1, 2, 3 or 4.
3575 * @note This function set the 2 items of offset configuration:
3576 * - ADC channel to which the offset programmed will be applied
3577 * (independently of channel mapped on ADC group regular
3578 * or group injected)
3579 * - Offset level (offset to be subtracted from the raw
3580 * converted data).
3581 * @note Caution: Offset format is dependent to ADC resolution:
3582 * offset has to be left-aligned on bit 11, the LSB (right bits)
3583 * are set to 0.
3584 * @note This function enables the offset, by default. It can be forced
3585 * to disable state using function LL_ADC_SetOffsetState().
3586 * @note If a channel is mapped on several offsets numbers, only the offset
3587 * with the lowest value is considered for the subtraction.
3588 * @note On this STM32 series, setting of this feature is conditioned to
3589 * ADC state:
3590 * ADC must be disabled or enabled without conversion on going
3591 * on either groups regular or injected.
3592 * @note On STM32U5, some fast channels are available: fast analog inputs
3593 * coming from GPIO pads (ADC_IN0..5).
3594 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
3595 * OFR1 OFFSET1 LL_ADC_SetOffset\n
3596 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
3597 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
3598 * OFR2 OFFSET2 LL_ADC_SetOffset\n
3599 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
3600 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
3601 * OFR3 OFFSET3 LL_ADC_SetOffset\n
3602 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
3603 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
3604 * OFR4 OFFSET4 LL_ADC_SetOffset\n
3605 * OFR4 OFFSET4_EN LL_ADC_SetOffset
3606 * @param ADCx ADC instance
3607 * @param Offsety This parameter can be one of the following values:
3608 * @arg @ref LL_ADC_OFFSET_1
3609 * @arg @ref LL_ADC_OFFSET_2
3610 * @arg @ref LL_ADC_OFFSET_3
3611 * @arg @ref LL_ADC_OFFSET_4
3612 * @param Channel This parameter can be one of the following values:
3613 * @arg @ref LL_ADC_CHANNEL_0 (3)
3614 * @arg @ref LL_ADC_CHANNEL_1 (3)
3615 * @arg @ref LL_ADC_CHANNEL_2 (3)
3616 * @arg @ref LL_ADC_CHANNEL_3 (3)
3617 * @arg @ref LL_ADC_CHANNEL_4 (3)
3618 * @arg @ref LL_ADC_CHANNEL_5 (3)
3619 * @arg @ref LL_ADC_CHANNEL_6
3620 * @arg @ref LL_ADC_CHANNEL_7
3621 * @arg @ref LL_ADC_CHANNEL_8
3622 * @arg @ref LL_ADC_CHANNEL_9
3623 * @arg @ref LL_ADC_CHANNEL_10
3624 * @arg @ref LL_ADC_CHANNEL_11
3625 * @arg @ref LL_ADC_CHANNEL_12
3626 * @arg @ref LL_ADC_CHANNEL_13
3627 * @arg @ref LL_ADC_CHANNEL_14
3628 * @arg @ref LL_ADC_CHANNEL_15
3629 * @arg @ref LL_ADC_CHANNEL_16
3630 * @arg @ref LL_ADC_CHANNEL_17
3631 * @arg @ref LL_ADC_CHANNEL_18
3632 * @arg @ref LL_ADC_CHANNEL_19
3633 * @arg @ref LL_ADC_CHANNEL_VREFINT
3634 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3635 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3636 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
3637 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
3638 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
3639 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
3640 *
3641 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
3642 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
3643 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
3644 * Other channels are slow channels (conversion rate: refer to reference manual).
3645 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
3646 * @retval None
3647 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)3648 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3649 {
3650 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3651
3652 MODIFY_REG(*preg,
3653 ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3654 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) << 1UL) | OffsetLevel);
3655 }
3656
3657 /**
3658 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3659 * Channel to which the offset programmed will be applied
3660 * (independently of channel mapped on ADC group regular
3661 * or group injected)
3662 * @note Usage of the returned channel number:
3663 * - To reinject this channel into another function LL_ADC_xxx:
3664 * the returned channel number is only partly formatted on definition
3665 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3666 * with parts of literals LL_ADC_CHANNEL_x or using
3667 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3668 * Then the selected literal LL_ADC_CHANNEL_x can be used
3669 * as parameter for another function.
3670 * - To get the channel number in decimal format:
3671 * process the returned value with the helper macro
3672 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3673 * @note On STM32U5, some fast channels are available: fast analog inputs
3674 * coming from GPIO pads (ADC_IN0..5).
3675 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
3676 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
3677 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
3678 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
3679 * @param ADCx ADC instance
3680 * @param Offsety This parameter can be one of the following values:
3681 * @arg @ref LL_ADC_OFFSET_1
3682 * @arg @ref LL_ADC_OFFSET_2
3683 * @arg @ref LL_ADC_OFFSET_3
3684 * @arg @ref LL_ADC_OFFSET_4
3685 * @retval Returned value can be one of the following values:
3686 * @arg @ref LL_ADC_CHANNEL_0 (3)
3687 * @arg @ref LL_ADC_CHANNEL_1 (3)
3688 * @arg @ref LL_ADC_CHANNEL_2 (3)
3689 * @arg @ref LL_ADC_CHANNEL_3 (3)
3690 * @arg @ref LL_ADC_CHANNEL_4 (3)
3691 * @arg @ref LL_ADC_CHANNEL_5 (3)
3692 * @arg @ref LL_ADC_CHANNEL_6
3693 * @arg @ref LL_ADC_CHANNEL_7
3694 * @arg @ref LL_ADC_CHANNEL_8
3695 * @arg @ref LL_ADC_CHANNEL_9
3696 * @arg @ref LL_ADC_CHANNEL_10
3697 * @arg @ref LL_ADC_CHANNEL_11
3698 * @arg @ref LL_ADC_CHANNEL_12
3699 * @arg @ref LL_ADC_CHANNEL_13
3700 * @arg @ref LL_ADC_CHANNEL_14
3701 * @arg @ref LL_ADC_CHANNEL_15
3702 * @arg @ref LL_ADC_CHANNEL_16
3703 * @arg @ref LL_ADC_CHANNEL_17
3704 * @arg @ref LL_ADC_CHANNEL_18
3705 * @arg @ref LL_ADC_CHANNEL_19
3706 * @arg @ref LL_ADC_CHANNEL_VREFINT
3707 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3708 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3709 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
3710 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
3711 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
3712 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
3713 *
3714 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
3715 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
3716 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
3717 * Other channels are slow channels (conversion rate: refer to reference manual).
3718 * (1, 2) For ADC channel read back from ADC register,
3719 * comparison with internal channel parameter to be done
3720 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3721 */
LL_ADC_GetOffsetChannel(const ADC_TypeDef * ADCx,uint32_t Offsety)3722 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3723 {
3724 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3725
3726 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3727 }
3728
3729 /**
3730 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3731 * Offset level (offset to be subtracted from the raw
3732 * converted data).
3733 * @note Caution: Offset format is dependent to ADC resolution:
3734 * offset has to be left-aligned on bit 11, the LSB (right bits)
3735 * are set to 0.
3736 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3737 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3738 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3739 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3740 * @param ADCx ADC instance
3741 * @param Offsety This parameter can be one of the following values:
3742 * @arg @ref LL_ADC_OFFSET_1
3743 * @arg @ref LL_ADC_OFFSET_2
3744 * @arg @ref LL_ADC_OFFSET_3
3745 * @arg @ref LL_ADC_OFFSET_4
3746 * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
3747 */
LL_ADC_GetOffsetLevel(const ADC_TypeDef * ADCx,uint32_t Offsety)3748 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3749 {
3750 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3751
3752 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3753 }
3754
3755 /**
3756 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3757 * choose offset sign.
3758 * @note On this STM32 series, setting of this feature is conditioned to
3759 * ADC state:
3760 * ADC must be disabled or enabled without conversion on going
3761 * on either groups regular or injected.
3762 * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
3763 * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
3764 * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
3765 * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
3766 * @param ADCx ADC instance
3767 * @param Offsety This parameter can be one of the following values:
3768 * @arg @ref LL_ADC_OFFSET_1
3769 * @arg @ref LL_ADC_OFFSET_2
3770 * @arg @ref LL_ADC_OFFSET_3
3771 * @arg @ref LL_ADC_OFFSET_4
3772 * @param OffsetSign This parameter can be one of the following values:
3773 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3774 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3775 * @retval None
3776 */
LL_ADC_SetOffsetSign(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSign)3777 __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
3778 {
3779 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3780
3781 MODIFY_REG(*preg, ADC_OFR1_OFFSETPOS, OffsetSign);
3782 }
3783
3784 /**
3785 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3786 * offset sign if positive or negative.
3787 * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
3788 * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
3789 * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
3790 * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
3791 * @param ADCx ADC instance
3792 * @param Offsety This parameter can be one of the following values:
3793 * @arg @ref LL_ADC_OFFSET_1
3794 * @arg @ref LL_ADC_OFFSET_2
3795 * @arg @ref LL_ADC_OFFSET_3
3796 * @arg @ref LL_ADC_OFFSET_4
3797 * @retval Returned value can be one of the following values:
3798 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3799 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3800 */
LL_ADC_GetOffsetSign(const ADC_TypeDef * ADCx,uint32_t Offsety)3801 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety)
3802 {
3803 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3804
3805 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
3806 }
3807
3808 /**
3809 * @brief Set Signed saturation for the ADC selected offset number 1, 2, 3 or 4:
3810 * signed offset saturation if enabled or disabled.
3811 * @rmtoll OFR1 SSAT LL_ADC_SetOffsetSignedSaturation\n
3812 * OFR2 SSAT LL_ADC_SetOffsetSignedSaturation\n
3813 * OFR3 SSAT LL_ADC_SetOffsetSignedSaturation\n
3814 * OFR4 SSAT LL_ADC_SetOffsetSignedSaturation
3815 * @param ADCx ADC instance
3816 * @param Offsety This parameter can be one of the following values:
3817 * @arg @ref LL_ADC_OFFSET_1
3818 * @arg @ref LL_ADC_OFFSET_2
3819 * @arg @ref LL_ADC_OFFSET_3
3820 * @arg @ref LL_ADC_OFFSET_4
3821 * @param OffsetSignedSaturation This parameter can be one of the following values:
3822 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
3823 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
3824 * @retval Returned None
3825 */
LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSignedSaturation)3826 __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
3827 uint32_t OffsetSignedSaturation)
3828 {
3829 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3830 MODIFY_REG(*preg, ADC_OFR1_SSAT, OffsetSignedSaturation);
3831 }
3832
3833 /**
3834 * @brief Get Signed saturation for the ADC selected offset number 1, 2, 3 or 4:
3835 * signed offset saturation if enabled or disabled.
3836 * @rmtoll OFR1 SSAT LL_ADC_GetOffsetSignedSaturation\n
3837 * OFR2 SSAT LL_ADC_GetOffsetSignedSaturation\n
3838 * OFR3 SSAT LL_ADC_GetOffsetSignedSaturation\n
3839 * OFR4 SSAT LL_ADC_GetOffsetSignedSaturation
3840 * @param ADCx ADC instance
3841 * @param Offsety This parameter can be one of the following values:
3842 * @arg @ref LL_ADC_OFFSET_1
3843 * @arg @ref LL_ADC_OFFSET_2
3844 * @arg @ref LL_ADC_OFFSET_3
3845 * @arg @ref LL_ADC_OFFSET_4
3846 * @retval Returned value can be one of the following values:
3847 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
3848 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
3849 */
LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef * ADCx,uint32_t Offsety)3850 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
3851 {
3852 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3853 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSAT);
3854 }
3855
3856 /**
3857 * @brief Set Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4:
3858 * signed offset saturation if enabled or disabled.
3859 * @rmtoll OFR1 USAT LL_ADC_SetOffsetUnsignedSaturation\n
3860 * OFR2 USAT LL_ADC_SetOffsetUnsignedSaturation\n
3861 * OFR3 USAT LL_ADC_SetOffsetUnsignedSaturation\n
3862 * OFR4 USAT LL_ADC_SetOffsetUnsignedSaturation
3863 * @param ADCx ADC instance
3864 * @param Offsety This parameter can be one of the following values:
3865 * @arg @ref LL_ADC_OFFSET_1
3866 * @arg @ref LL_ADC_OFFSET_2
3867 * @arg @ref LL_ADC_OFFSET_3
3868 * @arg @ref LL_ADC_OFFSET_4
3869 * @param OffsetUnsignedSaturation This parameter can be one of the following values:
3870 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE
3871 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE
3872 * @retval Returned None
3873 */
LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetUnsignedSaturation)3874 __STATIC_INLINE void LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
3875 uint32_t OffsetUnsignedSaturation)
3876 {
3877 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3878 MODIFY_REG(*preg, ADC_OFR1_USAT, OffsetUnsignedSaturation);
3879 }
3880
3881 /**
3882 * @brief Get Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4:
3883 * signed offset saturation if enabled or disabled.
3884 * @rmtoll OFR1 USAT LL_ADC_GetOffsetUnsignedSaturation\n
3885 * OFR2 USAT LL_ADC_GetOffsetUnsignedSaturation\n
3886 * OFR3 USAT LL_ADC_GetOffsetUnsignedSaturation\n
3887 * OFR4 USAT LL_ADC_GetOffsetUnsignedSaturation
3888 * @param ADCx ADC instance
3889 * @param Offsety This parameter can be one of the following values:
3890 * @arg @ref LL_ADC_OFFSET_1
3891 * @arg @ref LL_ADC_OFFSET_2
3892 * @arg @ref LL_ADC_OFFSET_3
3893 * @arg @ref LL_ADC_OFFSET_4
3894 * @retval Returned value can be one of the following values:
3895 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE
3896 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE
3897 */
LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef * ADCx,uint32_t Offsety)3898 __STATIC_INLINE uint32_t LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
3899 {
3900 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3901 return (uint32_t) READ_BIT(*preg, ADC_OFR1_USAT);
3902 }
3903
3904 /**
3905 * @brief Set ADC gain compensation.
3906 * @note This function set the gain compensation coefficient
3907 * that is applied to raw converted data using the formula:
3908 * DATA = DATA(raw) * (gain compensation coef) / 4096
3909 * @note This function enables the gain compensation if given
3910 * coefficient is above 0, otherwise it disables it.
3911 * @note Gain compensation when enabled is applied to all channels.
3912 * @note On this STM32 series, setting of this feature is conditioned to
3913 * ADC state:
3914 * ADC must be disabled or enabled without conversion on going
3915 * on either groups regular or injected.
3916 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n
3917 * CFGR2 GCOMP LL_ADC_SetGainCompensation
3918 * @param ADCx ADC instance
3919 * @param GainCompensation This parameter can be:
3920 * 0 Gain compensation will be disabled and value set to 0
3921 * 1 -> 16393 Gain compensation will be enabled with specified value
3922 * @retval None
3923 */
LL_ADC_SetGainCompensation(ADC_TypeDef * ADCx,uint32_t GainCompensation)3924 __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
3925 {
3926 MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
3927 MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_GCOMP_GCOMP_Pos);
3928 }
3929
3930 /**
3931 * @brief Get the ADC gain compensation value
3932 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n
3933 * CFGR2 GCOMP LL_ADC_GetGainCompensation
3934 * @param ADCx ADC instance
3935 * @retval Returned value can be:
3936 * 0 Gain compensation is disabled
3937 * 1 -> 16393 Gain compensation is enabled with returned value
3938 */
LL_ADC_GetGainCompensation(const ADC_TypeDef * ADCx)3939 __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx)
3940 {
3941 return ((READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMP) == ADC_GCOMP_GCOMP) \
3942 ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
3943 }
3944
3945 /**
3946 * @}
3947 */
3948
3949 /**
3950 * @brief Set sampling time common to a group of channels.
3951 * @note Unit: ADC clock cycles.
3952 * @note On this STM32 series, sampling time scope is on ADC instance:
3953 * Sampling time common to all channels.
3954 * (on some other STM32 families, sampling time is channel wise)
3955 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3956 * converted:
3957 * sampling time constraints must be respected (sampling time can be
3958 * adjusted in function of ADC clock frequency and sampling time
3959 * setting).
3960 * Refer to device datasheet for timings values (parameters TS_vrefint,
3961 * TS_temp, ...).
3962 * @note Conversion time is the addition of sampling time and processing time.
3963 * On this STM32 series, ADC processing time is:
3964 * - 12.5 ADC clock cycles at ADC resolution 12 bits
3965 * - 10.5 ADC clock cycles at ADC resolution 10 bits
3966 * - 8.5 ADC clock cycles at ADC resolution 8 bits
3967 * - 6.5 ADC clock cycles at ADC resolution 6 bits
3968 * @note In case of ADC conversion of internal channel (VrefInt,
3969 * temperature sensor, ...), a sampling time minimum value
3970 * is required.
3971 * Refer to device datasheet.
3972 * @note On this STM32 series, setting of this feature is conditioned to
3973 * ADC state:
3974 * ADC must be disabled or enabled without conversion on going
3975 * on group regular.
3976 * @note Applicable only on ADC4 instance
3977 * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n
3978 * SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
3979 * @param ADCx ADC instance
3980 * @param SamplingTimeY This parameter can be one of the following values:
3981 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3982 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3983 * @param SamplingTime This parameter can be one of the following values:
3984 * @arg @ref LL_ADC4_SAMPLINGTIME_1CYCLE_5
3985 * @arg @ref LL_ADC4_SAMPLINGTIME_3CYCLES_5
3986 * @arg @ref LL_ADC4_SAMPLINGTIME_7CYCLES_5
3987 * @arg @ref LL_ADC4_SAMPLINGTIME_12CYCLES_5
3988 * @arg @ref LL_ADC4_SAMPLINGTIME_19CYCLES_5
3989 * @arg @ref LL_ADC4_SAMPLINGTIME_39CYCLES_5
3990 * @arg @ref LL_ADC4_SAMPLINGTIME_79CYCLES_5
3991 * @arg @ref LL_ADC4_SAMPLINGTIME_814CYCLES_5
3992 * @retval None
3993 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY,uint32_t SamplingTime)3994 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
3995 uint32_t SamplingTime)
3996 {
3997 MODIFY_REG(ADCx->SMPR1,
3998 ADC4_SMPR_SMP1 << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK),
3999 SamplingTime << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK));
4000 }
4001
4002 /**
4003 * @brief Get sampling time common to a group of channels.
4004 * @note Unit: ADC clock cycles.
4005 * @note On this STM32 series, sampling time scope is on ADC instance:
4006 * Sampling time common to all channels.
4007 * (on some other STM32 families, sampling time is channel wise)
4008 * @note Conversion time is the addition of sampling time and processing time.
4009 * Refer to reference manual for ADC processing time of
4010 * this STM32 series.
4011 * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n
4012 * SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
4013 * @param ADCx ADC instance (ADC4 for this device)
4014 * @param SamplingTimeY This parameter can be one of the following values:
4015 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
4016 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
4017 * @retval Returned value can be one of the following values:
4018 * @arg @ref LL_ADC4_SAMPLINGTIME_1CYCLE_5
4019 * @arg @ref LL_ADC4_SAMPLINGTIME_3CYCLES_5
4020 * @arg @ref LL_ADC4_SAMPLINGTIME_7CYCLES_5
4021 * @arg @ref LL_ADC4_SAMPLINGTIME_12CYCLES_5
4022 * @arg @ref LL_ADC4_SAMPLINGTIME_19CYCLES_5
4023 * @arg @ref LL_ADC4_SAMPLINGTIME_39CYCLES_5
4024 * @arg @ref LL_ADC4_SAMPLINGTIME_79CYCLES_5
4025 * @arg @ref LL_ADC4_SAMPLINGTIME_814CYCLES_5
4026 */
LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef * ADCx,uint32_t SamplingTimeY)4027 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
4028 {
4029 return (uint32_t)((READ_BIT(ADCx->SMPR1, ADC4_SMPR_SMP1 << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK)))
4030 >> (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK));
4031 }
4032
4033 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
4034 * @{
4035 */
4036
4037 /**
4038 * @brief Set ADC group regular conversion trigger source:
4039 * internal (SW start) or from external peripheral (timer event,
4040 * external interrupt line).
4041 * @note On this STM32 series, setting trigger source to external trigger
4042 * also set trigger polarity to rising edge
4043 * (default setting for compatibility with some ADC on other
4044 * STM32 families having this setting set by HW default value).
4045 * In case of need to modify trigger edge, use
4046 * function @ref LL_ADC_REG_SetTriggerEdge().
4047 * @note Availability of parameters of trigger sources from timer
4048 * depends on timers availability on the selected device.
4049 * @note On this STM32 series, setting of this feature is conditioned to
4050 * ADC state:
4051 * ADC must be disabled or enabled without conversion on going
4052 * on group regular.
4053 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
4054 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
4055 * @param ADCx ADC instance
4056 * @param TriggerSource This parameter can be one of the following values:
4057 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
4058 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
4059 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
4060 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
4061 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
4062 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
4063 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
4064 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
4065 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
4066 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
4067 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
4068 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
4069 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
4070 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
4071 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
4072 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
4073 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
4074 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
4075 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
4076 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
4077 * @retval None
4078 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)4079 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4080 {
4081 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
4082 {
4083 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
4084 }
4085 else /* ADCx == ADC4 */
4086 {
4087 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC4_CFGR1_EXTSEL, TriggerSource);
4088 }
4089 }
4090
4091 /**
4092 * @brief Get ADC group regular conversion trigger source:
4093 * internal (SW start) or from external peripheral (timer event,
4094 * external interrupt line).
4095 * @note To determine whether group regular trigger source is
4096 * internal (SW start) or external, without detail
4097 * of which peripheral is selected as external trigger,
4098 * (equivalent to
4099 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
4100 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
4101 * @note Availability of parameters of trigger sources from timer
4102 * depends on timers availability on the selected device.
4103 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
4104 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
4105 * @param ADCx ADC instance
4106 * @retval Returned value can be one of the following values:
4107 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
4108 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
4109 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
4110 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
4111 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
4112 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
4113 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
4114 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
4115 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
4116 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
4117 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
4118 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
4119 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
4120 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
4121 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
4122 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
4123 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
4124 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
4125 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
4126 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
4127 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)4128 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
4129 {
4130 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
4131 {
4132 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
4133
4134 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4135 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
4136 uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4137
4138 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
4139 /* to match with triggers literals definition. */
4140 return ((trigger_source
4141 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
4142 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
4143 );
4144 }
4145 else /* ADCx == ADC4 */
4146 {
4147 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC4_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
4148
4149 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4150 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
4151 uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4152
4153 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
4154 /* to match with triggers literals definition. */
4155 return ((trigger_source
4156 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC4_CFGR1_EXTSEL)
4157 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
4158 );
4159 }
4160 }
4161
4162 /**
4163 * @brief Get ADC group regular conversion trigger source internal (SW start)
4164 * or external.
4165 * @note In case of group regular trigger source set to external trigger,
4166 * to determine which peripheral is selected as external trigger,
4167 * use function @ref LL_ADC_REG_GetTriggerSource().
4168 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
4169 * @param ADCx ADC instance
4170 * @retval Value "0" if trigger source external trigger
4171 * Value "1" if trigger source SW start.
4172 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)4173 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4174 {
4175 return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
4176 }
4177
4178 /**
4179 * @brief Set ADC group regular conversion trigger polarity.
4180 * @note Applicable only for trigger source set to external trigger.
4181 * @note On this STM32 series, setting of this feature is conditioned to
4182 * ADC state:
4183 * ADC must be disabled or enabled without conversion on going
4184 * on group regular.
4185 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
4186 * @param ADCx ADC instance
4187 * @param ExternalTriggerEdge This parameter can be one of the following values:
4188 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4189 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4190 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4191 * @retval None
4192 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4193 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4194 {
4195 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
4196 }
4197
4198 /**
4199 * @brief Get ADC group regular conversion trigger polarity.
4200 * @note Applicable only for trigger source set to external trigger.
4201 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
4202 * @param ADCx ADC instance
4203 * @retval Returned value can be one of the following values:
4204 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4205 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4206 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4207 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)4208 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
4209 {
4210 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
4211 }
4212
4213 /**
4214 * @brief Set ADC trigger frequency mode.
4215 * @note ADC trigger frequency mode must be set to low frequency when
4216 * a duration is exceeded before ADC conversion start trigger event
4217 * (between ADC enable and ADC conversion start trigger event
4218 * or between two ADC conversion start trigger event).
4219 * Duration value: Refer to device datasheet, parameter "tIdle".
4220 * @note When ADC trigger frequency mode is set to low frequency,
4221 * some rearm cycles are inserted before performing ADC conversion
4222 * start, inducing a delay of 2 ADC clock cycles.
4223 * @note Usage of ADC trigger frequency mode with ADC low power mode:
4224 * - Low power mode auto wait: Only the first ADC conversion
4225 * start trigger inserts the rearm delay.
4226 * - Low power mode auto power-off: ADC trigger frequency mode
4227 * is discarded.
4228 * @note On this STM32 series, setting of this feature is conditioned to
4229 * ADC state:
4230 * ADC must be disabled or enabled without conversion on going
4231 * on group regular.
4232 * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
4233 * @param ADCx ADC instance
4234 * @param TriggerFrequencyMode This parameter can be one of the following values:
4235 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
4236 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
4237 * @retval None
4238 */
LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef * ADCx,uint32_t TriggerFrequencyMode)4239 __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
4240 {
4241 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
4242 {
4243 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, (TriggerFrequencyMode >> 2U));
4244 }
4245 else /* ADCx == ADC4 */
4246 {
4247 MODIFY_REG(ADCx->CFGR2, ADC4_CFGR2_LFTRIG, TriggerFrequencyMode);
4248 }
4249 }
4250
4251 /**
4252 * @brief Get ADC trigger frequency mode.
4253 * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
4254 * @param ADCx ADC instance
4255 * @retval Returned value can be one of the following values:
4256 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
4257 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
4258 */
LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef * ADCx)4259 __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx)
4260 {
4261 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
4262 {
4263 return (uint32_t)((READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)) << 2U);
4264 }
4265 else /* ADCx == ADC4 */
4266 {
4267 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_LFTRIG));
4268 }
4269 }
4270
4271 /**
4272 * @brief Set ADC sampling mode.
4273 * @note This function set the ADC conversion sampling mode
4274 * @note This mode applies to regular group only.
4275 * @note Set sampling mode is applied to all conversion of regular group.
4276 * @note On this STM32 series, setting of this feature is conditioned to
4277 * ADC state:
4278 * ADC must be disabled or enabled without conversion on going
4279 * on group regular.
4280 * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
4281 * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
4282 * @param ADCx ADC instance
4283 * @param SamplingMode This parameter can be one of the following values:
4284 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
4285 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
4286 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
4287 * @retval None
4288 */
LL_ADC_REG_SetSamplingMode(ADC_TypeDef * ADCx,uint32_t SamplingMode)4289 __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
4290 {
4291 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
4292 }
4293
4294 /**
4295 * @brief Get the ADC sampling mode
4296 * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n
4297 * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
4298 * @param ADCx ADC instance
4299 * @retval Returned value can be one of the following values:
4300 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
4301 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
4302 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
4303 */
LL_ADC_REG_GetSamplingMode(const ADC_TypeDef * ADCx)4304 __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx)
4305 {
4306 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
4307 }
4308
4309 /**
4310 * @brief Start ADC sampling phase for sampling time trigger mode
4311 * @note This function is relevant only when
4312 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
4313 * using @ref LL_ADC_REG_SetSamplingMode
4314 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
4315 * @note On this STM32 series, setting of this feature is conditioned to
4316 * ADC state:
4317 * ADC must be enabled without conversion on going on group regular,
4318 * without conversion stop command on going on group regular,
4319 * without ADC disable command on going.
4320 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
4321 * @param ADCx ADC instance
4322 * @retval None
4323 */
LL_ADC_REG_StartSamplingPhase(ADC_TypeDef * ADCx)4324 __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
4325 {
4326 SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
4327 }
4328
4329 /**
4330 * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion
4331 * @note This function is relevant only when
4332 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
4333 * using @ref LL_ADC_REG_SetSamplingMode
4334 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
4335 * - @ref LL_ADC_REG_StartSamplingPhase has been called to start
4336 * the sampling phase
4337 * @note On this STM32 series, setting of this feature is conditioned to
4338 * ADC state:
4339 * ADC must be enabled without conversion on going on group regular,
4340 * without conversion stop command on going on group regular,
4341 * without ADC disable command on going.
4342 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
4343 * @param ADCx ADC instance
4344 * @retval None
4345 */
LL_ADC_REG_StopSamplingPhase(ADC_TypeDef * ADCx)4346 __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
4347 {
4348 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
4349 }
4350
4351 /**
4352 * @brief Set ADC group regular sequencer configuration flexibility.
4353 * @note On this STM32 series, ADC group regular sequencer both modes
4354 * "fully configurable" or "not fully configurable" are
4355 * available:
4356 * - sequencer configured to fully configurable:
4357 * sequencer length and each rank
4358 * affectation to a channel are configurable.
4359 * Refer to description of function
4360 * @ref LL_ADC_REG_SetSequencerLength().
4361 * - sequencer configured to not fully configurable:
4362 * sequencer length and each rank affectation to a channel
4363 * are fixed by channel HW number.
4364 * Refer to description of function
4365 * @ref LL_ADC_REG_SetSequencerChannels().
4366 * @note On this STM32 series, setting of this feature is conditioned to
4367 * ADC state:
4368 * ADC must be disabled or enabled without conversion on going
4369 * on group regular.
4370 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
4371 * @param ADCx ADC instance
4372 * @param Configurability This parameter can be one of the following values:
4373 * @arg @ref LL_ADC_REG_SEQ_FIXED
4374 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
4375 * @retval None
4376 * @note On this STM32U5 series, this is applicable on ADC4 only.
4377 */
LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef * ADCx,uint32_t Configurability)4378 __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
4379 {
4380 MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_CHSELRMOD, Configurability);
4381 }
4382
4383 /**
4384 * @brief Get ADC group regular sequencer configuration flexibility.
4385 * @note On this STM32 series, ADC group regular sequencer both modes
4386 * "fully configurable" or "not fully configurable" are
4387 * available:
4388 * - sequencer configured to fully configurable:
4389 * sequencer length and each rank
4390 * affectation to a channel are configurable.
4391 * Refer to description of function
4392 * @ref LL_ADC_REG_SetSequencerLength().
4393 * - sequencer configured to not fully configurable:
4394 * sequencer length and each rank affectation to a channel
4395 * are fixed by channel HW number.
4396 * Refer to description of function
4397 * @ref LL_ADC_REG_SetSequencerChannels().
4398 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
4399 * @param ADCx ADC instance
4400 * @retval Returned value can be one of the following values:
4401 * @arg @ref LL_ADC_REG_SEQ_FIXED
4402 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
4403 * @note On this STM32U5 series, this is applicable on ADC4 only.
4404 */
LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef * ADCx)4405 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx)
4406 {
4407 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_CHSELRMOD));
4408 }
4409
4410 /**
4411 * @brief Set ADC group regular sequencer length and scan direction.
4412 * @note Description of ADC group regular sequencer features:
4413 * - For devices with sequencer fully configurable
4414 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4415 * sequencer length and each rank affectation to a channel
4416 * are configurable.
4417 * This function performs configuration of:
4418 * - Sequence length: Number of ranks in the scan sequence.
4419 * - Sequence direction: Unless specified in parameters, sequencer
4420 * scan direction is forward (from rank 1 to rank n).
4421 * Sequencer ranks are selected using
4422 * function "LL_ADC_REG_SetSequencerRanks()".
4423 * - For devices with sequencer not fully configurable
4424 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4425 * sequencer length and each rank affectation to a channel
4426 * are defined by channel number.
4427 * This function performs configuration of:
4428 * - Sequence length: Number of ranks in the scan sequence is
4429 * defined by number of channels set in the sequence,
4430 * rank of each channel is fixed by channel HW number.
4431 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4432 * - Sequence direction: Unless specified in parameters, sequencer
4433 * scan direction is forward (from lowest channel number to
4434 * highest channel number).
4435 * Sequencer ranks are selected using
4436 * function "LL_ADC_REG_SetSequencerChannels()".
4437 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4438 * ADC conversion on only 1 channel.
4439 * @note On this STM32 series, setting of this feature is conditioned to
4440 * ADC state:
4441 * ADC must be disabled or enabled without conversion on going
4442 * on group regular.
4443 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
4444 * @param ADCx ADC instance
4445 * @param SequencerNbRanks This parameter can be one of the following values:
4446 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4447 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4448 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4449 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4450 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4451 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4452 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4453 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4454 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4455 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4456 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4457 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4458 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4459 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4460 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4461 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4462 * Note: Specific case for ADC4, use literals LL_ADC4_REG_SEQ_SCAN_x
4463 * @retval None
4464 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4465 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4466 {
4467 if (ADCx != ADC4) /* ADC1 or ADC2 */
4468 {
4469 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
4470 }
4471 else
4472 {
4473 SET_BIT(ADCx->CHSELR, SequencerNbRanks);
4474 }
4475 }
4476
4477 /**
4478 * @brief Get ADC group regular sequencer length and scan direction.
4479 * @note Description of ADC group regular sequencer features:
4480 * - For devices with sequencer fully configurable
4481 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4482 * sequencer length and each rank affectation to a channel
4483 * are configurable.
4484 * This function retrieves:
4485 * - Sequence length: Number of ranks in the scan sequence.
4486 * - Sequence direction: Unless specified in parameters, sequencer
4487 * scan direction is forward (from rank 1 to rank n).
4488 * Sequencer ranks are selected using
4489 * function "LL_ADC_REG_SetSequencerRanks()".
4490 * - For devices with sequencer not fully configurable
4491 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4492 * sequencer length and each rank affectation to a channel
4493 * are defined by channel number.
4494 * This function retrieves:
4495 * - Sequence length: Number of ranks in the scan sequence is
4496 * defined by number of channels set in the sequence,
4497 * rank of each channel is fixed by channel HW number.
4498 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4499 * - Sequence direction: Unless specified in parameters, sequencer
4500 * scan direction is forward (from lowest channel number to
4501 * highest channel number).
4502 * Sequencer ranks are selected using
4503 * function "LL_ADC_REG_SetSequencerChannels()".
4504 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4505 * ADC conversion on only 1 channel.
4506 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
4507 * @param ADCx ADC instance
4508 * @retval Returned value can be one of the following values:
4509 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4510 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4511 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4512 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4513 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4514 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4515 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4516 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4517 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4518 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4519 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4520 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4521 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4522 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4523 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4524 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4525 * Note: Specific case for ADC4, use literals LL_ADC4_REG_SEQ_SCAN_x
4526 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)4527 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
4528 {
4529 if (ADCx != ADC4) /* ADC1 or ADC2 */
4530 {
4531 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
4532 }
4533 else
4534 {
4535 uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
4536 uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
4537 uint32_t rank_index;
4538 uint32_t rank_shifted;
4539
4540 /* Parse register for end of sequence identifier */
4541 /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
4542 (ADC_CHSELR_SQ2), value "4" to length of end of sequence
4543 identifier (0xF)*/
4544 for (rank_index = 0UL; rank_index <= (28U - 4U); rank_index += 4U)
4545 {
4546 rank_shifted = (uint32_t)(0xF0UL << rank_index);
4547 if ((channels_ranks & rank_shifted) == rank_shifted)
4548 {
4549 sequencer_length = rank_shifted;
4550 break;
4551 }
4552 }
4553
4554 return sequencer_length;
4555 }
4556 }
4557
4558 /**
4559 * @brief Set ADC group regular sequencer discontinuous mode:
4560 * sequence subdivided and scan conversions interrupted every selected
4561 * number of ranks.
4562 * @note It is not possible to enable both ADC group regular
4563 * continuous mode and sequencer discontinuous mode.
4564 * @note It is not possible to enable both ADC auto-injected mode
4565 * and ADC group regular sequencer discontinuous mode.
4566 * @note On this STM32 series, setting of this feature is conditioned to
4567 * ADC state:
4568 * ADC must be disabled or enabled without conversion on going
4569 * on group regular.
4570 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
4571 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
4572 * @param ADCx ADC instance
4573 * @param SeqDiscont This parameter can be one of the following values:
4574 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4575 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4576 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4577 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4578 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4579 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4580 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4581 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4582 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4583 * @retval None
4584 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4585 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4586 {
4587 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM, SeqDiscont);
4588 }
4589
4590 /**
4591 * @brief Get ADC group regular sequencer discontinuous mode:
4592 * sequence subdivided and scan conversions interrupted every selected
4593 * number of ranks.
4594 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
4595 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
4596 * @param ADCx ADC instance
4597 * @retval Returned value can be one of the following values:
4598 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4599 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4600 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4601 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4602 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4603 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4604 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4605 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4606 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4607 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)4608 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4609 {
4610 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM));
4611 }
4612
4613 /**
4614 * @brief Set ADC group regular sequence: channel on the selected
4615 * scan sequence rank.
4616 * @note This function performs configuration of:
4617 * - Channels ordering into each rank of scan sequence:
4618 * whatever channel can be placed into whatever rank.
4619 * @note On this STM32 series, ADC group regular sequencer is
4620 * fully configurable: sequencer length and each rank
4621 * affectation to a channel are configurable.
4622 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4623 * @note Depending on devices and packages, some channels may not be available.
4624 * Refer to device datasheet for channels availability.
4625 * @note On this STM32 series, to measure internal channels (VrefInt,
4626 * TempSensor, ...), measurement paths to internal channels must be
4627 * enabled separately.
4628 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4629 * @note On this STM32 series, setting of this feature is conditioned to
4630 * ADC state:
4631 * ADC must be disabled or enabled without conversion on going
4632 * on group regular.
4633 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
4634 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
4635 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
4636 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
4637 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
4638 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
4639 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
4640 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
4641 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
4642 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
4643 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
4644 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
4645 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
4646 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
4647 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
4648 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
4649 * @param ADCx ADC instance
4650 * @param Rank This parameter can be one of the following values:
4651 * @arg @ref LL_ADC_REG_RANK_1
4652 * @arg @ref LL_ADC_REG_RANK_2
4653 * @arg @ref LL_ADC_REG_RANK_3
4654 * @arg @ref LL_ADC_REG_RANK_4
4655 * @arg @ref LL_ADC_REG_RANK_5
4656 * @arg @ref LL_ADC_REG_RANK_6
4657 * @arg @ref LL_ADC_REG_RANK_7
4658 * @arg @ref LL_ADC_REG_RANK_8
4659 * @arg @ref LL_ADC_REG_RANK_9
4660 * @arg @ref LL_ADC_REG_RANK_10
4661 * @arg @ref LL_ADC_REG_RANK_11
4662 * @arg @ref LL_ADC_REG_RANK_12
4663 * @arg @ref LL_ADC_REG_RANK_13
4664 * @arg @ref LL_ADC_REG_RANK_14
4665 * @arg @ref LL_ADC_REG_RANK_15
4666 * @arg @ref LL_ADC_REG_RANK_16
4667 * Note: Specific case for ADC4, use literals LL_ADC_REG_RANK_x_ADC4
4668 * @param Channel This parameter can be one of the following values:
4669 * @arg @ref LL_ADC_CHANNEL_0 (3)
4670 * @arg @ref LL_ADC_CHANNEL_1 (3)
4671 * @arg @ref LL_ADC_CHANNEL_2 (3)
4672 * @arg @ref LL_ADC_CHANNEL_3 (3)
4673 * @arg @ref LL_ADC_CHANNEL_4 (3)
4674 * @arg @ref LL_ADC_CHANNEL_5 (3)
4675 * @arg @ref LL_ADC_CHANNEL_6
4676 * @arg @ref LL_ADC_CHANNEL_7
4677 * @arg @ref LL_ADC_CHANNEL_8
4678 * @arg @ref LL_ADC_CHANNEL_9
4679 * @arg @ref LL_ADC_CHANNEL_10
4680 * @arg @ref LL_ADC_CHANNEL_11
4681 * @arg @ref LL_ADC_CHANNEL_12
4682 * @arg @ref LL_ADC_CHANNEL_13
4683 * @arg @ref LL_ADC_CHANNEL_14
4684 * @arg @ref LL_ADC_CHANNEL_15
4685 * @arg @ref LL_ADC_CHANNEL_16
4686 * @arg @ref LL_ADC_CHANNEL_17
4687 * @arg @ref LL_ADC_CHANNEL_18
4688 * @arg @ref LL_ADC_CHANNEL_19
4689 * @arg @ref LL_ADC_CHANNEL_VREFINT
4690 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4691 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4692 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
4693 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
4694 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
4695 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
4696 *
4697 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
4698 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
4699 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4700 * Other channels are slow channels (conversion rate: refer to reference manual).
4701 * @retval None
4702 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4703 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4704 {
4705 /* Set bits with content of parameter "Channel" with bits position */
4706 /* in register and register position depending on parameter "Rank". */
4707 /* Parameters "Rank" and "Channel" are used with masks because containing */
4708 /* other bits reserved for other purpose. */
4709 if (ADCx != ADC4) /* ADC1 or ADC2 */
4710 {
4711 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) \
4712 >> ADC_SQRX_REGOFFSET_POS));
4713
4714 MODIFY_REG(*preg,
4715 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4716 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
4717 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4718 }
4719 else
4720 {
4721 MODIFY_REG(ADCx->CHSELR,
4722 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4723 (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
4724 }
4725 }
4726
4727 /**
4728 * @brief Get ADC group regular sequence: channel on the selected
4729 * scan sequence rank.
4730 * @note On this STM32 series, ADC group regular sequencer is
4731 * fully configurable: sequencer length and each rank
4732 * affectation to a channel are configurable.
4733 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4734 * @note Depending on devices and packages, some channels may not be available.
4735 * Refer to device datasheet for channels availability.
4736 * @note Usage of the returned channel number:
4737 * - To reinject this channel into another function LL_ADC_xxx:
4738 * the returned channel number is only partly formatted on definition
4739 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4740 * with parts of literals LL_ADC_CHANNEL_x or using
4741 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4742 * Then the selected literal LL_ADC_CHANNEL_x can be used
4743 * as parameter for another function.
4744 * - To get the channel number in decimal format:
4745 * process the returned value with the helper macro
4746 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4747 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
4748 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
4749 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
4750 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
4751 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
4752 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
4753 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
4754 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
4755 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
4756 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
4757 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
4758 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
4759 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
4760 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
4761 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
4762 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4763 * @param ADCx ADC instance
4764 * @param Rank This parameter can be one of the following values:
4765 * @arg @ref LL_ADC_REG_RANK_1
4766 * @arg @ref LL_ADC_REG_RANK_2
4767 * @arg @ref LL_ADC_REG_RANK_3
4768 * @arg @ref LL_ADC_REG_RANK_4
4769 * @arg @ref LL_ADC_REG_RANK_5
4770 * @arg @ref LL_ADC_REG_RANK_6
4771 * @arg @ref LL_ADC_REG_RANK_7
4772 * @arg @ref LL_ADC_REG_RANK_8
4773 * @arg @ref LL_ADC_REG_RANK_9
4774 * @arg @ref LL_ADC_REG_RANK_10
4775 * @arg @ref LL_ADC_REG_RANK_11
4776 * @arg @ref LL_ADC_REG_RANK_12
4777 * @arg @ref LL_ADC_REG_RANK_13
4778 * @arg @ref LL_ADC_REG_RANK_14
4779 * @arg @ref LL_ADC_REG_RANK_15
4780 * @arg @ref LL_ADC_REG_RANK_16
4781 * Note: Specific case for ADC4, use literals LL_ADC_REG_RANK_x_ADC4
4782 * @retval Returned value can be one of the following values:
4783 * @arg @ref LL_ADC_CHANNEL_0 (3)
4784 * @arg @ref LL_ADC_CHANNEL_1 (3)
4785 * @arg @ref LL_ADC_CHANNEL_2 (3)
4786 * @arg @ref LL_ADC_CHANNEL_3 (3)
4787 * @arg @ref LL_ADC_CHANNEL_4 (3)
4788 * @arg @ref LL_ADC_CHANNEL_5 (3)
4789 * @arg @ref LL_ADC_CHANNEL_6
4790 * @arg @ref LL_ADC_CHANNEL_7
4791 * @arg @ref LL_ADC_CHANNEL_8
4792 * @arg @ref LL_ADC_CHANNEL_9
4793 * @arg @ref LL_ADC_CHANNEL_10
4794 * @arg @ref LL_ADC_CHANNEL_11
4795 * @arg @ref LL_ADC_CHANNEL_12
4796 * @arg @ref LL_ADC_CHANNEL_13
4797 * @arg @ref LL_ADC_CHANNEL_14
4798 * @arg @ref LL_ADC_CHANNEL_15
4799 * @arg @ref LL_ADC_CHANNEL_16
4800 * @arg @ref LL_ADC_CHANNEL_17
4801 * @arg @ref LL_ADC_CHANNEL_18
4802 * @arg @ref LL_ADC_CHANNEL_19
4803 * @arg @ref LL_ADC_CHANNEL_VREFINT
4804 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4805 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4806 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
4807 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
4808 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
4809 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
4810 *
4811 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
4812 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
4813 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4814 * Other channels are slow channels (conversion rate: refer to reference manual).
4815 * (1, 2) For ADC channel read back from ADC register,
4816 * comparison with internal channel parameter to be done
4817 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4818 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4819 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4820 {
4821 if (ADCx != ADC4) /* ADC1 or ADC2 */
4822 {
4823 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) \
4824 >> ADC_SQRX_REGOFFSET_POS));
4825
4826 return (uint32_t)((READ_BIT(*preg,
4827 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4828 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4829 );
4830 }
4831 else
4832 {
4833 return (uint32_t)((READ_BIT(ADCx->CHSELR,
4834 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4835 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
4836 ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4837 );
4838 }
4839 }
4840
4841 /**
4842 * @brief Set ADC group regular sequencer scan direction.
4843 * @note On this STM32 series, parameter relevant only is sequencer is set
4844 * to mode not fully configurable,
4845 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
4846 * @note On some other STM32 families, this setting is not available and
4847 * the default scan direction is forward.
4848 * @note On this STM32 series, setting of this feature is conditioned to
4849 * ADC state:
4850 * ADC must be disabled or enabled without conversion on going
4851 * on group regular.
4852 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
4853 * @param ADCx ADC instance
4854 * @param ScanDirection This parameter can be one of the following values:
4855 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
4856 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
4857 * @retval None
4858 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)4859 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
4860 {
4861 MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_SCANDIR, ScanDirection);
4862 }
4863
4864 /**
4865 * @brief Get ADC group regular sequencer scan direction.
4866 * @note On this STM32 series, parameter relevant only is sequencer is set
4867 * to mode not fully configurable,
4868 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
4869 * @note On some other STM32 families, this setting is not available and
4870 * the default scan direction is forward.
4871 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
4872 * @param ADCx ADC instance
4873 * @retval Returned value can be one of the following values:
4874 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
4875 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
4876 */
LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef * ADCx)4877 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx)
4878 {
4879 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_SCANDIR));
4880 }
4881
4882 /**
4883 * @brief Set ADC group regular sequence: channel on rank corresponding to
4884 * channel number.
4885 * @note This function performs:
4886 * - Channels ordering into each rank of scan sequence:
4887 * rank of each channel is fixed by channel HW number
4888 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4889 * - Set channels selected by overwriting the current sequencer
4890 * configuration.
4891 * @note On this STM32 series, ADC group regular sequencer both modes
4892 * "fully configurable" or "not fully configurable"
4893 * are available, they can be chosen using
4894 * function @ref LL_ADC_REG_SetSequencerConfigurable().
4895 * This function can be used with setting "not fully configurable".
4896 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
4897 * and @ref LL_ADC_REG_SetSequencerLength().
4898 * @note Depending on devices and packages, some channels may not be available.
4899 * Refer to device datasheet for channels availability.
4900 * @note On this STM32 series, to measure internal channels (VrefInt,
4901 * TempSensor, ...), measurement paths to internal channels must be
4902 * enabled separately.
4903 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4904 * @note On this STM32 series, setting of this feature is conditioned to
4905 * ADC state:
4906 * ADC must be disabled or enabled without conversion on going
4907 * on group regular.
4908 * @note One or several values can be selected.
4909 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4910 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
4911 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
4912 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
4913 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
4914 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
4915 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
4916 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
4917 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
4918 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
4919 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
4920 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
4921 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
4922 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
4923 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
4924 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
4925 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
4926 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
4927 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
4928 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
4929 * @param ADCx ADC instance
4930 * @param Channel This parameter can be a combination of the following values:
4931 * @arg @ref LL_ADC_CHANNEL_0
4932 * @arg @ref LL_ADC_CHANNEL_1
4933 * @arg @ref LL_ADC_CHANNEL_2
4934 * @arg @ref LL_ADC_CHANNEL_3
4935 * @arg @ref LL_ADC_CHANNEL_4
4936 * @arg @ref LL_ADC_CHANNEL_5
4937 * @arg @ref LL_ADC_CHANNEL_6
4938 * @arg @ref LL_ADC_CHANNEL_7
4939 * @arg @ref LL_ADC_CHANNEL_8
4940 * @arg @ref LL_ADC_CHANNEL_9
4941 * @arg @ref LL_ADC_CHANNEL_10
4942 * @arg @ref LL_ADC_CHANNEL_11
4943 * @arg @ref LL_ADC_CHANNEL_12
4944 * @arg @ref LL_ADC_CHANNEL_13
4945 * @arg @ref LL_ADC_CHANNEL_14
4946 * @arg @ref LL_ADC_CHANNEL_15 (1)
4947 * @arg @ref LL_ADC_CHANNEL_16 (1)
4948 * @arg @ref LL_ADC_CHANNEL_17 (1)
4949 * @arg @ref LL_ADC_CHANNEL_18
4950 * @arg @ref LL_ADC_CHANNEL_VREFINT
4951 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4952 * @arg @ref LL_ADC_CHANNEL_VBAT
4953 *
4954 * (1) On STM32U5, parameter can be set in ADC group sequencer
4955 * only if sequencer is set in mode "not fully configurable",
4956 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
4957 * @retval None
4958 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)4959 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
4960 {
4961 /* Parameter "Channel" is used with masks because containing */
4962 /* other bits reserved for other purpose. */
4963 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
4964 }
4965
4966 /**
4967 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
4968 * channel number.
4969 * @note This function performs:
4970 * - Channels ordering into each rank of scan sequence:
4971 * rank of each channel is fixed by channel HW number
4972 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4973 * - Set channels selected by adding them to the current sequencer
4974 * configuration.
4975 * @note On this STM32 series, ADC group regular sequencer both modes
4976 * "fully configurable" or "not fully configurable"
4977 * are available, they can be chosen using
4978 * function @ref LL_ADC_REG_SetSequencerConfigurable().
4979 * This function can be used with setting "not fully configurable".
4980 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
4981 * and @ref LL_ADC_REG_SetSequencerLength().
4982 * @note Depending on devices and packages, some channels may not be available.
4983 * Refer to device datasheet for channels availability.
4984 * @note On this STM32 series, to measure internal channels (VrefInt,
4985 * TempSensor, ...), measurement paths to internal channels must be
4986 * enabled separately.
4987 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4988 * @note On this STM32 series, setting of this feature is conditioned to
4989 * ADC state:
4990 * ADC must be disabled or enabled without conversion on going
4991 * on group regular.
4992 * @note One or several values can be selected.
4993 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4994 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
4995 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
4996 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
4997 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
4998 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
4999 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
5000 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
5001 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
5002 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
5003 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
5004 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
5005 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
5006 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
5007 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
5008 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
5009 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
5010 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
5011 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
5012 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
5013 * @param ADCx ADC instance
5014 * @param Channel This parameter can be a combination of the following values:
5015 * @arg @ref LL_ADC_CHANNEL_0
5016 * @arg @ref LL_ADC_CHANNEL_1
5017 * @arg @ref LL_ADC_CHANNEL_2
5018 * @arg @ref LL_ADC_CHANNEL_3
5019 * @arg @ref LL_ADC_CHANNEL_4
5020 * @arg @ref LL_ADC_CHANNEL_5
5021 * @arg @ref LL_ADC_CHANNEL_6
5022 * @arg @ref LL_ADC_CHANNEL_7
5023 * @arg @ref LL_ADC_CHANNEL_8
5024 * @arg @ref LL_ADC_CHANNEL_9
5025 * @arg @ref LL_ADC_CHANNEL_10
5026 * @arg @ref LL_ADC_CHANNEL_11
5027 * @arg @ref LL_ADC_CHANNEL_12
5028 * @arg @ref LL_ADC_CHANNEL_13
5029 * @arg @ref LL_ADC_CHANNEL_14
5030 * @arg @ref LL_ADC_CHANNEL_15 (1)
5031 * @arg @ref LL_ADC_CHANNEL_16 (1)
5032 * @arg @ref LL_ADC_CHANNEL_17 (1)
5033 * @arg @ref LL_ADC_CHANNEL_18
5034 * @arg @ref LL_ADC_CHANNEL_VREFINT
5035 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5036 * @arg @ref LL_ADC_CHANNEL_VBAT
5037 *
5038 * (1) On STM32U5, parameter can be set in ADC group sequencer
5039 * only if sequencer is set in mode "not fully configurable",
5040 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
5041 * @retval None
5042 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)5043 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
5044 {
5045 /* Parameter "Channel" is used with masks because containing */
5046 /* other bits reserved for other purpose. */
5047 SET_BIT(ADCx->CHSELR, (1UL << ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & ADC_CHSELR_CHSEL) & 0x1FUL)));
5048 }
5049
5050 /**
5051 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
5052 * channel number.
5053 * @note This function performs:
5054 * - Channels ordering into each rank of scan sequence:
5055 * rank of each channel is fixed by channel HW number
5056 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
5057 * - Set channels selected by removing them to the current sequencer
5058 * configuration.
5059 * @note On this STM32 series, ADC group regular sequencer both modes
5060 * "fully configurable" or "not fully configurable"
5061 * are available, they can be chosen using
5062 * function @ref LL_ADC_REG_SetSequencerConfigurable().
5063 * This function can be used with setting "not fully configurable".
5064 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
5065 * and @ref LL_ADC_REG_SetSequencerLength().
5066 * @note Depending on devices and packages, some channels may not be available.
5067 * Refer to device datasheet for channels availability.
5068 * @note On this STM32 series, to measure internal channels (VrefInt,
5069 * TempSensor, ...), measurement paths to internal channels must be
5070 * enabled separately.
5071 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5072 * @note On this STM32 series, setting of this feature is conditioned to
5073 * ADC state:
5074 * ADC must be disabled or enabled without conversion on going
5075 * on group regular.
5076 * @note One or several values can be selected.
5077 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5078 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
5079 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
5080 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
5081 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
5082 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
5083 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
5084 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
5085 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
5086 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
5087 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
5088 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
5089 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
5090 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
5091 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
5092 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
5093 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
5094 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
5095 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
5096 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
5097 * @param ADCx ADC instance
5098 * @param Channel This parameter can be a combination of the following values:
5099 * @arg @ref LL_ADC_CHANNEL_0
5100 * @arg @ref LL_ADC_CHANNEL_1
5101 * @arg @ref LL_ADC_CHANNEL_2
5102 * @arg @ref LL_ADC_CHANNEL_3
5103 * @arg @ref LL_ADC_CHANNEL_4
5104 * @arg @ref LL_ADC_CHANNEL_5
5105 * @arg @ref LL_ADC_CHANNEL_6
5106 * @arg @ref LL_ADC_CHANNEL_7
5107 * @arg @ref LL_ADC_CHANNEL_8
5108 * @arg @ref LL_ADC_CHANNEL_9
5109 * @arg @ref LL_ADC_CHANNEL_10
5110 * @arg @ref LL_ADC_CHANNEL_11
5111 * @arg @ref LL_ADC_CHANNEL_12
5112 * @arg @ref LL_ADC_CHANNEL_13
5113 * @arg @ref LL_ADC_CHANNEL_14
5114 * @arg @ref LL_ADC_CHANNEL_15 (1)
5115 * @arg @ref LL_ADC_CHANNEL_16 (1)
5116 * @arg @ref LL_ADC_CHANNEL_17 (1)
5117 * @arg @ref LL_ADC_CHANNEL_18
5118 * @arg @ref LL_ADC_CHANNEL_VREFINT
5119 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5120 * @arg @ref LL_ADC_CHANNEL_VBAT
5121 *
5122 * (1) On STM32U5, parameter can be set in ADC group sequencer
5123 * only if sequencer is set in mode "not fully configurable",
5124 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
5125 * @retval None
5126 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)5127 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
5128 {
5129 /* Parameter "Channel" is used with masks because containing */
5130 /* other bits reserved for other purpose. */
5131 CLEAR_BIT(ADCx->CHSELR, (1UL << ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)));
5132 }
5133
5134 /**
5135 * @brief Get ADC group regular sequence: channel on rank corresponding to
5136 * channel number.
5137 * @note This function performs:
5138 * - Channels order reading into each rank of scan sequence:
5139 * rank of each channel is fixed by channel HW number
5140 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
5141 * @note On this STM32 series, ADC group regular sequencer both modes
5142 * "fully configurable" or "not fully configurable"
5143 * are available, they can be chosen using
5144 * function @ref LL_ADC_REG_SetSequencerConfigurable().
5145 * This function can be used with setting "not fully configurable".
5146 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
5147 * and @ref LL_ADC_REG_SetSequencerLength().
5148 * @note Depending on devices and packages, some channels may not be available.
5149 * Refer to device datasheet for channels availability.
5150 * @note On this STM32 series, to measure internal channels (VrefInt,
5151 * TempSensor, ...), measurement paths to internal channels must be
5152 * enabled separately.
5153 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5154 * @note On this STM32 series, setting of this feature is conditioned to
5155 * ADC state:
5156 * ADC must be disabled or enabled without conversion on going
5157 * on group regular.
5158 * @note One or several values can be retrieved.
5159 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5160 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
5161 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
5162 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
5163 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
5164 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
5165 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
5166 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
5167 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
5168 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
5169 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
5170 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
5171 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
5172 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
5173 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
5174 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
5175 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
5176 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
5177 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
5178 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
5179 * @param ADCx ADC instance
5180 * @retval Returned value can be a combination of the following values:
5181 * @arg @ref LL_ADC_CHANNEL_0
5182 * @arg @ref LL_ADC_CHANNEL_1
5183 * @arg @ref LL_ADC_CHANNEL_2
5184 * @arg @ref LL_ADC_CHANNEL_3
5185 * @arg @ref LL_ADC_CHANNEL_4
5186 * @arg @ref LL_ADC_CHANNEL_5
5187 * @arg @ref LL_ADC_CHANNEL_6
5188 * @arg @ref LL_ADC_CHANNEL_7
5189 * @arg @ref LL_ADC_CHANNEL_8
5190 * @arg @ref LL_ADC_CHANNEL_9
5191 * @arg @ref LL_ADC_CHANNEL_10
5192 * @arg @ref LL_ADC_CHANNEL_11
5193 * @arg @ref LL_ADC_CHANNEL_12
5194 * @arg @ref LL_ADC_CHANNEL_13
5195 * @arg @ref LL_ADC_CHANNEL_14
5196 * @arg @ref LL_ADC_CHANNEL_15 (1)
5197 * @arg @ref LL_ADC_CHANNEL_16 (1)
5198 * @arg @ref LL_ADC_CHANNEL_17 (1)
5199 * @arg @ref LL_ADC_CHANNEL_18
5200 * @arg @ref LL_ADC_CHANNEL_VREFINT
5201 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5202 * @arg @ref LL_ADC_CHANNEL_VBAT
5203 *
5204 * (1) On STM32U5, parameter can be set in ADC group sequencer
5205 * only if sequencer is set in mode "not fully configurable",
5206 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
5207 */
LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef * ADCx)5208 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx)
5209 {
5210 uint32_t channels_bitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
5211
5212 return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC4_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
5213 | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC4_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
5214 | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC4_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
5215 | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC4_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
5216 | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC4_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
5217 | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC4_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
5218 | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC4_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
5219 | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC4_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
5220 | (((channels_bitfield & ADC_CHSELR_CHSEL8) >> ADC4_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
5221 | (((channels_bitfield & ADC_CHSELR_CHSEL9) >> ADC4_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
5222 | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC4_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
5223 | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC4_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
5224 | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC4_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
5225 | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC4_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
5226 | (((channels_bitfield & ADC_CHSELR_CHSEL14) >> ADC4_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
5227 | (((channels_bitfield & ADC_CHSELR_CHSEL15) >> ADC4_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
5228 | (((channels_bitfield & ADC_CHSELR_CHSEL16) >> ADC4_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
5229 | (((channels_bitfield & ADC_CHSELR_CHSEL17) >> ADC4_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
5230 | (((channels_bitfield & ADC_CHSELR_CHSEL18) >> ADC4_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
5231 | (((channels_bitfield & ADC_CHSELR_CHSEL19) >> ADC4_CHSELR_CHSEL19_BITOFFSET_POS) * LL_ADC_CHANNEL_19)
5232 | (((channels_bitfield & ADC_CHSELR_CHSEL20) >> ADC4_CHSELR_CHSEL20_BITOFFSET_POS) * LL_ADC_CHANNEL_20)
5233 | (((channels_bitfield & ADC_CHSELR_CHSEL21) >> ADC4_CHSELR_CHSEL21_BITOFFSET_POS) * LL_ADC_CHANNEL_21)
5234 | (((channels_bitfield & ADC_CHSELR_CHSEL22) >> ADC4_CHSELR_CHSEL22_BITOFFSET_POS) * LL_ADC_CHANNEL_22)
5235 | (((channels_bitfield & ADC_CHSELR_CHSEL23) >> ADC4_CHSELR_CHSEL23_BITOFFSET_POS) * LL_ADC_CHANNEL_23)
5236
5237 );
5238 }
5239
5240 /**
5241 * @brief Set ADC Channel Preselection to LL_ADC_CHANNEL_x, x = 0 to 19.
5242 * @note This function set the the value for the channel preselection register
5243 * corresponding to ADC channel to be selected.
5244 * @note Caution: This is not valid for ADC4.
5245 * @rmtoll PCSEL PCSEL0 LL_ADC_CHANNEL_0\n
5246 * PCSEL PCSEL1 LL_ADC_CHANNEL_1\n
5247 * PCSEL PCSEL2 LL_ADC_CHANNEL_2\n
5248 * PCSEL PCSEL3 LL_ADC_CHANNEL_3\n
5249 * PCSEL PCSEL4 LL_ADC_CHANNEL_4\n
5250 * PCSEL PCSEL5 LL_ADC_CHANNEL_5\n
5251 * PCSEL PCSEL6 LL_ADC_CHANNEL_6\n
5252 * PCSEL PCSEL7 LL_ADC_CHANNEL_7\n
5253 * PCSEL PCSEL8 LL_ADC_CHANNEL_8\n
5254 * PCSEL PCSEL9 LL_ADC_CHANNEL_9\n
5255 * PCSEL PCSEL10 LL_ADC_CHANNEL_10\n
5256 * PCSEL PCSEL11 LL_ADC_CHANNEL_11\n
5257 * PCSEL PCSEL12 LL_ADC_CHANNEL_12\n
5258 * PCSEL PCSEL13 LL_ADC_CHANNEL_13\n
5259 * PCSEL PCSEL14 LL_ADC_CHANNEL_14\n
5260 * PCSEL PCSEL15 LL_ADC_CHANNEL_15\n
5261 * PCSEL PCSEL16 LL_ADC_CHANNEL_16\n
5262 * PCSEL PCSEL17 LL_ADC_CHANNEL_17\n
5263 * PCSEL PCSEL18 LL_ADC_CHANNEL_18\n
5264 * PCSEL PCSEL19 LL_ADC_CHANNEL_19
5265 * @param ADCx ADC instance.
5266 * @param Channel This parameter can be one of the following values:
5267 * @arg @ref LL_ADC_CHANNEL_0
5268 * @arg @ref LL_ADC_CHANNEL_1
5269 * @arg @ref LL_ADC_CHANNEL_2
5270 * @arg @ref LL_ADC_CHANNEL_3
5271 * @arg @ref LL_ADC_CHANNEL_4
5272 * @arg @ref LL_ADC_CHANNEL_5
5273 * @arg @ref LL_ADC_CHANNEL_6
5274 * @arg @ref LL_ADC_CHANNEL_7
5275 * @arg @ref LL_ADC_CHANNEL_8
5276 * @arg @ref LL_ADC_CHANNEL_9
5277 * @arg @ref LL_ADC_CHANNEL_10
5278 * @arg @ref LL_ADC_CHANNEL_11
5279 * @arg @ref LL_ADC_CHANNEL_12
5280 * @arg @ref LL_ADC_CHANNEL_13
5281 * @arg @ref LL_ADC_CHANNEL_14
5282 * @arg @ref LL_ADC_CHANNEL_15
5283 * @arg @ref LL_ADC_CHANNEL_16
5284 * @arg @ref LL_ADC_CHANNEL_17
5285 * @arg @ref LL_ADC_CHANNEL_18
5286 * @arg @ref LL_ADC_CHANNEL_19
5287 * @arg @ref LL_ADC_CHANNEL_VREFINT
5288 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5289 * @arg @ref LL_ADC_CHANNEL_VBAT
5290 *
5291 * @retval None
5292 */
LL_ADC_SetChannelPreselection(ADC_TypeDef * ADCx,uint32_t Channel)5293 __STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
5294 {
5295 __IO uint32_t channel_preselectione = READ_REG(ADCx->PCSEL);
5296 WRITE_REG(ADCx->PCSEL,
5297 channel_preselectione | (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)Channel) & 0x1FUL)));
5298 }
5299
5300 /**
5301 * @brief Get ADC Channel Preselection register value.
5302 * @note This function set the the value for the channel preselection register
5303 * corresponding to ADC channel to be selected.
5304 * @note Caution: This is not valid for ADC4.
5305 * @rmtoll PCSEL PCSEL0 LL_ADC_CHANNEL_0\n
5306 * PCSEL PCSEL1 LL_ADC_CHANNEL_1\n
5307 * PCSEL PCSEL2 LL_ADC_CHANNEL_2\n
5308 * PCSEL PCSEL3 LL_ADC_CHANNEL_3\n
5309 * PCSEL PCSEL4 LL_ADC_CHANNEL_4\n
5310 * PCSEL PCSEL5 LL_ADC_CHANNEL_5\n
5311 * PCSEL PCSEL6 LL_ADC_CHANNEL_6\n
5312 * PCSEL PCSEL7 LL_ADC_CHANNEL_7\n
5313 * PCSEL PCSEL8 LL_ADC_CHANNEL_8\n
5314 * PCSEL PCSEL9 LL_ADC_CHANNEL_9\n
5315 * PCSEL PCSEL10 LL_ADC_CHANNEL_10\n
5316 * PCSEL PCSEL11 LL_ADC_CHANNEL_11\n
5317 * PCSEL PCSEL12 LL_ADC_CHANNEL_12\n
5318 * PCSEL PCSEL13 LL_ADC_CHANNEL_13\n
5319 * PCSEL PCSEL14 LL_ADC_CHANNEL_14\n
5320 * PCSEL PCSEL15 LL_ADC_CHANNEL_15\n
5321 * PCSEL PCSEL16 LL_ADC_CHANNEL_16\n
5322 * PCSEL PCSEL17 LL_ADC_CHANNEL_17\n
5323 * PCSEL PCSEL18 LL_ADC_CHANNEL_18\n
5324 * PCSEL PCSEL19 LL_ADC_CHANNEL_19
5325 * @param ADCx ADC instance.
5326 * @retval Returned decimal value that can correspend to one or multiple channels:
5327 *
5328 * @note User helper macro @ref __LL_ADC_DECIMAL_NB_TO_CHANNEL().
5329 */
LL_ADC_GetChannelPreselection(const ADC_TypeDef * ADCx)5330 __STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *ADCx)
5331 {
5332 return (uint32_t)(READ_BIT(ADCx->PCSEL, ADC_PCSEL_PCSEL));
5333 }
5334
5335 /**
5336 * @brief Set ADC low power mode.
5337 * @note Description of ADC low power mode:
5338 * - ADC low power mode "auto power-off":
5339 * the ADC automatically powers-off after a conversion and
5340 * automatically wakes up when a new conversion is triggered
5341 * (with startup time between trigger and start of sampling).
5342 * This feature can be combined with low power mode "auto wait".
5343 * @note On this STM32 series, setting of this feature is conditioned to
5344 * ADC state:
5345 * ADC must be disabled.
5346 * @rmtoll PWRR AUTOFF LL_ADC_SetLPModeAutoPowerOff
5347 * @param ADCx ADC instance
5348 * @param LowPowerMode This parameter can be one of the following values:
5349 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
5350 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
5351 * @retval None
5352 */
LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef * ADCx,uint32_t LowPowerMode)5353 __STATIC_INLINE void LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
5354 {
5355 MODIFY_REG(ADCx->PWRR, ADC4_PWRR_AUTOFF, LowPowerMode);
5356 }
5357
5358 /**
5359 * @brief Get ADC low power mode.
5360 * @note Description of ADC low power mode:
5361 * - ADC low power mode "auto power-off":
5362 * the ADC automatically powers-off after a conversion and
5363 * automatically wakes up when a new conversion is triggered
5364 * (with startup time between trigger and start of sampling).
5365 * This feature can be combined with low power mode "auto wait".
5366 * @rmtoll PW AUTOFF LL_ADC_GetLPModeAutoPowerOff
5367 * @param ADCx ADC instance
5368 * @retval Returned value can be one of the following values:
5369 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
5370 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
5371 */
LL_ADC_GetLPModeAutoPowerOff(const ADC_TypeDef * ADCx)5372 __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoPowerOff(const ADC_TypeDef *ADCx)
5373 {
5374 return (uint32_t)(READ_BIT(ADCx->PWRR, ADC4_PWRR_AUTOFF));
5375 }
5376
5377 /**
5378 * @brief Set ADC low power mode: deep power down in autonomous mode
5379 * @note On this STM32 series, setting of this feature is conditioned to
5380 * ADC state:
5381 * ADC must be disabled.
5382 * @rmtoll PWRR DPD LL_ADC_SetLPModeAutonomousDPD
5383 * @param ADCx ADC instance
5384 * @param LowPowerMode This parameter can be one of the following values:
5385 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
5386 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
5387 * @retval None
5388 */
LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef * ADCx,uint32_t LowPowerMode)5389 __STATIC_INLINE void LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
5390 {
5391 MODIFY_REG(ADCx->PWRR, ADC4_PWRR_DPD, LowPowerMode);
5392 }
5393
5394 /**
5395 * @brief Get ADC low power mode: deep power down in autonomous mode
5396 * @rmtoll PWRR DPD LL_ADC_GetLPModeAutonomousDPD
5397 * @param ADCx ADC instance
5398 * @retval Returned value can be one of the following values:
5399 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
5400 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
5401 */
LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef * ADCx)5402 __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef *ADCx)
5403 {
5404 return (uint32_t)(READ_BIT(ADCx->PWRR, ADC4_PWRR_DPD));
5405 }
5406
5407 /**
5408 * @brief Set ADC VREF protection when multiple ADCs are working simultaneously
5409 * @note In case of simultaneous sampling phase of ADC4 and ADC1/2,
5410 * ADC4 is put on hold during one or two ADC4 clock cycles to avoid noise on Vref+.
5411 * ADC state:
5412 * ADC must be disabled.
5413 * @rmtoll PWRR VREFPROT LL_ADC_SetVrefProtection\n
5414 * PWRR VREFSECSMP LL_ADC_SetVrefProtection
5415 * @param ADCx ADC instance
5416 * @param VrefProtection This parameter can be one of the following values:
5417 * @arg @ref LL_ADC_VREF_PROT_DISABLE
5418 * @arg @ref LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE
5419 * @arg @ref LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE
5420 * @retval None
5421 */
LL_ADC_SetVrefProtection(ADC_TypeDef * ADCx,uint32_t VrefProtection)5422 __STATIC_INLINE void LL_ADC_SetVrefProtection(ADC_TypeDef *ADCx, uint32_t VrefProtection)
5423 {
5424 MODIFY_REG(ADCx->PWRR, ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP, VrefProtection);
5425 }
5426
5427 /**
5428 * @brief ADC VREF protection when multiple ADCs are working simultaneously
5429 * @rmtoll PWRR VREFPROT LL_ADC_GetVrefProtection\n
5430 * PWRR VREFSECSMP LL_ADC_GetVrefProtection
5431 * @param ADCx ADC instance
5432 * @retval Returned value can be one of the following values:
5433 * @arg @ref LL_ADC_VREF_PROT_DISABLE
5434 * @arg @ref LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE
5435 * @arg @ref LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE
5436 */
LL_ADC_GetVrefProtection(const ADC_TypeDef * ADCx)5437 __STATIC_INLINE uint32_t LL_ADC_GetVrefProtection(const ADC_TypeDef *ADCx)
5438 {
5439 return (uint32_t)(READ_BIT(ADCx->PWRR, ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP));
5440 }
5441
5442 /**
5443 * @brief Set ADC continuous conversion mode on ADC group regular.
5444 * @note Description of ADC continuous conversion mode:
5445 * - single mode: one conversion per trigger
5446 * - continuous mode: after the first trigger, following
5447 * conversions launched successively automatically.
5448 * @note It is not possible to enable both ADC group regular
5449 * continuous mode and sequencer discontinuous mode.
5450 * @note On this STM32 series, setting of this feature is conditioned to
5451 * ADC state:
5452 * ADC must be disabled or enabled without conversion on going
5453 * on group regular.
5454 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
5455 * @param ADCx ADC instance
5456 * @param Continuous This parameter can be one of the following values:
5457 * @arg @ref LL_ADC_REG_CONV_SINGLE
5458 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
5459 * @retval None
5460 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)5461 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
5462 {
5463 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
5464 }
5465
5466 /**
5467 * @brief Get ADC continuous conversion mode on ADC group regular.
5468 * @note Description of ADC continuous conversion mode:
5469 * - single mode: one conversion per trigger
5470 * - continuous mode: after the first trigger, following
5471 * conversions launched successively automatically.
5472 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
5473 * @param ADCx ADC instance
5474 * @retval Returned value can be one of the following values:
5475 * @arg @ref LL_ADC_REG_CONV_SINGLE
5476 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
5477 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)5478 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
5479 {
5480 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
5481 }
5482
5483 /**
5484 * @brief Set ADC data transfer mode
5485 * @note Conversion data can be either:
5486 * - Available in Data Register
5487 * - Transferred by DMA in one shot mode
5488 * - Transferred by DMA in circular mode
5489 * - Transferred to MDF data register
5490 * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode
5491 * @param ADCx ADC instance
5492 * @param DataTransferMode This parameter can be one of the following values:
5493 * @arg @ref LL_ADC_REG_DR_TRANSFER
5494 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
5495 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
5496 * @arg @ref LL_ADC_REG_MDF_TRANSFER
5497 * @retval None
5498 */
LL_ADC_REG_SetDataTransferMode(ADC_TypeDef * ADCx,uint32_t DataTransferMode)5499 __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
5500 {
5501 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMNGT, DataTransferMode);
5502 }
5503
5504 /**
5505 * @brief Get ADC data transfer mode
5506 * @note Conversion data can be either:
5507 * - Available in Data Register
5508 * - Transferred by DMA in one shot mode
5509 * - Transferred by DMA in circular mode
5510 * - Transferred to DFSDM data register
5511 * @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode
5512 * @param ADCx ADC instance
5513 * @retval Returned value can be one of the following values:
5514 * @arg @ref LL_ADC_REG_DR_TRANSFER
5515 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
5516 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
5517 * @arg @ref LL_ADC_REG_MDF_TRANSFER
5518 */
LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef * ADCx)5519 __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx)
5520 {
5521 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMNGT));
5522 }
5523
5524 /**
5525 * @brief Set ADC group regular conversion data transfer: no transfer or
5526 * transfer by DMA, and DMA requests mode.
5527 * @note If transfer by DMA selected, specifies the DMA requests
5528 * mode:
5529 * - Limited mode (One shot mode): DMA transfer requests are stopped
5530 * when number of DMA data transfers (number of
5531 * ADC conversions) is reached.
5532 * This ADC mode is intended to be used with DMA mode non-circular.
5533 * - Unlimited mode: DMA transfer requests are unlimited,
5534 * whatever number of DMA data transfers (number of
5535 * ADC conversions).
5536 * This ADC mode is intended to be used with DMA mode circular.
5537 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5538 * mode non-circular:
5539 * when DMA transfers size will be reached, DMA will stop transfers of
5540 * ADC conversions data ADC will raise an overrun error
5541 * (overrun flag and interruption if enabled).
5542 * @note To configure DMA source address (peripheral address),
5543 * use function @ref LL_ADC_DMA_GetRegAddr().
5544 * @note On this STM32 series, setting of this feature is conditioned to
5545 * ADC state:
5546 * ADC must be disabled or enabled without conversion on going
5547 * on group regular.
5548 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
5549 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
5550 * @param ADCx ADC instance
5551 * @param DMATransfer This parameter can be one of the following values:
5552 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
5553 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
5554 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
5555 * @retval None
5556 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)5557 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
5558 {
5559 MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG, DMATransfer);
5560 }
5561
5562 /**
5563 * @brief Get ADC group regular conversion data transfer: no transfer or
5564 * transfer by DMA, and DMA requests mode.
5565 * @note If transfer by DMA selected, specifies the DMA requests
5566 * mode:
5567 * - Limited mode (One shot mode): DMA transfer requests are stopped
5568 * when number of DMA data transfers (number of
5569 * ADC conversions) is reached.
5570 * This ADC mode is intended to be used with DMA mode non-circular.
5571 * - Unlimited mode: DMA transfer requests are unlimited,
5572 * whatever number of DMA data transfers (number of
5573 * ADC conversions).
5574 * This ADC mode is intended to be used with DMA mode circular.
5575 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5576 * mode non-circular:
5577 * when DMA transfers size will be reached, DMA will stop transfers of
5578 * ADC conversions data ADC will raise an overrun error
5579 * (overrun flag and interruption if enabled).
5580 * @note To configure DMA source address (peripheral address),
5581 * use function @ref LL_ADC_DMA_GetRegAddr().
5582 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
5583 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
5584 * @param ADCx ADC instance
5585 * @retval Returned value can be one of the following values:
5586 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
5587 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
5588 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
5589 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)5590 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
5591 {
5592 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG));
5593 }
5594
5595 /**
5596 * @brief Set ADC group regular behavior in case of overrun:
5597 * data preserved or overwritten.
5598 * @note Compatibility with devices without feature overrun:
5599 * other devices without this feature have a behavior
5600 * equivalent to data overwritten.
5601 * The default setting of overrun is data preserved.
5602 * Therefore, for compatibility with all devices, parameter
5603 * overrun should be set to data overwritten.
5604 * @note On this STM32 series, setting of this feature is conditioned to
5605 * ADC state:
5606 * ADC must be disabled or enabled without conversion on going
5607 * on group regular.
5608 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
5609 * @param ADCx ADC instance
5610 * @param Overrun This parameter can be one of the following values:
5611 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
5612 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
5613 * @retval None
5614 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)5615 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
5616 {
5617 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
5618 }
5619
5620 /**
5621 * @brief Get ADC group regular behavior in case of overrun:
5622 * data preserved or overwritten.
5623 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
5624 * @param ADCx ADC instance
5625 * @retval Returned value can be one of the following values:
5626 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
5627 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
5628 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)5629 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
5630 {
5631 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
5632 }
5633
5634 /**
5635 * @}
5636 */
5637
5638 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
5639 * @{
5640 */
5641
5642 /**
5643 * @brief Set ADC group injected conversion trigger source:
5644 * internal (SW start) or from external peripheral (timer event,
5645 * external interrupt line).
5646 * @note On this STM32 series, setting trigger source to external trigger
5647 * also set trigger polarity to rising edge
5648 * (default setting for compatibility with some ADC on other
5649 * STM32 families having this setting set by HW default value).
5650 * In case of need to modify trigger edge, use
5651 * function @ref LL_ADC_INJ_SetTriggerEdge().
5652 * @note Availability of parameters of trigger sources from timer
5653 * depends on timers availability on the selected device.
5654 * @note On this STM32 series, setting of this feature is conditioned to
5655 * ADC state:
5656 * ADC must not be disabled. Can be enabled with or without conversion
5657 * on going on either groups regular or injected.
5658 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
5659 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
5660 * @param ADCx ADC instance
5661 * @param TriggerSource This parameter can be one of the following values:
5662 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5663 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5664 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5665 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5666 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
5667 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
5668 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
5669 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
5670 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
5671 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5672 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
5673 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
5674 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
5675 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5676 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
5677 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5678 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
5679 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
5680 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
5681 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
5682 * @retval None
5683 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)5684 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
5685 {
5686 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
5687 }
5688
5689 /**
5690 * @brief Get ADC group injected conversion trigger source:
5691 * internal (SW start) or from external peripheral (timer event,
5692 * external interrupt line).
5693 * @note To determine whether group injected trigger source is
5694 * internal (SW start) or external, without detail
5695 * of which peripheral is selected as external trigger,
5696 * (equivalent to
5697 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
5698 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
5699 * @note Availability of parameters of trigger sources from timer
5700 * depends on timers availability on the selected device.
5701 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
5702 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
5703 * @param ADCx ADC instance
5704 * @retval Returned value can be one of the following values:
5705 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5706 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5707 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5708 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5709 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
5710 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
5711 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
5712 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
5713 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
5714 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5715 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
5716 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
5717 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
5718 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5719 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
5720 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5721 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
5722 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
5723 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
5724 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
5725 */
LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef * ADCx)5726 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
5727 {
5728 __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
5729
5730 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
5731 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
5732 uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
5733
5734 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
5735 /* to match with triggers literals definition. */
5736 return ((trigger_source
5737 & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
5738 | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
5739 );
5740 }
5741
5742 /**
5743 * @brief Get ADC group injected conversion trigger source internal (SW start)
5744 or external
5745 * @note In case of group injected trigger source set to external trigger,
5746 * to determine which peripheral is selected as external trigger,
5747 * use function @ref LL_ADC_INJ_GetTriggerSource.
5748 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
5749 * @param ADCx ADC instance
5750 * @retval Value "0" if trigger source external trigger
5751 * Value "1" if trigger source SW start.
5752 */
LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)5753 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
5754 {
5755 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
5756 }
5757
5758 /**
5759 * @brief Set ADC group injected conversion trigger polarity.
5760 * Applicable only for trigger source set to external trigger.
5761 * @note On this STM32 series, setting of this feature is conditioned to
5762 * ADC state:
5763 * ADC must not be disabled. Can be enabled with or without conversion
5764 * on going on either groups regular or injected.
5765 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
5766 * @param ADCx ADC instance
5767 * @param ExternalTriggerEdge This parameter can be one of the following values:
5768 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5769 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5770 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5771 * @retval None
5772 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)5773 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
5774 {
5775 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
5776 }
5777
5778 /**
5779 * @brief Get ADC group injected conversion trigger polarity.
5780 * Applicable only for trigger source set to external trigger.
5781 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
5782 * @param ADCx ADC instance
5783 * @retval Returned value can be one of the following values:
5784 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5785 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5786 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5787 */
LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef * ADCx)5788 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
5789 {
5790 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
5791 }
5792
5793 /**
5794 * @brief Set ADC group injected sequencer length and scan direction.
5795 * @note This function performs configuration of:
5796 * - Sequence length: Number of ranks in the scan sequence.
5797 * - Sequence direction: Unless specified in parameters, sequencer
5798 * scan direction is forward (from rank 1 to rank n).
5799 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
5800 * ADC conversion on only 1 channel.
5801 * @note On this STM32 series, setting of this feature is conditioned to
5802 * ADC state:
5803 * ADC must not be disabled. Can be enabled with or without conversion
5804 * on going on either groups regular or injected.
5805 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
5806 * @param ADCx ADC instance
5807 * @param SequencerNbRanks This parameter can be one of the following values:
5808 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5809 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5810 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5811 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5812 * @retval None
5813 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)5814 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
5815 {
5816 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
5817 }
5818
5819 /**
5820 * @brief Get ADC group injected sequencer length and scan direction.
5821 * @note This function retrieves:
5822 * - Sequence length: Number of ranks in the scan sequence.
5823 * - Sequence direction: Unless specified in parameters, sequencer
5824 * scan direction is forward (from rank 1 to rank n).
5825 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
5826 * ADC conversion on only 1 channel.
5827 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
5828 * @param ADCx ADC instance
5829 * @retval Returned value can be one of the following values:
5830 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5831 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5832 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5833 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5834 */
LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef * ADCx)5835 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
5836 {
5837 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
5838 }
5839
5840 /**
5841 * @brief Set ADC group injected sequencer discontinuous mode:
5842 * sequence subdivided and scan conversions interrupted every selected
5843 * number of ranks.
5844 * @note It is not possible to enable both ADC group injected
5845 * auto-injected mode and sequencer discontinuous mode.
5846 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
5847 * @param ADCx ADC instance
5848 * @param SeqDiscont This parameter can be one of the following values:
5849 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
5850 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
5851 * @retval None
5852 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)5853 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
5854 {
5855 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JDISCEN, SeqDiscont);
5856 }
5857
5858 /**
5859 * @brief Get ADC group injected sequencer discontinuous mode:
5860 * sequence subdivided and scan conversions interrupted every selected
5861 * number of ranks.
5862 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
5863 * @param ADCx ADC instance
5864 * @retval Returned value can be one of the following values:
5865 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
5866 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
5867 */
LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef * ADCx)5868 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
5869 {
5870 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JDISCEN));
5871 }
5872
5873 /**
5874 * @brief Set ADC group injected sequence: channel on the selected
5875 * sequence rank.
5876 * @note Depending on devices and packages, some channels may not be available.
5877 * Refer to device datasheet for channels availability.
5878 * @note On this STM32 series, to measure internal channels (VrefInt,
5879 * TempSensor, ...), measurement paths to internal channels must be
5880 * enabled separately.
5881 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5882 * @note On STM32U5, some fast channels are available: fast analog inputs
5883 * coming from GPIO pads (ADC_IN0..5).
5884 * @note On this STM32 series, setting of this feature is conditioned to
5885 * ADC state:
5886 * ADC must not be disabled. Can be enabled with or without conversion
5887 * on going on either groups regular or injected.
5888 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
5889 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
5890 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
5891 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
5892 * @param ADCx ADC instance
5893 * @param Rank This parameter can be one of the following values:
5894 * @arg @ref LL_ADC_INJ_RANK_1
5895 * @arg @ref LL_ADC_INJ_RANK_2
5896 * @arg @ref LL_ADC_INJ_RANK_3
5897 * @arg @ref LL_ADC_INJ_RANK_4
5898 * @param Channel This parameter can be one of the following values:
5899 * @arg @ref LL_ADC_CHANNEL_0 (3)
5900 * @arg @ref LL_ADC_CHANNEL_1 (3)
5901 * @arg @ref LL_ADC_CHANNEL_2 (3)
5902 * @arg @ref LL_ADC_CHANNEL_3 (3)
5903 * @arg @ref LL_ADC_CHANNEL_4 (3)
5904 * @arg @ref LL_ADC_CHANNEL_5 (3)
5905 * @arg @ref LL_ADC_CHANNEL_6
5906 * @arg @ref LL_ADC_CHANNEL_7
5907 * @arg @ref LL_ADC_CHANNEL_8
5908 * @arg @ref LL_ADC_CHANNEL_9
5909 * @arg @ref LL_ADC_CHANNEL_10
5910 * @arg @ref LL_ADC_CHANNEL_11
5911 * @arg @ref LL_ADC_CHANNEL_12
5912 * @arg @ref LL_ADC_CHANNEL_13
5913 * @arg @ref LL_ADC_CHANNEL_14
5914 * @arg @ref LL_ADC_CHANNEL_15
5915 * @arg @ref LL_ADC_CHANNEL_16
5916 * @arg @ref LL_ADC_CHANNEL_17
5917 * @arg @ref LL_ADC_CHANNEL_18
5918 * @arg @ref LL_ADC_CHANNEL_19
5919 * @arg @ref LL_ADC_CHANNEL_VREFINT
5920 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5921 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5922 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
5923 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
5924 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
5925 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
5926 *
5927 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
5928 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
5929 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5930 * Other channels are slow channels (conversion rate: refer to reference manual).
5931 * @retval None
5932 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)5933 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
5934 {
5935 /* Set bits with content of parameter "Channel" with bits position */
5936 /* in register depending on parameter "Rank". */
5937 /* Parameters "Rank" and "Channel" are used with masks because containing */
5938 /* other bits reserved for other purpose. */
5939 MODIFY_REG(ADCx->JSQR,
5940 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
5941 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
5942 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
5943 }
5944
5945 /**
5946 * @brief Get ADC group injected sequence: channel on the selected
5947 * sequence rank.
5948 * @note Depending on devices and packages, some channels may not be available.
5949 * Refer to device datasheet for channels availability.
5950 * @note Usage of the returned channel number:
5951 * - To reinject this channel into another function LL_ADC_xxx:
5952 * the returned channel number is only partly formatted on definition
5953 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5954 * with parts of literals LL_ADC_CHANNEL_x or using
5955 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5956 * Then the selected literal LL_ADC_CHANNEL_x can be used
5957 * as parameter for another function.
5958 * - To get the channel number in decimal format:
5959 * process the returned value with the helper macro
5960 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5961 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
5962 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
5963 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
5964 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
5965 * @param ADCx ADC instance
5966 * @param Rank This parameter can be one of the following values:
5967 * @arg @ref LL_ADC_INJ_RANK_1
5968 * @arg @ref LL_ADC_INJ_RANK_2
5969 * @arg @ref LL_ADC_INJ_RANK_3
5970 * @arg @ref LL_ADC_INJ_RANK_4
5971 * @retval Returned value can be one of the following values:
5972 * @arg @ref LL_ADC_CHANNEL_0 (3)
5973 * @arg @ref LL_ADC_CHANNEL_1 (3)
5974 * @arg @ref LL_ADC_CHANNEL_2 (3)
5975 * @arg @ref LL_ADC_CHANNEL_3 (3)
5976 * @arg @ref LL_ADC_CHANNEL_4 (3)
5977 * @arg @ref LL_ADC_CHANNEL_5 (3)
5978 * @arg @ref LL_ADC_CHANNEL_6
5979 * @arg @ref LL_ADC_CHANNEL_7
5980 * @arg @ref LL_ADC_CHANNEL_8
5981 * @arg @ref LL_ADC_CHANNEL_9
5982 * @arg @ref LL_ADC_CHANNEL_10
5983 * @arg @ref LL_ADC_CHANNEL_11
5984 * @arg @ref LL_ADC_CHANNEL_12
5985 * @arg @ref LL_ADC_CHANNEL_13
5986 * @arg @ref LL_ADC_CHANNEL_14
5987 * @arg @ref LL_ADC_CHANNEL_15
5988 * @arg @ref LL_ADC_CHANNEL_16
5989 * @arg @ref LL_ADC_CHANNEL_17
5990 * @arg @ref LL_ADC_CHANNEL_18
5991 * @arg @ref LL_ADC_CHANNEL_19
5992 * @arg @ref LL_ADC_CHANNEL_VREFINT
5993 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5994 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5995 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
5996 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
5997 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
5998 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
5999 *
6000 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6001 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6002 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6003 * Other channels are slow channels (conversion rate: refer to reference manual).
6004 * (1, 2) For ADC channel read back from ADC register,
6005 * comparison with internal channel parameter to be done
6006 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
6007 */
LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)6008 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
6009 {
6010 return (uint32_t)((READ_BIT(ADCx->JSQR,
6011 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
6012 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
6013 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
6014 );
6015 }
6016
6017 /**
6018 * @brief Set ADC group injected conversion trigger:
6019 * independent or from ADC group regular.
6020 * @note This mode can be used to extend number of data registers
6021 * updated after one ADC conversion trigger and with data
6022 * permanently kept (not erased by successive conversions of scan of
6023 * ADC sequencer ranks), up to 5 data registers:
6024 * 1 data register on ADC group regular, 4 data registers
6025 * on ADC group injected.
6026 * @note If ADC group injected injected trigger source is set to an
6027 * external trigger, this feature must be must be set to
6028 * independent trigger.
6029 * ADC group injected automatic trigger is compliant only with
6030 * group injected trigger source set to SW start, without any
6031 * further action on ADC group injected conversion start or stop:
6032 * in this case, ADC group injected is controlled only
6033 * from ADC group regular.
6034 * @note It is not possible to enable both ADC group injected
6035 * auto-injected mode and sequencer discontinuous mode.
6036 * @note On this STM32 series, setting of this feature is conditioned to
6037 * ADC state:
6038 * ADC must be disabled or enabled without conversion on going
6039 * on either groups regular or injected.
6040 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
6041 * @param ADCx ADC instance
6042 * @param TrigAuto This parameter can be one of the following values:
6043 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
6044 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
6045 * @retval None
6046 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)6047 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
6048 {
6049 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JAUTO, TrigAuto);
6050 }
6051
6052 /**
6053 * @brief Get ADC group injected conversion trigger:
6054 * independent or from ADC group regular.
6055 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
6056 * @param ADCx ADC instance
6057 * @retval Returned value can be one of the following values:
6058 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
6059 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
6060 */
LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef * ADCx)6061 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
6062 {
6063 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JAUTO));
6064 }
6065
6066 /**
6067 * @brief Set one context on ADC group injected that will be checked in
6068 * contexts queue.
6069 * @note A context is a setting of group injected sequencer:
6070 * - group injected trigger
6071 * - sequencer length
6072 * - sequencer ranks
6073 * This function is intended to be used when contexts queue is enabled,
6074 * because the sequence must be fully configured in one time
6075 * (functions to set separately injected trigger and sequencer channels
6076 * cannot be used):
6077 * @note In the contexts queue, only the active context can be read.
6078 * The parameters of this function can be read using functions:
6079 * @arg @ref LL_ADC_INJ_GetTriggerSource()
6080 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
6081 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
6082 * @note On this STM32 series, to measure internal channels (VrefInt,
6083 * TempSensor, ...), measurement paths to internal channels must be
6084 * enabled separately.
6085 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
6086 * @note On STM32U5, some fast channels are available: fast analog inputs
6087 * coming from GPIO pads (ADC_IN0..5).
6088 * @note On this STM32 series, setting of this feature is conditioned to
6089 * ADC state:
6090 * ADC must not be disabled. Can be enabled with or without conversion
6091 * on going on either groups regular or injected.
6092 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
6093 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
6094 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
6095 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
6096 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
6097 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
6098 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
6099 * @param ADCx ADC instance
6100 * @param TriggerSource This parameter can be one of the following values:
6101 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
6102 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
6103 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
6104 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
6105 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
6106 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
6107 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
6108 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
6109 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
6110 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
6111 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
6112 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
6113 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
6114 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
6115 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
6116 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
6117 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
6118 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
6119 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
6120 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
6121 * @param ExternalTriggerEdge This parameter can be one of the following values:
6122 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
6123 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
6124 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
6125 *
6126 * Note: This parameter is discarded in case of SW start:
6127 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
6128 * @param SequencerNbRanks This parameter can be one of the following values:
6129 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
6130 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
6131 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
6132 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
6133 * @param Rank1_Channel This parameter can be one of the following values:
6134 * @arg @ref LL_ADC_CHANNEL_0 (3)
6135 * @arg @ref LL_ADC_CHANNEL_1 (3)
6136 * @arg @ref LL_ADC_CHANNEL_2 (3)
6137 * @arg @ref LL_ADC_CHANNEL_3 (3)
6138 * @arg @ref LL_ADC_CHANNEL_4 (3)
6139 * @arg @ref LL_ADC_CHANNEL_5 (3)
6140 * @arg @ref LL_ADC_CHANNEL_6
6141 * @arg @ref LL_ADC_CHANNEL_7
6142 * @arg @ref LL_ADC_CHANNEL_8
6143 * @arg @ref LL_ADC_CHANNEL_9
6144 * @arg @ref LL_ADC_CHANNEL_10
6145 * @arg @ref LL_ADC_CHANNEL_11
6146 * @arg @ref LL_ADC_CHANNEL_12
6147 * @arg @ref LL_ADC_CHANNEL_13
6148 * @arg @ref LL_ADC_CHANNEL_14
6149 * @arg @ref LL_ADC_CHANNEL_15
6150 * @arg @ref LL_ADC_CHANNEL_16
6151 * @arg @ref LL_ADC_CHANNEL_17
6152 * @arg @ref LL_ADC_CHANNEL_18
6153 * @arg @ref LL_ADC_CHANNEL_19
6154 * @arg @ref LL_ADC_CHANNEL_VREFINT
6155 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6156 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6157 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6158 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6159 *
6160 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6161 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6162 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6163 * Other channels are slow channels (conversion rate: refer to reference manual).
6164 * @param Rank2_Channel This parameter can be one of the following values:
6165 * @arg @ref LL_ADC_CHANNEL_0 (3)
6166 * @arg @ref LL_ADC_CHANNEL_1 (3)
6167 * @arg @ref LL_ADC_CHANNEL_2 (3)
6168 * @arg @ref LL_ADC_CHANNEL_3 (3)
6169 * @arg @ref LL_ADC_CHANNEL_4 (3)
6170 * @arg @ref LL_ADC_CHANNEL_5 (3)
6171 * @arg @ref LL_ADC_CHANNEL_6
6172 * @arg @ref LL_ADC_CHANNEL_7
6173 * @arg @ref LL_ADC_CHANNEL_8
6174 * @arg @ref LL_ADC_CHANNEL_9
6175 * @arg @ref LL_ADC_CHANNEL_10
6176 * @arg @ref LL_ADC_CHANNEL_11
6177 * @arg @ref LL_ADC_CHANNEL_12
6178 * @arg @ref LL_ADC_CHANNEL_13
6179 * @arg @ref LL_ADC_CHANNEL_14
6180 * @arg @ref LL_ADC_CHANNEL_15
6181 * @arg @ref LL_ADC_CHANNEL_16
6182 * @arg @ref LL_ADC_CHANNEL_17
6183 * @arg @ref LL_ADC_CHANNEL_18
6184 * @arg @ref LL_ADC_CHANNEL_19
6185 * @arg @ref LL_ADC_CHANNEL_VREFINT
6186 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6187 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6188 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6189 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6190 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
6191 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
6192 *
6193 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6194 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6195 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6196 * Other channels are slow channels (conversion rate: refer to reference manual).
6197 * @param Rank3_Channel This parameter can be one of the following values:
6198 * @arg @ref LL_ADC_CHANNEL_0 (3)
6199 * @arg @ref LL_ADC_CHANNEL_1 (3)
6200 * @arg @ref LL_ADC_CHANNEL_2 (3)
6201 * @arg @ref LL_ADC_CHANNEL_3 (3)
6202 * @arg @ref LL_ADC_CHANNEL_4 (3)
6203 * @arg @ref LL_ADC_CHANNEL_5 (3)
6204 * @arg @ref LL_ADC_CHANNEL_6
6205 * @arg @ref LL_ADC_CHANNEL_7
6206 * @arg @ref LL_ADC_CHANNEL_8
6207 * @arg @ref LL_ADC_CHANNEL_9
6208 * @arg @ref LL_ADC_CHANNEL_10
6209 * @arg @ref LL_ADC_CHANNEL_11
6210 * @arg @ref LL_ADC_CHANNEL_12
6211 * @arg @ref LL_ADC_CHANNEL_13
6212 * @arg @ref LL_ADC_CHANNEL_14
6213 * @arg @ref LL_ADC_CHANNEL_15
6214 * @arg @ref LL_ADC_CHANNEL_16
6215 * @arg @ref LL_ADC_CHANNEL_17
6216 * @arg @ref LL_ADC_CHANNEL_18
6217 * @arg @ref LL_ADC_CHANNEL_19
6218 * @arg @ref LL_ADC_CHANNEL_VREFINT
6219 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6220 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6221 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6222 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6223 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
6224 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
6225 *
6226 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6227 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6228 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6229 * Other channels are slow channels (conversion rate: refer to reference manual).
6230 * @param Rank4_Channel This parameter can be one of the following values:
6231 * @arg @ref LL_ADC_CHANNEL_0 (3)
6232 * @arg @ref LL_ADC_CHANNEL_1 (3)
6233 * @arg @ref LL_ADC_CHANNEL_2 (3)
6234 * @arg @ref LL_ADC_CHANNEL_3 (3)
6235 * @arg @ref LL_ADC_CHANNEL_4 (3)
6236 * @arg @ref LL_ADC_CHANNEL_5 (3)
6237 * @arg @ref LL_ADC_CHANNEL_6
6238 * @arg @ref LL_ADC_CHANNEL_7
6239 * @arg @ref LL_ADC_CHANNEL_8
6240 * @arg @ref LL_ADC_CHANNEL_9
6241 * @arg @ref LL_ADC_CHANNEL_10
6242 * @arg @ref LL_ADC_CHANNEL_11
6243 * @arg @ref LL_ADC_CHANNEL_12
6244 * @arg @ref LL_ADC_CHANNEL_13
6245 * @arg @ref LL_ADC_CHANNEL_14
6246 * @arg @ref LL_ADC_CHANNEL_15
6247 * @arg @ref LL_ADC_CHANNEL_16
6248 * @arg @ref LL_ADC_CHANNEL_17
6249 * @arg @ref LL_ADC_CHANNEL_18
6250 * @arg @ref LL_ADC_CHANNEL_19
6251 * @arg @ref LL_ADC_CHANNEL_VREFINT
6252 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6253 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6254 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6255 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6256 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
6257 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
6258 *
6259 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6260 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6261 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6262 * Other channels are slow channels (conversion rate: refer to reference manual).
6263 * @retval None
6264 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)6265 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
6266 uint32_t TriggerSource,
6267 uint32_t ExternalTriggerEdge,
6268 uint32_t SequencerNbRanks,
6269 uint32_t Rank1_Channel,
6270 uint32_t Rank2_Channel,
6271 uint32_t Rank3_Channel,
6272 uint32_t Rank4_Channel)
6273 {
6274 /* Set bits with content of parameter "Rankx_Channel" with bits position */
6275 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
6276 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
6277 /* because containing other bits reserved for other purpose. */
6278 /* If parameter "TriggerSource" is set to SW start, then parameter */
6279 /* "ExternalTriggerEdge" is discarded. */
6280 /* "TriggerSource" is define dwith default edge (rising): */
6281 /* So we need to discard the default edge else the edge will not as expected*/
6282 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
6283 MODIFY_REG(ADCx->JSQR,
6284 ADC_JSQR_JEXTSEL |
6285 ADC_JSQR_JEXTEN |
6286 ADC_JSQR_JSQ4 |
6287 ADC_JSQR_JSQ3 |
6288 ADC_JSQR_JSQ2 |
6289 ADC_JSQR_JSQ1 |
6290 ADC_JSQR_JL,
6291 (TriggerSource & ADC_JSQR_JEXTSEL) |
6292 (ExternalTriggerEdge * (is_trigger_not_sw)) |
6293 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
6294 << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6295 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
6296 << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6297 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
6298 << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6299 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
6300 << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6301 SequencerNbRanks
6302 );
6303 }
6304
6305 /**
6306 * @}
6307 */
6308
6309 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
6310 * @{
6311 */
6312
6313 /**
6314 * @brief Set sampling time of the selected ADC channel
6315 * Unit: ADC clock cycles.
6316 * @note On this device, sampling time is on channel scope: independently
6317 * of channel mapped on ADC group regular or injected.
6318 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
6319 * converted:
6320 * sampling time constraints must be respected (sampling time can be
6321 * adjusted in function of ADC clock frequency and sampling time
6322 * setting).
6323 * Refer to device datasheet for timings values (parameters TS_vrefint,
6324 * TS_temp, ...).
6325 * @note Conversion time is the addition of sampling time and processing time.
6326 * On this STM32 series, ADC processing time is:
6327 * - 12.5 ADC clock cycles at ADC resolution 12 bits
6328 * - 10.5 ADC clock cycles at ADC resolution 10 bits
6329 * - 8.5 ADC clock cycles at ADC resolution 8 bits
6330 * - 6.5 ADC clock cycles at ADC resolution 6 bits
6331 * @note In case of ADC conversion of internal channel (VrefInt,
6332 * temperature sensor, ...), a sampling time minimum value
6333 * is required.
6334 * Refer to device datasheet.
6335 * @note On this STM32 series, setting of this feature is conditioned to
6336 * ADC state:
6337 * ADC must be disabled or enabled without conversion on going
6338 * on either groups regular or injected.
6339 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
6340 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
6341 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
6342 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
6343 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
6344 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
6345 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
6346 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
6347 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
6348 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
6349 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
6350 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
6351 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
6352 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
6353 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
6354 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
6355 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
6356 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
6357 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
6358 * @param ADCx ADC instance
6359 * @param Channel This parameter can be one of the following values:
6360 * @arg @ref LL_ADC_CHANNEL_0 (3)
6361 * @arg @ref LL_ADC_CHANNEL_1 (3)
6362 * @arg @ref LL_ADC_CHANNEL_2 (3)
6363 * @arg @ref LL_ADC_CHANNEL_3 (3)
6364 * @arg @ref LL_ADC_CHANNEL_4 (3)
6365 * @arg @ref LL_ADC_CHANNEL_5 (3)
6366 * @arg @ref LL_ADC_CHANNEL_6
6367 * @arg @ref LL_ADC_CHANNEL_7
6368 * @arg @ref LL_ADC_CHANNEL_8
6369 * @arg @ref LL_ADC_CHANNEL_9
6370 * @arg @ref LL_ADC_CHANNEL_10
6371 * @arg @ref LL_ADC_CHANNEL_11
6372 * @arg @ref LL_ADC_CHANNEL_12
6373 * @arg @ref LL_ADC_CHANNEL_13
6374 * @arg @ref LL_ADC_CHANNEL_14
6375 * @arg @ref LL_ADC_CHANNEL_15
6376 * @arg @ref LL_ADC_CHANNEL_16
6377 * @arg @ref LL_ADC_CHANNEL_17
6378 * @arg @ref LL_ADC_CHANNEL_18
6379 * @arg @ref LL_ADC_CHANNEL_19
6380 * @arg @ref LL_ADC_CHANNEL_VREFINT
6381 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6382 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6383 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6384 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6385 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
6386 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
6387 *
6388 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6389 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6390 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6391 * Other channels are slow channels (conversion rate: refer to reference manual).
6392 * @param SamplingTime This parameter can be one of the following values, In case of ADC1 instance:
6393 * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES (1)
6394 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES (1)
6395 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES (1)
6396 * @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES (1)
6397 * @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES (1)
6398 * @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES (1)
6399 * @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES (1)
6400 * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES (1)
6401 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 (2)
6402 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 (2)
6403 *
6404 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6405 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6406 * @retval None
6407 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)6408 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
6409 {
6410 if (ADCx != ADC4) /* ADC1 or ADC2 */
6411 {
6412 /* Set bits with content of parameter "SamplingTime" with bits position */
6413 /* in register and register position depending on parameter "Channel". */
6414 /* Parameter "Channel" is used with masks because containing */
6415 /* other bits reserved for other purpose. */
6416 uint32_t shift_value = ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) - (10UL * ((Channel \
6417 & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
6418 >> ADC_SMPRX_REGOFFSET_POS))) * 3UL);
6419 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
6420 >> ADC_SMPRX_REGOFFSET_POS));
6421
6422 MODIFY_REG(*preg, ADC_SMPR1_SMP0 << shift_value, SamplingTime << shift_value);
6423
6424 }
6425 else
6426 {
6427 /* Parameter "Channel" is used with masks because containing */
6428 /* other bits reserved for other purpose. It needs to be converted to decimal */
6429 /* to select the bit position */
6430 MODIFY_REG(ADCx->SMPR1,
6431 ((Channel & ADC_CHANNEL_ID_BITFIELD_MASK) << ADC4_SMPR_SMPSEL0_BITOFFSET_POS),
6432 ((Channel & ADC_CHANNEL_ID_BITFIELD_MASK) << ADC4_SMPR_SMPSEL0_BITOFFSET_POS)
6433 & (SamplingTime & ADC4_SAMPLING_TIME_CH_MASK)
6434 );
6435 }
6436 }
6437
6438 /**
6439 * @brief Get sampling time of the selected ADC channel
6440 * Unit: ADC clock cycles.
6441 * @note On this device, sampling time is on channel scope: independently
6442 * of channel mapped on ADC group regular or injected.
6443 * @note Conversion time is the addition of sampling time and processing time.
6444 * On this STM32 series, ADC processing time is:
6445 * - 12.5 ADC clock cycles at ADC resolution 12 bits
6446 * - 10.5 ADC clock cycles at ADC resolution 10 bits
6447 * - 8.5 ADC clock cycles at ADC resolution 8 bits
6448 * - 6.5 ADC clock cycles at ADC resolution 6 bits
6449 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
6450 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
6451 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
6452 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
6453 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
6454 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
6455 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
6456 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
6457 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
6458 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
6459 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
6460 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
6461 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
6462 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
6463 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
6464 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
6465 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
6466 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
6467 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
6468 * @param ADCx ADC instance
6469 * @param Channel This parameter can be one of the following values:
6470 * @arg @ref LL_ADC_CHANNEL_0 (3)
6471 * @arg @ref LL_ADC_CHANNEL_1 (3)
6472 * @arg @ref LL_ADC_CHANNEL_2 (3)
6473 * @arg @ref LL_ADC_CHANNEL_3 (3)
6474 * @arg @ref LL_ADC_CHANNEL_4 (3)
6475 * @arg @ref LL_ADC_CHANNEL_5 (3)
6476 * @arg @ref LL_ADC_CHANNEL_6
6477 * @arg @ref LL_ADC_CHANNEL_7
6478 * @arg @ref LL_ADC_CHANNEL_8
6479 * @arg @ref LL_ADC_CHANNEL_9
6480 * @arg @ref LL_ADC_CHANNEL_10
6481 * @arg @ref LL_ADC_CHANNEL_11
6482 * @arg @ref LL_ADC_CHANNEL_12
6483 * @arg @ref LL_ADC_CHANNEL_13
6484 * @arg @ref LL_ADC_CHANNEL_14
6485 * @arg @ref LL_ADC_CHANNEL_15
6486 * @arg @ref LL_ADC_CHANNEL_16
6487 * @arg @ref LL_ADC_CHANNEL_17
6488 * @arg @ref LL_ADC_CHANNEL_18
6489 * @arg @ref LL_ADC_CHANNEL_19
6490 * @arg @ref LL_ADC_CHANNEL_VREFINT
6491 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6492 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6493 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6494 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6495 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
6496 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
6497 *
6498 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6499 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6500 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6501 * Other channels are slow channels (conversion rate: refer to reference manual).
6502 * @retval In case of ADC1 insatnace, Returned value can be one of the following values:
6503 * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES (1)
6504 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES (1)
6505 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES (1)
6506 * @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES (1)
6507 * @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES (1)
6508 * @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES (1)
6509 * @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES (1)
6510 * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES (1)
6511 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 (2)
6512 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 (2)
6513 *
6514 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6515 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6516 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)6517 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
6518 {
6519 if (ADCx != ADC4) /* (ADCx == ADC1) || (ADCx == ADC2) */
6520 {
6521 uint32_t shift_value = ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) - (10UL * ((Channel \
6522 & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
6523 >> ADC_SMPRX_REGOFFSET_POS))) * 3UL);
6524 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
6525 >> ADC_SMPRX_REGOFFSET_POS));
6526
6527 return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << shift_value) >> shift_value);
6528 }
6529 else /* ADCx == ADC4 */
6530 {
6531 uint32_t smpr = READ_REG(ADCx->SMPR1);
6532
6533 /* Retrieve sampling time bit corresponding to the selected channel */
6534 /* and shift it to position 0. */
6535 uint32_t smp_channel_posbit0 = ((smpr & ADC4_SAMPLING_TIME_CH_MASK)
6536 >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) \
6537 >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
6538 + ADC4_SMPR_SMPSEL0_BITOFFSET_POS)
6539 & 0x1FUL));
6540
6541 /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
6542 return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
6543 | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
6544 }
6545 }
6546
6547 /**
6548 * @brief Set mode single-ended or differential input of the selected
6549 * ADC channel.
6550 * @note Channel ending is on channel scope: independently of channel mapped
6551 * on ADC group regular or injected.
6552 * In differential mode: Differential measurement is carried out
6553 * between the selected channel 'i' (positive input) and
6554 * channel 'i+1' (negative input). Only channel 'i' has to be
6555 * configured, channel 'i+1' is configured automatically.
6556 * @note Refer to Reference Manual to ensure the selected channel is
6557 * available in differential mode.
6558 * For example, internal channels (VrefInt, TempSensor, ...) are
6559 * not available in differential mode.
6560 * @note When configuring a channel 'i' in differential mode,
6561 * the channel 'i+1' is not usable separately.
6562 * @note On STM32U5, some channels are internally fixed to single-ended inputs
6563 * configuration:
6564 * - ADC1: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
6565 * - ADC2: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
6566 * - ADC4: None
6567 * @note For ADC channels configured in differential mode, both inputs
6568 * should be biased at (Vref+)/2 +/-200mV.
6569 * (Vref+ is the analog voltage reference)
6570 * @note On this STM32 series, setting of this feature is conditioned to
6571 * ADC state:
6572 * ADC must be ADC disabled.
6573 * @note One or several values can be selected.
6574 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
6575 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
6576 * @param ADCx ADC instance
6577 * @param Channel This parameter can be one of the following values:
6578 * @arg @ref LL_ADC_CHANNEL_1
6579 * @arg @ref LL_ADC_CHANNEL_2
6580 * @arg @ref LL_ADC_CHANNEL_3
6581 * @arg @ref LL_ADC_CHANNEL_4
6582 * @arg @ref LL_ADC_CHANNEL_5
6583 * @arg @ref LL_ADC_CHANNEL_10
6584 * @arg @ref LL_ADC_CHANNEL_11
6585 * @arg @ref LL_ADC_CHANNEL_12
6586 * @arg @ref LL_ADC_CHANNEL_13
6587 * @arg @ref LL_ADC_CHANNEL_14
6588 * @arg @ref LL_ADC_CHANNEL_15
6589 * @arg @ref LL_ADC_CHANNEL_16
6590 * @arg @ref LL_ADC_CHANNEL_17
6591 * @arg @ref LL_ADC_CHANNEL_18
6592 * @arg @ref LL_ADC_CHANNEL_19
6593 * @param SingleDiff This parameter can be a combination of the following values:
6594 * @arg @ref LL_ADC_SINGLE_ENDED
6595 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6596 * @retval None
6597 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)6598 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
6599 {
6600 /* Bits of channels in single or differential mode are set only for */
6601 /* differential mode (for single mode, mask of bits allowed to be set is */
6602 /* shifted out of range of bits of channels in single or differential mode. */
6603 MODIFY_REG(ADCx->DIFSEL,
6604 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
6605 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff \
6606 & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
6607 }
6608
6609 /**
6610 * @brief Get mode single-ended or differential input of the selected
6611 * ADC channel.
6612 * @note When configuring a channel 'i' in differential mode,
6613 * the channel 'i+1' is not usable separately.
6614 * Therefore, to ensure a channel is configured in single-ended mode,
6615 * the configuration of channel itself and the channel 'i-1' must be
6616 * read back (to ensure that the selected channel channel has not been
6617 * configured in differential mode by the previous channel).
6618 * @note Refer to Reference Manual to ensure the selected channel is
6619 * available in differential mode.
6620 * For example, internal channels (VrefInt, TempSensor, ...) are
6621 * not available in differential mode.
6622 * @note When configuring a channel 'i' in differential mode,
6623 * the channel 'i+1' is not usable separately.
6624 * @note On STM32U5, some channels are internally fixed to single-ended inputs
6625 * configuration:
6626 * - ADC1: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
6627 * - ADC2: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
6628 * - ADC4: None
6629 * @note One or several values can be selected. In this case, the value
6630 * returned is null if all channels are in single ended-mode.
6631 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
6632 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
6633 * @param ADCx ADC instance
6634 * @param Channel This parameter can be a combination of the following values:
6635 * @arg @ref LL_ADC_CHANNEL_1
6636 * @arg @ref LL_ADC_CHANNEL_2
6637 * @arg @ref LL_ADC_CHANNEL_3
6638 * @arg @ref LL_ADC_CHANNEL_4
6639 * @arg @ref LL_ADC_CHANNEL_5
6640 * @arg @ref LL_ADC_CHANNEL_10
6641 * @arg @ref LL_ADC_CHANNEL_11
6642 * @arg @ref LL_ADC_CHANNEL_12
6643 * @arg @ref LL_ADC_CHANNEL_13
6644 * @arg @ref LL_ADC_CHANNEL_14
6645 * @arg @ref LL_ADC_CHANNEL_15
6646 * @arg @ref LL_ADC_CHANNEL_16
6647 * @arg @ref LL_ADC_CHANNEL_17
6648 * @arg @ref LL_ADC_CHANNEL_18
6649 * @arg @ref LL_ADC_CHANNEL_19
6650 * @retval 0: channel in single-ended mode, else: channel in differential mode
6651 */
LL_ADC_GetChannelSingleDiff(const ADC_TypeDef * ADCx,uint32_t Channel)6652 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
6653 {
6654 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
6655 }
6656
6657 /**
6658 * @}
6659 */
6660
6661 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
6662 * @{
6663 */
6664
6665 /**
6666 * @brief Set ADC analog watchdog monitored channels:
6667 * a single channel, multiple channels or all channels,
6668 * on ADC groups regular and-or injected.
6669 * @note Once monitored channels are selected, analog watchdog
6670 * is enabled.
6671 * @note In case of need to define a single channel to monitor
6672 * with analog watchdog from sequencer channel definition,
6673 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
6674 * @note On this STM32 series, there are 2 kinds of analog watchdog
6675 * instance:
6676 * - AWD standard (instance AWD1):
6677 * - channels monitored: can monitor 1 channel or all channels.
6678 * - groups monitored: ADC groups regular and-or injected.
6679 * - resolution: resolution is not limited (corresponds to
6680 * ADC resolution configured).
6681 * - AWD flexible (instances AWD2, AWD3):
6682 * - channels monitored: flexible on channels monitored, selection is
6683 * channel wise, from from 1 to all channels.
6684 * Specificity of this analog watchdog: Multiple channels can
6685 * be selected. For example:
6686 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6687 * - groups monitored: not selection possible (monitoring on both
6688 * groups regular and injected).
6689 * Channels selected are monitored on groups regular and injected:
6690 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6691 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6692 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6693 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6694 * the 2 LSB are ignored.
6695 * @note On this STM32 series, setting of this feature is conditioned to
6696 * ADC state:
6697 * ADC must be disabled or enabled without conversion on going
6698 * on either groups regular or injected.
6699 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
6700 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
6701 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
6702 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
6703 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
6704 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
6705 * @param ADCx ADC instance
6706 * @param AWDy This parameter can be one of the following values:
6707 * @arg @ref LL_ADC_AWD1
6708 * @arg @ref LL_ADC_AWD2
6709 * @arg @ref LL_ADC_AWD3
6710 * @param AWDChannelGroup This parameter can be one of the following values:
6711 * @arg @ref LL_ADC_AWD_DISABLE
6712 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
6713 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
6714 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
6715 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
6716 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
6717 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
6718 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
6719 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
6720 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
6721 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
6722 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
6723 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
6724 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
6725 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
6726 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
6727 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
6728 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
6729 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
6730 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
6731 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
6732 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
6733 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
6734 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
6735 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
6736 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
6737 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
6738 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
6739 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
6740 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
6741 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
6742 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
6743 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
6744 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
6745 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
6746 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
6747 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
6748 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
6749 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
6750 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
6751 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
6752 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
6753 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
6754 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
6755 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
6756 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
6757 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
6758 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
6759 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
6760 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
6761 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
6762 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
6763 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
6764 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
6765 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
6766 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
6767 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
6768 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
6769 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
6770 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
6771 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
6772 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
6773 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
6774 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
6775 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
6776 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
6777 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
6778 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
6779 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
6780 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
6781 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
6782 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
6783 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
6784 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC4_REG (0)(2)
6785 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC4_REG (0)(2)
6786 *
6787 * (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
6788 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6789 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6790 * @retval None
6791 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)6792 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
6793 {
6794 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
6795 /* in register and register position depending on parameter "AWDy". */
6796 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
6797 /* containing other bits reserved for other purpose. */
6798
6799 __IO uint32_t *preg;
6800 uint32_t channel_monitored;
6801
6802 if (AWDy == LL_ADC_AWD1)
6803 {
6804 /* Set pointer to register of selected analog watchdog */
6805 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
6806
6807 /* Compute channel monitored as number */
6808 channel_monitored = (AWDChannelGroup & ADC_AWD_CR1_CHANNEL_MASK);
6809 }
6810 else
6811 {
6812 /* Set pointer to register of selected analog watchdog */
6813 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CR3_REGOFFSET)) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL));
6814
6815 /* Compute channel monitored as bitfield */
6816 channel_monitored = (1UL << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) \
6817 >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
6818 /* Case of all channels monitored */
6819 channel_monitored |= ((1UL - ((AWDChannelGroup & ADC_CFGR1_AWD1SGL) >> ADC_CFGR1_AWD1SGL_Pos)) * 0x00FFFFFFUL);
6820 /* Case of no channel monitored */
6821 channel_monitored *= ((((AWDChannelGroup & (ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)) == 0UL) ? 0UL : 1UL));
6822 }
6823
6824 MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), channel_monitored);
6825 }
6826
6827 /**
6828 * @brief Get ADC analog watchdog monitored channel.
6829 * @note Usage of the returned channel number:
6830 * - To reinject this channel into another function LL_ADC_xxx:
6831 * the returned channel number is only partly formatted on definition
6832 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
6833 * with parts of literals LL_ADC_CHANNEL_x or using
6834 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
6835 * Then the selected literal LL_ADC_CHANNEL_x can be used
6836 * as parameter for another function.
6837 * - To get the channel number in decimal format:
6838 * process the returned value with the helper macro
6839 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
6840 * Applicable only when the analog watchdog is set to monitor
6841 * one channel.
6842 * @note On this STM32 series, there are 2 kinds of analog watchdog
6843 * instance:
6844 * - AWD standard (instance AWD1):
6845 * - channels monitored: can monitor 1 channel or all channels.
6846 * - groups monitored: ADC groups regular and-or injected.
6847 * - resolution: resolution is not limited (corresponds to
6848 * ADC resolution configured).
6849 * - AWD flexible (instances AWD2, AWD3):
6850 * - channels monitored: flexible on channels monitored, selection is
6851 * channel wise, from from 1 to all channels.
6852 * Specificity of this analog watchdog: Multiple channels can
6853 * be selected. For example:
6854 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6855 * - groups monitored: not selection possible (monitoring on both
6856 * groups regular and injected).
6857 * Channels selected are monitored on groups regular and injected:
6858 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6859 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6860 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6861 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6862 * the 2 LSB are ignored.
6863 * @note On this STM32 series, setting of this feature is conditioned to
6864 * ADC state:
6865 * ADC must be disabled or enabled without conversion on going
6866 * on either groups regular or injected.
6867 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
6868 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
6869 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
6870 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
6871 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
6872 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
6873 * @param ADCx ADC instance
6874 * @param AWDy This parameter can be one of the following values:
6875 * @arg @ref LL_ADC_AWD1
6876 * @arg @ref LL_ADC_AWD2 (1)
6877 * @arg @ref LL_ADC_AWD3 (1)
6878 *
6879 * (1) On this AWD number, monitored channel can be retrieved
6880 * if only 1 channel is programmed (or none or all channels).
6881 * This function cannot retrieve monitored channel if
6882 * multiple channels are programmed simultaneously
6883 * by bitfield.
6884 * @retval Returned value can be one of the following values:
6885 * @arg @ref LL_ADC_AWD_DISABLE
6886 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
6887 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
6888 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
6889 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
6890 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
6891 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
6892 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
6893 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
6894 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
6895 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
6896 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
6897 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
6898 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
6899 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
6900 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
6901 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
6902 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
6903 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
6904 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
6905 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
6906 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
6907 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
6908 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
6909 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
6910 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
6911 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
6912 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
6913 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
6914 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
6915 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
6916 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
6917 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
6918 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
6919 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
6920 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
6921 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
6922 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
6923 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
6924 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
6925 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
6926 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
6927 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
6928 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
6929 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
6930 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
6931 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
6932 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
6933 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
6934 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
6935 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
6936 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
6937 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
6938 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
6939 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
6940 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
6941 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
6942 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
6943 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
6944 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
6945 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
6946 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
6947 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
6948 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
6949 *
6950 * (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
6951 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)6952 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
6953 {
6954 const __IO uint32_t *preg;
6955
6956 if (AWDy == LL_ADC_AWD1)
6957 {
6958 /* Set pointer to register of selected analog watchdog */
6959 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
6960 }
6961 else
6962 {
6963 /* Set pointer to register of selected analog watchdog */
6964 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) \
6965 >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL));
6966 }
6967
6968 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
6969
6970 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
6971 /* (parameter value LL_ADC_AWD_DISABLE). */
6972 /* Else, the selected AWD is enabled and is monitoring a group of channels */
6973 /* or a single channel. */
6974 if (analog_wd_monit_channels != 0UL)
6975 {
6976 if (AWDy == LL_ADC_AWD1)
6977 {
6978 if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
6979 {
6980 /* AWD monitoring a group of channels */
6981 analog_wd_monit_channels = ((analog_wd_monit_channels | (0x000FFFFFUL)) & (~(ADC_CFGR1_AWD1CH)));
6982 }
6983 else
6984 {
6985 /* AWD monitoring a single channel */
6986 analog_wd_monit_channels = analog_wd_monit_channels;
6987 }
6988 }
6989 else
6990 {
6991 if (ADCx != ADC4)
6992 {
6993 if ((analog_wd_monit_channels & 0x000FFFFFUL) == 0x000FFFFFUL)
6994 {
6995 /* AWD monitoring a group of channels */
6996 analog_wd_monit_channels = (0x000FFFFFUL | ((ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)));
6997 }
6998 else
6999 {
7000 /* AWD monitoring a single channel */
7001 /* AWD monitoring a group of channels */
7002 analog_wd_monit_channels = ((ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
7003 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) \
7004 << ADC_CFGR1_AWD1CH_Pos));
7005 }
7006 }
7007 else
7008 {
7009 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
7010 {
7011 /* AWD monitoring a group of channels */
7012 analog_wd_monit_channels = (0x000FFFFFUL | (ADC_CFGR1_AWD1EN));
7013 }
7014 else
7015 {
7016 /* AWD monitoring a single channel */
7017 /* AWD monitoring a group of channels */
7018 analog_wd_monit_channels = ((ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
7019 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) \
7020 << ADC_CFGR1_AWD1CH_Pos));
7021 }
7022 }
7023 }
7024 }
7025
7026 return analog_wd_monit_channels;
7027 }
7028
7029 /**
7030 * @brief Set ADC analog watchdog threshold value of threshold
7031 * high or low.
7032 * @note In case of ADC resolution different of 12 bits,
7033 * analog watchdog thresholds data require a specific shift.
7034 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
7035 * @note On this STM32 series, there are 2 kinds of analog watchdog
7036 * instance:
7037 * - AWD standard (instance AWD1):
7038 * - channels monitored: can monitor 1 channel or all channels.
7039 * - groups monitored: ADC groups regular and-or injected.
7040 * - resolution: resolution is not limited (corresponds to
7041 * ADC resolution configured).
7042 * - AWD flexible (instances AWD2, AWD3):
7043 * - channels monitored: flexible on channels monitored, selection is
7044 * channel wise, from from 1 to all channels.
7045 * Specificity of this analog watchdog: Multiple channels can
7046 * be selected. For example:
7047 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
7048 * - groups monitored: not selection possible (monitoring on both
7049 * groups regular and injected).
7050 * Channels selected are monitored on groups regular and injected:
7051 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
7052 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
7053 * - resolution: resolution is limited to 8 bits: if ADC resolution is
7054 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
7055 * the 2 LSB are ignored.
7056 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
7057 * impacted: the comparison of analog watchdog thresholds is done
7058 * on oversampling intermediate computation (after ratio, before shift
7059 * application): intermediate register bitfield [32:7]
7060 * (26 most significant bits).
7061 * @note On this STM32 series, setting of this feature is conditioned to
7062 * ADC state:
7063 * ADC must be disabled or enabled without conversion on going
7064 * on either ADC groups regular or injected.
7065 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
7066 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
7067 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
7068 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
7069 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
7070 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
7071 * @param ADCx ADC instance
7072 * @param AWDy This parameter can be one of the following values:
7073 * @arg @ref LL_ADC_AWD1
7074 * @arg @ref LL_ADC_AWD2
7075 * @arg @ref LL_ADC_AWD3
7076 * @param AWDThresholdsHighLow This parameter can be one of the following values:
7077 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
7078 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
7079 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
7080 * @retval None
7081 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)7082 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
7083 uint32_t AWDThresholdValue)
7084 {
7085 __IO uint32_t *preg;
7086 /* Set bits with content of parameter "AWDThresholdValue" with bits */
7087 /* position in register and register position depending on parameters */
7088 /* "AWDThresholdsHighLow" and "AWDy". */
7089 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
7090 /* containing other bits reserved for other purpose. */
7091 if (ADCx != ADC4) /* ADCx == ADC1 or ADCx == ADC2 */
7092 {
7093 if (AWDy == LL_ADC_AWD1)
7094 {
7095 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (AWDThresholdsHighLow));
7096 }
7097 else
7098 {
7099 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
7100 >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
7101 + (AWDThresholdsHighLow));
7102 }
7103
7104 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
7105 }
7106 else /* ADCx == ADC4 */
7107 {
7108 if (AWDy == LL_ADC_AWD1)
7109 {
7110 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
7111 }
7112 else
7113 {
7114 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS))\
7115 + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
7116 }
7117
7118 MODIFY_REG(*preg,
7119 ADC_AWD1TR_LT1 << (AWDThresholdsHighLow * ADC_AWD1TR_HT1_Pos),
7120 AWDThresholdValue << (((AWDThresholdsHighLow << ADC_AWD1TR_HT1_Pos) & ADC_AWD_TRX_BIT_HIGH_MASK) \
7121 >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
7122
7123 }
7124 }
7125
7126 /**
7127 * @brief Get ADC analog watchdog threshold value of threshold high,
7128 * threshold low or raw data with ADC thresholds high and low
7129 * concatenated.
7130 * @note In case of ADC resolution different of 12 bits,
7131 * analog watchdog thresholds data require a specific shift.
7132 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
7133 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
7134 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
7135 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
7136 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
7137 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
7138 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
7139 * @param ADCx ADC instance
7140 * @param AWDy This parameter can be one of the following values:
7141 * @arg @ref LL_ADC_AWD1
7142 * @arg @ref LL_ADC_AWD2
7143 * @arg @ref LL_ADC_AWD3
7144 * @param AWDThresholdsHighLow This parameter can be one of the following values:
7145 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
7146 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
7147 * @retval In case of ADC1 instance, Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
7148 * @retval In case of ADC1 instance, Value between Min_Data=0x000 and Max_Data=0xFFF
7149 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)7150 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy,
7151 uint32_t AWDThresholdsHighLow)
7152 {
7153 const __IO uint32_t *preg;
7154 if (ADCx != ADC4) /* ADCx == ADC1 or ADCx == ADC2 */
7155 {
7156 if (AWDy == LL_ADC_AWD1)
7157 {
7158 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (AWDThresholdsHighLow));
7159 }
7160 else
7161 {
7162 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
7163 + (AWDThresholdsHighLow));
7164 }
7165
7166 return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
7167 }
7168 else /* ADCx == ADC4 */
7169 {
7170 if (AWDy == LL_ADC_AWD1)
7171 {
7172 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
7173
7174 }
7175 else
7176 {
7177 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS))\
7178 + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
7179 }
7180
7181 return (uint32_t)(READ_BIT(*preg,
7182 (ADC_AWD1TR_LT1 << (AWDThresholdsHighLow * ADC_AWD1TR_HT1_Pos)))
7183 >> (((AWDThresholdsHighLow << ADC_AWD1TR_HT1_Pos) & ADC_AWD_TRX_BIT_HIGH_MASK) \
7184 >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
7185 );
7186 }
7187 }
7188
7189 /**
7190 * @brief Set ADC analog watchdog thresholds value of both thresholds
7191 * high and low.
7192 * @note If value of only one threshold high or low must be set,
7193 * use function @ref LL_ADC_SetAnalogWDThresholds().
7194 * @note In case of ADC resolution different of 12 bits,
7195 * analog watchdog thresholds data require a specific shift.
7196 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
7197 * @note On this STM32 series, there are 2 kinds of analog watchdog
7198 * instance:
7199 * - AWD standard (instance AWD1):
7200 * - channels monitored: can monitor 1 channel or all channels.
7201 * - groups monitored: ADC group regular.
7202 * - resolution: resolution is not limited (corresponds to
7203 * ADC resolution configured).
7204 * - AWD flexible (instances AWD2, AWD3):
7205 * - channels monitored: flexible on channels monitored, selection is
7206 * channel wise, from from 1 to all channels.
7207 * Specificity of this analog watchdog: Multiple channels can
7208 * be selected. For example:
7209 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
7210 * - groups monitored: not selection possible (monitoring on both
7211 * groups regular and injected).
7212 * Channels selected are monitored on groups regular and injected:
7213 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
7214 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
7215 * - resolution: resolution is not limited (corresponds to
7216 * ADC resolution configured).
7217 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
7218 * impacted: the comparison of analog watchdog thresholds is done on
7219 * oversampling final computation (after ratio and shift application):
7220 * ADC data register bitfield [15:4] (12 most significant bits).
7221 * Examples:
7222 * - Oversampling ratio and shift selected to have ADC conversion data
7223 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
7224 * ADC analog watchdog thresholds must be divided by 16.
7225 * - Oversampling ratio and shift selected to have ADC conversion data
7226 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
7227 * ADC analog watchdog thresholds must be divided by 4.
7228 * - Oversampling ratio and shift selected to have ADC conversion data
7229 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
7230 * ADC analog watchdog thresholds match directly to ADC data register.
7231 * @note On this STM32 series, setting of this feature is conditioned to
7232 * ADC state:
7233 * ADC must be disabled or enabled without conversion on going
7234 * on group regular.
7235 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
7236 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
7237 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
7238 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
7239 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
7240 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
7241 * @param ADCx ADC instance
7242 * @param AWDy This parameter can be one of the following values:
7243 * @arg @ref LL_ADC_AWD1
7244 * @arg @ref LL_ADC_AWD2
7245 * @arg @ref LL_ADC_AWD3
7246 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
7247 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
7248 * @retval None
7249 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)7250 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
7251 uint32_t AWDThresholdLowValue)
7252 {
7253 __IO uint32_t *preg;
7254 __IO uint32_t *preg2;
7255 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
7256 /* position in register and register position depending on parameter */
7257 /* "AWDy". */
7258 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
7259 /* containing other bits reserved for other purpose. */
7260 if (ADCx != ADC4) /* ADC1 or ADC2 */
7261 {
7262 if (AWDy == LL_ADC_AWD1)
7263 {
7264 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (LL_ADC_AWD_THRESHOLD_LOW));
7265 preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (LL_ADC_AWD_THRESHOLD_HIGH));
7266 }
7267 else
7268 {
7269 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
7270 >> (ADC_AWD_TRX_REGOFFSET_POS - 1UL)))
7271 + (LL_ADC_AWD_THRESHOLD_LOW));
7272 preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
7273 >> (ADC_AWD_TRX_REGOFFSET_POS - 1UL)))
7274 + (LL_ADC_AWD_THRESHOLD_HIGH));
7275 }
7276
7277 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdLowValue);
7278 MODIFY_REG(*preg2, ADC_HTR_HT, AWDThresholdHighValue);
7279 }
7280 else
7281 {
7282 if (AWDy == LL_ADC_AWD1)
7283 {
7284 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
7285 }
7286 else
7287 {
7288 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS)) \
7289 + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
7290 }
7291
7292 MODIFY_REG(*preg,
7293 ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
7294 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
7295 }
7296 }
7297
7298 /**
7299 * @brief Set ADC analog watchdog filtering configuration
7300 * @note On this STM32 series, setting of this feature is conditioned to
7301 * ADC state:
7302 * ADC must be disabled or enabled without conversion on going
7303 * on either groups regular or injected.
7304 * @note On this STM32 series, this feature is only available on first
7305 * analog watchdog (AWD1)
7306 * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
7307 * @param ADCx ADC instance
7308 * @param AWDy This parameter can be one of the following values:
7309 * @arg @ref LL_ADC_AWD1
7310 * @param FilteringConfig This parameter can be one of the following values:
7311 * @arg @ref LL_ADC_AWD_FILTERING_NONE
7312 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
7313 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
7314 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
7315 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
7316 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
7317 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
7318 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
7319 * @retval None
7320 */
LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t FilteringConfig)7321 __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
7322 {
7323 /* Prevent unused argument(s) compilation warning */
7324 (void)(AWDy);
7325 MODIFY_REG(ADCx->HTR1, ADC_HTR_AWDFILT, FilteringConfig);
7326 }
7327
7328 /**
7329 * @brief Get ADC analog watchdog filtering configuration
7330 * @note On this STM32 series, this feature is only available on first
7331 * analog watchdog (AWD1)
7332 * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
7333 * @param ADCx ADC instance
7334 * @param AWDy This parameter can be one of the following values:
7335 * @arg @ref LL_ADC_AWD1
7336 * @retval Returned value can be:
7337 * @arg @ref LL_ADC_AWD_FILTERING_NONE
7338 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
7339 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
7340 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
7341 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
7342 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
7343 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
7344 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
7345 */
LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef * ADCx,uint32_t AWDy)7346 __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy)
7347 {
7348 /* Prevent unused argument(s) compilation warning */
7349 (void)(AWDy);
7350 return (uint32_t)(READ_BIT(ADCx->HTR1, ADC_HTR_AWDFILT));
7351 }
7352
7353 /**
7354 * @}
7355 */
7356
7357 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
7358 * @{
7359 */
7360
7361 /**
7362 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
7363 * (availability of ADC group injected depends on STM32 families).
7364 * @note If both groups regular and injected are selected,
7365 * specify behavior of ADC group injected interrupting
7366 * group regular: when ADC group injected is triggered,
7367 * the oversampling on ADC group regular is either
7368 * temporary stopped and continued, or resumed from start
7369 * (oversampler buffer reset).
7370 * @note On this STM32 series, setting of this feature is conditioned to
7371 * ADC state:
7372 * ADC must be disabled or enabled without conversion on going
7373 * on either groups regular or injected.
7374 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
7375 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
7376 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
7377 * @param ADCx ADC instance
7378 * @param OvsScope This parameter can be one of the following values:
7379 * @arg @ref LL_ADC_OVS_DISABLE
7380 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
7381 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
7382 * @arg @ref LL_ADC_OVS_GRP_INJECTED
7383 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
7384 * @retval None
7385 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)7386 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
7387 {
7388 if (ADCx != ADC4)
7389 {
7390 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
7391 }
7392 else
7393 {
7394 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE, OvsScope);
7395 }
7396 }
7397
7398 /**
7399 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
7400 * (availability of ADC group injected depends on STM32 families).
7401 * @note If both groups regular and injected are selected,
7402 * specify behavior of ADC group injected interrupting
7403 * group regular: when ADC group injected is triggered,
7404 * the oversampling on ADC group regular is either
7405 * temporary stopped and continued, or resumed from start
7406 * (oversampler buffer reset).
7407 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
7408 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
7409 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
7410 * @param ADCx ADC instance
7411 * @retval Returned value can be one of the following values:
7412 * @arg @ref LL_ADC_OVS_DISABLE
7413 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
7414 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
7415 * @arg @ref LL_ADC_OVS_GRP_INJECTED
7416 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
7417 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)7418 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
7419 {
7420 if (ADCx != ADC4)
7421 {
7422 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
7423 }
7424 else
7425 {
7426 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE));
7427 }
7428 }
7429
7430 /**
7431 * @brief Set ADC oversampling discontinuous mode (triggered mode)
7432 * on the selected ADC group.
7433 * @note Number of oversampled conversions are done either in:
7434 * - continuous mode (all conversions of oversampling ratio
7435 * are done from 1 trigger)
7436 * - discontinuous mode (each conversion of oversampling ratio
7437 * needs a trigger)
7438 * @note On this STM32 series, setting of this feature is conditioned to
7439 * ADC state:
7440 * ADC must be disabled or enabled without conversion on going
7441 * on group regular.
7442 * @note On this STM32 series, oversampling discontinuous mode
7443 * (triggered mode) can be used only when oversampling is
7444 * set on group regular only and in resumed mode.
7445 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
7446 * @param ADCx ADC instance
7447 * @param OverSamplingDiscont This parameter can be one of the following values:
7448 * @arg @ref LL_ADC_OVS_REG_CONT
7449 * @arg @ref LL_ADC_OVS_REG_DISCONT
7450 * @retval None
7451 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)7452 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
7453 {
7454 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
7455 }
7456
7457 /**
7458 * @brief Get ADC oversampling discontinuous mode (triggered mode)
7459 * on the selected ADC group.
7460 * @note Number of oversampled conversions are done either in:
7461 * - continuous mode (all conversions of oversampling ratio
7462 * are done from 1 trigger)
7463 * - discontinuous mode (each conversion of oversampling ratio
7464 * needs a trigger)
7465 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
7466 * @param ADCx ADC instance
7467 * @retval Returned value can be one of the following values:
7468 * @arg @ref LL_ADC_OVS_REG_CONT
7469 * @arg @ref LL_ADC_OVS_REG_DISCONT
7470 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)7471 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
7472 {
7473 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
7474 }
7475
7476 /**
7477 * @brief Set ADC oversampling
7478 * (impacting both ADC groups regular and injected)
7479 * @note This function set the 2 items of oversampling configuration:
7480 * - ratio
7481 * - shift
7482 * @note On this STM32 series, setting of this feature is conditioned to
7483 * ADC state:
7484 * ADC must be disabled or enabled without conversion on going
7485 * on either groups regular or injected.
7486 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
7487 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
7488 * @param ADCx ADC instance
7489 * @param Ratio For ADC instance ADC1, ADC2: This parameter can be in the range from 1 to 1024.
7490 * For ADC instance ADC4: This parameter can be one of the following values:
7491 * @arg @ref LL_ADC_OVS_RATIO_2
7492 * @arg @ref LL_ADC_OVS_RATIO_4
7493 * @arg @ref LL_ADC_OVS_RATIO_8
7494 * @arg @ref LL_ADC_OVS_RATIO_16
7495 * @arg @ref LL_ADC_OVS_RATIO_32
7496 * @arg @ref LL_ADC_OVS_RATIO_64
7497 * @arg @ref LL_ADC_OVS_RATIO_128
7498 * @arg @ref LL_ADC_OVS_RATIO_256
7499 * @param Shift This parameter can be one of the following values:
7500 * @arg @ref LL_ADC_OVS_SHIFT_NONE
7501 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
7502 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
7503 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
7504 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
7505 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
7506 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
7507 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
7508 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
7509 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9 (1)
7510 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 (1)
7511 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 (1)
7512 *
7513 * (1): Only for ADC1 instance.
7514 * @retval None
7515 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)7516 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
7517 {
7518 if (ADCx != ADC4)
7519 {
7520 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
7521 }
7522 else /* ADCx == ADC4 */
7523 {
7524 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC4_CFGR2_OVSR),
7525 (Shift | (Ratio & ~ADC4_OVERSAMPLING_RATIO_PARAMETER_MASK)));
7526 }
7527 }
7528
7529 /**
7530 * @brief Get ADC oversampling ratio
7531 * (impacting both ADC groups regular and injected)
7532 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
7533 * @param ADCx ADC instance
7534 * @retval Ratio This parameter can be a value from 1 to 1024 in the case of ADC1/2,
7535 * In the case of ADC4 can be one of the following values:
7536 * @arg @ref LL_ADC_OVS_RATIO_2
7537 * @arg @ref LL_ADC_OVS_RATIO_4
7538 * @arg @ref LL_ADC_OVS_RATIO_8
7539 * @arg @ref LL_ADC_OVS_RATIO_16
7540 * @arg @ref LL_ADC_OVS_RATIO_32
7541 * @arg @ref LL_ADC_OVS_RATIO_64
7542 * @arg @ref LL_ADC_OVS_RATIO_128
7543 * @arg @ref LL_ADC_OVS_RATIO_256
7544 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)7545 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
7546 {
7547 if (ADCx != ADC4)
7548 {
7549 return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
7550 }
7551 else /* ADCx == ADC4 */
7552 {
7553 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_OVSR) | ADC4_OVERSAMPLING_RATIO_PARAMETER);
7554 }
7555 }
7556
7557 /**
7558 * @brief Get ADC oversampling shift
7559 * (impacting both ADC groups regular and injected)
7560 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
7561 * @param ADCx ADC instance
7562 * @retval Shift This parameter can be one of the following values:
7563 * @arg @ref LL_ADC_OVS_SHIFT_NONE
7564 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
7565 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
7566 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
7567 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
7568 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
7569 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
7570 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
7571 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
7572 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9 (1)
7573 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 (1)
7574 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 (1)
7575 *
7576 * (1): Only for ADC1 instance.
7577 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)7578 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
7579 {
7580 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
7581 }
7582
7583 #if defined(ADC_MULTIMODE_SUPPORT)
7584 /**
7585 * @brief Set ADC multimode configuration to operate in independent mode
7586 * or multimode (for devices with several ADC instances).
7587 * @note If multimode configuration: the selected ADC instance is
7588 * either master or slave depending on hardware.
7589 * Refer to reference manual.
7590 * @note On this STM32 series, setting of this feature is conditioned to
7591 * ADC state:
7592 * All ADC instances of the ADC common group must be disabled.
7593 * This check can be done with function @ref LL_ADC_IsEnabled() for each
7594 * ADC instance or by using helper macro
7595 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
7596 * @rmtoll CCR DUAL LL_ADC_SetMultimode
7597 * @param ADCxy_COMMON ADC common instance
7598 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7599 * @param Multimode This parameter can be one of the following values:
7600 * @arg @ref LL_ADC_MULTI_INDEPENDENT
7601 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
7602 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
7603 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
7604 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
7605 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
7606 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
7607 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
7608 * @retval None
7609 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)7610 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
7611 {
7612 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
7613 }
7614
7615 /**
7616 * @brief Get ADC multimode configuration to operate in independent mode
7617 * or multimode (for devices with several ADC instances).
7618 * @note If multimode configuration: the selected ADC instance is
7619 * either master or slave depending on hardware.
7620 * Refer to reference manual.
7621 * @rmtoll CCR DUAL LL_ADC_GetMultimode
7622 * @param ADCxy_COMMON ADC common instance
7623 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7624 * @retval Returned value can be one of the following values:
7625 * @arg @ref LL_ADC_MULTI_INDEPENDENT
7626 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
7627 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
7628 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
7629 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
7630 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
7631 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
7632 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
7633 */
LL_ADC_GetMultimode(const ADC_Common_TypeDef * ADCxy_COMMON)7634 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
7635 {
7636 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
7637 }
7638
7639 /**
7640 * @brief Set ADC multimode conversion data transfer: no transfer
7641 * or transfer by DMA.
7642 * @note If ADC multimode transfer by DMA is not selected:
7643 * each ADC uses its own DMA channel, with its individual
7644 * DMA transfer settings.
7645 * If ADC multimode transfer by DMA is selected:
7646 * One DMA channel is used for both ADC (DMA of ADC master)
7647 * Specifies the DMA requests mode:
7648 * - Limited mode (One shot mode): DMA transfer requests are stopped
7649 * when number of DMA data transfers (number of
7650 * ADC conversions) is reached.
7651 * This ADC mode is intended to be used with DMA mode non-circular.
7652 * - Unlimited mode: DMA transfer requests are unlimited,
7653 * whatever number of DMA data transfers (number of
7654 * ADC conversions).
7655 * This ADC mode is intended to be used with DMA mode circular.
7656 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
7657 * mode non-circular:
7658 * when DMA transfers size will be reached, DMA will stop transfers of
7659 * ADC conversions data ADC will raise an overrun error
7660 * (overrun flag and interruption if enabled).
7661 * @note How to retrieve multimode conversion data:
7662 * Whatever multimode transfer by DMA setting: using function
7663 * @ref LL_ADC_REG_ReadMultiConversionData32().
7664 * If ADC multimode transfer by DMA is selected: conversion data
7665 * is a raw data with ADC master and slave concatenated.
7666 * A macro is available to get the conversion data of
7667 * ADC master or ADC slave: see helper macro
7668 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
7669 * @note On this STM32 series, setting of this feature is conditioned to
7670 * ADC state:
7671 * All ADC instances of the ADC common group must be disabled
7672 * or enabled without conversion on going on group regular.
7673 * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
7674 * @param ADCxy_COMMON ADC common instance
7675 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7676 * @param MultiDMATransfer This parameter can be one of the following values:
7677 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
7678 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
7679 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
7680 * @retval None
7681 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)7682 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
7683 {
7684 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);
7685 }
7686
7687 /**
7688 * @brief Get ADC multimode conversion data transfer: no transfer
7689 * or transfer by DMA.
7690 * @note If ADC multimode transfer by DMA is not selected:
7691 * each ADC uses its own DMA channel, with its individual
7692 * DMA transfer settings.
7693 * If ADC multimode transfer by DMA is selected:
7694 * One DMA channel is used for both ADC (DMA of ADC master)
7695 * Specifies the DMA requests mode:
7696 * - Limited mode (One shot mode): DMA transfer requests are stopped
7697 * when number of DMA data transfers (number of
7698 * ADC conversions) is reached.
7699 * This ADC mode is intended to be used with DMA mode non-circular.
7700 * - Unlimited mode: DMA transfer requests are unlimited,
7701 * whatever number of DMA data transfers (number of
7702 * ADC conversions).
7703 * This ADC mode is intended to be used with DMA mode circular.
7704 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
7705 * mode non-circular:
7706 * when DMA transfers size will be reached, DMA will stop transfers of
7707 * ADC conversions data ADC will raise an overrun error
7708 * (overrun flag and interruption if enabled).
7709 * @note How to retrieve multimode conversion data:
7710 * Whatever multimode transfer by DMA setting: using function
7711 * @ref LL_ADC_REG_ReadMultiConversionData32().
7712 * If ADC multimode transfer by DMA is selected: conversion data
7713 * is a raw data with ADC master and slave concatenated.
7714 * A macro is available to get the conversion data of
7715 * ADC master or ADC slave: see helper macro
7716 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
7717 * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
7718 * @param ADCxy_COMMON ADC common instance
7719 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7720 * @retval Returned value can be one of the following values:
7721 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
7722 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
7723 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
7724 */
LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef * ADCxy_COMMON)7725 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
7726 {
7727 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
7728 }
7729
7730 /**
7731 * @brief Set ADC multimode delay between 2 sampling phases.
7732 * @note The sampling delay range depends on ADC resolution:
7733 * - ADC resolution 14 bits can have maximum delay of 16 cycles.
7734 * - ADC resolution 12 bits can have maximum delay of 16 cycles.
7735 * - ADC resolution 10 bits can have maximum delay of 15 cycles.
7736 * - ADC resolution 8 bits can have maximum delay of 13 cycles.
7737 * @note On this STM32 series, setting of this feature is conditioned to
7738 * ADC state:
7739 * All ADC instances of the ADC common group must be disabled.
7740 * This check can be done with function @ref LL_ADC_IsEnabled() for each
7741 * ADC instance or by using helper macro helper macro
7742 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
7743 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
7744 * @param ADCxy_COMMON ADC common instance
7745 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7746 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
7747 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
7748 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
7749 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
7750 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
7751 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
7752 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
7753 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
7754 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
7755 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
7756 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
7757 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
7758 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
7759 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
7760 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS
7761 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (1)
7762 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (1)
7763 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS
7764 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (2)
7765 *
7766 * (1) Parameter available only if ADC resolution is 14, 12 or 10 bits.
7767 * (2) Parameter available only if ADC resolution is 14 or 12 bits.
7768 * @retval None
7769 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)7770 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
7771 {
7772 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
7773 }
7774
7775 /**
7776 * @brief Get ADC multimode delay between 2 sampling phases.
7777 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
7778 * @param ADCxy_COMMON ADC common instance
7779 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7780 * @retval Returned value can be one of the following values:
7781 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
7782 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
7783 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
7784 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
7785 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
7786 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
7787 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
7788 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
7789 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
7790 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
7791 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
7792 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
7793 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
7794 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS
7795 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (1)
7796 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (1)
7797 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS
7798 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (2)
7799 *
7800 * (1) Parameter available only if ADC resolution is 14, 12 or 10 bits.
7801 * (2) Parameter available only if ADC resolution is 14 or 12 bits.
7802 */
LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef * ADCxy_COMMON)7803 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
7804 {
7805 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
7806 }
7807
7808 #endif /* ADC_MULTIMODE_SUPPORT */
7809
7810 /**
7811 * @}
7812 */
7813 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
7814 * @{
7815 */
7816
7817 /**
7818 * @brief Put ADC instance in deep power down state.
7819 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
7820 * state, the internal analog calibration is lost. After exiting from
7821 * deep power down, calibration must be relaunched or calibration factor
7822 * (preliminarily saved) must be set back into calibration register.
7823 * @note On this STM32 series, setting of this feature is conditioned to
7824 * ADC state:
7825 * ADC must be ADC disabled.
7826 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
7827 * @param ADCx ADC instance
7828 * @retval None
7829 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)7830 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
7831 {
7832 /* Note: Write register with some additional bits forced to state reset */
7833 /* instead of modifying only the selected bit for this function, */
7834 /* to not interfere with bits with HW property "rs". */
7835 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_DEEPPWD);
7836 }
7837
7838 /**
7839 * @brief Disable ADC deep power down mode.
7840 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
7841 * state, the internal analog calibration is lost. After exiting from
7842 * deep power down, calibration must be relaunched or calibration factor
7843 * (preliminarily saved) must be set back into calibration register.
7844 * @note On this STM32 series, setting of this feature is conditioned to
7845 * ADC state:
7846 * ADC must be ADC disabled.
7847 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
7848 * @param ADCx ADC instance
7849 * @retval None
7850 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)7851 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
7852 {
7853 /* Note: Write register with some additional bits forced to state reset */
7854 /* instead of modifying only the selected bit for this function, */
7855 /* to not interfere with bits with HW property "rs". */
7856 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
7857 }
7858
7859 /**
7860 * @brief Get the selected ADC instance deep power down state.
7861 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
7862 * @param ADCx ADC instance
7863 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
7864 */
LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef * ADCx)7865 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
7866 {
7867 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
7868 }
7869
7870 /**
7871 * @brief Enable ADC instance internal voltage regulator.
7872 * @note On this STM32 series, after ADC internal voltage regulator enable,
7873 * a delay for ADC internal voltage regulator stabilization
7874 * is required before performing a ADC calibration or ADC enable.
7875 * Refer to device datasheet, parameter tADCVREG_STUP.
7876 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
7877 * @note On this STM32 series, setting of this feature is conditioned to
7878 * ADC state:
7879 * ADC must be ADC disabled.
7880 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
7881 * @param ADCx ADC instance
7882 * @retval None
7883 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)7884 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
7885 {
7886 /* Note: Write register with some additional bits forced to state reset */
7887 /* instead of modifying only the selected bit for this function, */
7888 /* to not interfere with bits with HW property "rs". */
7889 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN);
7890 }
7891
7892 /**
7893 * @brief Disable ADC internal voltage regulator.
7894 * @note On this STM32 series, setting of this feature is conditioned to
7895 * ADC state:
7896 * ADC must be ADC disabled.
7897 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
7898 * @param ADCx ADC instance
7899 * @retval None
7900 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)7901 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
7902 {
7903 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
7904 }
7905
7906 /**
7907 * @brief Get the selected ADC instance internal voltage regulator state.
7908 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
7909 * @param ADCx ADC instance
7910 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
7911 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)7912 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
7913 {
7914 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
7915 }
7916
7917 /**
7918 * @brief Enable the selected ADC instance.
7919 * @note On this STM32 series, after ADC enable, a delay for
7920 * ADC internal analog stabilization is required before performing a
7921 * ADC conversion start.
7922 * Refer to device datasheet, parameter tSTAB.
7923 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7924 * is enabled and when conversion clock is active.
7925 * (not only core clock: this ADC has a dual clock domain)
7926 * @note On this STM32 series, setting of this feature is conditioned to
7927 * ADC state:
7928 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
7929 * @rmtoll CR ADEN LL_ADC_Enable
7930 * @param ADCx ADC instance
7931 * @retval None
7932 */
LL_ADC_Enable(ADC_TypeDef * ADCx)7933 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
7934 {
7935 /* Note: Write register with some additional bits forced to state reset */
7936 /* instead of modifying only the selected bit for this function, */
7937 /* to not interfere with bits with HW property "rs". */
7938 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN);
7939 }
7940
7941 /**
7942 * @brief Disable the selected ADC instance.
7943 * @note On this STM32 series, setting of this feature is conditioned to
7944 * ADC state:
7945 * ADC must be not disabled. Must be enabled without conversion on going
7946 * on either groups regular or injected.
7947 * @rmtoll CR ADDIS LL_ADC_Disable
7948 * @param ADCx ADC instance
7949 * @retval None
7950 */
LL_ADC_Disable(ADC_TypeDef * ADCx)7951 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
7952 {
7953 /* Note: Write register with some additional bits forced to state reset */
7954 /* instead of modifying only the selected bit for this function, */
7955 /* to not interfere with bits with HW property "rs". */
7956 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS);
7957 }
7958
7959 /**
7960 * @brief Get the selected ADC instance enable state.
7961 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7962 * is enabled and when conversion clock is active.
7963 * (not only core clock: this ADC has a dual clock domain)
7964 * @rmtoll CR ADEN LL_ADC_IsEnabled
7965 * @param ADCx ADC instance
7966 * @retval 0: ADC is disabled, 1: ADC is enabled.
7967 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)7968 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
7969 {
7970 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
7971 }
7972
7973 /**
7974 * @brief Get the selected ADC instance disable state.
7975 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
7976 * @param ADCx ADC instance
7977 * @retval 0: no ADC disable command on going.
7978 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)7979 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
7980 {
7981 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
7982 }
7983
7984 /**
7985 * @brief Start ADC calibration in the mode single-ended
7986 * or differential (for devices with differential mode available).
7987 * @note On this STM32 series, a minimum number of ADC clock cycles
7988 * are required between ADC end of calibration and ADC enable.
7989 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
7990 * @note Calibration duration:
7991 * - Calibration of offset: 520 ADC clock cycles
7992 * - Calibration of linearity: 131072 ADC clock cycles
7993 * @note For devices with differential mode available:
7994 * Calibration of offset is specific to each of
7995 * single-ended and differential modes
7996 * (calibration run must be performed for each of these
7997 * differential modes, if used afterwards and if the application
7998 * requires their calibration).
7999 * Calibration of linearity is common to both
8000 * single-ended and differential modes
8001 * (calibration run can be performed only once).
8002 * @note On this STM32 series, setting of this feature is conditioned to
8003 * ADC state:
8004 * ADC must be ADC disabled.
8005 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
8006 * CR ADCALDIF LL_ADC_StartCalibration\n
8007 * CR ADCALLIN LL_ADC_StartCalibration
8008 * @param ADCx ADC instance
8009 * @param CalibrationMode This parameter can be one of the following values:
8010 * @arg @ref LL_ADC_CALIB_OFFSET
8011 * @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY
8012 * @retval None
8013 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t CalibrationMode)8014 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode)
8015 {
8016 /* Note: Write register with some additional bits forced to state reset */
8017 /* instead of modifying only the selected bit for this function, */
8018 /* to not interfere with bits with HW property "rs". */
8019 if (ADCx != ADC4) /* ADC1 or ADC2 */
8020 {
8021 MODIFY_REG(ADCx->CR,
8022 ADC_CR_ADCALLIN | ADC_CR_BITS_PROPERTY_RS,
8023 ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK));
8024 }
8025 else
8026 {
8027 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCAL);
8028 }
8029 }
8030
8031 /**
8032 * @brief Get ADC calibration state.
8033 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
8034 * @param ADCx ADC instance
8035 * @retval 0: calibration complete, 1: calibration in progress.
8036 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)8037 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
8038 {
8039 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
8040 }
8041
8042 /**
8043 * @}
8044 */
8045
8046 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
8047 * @{
8048 */
8049
8050 /**
8051 * @brief Start ADC group regular conversion.
8052 * @note On this STM32 series, this function is relevant for both
8053 * internal trigger (SW start) and external trigger:
8054 * - If ADC trigger has been set to software start, ADC conversion
8055 * starts immediately.
8056 * - If ADC trigger has been set to external trigger, ADC conversion
8057 * will start at next trigger event (on the selected trigger edge)
8058 * following the ADC start conversion command.
8059 * @note On this STM32 series, setting of this feature is conditioned to
8060 * ADC state:
8061 * ADC must be enabled without conversion on going on group regular,
8062 * without conversion stop command on going on group regular,
8063 * without ADC disable command on going.
8064 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
8065 * @param ADCx ADC instance
8066 * @retval None
8067 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)8068 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
8069 {
8070 /* Note: Write register with some additional bits forced to state reset */
8071 /* instead of modifying only the selected bit for this function, */
8072 /* to not interfere with bits with HW property "rs". */
8073 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART);
8074 }
8075
8076 /**
8077 * @brief Stop ADC group regular conversion.
8078 * @note On this STM32 series, setting of this feature is conditioned to
8079 * ADC state:
8080 * ADC must be enabled with conversion on going on group regular,
8081 * without ADC disable command on going.
8082 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
8083 * @param ADCx ADC instance
8084 * @retval None
8085 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)8086 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
8087 {
8088 /* Note: Write register with some additional bits forced to state reset */
8089 /* instead of modifying only the selected bit for this function, */
8090 /* to not interfere with bits with HW property "rs". */
8091 MODIFY_REG(ADCx->CR,
8092 ADC_CR_BITS_PROPERTY_RS,
8093 ADC_CR_ADSTP);
8094 }
8095
8096 /**
8097 * @brief Get ADC group regular conversion state.
8098 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
8099 * @param ADCx ADC instance
8100 * @retval 0: no conversion is on going on ADC group regular.
8101 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)8102 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
8103 {
8104 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8105 }
8106
8107 /**
8108 * @brief Get ADC group regular command of conversion stop state
8109 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
8110 * @param ADCx ADC instance
8111 * @retval 0: no command of conversion stop is on going on ADC group regular.
8112 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)8113 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
8114 {
8115 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
8116 }
8117
8118 /**
8119 * @brief Get ADC group regular conversion data, range fit for
8120 * all ADC configurations: all ADC resolutions and
8121 * all oversampling increased data width (for devices
8122 * with feature oversampling).
8123 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
8124 * @param ADCx ADC instance
8125 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
8126 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)8127 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
8128 {
8129 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8130 }
8131
8132 /**
8133 * @brief Get ADC group regular conversion data, range fit for
8134 * ADC resolution 16 bits.
8135 * @note For devices with feature oversampling: Oversampling
8136 * can increase data width, function for extended range
8137 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
8138 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData16
8139 * @param ADCx ADC instance
8140 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
8141 */
LL_ADC_REG_ReadConversionData16(const ADC_TypeDef * ADCx)8142 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(const ADC_TypeDef *ADCx)
8143 {
8144 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8145 }
8146
8147 /**
8148 * @brief Get ADC group regular conversion data, range fit for
8149 * ADC resolution 14 bits.
8150 * @note For devices with feature oversampling: Oversampling
8151 * can increase data width, function for extended range
8152 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
8153 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData14
8154 * @param ADCx ADC instance
8155 * @retval Value between Min_Data=0x00 and Max_Data=0x3FF
8156 */
LL_ADC_REG_ReadConversionData14(const ADC_TypeDef * ADCx)8157 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(const ADC_TypeDef *ADCx)
8158 {
8159 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8160 }
8161
8162 /**
8163 * @brief Get ADC group regular conversion data, range fit for
8164 * ADC resolution 12 bits.
8165 * @note For devices with feature oversampling: Oversampling
8166 * can increase data width, function for extended range
8167 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
8168 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
8169 * @param ADCx ADC instance
8170 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
8171 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)8172 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
8173 {
8174 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8175 }
8176
8177 /**
8178 * @brief Get ADC group regular conversion data, range fit for
8179 * ADC resolution 10 bits.
8180 * @note For devices with feature oversampling: Oversampling
8181 * can increase data width, function for extended range
8182 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
8183 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
8184 * @param ADCx ADC instance
8185 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
8186 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)8187 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
8188 {
8189 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8190 }
8191
8192 /**
8193 * @brief Get ADC group regular conversion data, range fit for
8194 * ADC resolution 8 bits.
8195 * @note For devices with feature oversampling: Oversampling
8196 * can increase data width, function for extended range
8197 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
8198 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
8199 * @param ADCx ADC instance
8200 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
8201 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)8202 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
8203 {
8204 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8205 }
8206
8207 #if defined(ADC_MULTIMODE_SUPPORT)
8208 /**
8209 * @brief Get ADC multimode conversion data of ADC master, ADC slave
8210 * or raw data with ADC master and slave concatenated.
8211 * @note If raw data with ADC master and slave concatenated is retrieved,
8212 * a macro is available to get the conversion data of
8213 * ADC master or ADC slave: see helper macro
8214 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
8215 * (however this macro is mainly intended for multimode
8216 * transfer by DMA, because this function can do the same
8217 * by getting multimode conversion data of ADC master or ADC slave
8218 * separately).
8219 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
8220 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
8221 * @param ADCxy_COMMON ADC common instance
8222 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8223 * @param ConversionData This parameter can be one of the following values:
8224 * @arg @ref LL_ADC_MULTI_MASTER
8225 * @arg @ref LL_ADC_MULTI_SLAVE
8226 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
8227 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
8228 */
LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)8229 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON,
8230 uint32_t ConversionData)
8231 {
8232 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) >> (POSITION_VAL(ConversionData) & 0x1FUL));
8233 }
8234 #endif /* ADC_MULTIMODE_SUPPORT */
8235 /**
8236 * @}
8237 */
8238
8239 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
8240 * @{
8241 */
8242
8243 /**
8244 * @brief Start ADC group injected conversion.
8245 * @note On this STM32 series, this function is relevant for both
8246 * internal trigger (SW start) and external trigger:
8247 * - If ADC trigger has been set to software start, ADC conversion
8248 * starts immediately.
8249 * - If ADC trigger has been set to external trigger, ADC conversion
8250 * will start at next trigger event (on the selected trigger edge)
8251 * following the ADC start conversion command.
8252 * @note On this STM32 series, setting of this feature is conditioned to
8253 * ADC state:
8254 * ADC must be enabled without conversion on going on group injected,
8255 * without conversion stop command on going on group injected,
8256 * without ADC disable command on going.
8257 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
8258 * @param ADCx ADC instance
8259 * @retval None
8260 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)8261 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
8262 {
8263 /* Note: Write register with some additional bits forced to state reset */
8264 /* instead of modifying only the selected bit for this function, */
8265 /* to not interfere with bits with HW property "rs". */
8266 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTART);
8267 }
8268
8269 /**
8270 * @brief Stop ADC group injected conversion.
8271 * @note On this STM32 series, setting of this feature is conditioned to
8272 * ADC state:
8273 * ADC must be enabled with conversion on going on group injected,
8274 * without ADC disable command on going.
8275 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
8276 * @param ADCx ADC instance
8277 * @retval None
8278 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)8279 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
8280 {
8281 /* Note: Write register with some additional bits forced to state reset */
8282 /* instead of modifying only the selected bit for this function, */
8283 /* to not interfere with bits with HW property "rs". */
8284 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTP);
8285 }
8286
8287 /**
8288 * @brief Get ADC group injected conversion state.
8289 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
8290 * @param ADCx ADC instance
8291 * @retval 0: no conversion is on going on ADC group injected.
8292 */
LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef * ADCx)8293 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
8294 {
8295 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
8296 }
8297
8298 /**
8299 * @brief Get ADC group injected command of conversion stop state
8300 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
8301 * @param ADCx ADC instance
8302 * @retval 0: no command of conversion stop is on going on ADC group injected.
8303 */
LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef * ADCx)8304 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
8305 {
8306 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
8307 }
8308
8309 /**
8310 * @brief Get ADC group regular conversion data, range fit for
8311 * all ADC configurations: all ADC resolutions and
8312 * all oversampling increased data width (for devices
8313 * with feature oversampling).
8314 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
8315 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
8316 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
8317 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
8318 * @param ADCx ADC instance
8319 * @param Rank This parameter can be one of the following values:
8320 * @arg @ref LL_ADC_INJ_RANK_1
8321 * @arg @ref LL_ADC_INJ_RANK_2
8322 * @arg @ref LL_ADC_INJ_RANK_3
8323 * @arg @ref LL_ADC_INJ_RANK_4
8324 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
8325 */
LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef * ADCx,uint32_t Rank)8326 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
8327 {
8328 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8329 >> ADC_JDRX_REGOFFSET_POS));
8330
8331 return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8332 }
8333
8334 /**
8335 * @brief Get ADC group injected conversion data, range fit for
8336 * ADC resolution 16 bits.
8337 * @note For devices with feature oversampling: Oversampling
8338 * can increase data width, function for extended range
8339 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8340 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16\n
8341 * JDR2 JDATA LL_ADC_INJ_ReadConversionData16\n
8342 * JDR3 JDATA LL_ADC_INJ_ReadConversionData16\n
8343 * JDR4 JDATA LL_ADC_INJ_ReadConversionData16
8344 * @param ADCx ADC instance
8345 * @param Rank This parameter can be one of the following values:
8346 * @arg @ref LL_ADC_INJ_RANK_1
8347 * @arg @ref LL_ADC_INJ_RANK_2
8348 * @arg @ref LL_ADC_INJ_RANK_3
8349 * @arg @ref LL_ADC_INJ_RANK_4
8350 * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF
8351 */
LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef * ADCx,uint32_t Rank)8352 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef *ADCx, uint32_t Rank)
8353 {
8354 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8355 >> ADC_JDRX_REGOFFSET_POS));
8356
8357 return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8358 }
8359
8360 /**
8361 * @brief Get ADC group injected conversion data, range fit for
8362 * ADC resolution 14 bits.
8363 * @note For devices with feature oversampling: Oversampling
8364 * can increase data width, function for extended range
8365 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8366 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14\n
8367 * JDR2 JDATA LL_ADC_INJ_ReadConversionData14\n
8368 * JDR3 JDATA LL_ADC_INJ_ReadConversionData14\n
8369 * JDR4 JDATA LL_ADC_INJ_ReadConversionData14
8370 * @param ADCx ADC instance
8371 * @param Rank This parameter can be one of the following values:
8372 * @arg @ref LL_ADC_INJ_RANK_1
8373 * @arg @ref LL_ADC_INJ_RANK_2
8374 * @arg @ref LL_ADC_INJ_RANK_3
8375 * @arg @ref LL_ADC_INJ_RANK_4
8376 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF
8377 */
LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef * ADCx,uint32_t Rank)8378 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef *ADCx, uint32_t Rank)
8379 {
8380 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8381 >> ADC_JDRX_REGOFFSET_POS));
8382
8383 return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8384 }
8385
8386 /**
8387 * @brief Get ADC group injected conversion data, range fit for
8388 * ADC resolution 12 bits.
8389 * @note For devices with feature oversampling: Oversampling
8390 * can increase data width, function for extended range
8391 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8392 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
8393 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
8394 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
8395 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
8396 * @param ADCx ADC instance
8397 * @param Rank This parameter can be one of the following values:
8398 * @arg @ref LL_ADC_INJ_RANK_1
8399 * @arg @ref LL_ADC_INJ_RANK_2
8400 * @arg @ref LL_ADC_INJ_RANK_3
8401 * @arg @ref LL_ADC_INJ_RANK_4
8402 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
8403 */
LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef * ADCx,uint32_t Rank)8404 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
8405 {
8406 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8407 >> ADC_JDRX_REGOFFSET_POS));
8408
8409 return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8410 }
8411
8412 /**
8413 * @brief Get ADC group injected conversion data, range fit for
8414 * ADC resolution 10 bits.
8415 * @note For devices with feature oversampling: Oversampling
8416 * can increase data width, function for extended range
8417 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8418 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
8419 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
8420 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
8421 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
8422 * @param ADCx ADC instance
8423 * @param Rank This parameter can be one of the following values:
8424 * @arg @ref LL_ADC_INJ_RANK_1
8425 * @arg @ref LL_ADC_INJ_RANK_2
8426 * @arg @ref LL_ADC_INJ_RANK_3
8427 * @arg @ref LL_ADC_INJ_RANK_4
8428 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
8429 */
LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef * ADCx,uint32_t Rank)8430 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
8431 {
8432 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8433 >> ADC_JDRX_REGOFFSET_POS));
8434
8435 return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8436 }
8437
8438 /**
8439 * @brief Get ADC group injected conversion data, range fit for
8440 * ADC resolution 8 bits.
8441 * @note For devices with feature oversampling: Oversampling
8442 * can increase data width, function for extended range
8443 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8444 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
8445 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
8446 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
8447 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
8448 * @param ADCx ADC instance
8449 * @param Rank This parameter can be one of the following values:
8450 * @arg @ref LL_ADC_INJ_RANK_1
8451 * @arg @ref LL_ADC_INJ_RANK_2
8452 * @arg @ref LL_ADC_INJ_RANK_3
8453 * @arg @ref LL_ADC_INJ_RANK_4
8454 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
8455 */
LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef * ADCx,uint32_t Rank)8456 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
8457 {
8458 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8459 >> ADC_JDRX_REGOFFSET_POS));
8460
8461 return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8462 }
8463
8464 /**
8465 * @}
8466 */
8467
8468 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
8469 * @{
8470 */
8471
8472 /**
8473 * @brief Get flag ADC ready.
8474 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
8475 * is enabled and when conversion clock is active.
8476 * (not only core clock: this ADC has a dual clock domain)
8477 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
8478 * @param ADCx ADC instance
8479 * @retval State of bit (1 or 0).
8480 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)8481 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
8482 {
8483 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
8484 }
8485
8486 /**
8487 * @brief Get flag ADC group regular end of unitary conversion.
8488 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
8489 * @param ADCx ADC instance
8490 * @retval State of bit (1 or 0).
8491 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)8492 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
8493 {
8494 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
8495 }
8496
8497 /**
8498 * @brief Get flag ADC group regular end of sequence conversions.
8499 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
8500 * @param ADCx ADC instance
8501 * @retval State of bit (1 or 0).
8502 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)8503 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
8504 {
8505 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
8506 }
8507
8508 /**
8509 * @brief Get flag ADC group regular overrun.
8510 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
8511 * @param ADCx ADC instance
8512 * @retval State of bit (1 or 0).
8513 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)8514 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
8515 {
8516 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
8517 }
8518
8519 /**
8520 * @brief Get flag ADC group regular end of sampling phase.
8521 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
8522 * @param ADCx ADC instance
8523 * @retval State of bit (1 or 0).
8524 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)8525 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
8526 {
8527 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
8528 }
8529
8530 /**
8531 * @brief Get flag ADC group injected end of unitary conversion.
8532 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
8533 * @param ADCx ADC instance
8534 * @retval State of bit (1 or 0).
8535 */
LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef * ADCx)8536 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
8537 {
8538 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
8539 }
8540
8541 /**
8542 * @brief Get flag ADC group injected end of sequence conversions.
8543 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
8544 * @param ADCx ADC instance
8545 * @retval State of bit (1 or 0).
8546 */
LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef * ADCx)8547 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
8548 {
8549 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
8550 }
8551
8552 /**
8553 * @brief Get flag ADC analog watchdog 1 flag
8554 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
8555 * @param ADCx ADC instance
8556 * @retval State of bit (1 or 0).
8557 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)8558 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
8559 {
8560 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
8561 }
8562
8563 /**
8564 * @brief Get flag ADC analog watchdog 2.
8565 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
8566 * @param ADCx ADC instance
8567 * @retval State of bit (1 or 0).
8568 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)8569 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
8570 {
8571 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
8572 }
8573
8574 /**
8575 * @brief Get flag ADC analog watchdog 3.
8576 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
8577 * @param ADCx ADC instance
8578 * @retval State of bit (1 or 0).
8579 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)8580 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
8581 {
8582 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
8583 }
8584
8585 /**
8586 * @brief Clear flag ADC ready.
8587 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
8588 * is enabled and when conversion clock is active.
8589 * (not only core clock: this ADC has a dual clock domain)
8590 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
8591 * @param ADCx ADC instance
8592 * @retval None
8593 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)8594 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
8595 {
8596 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
8597 }
8598
8599 /**
8600 * @brief Clear flag ADC group regular end of unitary conversion.
8601 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
8602 * @param ADCx ADC instance
8603 * @retval None
8604 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)8605 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
8606 {
8607 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
8608 }
8609
8610 /**
8611 * @brief Clear flag ADC group regular end of sequence conversions.
8612 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
8613 * @param ADCx ADC instance
8614 * @retval None
8615 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)8616 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
8617 {
8618 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
8619 }
8620
8621 /**
8622 * @brief Clear flag ADC group regular overrun.
8623 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
8624 * @param ADCx ADC instance
8625 * @retval None
8626 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)8627 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
8628 {
8629 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
8630 }
8631
8632 /**
8633 * @brief Clear flag ADC group regular end of sampling phase.
8634 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
8635 * @param ADCx ADC instance
8636 * @retval None
8637 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)8638 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
8639 {
8640 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
8641 }
8642
8643 /**
8644 * @brief Clear flag ADC group injected end of unitary conversion.
8645 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
8646 * @param ADCx ADC instance
8647 * @retval None
8648 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)8649 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
8650 {
8651 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
8652 }
8653
8654 /**
8655 * @brief Clear flag ADC group injected end of sequence conversions.
8656 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
8657 * @param ADCx ADC instance
8658 * @retval None
8659 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)8660 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
8661 {
8662 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
8663 }
8664
8665 /**
8666 * @brief Clear flag ADC analog watchdog 1.
8667 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
8668 * @param ADCx ADC instance
8669 * @retval None
8670 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)8671 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
8672 {
8673 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
8674 }
8675
8676 /**
8677 * @brief Clear flag ADC analog watchdog 2.
8678 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
8679 * @param ADCx ADC instance
8680 * @retval None
8681 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)8682 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
8683 {
8684 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
8685 }
8686
8687 /**
8688 * @brief Clear flag ADC analog watchdog 3.
8689 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
8690 * @param ADCx ADC instance
8691 * @retval None
8692 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)8693 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
8694 {
8695 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
8696 }
8697
8698
8699 /**
8700 * @}
8701 */
8702
8703 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
8704 * @{
8705 */
8706
8707 /**
8708 * @brief Enable ADC ready.
8709 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
8710 * @param ADCx ADC instance
8711 * @retval None
8712 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)8713 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
8714 {
8715 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8716 }
8717
8718 /**
8719 * @brief Enable interruption ADC group regular end of unitary conversion.
8720 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
8721 * @param ADCx ADC instance
8722 * @retval None
8723 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)8724 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
8725 {
8726 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
8727 }
8728
8729 /**
8730 * @brief Enable interruption ADC group regular end of sequence conversions.
8731 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
8732 * @param ADCx ADC instance
8733 * @retval None
8734 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)8735 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
8736 {
8737 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
8738 }
8739
8740 /**
8741 * @brief Enable ADC group regular interruption overrun.
8742 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
8743 * @param ADCx ADC instance
8744 * @retval None
8745 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)8746 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
8747 {
8748 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
8749 }
8750
8751 /**
8752 * @brief Enable interruption ADC group regular end of sampling.
8753 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
8754 * @param ADCx ADC instance
8755 * @retval None
8756 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)8757 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
8758 {
8759 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8760 }
8761
8762 /**
8763 * @brief Enable interruption ADC group injected end of unitary conversion.
8764 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
8765 * @param ADCx ADC instance
8766 * @retval None
8767 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)8768 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
8769 {
8770 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8771 }
8772
8773 /**
8774 * @brief Enable interruption ADC group injected end of sequence conversions.
8775 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
8776 * @param ADCx ADC instance
8777 * @retval None
8778 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)8779 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
8780 {
8781 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8782 }
8783
8784 /**
8785 * @brief Enable interruption ADC analog watchdog 1.
8786 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
8787 * @param ADCx ADC instance
8788 * @retval None
8789 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)8790 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
8791 {
8792 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8793 }
8794
8795 /**
8796 * @brief Enable interruption ADC analog watchdog 2.
8797 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
8798 * @param ADCx ADC instance
8799 * @retval None
8800 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)8801 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
8802 {
8803 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8804 }
8805
8806 /**
8807 * @brief Enable interruption ADC analog watchdog 3.
8808 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
8809 * @param ADCx ADC instance
8810 * @retval None
8811 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)8812 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
8813 {
8814 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8815 }
8816
8817 /**
8818 * @brief Enable interruption ADC end of calibration.
8819 * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
8820 * @param ADCx ADC instance
8821 * @retval None
8822 */
LL_ADC_EnableIT_EOCAL(ADC_TypeDef * ADCx)8823 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
8824 {
8825 SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
8826 }
8827
8828 /**
8829 * @brief Disable interruption ADC ready.
8830 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
8831 * @param ADCx ADC instance
8832 * @retval None
8833 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)8834 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
8835 {
8836 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8837 }
8838
8839 /**
8840 * @brief Disable interruption ADC group regular end of unitary conversion.
8841 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
8842 * @param ADCx ADC instance
8843 * @retval None
8844 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)8845 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
8846 {
8847 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
8848 }
8849
8850 /**
8851 * @brief Disable interruption ADC group regular end of sequence conversions.
8852 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
8853 * @param ADCx ADC instance
8854 * @retval None
8855 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)8856 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
8857 {
8858 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
8859 }
8860
8861 /**
8862 * @brief Disable interruption ADC group regular overrun.
8863 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
8864 * @param ADCx ADC instance
8865 * @retval None
8866 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)8867 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
8868 {
8869 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
8870 }
8871
8872 /**
8873 * @brief Disable interruption ADC group regular end of sampling.
8874 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
8875 * @param ADCx ADC instance
8876 * @retval None
8877 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)8878 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
8879 {
8880 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8881 }
8882
8883 /**
8884 * @brief Disable interruption ADC group regular end of unitary conversion.
8885 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
8886 * @param ADCx ADC instance
8887 * @retval None
8888 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)8889 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
8890 {
8891 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8892 }
8893
8894 /**
8895 * @brief Disable interruption ADC group injected end of sequence conversions.
8896 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
8897 * @param ADCx ADC instance
8898 * @retval None
8899 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)8900 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
8901 {
8902 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8903 }
8904
8905 /**
8906 * @brief Disable interruption ADC analog watchdog 1.
8907 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
8908 * @param ADCx ADC instance
8909 * @retval None
8910 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)8911 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
8912 {
8913 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8914 }
8915
8916 /**
8917 * @brief Disable interruption ADC analog watchdog 2.
8918 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
8919 * @param ADCx ADC instance
8920 * @retval None
8921 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)8922 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
8923 {
8924 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8925 }
8926
8927 /**
8928 * @brief Disable interruption ADC analog watchdog 3.
8929 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
8930 * @param ADCx ADC instance
8931 * @retval None
8932 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)8933 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
8934 {
8935 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8936 }
8937
8938 /**
8939 * @brief Disable interruption ADC end of calibration.
8940 * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
8941 * @param ADCx ADC instance
8942 * @retval None
8943 */
LL_ADC_DisableIT_EOCAL(ADC_TypeDef * ADCx)8944 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
8945 {
8946 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
8947 }
8948
8949 /**
8950 * @brief Get state of interruption ADC ready
8951 * (0: interrupt disabled, 1: interrupt enabled).
8952 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
8953 * @param ADCx ADC instance
8954 * @retval State of bit (1 or 0).
8955 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)8956 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
8957 {
8958 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
8959 }
8960
8961 /**
8962 * @brief Get state of interruption ADC group regular end of unitary conversion
8963 * (0: interrupt disabled, 1: interrupt enabled).
8964 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
8965 * @param ADCx ADC instance
8966 * @retval State of bit (1 or 0).
8967 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)8968 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
8969 {
8970 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
8971 }
8972
8973 /**
8974 * @brief Get state of interruption ADC group regular end of sequence conversions
8975 * (0: interrupt disabled, 1: interrupt enabled).
8976 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
8977 * @param ADCx ADC instance
8978 * @retval State of bit (1 or 0).
8979 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)8980 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
8981 {
8982 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
8983 }
8984
8985 /**
8986 * @brief Get state of interruption ADC group regular overrun
8987 * (0: interrupt disabled, 1: interrupt enabled).
8988 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
8989 * @param ADCx ADC instance
8990 * @retval State of bit (1 or 0).
8991 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)8992 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
8993 {
8994 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
8995 }
8996
8997 /**
8998 * @brief Get state of interruption ADC group regular end of sampling
8999 * (0: interrupt disabled, 1: interrupt enabled).
9000 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
9001 * @param ADCx ADC instance
9002 * @retval State of bit (1 or 0).
9003 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)9004 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
9005 {
9006 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
9007 }
9008
9009 /**
9010 * @brief Get state of interruption ADC group injected end of unitary conversion
9011 * (0: interrupt disabled, 1: interrupt enabled).
9012 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
9013 * @param ADCx ADC instance
9014 * @retval State of bit (1 or 0).
9015 */
LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef * ADCx)9016 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
9017 {
9018 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
9019 }
9020
9021 /**
9022 * @brief Get state of interruption ADC group injected end of sequence conversions
9023 * (0: interrupt disabled, 1: interrupt enabled).
9024 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
9025 * @param ADCx ADC instance
9026 * @retval State of bit (1 or 0).
9027 */
LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef * ADCx)9028 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
9029 {
9030 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
9031 }
9032
9033 /**
9034 * @brief Get state of interruption ADC analog watchdog 1
9035 * (0: interrupt disabled, 1: interrupt enabled).
9036 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
9037 * @param ADCx ADC instance
9038 * @retval State of bit (1 or 0).
9039 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)9040 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
9041 {
9042 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
9043 }
9044
9045 /**
9046 * @brief Get state of interruption Get ADC analog watchdog 2
9047 * (0: interrupt disabled, 1: interrupt enabled).
9048 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
9049 * @param ADCx ADC instance
9050 * @retval State of bit (1 or 0).
9051 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)9052 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
9053 {
9054 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
9055 }
9056
9057 /**
9058 * @brief Get state of interruption Get ADC analog watchdog 3
9059 * (0: interrupt disabled, 1: interrupt enabled).
9060 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
9061 * @param ADCx ADC instance
9062 * @retval State of bit (1 or 0).
9063 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)9064 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
9065 {
9066 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
9067 }
9068
9069 /**
9070 * @brief Get state of interruption ADC end of calibration
9071 * (0: interrupt disabled, 1: interrupt enabled).
9072 * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
9073 * @param ADCx ADC instance
9074 * @retval State of bit (1 or 0).
9075 */
LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef * ADCx)9076 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx)
9077 {
9078 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
9079 }
9080
9081 /**
9082 * @}
9083 */
9084
9085 #if defined(USE_FULL_LL_DRIVER)
9086 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
9087 * @{
9088 */
9089
9090 /* Initialization of some features of ADC common parameters and multimode */
9091 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *pADCxy_COMMON);
9092 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *pADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
9093 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
9094
9095 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
9096 /* (availability of ADC group injected depends on STM32 families) */
9097 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *pADCx);
9098
9099 /* Initialization of some features of ADC instance */
9100 ErrorStatus LL_ADC_Init(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct);
9101 void LL_ADC_StructInit(const ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct);
9102
9103 /* Initialization of some features of ADC instance and ADC group regular */
9104 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
9105 void LL_ADC_REG_StructInit(const ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
9106
9107 /* Initialization of some features of ADC instance and ADC group injected */
9108 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *pADCx, LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
9109 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
9110
9111 /**
9112 * @}
9113 */
9114 #endif /* USE_FULL_LL_DRIVER */
9115
9116 /**
9117 * @}
9118 */
9119
9120 /**
9121 * @}
9122 */
9123
9124 #endif /* ADC1 || ADC2 || ADC3 */
9125
9126 /**
9127 * @}
9128 */
9129
9130 #ifdef __cplusplus
9131 }
9132 #endif
9133
9134 #endif /* STM32U5xx_LL_ADC_H */
9135
