1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_ADC_H
21 #define STM32H5xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET (0x00000000UL)
56 #define ADC_SQR2_REGOFFSET (0x00000100UL)
57 #define ADC_SQR3_REGOFFSET (0x00000200UL)
58 #define ADC_SQR4_REGOFFSET (0x00000300UL)
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
61 | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/
63 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
64
65 /* Definition of ADC group regular sequencer bits information to be inserted */
66 /* into ADC group regular sequencer ranks literals definition. */
67 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
68 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
69 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
70 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
71 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)
72 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)
73 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)
74 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
75 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
76 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
77 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
78 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
79 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
80 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
81 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
82 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
83
84 /* Internal mask for ADC group injected sequencer: */
85 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
86 /* - data register offset */
87 /* - sequencer rank bits position into the selected register */
88
89 /* Internal register offset for ADC group injected data register */
90 /* (offset placed into a spare area of literal definition) */
91 #define ADC_JDR1_REGOFFSET (0x00000000UL)
92 #define ADC_JDR2_REGOFFSET (0x00000100UL)
93 #define ADC_JDR3_REGOFFSET (0x00000200UL)
94 #define ADC_JDR4_REGOFFSET (0x00000300UL)
95
96 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
97 | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
98 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
99 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/
100
101 /* Definition of ADC group injected sequencer bits information to be inserted */
102 /* into ADC group injected sequencer ranks literals definition. */
103 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
104 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
105 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
106 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
107
108 /* Internal mask for ADC group regular trigger: */
109 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
110 /* - regular trigger source */
111 /* - regular trigger edge */
112 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for
113 compatibility with some ADC on other STM32 series
114 having this setting set by HW default value) */
115
116 /* Mask containing trigger source masks for each of possible */
117 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
118 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
119 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
120 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
121 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
122 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
123
124 /* Mask containing trigger edge masks for each of possible */
125 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
126 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
127 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
128 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
129 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
130 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
131
132 /* Definition of ADC group regular trigger bits information. */
133 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)
134 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)
135
136 /* Internal mask for ADC group injected trigger: */
137 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
138 /* - injected trigger source */
139 /* - injected trigger edge */
140 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
141 compatibility with some ADC on other STM32 series
142 having this setting set by HW default value) */
143
144 /* Mask containing trigger source masks for each of possible */
145 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
146 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
147 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
148 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
149 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
150 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
151
152 /* Mask containing trigger edge masks for each of possible */
153 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
154 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
155 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
156 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
157 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
158 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
159
160 /* Definition of ADC group injected trigger bits information. */
161 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
162 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
163
164 /* Internal mask for ADC channel: */
165 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
166 /* - channel identifier defined by number */
167 /* - channel identifier defined by bitfield */
168 /* - channel differentiation between external channels (connected to */
169 /* GPIO pins) and internal channels (connected to internal paths) */
170 /* - channel sampling time defined by SMPRx register offset */
171 /* and SMPx bits positions into SMPRx register */
172 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
173 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
174 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
175 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
176 | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
177 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
178 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
179 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
180
181 /* Channel differentiation between external and internal channels */
182 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
183 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case
184 of different ADC internal channels mapped on same channel
185 number on different ADC instances */
186 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
187
188 /* Internal register offset for ADC channel sampling time configuration */
189 /* (offset placed into a spare area of literal definition) */
190 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
191 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
192 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
193 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET
194 in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
195
196 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
197 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK"
198 position in register */
199
200 /* Definition of channels ID number information to be inserted into */
201 /* channels literals definition. */
202 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
203 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
204 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
205 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
206 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
207 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
208 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
209 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
210 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
211 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
212 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
213 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
214 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
215 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
216 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
217 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
218 ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
219 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
220 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
221 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
222 #define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
223
224 /* Definition of channels ID bitfield information to be inserted into */
225 /* channels literals definition. */
226 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
227 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
228 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
229 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
230 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
231 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
232 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
233 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
234 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
235 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
236 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
237 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
238 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
239 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
240 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
241 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
242 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
243 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
244 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
245 #define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
246
247 /* Definition of channels sampling time information to be inserted into */
248 /* channels literals definition. */
249 /* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position */
250 /* in register. */
251 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
252 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
253 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
254 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
255 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
256 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
257 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
258 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
259 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
260 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
261 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
262 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
263 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
264 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
265 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
266 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
267 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
268 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
269 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
270 #define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
271
272
273 /* Internal mask for ADC mode single or differential ended: */
274 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
275 /* the relevant bits for: */
276 /* (concatenation of multiple bits used in different registers) */
277 /* - ADC calibration: calibration start, calibration factor get or set */
278 /* - ADC channels: set each ADC channel ending mode */
279 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
280 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
281 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
282 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen
283 to perform of shift when single mode is selected, shift value out of
284 channels bits range. */
285 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
286 mask of bit */
287 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode:
288 position of bit */
289 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
290 ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */
291
292 /* Internal mask for ADC analog watchdog: */
293 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
294 /* (concatenation of multiple bits used in different analog watchdogs, */
295 /* (feature of several watchdogs not available on all STM32 series)). */
296 /* - analog watchdog 1: monitored channel defined by number, */
297 /* selection of ADC group (ADC groups regular and-or injected). */
298 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
299 /* selection on groups. */
300
301 /* Internal register offset for ADC analog watchdog channel configuration */
302 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
303 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
304 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
305
306 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
307 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
308 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
309 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
310
311 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
312
313 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
314 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
315 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
316
317 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
318 in ADC_AWD_CRX_REGOFFSET_MASK */
319
320 /* Internal register offset for ADC analog watchdog threshold configuration */
321 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
322 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
323 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
324 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
325 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
326 in ADC_AWD_TRX_REGOFFSET_MASK */
327 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
328 threshold high: mask of bit */
329 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
330 threshold high: position of bit */
331 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
332 position to perform a shift of 4 ranks */
333
334 /* Internal mask for ADC offset: */
335 /* Internal register offset for ADC offset instance configuration */
336 #define ADC_OFR1_REGOFFSET (0x00000000UL)
337 #define ADC_OFR2_REGOFFSET (0x00000001UL)
338 #define ADC_OFR3_REGOFFSET (0x00000002UL)
339 #define ADC_OFR4_REGOFFSET (0x00000003UL)
340 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
341 | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
342
343
344 /* ADC registers bits positions */
345 #define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
346 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
347 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
348 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
349 #define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)
350
351
352 /* ADC registers bits groups */
353 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
354 | ADC_CR_JADSTART | ADC_CR_JADSTP \
355 | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
356 HW property "rs": Software can read as well as set this bit.
357 Writing '0' has no effect on the bit value. */
358
359
360 /* ADC internal channels related definitions */
361 /* Internal voltage reference VrefInt */
362 #define VREFINT_CAL_ADDR ((uint16_t*) (0x08FFF810UL)) /* Internal voltage reference, address of
363 parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
364 (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
365 #define VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value
366 with which VrefInt has been calibrated in production
367 (tolerance: +-10 mV) (unit: mV). */
368 /* Temperature sensor */
369 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x08FFF814UL)) /* Address of parameter TS_CAL1: On STM32H5,
370 temperature sensor ADC raw data acquired at temperature 30 DegC
371 (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
372 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x08FFF818UL)) /* Address of parameter TS_CAL2: On STM32H5,
373 temperature sensor ADC raw data acquired at temperature 130 DegC
374 (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
375 #define TEMPSENSOR_CAL1_TEMP (30L) /* Temperature at which temperature sensor
376 has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
377 (tolerance: +-5 DegC) (unit: DegC). */
378 #define TEMPSENSOR_CAL2_TEMP (130L) /* Temperature at which temperature sensor
379 has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
380 (tolerance: +-5 DegC) (unit: DegC). */
381 #define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) value
382 with which temperature sensor has been calibrated in production
383 (tolerance +-10 mV) (unit: mV). */
384
385 /**
386 * @}
387 */
388
389 /* Private macros ------------------------------------------------------------*/
390 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
391 * @{
392 */
393
394 /**
395 * @brief Driver macro reserved for internal use: set a pointer to
396 * a register from a register basis from which an offset
397 * is applied.
398 * @param __REG__ Register basis from which the offset is applied.
399 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
400 * @retval Pointer to register address
401 */
402 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
403 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
404
405 /**
406 * @}
407 */
408
409 /* Exported types ------------------------------------------------------------*/
410 #if defined(USE_FULL_LL_DRIVER)
411 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
412 * @{
413 */
414
415 /**
416 * @brief Structure definition of some features of ADC common parameters
417 * and multimode
418 * (all ADC instances belonging to the same ADC common instance).
419 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
420 * is conditioned to ADC instances state (all ADC instances
421 * sharing the same ADC common instance):
422 * All ADC instances sharing the same ADC common instance must be
423 * disabled.
424 */
425 typedef struct
426 {
427 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
428 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
429 @note On this STM32 series, if ADC group injected is used, some clock ratio
430 constraints between ADC clock and AHB clock must be respected.
431 Refer to reference manual.
432 This feature can be modified afterwards using unitary function
433 @ref LL_ADC_SetCommonClock(). */
434
435 #if defined(ADC_MULTIMODE_SUPPORT)
436 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode
437 (for devices with several ADC instances).
438 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
439 This feature can be modified afterwards using unitary function
440 @ref LL_ADC_SetMultimode(). */
441
442 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
443 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
444 This feature can be modified afterwards using unitary function
445 @ref LL_ADC_SetMultiDMATransfer(). */
446
447 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
448 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
449 This feature can be modified afterwards using unitary function
450 @ref LL_ADC_SetMultiTwoSamplingDelay(). */
451 #endif /* ADC_MULTIMODE_SUPPORT */
452
453 } LL_ADC_CommonInitTypeDef;
454
455 /**
456 * @brief Structure definition of some features of ADC instance.
457 * @note These parameters have an impact on ADC scope: ADC instance.
458 * Affects both group regular and group injected (availability
459 * of ADC group injected depends on STM32 series).
460 * Refer to corresponding unitary functions into
461 * @ref ADC_LL_EF_Configuration_ADC_Instance .
462 * @note The setting of these parameters by function @ref LL_ADC_Init()
463 * is conditioned to ADC state:
464 * ADC instance must be disabled.
465 * This condition is applied to all ADC features, for efficiency
466 * and compatibility over all STM32 series. However, the different
467 * features can be set under different ADC state conditions
468 * (setting possible with ADC enabled without conversion on going,
469 * ADC enabled with conversion on going, ...)
470 * Each feature can be updated afterwards with a unitary function
471 * and potentially with ADC in a different state than disabled,
472 * refer to description of each function for setting
473 * conditioned to ADC state.
474 */
475 typedef struct
476 {
477 uint32_t Resolution; /*!< Set ADC resolution.
478 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
479 This feature can be modified afterwards using unitary function
480 @ref LL_ADC_SetResolution(). */
481
482 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
483 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
484 This feature can be modified afterwards using unitary function
485 @ref LL_ADC_SetDataAlignment(). */
486
487 uint32_t LowPowerMode; /*!< Set ADC low power mode.
488 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
489 This feature can be modified afterwards using unitary function
490 @ref LL_ADC_SetLowPowerMode(). */
491
492 } LL_ADC_InitTypeDef;
493
494 /**
495 * @brief Structure definition of some features of ADC group regular.
496 * @note These parameters have an impact on ADC scope: ADC group regular.
497 * Refer to corresponding unitary functions into
498 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
499 * (functions with prefix "REG").
500 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
501 * is conditioned to ADC state:
502 * ADC instance must be disabled.
503 * This condition is applied to all ADC features, for efficiency
504 * and compatibility over all STM32 series. However, the different
505 * features can be set under different ADC state conditions
506 * (setting possible with ADC enabled without conversion on going,
507 * ADC enabled with conversion on going, ...)
508 * Each feature can be updated afterwards with a unitary function
509 * and potentially with ADC in a different state than disabled,
510 * refer to description of each function for setting
511 * conditioned to ADC state.
512 */
513 typedef struct
514 {
515 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
516 from external peripheral (timer event, external interrupt line).
517 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
518 @note On this STM32 series, setting trigger source to external trigger also
519 set trigger polarity to rising edge(default setting for compatibility
520 with some ADC on other STM32 series having this setting set by HW
521 default value).
522 In case of need to modify trigger edge, use function
523 @ref LL_ADC_REG_SetTriggerEdge().
524 This feature can be modified afterwards using unitary function
525 @ref LL_ADC_REG_SetTriggerSource(). */
526
527 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
528 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
529 This feature can be modified afterwards using unitary function
530 @ref LL_ADC_REG_SetSequencerLength(). */
531
532 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
533 and scan conversions interrupted every selected number of ranks.
534 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
535 @note This parameter has an effect only if group regular sequencer is
536 enabled (scan length of 2 ranks or more).
537 This feature can be modified afterwards using unitary function
538 @ref LL_ADC_REG_SetSequencerDiscont(). */
539
540 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
541 conversions are performed in single mode (one conversion per trigger) or in
542 continuous mode (after the first trigger, following conversions launched
543 successively automatically).
544 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
545 Note: It is not possible to enable both ADC group regular continuous mode
546 and discontinuous mode.
547 This feature can be modified afterwards using unitary function
548 @ref LL_ADC_REG_SetContinuousMode(). */
549
550 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
551 by DMA, and DMA requests mode.
552 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
553 This feature can be modified afterwards using unitary function
554 @ref LL_ADC_REG_SetDMATransfer(). */
555
556 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
557 data preserved or overwritten.
558 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
559 This feature can be modified afterwards using unitary function
560 @ref LL_ADC_REG_SetOverrun(). */
561
562 } LL_ADC_REG_InitTypeDef;
563
564 /**
565 * @brief Structure definition of some features of ADC group injected.
566 * @note These parameters have an impact on ADC scope: ADC group injected.
567 * Refer to corresponding unitary functions into
568 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
569 * (functions with prefix "INJ").
570 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
571 * is conditioned to ADC state:
572 * ADC instance must be disabled.
573 * This condition is applied to all ADC features, for efficiency
574 * and compatibility over all STM32 series. However, the different
575 * features can be set under different ADC state conditions
576 * (setting possible with ADC enabled without conversion on going,
577 * ADC enabled with conversion on going, ...)
578 * Each feature can be updated afterwards with a unitary function
579 * and potentially with ADC in a different state than disabled,
580 * refer to description of each function for setting
581 * conditioned to ADC state.
582 */
583 typedef struct
584 {
585 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start)
586 or from external peripheral (timer event, external interrupt line).
587 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
588 @note On this STM32 series, setting trigger source to external trigger also
589 set trigger polarity to rising edge (default setting for
590 compatibility with some ADC on other STM32 series having this
591 setting set by HW default value).
592 In case of need to modify trigger edge, use function
593 @ref LL_ADC_INJ_SetTriggerEdge().
594 This feature can be modified afterwards using unitary function
595 @ref LL_ADC_INJ_SetTriggerSource(). */
596
597 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
598 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
599 This feature can be modified afterwards using unitary function
600 @ref LL_ADC_INJ_SetSequencerLength(). */
601
602 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
603 and scan conversions interrupted every selected number of ranks.
604 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
605 @note This parameter has an effect only if group injected sequencer is
606 enabled (scan length of 2 ranks or more).
607 This feature can be modified afterwards using unitary function
608 @ref LL_ADC_INJ_SetSequencerDiscont(). */
609
610 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group
611 regular.
612 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
613 Note: This parameter must be set to set to independent trigger if injected
614 trigger source is set to an external trigger.
615 This feature can be modified afterwards using unitary function
616 @ref LL_ADC_INJ_SetTrigAuto(). */
617
618 } LL_ADC_INJ_InitTypeDef;
619
620 /**
621 * @}
622 */
623 #endif /* USE_FULL_LL_DRIVER */
624
625 /* Exported constants --------------------------------------------------------*/
626 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
627 * @{
628 */
629
630 /** @defgroup ADC_LL_EC_FLAG ADC flags
631 * @brief Flags defines which can be used with LL_ADC_ReadReg function
632 * @{
633 */
634 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
635 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
636 conversion */
637 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
638 conversions */
639 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
640 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
641 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary
642 conversion */
643 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence
644 conversions */
645 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue
646 overflow */
647 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
648 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
649 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
650 #if defined(ADC_MULTIMODE_SUPPORT)
651 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
652 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
653 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of
654 unitary conversion */
655 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of
656 unitary conversion */
657 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of
658 sequence conversions */
659 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of
660 sequence conversions */
661 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular
662 overrun */
663 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular
664 overrun */
665 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of
666 sampling phase */
667 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of
668 sampling phase */
669 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of
670 unitary conversion */
671 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of
672 unitary conversion */
673 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of
674 sequence conversions */
675 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of
676 sequence conversions */
677 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected
678 contexts queue overflow */
679 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected
680 contexts queue overflow */
681 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1
682 of the ADC master */
683 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1
684 of the ADC slave */
685 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2
686 of the ADC master */
687 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2
688 of the ADC slave */
689 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3
690 of the ADC master */
691 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3
692 of the ADC slave */
693 #endif /* ADC_MULTIMODE_SUPPORT */
694 /**
695 * @}
696 */
697
698 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
699 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
700 * @{
701 */
702 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
703 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
704 conversion */
705 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
706 conversions */
707 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
708 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
709 phase */
710 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary
711 conversion */
712 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence
713 conversions */
714 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue
715 overflow */
716 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
717 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
718 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
719 /**
720 * @}
721 */
722
723 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
724 * @{
725 */
726 /* List of ADC registers intended to be used (most commonly) with */
727 /* DMA transfer. */
728 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
729 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
730 (corresponding to register DR) to be used with ADC configured in independent
731 mode. Without DMA transfer, register accessed by LL function
732 @ref LL_ADC_REG_ReadConversionData32() and other
733 functions @ref LL_ADC_REG_ReadConversionDatax() */
734 #if defined(ADC_MULTIMODE_SUPPORT)
735 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register
736 (corresponding to register CDR) to be used with ADC configured in multimode
737 (available on STM32 devices with several ADC instances).
738 Without DMA transfer, register accessed by LL function
739 @ref LL_ADC_REG_ReadMultiConversionData32() */
740 #endif /* ADC_MULTIMODE_SUPPORT */
741 /**
742 * @}
743 */
744
745 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
746 * @{
747 */
748 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
749 AHB clock without prescaler */
750 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from
751 AHB clock with prescaler division by 2 */
752 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
753 AHB clock with prescaler division by 4 */
754 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without
755 prescaler */
756 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
757 prescaler division by 2 */
758 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
759 prescaler division by 4 */
760 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
761 prescaler division by 6 */
762 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
763 prescaler division by 8 */
764 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
765 prescaler division by 10 */
766 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
767 prescaler division by 12 */
768 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
769 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
770 prescaler division by 16 */
771 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
772 prescaler division by 32 */
773 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
774 prescaler division by 64 */
775 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
776 prescaler division by 128 */
777 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
778 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
779 prescaler division by 256 */
780 /**
781 * @}
782 */
783
784 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
785 * @{
786 */
787 /* Note: Other measurement paths to internal channels may be available */
788 /* (connections to other peripherals). */
789 /* If they are not listed below, they do not require any specific */
790 /* path enable. In this case, Access to measurement path is done */
791 /* only by selecting the corresponding ADC internal channel. */
792 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
793 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
794 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel
795 temperature sensor */
796 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
797 /**
798 * @}
799 */
800
801 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
802 * @{
803 */
804 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
805 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
806 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
807 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
808 /**
809 * @}
810 */
811
812 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
813 * @{
814 */
815 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
816 (alignment on data register LSB bit 0)*/
817 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned
818 (alignment on data register MSB bit 15)*/
819 /**
820 * @}
821 */
822
823 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
824 * @{
825 */
826 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
827 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power
828 mode, ADC conversions are performed only when necessary
829 (when previous ADC conversion data is read).
830 See description with function @ref LL_ADC_SetLowPowerMode(). */
831 /**
832 * @}
833 */
834
835 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset instance
836 * @{
837 */
838 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level
839 to which the offset programmed will be applied (independently of channel
840 mapped on ADC group regular or injected) */
841 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level
842 to which the offset programmed will be applied (independently of channel
843 mapped on ADC group regular or injected) */
844 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level
845 to which the offset programmed will be applied (independently of channel
846 mapped on ADC group regular or injected) */
847 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level
848 to which the offset programmed will be applied (independently of channel
849 mapped on ADC group regular or injected) */
850 /**
851 * @}
852 */
853
854 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
855 * @{
856 */
857 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled
858 (setting offset instance wise) */
859 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled
860 (setting offset instance wise) */
861 /**
862 * @}
863 */
864
865 /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
866 * @{
867 */
868 #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative */
869 #define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive */
870 /**
871 * @}
872 */
873
874 /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
875 * @{
876 */
877 #define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC
878 selected offset instance 1, 2, 3 or 4) */
879 #define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC
880 selected offset instance 1, 2, 3 or 4) */
881 /**
882 * @}
883 */
884 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
885 * @{
886 */
887 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
888 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32
889 devices)*/
890 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
891 /**
892 * @}
893 */
894
895 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
896 * @{
897 */
898 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP \
899 | ADC_CHANNEL_0_BITFIELD) /*!< ADC channel ADCx_IN0 */
900 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP \
901 | ADC_CHANNEL_1_BITFIELD) /*!< ADC channel ADCx_IN1 */
902 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP \
903 | ADC_CHANNEL_2_BITFIELD) /*!< ADC channel ADCx_IN2 */
904 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP \
905 | ADC_CHANNEL_3_BITFIELD) /*!< ADC channel ADCx_IN3 */
906 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP \
907 | ADC_CHANNEL_4_BITFIELD) /*!< ADC channel ADCx_IN4 */
908 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP \
909 | ADC_CHANNEL_5_BITFIELD) /*!< ADC channel ADCx_IN5 */
910 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP \
911 | ADC_CHANNEL_6_BITFIELD) /*!< ADC channel ADCx_IN6 */
912 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP \
913 | ADC_CHANNEL_7_BITFIELD) /*!< ADC channel ADCx_IN7 */
914 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP \
915 | ADC_CHANNEL_8_BITFIELD) /*!< ADC channel ADCx_IN8 */
916 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP \
917 | ADC_CHANNEL_9_BITFIELD) /*!< ADC channel ADCx_IN9 */
918 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP \
919 | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
920 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP \
921 | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
922 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP \
923 | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
924 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP \
925 | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
926 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP \
927 | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
928 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP \
929 | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
930 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP \
931 | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
932 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP \
933 | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
934 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP \
935 | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */
936 #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP \
937 | ADC_CHANNEL_19_BITFIELD) /*!< ADC channel ADCx_IN19 */
938 #if defined (ADC2)
939 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
940 connected to VrefInt: Internal voltage reference.
941 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. */
942 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
943 connected to internal temperature sensor.
944 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. */
945 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel
946 connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4
947 to have channel voltage always below Vdda.
948 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC2. */
949 #define LL_ADC_CHANNEL_VDDCORE (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel
950 connected to Vddcore.
951 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC2. */
952 #else
953 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
954 connected to VrefInt: Internal voltage reference. */
955 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
956 connected to internal temperature sensor.*/
957 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_2 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
958 connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4
959 to have channel voltage always below Vdda. */
960 #define LL_ADC_CHANNEL_VDDCORE (LL_ADC_CHANNEL_6 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
961 connected to Vddcore.*/
962 #endif /* ADC2 */
963
964 /* Definitions for backward compatibility with legacy STM32 series */
965 #define LL_ADC_CHANNEL_VCORE LL_ADC_CHANNEL_VDDCORE
966 /**
967 * @}
968 */
969
970 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
971 * @{
972 */
973 /* Triggers common to all devices of STM32H5 series */
974 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular
975 conversion trigger internal: SW start. */
976 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
977 conversion trigger from external peripheral: TIM1 channel 1 event
978 (capture compare: input capture or output capture).
979 Trigger edge set to rising edge (default setting). */
980 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
981 conversion trigger from external peripheral: TIM1 channel 2 event
982 (capture compare: input capture or output capture).
983 Trigger edge set to rising edge (default setting). */
984 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
985 conversion trigger from external peripheral: TIM1 channel 3 event
986 (capture compare: input capture or output capture).
987 Trigger edge set to rising edge (default setting). */
988 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 \
989 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
990 conversion trigger from external peripheral: TIM2 channel 2 event
991 (capture compare: input capture or output capture).
992 Trigger edge set to rising edge (default setting). */
993 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
994 conversion trigger from external peripheral: TIM3 TRGO event.
995 Trigger edge set to rising edge (default setting). */
996 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 \
997 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
998 conversion trigger from external peripheral: external interrupt line 11
999 event. Trigger edge set to rising edge (default setting). */
1000 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 \
1001 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1002 conversion trigger from external peripheral: TIM1 TRGO event.
1003 Trigger edge set to rising edge (default setting). */
1004 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 \
1005 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1006 conversion trigger from external peripheral: TIM1 TRGO2 event.
1007 Trigger edge set to rising edge (default setting). */
1008 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 \
1009 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1010 conversion trigger from external peripheral: TIM2 TRGO event.
1011 Trigger edge set to rising edge (default setting). */
1012 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \
1013 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1014 conversion trigger from external peripheral: TIM6 TRGO event.
1015 Trigger edge set to rising edge (default setting). */
1016 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \
1017 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 \
1018 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1019 conversion trigger from external peripheral: TIM3 channel 4 event
1020 (capture compare: input capture or output capture).
1021 Trigger edge set to rising edge (default setting). */
1022 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE15 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1023 conversion trigger from external peripheral: LPTIM1 OUT event.
1024 Trigger edge set to rising edge (default setting). */
1025 #define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 \
1026 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1027 conversion trigger from external peripheral: LPTIM2 OUT event.
1028 Trigger edge set to rising edge (default setting). */
1029 #define LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 \
1030 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1031 conversion trigger from external peripheral: LPTIM3 event OUT.
1032 Trigger edge set to rising edge (default setting). */
1033
1034 /* Triggers specific to some devices of STM32H5 series */
1035 #if defined(TIM8)
1036 /* Devices STM32H563/H573xx */
1037 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 \
1038 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1039 conversion trigger from external peripheral: TIM4 channel 4 event
1040 (capture compare: input capture or output capture).
1041 Trigger edge set to rising edge (default setting).
1042 Specific to devices: STM32H563/H573xx. */
1043 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 \
1044 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1045 conversion trigger from external peripheral: TIM12 TRGO event.
1046 Trigger edge set to rising edge (default setting).
1047 Specific to devices: STM32H563/H573xx. */
1048 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1049 conversion trigger from external peripheral: TIM8 TRGO event.
1050 Trigger edge set to rising edge (default setting).
1051 Specific to devices: STM32H563/H573xx. */
1052 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \
1053 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1054 conversion trigger from external peripheral: TIM4 TRGO event.
1055 Trigger edge set to rising edge (default setting).
1056 Specific to devices: STM32H563/H573xx. */
1057 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \
1058 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1059 conversion trigger from external peripheral: TIM15 TRGO event.
1060 Trigger edge set to rising edge (default setting).
1061 Specific to devices: STM32H563/H573xx. */
1062 #else
1063 /* Devices STM32H503xx */
1064 #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 \
1065 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1066 conversion trigger from external peripheral: TIM7 TRGO event.
1067 Trigger edge set to rising edge (default setting).
1068 Specific to devices: STM32H503xx. */
1069 #endif /* Devices STM32H563/H573xx or STM32H503xx */
1070 /**
1071 * @}
1072 */
1073
1074 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
1075 * @{
1076 */
1077 #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion
1078 trigger polarity set to rising edge */
1079 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1) /*!< ADC group regular conversion
1080 trigger polarity set to falling edge */
1081 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion
1082 trigger polarity set to both rising and falling edges */
1083 /**
1084 * @}
1085 */
1086
1087 /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
1088 * @{
1089 */
1090 #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration
1091 is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */
1092 #define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts
1093 immediately after end of conversion, and stops upon trigger event.
1094 Note: First conversion is using minimal sampling time
1095 (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */
1096 #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is
1097 controlled by trigger events: trigger rising edge for start sampling,
1098 trigger falling edge for stop sampling and start conversion */
1099 /**
1100 * @}
1101 */
1102
1103 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
1104 * @{
1105 */
1106 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
1107 one conversion per trigger */
1108 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions performed in continuous mode:
1109 after the first trigger, following conversions launched successively
1110 automatically */
1111 /**
1112 * @}
1113 */
1114
1115 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
1116 * @{
1117 */
1118 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
1119 #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA
1120 in limited mode (one shot mode): DMA transfer requests are stopped when
1121 number of DMA data transfers (number of ADC conversions) is reached.
1122 This ADC mode is intended to be used with DMA mode non-circular. */
1123 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are
1124 transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
1125 whatever number of DMA data transferred (number of ADC conversions).
1126 This ADC mode is intended to be used with DMA mode circular. */
1127 /**
1128 * @}
1129 */
1130
1131 #if defined(ADC_SMPR1_SMPPLUS)
1132 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
1133 * @{
1134 */
1135 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */
1136 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock
1137 cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped
1138 with selection sampling time 2.5 ADC clock cycles, whatever channels mapped
1139 on ADC groups regular or injected). */
1140 /**
1141 * @}
1142 */
1143 #endif /* ADC_SMPR1_SMPPLUS */
1144
1145 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
1146 * @{
1147 */
1148 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
1149 data preserved */
1150 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun:
1151 data overwritten */
1152 /**
1153 * @}
1154 */
1155
1156 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1157 * @{
1158 */
1159 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable
1160 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1161 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1162 with 2 ranks in the sequence */
1163 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1164 with 3 ranks in the sequence */
1165 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1166 with 4 ranks in the sequence */
1167 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1168 with 5 ranks in the sequence */
1169 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1170 with 6 ranks in the sequence */
1171 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1172 with 7 ranks in the sequence */
1173 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1 \
1174 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1175 with 8 ranks in the sequence */
1176 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3) /*!< ADC group regular sequencer enable
1177 with 9 ranks in the sequence */
1178 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1179 with 10 ranks in the sequence */
1180 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1181 with 11 ranks in the sequence */
1182 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \
1183 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1184 with 12 ranks in the sequence */
1185 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1186 with 13 ranks in the sequence */
1187 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1188 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1189 with 14 ranks in the sequence */
1190 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1191 | ADC_SQR1_L_1) /*!< ADC group regular sequencerenable
1192 with 15 ranks in the sequence */
1193 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1194 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1195 with 16 ranks in the sequence */
1196 /**
1197 * @}
1198 */
1199
1200 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1201 * @{
1202 */
1203 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
1204 discontinuous mode disable */
1205 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1206 discontinuous mode enable with sequence interruption every rank */
1207 #define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1208 discontinuous mode enabled with sequence interruption every 2 ranks */
1209 #define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1210 discontinuous mode enable with sequence interruption every 3 ranks */
1211 #define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 \
1212 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1213 discontinuous mode enable with sequence interruption every 4 ranks */
1214 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1215 discontinuous mode enable with sequence interruption every 5 ranks */
1216 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 \
1217 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1218 discontinuous mode enable with sequence interruption every 6 ranks */
1219 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
1220 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1221 discontinuous mode enable with sequence interruption every 7 ranks */
1222 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
1223 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1224 discontinuous mode enable with sequence interruption every 8 ranks */
1225 /**
1226 * @}
1227 */
1228
1229 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1230 * @{
1231 */
1232 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group
1233 regular sequencer rank 1 */
1234 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group
1235 regular sequencer rank 2 */
1236 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group
1237 regular sequencer rank 3 */
1238 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group
1239 regular sequencer rank 4 */
1240 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group
1241 regular sequencer rank 5 */
1242 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group
1243 regular sequencer rank 6 */
1244 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group
1245 regular sequencer rank 7 */
1246 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group
1247 regular sequencer rank 8 */
1248 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group
1249 regular sequencer rank 9 */
1250 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group
1251 regular sequencer rank 10 */
1252 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group
1253 regular sequencer rank 11 */
1254 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group
1255 regular sequencer rank 12 */
1256 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group
1257 regular sequencer rank 13 */
1258 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group
1259 regular sequencer rank 14 */
1260 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group
1261 regular sequencer rank 15 */
1262 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group
1263 regular sequencer rank 16 */
1264 /**
1265 * @}
1266 */
1267
1268 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1269 * @{
1270 */
1271 /* Triggers common to all devices of STM32H5 series */
1272 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected
1273 conversion trigger internal: SW start. */
1274 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1275 conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge
1276 set to rising edge (default setting). */
1277 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1278 conversion trigger from external peripheral: TIM1 channel 4 event (capture
1279 compare: input capture or output capture). Trigger edge set to rising edge
1280 (default setting). */
1281 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1282 conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge
1283 set to rising edge (default setting). */
1284 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1285 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1286 conversion trigger from external peripheral: TIM2 channel 1 event (capture
1287 compare: input capture or output capture). Trigger edge set to rising edge
1288 (default setting). */
1289 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1290 conversion trigger from external peripheral: TIM3 channel 4 event (capture
1291 compare: input capture or output capture). Trigger edge set to rising edge
1292 (default setting). */
1293 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
1294 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1295 conversion trigger from external peripheral: external interrupt line 15.
1296 Trigger edge set to rising edge (default setting). */
1297 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1298 conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge
1299 set to rising edge (default setting). */
1300 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \
1301 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected
1302 conversion trigger from external peripheral: TIM3 channel 3 event (capture
1303 compare: input capture or output capture). Trigger edge set to rising edge
1304 (default setting). */
1305 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
1306 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1307 conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge
1308 set to rising edge (default setting). */
1309 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
1310 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected
1311 conversion trigger from external peripheral: TIM3 channel 1 event (capture
1312 compare: input capture or output capture). Trigger edge set to rising edge
1313 (default setting). */
1314 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
1315 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected
1316 conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge
1317 set to rising edge (default setting). */
1318 #define LL_ADC_INJ_TRIG_EXT_LPTIM1_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \
1319 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1320 conversion trigger from external peripheral: LPTIM1 channel 1 event. Trigger
1321 edge set to rising edge (default setting). */
1322 #define LL_ADC_INJ_TRIG_EXT_LPTIM2_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \
1323 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected
1324 conversion trigger from external peripheral: LPTIM2 channel 1 event. Trigger
1325 edge set to rising edge (default setting). */
1326
1327 /* Triggers specific to some devices of STM32H5 series */
1328 #if defined(TIM8)
1329 /* Devices STM32H563/H573xx */
1330 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
1331 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1332 conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge
1333 set to rising edge (default setting).
1334 Specific to devices: STM32H563/H573xx. */
1335 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
1336 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected
1337 conversion trigger from external peripheral: TIM9 channel 1 event (capture
1338 compare: input capture or output capture). Trigger edge set to rising edge
1339 (default setting).
1340 Specific to devices: STM32H563/H573xx. */
1341 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 \
1342 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1343 conversion trigger from external peripheral: TIM12 TRGO event. Trigger edge
1344 set to rising edge (default setting).
1345 Specific to devices: STM32H563/H573xx. */
1346 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \
1347 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1348 conversion trigger from external peripheral: TIM9 TRGO event. Trigger edge
1349 set to rising edge (default setting).
1350 Specific to devices: STM32H563/H573xx. */
1351 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
1352 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1353 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1354 conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge
1355 set to rising edge (default setting). */
1356 #else
1357 /* Devices STM32H503xx */
1358 #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 \
1359 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1360 conversion trigger from external peripheral: TIM7 TRGO event. Trigger edge
1361 set to rising edge (default setting). */
1362 #endif /* Devices STM32H563/H573xx or STM32H503xx */
1363 /**
1364 * @}
1365 */
1366
1367 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1368 * @{
1369 */
1370 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
1371 trigger polarity set to rising edge */
1372 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion
1373 trigger polarity set to falling edge */
1374 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
1375 trigger polarity set to both rising and falling edges */
1376 /**
1377 * @}
1378 */
1379
1380 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1381 * @{
1382 */
1383 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent.
1384 Setting mandatory if ADC group injected injected trigger source is set to
1385 an external trigger. */
1386 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group
1387 regular. Setting compliant only with group injected trigger source set to
1388 SW start, without any further action on ADC group injected conversion start
1389 or stop: in this case, ADC group injected is controlled only from ADC group
1390 regular. */
1391 /**
1392 * @}
1393 */
1394
1395 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1396 * @{
1397 */
1398 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled
1399 and can contain up to 2 contexts. When all contexts have been processed,
1400 the queue maintains the last context active perpetually. */
1401 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled
1402 and can contain up to 2 contexts. When all contexts have been processed,
1403 the queue is empty and injected group triggers are disabled. */
1404 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled:
1405 only 1 sequence can be configured and is active perpetually. */
1406 /**
1407 * @}
1408 */
1409
1410 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1411 * @{
1412 */
1413 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable
1414 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1415 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
1416 with 2 ranks in the sequence */
1417 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable
1418 with 3 ranks in the sequence */
1419 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
1420 with 4 ranks in the sequence */
1421 /**
1422 * @}
1423 */
1424
1425 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1426 * @{
1427 */
1428 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode
1429 disable */
1430 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode
1431 enable with sequence interruption every rank */
1432 /**
1433 * @}
1434 */
1435
1436 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1437 * @{
1438 */
1439 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \
1440 | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 1 */
1441 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \
1442 | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 2 */
1443 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \
1444 | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 3 */
1445 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \
1446 | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 4 */
1447 /**
1448 * @}
1449 */
1450
1451 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1452 * @{
1453 */
1454 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
1455 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
1456 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */
1457 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 (ADC_SMPR2_SMP10_1 \
1458 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
1459 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */
1460 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 \
1461 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
1462 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 \
1463 | ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */
1464 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 \
1465 | ADC_SMPR2_SMP10_1 \
1466 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
1467 /**
1468 * @}
1469 */
1470
1471 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1472 * @{
1473 */
1474 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending
1475 set to single ended (literal also used to set calibration mode) */
1476 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending
1477 set to differential (literal also used to set calibration mode) */
1478 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending
1479 set to both single ended and differential (literal used only to set
1480 calibration factors) */
1481 /**
1482 * @}
1483 */
1484
1485 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1486 * @{
1487 */
1488 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
1489 | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1490 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
1491 | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1492 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
1493 | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1494 /**
1495 * @}
1496 */
1497
1498 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1499 * @{
1500 */
1501 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
1502 disabled */
1503 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
1504 | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring
1505 of all channels, converted by group regular only */
1506 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1507 | ADC_CFGR_JAWD1EN) /*!< ADC analog watchdog monitoring
1508 of all channels, converted by group injected only */
1509 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1510 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring
1511 of all channels, converted by either group regular or injected */
1512 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1513 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1514 of ADC channel ADCx_IN0, converted by group regular only */
1515 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1516 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1517 of ADC channel ADCx_IN0, converted by group injected only */
1518 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1519 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1520 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1521 of ADC channel ADCx_IN0, converted by either group regular or injected */
1522 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1523 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1524 of ADC channel ADCx_IN1, converted by group regular only */
1525 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1526 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1527 of ADC channel ADCx_IN1, converted by group injected only */
1528 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1529 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1530 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1531 of ADC channel ADCx_IN1, converted by either group regular or injected */
1532 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1533 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1534 of ADC channel ADCx_IN2, converted by group regular only */
1535 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1536 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1537 of ADC channel ADCx_IN2, converted by group injected only */
1538 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1539 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1540 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1541 of ADC channel ADCx_IN2, converted by either group regular or injected */
1542 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1543 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1544 of ADC channel ADCx_IN3, converted by group regular only */
1545 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1546 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1547 of ADC channel ADCx_IN3, converted by group injected only */
1548 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1549 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1550 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1551 of ADC channel ADCx_IN3, converted by either group regular or injected */
1552 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1553 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1554 of ADC channel ADCx_IN4, converted by group regular only */
1555 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1556 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1557 of ADC channel ADCx_IN4, converted by group injected only */
1558 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1559 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1560 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1561 of ADC channel ADCx_IN4, converted by either group regular or injected */
1562 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1563 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1564 of ADC channel ADCx_IN5, converted by group regular only */
1565 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1566 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1567 of ADC channel ADCx_IN5, converted by group injected only */
1568 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1569 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1570 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1571 of ADC channel ADCx_IN5, converted by either group regular or injected */
1572 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1573 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1574 of ADC channel ADCx_IN6, converted by group regular only */
1575 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1576 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1577 of ADC channel ADCx_IN6, converted by group injected only */
1578 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1579 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1580 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1581 of ADC channel ADCx_IN6, converted by either group regular or injected */
1582 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1583 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1584 of ADC channel ADCx_IN7, converted by group regular only */
1585 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1586 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1587 of ADC channel ADCx_IN7, converted by group injected only */
1588 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1589 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1590 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1591 of ADC channel ADCx_IN7, converted by either group regular or injected */
1592 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1593 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1594 of ADC channel ADCx_IN8, converted by group regular only */
1595 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1596 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1597 of ADC channel ADCx_IN8, converted by group injected only */
1598 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1599 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1600 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1601 of ADC channel ADCx_IN8, converted by either group regular or injected */
1602 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1603 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1604 of ADC channel ADCx_IN9, converted by group regular only */
1605 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1606 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1607 of ADC channel ADCx_IN9, converted by group injected only */
1608 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1609 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1610 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1611 of ADC channel ADCx_IN9, converted by either group regular or injected */
1612 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1613 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1614 of ADC channel ADCx_IN10, converted by group regular only */
1615 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1616 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1617 of ADC channel ADCx_IN10, converted by group injected only */
1618 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)\
1619 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1620 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1621 of ADC channel ADCx_IN10, converted by either group regular or injected */
1622 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1623 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1624 of ADC channel ADCx_IN11, converted by group regular only */
1625 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1626 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1627 of ADC channel ADCx_IN11, converted by group injected only */
1628 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1629 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1630 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1631 of ADC channel ADCx_IN11, converted by either group regular or injected */
1632 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1633 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1634 of ADC channel ADCx_IN12, converted by group regular only */
1635 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1636 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1637 of ADC channel ADCx_IN12, converted by group injected only */
1638 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1639 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1640 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1641 of ADC channel ADCx_IN12, converted by either group regular or injected */
1642 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1643 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1644 of ADC channel ADCx_IN13, converted by group regular only */
1645 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1646 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1647 of ADC channel ADCx_IN13, converted by group injected only */
1648 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1649 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1650 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1651 of ADC channel ADCx_IN13, converted by either group regular or injected */
1652 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1653 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1654 of ADC channel ADCx_IN14, converted by group regular only */
1655 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1656 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1657 of ADC channel ADCx_IN14, converted by group only */
1658 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1659 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1660 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1661 of ADC channel ADCx_IN14, converted by either group regular or injected */
1662 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1663 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1664 monitoring of ADC channel ADCx_IN15, converted by group regular only */
1665 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1666 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1667 of ADC channel ADCx_IN15, converted by group injected only */
1668 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1669 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1670 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1671 of ADC channel ADCx_IN15, converted by either group
1672 regular or injected */
1673 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1674 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1675 of ADC channel ADCx_IN16, converted by group regular only */
1676 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1677 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1678 of ADC channel ADCx_IN16, converted by group injected only */
1679 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1680 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1681 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1682 of ADC channel ADCx_IN16, converted by either group regular or injected */
1683 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1684 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1685 of ADC channel ADCx_IN17, converted by group regular only */
1686 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1687 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1688 of ADC channel ADCx_IN17, converted by group injected only */
1689 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1690 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1691 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1692 of ADC channel ADCx_IN17, converted by either group regular or injected */
1693 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1694 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1695 of ADC channel ADCx_IN18, converted by group regular only */
1696 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1697 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1698 of ADC channel ADCx_IN18, converted by group injected only */
1699 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1700 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1701 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1702 of ADC channel ADCx_IN18, converted by either group regular or injected */
1703 #define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) \
1704 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1705 of ADC channel ADCx_IN19, converted by group regular only */
1706 #define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) \
1707 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1708 of ADC channel ADCx_IN19, converted by group injected only */
1709 #define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) \
1710 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1711 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1712 of ADC channel ADCx_IN19, converted by either group regular or injected */
1713 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1714 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1715 of ADC internal channel connected to VrefInt: Internal voltage reference,
1716 converted by group regular only.
1717 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. */
1718 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1719 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1720 of ADC internal channel connected to VrefInt: Internal voltage reference,
1721 converted by group injected only.
1722 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. */
1723 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1724 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1725 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1726 of ADC internal channel connected to VrefInt: Internal voltage reference,
1727 converted by either group regular or injected.
1728 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. */
1729 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1730 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1731 of ADC internal channel connected to internal temperature sensor,
1732 converted by group regular only.
1733 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. */
1734 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1735 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1736 of ADC internal channel connected to internal temperature sensor,
1737 converted by group injected only.
1738 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. */
1739 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1740 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1741 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1742 of ADC internal channel connected to internal temperature sensor,
1743 converted by either group regular or injected.
1744 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC1. */
1745 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1746 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1747 of ADC internal channel connected to Vbat/4: Vbat voltage through
1748 a divider ladder of factor 1/4 to have channel voltage always below Vdda,
1749 converted by group regular only.
1750 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC2. */
1751 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1752 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1753 of ADC internal channel connected to Vbat/4: Vbat voltage through
1754 a divider ladder of factor 1/4 to have channel voltage always below Vdda,
1755 converted by group injected only.
1756 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC2. */
1757 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1758 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1759 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1760 of ADC internal channel connected to Vbat/4: Vbat voltage through
1761 a divider ladder of factor 1/4 to have channel voltage always below Vdda.
1762 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC2. */
1763 #define LL_ADC_AWD_CH_VDDCORE_REG ((LL_ADC_CHANNEL_VDDCORE & ADC_CHANNEL_ID_MASK) \
1764 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1765 of ADC internal channel connected to Vddcore, converted by group regular only
1766 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC2. */
1767 #define LL_ADC_AWD_CH_VDDCORE_INJ ((LL_ADC_CHANNEL_VDDCORE & ADC_CHANNEL_ID_MASK) \
1768 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1769 of ADC internal channel connected to Vddcore,
1770 converted by group injected only.
1771 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC2. */
1772 #define LL_ADC_AWD_CH_VDDCORE_REG_INJ ((LL_ADC_CHANNEL_VDDCORE & ADC_CHANNEL_ID_MASK) \
1773 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1774 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1775 of ADC internal channel connected to Vddcore,
1776 converted by either group regular or injected.
1777 On STM32H563xx/573xx, ADC channel available only on ADC instance: ADC2. */
1778
1779 /* Definitions for backward compatibility with legacy STM32 series */
1780 #define LL_ADC_AWD_CH_VCORE_REG LL_ADC_AWD_CH_VDDCORE_REG
1781 #define LL_ADC_AWD_CH_VCORE_INJ LL_ADC_AWD_CH_VDDCORE_INJ
1782 #define LL_ADC_AWD_CH_VCORE_REG_INJ LL_ADC_AWD_CH_VDDCORE_REG_INJ
1783 /**
1784 * @}
1785 */
1786
1787 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1788 * @{
1789 */
1790 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1) /*!< ADC analog watchdog threshold high */
1791 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
1792 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 \
1793 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low
1794 concatenated into the same data */
1795 /**
1796 * @}
1797 */
1798
1799 /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
1800 * @{
1801 */
1802 #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering,
1803 one out-of-window sample is needed to raise flag or interrupt */
1804 #define LL_ADC_AWD_FILTERING_2SAMPLES (ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 2
1805 out-of-window samples are needed to raise flag or interrupt */
1806 #define LL_ADC_AWD_FILTERING_3SAMPLES (ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 3
1807 consecutives out-of-window samples are needed to raise flag or interrupt */
1808 #define LL_ADC_AWD_FILTERING_4SAMPLES (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 4
1809 consecutives out-of-window samples are needed to raise flag or interrupt */
1810 #define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2) /*!< ADC analog watchdog 5
1811 consecutives out-of-window samples are needed to raise flag or interrupt */
1812 #define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 6
1813 consecutives out-of-window samples are needed to raise flag or interrupt */
1814 #define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 7
1815 consecutives out-of-window samples are needed to raise flag or interrupt */
1816 #define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \
1817 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 8
1818 consecutives out-of-window samples are needed to raise flag or interrupt */
1819 /**
1820 * @}
1821 */
1822
1823 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1824 * @{
1825 */
1826 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1827 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1828 ADC group regular. If group injected interrupts group regular:
1829 when ADC group injected is triggered, the oversampling on ADC group regular
1830 is temporary stopped and continued afterwards. */
1831 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1832 ADC group regular. If group injected interrupts group regular:
1833 when ADC group injected is triggered, the oversampling on ADC group regular
1834 is resumed from start (oversampler buffer reset). */
1835 #define LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of
1836 ADC group injected. */
1837 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1838 both ADC groups regular and injected. If group injected interrupting group
1839 regular: when ADC group injected is triggered, the oversampling on ADC group
1840 regular is resumed from start (oversampler buffer reset). */
1841 /**
1842 * @}
1843 */
1844
1845 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1846 * @{
1847 */
1848 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
1849 (all conversions of oversampling ratio are done from 1 trigger) */
1850 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous
1851 mode (each conversion of oversampling ratio needs a trigger) */
1852 /**
1853 * @}
1854 */
1855
1856 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1857 * @{
1858 */
1859 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2
1860 (sum of conversions data computed to result as oversampling conversion data
1861 (before potential shift) */
1862 #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4
1863 (sum of conversions data computed to result as oversampling conversion data
1864 (before potential shift) */
1865 #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8
1866 (sum of conversions data computed to result as oversampling conversion data
1867 (before potential shift) */
1868 #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
1869 (sum of conversions data computed to result as oversampling conversion data
1870 (before potential shift) */
1871 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32
1872 (sum of conversions data computed to result as oversampling conversion data
1873 (before potential shift) */
1874 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
1875 (sum of conversions data computed to result as oversampling conversion data
1876 (before potential shift) */
1877 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
1878 (sum of conversions data computed to result as oversampling conversion data
1879 (before potential shift) */
1880 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
1881 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256
1882 (sum of conversions data computed to result as oversampling conversion data
1883 (before potential shift) */
1884 /**
1885 * @}
1886 */
1887
1888 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
1889 * @{
1890 */
1891 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
1892 (sum of the ADC conversions data is not divided to result as oversampling
1893 conversion data) */
1894 #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
1895 (sum of the ADC conversions data (after OVS ratio) is divided by 2
1896 to result as oversampling conversion data) */
1897 #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
1898 (sum of the ADC conversions data (after OVS ratio) is divided by 4
1899 to result as oversampling conversion data) */
1900 #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
1901 (sum of the ADC conversions data (after OVS ratio) is divided by 8
1902 to result as oversampling conversion data) */
1903 #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
1904 (sum of the ADC conversions data (after OVS ratio) is divided by 16
1905 to result as oversampling conversion data) */
1906 #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
1907 (sum of the ADC conversions data (after OVS ratio) is divided by 32
1908 to result as oversampling conversion data) */
1909 #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
1910 (sum of the ADC conversions data (after OVS ratio) is divided by 64
1911 to result as oversampling conversion data) */
1912 #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
1913 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
1914 (sum of the ADC conversions data (after OVS ratio) is divided by 128
1915 to result as oversampling conversion data) */
1916 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
1917 (sum of the ADC conversions data (after OVS ratio) is divided by 256
1918 to result as oversampling conversion data) */
1919 /**
1920 * @}
1921 */
1922
1923 #if defined(ADC_MULTIMODE_SUPPORT)
1924 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1925 * @{
1926 */
1927 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC
1928 independent mode) */
1929 #define LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular
1930 simultaneous */
1931 #define LL_ADC_MULTI_DUAL_REG_INTERL (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \
1932 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1933 regular interleaved */
1934 #define LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
1935 simultaneous */
1936 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
1937 alternate trigger. Works only with external triggers (not SW start) */
1938 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1939 regular simultaneous + group injected simultaneous */
1940 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group
1941 regular simultaneous + group injected alternate trigger */
1942 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1943 regular interleaved + group injected simultaneous */
1944 /**
1945 * @}
1946 */
1947
1948 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1949 * @{
1950 */
1951 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular
1952 conversions are transferred by DMA: each ADC uses its own DMA channel,
1953 with its individual DMA transfer settings */
1954 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1) /*!< ADC multimode group regular
1955 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1956 ADC master), in limited mode (one shot mode): DMA transfer requests
1957 are stopped when number of DMA data transfers (number of ADC conversions)
1958 is reached. This ADC mode is intended to be used with DMA mode
1959 non-circular. Setting for ADC resolution of 12 and 10 bits */
1960 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
1961 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1962 ADC master), in limited mode (one shot mode): DMA transfer requests
1963 are stopped when number of DMA data transfers (number of ADC conversions)
1964 is reached. This ADC mode is intended to be used with DMA mode
1965 non-circular. Setting for ADC resolution of 8 and 6 bits */
1966 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1) /*!< ADC multimode group regular
1967 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1968 ADC master), in unlimited mode: DMA transfer requests are unlimited,
1969 whatever number of DMA data transferred (number of ADC conversions).
1970 This ADC mode is intended to be used with DMA mode circular.
1971 Setting for ADC resolution of 12 and 10 bits */
1972 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 \
1973 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
1974 conversions are transferred by DMA, one DMA channel for both ADC (DMA of
1975 ADC master), in unlimited mode: DMA transfer requests are unlimited,
1976 whatever number of DMA data transferred (number of ADC conversions).
1977 This ADC mode is intended to be used with DMA mode circular.
1978 Setting for ADC resolution of 8 and 6 bits */
1979 /**
1980 * @}
1981 */
1982
1983 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1984 * @{
1985 */
1986 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two
1987 sampling phases: 1 ADC clock cycle */
1988 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1989 sampling phases: 2 ADC clock cycles */
1990 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
1991 sampling phases: 3 ADC clock cycles */
1992 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1993 sampling phases: 4 ADC clock cycles */
1994 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2) /*!< ADC multimode delay between two
1995 sampling phases: 5 ADC clock cycles */
1996 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1997 sampling phases: 6 ADC clock cycles */
1998 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
1999 sampling phases: 7 ADC clock cycles */
2000 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \
2001 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
2002 sampling phases: 8 ADC clock cycles */
2003 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3) /*!< ADC multimode delay between two
2004 sampling phases: 9 ADC clock cycles */
2005 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
2006 sampling phases: 10 ADC clock cycles */
2007 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
2008 sampling phases: 11 ADC clock cycles */
2009 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \
2010 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
2011 sampling phases: 12 ADC clock cycles */
2012 /**
2013 * @}
2014 */
2015
2016 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
2017 * @{
2018 */
2019 #define LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
2020 instances: ADC master */
2021 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC
2022 instances: ADC slave */
2023 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \
2024 | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
2025 instances: both ADC master and ADC slave */
2026 /**
2027 * @}
2028 */
2029
2030 #endif /* ADC_MULTIMODE_SUPPORT */
2031
2032 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
2033 * @{
2034 */
2035 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
2036 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
2037 calibration parameters. This value is coded on 16 bits
2038 (to fit on signed word or double word) and corresponds
2039 to an inconsistent temperature value. */
2040 /**
2041 * @}
2042 */
2043
2044 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
2045 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
2046 * not timeout values.
2047 * For details on delays values, refer to descriptions in source code
2048 * above each literal definition.
2049 * @{
2050 */
2051
2052 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
2053 /* not timeout values. */
2054 /* Timeout values for ADC operations are dependent to device clock */
2055 /* configuration (system clock versus ADC clock), */
2056 /* and therefore must be defined in user application. */
2057 /* Indications for estimation of ADC timeout delays, for this */
2058 /* STM32 series: */
2059 /* - ADC calibration time: maximum delay is 112/fADC. */
2060 /* (refer to device datasheet, parameter "tCAL") */
2061 /* - ADC enable time: maximum delay is 1 conversion cycle. */
2062 /* (refer to device datasheet, parameter "tSTAB") */
2063 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
2064 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
2065 /* cycles */
2066 /* - ADC conversion time: duration depending on ADC clock and ADC */
2067 /* configuration. */
2068 /* (refer to device reference manual, section "Timing") */
2069
2070 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
2071 /* Delay set to maximum value (refer to device datasheet, */
2072 /* parameter "tADCVREG_STUP"). */
2073 /* Unit: us */
2074 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage
2075 regulator start-up time) */
2076
2077 /* Delay for internal voltage reference stabilization time. */
2078 /* Delay set to maximum value (refer to device datasheet, */
2079 /* parameter "tstart_vrefint"). */
2080 /* Unit: us */
2081 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
2082 time */
2083
2084 /* Delay for temperature sensor stabilization time. */
2085 /* Literal set to maximum value (refer to device datasheet, */
2086 /* parameter "tSTART"). */
2087 /* Unit: us */
2088 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
2089 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 26UL) /*!< Delay for temperature sensor buffer stabilization
2090 time (starting from ADC enable, refer to
2091 @ref LL_ADC_Enable()) */
2092
2093 /* Delay required between ADC end of calibration and ADC enable. */
2094 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
2095 /* are required between ADC end of calibration and ADC enable. */
2096 /* Wait time can be computed in user application by waiting for the */
2097 /* equivalent number of CPU cycles, by taking into account */
2098 /* ratio of CPU clock versus ADC clock prescalers. */
2099 /* Unit: ADC clock cycles. */
2100 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration
2101 and ADC enable */
2102
2103 /**
2104 * @}
2105 */
2106
2107 /**
2108 * @}
2109 */
2110
2111
2112 /* Exported macro ------------------------------------------------------------*/
2113 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
2114 * @{
2115 */
2116
2117 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
2118 * @{
2119 */
2120
2121 /**
2122 * @brief Write a value in ADC register
2123 * @param __INSTANCE__ ADC Instance
2124 * @param __REG__ Register to be written
2125 * @param __VALUE__ Value to be written in the register
2126 * @retval None
2127 */
2128 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2129
2130 /**
2131 * @brief Read a value in ADC register
2132 * @param __INSTANCE__ ADC Instance
2133 * @param __REG__ Register to be read
2134 * @retval Register value
2135 */
2136 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2137 /**
2138 * @}
2139 */
2140
2141 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
2142 * @{
2143 */
2144
2145 /**
2146 * @brief Helper macro to get ADC channel number in decimal format
2147 * from literals LL_ADC_CHANNEL_x.
2148 * @note Example:
2149 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
2150 * will return decimal number "4".
2151 * @note The input can be a value from functions where a channel
2152 * number is returned, either defined with number
2153 * or with bitfield (only one bit must be set).
2154 * @param __CHANNEL__ This parameter can be one of the following values:
2155 * @arg @ref LL_ADC_CHANNEL_0 (3)
2156 * @arg @ref LL_ADC_CHANNEL_1 (3)
2157 * @arg @ref LL_ADC_CHANNEL_2 (3)
2158 * @arg @ref LL_ADC_CHANNEL_3 (3)
2159 * @arg @ref LL_ADC_CHANNEL_4 (3)
2160 * @arg @ref LL_ADC_CHANNEL_5 (3)
2161 * @arg @ref LL_ADC_CHANNEL_6
2162 * @arg @ref LL_ADC_CHANNEL_7
2163 * @arg @ref LL_ADC_CHANNEL_8
2164 * @arg @ref LL_ADC_CHANNEL_9
2165 * @arg @ref LL_ADC_CHANNEL_10
2166 * @arg @ref LL_ADC_CHANNEL_11
2167 * @arg @ref LL_ADC_CHANNEL_12
2168 * @arg @ref LL_ADC_CHANNEL_13
2169 * @arg @ref LL_ADC_CHANNEL_14
2170 * @arg @ref LL_ADC_CHANNEL_15
2171 * @arg @ref LL_ADC_CHANNEL_16
2172 * @arg @ref LL_ADC_CHANNEL_17
2173 * @arg @ref LL_ADC_CHANNEL_18
2174 * @arg @ref LL_ADC_CHANNEL_19
2175 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2176 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2177 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
2178 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
2179 *
2180 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
2181 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
2182 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
2183 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
2184 * @retval Value between Min_Data=0 and Max_Data=18
2185 */
2186 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
2187 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
2188 ( \
2189 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
2190 ) \
2191 : \
2192 ( \
2193 (uint32_t)POSITION_VAL((__CHANNEL__)) \
2194 ) \
2195 )
2196
2197 /**
2198 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
2199 * from number in decimal format.
2200 * @note Example:
2201 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
2202 * will return a data equivalent to "LL_ADC_CHANNEL_4".
2203 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
2204 * @retval Returned value can be one of the following values:
2205 * @arg @ref LL_ADC_CHANNEL_0 (3)
2206 * @arg @ref LL_ADC_CHANNEL_1 (3)
2207 * @arg @ref LL_ADC_CHANNEL_2 (3)
2208 * @arg @ref LL_ADC_CHANNEL_3 (3)
2209 * @arg @ref LL_ADC_CHANNEL_4 (3)
2210 * @arg @ref LL_ADC_CHANNEL_5 (3)
2211 * @arg @ref LL_ADC_CHANNEL_6
2212 * @arg @ref LL_ADC_CHANNEL_7
2213 * @arg @ref LL_ADC_CHANNEL_8
2214 * @arg @ref LL_ADC_CHANNEL_9
2215 * @arg @ref LL_ADC_CHANNEL_10
2216 * @arg @ref LL_ADC_CHANNEL_11
2217 * @arg @ref LL_ADC_CHANNEL_12
2218 * @arg @ref LL_ADC_CHANNEL_13
2219 * @arg @ref LL_ADC_CHANNEL_14
2220 * @arg @ref LL_ADC_CHANNEL_15
2221 * @arg @ref LL_ADC_CHANNEL_16
2222 * @arg @ref LL_ADC_CHANNEL_17
2223 * @arg @ref LL_ADC_CHANNEL_18
2224 * @arg @ref LL_ADC_CHANNEL_19
2225 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(4)
2226 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(4)
2227 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(4)
2228 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(4)
2229 *
2230 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
2231 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
2232 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
2233 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
2234 * (4) For ADC channel read back from ADC register,
2235 * comparison with internal channel parameter to be done
2236 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2237 */
2238 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
2239 (((__DECIMAL_NB__) <= 9UL) ? \
2240 ( \
2241 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2242 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2243 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
2244 ) \
2245 : \
2246 ( \
2247 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2248 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2249 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
2250 ) \
2251 )
2252
2253 /**
2254 * @brief Helper macro to determine whether the selected channel
2255 * corresponds to literal definitions of driver.
2256 * @note The different literal definitions of ADC channels are:
2257 * - ADC internal channel:
2258 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
2259 * - ADC external channel (channel connected to a GPIO pin):
2260 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
2261 * @note The channel parameter must be a value defined from literal
2262 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2263 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2264 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
2265 * must not be a value from functions where a channel number is
2266 * returned from ADC registers,
2267 * because internal and external channels share the same channel
2268 * number in ADC registers. The differentiation is made only with
2269 * parameters definitions of driver.
2270 * @param __CHANNEL__ This parameter can be one of the following values:
2271 * @arg @ref LL_ADC_CHANNEL_0 (3)
2272 * @arg @ref LL_ADC_CHANNEL_1 (3)
2273 * @arg @ref LL_ADC_CHANNEL_2 (3)
2274 * @arg @ref LL_ADC_CHANNEL_3 (3)
2275 * @arg @ref LL_ADC_CHANNEL_4 (3)
2276 * @arg @ref LL_ADC_CHANNEL_5 (3)
2277 * @arg @ref LL_ADC_CHANNEL_6
2278 * @arg @ref LL_ADC_CHANNEL_7
2279 * @arg @ref LL_ADC_CHANNEL_8
2280 * @arg @ref LL_ADC_CHANNEL_9
2281 * @arg @ref LL_ADC_CHANNEL_10
2282 * @arg @ref LL_ADC_CHANNEL_11
2283 * @arg @ref LL_ADC_CHANNEL_12
2284 * @arg @ref LL_ADC_CHANNEL_13
2285 * @arg @ref LL_ADC_CHANNEL_14
2286 * @arg @ref LL_ADC_CHANNEL_15
2287 * @arg @ref LL_ADC_CHANNEL_16
2288 * @arg @ref LL_ADC_CHANNEL_17
2289 * @arg @ref LL_ADC_CHANNEL_18
2290 * @arg @ref LL_ADC_CHANNEL_19
2291 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2292 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2293 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
2294 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
2295 *
2296 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
2297 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
2298 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
2299 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
2300 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
2301 connected to a GPIO pin).
2302 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
2303 */
2304 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
2305 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
2306
2307 /**
2308 * @brief Helper macro to convert a channel defined from parameter
2309 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2310 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2311 * to its equivalent parameter definition of a ADC external channel
2312 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
2313 * @note The channel parameter can be, additionally to a value
2314 * defined from parameter definition of a ADC internal channel
2315 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
2316 * a value defined from parameter definition of
2317 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2318 * or a value from functions where a channel number is returned
2319 * from ADC registers.
2320 * @param __CHANNEL__ This parameter can be one of the following values:
2321 * @arg @ref LL_ADC_CHANNEL_0 (3)
2322 * @arg @ref LL_ADC_CHANNEL_1 (3)
2323 * @arg @ref LL_ADC_CHANNEL_2 (3)
2324 * @arg @ref LL_ADC_CHANNEL_3 (3)
2325 * @arg @ref LL_ADC_CHANNEL_4 (3)
2326 * @arg @ref LL_ADC_CHANNEL_5 (3)
2327 * @arg @ref LL_ADC_CHANNEL_6
2328 * @arg @ref LL_ADC_CHANNEL_7
2329 * @arg @ref LL_ADC_CHANNEL_8
2330 * @arg @ref LL_ADC_CHANNEL_9
2331 * @arg @ref LL_ADC_CHANNEL_10
2332 * @arg @ref LL_ADC_CHANNEL_11
2333 * @arg @ref LL_ADC_CHANNEL_12
2334 * @arg @ref LL_ADC_CHANNEL_13
2335 * @arg @ref LL_ADC_CHANNEL_14
2336 * @arg @ref LL_ADC_CHANNEL_15
2337 * @arg @ref LL_ADC_CHANNEL_16
2338 * @arg @ref LL_ADC_CHANNEL_17
2339 * @arg @ref LL_ADC_CHANNEL_18
2340 * @arg @ref LL_ADC_CHANNEL_19
2341 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2342 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2343 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
2344 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
2345 *
2346 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
2347 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
2348 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
2349 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
2350 * @retval Returned value can be one of the following values:
2351 * @arg @ref LL_ADC_CHANNEL_0
2352 * @arg @ref LL_ADC_CHANNEL_1
2353 * @arg @ref LL_ADC_CHANNEL_2
2354 * @arg @ref LL_ADC_CHANNEL_3
2355 * @arg @ref LL_ADC_CHANNEL_4
2356 * @arg @ref LL_ADC_CHANNEL_5
2357 * @arg @ref LL_ADC_CHANNEL_6
2358 * @arg @ref LL_ADC_CHANNEL_7
2359 * @arg @ref LL_ADC_CHANNEL_8
2360 * @arg @ref LL_ADC_CHANNEL_9
2361 * @arg @ref LL_ADC_CHANNEL_10
2362 * @arg @ref LL_ADC_CHANNEL_11
2363 * @arg @ref LL_ADC_CHANNEL_12
2364 * @arg @ref LL_ADC_CHANNEL_13
2365 * @arg @ref LL_ADC_CHANNEL_14
2366 * @arg @ref LL_ADC_CHANNEL_15
2367 * @arg @ref LL_ADC_CHANNEL_16
2368 * @arg @ref LL_ADC_CHANNEL_17
2369 * @arg @ref LL_ADC_CHANNEL_18
2370 * @arg @ref LL_ADC_CHANNEL_19
2371 */
2372 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
2373 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
2374
2375 /**
2376 * @brief Helper macro to determine whether the internal channel
2377 * selected is available on the ADC instance selected.
2378 * @note The channel parameter must be a value defined from parameter
2379 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2380 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2381 * must not be a value defined from parameter definition of
2382 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2383 * or a value from functions where a channel number is
2384 * returned from ADC registers,
2385 * because internal and external channels share the same channel
2386 * number in ADC registers. The differentiation is made only with
2387 * parameters definitions of driver.
2388 * @param __ADC_INSTANCE__ ADC instance
2389 * @param __CHANNEL__ This parameter can be one of the following values:
2390 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2391 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2392 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
2393 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
2394 *
2395 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.
2396 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.
2397 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
2398 * Value "1" if the internal channel selected is available on the ADC instance selected.
2399 */
2400 #if defined(ADC2)
2401 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2402 ((((__ADC_INSTANCE__) == ADC1) \
2403 &&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR ) || \
2404 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)) \
2405 ) \
2406 || \
2407 (((__ADC_INSTANCE__) == ADC2) \
2408 &&(((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2409 ((__CHANNEL__) == LL_ADC_CHANNEL_VDDCORE)) \
2410 ) \
2411 )
2412 #else
2413 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2414 (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2415 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
2416 ((__CHANNEL__) == LL_ADC_CHANNEL_VDDCORE) || \
2417 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
2418 )
2419 #endif /* ADC2 */
2420
2421 /**
2422 * @brief Helper macro to define ADC analog watchdog parameter:
2423 * define a single channel to monitor with analog watchdog
2424 * from sequencer channel and groups definition.
2425 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2426 * Example:
2427 * LL_ADC_SetAnalogWDMonitChannels(
2428 * ADC1, LL_ADC_AWD1,
2429 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
2430 * @param __CHANNEL__ This parameter can be one of the following values:
2431 * @arg @ref LL_ADC_CHANNEL_0 (3)
2432 * @arg @ref LL_ADC_CHANNEL_1 (3)
2433 * @arg @ref LL_ADC_CHANNEL_2 (3)
2434 * @arg @ref LL_ADC_CHANNEL_3 (3)
2435 * @arg @ref LL_ADC_CHANNEL_4 (3)
2436 * @arg @ref LL_ADC_CHANNEL_5 (3)
2437 * @arg @ref LL_ADC_CHANNEL_6
2438 * @arg @ref LL_ADC_CHANNEL_7
2439 * @arg @ref LL_ADC_CHANNEL_8
2440 * @arg @ref LL_ADC_CHANNEL_9
2441 * @arg @ref LL_ADC_CHANNEL_10
2442 * @arg @ref LL_ADC_CHANNEL_11
2443 * @arg @ref LL_ADC_CHANNEL_12
2444 * @arg @ref LL_ADC_CHANNEL_13
2445 * @arg @ref LL_ADC_CHANNEL_14
2446 * @arg @ref LL_ADC_CHANNEL_15
2447 * @arg @ref LL_ADC_CHANNEL_16
2448 * @arg @ref LL_ADC_CHANNEL_17
2449 * @arg @ref LL_ADC_CHANNEL_18
2450 * @arg @ref LL_ADC_CHANNEL_19
2451 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(4)
2452 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(4)
2453 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(4)
2454 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(4)
2455 *
2456 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
2457 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
2458 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
2459 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
2460 * (4) For ADC channel read back from ADC register,
2461 * comparison with internal channel parameter to be done
2462 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2463 * @param __GROUP__ This parameter can be one of the following values:
2464 * @arg @ref LL_ADC_GROUP_REGULAR
2465 * @arg @ref LL_ADC_GROUP_INJECTED
2466 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
2467 * @retval Returned value can be one of the following values:
2468 * @arg @ref LL_ADC_AWD_DISABLE
2469 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
2470 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
2471 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
2472 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
2473 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
2474 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
2475 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
2476 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
2477 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
2478 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
2479 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
2480 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
2481 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
2482 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
2483 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
2484 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
2485 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
2486 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
2487 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
2488 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
2489 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
2490 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
2491 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
2492 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
2493 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
2494 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
2495 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2496 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
2497 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
2498 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2499 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2500 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2501 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2502 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2503 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2504 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2505 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2506 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2507 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2508 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2509 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2510 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2511 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2512 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2513 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2514 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2515 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2516 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2517 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2518 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2519 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2520 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2521 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2522 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2523 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2524 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2525 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2526 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2527 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2528 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2529 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
2530 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
2531 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
2532 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
2533 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
2534 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
2535 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
2536 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
2537 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
2538 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(2)
2539 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(2)
2540 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (2)
2541 * @arg @ref LL_ADC_AWD_CH_VDDCORE_REG (0)(2)
2542 * @arg @ref LL_ADC_AWD_CH_VDDCORE_INJ (0)(2)
2543 * @arg @ref LL_ADC_AWD_CH_VDDCORE_REG_INJ (2)
2544 *
2545 * (0) On STM32H5, parameter available only on analog watchdog number: AWD1.\n
2546 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.
2547 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.
2548 */
2549 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2550 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2551 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2552 : \
2553 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2554 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2555 : \
2556 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2557 )
2558
2559 /**
2560 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2561 * or low in function of ADC resolution, when ADC resolution is
2562 * different of 12 bits.
2563 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
2564 * or @ref LL_ADC_SetAnalogWDThresholds().
2565 * Example, with a ADC resolution of 8 bits, to set the value of
2566 * analog watchdog threshold high (on 8 bits):
2567 * LL_ADC_SetAnalogWDThresholds
2568 * (< ADCx param >,
2569 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
2570 * );
2571 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2572 * @arg @ref LL_ADC_RESOLUTION_12B
2573 * @arg @ref LL_ADC_RESOLUTION_10B
2574 * @arg @ref LL_ADC_RESOLUTION_8B
2575 * @arg @ref LL_ADC_RESOLUTION_6B
2576 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
2577 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2578 */
2579 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2580 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2581
2582 /**
2583 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2584 * or low in function of ADC resolution, when ADC resolution is
2585 * different of 12 bits.
2586 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2587 * Example, with a ADC resolution of 8 bits, to get the value of
2588 * analog watchdog threshold high (on 8 bits):
2589 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2590 * (LL_ADC_RESOLUTION_8B,
2591 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2592 * );
2593 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2594 * @arg @ref LL_ADC_RESOLUTION_12B
2595 * @arg @ref LL_ADC_RESOLUTION_10B
2596 * @arg @ref LL_ADC_RESOLUTION_8B
2597 * @arg @ref LL_ADC_RESOLUTION_6B
2598 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
2599 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2600 */
2601 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
2602 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2603
2604 /**
2605 * @brief Helper macro to get the ADC analog watchdog threshold high
2606 * or low from raw value containing both thresholds concatenated.
2607 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2608 * Example, to get analog watchdog threshold high from the register raw value:
2609 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
2610 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
2611 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
2612 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
2613 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2614 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2615 */
2616 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
2617 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
2618 & LL_ADC_AWD_THRESHOLD_LOW)
2619
2620 /**
2621 * @brief Helper macro to set the ADC calibration value with both single ended
2622 * and differential modes calibration factors concatenated.
2623 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2624 * Example, to set calibration factors single ended to 0x55
2625 * and differential ended to 0x2A:
2626 * LL_ADC_SetCalibrationFactor(
2627 * ADC1,
2628 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2629 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2630 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2631 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2632 */
2633 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2634 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2635
2636 #if defined(ADC_MULTIMODE_SUPPORT)
2637 /**
2638 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2639 * or ADC slave from raw value with both ADC conversion data concatenated.
2640 * @note This macro is intended to be used when multimode transfer by DMA
2641 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2642 * In this case the transferred data need to processed with this macro
2643 * to separate the conversion data of ADC master and ADC slave.
2644 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2645 * @arg @ref LL_ADC_MULTI_MASTER
2646 * @arg @ref LL_ADC_MULTI_SLAVE
2647 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2648 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2649 */
2650 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2651 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2652 #endif /* ADC_MULTIMODE_SUPPORT */
2653
2654 #if defined(ADC_MULTIMODE_SUPPORT)
2655 /**
2656 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2657 * it has a dependence in multimode (ADC master of the corresponding
2658 * ADC common instance).
2659 * @note In case of device with multimode available and a mix of
2660 * ADC instances compliant and not compliant with multimode feature,
2661 * ADC instances not compliant with multimode feature are
2662 * considered as master instances (do not depend to
2663 * any other ADC instance).
2664 * @param __ADCx__ ADC instance
2665 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2666 */
2667 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2668 ( ( ((__ADCx__) == ADC2) \
2669 )? \
2670 (ADC1) \
2671 : \
2672 (__ADCx__) \
2673 )
2674 #endif /* ADC_MULTIMODE_SUPPORT */
2675
2676 /**
2677 * @brief Helper macro to select the ADC common instance
2678 * to which is belonging the selected ADC instance.
2679 * @note ADC common register instance can be used for:
2680 * - Set parameters common to several ADC instances
2681 * - Multimode (for devices with several ADC instances)
2682 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2683 * @param __ADCx__ ADC instance
2684 * @retval ADC common register instance
2685 */
2686 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
2687 /**
2688 * @brief Helper macro to check if all ADC instances sharing the same
2689 * ADC common instance are disabled.
2690 * @note This check is required by functions with setting conditioned to
2691 * ADC state:
2692 * All ADC instances of the ADC common group must be disabled.
2693 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2694 * @note On devices with only 1 ADC common instance, parameter of this macro
2695 * is useless and can be ignored (parameter kept for compatibility
2696 * with devices featuring several ADC common instances).
2697 * @param __ADCXY_COMMON__ ADC common instance
2698 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2699 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2700 * are disabled.
2701 * Value "1" if at least one ADC instance sharing the same ADC common instance
2702 * is enabled.
2703 */
2704 #if defined(ADC2)
2705 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2706 (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
2707 #else
2708 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) (LL_ADC_IsEnabled(ADC1))
2709 #endif /* ADC2 */
2710
2711 /**
2712 * @brief Helper macro to define the ADC conversion data full-scale digital
2713 * value corresponding to the selected ADC resolution.
2714 * @note ADC conversion data full-scale corresponds to voltage range
2715 * determined by analog voltage references Vref+ and Vref-
2716 * (refer to reference manual).
2717 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2718 * @arg @ref LL_ADC_RESOLUTION_12B
2719 * @arg @ref LL_ADC_RESOLUTION_10B
2720 * @arg @ref LL_ADC_RESOLUTION_8B
2721 * @arg @ref LL_ADC_RESOLUTION_6B
2722 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2723 */
2724 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2725 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2726
2727 /**
2728 * @brief Helper macro to convert the ADC conversion data from
2729 * a resolution to another resolution.
2730 * @param __DATA__ ADC conversion data to be converted
2731 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2732 * This parameter can be one of the following values:
2733 * @arg @ref LL_ADC_RESOLUTION_12B
2734 * @arg @ref LL_ADC_RESOLUTION_10B
2735 * @arg @ref LL_ADC_RESOLUTION_8B
2736 * @arg @ref LL_ADC_RESOLUTION_6B
2737 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2738 * This parameter can be one of the following values:
2739 * @arg @ref LL_ADC_RESOLUTION_12B
2740 * @arg @ref LL_ADC_RESOLUTION_10B
2741 * @arg @ref LL_ADC_RESOLUTION_8B
2742 * @arg @ref LL_ADC_RESOLUTION_6B
2743 * @retval ADC conversion data to the requested resolution
2744 */
2745 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2746 __ADC_RESOLUTION_CURRENT__,\
2747 __ADC_RESOLUTION_TARGET__) \
2748 (((__DATA__) \
2749 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2750 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2751 )
2752
2753 /**
2754 * @brief Helper macro to calculate the voltage (unit: mVolt)
2755 * corresponding to a ADC conversion data (unit: digital value).
2756 * @note Analog reference voltage (Vref+) must be either known from
2757 * user board environment or can be calculated using ADC measurement
2758 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2759 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2760 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2761 * (unit: digital value).
2762 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2763 * @arg @ref LL_ADC_RESOLUTION_12B
2764 * @arg @ref LL_ADC_RESOLUTION_10B
2765 * @arg @ref LL_ADC_RESOLUTION_8B
2766 * @arg @ref LL_ADC_RESOLUTION_6B
2767 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2768 */
2769 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2770 __ADC_DATA__,\
2771 __ADC_RESOLUTION__) \
2772 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2773 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2774 )
2775
2776 /**
2777 * @brief Helper macro to calculate the voltage (unit: mVolt)
2778 * corresponding to a ADC conversion data (unit: digital value) in
2779 * differential ended mode.
2780 * @note ADC data from ADC data register is unsigned and centered around
2781 * middle code in. Converted voltage can be positive or negative
2782 * depending on differential input voltages.
2783 * @note Analog reference voltage (Vref+) must be either known from
2784 * user board environment or can be calculated using ADC measurement
2785 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2786 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2787 * @param __ADC_DATA__ ADC conversion data (unit: digital value).
2788 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2789 * @arg @ref LL_ADC_RESOLUTION_12B
2790 * @arg @ref LL_ADC_RESOLUTION_10B
2791 * @arg @ref LL_ADC_RESOLUTION_8B
2792 * @arg @ref LL_ADC_RESOLUTION_6B
2793 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2794 */
2795 #define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2796 __ADC_DATA__,\
2797 __ADC_RESOLUTION__)\
2798 ((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\
2799 / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\
2800 - (int32_t)(__VREFANALOG_VOLTAGE__))
2801
2802 /**
2803 * @brief Helper macro to calculate analog reference voltage (Vref+)
2804 * (unit: mVolt) from ADC conversion data of internal voltage
2805 * reference VrefInt.
2806 * @note Computation is using VrefInt calibration value
2807 * stored in system memory for each device during production.
2808 * @note This voltage depends on user board environment: voltage level
2809 * connected to pin Vref+.
2810 * On devices with small package, the pin Vref+ is not present
2811 * and internally bonded to pin Vdda.
2812 * @note On this STM32 series, calibration data of internal voltage reference
2813 * VrefInt corresponds to a resolution of 12 bits,
2814 * this is the recommended ADC resolution to convert voltage of
2815 * internal voltage reference VrefInt.
2816 * Otherwise, this macro performs the processing to scale
2817 * ADC conversion data to 12 bits.
2818 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2819 * of internal voltage reference VrefInt (unit: digital value).
2820 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2821 * @arg @ref LL_ADC_RESOLUTION_12B
2822 * @arg @ref LL_ADC_RESOLUTION_10B
2823 * @arg @ref LL_ADC_RESOLUTION_8B
2824 * @arg @ref LL_ADC_RESOLUTION_6B
2825 * @retval Analog reference voltage (unit: mV)
2826 */
2827 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2828 __ADC_RESOLUTION__) \
2829 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2830 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2831 (__ADC_RESOLUTION__), \
2832 LL_ADC_RESOLUTION_12B) \
2833 )
2834
2835 /**
2836 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2837 * from ADC conversion data of internal temperature sensor.
2838 * @note Computation is using temperature sensor calibration values
2839 * stored in system memory for each device during production.
2840 * @note Calculation formula:
2841 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2842 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2843 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2844 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2845 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2846 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2847 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2848 * TEMP_DEGC_CAL1 (calibrated in factory)
2849 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2850 * TEMP_DEGC_CAL2 (calibrated in factory)
2851 * Caution: Calculation relevancy under reserve that calibration
2852 * parameters are correct (address and data).
2853 * To calculate temperature using temperature sensor
2854 * datasheet typical values (generic values less, therefore
2855 * less accurate than calibrated values),
2856 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2857 * @note As calculation input, the analog reference voltage (Vref+) must be
2858 * defined as it impacts the ADC LSB equivalent voltage.
2859 * @note Analog reference voltage (Vref+) must be either known from
2860 * user board environment or can be calculated using ADC measurement
2861 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2862 * @note On this STM32 series, calibration data of temperature sensor
2863 * corresponds to a resolution of 12 bits,
2864 * this is the recommended ADC resolution to convert voltage of
2865 * temperature sensor.
2866 * Otherwise, this macro performs the processing to scale
2867 * ADC conversion data to 12 bits.
2868 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2869 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2870 * temperature sensor (unit: digital value).
2871 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2872 * sensor voltage has been measured.
2873 * This parameter can be one of the following values:
2874 * @arg @ref LL_ADC_RESOLUTION_12B
2875 * @arg @ref LL_ADC_RESOLUTION_10B
2876 * @arg @ref LL_ADC_RESOLUTION_8B
2877 * @arg @ref LL_ADC_RESOLUTION_6B
2878 * @retval Temperature (unit: degree Celsius)
2879 * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
2880 */
2881 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2882 __TEMPSENSOR_ADC_DATA__,\
2883 __ADC_RESOLUTION__)\
2884 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \
2885 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2886 (__ADC_RESOLUTION__), \
2887 LL_ADC_RESOLUTION_12B) \
2888 * (__VREFANALOG_VOLTAGE__)) \
2889 / TEMPSENSOR_CAL_VREFANALOG) \
2890 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2891 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2892 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2893 ) + TEMPSENSOR_CAL1_TEMP \
2894 ) \
2895 : \
2896 ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \
2897 )
2898
2899 /**
2900 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2901 * from ADC conversion data of internal temperature sensor.
2902 * @note Computation is using temperature sensor typical values
2903 * (refer to device datasheet).
2904 * @note Calculation formula:
2905 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2906 * / Avg_Slope + CALx_TEMP
2907 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2908 * (unit: digital value)
2909 * Avg_Slope = temperature sensor slope
2910 * (unit: uV/Degree Celsius)
2911 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2912 * temperature CALx_TEMP (unit: mV)
2913 * Caution: Calculation relevancy under reserve the temperature sensor
2914 * of the current device has characteristics in line with
2915 * datasheet typical values.
2916 * If temperature sensor calibration values are available on
2917 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2918 * temperature calculation will be more accurate using
2919 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2920 * @note As calculation input, the analog reference voltage (Vref+) must be
2921 * defined as it impacts the ADC LSB equivalent voltage.
2922 * @note Analog reference voltage (Vref+) must be either known from
2923 * user board environment or can be calculated using ADC measurement
2924 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2925 * @note ADC measurement data must correspond to a resolution of 12 bits
2926 * (full scale digital value 4095). If not the case, the data must be
2927 * preliminarily rescaled to an equivalent resolution of 12 bits.
2928 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
2929 * (unit: uV/DegCelsius).
2930 * On STM32H5, refer to device datasheet parameter "Avg_Slope".
2931 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
2932 * (at temperature and Vref+ defined in parameters below) (unit: mV).
2933 * On this STM32 series, refer to datasheet parameter "V30" (corresponding
2934 * to TS_CAL1).
2935 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
2936 * (see parameter above) is corresponding (unit: mV)
2937 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
2938 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2939 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2940 * This parameter can be one of the following values:
2941 * @arg @ref LL_ADC_RESOLUTION_12B
2942 * @arg @ref LL_ADC_RESOLUTION_10B
2943 * @arg @ref LL_ADC_RESOLUTION_8B
2944 * @arg @ref LL_ADC_RESOLUTION_6B
2945 * @retval Temperature (unit: degree Celsius)
2946 */
2947 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2948 __TEMPSENSOR_TYP_CALX_V__,\
2949 __TEMPSENSOR_CALX_TEMP__,\
2950 __VREFANALOG_VOLTAGE__,\
2951 __TEMPSENSOR_ADC_DATA__,\
2952 __ADC_RESOLUTION__) \
2953 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2954 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2955 * 1000UL) \
2956 - \
2957 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2958 * 1000UL) \
2959 ) \
2960 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2961 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2962 )
2963
2964 /**
2965 * @}
2966 */
2967
2968 /**
2969 * @}
2970 */
2971
2972
2973 /* Exported functions --------------------------------------------------------*/
2974 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2975 * @{
2976 */
2977
2978 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2979 * @{
2980 */
2981 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2982 /* configuration of ADC instance, groups and multimode (if available): */
2983 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2984
2985 /**
2986 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2987 * ADC register address from ADC instance and a list of ADC registers
2988 * intended to be used (most commonly) with DMA transfer.
2989 * @note These ADC registers are data registers:
2990 * when ADC conversion data is available in ADC data registers,
2991 * ADC generates a DMA transfer request.
2992 * @note This macro is intended to be used with LL DMA driver, refer to
2993 * function "LL_DMA_ConfigAddresses()".
2994 * Example:
2995 * LL_DMA_ConfigAddresses(DMA1,
2996 * LL_DMA_CHANNEL_1,
2997 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2998 * (uint32_t)&< array or variable >,
2999 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
3000 * @note For devices with several ADC: in multimode, some devices
3001 * use a different data register outside of ADC instance scope
3002 * (common data register). This macro manages this register difference,
3003 * only ADC instance has to be set as parameter.
3004 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
3005 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
3006 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
3007 * @param ADCx ADC instance
3008 * @param Register This parameter can be one of the following values:
3009 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
3010 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
3011 *
3012 * (1) Available on devices with several ADC instances.
3013 * @retval ADC register address
3014 */
3015 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)3016 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
3017 {
3018 uint32_t data_reg_addr;
3019
3020 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
3021 {
3022 /* Retrieve address of register DR */
3023 data_reg_addr = (uint32_t) &(ADCx->DR);
3024 }
3025 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
3026 {
3027 /* Retrieve address of register CDR */
3028 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
3029 }
3030
3031 return data_reg_addr;
3032 }
3033 #else
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)3034 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
3035 {
3036 /* Prevent unused argument(s) compilation warning */
3037 (void)(Register);
3038
3039 /* Retrieve address of register DR */
3040 return (uint32_t) &(ADCx->DR);
3041 }
3042 #endif /* ADC_MULTIMODE_SUPPORT */
3043
3044 /**
3045 * @}
3046 */
3047
3048 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
3049 * ADC instances
3050 * @{
3051 */
3052
3053 /**
3054 * @brief Set parameter common to several ADC: Clock source and prescaler.
3055 * @note On this STM32 series, if ADC group injected is used, some
3056 * clock ratio constraints between ADC clock and AHB clock
3057 * must be respected.
3058 * Refer to reference manual.
3059 * @note On this STM32 series, setting of this feature is conditioned to
3060 * ADC state:
3061 * All ADC instances of the ADC common group must be disabled.
3062 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3063 * ADC instance or by using helper macro helper macro
3064 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3065 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
3066 * CCR PRESC LL_ADC_SetCommonClock
3067 * @param ADCxy_COMMON ADC common instance
3068 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3069 * @param CommonClock This parameter can be one of the following values:
3070 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
3071 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
3072 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
3073 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
3074 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
3075 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
3076 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
3077 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
3078 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
3079 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
3080 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
3081 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
3082 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
3083 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
3084 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3085 * @retval None
3086 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)3087 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
3088 {
3089 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
3090 }
3091
3092 /**
3093 * @brief Get parameter common to several ADC: Clock source and prescaler.
3094 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
3095 * CCR PRESC LL_ADC_GetCommonClock
3096 * @param ADCxy_COMMON ADC common instance
3097 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3098 * @retval Returned value can be one of the following values:
3099 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
3100 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
3101 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
3102 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
3103 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
3104 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
3105 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
3106 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
3107 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
3108 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
3109 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
3110 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
3111 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
3112 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
3113 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3114 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)3115 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
3116 {
3117 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
3118 }
3119
3120 /**
3121 * @brief Set parameter common to several ADC: measurement path to
3122 * internal channels (VrefInt, temperature sensor, ...).
3123 * Configure all paths (overwrite current configuration).
3124 * @note One or several values can be selected.
3125 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3126 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3127 * The values not selected are removed from configuration.
3128 * @note Stabilization time of measurement path to internal channel:
3129 * After enabling internal paths, before starting ADC conversion,
3130 * a delay is required for internal voltage reference and
3131 * temperature sensor stabilization time.
3132 * Refer to device datasheet.
3133 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3134 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3135 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
3136 * @note ADC internal channel sampling time constraint:
3137 * For ADC conversion of internal channels,
3138 * a sampling time minimum value is required.
3139 * Refer to device datasheet.
3140 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
3141 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
3142 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
3143 * @param ADCxy_COMMON ADC common instance
3144 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3145 * @param PathInternal This parameter can be a combination of the following values:
3146 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3147 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3148 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3149 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3150 * @retval None
3151 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3152 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3153 {
3154 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
3155 }
3156
3157 /**
3158 * @brief Set parameter common to several ADC: measurement path to
3159 * internal channels (VrefInt, temperature sensor, ...).
3160 * Add paths to the current configuration.
3161 * @note One or several values can be selected.
3162 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3163 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3164 * @note Stabilization time of measurement path to internal channel:
3165 * After enabling internal paths, before starting ADC conversion,
3166 * a delay is required for internal voltage reference and
3167 * temperature sensor stabilization time.
3168 * Refer to device datasheet.
3169 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3170 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3171 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
3172 * @note ADC internal channel sampling time constraint:
3173 * For ADC conversion of internal channels,
3174 * a sampling time minimum value is required.
3175 * Refer to device datasheet.
3176 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
3177 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
3178 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
3179 * @param ADCxy_COMMON ADC common instance
3180 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3181 * @param PathInternal This parameter can be a combination of the following values:
3182 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3183 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3184 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3185 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3186 * @retval None
3187 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3188 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3189 {
3190 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
3191 }
3192
3193 /**
3194 * @brief Set parameter common to several ADC: measurement path to
3195 * internal channels (VrefInt, temperature sensor, ...).
3196 * Remove paths to the current configuration.
3197 * @note One or several values can be selected.
3198 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3199 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3200 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
3201 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
3202 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
3203 * @param ADCxy_COMMON ADC common instance
3204 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3205 * @param PathInternal This parameter can be a combination of the following values:
3206 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3207 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3208 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3209 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3210 * @retval None
3211 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3212 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3213 {
3214 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
3215 }
3216
3217 /**
3218 * @brief Get parameter common to several ADC: measurement path to internal
3219 * channels (VrefInt, temperature sensor, ...).
3220 * @note One or several values can be selected.
3221 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3222 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3223 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
3224 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
3225 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
3226 * @param ADCxy_COMMON ADC common instance
3227 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3228 * @retval Returned value can be a combination of the following values:
3229 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3230 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3231 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3232 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3233 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)3234 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
3235 {
3236 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
3237 }
3238
3239 /**
3240 * @}
3241 */
3242
3243 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
3244 * @{
3245 */
3246
3247 #if defined (ADC2)
3248 /**
3249 * @brief Enable VddCore (internal digital core voltage) channel.
3250 * @note On this STM32 series, VddCore channel is controlled via a specific register.
3251 * @note On this STM32 series, VddCore channel is on ADC2 instance only.
3252 * @rmtoll OR OP0 LL_ADC_EnableChannelVDDcore
3253 * @param ADCx ADC instance
3254 * @retval None
3255 */
LL_ADC_EnableChannelVDDcore(ADC_TypeDef * ADCx)3256 __STATIC_INLINE void LL_ADC_EnableChannelVDDcore(ADC_TypeDef *ADCx)
3257 {
3258 SET_BIT(ADCx->OR, ADC_OR_OP0);
3259 }
3260 #else
3261 /**
3262 * @brief Enable VddCore (internal digital core voltage) channel.
3263 * @note On this STM32 series, VddCore channel is controlled via a specific register.
3264 * @rmtoll OR OP1 LL_ADC_EnableChannelVDDcore
3265 * @param ADCx ADC instance
3266 * @retval None
3267 */
LL_ADC_EnableChannelVDDcore(ADC_TypeDef * ADCx)3268 __STATIC_INLINE void LL_ADC_EnableChannelVDDcore(ADC_TypeDef *ADCx)
3269 {
3270 SET_BIT(ADCx->OR, ADC_OR_OP1);
3271 }
3272 #endif /* ADC2 */
3273
3274 #if defined (ADC2)
3275 /**
3276 * @brief Disable VddCore (internal digital core voltage) channel.
3277 * @note On this STM32 series, VddCore channel is controlled via a specific register.
3278 * @note On this STM32 series, VddCore channel is on ADC2 instance only.
3279 * @rmtoll OR OP0 LL_ADC_DisableChannelVDDcore
3280 * @param ADCx ADC instance
3281 * @retval None
3282 */
LL_ADC_DisableChannelVDDcore(ADC_TypeDef * ADCx)3283 __STATIC_INLINE void LL_ADC_DisableChannelVDDcore(ADC_TypeDef *ADCx)
3284 {
3285 CLEAR_BIT(ADCx->OR, ADC_OR_OP0);
3286 }
3287 #else
3288 /**
3289 * @brief Disable VddCore (internal digital core voltage) channel.
3290 * @note On this STM32 series, VddCore channel is controlled via a specific register.
3291 * @rmtoll OR OP1 LL_ADC_DisableChannelVDDcore
3292 * @param ADCx ADC instance
3293 * @retval None
3294 */
LL_ADC_DisableChannelVDDcore(ADC_TypeDef * ADCx)3295 __STATIC_INLINE void LL_ADC_DisableChannelVDDcore(ADC_TypeDef *ADCx)
3296 {
3297 CLEAR_BIT(ADCx->OR, ADC_OR_OP1);
3298 }
3299 #endif /* ADC2 */
3300
3301 /**
3302 * @brief Enable Channel 0 GPIO switch control.
3303 * @note On this STM32 series, Channel 0 channel connection to GPIO is controlled via specific register.
3304 * @note On this STM32 series, Channel 0 GPIO switch control must be enabled when INP0 is used.
3305 * @rmtoll OR OP0 LL_ADC_EnableChannel0_GPIO
3306 * @param ADCx ADC instance
3307 * @retval None
3308 */
LL_ADC_EnableChannel0_GPIO(const ADC_TypeDef * ADCx)3309 __STATIC_INLINE void LL_ADC_EnableChannel0_GPIO(const ADC_TypeDef *ADCx)
3310 {
3311 /* Prevent unused argument(s) compilation warning */
3312 (void)(ADCx);
3313 SET_BIT(ADC1->OR, ADC_OR_OP0);
3314 }
3315
3316 /**
3317 * @brief Disable Channel 0 GPIO switch control.
3318 * @note On this STM32 series, Channel 0 connection to GPIO is controlled via specific register.
3319 * @rmtoll OR OP0 LL_ADC_DisableChannel0_GPIO
3320 * @param ADCx ADC instance
3321 * @retval None
3322 */
LL_ADC_DisableChannel0_GPIO(const ADC_TypeDef * ADCx)3323 __STATIC_INLINE void LL_ADC_DisableChannel0_GPIO(const ADC_TypeDef *ADCx)
3324 {
3325 /* Prevent unused argument(s) compilation warning */
3326 (void)(ADCx);
3327 CLEAR_BIT(ADC1->OR, ADC_OR_OP0);
3328 }
3329
3330 /**
3331 * @brief Set ADC calibration factor in the mode single-ended
3332 * or differential (for devices with differential mode available).
3333 * @note This function is intended to set calibration parameters
3334 * without having to perform a new calibration using
3335 * @ref LL_ADC_StartCalibration().
3336 * @note For devices with differential mode available:
3337 * Calibration of offset is specific to each of
3338 * single-ended and differential modes
3339 * (calibration factor must be specified for each of these
3340 * differential modes, if used afterwards and if the application
3341 * requires their calibration).
3342 * @note In case of setting calibration factors of both modes single ended
3343 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
3344 * both calibration factors must be concatenated.
3345 * To perform this processing, use helper macro
3346 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
3347 * @note On this STM32 series, setting of this feature is conditioned to
3348 * ADC state:
3349 * ADC must be enabled, without calibration on going, without conversion
3350 * on going on group regular.
3351 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
3352 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
3353 * @param ADCx ADC instance
3354 * @param SingleDiff This parameter can be one of the following values:
3355 * @arg @ref LL_ADC_SINGLE_ENDED
3356 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3357 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
3358 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
3359 * @retval None
3360 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)3361 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
3362 {
3363 MODIFY_REG(ADCx->CALFACT,
3364 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
3365 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK)
3366 >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)
3367 & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
3368 }
3369
3370 /**
3371 * @brief Get ADC calibration factor in the mode single-ended
3372 * or differential (for devices with differential mode available).
3373 * @note Calibration factors are set by hardware after performing
3374 * a calibration run using function @ref LL_ADC_StartCalibration().
3375 * @note For devices with differential mode available:
3376 * Calibration of offset is specific to each of
3377 * single-ended and differential modes
3378 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
3379 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
3380 * @param ADCx ADC instance
3381 * @param SingleDiff This parameter can be one of the following values:
3382 * @arg @ref LL_ADC_SINGLE_ENDED
3383 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3384 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
3385 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx,uint32_t SingleDiff)3386 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
3387 {
3388 /* Retrieve bits with position in register depending on parameter */
3389 /* "SingleDiff". */
3390 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
3391 /* containing other bits reserved for other purpose. */
3392 return (uint32_t)(READ_BIT(ADCx->CALFACT,
3393 (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK))
3394 >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
3395 ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
3396 }
3397
3398 /**
3399 * @brief Set ADC resolution.
3400 * Refer to reference manual for alignments formats
3401 * dependencies to ADC resolutions.
3402 * @note On this STM32 series, setting of this feature is conditioned to
3403 * ADC state:
3404 * ADC must be disabled or enabled without conversion on going
3405 * on either groups regular or injected.
3406 * @rmtoll CFGR RES LL_ADC_SetResolution
3407 * @param ADCx ADC instance
3408 * @param Resolution This parameter can be one of the following values:
3409 * @arg @ref LL_ADC_RESOLUTION_12B
3410 * @arg @ref LL_ADC_RESOLUTION_10B
3411 * @arg @ref LL_ADC_RESOLUTION_8B
3412 * @arg @ref LL_ADC_RESOLUTION_6B
3413 * @retval None
3414 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)3415 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
3416 {
3417 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3418 }
3419
3420 /**
3421 * @brief Get ADC resolution.
3422 * Refer to reference manual for alignments formats
3423 * dependencies to ADC resolutions.
3424 * @rmtoll CFGR RES LL_ADC_GetResolution
3425 * @param ADCx ADC instance
3426 * @retval Returned value can be one of the following values:
3427 * @arg @ref LL_ADC_RESOLUTION_12B
3428 * @arg @ref LL_ADC_RESOLUTION_10B
3429 * @arg @ref LL_ADC_RESOLUTION_8B
3430 * @arg @ref LL_ADC_RESOLUTION_6B
3431 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)3432 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
3433 {
3434 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3435 }
3436
3437 /**
3438 * @brief Set ADC conversion data alignment.
3439 * @note Refer to reference manual for alignments formats
3440 * dependencies to ADC resolutions.
3441 * @note On this STM32 series, setting of this feature is conditioned to
3442 * ADC state:
3443 * ADC must be disabled or enabled without conversion on going
3444 * on either groups regular or injected.
3445 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
3446 * @param ADCx ADC instance
3447 * @param DataAlignment This parameter can be one of the following values:
3448 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3449 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3450 * @retval None
3451 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)3452 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
3453 {
3454 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
3455 }
3456
3457 /**
3458 * @brief Get ADC conversion data alignment.
3459 * @note Refer to reference manual for alignments formats
3460 * dependencies to ADC resolutions.
3461 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
3462 * @param ADCx ADC instance
3463 * @retval Returned value can be one of the following values:
3464 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3465 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3466 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)3467 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
3468 {
3469 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
3470 }
3471
3472 /**
3473 * @brief Set ADC low power mode.
3474 * @note Description of ADC low power modes:
3475 * - ADC low power mode "auto wait": Dynamic low power mode,
3476 * ADC conversions occurrences are limited to the minimum necessary
3477 * in order to reduce power consumption.
3478 * New ADC conversion starts only when the previous
3479 * unitary conversion data (for ADC group regular)
3480 * or previous sequence conversions data (for ADC group injected)
3481 * has been retrieved by user software.
3482 * In the meantime, ADC remains idle: does not performs any
3483 * other conversion.
3484 * This mode allows to automatically adapt the ADC conversions
3485 * triggers to the speed of the software that reads the data.
3486 * Moreover, this avoids risk of overrun for low frequency
3487 * applications.
3488 * How to use this low power mode:
3489 * - It is not recommended to use with interruption or DMA
3490 * since these modes have to clear immediately the EOC flag
3491 * (by CPU to free the IRQ pending event or by DMA).
3492 * Auto wait will work but fort a very short time, discarding
3493 * its intended benefit (except specific case of high load of CPU
3494 * or DMA transfers which can justify usage of auto wait).
3495 * - Do use with polling: 1. Start conversion,
3496 * 2. Later on, when conversion data is needed: poll for end of
3497 * conversion to ensure that conversion is completed and
3498 * retrieve ADC conversion data. This will trig another
3499 * ADC conversion start.
3500 * @note With ADC low power mode "auto wait", the ADC conversion data read
3501 * is corresponding to previous ADC conversion start, independently
3502 * of delay during which ADC was idle.
3503 * Therefore, the ADC conversion data may be outdated: does not
3504 * correspond to the current voltage level on the selected
3505 * ADC channel.
3506 * @note On this STM32 series, setting of this feature is conditioned to
3507 * ADC state:
3508 * ADC must be disabled or enabled without conversion on going
3509 * on either groups regular or injected.
3510 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
3511 * @param ADCx ADC instance
3512 * @param LowPowerMode This parameter can be one of the following values:
3513 * @arg @ref LL_ADC_LP_MODE_NONE
3514 * @arg @ref LL_ADC_LP_AUTOWAIT
3515 * @retval None
3516 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)3517 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3518 {
3519 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
3520 }
3521
3522 /**
3523 * @brief Get ADC low power mode:
3524 * @note Description of ADC low power modes:
3525 * - ADC low power mode "auto wait": Dynamic low power mode,
3526 * ADC conversions occurrences are limited to the minimum necessary
3527 * in order to reduce power consumption.
3528 * New ADC conversion starts only when the previous
3529 * unitary conversion data (for ADC group regular)
3530 * or previous sequence conversions data (for ADC group injected)
3531 * has been retrieved by user software.
3532 * In the meantime, ADC remains idle: does not performs any
3533 * other conversion.
3534 * This mode allows to automatically adapt the ADC conversions
3535 * triggers to the speed of the software that reads the data.
3536 * Moreover, this avoids risk of overrun for low frequency
3537 * applications.
3538 * How to use this low power mode:
3539 * - It is not recommended to use with interruption or DMA
3540 * since these modes have to clear immediately the EOC flag
3541 * (by CPU to free the IRQ pending event or by DMA).
3542 * Auto wait will work but fort a very short time, discarding
3543 * its intended benefit (except specific case of high load of CPU
3544 * or DMA transfers which can justify usage of auto wait).
3545 * - Do use with polling: 1. Start conversion,
3546 * 2. Later on, when conversion data is needed: poll for end of
3547 * conversion to ensure that conversion is completed and
3548 * retrieve ADC conversion data. This will trig another
3549 * ADC conversion start.
3550 * @note With ADC low power mode "auto wait", the ADC conversion data read
3551 * is corresponding to previous ADC conversion start, independently
3552 * of delay during which ADC was idle.
3553 * Therefore, the ADC conversion data may be outdated: does not
3554 * correspond to the current voltage level on the selected
3555 * ADC channel.
3556 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
3557 * @param ADCx ADC instance
3558 * @retval Returned value can be one of the following values:
3559 * @arg @ref LL_ADC_LP_MODE_NONE
3560 * @arg @ref LL_ADC_LP_AUTOWAIT
3561 */
LL_ADC_GetLowPowerMode(const ADC_TypeDef * ADCx)3562 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
3563 {
3564 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
3565 }
3566
3567 /**
3568 * @brief Set ADC selected offset instance 1, 2, 3 or 4.
3569 * @note This function set the 2 items of offset configuration:
3570 * - ADC channel to which the offset programmed will be applied
3571 * (independently of channel mapped on ADC group regular
3572 * or group injected)
3573 * - Offset level (offset to be subtracted from the raw
3574 * converted data).
3575 * @note Caution: Offset format is dependent to ADC resolution:
3576 * offset has to be left-aligned on bit 11, the LSB (right bits)
3577 * are set to 0.
3578 * @note This function enables the offset, by default. It can be forced
3579 * to disable state using function LL_ADC_SetOffsetState().
3580 * @note If a channel is mapped on several offsets numbers, only the offset
3581 * with the lowest value is considered for the subtraction.
3582 * @note On this STM32 series, setting of this feature is conditioned to
3583 * ADC state:
3584 * ADC must be disabled or enabled without conversion on going
3585 * on either groups regular or injected.
3586 * @note On STM32H5, some fast channels are available: fast analog inputs
3587 * coming from GPIO pads (ADC_IN0..5).
3588 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
3589 * OFR1 OFFSET1 LL_ADC_SetOffset\n
3590 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
3591 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
3592 * OFR2 OFFSET2 LL_ADC_SetOffset\n
3593 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
3594 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
3595 * OFR3 OFFSET3 LL_ADC_SetOffset\n
3596 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
3597 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
3598 * OFR4 OFFSET4 LL_ADC_SetOffset\n
3599 * OFR4 OFFSET4_EN LL_ADC_SetOffset
3600 * @param ADCx ADC instance
3601 * @param Offsety This parameter can be one of the following values:
3602 * @arg @ref LL_ADC_OFFSET_1
3603 * @arg @ref LL_ADC_OFFSET_2
3604 * @arg @ref LL_ADC_OFFSET_3
3605 * @arg @ref LL_ADC_OFFSET_4
3606 * @param Channel This parameter can be one of the following values:
3607 * @arg @ref LL_ADC_CHANNEL_0 (3)
3608 * @arg @ref LL_ADC_CHANNEL_1 (3)
3609 * @arg @ref LL_ADC_CHANNEL_2 (3)
3610 * @arg @ref LL_ADC_CHANNEL_3 (3)
3611 * @arg @ref LL_ADC_CHANNEL_4 (3)
3612 * @arg @ref LL_ADC_CHANNEL_5 (3)
3613 * @arg @ref LL_ADC_CHANNEL_6
3614 * @arg @ref LL_ADC_CHANNEL_7
3615 * @arg @ref LL_ADC_CHANNEL_8
3616 * @arg @ref LL_ADC_CHANNEL_9
3617 * @arg @ref LL_ADC_CHANNEL_10
3618 * @arg @ref LL_ADC_CHANNEL_11
3619 * @arg @ref LL_ADC_CHANNEL_12
3620 * @arg @ref LL_ADC_CHANNEL_13
3621 * @arg @ref LL_ADC_CHANNEL_14
3622 * @arg @ref LL_ADC_CHANNEL_15
3623 * @arg @ref LL_ADC_CHANNEL_16
3624 * @arg @ref LL_ADC_CHANNEL_17
3625 * @arg @ref LL_ADC_CHANNEL_18
3626 * @arg @ref LL_ADC_CHANNEL_19
3627 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3628 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3629 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
3630 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
3631 *
3632 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
3633 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
3634 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
3635 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
3636 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3637 * @retval None
3638 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)3639 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3640 {
3641 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3642
3643 MODIFY_REG(*preg,
3644 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3645 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3646 }
3647
3648 /**
3649 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3650 * Channel to which the offset programmed will be applied
3651 * (independently of channel mapped on ADC group regular
3652 * or group injected)
3653 * @note Usage of the returned channel number:
3654 * - To reinject this channel into another function LL_ADC_xxx:
3655 * the returned channel number is only partly formatted on definition
3656 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3657 * with parts of literals LL_ADC_CHANNEL_x or using
3658 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3659 * Then the selected literal LL_ADC_CHANNEL_x can be used
3660 * as parameter for another function.
3661 * - To get the channel number in decimal format:
3662 * process the returned value with the helper macro
3663 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3664 * @note On STM32H5, some fast channels are available: fast analog inputs
3665 * coming from GPIO pads (ADC_IN0..5).
3666 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
3667 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
3668 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
3669 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
3670 * @param ADCx ADC instance
3671 * @param Offsety This parameter can be one of the following values:
3672 * @arg @ref LL_ADC_OFFSET_1
3673 * @arg @ref LL_ADC_OFFSET_2
3674 * @arg @ref LL_ADC_OFFSET_3
3675 * @arg @ref LL_ADC_OFFSET_4
3676 * @retval Returned value can be one of the following values:
3677 * @arg @ref LL_ADC_CHANNEL_0 (3)
3678 * @arg @ref LL_ADC_CHANNEL_1 (3)
3679 * @arg @ref LL_ADC_CHANNEL_2 (3)
3680 * @arg @ref LL_ADC_CHANNEL_3 (3)
3681 * @arg @ref LL_ADC_CHANNEL_4 (3)
3682 * @arg @ref LL_ADC_CHANNEL_5 (3)
3683 * @arg @ref LL_ADC_CHANNEL_6
3684 * @arg @ref LL_ADC_CHANNEL_7
3685 * @arg @ref LL_ADC_CHANNEL_8
3686 * @arg @ref LL_ADC_CHANNEL_9
3687 * @arg @ref LL_ADC_CHANNEL_10
3688 * @arg @ref LL_ADC_CHANNEL_11
3689 * @arg @ref LL_ADC_CHANNEL_12
3690 * @arg @ref LL_ADC_CHANNEL_13
3691 * @arg @ref LL_ADC_CHANNEL_14
3692 * @arg @ref LL_ADC_CHANNEL_15
3693 * @arg @ref LL_ADC_CHANNEL_16
3694 * @arg @ref LL_ADC_CHANNEL_17
3695 * @arg @ref LL_ADC_CHANNEL_18
3696 * @arg @ref LL_ADC_CHANNEL_19
3697 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(4)
3698 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(4)
3699 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(4)
3700 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(4)
3701 *
3702 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
3703 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
3704 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
3705 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
3706 * (4) For ADC channel read back from ADC register,
3707 * comparison with internal channel parameter to be done
3708 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3709 */
LL_ADC_GetOffsetChannel(const ADC_TypeDef * ADCx,uint32_t Offsety)3710 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3711 {
3712 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3713
3714 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3715 }
3716
3717 /**
3718 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3719 * Offset level (offset to be subtracted from the raw
3720 * converted data).
3721 * @note Caution: Offset format is dependent to ADC resolution:
3722 * offset has to be left-aligned on bit 11, the LSB (right bits)
3723 * are set to 0.
3724 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3725 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3726 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3727 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3728 * @param ADCx ADC instance
3729 * @param Offsety This parameter can be one of the following values:
3730 * @arg @ref LL_ADC_OFFSET_1
3731 * @arg @ref LL_ADC_OFFSET_2
3732 * @arg @ref LL_ADC_OFFSET_3
3733 * @arg @ref LL_ADC_OFFSET_4
3734 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3735 */
LL_ADC_GetOffsetLevel(const ADC_TypeDef * ADCx,uint32_t Offsety)3736 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3737 {
3738 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3739
3740 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3741 }
3742
3743 /**
3744 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
3745 * force offset state disable or enable
3746 * without modifying offset channel or offset value.
3747 * @note This function should be needed only in case of offset to be
3748 * enabled-disabled dynamically, and should not be needed in other cases:
3749 * function LL_ADC_SetOffset() automatically enables the offset.
3750 * @note On this STM32 series, setting of this feature is conditioned to
3751 * ADC state:
3752 * ADC must be disabled or enabled without conversion on going
3753 * on either groups regular or injected.
3754 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3755 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3756 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3757 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3758 * @param ADCx ADC instance
3759 * @param Offsety This parameter can be one of the following values:
3760 * @arg @ref LL_ADC_OFFSET_1
3761 * @arg @ref LL_ADC_OFFSET_2
3762 * @arg @ref LL_ADC_OFFSET_3
3763 * @arg @ref LL_ADC_OFFSET_4
3764 * @param OffsetState This parameter can be one of the following values:
3765 * @arg @ref LL_ADC_OFFSET_DISABLE
3766 * @arg @ref LL_ADC_OFFSET_ENABLE
3767 * @retval None
3768 */
LL_ADC_SetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetState)3769 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3770 {
3771 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3772
3773 MODIFY_REG(*preg,
3774 ADC_OFR1_OFFSET1_EN,
3775 OffsetState);
3776 }
3777
3778 /**
3779 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3780 * offset state disabled or enabled.
3781 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3782 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3783 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3784 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3785 * @param ADCx ADC instance
3786 * @param Offsety This parameter can be one of the following values:
3787 * @arg @ref LL_ADC_OFFSET_1
3788 * @arg @ref LL_ADC_OFFSET_2
3789 * @arg @ref LL_ADC_OFFSET_3
3790 * @arg @ref LL_ADC_OFFSET_4
3791 * @retval Returned value can be one of the following values:
3792 * @arg @ref LL_ADC_OFFSET_DISABLE
3793 * @arg @ref LL_ADC_OFFSET_ENABLE
3794 */
LL_ADC_GetOffsetState(const ADC_TypeDef * ADCx,uint32_t Offsety)3795 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety)
3796 {
3797 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3798
3799 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3800 }
3801
3802 /**
3803 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
3804 * choose offset sign.
3805 * @note On this STM32 series, setting of this feature is conditioned to
3806 * ADC state:
3807 * ADC must be disabled or enabled without conversion on going
3808 * on either groups regular or injected.
3809 * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
3810 * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
3811 * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
3812 * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
3813 * @param ADCx ADC instance
3814 * @param Offsety This parameter can be one of the following values:
3815 * @arg @ref LL_ADC_OFFSET_1
3816 * @arg @ref LL_ADC_OFFSET_2
3817 * @arg @ref LL_ADC_OFFSET_3
3818 * @arg @ref LL_ADC_OFFSET_4
3819 * @param OffsetSign This parameter can be one of the following values:
3820 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3821 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3822 * @retval None
3823 */
LL_ADC_SetOffsetSign(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSign)3824 __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
3825 {
3826 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3827
3828 MODIFY_REG(*preg,
3829 ADC_OFR1_OFFSETPOS,
3830 OffsetSign);
3831 }
3832
3833 /**
3834 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3835 * offset sign if positive or negative.
3836 * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
3837 * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
3838 * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
3839 * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
3840 * @param ADCx ADC instance
3841 * @param Offsety This parameter can be one of the following values:
3842 * @arg @ref LL_ADC_OFFSET_1
3843 * @arg @ref LL_ADC_OFFSET_2
3844 * @arg @ref LL_ADC_OFFSET_3
3845 * @arg @ref LL_ADC_OFFSET_4
3846 * @retval Returned value can be one of the following values:
3847 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3848 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3849 */
LL_ADC_GetOffsetSign(const ADC_TypeDef * ADCx,uint32_t Offsety)3850 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety)
3851 {
3852 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3853
3854 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
3855 }
3856
3857 /**
3858 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
3859 * choose offset saturation mode.
3860 * @note On this STM32 series, setting of this feature is conditioned to
3861 * ADC state:
3862 * ADC must be disabled or enabled without conversion on going
3863 * on either groups regular or injected.
3864 * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n
3865 * OFR2 SATEN LL_ADC_SetOffsetSaturation\n
3866 * OFR3 SATEN LL_ADC_SetOffsetSaturation\n
3867 * OFR4 SATEN LL_ADC_SetOffsetSaturation
3868 * @param ADCx ADC instance
3869 * @param Offsety This parameter can be one of the following values:
3870 * @arg @ref LL_ADC_OFFSET_1
3871 * @arg @ref LL_ADC_OFFSET_2
3872 * @arg @ref LL_ADC_OFFSET_3
3873 * @arg @ref LL_ADC_OFFSET_4
3874 * @param OffsetSaturation This parameter can be one of the following values:
3875 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3876 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3877 * @retval None
3878 */
LL_ADC_SetOffsetSaturation(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSaturation)3879 __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
3880 {
3881 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3882
3883 MODIFY_REG(*preg,
3884 ADC_OFR1_SATEN,
3885 OffsetSaturation);
3886 }
3887
3888 /**
3889 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3890 * offset saturation if enabled or disabled.
3891 * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n
3892 * OFR2 SATEN LL_ADC_GetOffsetSaturation\n
3893 * OFR3 SATEN LL_ADC_GetOffsetSaturation\n
3894 * OFR4 SATEN LL_ADC_GetOffsetSaturation
3895 * @param ADCx ADC instance
3896 * @param Offsety This parameter can be one of the following values:
3897 * @arg @ref LL_ADC_OFFSET_1
3898 * @arg @ref LL_ADC_OFFSET_2
3899 * @arg @ref LL_ADC_OFFSET_3
3900 * @arg @ref LL_ADC_OFFSET_4
3901 * @retval Returned value can be one of the following values:
3902 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3903 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3904 */
LL_ADC_GetOffsetSaturation(const ADC_TypeDef * ADCx,uint32_t Offsety)3905 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
3906 {
3907 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3908
3909 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN);
3910 }
3911
3912 #if defined(ADC_SMPR1_SMPPLUS)
3913 /**
3914 * @brief Set ADC sampling time common configuration impacting
3915 * settings of sampling time channel wise.
3916 * @note On this STM32 series, setting of this feature is conditioned to
3917 * ADC state:
3918 * ADC must be disabled or enabled without conversion on going
3919 * on either groups regular or injected.
3920 * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
3921 * @param ADCx ADC instance
3922 * @param SamplingTimeCommonConfig This parameter can be one of the following values:
3923 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3924 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3925 * @retval None
3926 */
LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef * ADCx,uint32_t SamplingTimeCommonConfig)3927 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
3928 {
3929 MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
3930 }
3931
3932 /**
3933 * @brief Get ADC sampling time common configuration impacting
3934 * settings of sampling time channel wise.
3935 * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
3936 * @param ADCx ADC instance
3937 * @retval Returned value can be one of the following values:
3938 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3939 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3940 */
LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef * ADCx)3941 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef *ADCx)
3942 {
3943 return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
3944 }
3945 #endif /* ADC_SMPR1_SMPPLUS */
3946
3947 /**
3948 * @}
3949 */
3950
3951 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3952 * @{
3953 */
3954
3955 /**
3956 * @brief Set ADC group regular conversion trigger source:
3957 * internal (SW start) or from external peripheral (timer event,
3958 * external interrupt line).
3959 * @note On this STM32 series, setting trigger source to external trigger
3960 * also set trigger polarity to rising edge
3961 * (default setting for compatibility with some ADC on other
3962 * STM32 series having this setting set by HW default value).
3963 * In case of need to modify trigger edge, use
3964 * function @ref LL_ADC_REG_SetTriggerEdge().
3965 * @note Availability of parameters of trigger sources from timer
3966 * depends on timers availability on the selected device.
3967 * @note On this STM32 series, setting of this feature is conditioned to
3968 * ADC state:
3969 * ADC must be disabled or enabled without conversion on going
3970 * on group regular.
3971 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3972 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3973 * @param ADCx ADC instance
3974 * @param TriggerSource This parameter can be one of the following values:
3975 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3976 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3977 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3978 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3979 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3980 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3981 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3982 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3983 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3984 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3985 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO (1)
3986 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
3987 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3988 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO (2)
3989 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (1)
3990 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)
3991 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
3992 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
3993 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
3994 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3995 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE15
3996 *
3997 * (1) On STM32H5 series, parameter specific to devices: STM32H563/H573xx.
3998 * (2) On STM32H5 series, parameter specific to devices: STM32H503xx.
3999 * @retval None
4000 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)4001 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4002 {
4003 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
4004 }
4005
4006 /**
4007 * @brief Get ADC group regular conversion trigger source:
4008 * internal (SW start) or from external peripheral (timer event,
4009 * external interrupt line).
4010 * @note To determine whether group regular trigger source is
4011 * internal (SW start) or external, without detail
4012 * of which peripheral is selected as external trigger,
4013 * (equivalent to
4014 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
4015 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
4016 * @note Availability of parameters of trigger sources from timer
4017 * depends on timers availability on the selected device.
4018 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
4019 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
4020 * @param ADCx ADC instance
4021 * @retval Returned value can be one of the following values:
4022 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
4023 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
4024 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
4025 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
4026 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
4027 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
4028 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
4029 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
4030 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
4031 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
4032 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO (1)
4033 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
4034 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
4035 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO (2)
4036 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (1)
4037 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)
4038 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
4039 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
4040 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
4041 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
4042 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE15
4043 *
4044 * (1) On STM32H5 series, parameter specific to devices: STM32H563/H573xx.
4045 * (2) On STM32H5 series, parameter specific to devices: STM32H503xx.
4046 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)4047 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
4048 {
4049 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
4050
4051 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4052 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
4053 uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4054
4055 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
4056 /* to match with triggers literals definition. */
4057 return ((trigger_source
4058 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL)
4059 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN)
4060 );
4061 }
4062
4063 /**
4064 * @brief Get ADC group regular conversion trigger source internal (SW start)
4065 * or external.
4066 * @note In case of group regular trigger source set to external trigger,
4067 * to determine which peripheral is selected as external trigger,
4068 * use function @ref LL_ADC_REG_GetTriggerSource().
4069 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
4070 * @param ADCx ADC instance
4071 * @retval Value "0" if trigger source external trigger
4072 * Value "1" if trigger source SW start.
4073 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)4074 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4075 {
4076 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
4077 }
4078
4079 /**
4080 * @brief Set ADC group regular conversion trigger polarity.
4081 * @note Applicable only for trigger source set to external trigger.
4082 * @note On this STM32 series, setting of this feature is conditioned to
4083 * ADC state:
4084 * ADC must be disabled or enabled without conversion on going
4085 * on group regular.
4086 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
4087 * @param ADCx ADC instance
4088 * @param ExternalTriggerEdge This parameter can be one of the following values:
4089 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4090 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4091 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4092 * @retval None
4093 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4094 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4095 {
4096 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
4097 }
4098
4099 /**
4100 * @brief Get ADC group regular conversion trigger polarity.
4101 * @note Applicable only for trigger source set to external trigger.
4102 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
4103 * @param ADCx ADC instance
4104 * @retval Returned value can be one of the following values:
4105 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4106 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4107 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4108 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)4109 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
4110 {
4111 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
4112 }
4113
4114 /**
4115 * @brief Set ADC sampling mode.
4116 * @note This function set the ADC conversion sampling mode
4117 * @note This mode applies to regular group only.
4118 * @note Set sampling mode is applied to all conversion of regular group.
4119 * @note On this STM32 series, setting of this feature is conditioned to
4120 * ADC state:
4121 * ADC must be disabled or enabled without conversion on going
4122 * on group regular.
4123 * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
4124 * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
4125 * @param ADCx ADC instance
4126 * @param SamplingMode This parameter can be one of the following values:
4127 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
4128 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
4129 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
4130 * @retval None
4131 */
LL_ADC_REG_SetSamplingMode(ADC_TypeDef * ADCx,uint32_t SamplingMode)4132 __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
4133 {
4134 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
4135 }
4136
4137 /**
4138 * @brief Get the ADC sampling mode
4139 * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n
4140 * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
4141 * @param ADCx ADC instance
4142 * @retval Returned value can be one of the following values:
4143 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
4144 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
4145 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
4146 */
LL_ADC_REG_GetSamplingMode(const ADC_TypeDef * ADCx)4147 __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx)
4148 {
4149 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
4150 }
4151
4152 /**
4153 * @brief Set ADC group regular sequencer length and scan direction.
4154 * @note Description of ADC group regular sequencer features:
4155 * - For devices with sequencer fully configurable
4156 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4157 * sequencer length and each rank affectation to a channel
4158 * are configurable.
4159 * This function performs configuration of:
4160 * - Sequence length: Number of ranks in the scan sequence.
4161 * - Sequence direction: Unless specified in parameters, sequencer
4162 * scan direction is forward (from rank 1 to rank n).
4163 * Sequencer ranks are selected using
4164 * function "LL_ADC_REG_SetSequencerRanks()".
4165 * - For devices with sequencer not fully configurable
4166 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4167 * sequencer length and each rank affectation to a channel
4168 * are defined by channel number.
4169 * This function performs configuration of:
4170 * - Sequence length: Number of ranks in the scan sequence is
4171 * defined by number of channels set in the sequence,
4172 * rank of each channel is fixed by channel HW number.
4173 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4174 * - Sequence direction: Unless specified in parameters, sequencer
4175 * scan direction is forward (from lowest channel number to
4176 * highest channel number).
4177 * Sequencer ranks are selected using
4178 * function "LL_ADC_REG_SetSequencerChannels()".
4179 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4180 * ADC conversion on only 1 channel.
4181 * @note On this STM32 series, setting of this feature is conditioned to
4182 * ADC state:
4183 * ADC must be disabled or enabled without conversion on going
4184 * on group regular.
4185 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
4186 * @param ADCx ADC instance
4187 * @param SequencerNbRanks This parameter can be one of the following values:
4188 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4189 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4190 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4191 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4192 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4193 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4194 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4195 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4196 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4197 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4198 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4199 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4200 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4201 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4202 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4203 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4204 * @retval None
4205 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4206 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4207 {
4208 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
4209 }
4210
4211 /**
4212 * @brief Get ADC group regular sequencer length and scan direction.
4213 * @note Description of ADC group regular sequencer features:
4214 * - For devices with sequencer fully configurable
4215 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4216 * sequencer length and each rank affectation to a channel
4217 * are configurable.
4218 * This function retrieves:
4219 * - Sequence length: Number of ranks in the scan sequence.
4220 * - Sequence direction: Unless specified in parameters, sequencer
4221 * scan direction is forward (from rank 1 to rank n).
4222 * Sequencer ranks are selected using
4223 * function "LL_ADC_REG_SetSequencerRanks()".
4224 * - For devices with sequencer not fully configurable
4225 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4226 * sequencer length and each rank affectation to a channel
4227 * are defined by channel number.
4228 * This function retrieves:
4229 * - Sequence length: Number of ranks in the scan sequence is
4230 * defined by number of channels set in the sequence,
4231 * rank of each channel is fixed by channel HW number.
4232 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4233 * - Sequence direction: Unless specified in parameters, sequencer
4234 * scan direction is forward (from lowest channel number to
4235 * highest channel number).
4236 * Sequencer ranks are selected using
4237 * function "LL_ADC_REG_SetSequencerChannels()".
4238 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4239 * ADC conversion on only 1 channel.
4240 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
4241 * @param ADCx ADC instance
4242 * @retval Returned value can be one of the following values:
4243 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4244 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4245 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4246 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4247 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4248 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4249 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4250 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4251 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4252 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4253 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4254 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4255 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4256 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4257 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4258 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4259 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)4260 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
4261 {
4262 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
4263 }
4264
4265 /**
4266 * @brief Set ADC group regular sequencer discontinuous mode:
4267 * sequence subdivided and scan conversions interrupted every selected
4268 * number of ranks.
4269 * @note It is not possible to enable both ADC group regular
4270 * continuous mode and sequencer discontinuous mode.
4271 * @note It is not possible to enable both ADC auto-injected mode
4272 * and ADC group regular sequencer discontinuous mode.
4273 * @note On this STM32 series, setting of this feature is conditioned to
4274 * ADC state:
4275 * ADC must be disabled or enabled without conversion on going
4276 * on group regular.
4277 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
4278 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
4279 * @param ADCx ADC instance
4280 * @param SeqDiscont This parameter can be one of the following values:
4281 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4282 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4283 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4284 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4285 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4286 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4287 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4288 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4289 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4290 * @retval None
4291 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4292 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4293 {
4294 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
4295 }
4296
4297 /**
4298 * @brief Get ADC group regular sequencer discontinuous mode:
4299 * sequence subdivided and scan conversions interrupted every selected
4300 * number of ranks.
4301 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
4302 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
4303 * @param ADCx ADC instance
4304 * @retval Returned value can be one of the following values:
4305 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4306 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4307 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4308 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4309 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4310 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4311 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4312 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4313 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4314 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)4315 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4316 {
4317 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
4318 }
4319
4320 /**
4321 * @brief Set ADC group regular sequence: channel on the selected
4322 * scan sequence rank.
4323 * @note This function performs configuration of:
4324 * - Channels ordering into each rank of scan sequence:
4325 * whatever channel can be placed into whatever rank.
4326 * @note On this STM32 series, ADC group regular sequencer is
4327 * fully configurable: sequencer length and each rank
4328 * affectation to a channel are configurable.
4329 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4330 * @note Depending on devices and packages, some channels may not be available.
4331 * Refer to device datasheet for channels availability.
4332 * @note On this STM32 series, to measure internal channels (VrefInt,
4333 * TempSensor, ...), measurement paths to internal channels must be
4334 * enabled separately.
4335 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4336 * @note On this STM32 series, setting of this feature is conditioned to
4337 * ADC state:
4338 * ADC must be disabled or enabled without conversion on going
4339 * on group regular.
4340 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
4341 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
4342 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
4343 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
4344 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
4345 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
4346 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
4347 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
4348 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
4349 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
4350 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
4351 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
4352 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
4353 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
4354 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
4355 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
4356 * @param ADCx ADC instance
4357 * @param Rank This parameter can be one of the following values:
4358 * @arg @ref LL_ADC_REG_RANK_1
4359 * @arg @ref LL_ADC_REG_RANK_2
4360 * @arg @ref LL_ADC_REG_RANK_3
4361 * @arg @ref LL_ADC_REG_RANK_4
4362 * @arg @ref LL_ADC_REG_RANK_5
4363 * @arg @ref LL_ADC_REG_RANK_6
4364 * @arg @ref LL_ADC_REG_RANK_7
4365 * @arg @ref LL_ADC_REG_RANK_8
4366 * @arg @ref LL_ADC_REG_RANK_9
4367 * @arg @ref LL_ADC_REG_RANK_10
4368 * @arg @ref LL_ADC_REG_RANK_11
4369 * @arg @ref LL_ADC_REG_RANK_12
4370 * @arg @ref LL_ADC_REG_RANK_13
4371 * @arg @ref LL_ADC_REG_RANK_14
4372 * @arg @ref LL_ADC_REG_RANK_15
4373 * @arg @ref LL_ADC_REG_RANK_16
4374 * @param Channel This parameter can be one of the following values:
4375 * @arg @ref LL_ADC_CHANNEL_0 (3)
4376 * @arg @ref LL_ADC_CHANNEL_1 (3)
4377 * @arg @ref LL_ADC_CHANNEL_2 (3)
4378 * @arg @ref LL_ADC_CHANNEL_3 (3)
4379 * @arg @ref LL_ADC_CHANNEL_4 (3)
4380 * @arg @ref LL_ADC_CHANNEL_5 (3)
4381 * @arg @ref LL_ADC_CHANNEL_6
4382 * @arg @ref LL_ADC_CHANNEL_7
4383 * @arg @ref LL_ADC_CHANNEL_8
4384 * @arg @ref LL_ADC_CHANNEL_9
4385 * @arg @ref LL_ADC_CHANNEL_10
4386 * @arg @ref LL_ADC_CHANNEL_11
4387 * @arg @ref LL_ADC_CHANNEL_12
4388 * @arg @ref LL_ADC_CHANNEL_13
4389 * @arg @ref LL_ADC_CHANNEL_14
4390 * @arg @ref LL_ADC_CHANNEL_15
4391 * @arg @ref LL_ADC_CHANNEL_16
4392 * @arg @ref LL_ADC_CHANNEL_17
4393 * @arg @ref LL_ADC_CHANNEL_18
4394 * @arg @ref LL_ADC_CHANNEL_19
4395 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4396 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4397 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
4398 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
4399 *
4400 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
4401 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
4402 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
4403 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
4404 * @retval None
4405 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4406 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4407 {
4408 /* Set bits with content of parameter "Channel" with bits position */
4409 /* in register and register position depending on parameter "Rank". */
4410 /* Parameters "Rank" and "Channel" are used with masks because containing */
4411 /* other bits reserved for other purpose. */
4412 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
4413 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4414
4415 MODIFY_REG(*preg,
4416 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4417 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4418 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4419 }
4420
4421 /**
4422 * @brief Get ADC group regular sequence: channel on the selected
4423 * scan sequence rank.
4424 * @note On this STM32 series, ADC group regular sequencer is
4425 * fully configurable: sequencer length and each rank
4426 * affectation to a channel are configurable.
4427 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4428 * @note Depending on devices and packages, some channels may not be available.
4429 * Refer to device datasheet for channels availability.
4430 * @note Usage of the returned channel number:
4431 * - To reinject this channel into another function LL_ADC_xxx:
4432 * the returned channel number is only partly formatted on definition
4433 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4434 * with parts of literals LL_ADC_CHANNEL_x or using
4435 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4436 * Then the selected literal LL_ADC_CHANNEL_x can be used
4437 * as parameter for another function.
4438 * - To get the channel number in decimal format:
4439 * process the returned value with the helper macro
4440 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4441 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
4442 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
4443 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
4444 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
4445 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
4446 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
4447 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
4448 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
4449 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
4450 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
4451 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
4452 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
4453 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
4454 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
4455 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
4456 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4457 * @param ADCx ADC instance
4458 * @param Rank This parameter can be one of the following values:
4459 * @arg @ref LL_ADC_REG_RANK_1
4460 * @arg @ref LL_ADC_REG_RANK_2
4461 * @arg @ref LL_ADC_REG_RANK_3
4462 * @arg @ref LL_ADC_REG_RANK_4
4463 * @arg @ref LL_ADC_REG_RANK_5
4464 * @arg @ref LL_ADC_REG_RANK_6
4465 * @arg @ref LL_ADC_REG_RANK_7
4466 * @arg @ref LL_ADC_REG_RANK_8
4467 * @arg @ref LL_ADC_REG_RANK_9
4468 * @arg @ref LL_ADC_REG_RANK_10
4469 * @arg @ref LL_ADC_REG_RANK_11
4470 * @arg @ref LL_ADC_REG_RANK_12
4471 * @arg @ref LL_ADC_REG_RANK_13
4472 * @arg @ref LL_ADC_REG_RANK_14
4473 * @arg @ref LL_ADC_REG_RANK_15
4474 * @arg @ref LL_ADC_REG_RANK_16
4475 * @retval Returned value can be one of the following values:
4476 * @arg @ref LL_ADC_CHANNEL_0 (3)
4477 * @arg @ref LL_ADC_CHANNEL_1 (3)
4478 * @arg @ref LL_ADC_CHANNEL_2 (3)
4479 * @arg @ref LL_ADC_CHANNEL_3 (3)
4480 * @arg @ref LL_ADC_CHANNEL_4 (3)
4481 * @arg @ref LL_ADC_CHANNEL_5 (3)
4482 * @arg @ref LL_ADC_CHANNEL_6
4483 * @arg @ref LL_ADC_CHANNEL_7
4484 * @arg @ref LL_ADC_CHANNEL_8
4485 * @arg @ref LL_ADC_CHANNEL_9
4486 * @arg @ref LL_ADC_CHANNEL_10
4487 * @arg @ref LL_ADC_CHANNEL_11
4488 * @arg @ref LL_ADC_CHANNEL_12
4489 * @arg @ref LL_ADC_CHANNEL_13
4490 * @arg @ref LL_ADC_CHANNEL_14
4491 * @arg @ref LL_ADC_CHANNEL_15
4492 * @arg @ref LL_ADC_CHANNEL_16
4493 * @arg @ref LL_ADC_CHANNEL_17
4494 * @arg @ref LL_ADC_CHANNEL_18
4495 * @arg @ref LL_ADC_CHANNEL_19
4496 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(4)
4497 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(4)
4498 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(4)
4499 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(4)
4500 *
4501 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
4502 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
4503 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
4504 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
4505 * (4) For ADC channel read back from ADC register,
4506 * comparison with internal channel parameter to be done
4507 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4508 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4509 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4510 {
4511 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
4512 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4513
4514 return (uint32_t)((READ_BIT(*preg,
4515 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4516 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4517 );
4518 }
4519
4520 /**
4521 * @brief Set ADC continuous conversion mode on ADC group regular.
4522 * @note Description of ADC continuous conversion mode:
4523 * - single mode: one conversion per trigger
4524 * - continuous mode: after the first trigger, following
4525 * conversions launched successively automatically.
4526 * @note It is not possible to enable both ADC group regular
4527 * continuous mode and sequencer discontinuous mode.
4528 * @note On this STM32 series, setting of this feature is conditioned to
4529 * ADC state:
4530 * ADC must be disabled or enabled without conversion on going
4531 * on group regular.
4532 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
4533 * @param ADCx ADC instance
4534 * @param Continuous This parameter can be one of the following values:
4535 * @arg @ref LL_ADC_REG_CONV_SINGLE
4536 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4537 * @retval None
4538 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)4539 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4540 {
4541 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
4542 }
4543
4544 /**
4545 * @brief Get ADC continuous conversion mode on ADC group regular.
4546 * @note Description of ADC continuous conversion mode:
4547 * - single mode: one conversion per trigger
4548 * - continuous mode: after the first trigger, following
4549 * conversions launched successively automatically.
4550 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
4551 * @param ADCx ADC instance
4552 * @retval Returned value can be one of the following values:
4553 * @arg @ref LL_ADC_REG_CONV_SINGLE
4554 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4555 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)4556 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
4557 {
4558 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
4559 }
4560
4561 /**
4562 * @brief Set ADC group regular conversion data transfer: no transfer or
4563 * transfer by DMA, and DMA requests mode.
4564 * @note If transfer by DMA selected, specifies the DMA requests
4565 * mode:
4566 * - Limited mode (One shot mode): DMA transfer requests are stopped
4567 * when number of DMA data transfers (number of
4568 * ADC conversions) is reached.
4569 * This ADC mode is intended to be used with DMA mode non-circular.
4570 * - Unlimited mode: DMA transfer requests are unlimited,
4571 * whatever number of DMA data transfers (number of
4572 * ADC conversions).
4573 * This ADC mode is intended to be used with DMA mode circular.
4574 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4575 * mode non-circular:
4576 * when DMA transfers size will be reached, DMA will stop transfers of
4577 * ADC conversions data ADC will raise an overrun error
4578 * (overrun flag and interruption if enabled).
4579 * @note For devices with several ADC instances: ADC multimode DMA
4580 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
4581 * @note To configure DMA source address (peripheral address),
4582 * use function @ref LL_ADC_DMA_GetRegAddr().
4583 * @note On this STM32 series, setting of this feature is conditioned to
4584 * ADC state:
4585 * ADC must be disabled or enabled without conversion on going
4586 * on either groups regular or injected.
4587 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
4588 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
4589 * @param ADCx ADC instance
4590 * @param DMATransfer This parameter can be one of the following values:
4591 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4592 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4593 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4594 * @retval None
4595 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)4596 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
4597 {
4598 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
4599 }
4600
4601 /**
4602 * @brief Get ADC group regular conversion data transfer: no transfer or
4603 * transfer by DMA, and DMA requests mode.
4604 * @note If transfer by DMA selected, specifies the DMA requests
4605 * mode:
4606 * - Limited mode (One shot mode): DMA transfer requests are stopped
4607 * when number of DMA data transfers (number of
4608 * ADC conversions) is reached.
4609 * This ADC mode is intended to be used with DMA mode non-circular.
4610 * - Unlimited mode: DMA transfer requests are unlimited,
4611 * whatever number of DMA data transfers (number of
4612 * ADC conversions).
4613 * This ADC mode is intended to be used with DMA mode circular.
4614 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4615 * mode non-circular:
4616 * when DMA transfers size will be reached, DMA will stop transfers of
4617 * ADC conversions data ADC will raise an overrun error
4618 * (overrun flag and interruption if enabled).
4619 * @note For devices with several ADC instances: ADC multimode DMA
4620 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
4621 * @note To configure DMA source address (peripheral address),
4622 * use function @ref LL_ADC_DMA_GetRegAddr().
4623 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
4624 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
4625 * @param ADCx ADC instance
4626 * @retval Returned value can be one of the following values:
4627 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4628 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4629 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4630 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)4631 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
4632 {
4633 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
4634 }
4635
4636 /**
4637 * @brief Set ADC group regular behavior in case of overrun:
4638 * data preserved or overwritten.
4639 * @note Compatibility with devices without feature overrun:
4640 * other devices without this feature have a behavior
4641 * equivalent to data overwritten.
4642 * The default setting of overrun is data preserved.
4643 * Therefore, for compatibility with all devices, parameter
4644 * overrun should be set to data overwritten.
4645 * @note On this STM32 series, setting of this feature is conditioned to
4646 * ADC state:
4647 * ADC must be disabled or enabled without conversion on going
4648 * on group regular.
4649 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
4650 * @param ADCx ADC instance
4651 * @param Overrun This parameter can be one of the following values:
4652 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4653 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4654 * @retval None
4655 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)4656 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4657 {
4658 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
4659 }
4660
4661 /**
4662 * @brief Get ADC group regular behavior in case of overrun:
4663 * data preserved or overwritten.
4664 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
4665 * @param ADCx ADC instance
4666 * @retval Returned value can be one of the following values:
4667 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4668 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4669 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)4670 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
4671 {
4672 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
4673 }
4674
4675 /**
4676 * @}
4677 */
4678
4679 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
4680 * @{
4681 */
4682
4683 /**
4684 * @brief Set ADC group injected conversion trigger source:
4685 * internal (SW start) or from external peripheral (timer event,
4686 * external interrupt line).
4687 * @note On this STM32 series, setting trigger source to external trigger
4688 * also set trigger polarity to rising edge
4689 * (default setting for compatibility with some ADC on other
4690 * STM32 series having this setting set by HW default value).
4691 * In case of need to modify trigger edge, use
4692 * function @ref LL_ADC_INJ_SetTriggerEdge().
4693 * @note Availability of parameters of trigger sources from timer
4694 * depends on timers availability on the selected device.
4695 * @note On this STM32 series, setting of this feature is conditioned to
4696 * ADC state:
4697 * ADC must not be disabled. Can be enabled with or without conversion
4698 * on going on either groups regular or injected.
4699 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
4700 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
4701 * @param ADCx ADC instance
4702 * @param TriggerSource This parameter can be one of the following values:
4703 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4704 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4705 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4706 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4707 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4708 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4709 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4710 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4711 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4712 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4713 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (1)
4714 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4715 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (2)
4716 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)
4717 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)
4718 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (1)
4719 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (1)
4720 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH1
4721 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH1
4722 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4723 *
4724 * (1) On STM32H5 series, parameter specific to devices: STM32H563/H573xx.
4725 * (2) On STM32H5 series, parameter specific to devices: STM32H503xx.
4726 * @retval None
4727 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)4728 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4729 {
4730 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4731 }
4732
4733 /**
4734 * @brief Get ADC group injected conversion trigger source:
4735 * internal (SW start) or from external peripheral (timer event,
4736 * external interrupt line).
4737 * @note To determine whether group injected trigger source is
4738 * internal (SW start) or external, without detail
4739 * of which peripheral is selected as external trigger,
4740 * (equivalent to
4741 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
4742 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
4743 * @note Availability of parameters of trigger sources from timer
4744 * depends on timers availability on the selected device.
4745 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
4746 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
4747 * @param ADCx ADC instance
4748 * @retval Returned value can be one of the following values:
4749 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4750 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4751 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4752 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4753 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4754 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4755 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4756 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4757 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4758 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4759 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (1)
4760 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4761 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (2)
4762 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)
4763 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)
4764 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (1)
4765 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (1)
4766 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH1
4767 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH1
4768 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4769 *
4770 * (1) On STM32H5 series, parameter specific to devices: STM32H563/H573xx.
4771 * (2) On STM32H5 series, parameter specific to devices: STM32H503xx.
4772 */
LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef * ADCx)4773 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
4774 {
4775 __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4776
4777 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4778 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4779 uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4780
4781 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4782 /* to match with triggers literals definition. */
4783 return ((trigger_source
4784 & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
4785 | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
4786 );
4787 }
4788
4789 /**
4790 * @brief Get ADC group injected conversion trigger source internal (SW start)
4791 or external
4792 * @note In case of group injected trigger source set to external trigger,
4793 * to determine which peripheral is selected as external trigger,
4794 * use function @ref LL_ADC_INJ_GetTriggerSource.
4795 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4796 * @param ADCx ADC instance
4797 * @retval Value "0" if trigger source external trigger
4798 * Value "1" if trigger source SW start.
4799 */
LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)4800 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4801 {
4802 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4803 }
4804
4805 /**
4806 * @brief Set ADC group injected conversion trigger polarity.
4807 * Applicable only for trigger source set to external trigger.
4808 * @note On this STM32 series, setting of this feature is conditioned to
4809 * ADC state:
4810 * ADC must not be disabled. Can be enabled with or without conversion
4811 * on going on either groups regular or injected.
4812 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4813 * @param ADCx ADC instance
4814 * @param ExternalTriggerEdge This parameter can be one of the following values:
4815 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4816 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4817 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4818 * @retval None
4819 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4820 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4821 {
4822 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4823 }
4824
4825 /**
4826 * @brief Get ADC group injected conversion trigger polarity.
4827 * Applicable only for trigger source set to external trigger.
4828 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4829 * @param ADCx ADC instance
4830 * @retval Returned value can be one of the following values:
4831 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4832 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4833 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4834 */
LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef * ADCx)4835 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
4836 {
4837 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4838 }
4839
4840 /**
4841 * @brief Set ADC group injected sequencer length and scan direction.
4842 * @note This function performs configuration of:
4843 * - Sequence length: Number of ranks in the scan sequence.
4844 * - Sequence direction: Unless specified in parameters, sequencer
4845 * scan direction is forward (from rank 1 to rank n).
4846 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4847 * ADC conversion on only 1 channel.
4848 * @note On this STM32 series, setting of this feature is conditioned to
4849 * ADC state:
4850 * ADC must not be disabled. Can be enabled with or without conversion
4851 * on going on either groups regular or injected.
4852 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4853 * @param ADCx ADC instance
4854 * @param SequencerNbRanks This parameter can be one of the following values:
4855 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4856 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4857 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4858 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4859 * @retval None
4860 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4861 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4862 {
4863 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4864 }
4865
4866 /**
4867 * @brief Get ADC group injected sequencer length and scan direction.
4868 * @note This function retrieves:
4869 * - Sequence length: Number of ranks in the scan sequence.
4870 * - Sequence direction: Unless specified in parameters, sequencer
4871 * scan direction is forward (from rank 1 to rank n).
4872 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4873 * ADC conversion on only 1 channel.
4874 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4875 * @param ADCx ADC instance
4876 * @retval Returned value can be one of the following values:
4877 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4878 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4879 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4880 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4881 */
LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef * ADCx)4882 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
4883 {
4884 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4885 }
4886
4887 /**
4888 * @brief Set ADC group injected sequencer discontinuous mode:
4889 * sequence subdivided and scan conversions interrupted every selected
4890 * number of ranks.
4891 * @note It is not possible to enable both ADC group injected
4892 * auto-injected mode and sequencer discontinuous mode.
4893 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4894 * @param ADCx ADC instance
4895 * @param SeqDiscont This parameter can be one of the following values:
4896 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4897 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4898 * @retval None
4899 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4900 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4901 {
4902 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4903 }
4904
4905 /**
4906 * @brief Get ADC group injected sequencer discontinuous mode:
4907 * sequence subdivided and scan conversions interrupted every selected
4908 * number of ranks.
4909 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4910 * @param ADCx ADC instance
4911 * @retval Returned value can be one of the following values:
4912 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4913 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4914 */
LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef * ADCx)4915 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4916 {
4917 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4918 }
4919
4920 /**
4921 * @brief Set ADC group injected sequence: channel on the selected
4922 * sequence rank.
4923 * @note Depending on devices and packages, some channels may not be available.
4924 * Refer to device datasheet for channels availability.
4925 * @note On this STM32 series, to measure internal channels (VrefInt,
4926 * TempSensor, ...), measurement paths to internal channels must be
4927 * enabled separately.
4928 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4929 * @note On STM32H5, some fast channels are available: fast analog inputs
4930 * coming from GPIO pads (ADC_IN0..5).
4931 * @note On this STM32 series, setting of this feature is conditioned to
4932 * ADC state:
4933 * ADC must not be disabled. Can be enabled with or without conversion
4934 * on going on either groups regular or injected.
4935 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4936 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4937 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4938 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4939 * @param ADCx ADC instance
4940 * @param Rank This parameter can be one of the following values:
4941 * @arg @ref LL_ADC_INJ_RANK_1
4942 * @arg @ref LL_ADC_INJ_RANK_2
4943 * @arg @ref LL_ADC_INJ_RANK_3
4944 * @arg @ref LL_ADC_INJ_RANK_4
4945 * @param Channel This parameter can be one of the following values:
4946 * @arg @ref LL_ADC_CHANNEL_0 (3)
4947 * @arg @ref LL_ADC_CHANNEL_1 (3)
4948 * @arg @ref LL_ADC_CHANNEL_2 (3)
4949 * @arg @ref LL_ADC_CHANNEL_3 (3)
4950 * @arg @ref LL_ADC_CHANNEL_4 (3)
4951 * @arg @ref LL_ADC_CHANNEL_5 (3)
4952 * @arg @ref LL_ADC_CHANNEL_6
4953 * @arg @ref LL_ADC_CHANNEL_7
4954 * @arg @ref LL_ADC_CHANNEL_8
4955 * @arg @ref LL_ADC_CHANNEL_9
4956 * @arg @ref LL_ADC_CHANNEL_10
4957 * @arg @ref LL_ADC_CHANNEL_11
4958 * @arg @ref LL_ADC_CHANNEL_12
4959 * @arg @ref LL_ADC_CHANNEL_13
4960 * @arg @ref LL_ADC_CHANNEL_14
4961 * @arg @ref LL_ADC_CHANNEL_15
4962 * @arg @ref LL_ADC_CHANNEL_16
4963 * @arg @ref LL_ADC_CHANNEL_17
4964 * @arg @ref LL_ADC_CHANNEL_18
4965 * @arg @ref LL_ADC_CHANNEL_19
4966 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4967 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4968 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
4969 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
4970 *
4971 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
4972 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
4973 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
4974 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
4975 * @retval None
4976 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4977 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4978 {
4979 /* Set bits with content of parameter "Channel" with bits position */
4980 /* in register depending on parameter "Rank". */
4981 /* Parameters "Rank" and "Channel" are used with masks because containing */
4982 /* other bits reserved for other purpose. */
4983 MODIFY_REG(ADCx->JSQR,
4984 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4985 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4986 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4987 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4988 }
4989
4990 /**
4991 * @brief Get ADC group injected sequence: channel on the selected
4992 * sequence rank.
4993 * @note Depending on devices and packages, some channels may not be available.
4994 * Refer to device datasheet for channels availability.
4995 * @note Usage of the returned channel number:
4996 * - To reinject this channel into another function LL_ADC_xxx:
4997 * the returned channel number is only partly formatted on definition
4998 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4999 * with parts of literals LL_ADC_CHANNEL_x or using
5000 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5001 * Then the selected literal LL_ADC_CHANNEL_x can be used
5002 * as parameter for another function.
5003 * - To get the channel number in decimal format:
5004 * process the returned value with the helper macro
5005 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5006 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
5007 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
5008 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
5009 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
5010 * @param ADCx ADC instance
5011 * @param Rank This parameter can be one of the following values:
5012 * @arg @ref LL_ADC_INJ_RANK_1
5013 * @arg @ref LL_ADC_INJ_RANK_2
5014 * @arg @ref LL_ADC_INJ_RANK_3
5015 * @arg @ref LL_ADC_INJ_RANK_4
5016 * @retval Returned value can be one of the following values:
5017 * @arg @ref LL_ADC_CHANNEL_0 (3)
5018 * @arg @ref LL_ADC_CHANNEL_1 (3)
5019 * @arg @ref LL_ADC_CHANNEL_2 (3)
5020 * @arg @ref LL_ADC_CHANNEL_3 (3)
5021 * @arg @ref LL_ADC_CHANNEL_4 (3)
5022 * @arg @ref LL_ADC_CHANNEL_5 (3)
5023 * @arg @ref LL_ADC_CHANNEL_6
5024 * @arg @ref LL_ADC_CHANNEL_7
5025 * @arg @ref LL_ADC_CHANNEL_8
5026 * @arg @ref LL_ADC_CHANNEL_9
5027 * @arg @ref LL_ADC_CHANNEL_10
5028 * @arg @ref LL_ADC_CHANNEL_11
5029 * @arg @ref LL_ADC_CHANNEL_12
5030 * @arg @ref LL_ADC_CHANNEL_13
5031 * @arg @ref LL_ADC_CHANNEL_14
5032 * @arg @ref LL_ADC_CHANNEL_15
5033 * @arg @ref LL_ADC_CHANNEL_16
5034 * @arg @ref LL_ADC_CHANNEL_17
5035 * @arg @ref LL_ADC_CHANNEL_18
5036 * @arg @ref LL_ADC_CHANNEL_19
5037 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(4)
5038 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(4)
5039 * @arg @ref LL_ADC_CHANNEL_VBAT (2)(4)
5040 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)(4)
5041 *
5042 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
5043 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
5044 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5045 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5046 * (4) For ADC channel read back from ADC register,
5047 * comparison with internal channel parameter to be done
5048 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
5049 */
LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)5050 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
5051 {
5052 return (uint32_t)((READ_BIT(ADCx->JSQR,
5053 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5054 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
5055 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
5056 );
5057 }
5058
5059 /**
5060 * @brief Set ADC group injected conversion trigger:
5061 * independent or from ADC group regular.
5062 * @note This mode can be used to extend number of data registers
5063 * updated after one ADC conversion trigger and with data
5064 * permanently kept (not erased by successive conversions of scan of
5065 * ADC sequencer ranks), up to 5 data registers:
5066 * 1 data register on ADC group regular, 4 data registers
5067 * on ADC group injected.
5068 * @note If ADC group injected injected trigger source is set to an
5069 * external trigger, this feature must be must be set to
5070 * independent trigger.
5071 * ADC group injected automatic trigger is compliant only with
5072 * group injected trigger source set to SW start, without any
5073 * further action on ADC group injected conversion start or stop:
5074 * in this case, ADC group injected is controlled only
5075 * from ADC group regular.
5076 * @note It is not possible to enable both ADC group injected
5077 * auto-injected mode and sequencer discontinuous mode.
5078 * @note On this STM32 series, setting of this feature is conditioned to
5079 * ADC state:
5080 * ADC must be disabled or enabled without conversion on going
5081 * on either groups regular or injected.
5082 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
5083 * @param ADCx ADC instance
5084 * @param TrigAuto This parameter can be one of the following values:
5085 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5086 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5087 * @retval None
5088 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)5089 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
5090 {
5091 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
5092 }
5093
5094 /**
5095 * @brief Get ADC group injected conversion trigger:
5096 * independent or from ADC group regular.
5097 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
5098 * @param ADCx ADC instance
5099 * @retval Returned value can be one of the following values:
5100 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5101 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5102 */
LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef * ADCx)5103 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
5104 {
5105 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
5106 }
5107
5108 /**
5109 * @brief Set ADC group injected contexts queue mode.
5110 * @note A context is a setting of group injected sequencer:
5111 * - group injected trigger
5112 * - sequencer length
5113 * - sequencer ranks
5114 * If contexts queue is disabled:
5115 * - only 1 sequence can be configured
5116 * and is active perpetually.
5117 * If contexts queue is enabled:
5118 * - up to 2 contexts can be queued
5119 * and are checked in and out as a FIFO stack (first-in, first-out).
5120 * - If a new context is set when queues is full, error is triggered
5121 * by interruption "Injected Queue Overflow".
5122 * - Two behaviors are possible when all contexts have been processed:
5123 * the contexts queue can maintain the last context active perpetually
5124 * or can be empty and injected group triggers are disabled.
5125 * - Triggers can be only external (not internal SW start)
5126 * - Caution: The sequence must be fully configured in one time
5127 * (one write of register JSQR makes a check-in of a new context
5128 * into the queue).
5129 * Therefore functions to set separately injected trigger and
5130 * sequencer channels cannot be used, register JSQR must be set
5131 * using function @ref LL_ADC_INJ_ConfigQueueContext().
5132 * @note This parameter can be modified only when no conversion is on going
5133 * on either groups regular or injected.
5134 * @note A modification of the context mode (bit JQDIS) causes the contexts
5135 * queue to be flushed and the register JSQR is cleared.
5136 * @note On this STM32 series, setting of this feature is conditioned to
5137 * ADC state:
5138 * ADC must be disabled or enabled without conversion on going
5139 * on either groups regular or injected.
5140 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
5141 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
5142 * @param ADCx ADC instance
5143 * @param QueueMode This parameter can be one of the following values:
5144 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5145 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5146 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5147 * @retval None
5148 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)5149 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
5150 {
5151 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
5152 }
5153
5154 /**
5155 * @brief Get ADC group injected context queue mode.
5156 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
5157 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
5158 * @param ADCx ADC instance
5159 * @retval Returned value can be one of the following values:
5160 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5161 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5162 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5163 */
LL_ADC_INJ_GetQueueMode(const ADC_TypeDef * ADCx)5164 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx)
5165 {
5166 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
5167 }
5168
5169 /**
5170 * @brief Set one context on ADC group injected that will be checked in
5171 * contexts queue.
5172 * @note A context is a setting of group injected sequencer:
5173 * - group injected trigger
5174 * - sequencer length
5175 * - sequencer ranks
5176 * This function is intended to be used when contexts queue is enabled,
5177 * because the sequence must be fully configured in one time
5178 * (functions to set separately injected trigger and sequencer channels
5179 * cannot be used):
5180 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
5181 * @note In the contexts queue, only the active context can be read.
5182 * The parameters of this function can be read using functions:
5183 * @arg @ref LL_ADC_INJ_GetTriggerSource()
5184 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
5185 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
5186 * @note On this STM32 series, to measure internal channels (VrefInt,
5187 * TempSensor, ...), measurement paths to internal channels must be
5188 * enabled separately.
5189 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5190 * @note On STM32H5, some fast channels are available: fast analog inputs
5191 * coming from GPIO pads (ADC_IN0..5).
5192 * @note On this STM32 series, setting of this feature is conditioned to
5193 * ADC state:
5194 * ADC must not be disabled. Can be enabled with or without conversion
5195 * on going on either groups regular or injected.
5196 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
5197 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
5198 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
5199 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
5200 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
5201 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
5202 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
5203 * @param ADCx ADC instance
5204 * @param TriggerSource This parameter can be one of the following values:
5205 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5206 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5207 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5208 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5209 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5210 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
5211 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5212 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
5213 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
5214 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
5215 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (1)
5216 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5217 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (2)
5218 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)
5219 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)
5220 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (1)
5221 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (1)
5222 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH1
5223 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH1
5224 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
5225 *
5226 * (1) On STM32H5 series, parameter specific to devices: STM32H563/H573xx.
5227 * (2) On STM32H5 series, parameter specific to devices: STM32H503xx.
5228 * @param ExternalTriggerEdge This parameter can be one of the following values:
5229 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5230 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5231 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5232 *
5233 * Note: This parameter is discarded in case of SW start:
5234 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
5235 * @param SequencerNbRanks This parameter can be one of the following values:
5236 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5237 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5238 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5239 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5240 * @param Rank1_Channel This parameter can be one of the following values:
5241 * @arg @ref LL_ADC_CHANNEL_0 (3)
5242 * @arg @ref LL_ADC_CHANNEL_1 (3)
5243 * @arg @ref LL_ADC_CHANNEL_2 (3)
5244 * @arg @ref LL_ADC_CHANNEL_3 (3)
5245 * @arg @ref LL_ADC_CHANNEL_4 (3)
5246 * @arg @ref LL_ADC_CHANNEL_5 (3)
5247 * @arg @ref LL_ADC_CHANNEL_6
5248 * @arg @ref LL_ADC_CHANNEL_7
5249 * @arg @ref LL_ADC_CHANNEL_8
5250 * @arg @ref LL_ADC_CHANNEL_9
5251 * @arg @ref LL_ADC_CHANNEL_10
5252 * @arg @ref LL_ADC_CHANNEL_11
5253 * @arg @ref LL_ADC_CHANNEL_12
5254 * @arg @ref LL_ADC_CHANNEL_13
5255 * @arg @ref LL_ADC_CHANNEL_14
5256 * @arg @ref LL_ADC_CHANNEL_15
5257 * @arg @ref LL_ADC_CHANNEL_16
5258 * @arg @ref LL_ADC_CHANNEL_17
5259 * @arg @ref LL_ADC_CHANNEL_18
5260 * @arg @ref LL_ADC_CHANNEL_19
5261 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5262 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5263 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
5264 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
5265 *
5266 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
5267 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
5268 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5269 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5270 * @param Rank2_Channel This parameter can be one of the following values:
5271 * @arg @ref LL_ADC_CHANNEL_0 (3)
5272 * @arg @ref LL_ADC_CHANNEL_1 (3)
5273 * @arg @ref LL_ADC_CHANNEL_2 (3)
5274 * @arg @ref LL_ADC_CHANNEL_3 (3)
5275 * @arg @ref LL_ADC_CHANNEL_4 (3)
5276 * @arg @ref LL_ADC_CHANNEL_5 (3)
5277 * @arg @ref LL_ADC_CHANNEL_6
5278 * @arg @ref LL_ADC_CHANNEL_7
5279 * @arg @ref LL_ADC_CHANNEL_8
5280 * @arg @ref LL_ADC_CHANNEL_9
5281 * @arg @ref LL_ADC_CHANNEL_10
5282 * @arg @ref LL_ADC_CHANNEL_11
5283 * @arg @ref LL_ADC_CHANNEL_12
5284 * @arg @ref LL_ADC_CHANNEL_13
5285 * @arg @ref LL_ADC_CHANNEL_14
5286 * @arg @ref LL_ADC_CHANNEL_15
5287 * @arg @ref LL_ADC_CHANNEL_16
5288 * @arg @ref LL_ADC_CHANNEL_17
5289 * @arg @ref LL_ADC_CHANNEL_18
5290 * @arg @ref LL_ADC_CHANNEL_19
5291 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5292 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5293 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
5294 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
5295 *
5296 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
5297 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
5298 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5299 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5300 * @param Rank3_Channel This parameter can be one of the following values:
5301 * @arg @ref LL_ADC_CHANNEL_0 (3)
5302 * @arg @ref LL_ADC_CHANNEL_1 (3)
5303 * @arg @ref LL_ADC_CHANNEL_2 (3)
5304 * @arg @ref LL_ADC_CHANNEL_3 (3)
5305 * @arg @ref LL_ADC_CHANNEL_4 (3)
5306 * @arg @ref LL_ADC_CHANNEL_5 (3)
5307 * @arg @ref LL_ADC_CHANNEL_6
5308 * @arg @ref LL_ADC_CHANNEL_7
5309 * @arg @ref LL_ADC_CHANNEL_8
5310 * @arg @ref LL_ADC_CHANNEL_9
5311 * @arg @ref LL_ADC_CHANNEL_10
5312 * @arg @ref LL_ADC_CHANNEL_11
5313 * @arg @ref LL_ADC_CHANNEL_12
5314 * @arg @ref LL_ADC_CHANNEL_13
5315 * @arg @ref LL_ADC_CHANNEL_14
5316 * @arg @ref LL_ADC_CHANNEL_15
5317 * @arg @ref LL_ADC_CHANNEL_16
5318 * @arg @ref LL_ADC_CHANNEL_17
5319 * @arg @ref LL_ADC_CHANNEL_18
5320 * @arg @ref LL_ADC_CHANNEL_19
5321 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5322 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5323 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
5324 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
5325 *
5326 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
5327 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
5328 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5329 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5330 * @param Rank4_Channel This parameter can be one of the following values:
5331 * @arg @ref LL_ADC_CHANNEL_0 (3)
5332 * @arg @ref LL_ADC_CHANNEL_1 (3)
5333 * @arg @ref LL_ADC_CHANNEL_2 (3)
5334 * @arg @ref LL_ADC_CHANNEL_3 (3)
5335 * @arg @ref LL_ADC_CHANNEL_4 (3)
5336 * @arg @ref LL_ADC_CHANNEL_5 (3)
5337 * @arg @ref LL_ADC_CHANNEL_6
5338 * @arg @ref LL_ADC_CHANNEL_7
5339 * @arg @ref LL_ADC_CHANNEL_8
5340 * @arg @ref LL_ADC_CHANNEL_9
5341 * @arg @ref LL_ADC_CHANNEL_10
5342 * @arg @ref LL_ADC_CHANNEL_11
5343 * @arg @ref LL_ADC_CHANNEL_12
5344 * @arg @ref LL_ADC_CHANNEL_13
5345 * @arg @ref LL_ADC_CHANNEL_14
5346 * @arg @ref LL_ADC_CHANNEL_15
5347 * @arg @ref LL_ADC_CHANNEL_16
5348 * @arg @ref LL_ADC_CHANNEL_17
5349 * @arg @ref LL_ADC_CHANNEL_18
5350 * @arg @ref LL_ADC_CHANNEL_19
5351 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5352 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5353 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
5354 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
5355 *
5356 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
5357 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
5358 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5359 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5360 * @retval None
5361 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)5362 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
5363 uint32_t TriggerSource,
5364 uint32_t ExternalTriggerEdge,
5365 uint32_t SequencerNbRanks,
5366 uint32_t Rank1_Channel,
5367 uint32_t Rank2_Channel,
5368 uint32_t Rank3_Channel,
5369 uint32_t Rank4_Channel)
5370 {
5371 /* Set bits with content of parameter "Rankx_Channel" with bits position */
5372 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
5373 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
5374 /* because containing other bits reserved for other purpose. */
5375 /* If parameter "TriggerSource" is set to SW start, then parameter */
5376 /* "ExternalTriggerEdge" is discarded. */
5377 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
5378 MODIFY_REG(ADCx->JSQR,
5379 ADC_JSQR_JEXTSEL |
5380 ADC_JSQR_JEXTEN |
5381 ADC_JSQR_JSQ4 |
5382 ADC_JSQR_JSQ3 |
5383 ADC_JSQR_JSQ2 |
5384 ADC_JSQR_JSQ1 |
5385 ADC_JSQR_JL,
5386 (TriggerSource & ADC_JSQR_JEXTSEL) |
5387 (ExternalTriggerEdge * (is_trigger_not_sw)) |
5388 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5389 << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5390 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5391 << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5392 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5393 << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5394 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5395 << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5396 SequencerNbRanks
5397 );
5398 }
5399
5400 /**
5401 * @}
5402 */
5403
5404 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
5405 * @{
5406 */
5407
5408 /**
5409 * @brief Set sampling time of the selected ADC channel
5410 * Unit: ADC clock cycles.
5411 * @note On this device, sampling time is on channel scope: independently
5412 * of channel mapped on ADC group regular or injected.
5413 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
5414 * converted:
5415 * sampling time constraints must be respected (sampling time can be
5416 * adjusted in function of ADC clock frequency and sampling time
5417 * setting).
5418 * Refer to device datasheet for timings values (parameters TS_vrefint,
5419 * TS_temp, ...).
5420 * @note Conversion time is the addition of sampling time and processing time.
5421 * On this STM32 series, ADC processing time is:
5422 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5423 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5424 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5425 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5426 * @note In case of ADC conversion of internal channel (VrefInt,
5427 * temperature sensor, ...), a sampling time minimum value
5428 * is required.
5429 * Refer to device datasheet.
5430 * @note On this STM32 series, setting of this feature is conditioned to
5431 * ADC state:
5432 * ADC must be disabled or enabled without conversion on going
5433 * on either groups regular or injected.
5434 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
5435 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
5436 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
5437 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
5438 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
5439 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
5440 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
5441 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
5442 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
5443 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
5444 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
5445 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
5446 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
5447 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
5448 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
5449 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
5450 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
5451 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
5452 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
5453 * @param ADCx ADC instance
5454 * @param Channel This parameter can be one of the following values:
5455 * @arg @ref LL_ADC_CHANNEL_0 (3)
5456 * @arg @ref LL_ADC_CHANNEL_1 (3)
5457 * @arg @ref LL_ADC_CHANNEL_2 (3)
5458 * @arg @ref LL_ADC_CHANNEL_3 (3)
5459 * @arg @ref LL_ADC_CHANNEL_4 (3)
5460 * @arg @ref LL_ADC_CHANNEL_5 (3)
5461 * @arg @ref LL_ADC_CHANNEL_6
5462 * @arg @ref LL_ADC_CHANNEL_7
5463 * @arg @ref LL_ADC_CHANNEL_8
5464 * @arg @ref LL_ADC_CHANNEL_9
5465 * @arg @ref LL_ADC_CHANNEL_10
5466 * @arg @ref LL_ADC_CHANNEL_11
5467 * @arg @ref LL_ADC_CHANNEL_12
5468 * @arg @ref LL_ADC_CHANNEL_13
5469 * @arg @ref LL_ADC_CHANNEL_14
5470 * @arg @ref LL_ADC_CHANNEL_15
5471 * @arg @ref LL_ADC_CHANNEL_16
5472 * @arg @ref LL_ADC_CHANNEL_17
5473 * @arg @ref LL_ADC_CHANNEL_18
5474 * @arg @ref LL_ADC_CHANNEL_19
5475 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5476 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5477 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
5478 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
5479 *
5480 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
5481 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
5482 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5483 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5484 * @param SamplingTime This parameter can be one of the following values:
5485 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5486 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5487 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5488 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5489 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5490 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5491 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5492 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5493 *
5494 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5495 * can be replaced by 3.5 ADC clock cycles.
5496 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5497 * @retval None
5498 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)5499 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
5500 {
5501 /* Set bits with content of parameter "SamplingTime" with bits position */
5502 /* in register and register position depending on parameter "Channel". */
5503 /* Parameter "Channel" is used with masks because containing */
5504 /* other bits reserved for other purpose. */
5505 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
5506 ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5507
5508 MODIFY_REG(*preg,
5509 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
5510 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
5511 }
5512
5513 /**
5514 * @brief Get sampling time of the selected ADC channel
5515 * Unit: ADC clock cycles.
5516 * @note On this device, sampling time is on channel scope: independently
5517 * of channel mapped on ADC group regular or injected.
5518 * @note Conversion time is the addition of sampling time and processing time.
5519 * On this STM32 series, ADC processing time is:
5520 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5521 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5522 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5523 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5524 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
5525 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
5526 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
5527 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
5528 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
5529 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
5530 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
5531 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
5532 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
5533 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
5534 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
5535 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
5536 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
5537 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
5538 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
5539 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
5540 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
5541 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
5542 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
5543 * @param ADCx ADC instance
5544 * @param Channel This parameter can be one of the following values:
5545 * @arg @ref LL_ADC_CHANNEL_0 (3)
5546 * @arg @ref LL_ADC_CHANNEL_1 (3)
5547 * @arg @ref LL_ADC_CHANNEL_2 (3)
5548 * @arg @ref LL_ADC_CHANNEL_3 (3)
5549 * @arg @ref LL_ADC_CHANNEL_4 (3)
5550 * @arg @ref LL_ADC_CHANNEL_5 (3)
5551 * @arg @ref LL_ADC_CHANNEL_6
5552 * @arg @ref LL_ADC_CHANNEL_7
5553 * @arg @ref LL_ADC_CHANNEL_8
5554 * @arg @ref LL_ADC_CHANNEL_9
5555 * @arg @ref LL_ADC_CHANNEL_10
5556 * @arg @ref LL_ADC_CHANNEL_11
5557 * @arg @ref LL_ADC_CHANNEL_12
5558 * @arg @ref LL_ADC_CHANNEL_13
5559 * @arg @ref LL_ADC_CHANNEL_14
5560 * @arg @ref LL_ADC_CHANNEL_15
5561 * @arg @ref LL_ADC_CHANNEL_16
5562 * @arg @ref LL_ADC_CHANNEL_17
5563 * @arg @ref LL_ADC_CHANNEL_18
5564 * @arg @ref LL_ADC_CHANNEL_19
5565 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5566 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5567 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
5568 * @arg @ref LL_ADC_CHANNEL_VDDCORE (2)
5569 *
5570 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n
5571 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n
5572 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC)
5573 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC)
5574 * @retval Returned value can be one of the following values:
5575 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5576 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5577 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5578 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5579 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5580 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5581 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5582 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5583 *
5584 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5585 * can be replaced by 3.5 ADC clock cycles.
5586 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5587 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)5588 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
5589 {
5590 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK)
5591 >> ADC_SMPRX_REGOFFSET_POS));
5592
5593 return (uint32_t)(READ_BIT(*preg,
5594 ADC_SMPR1_SMP0
5595 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5596 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5597 );
5598 }
5599
5600 /**
5601 * @brief Set mode single-ended or differential input of the selected
5602 * ADC channel.
5603 * @note Channel ending is on channel scope: independently of channel mapped
5604 * on ADC group regular or injected.
5605 * In differential mode: Differential measurement is carried out
5606 * between the selected channel 'i' (positive input) and
5607 * channel 'i+1' (negative input). Only channel 'i' has to be
5608 * configured, channel 'i+1' is configured automatically.
5609 * @note Refer to Reference Manual to ensure the selected channel is
5610 * available in differential mode.
5611 * For example, internal channels (VrefInt, TempSensor, ...) are
5612 * not available in differential mode.
5613 * @note When configuring a channel 'i' in differential mode,
5614 * the channel 'i+1' is not usable separately.
5615 * @note For ADC channels configured in differential mode, both inputs
5616 * should be biased at (Vref+)/2 +/-200mV.
5617 * (Vref+ is the analog voltage reference)
5618 * @note On this STM32 series, setting of this feature is conditioned to
5619 * ADC state:
5620 * ADC must be ADC disabled.
5621 * @note One or several values can be selected.
5622 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5623 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
5624 * @param ADCx ADC instance
5625 * @param Channel This parameter can be one of the following values:
5626 * @arg @ref LL_ADC_CHANNEL_1
5627 * @arg @ref LL_ADC_CHANNEL_2
5628 * @arg @ref LL_ADC_CHANNEL_3
5629 * @arg @ref LL_ADC_CHANNEL_4
5630 * @arg @ref LL_ADC_CHANNEL_5
5631 * @arg @ref LL_ADC_CHANNEL_6
5632 * @arg @ref LL_ADC_CHANNEL_7
5633 * @arg @ref LL_ADC_CHANNEL_8
5634 * @arg @ref LL_ADC_CHANNEL_9
5635 * @arg @ref LL_ADC_CHANNEL_10
5636 * @arg @ref LL_ADC_CHANNEL_11
5637 * @arg @ref LL_ADC_CHANNEL_12
5638 * @arg @ref LL_ADC_CHANNEL_13
5639 * @arg @ref LL_ADC_CHANNEL_14
5640 * @arg @ref LL_ADC_CHANNEL_15
5641 * @param SingleDiff This parameter can be a combination of the following values:
5642 * @arg @ref LL_ADC_SINGLE_ENDED
5643 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5644 * @retval None
5645 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)5646 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5647 {
5648 /* Bits of channels in single or differential mode are set only for */
5649 /* differential mode (for single mode, mask of bits allowed to be set is */
5650 /* shifted out of range of bits of channels in single or differential mode. */
5651 MODIFY_REG(ADCx->DIFSEL,
5652 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5653 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
5654 & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5655 }
5656
5657 /**
5658 * @brief Get mode single-ended or differential input of the selected
5659 * ADC channel.
5660 * @note When configuring a channel 'i' in differential mode,
5661 * the channel 'i+1' is not usable separately.
5662 * Therefore, to ensure a channel is configured in single-ended mode,
5663 * the configuration of channel itself and the channel 'i-1' must be
5664 * read back (to ensure that the selected channel channel has not been
5665 * configured in differential mode by the previous channel).
5666 * @note Refer to Reference Manual to ensure the selected channel is
5667 * available in differential mode.
5668 * For example, internal channels (VrefInt, TempSensor, ...) are
5669 * not available in differential mode.
5670 * @note When configuring a channel 'i' in differential mode,
5671 * the channel 'i+1' is not usable separately.
5672 * @note One or several values can be selected. In this case, the value
5673 * returned is null if all channels are in single ended-mode.
5674 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5675 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
5676 * @param ADCx ADC instance
5677 * @param Channel This parameter can be a combination of the following values:
5678 * @arg @ref LL_ADC_CHANNEL_1
5679 * @arg @ref LL_ADC_CHANNEL_2
5680 * @arg @ref LL_ADC_CHANNEL_3
5681 * @arg @ref LL_ADC_CHANNEL_4
5682 * @arg @ref LL_ADC_CHANNEL_5
5683 * @arg @ref LL_ADC_CHANNEL_6
5684 * @arg @ref LL_ADC_CHANNEL_7
5685 * @arg @ref LL_ADC_CHANNEL_8
5686 * @arg @ref LL_ADC_CHANNEL_9
5687 * @arg @ref LL_ADC_CHANNEL_10
5688 * @arg @ref LL_ADC_CHANNEL_11
5689 * @arg @ref LL_ADC_CHANNEL_12
5690 * @arg @ref LL_ADC_CHANNEL_13
5691 * @arg @ref LL_ADC_CHANNEL_14
5692 * @arg @ref LL_ADC_CHANNEL_15
5693 * @retval 0: channel in single-ended mode, else: channel in differential mode
5694 */
LL_ADC_GetChannelSingleDiff(const ADC_TypeDef * ADCx,uint32_t Channel)5695 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
5696 {
5697 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5698 }
5699
5700 /**
5701 * @}
5702 */
5703
5704 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5705 * @{
5706 */
5707
5708 /**
5709 * @brief Set ADC analog watchdog monitored channels:
5710 * a single channel, multiple channels or all channels,
5711 * on ADC groups regular and-or injected.
5712 * @note Once monitored channels are selected, analog watchdog
5713 * is enabled.
5714 * @note In case of need to define a single channel to monitor
5715 * with analog watchdog from sequencer channel definition,
5716 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5717 * @note On this STM32 series, there are 2 kinds of analog watchdog
5718 * instance:
5719 * - AWD standard (instance AWD1):
5720 * - channels monitored: can monitor 1 channel or all channels.
5721 * - groups monitored: ADC groups regular and-or injected.
5722 * - resolution: resolution is not limited (corresponds to
5723 * ADC resolution configured).
5724 * - AWD flexible (instances AWD2, AWD3):
5725 * - channels monitored: flexible on channels monitored, selection is
5726 * channel wise, from from 1 to all channels.
5727 * Specificity of this analog watchdog: Multiple channels can
5728 * be selected. For example:
5729 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5730 * - groups monitored: not selection possible (monitoring on both
5731 * groups regular and injected).
5732 * Channels selected are monitored on groups regular and injected:
5733 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5734 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5735 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5736 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5737 * the 2 LSB are ignored.
5738 * @note On this STM32 series, setting of this feature is conditioned to
5739 * ADC state:
5740 * ADC must be disabled or enabled without conversion on going
5741 * on either groups regular or injected.
5742 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5743 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5744 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5745 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5746 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5747 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5748 * @param ADCx ADC instance
5749 * @param AWDy This parameter can be one of the following values:
5750 * @arg @ref LL_ADC_AWD1
5751 * @arg @ref LL_ADC_AWD2
5752 * @arg @ref LL_ADC_AWD3
5753 * @param AWDChannelGroup This parameter can be one of the following values:
5754 * @arg @ref LL_ADC_AWD_DISABLE
5755 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5756 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5757 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5758 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5759 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5760 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5761 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5762 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5763 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5764 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5765 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5766 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5767 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5768 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5769 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5770 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5771 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5772 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5773 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5774 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5775 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5776 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5777 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5778 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5779 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5780 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5781 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5782 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5783 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5784 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5785 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5786 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5787 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5788 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5789 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5790 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5791 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5792 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5793 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5794 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5795 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5796 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5797 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5798 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5799 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5800 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5801 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5802 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5803 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5804 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5805 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5806 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5807 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5808 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5809 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5810 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5811 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5812 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5813 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5814 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5815 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
5816 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
5817 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
5818 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
5819 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
5820 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
5821 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
5822 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
5823 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
5824 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(2)
5825 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(2)
5826 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (2)
5827 * @arg @ref LL_ADC_AWD_CH_VDDCORE_REG (0)(2)
5828 * @arg @ref LL_ADC_AWD_CH_VDDCORE_INJ (0)(2)
5829 * @arg @ref LL_ADC_AWD_CH_VDDCORE_REG_INJ (2)
5830 *
5831 * (0) On STM32H5, parameter available only on analog watchdog number: AWD1.\n
5832 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.
5833 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.
5834 * @retval None
5835 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)5836 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5837 {
5838 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5839 /* in register and register position depending on parameter "AWDy". */
5840 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5841 /* containing other bits reserved for other purpose. */
5842 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
5843 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5844 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
5845 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5846
5847 MODIFY_REG(*preg,
5848 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5849 AWDChannelGroup & AWDy);
5850 }
5851
5852 /**
5853 * @brief Get ADC analog watchdog monitored channel.
5854 * @note Usage of the returned channel number:
5855 * - To reinject this channel into another function LL_ADC_xxx:
5856 * the returned channel number is only partly formatted on definition
5857 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5858 * with parts of literals LL_ADC_CHANNEL_x or using
5859 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5860 * Then the selected literal LL_ADC_CHANNEL_x can be used
5861 * as parameter for another function.
5862 * - To get the channel number in decimal format:
5863 * process the returned value with the helper macro
5864 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5865 * Applicable only when the analog watchdog is set to monitor
5866 * one channel.
5867 * @note On this STM32 series, there are 2 kinds of analog watchdog
5868 * instance:
5869 * - AWD standard (instance AWD1):
5870 * - channels monitored: can monitor 1 channel or all channels.
5871 * - groups monitored: ADC groups regular and-or injected.
5872 * - resolution: resolution is not limited (corresponds to
5873 * ADC resolution configured).
5874 * - AWD flexible (instances AWD2, AWD3):
5875 * - channels monitored: flexible on channels monitored, selection is
5876 * channel wise, from from 1 to all channels.
5877 * Specificity of this analog watchdog: Multiple channels can
5878 * be selected. For example:
5879 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5880 * - groups monitored: not selection possible (monitoring on both
5881 * groups regular and injected).
5882 * Channels selected are monitored on groups regular and injected:
5883 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5884 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5885 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5886 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5887 * the 2 LSB are ignored.
5888 * @note On this STM32 series, setting of this feature is conditioned to
5889 * ADC state:
5890 * ADC must be disabled or enabled without conversion on going
5891 * on either groups regular or injected.
5892 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5893 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5894 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5895 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5896 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5897 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5898 * @param ADCx ADC instance
5899 * @param AWDy This parameter can be one of the following values:
5900 * @arg @ref LL_ADC_AWD1
5901 * @arg @ref LL_ADC_AWD2 (1)
5902 * @arg @ref LL_ADC_AWD3 (1)
5903 *
5904 * (1) On this AWD number, monitored channel can be retrieved
5905 * if only 1 channel is programmed (or none or all channels).
5906 * This function cannot retrieve monitored channel if
5907 * multiple channels are programmed simultaneously
5908 * by bitfield.
5909 * @retval Returned value can be one of the following values:
5910 * @arg @ref LL_ADC_AWD_DISABLE
5911 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5912 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5913 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5914 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5915 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5916 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5917 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5918 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5919 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5920 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5921 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5922 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5923 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5924 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5925 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5926 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5927 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5928 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5929 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5930 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5931 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5932 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5933 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5934 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5935 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5936 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5937 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5938 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5939 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5940 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5941 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5942 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5943 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5944 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5945 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5946 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5947 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5948 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5949 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5950 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5951 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5952 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5953 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5954 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5955 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5956 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5957 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5958 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5959 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5960 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5961 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5962 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5963 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5964 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5965 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5966 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5967 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5968 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5969 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5970 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5971 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
5972 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
5973 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
5974 *
5975 * (0) On STM32H5, parameter available only on analog watchdog number: AWD1.
5976 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)5977 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
5978 {
5979 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
5980 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5981 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
5982 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5983
5984 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5985
5986 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
5987 /* (parameter value LL_ADC_AWD_DISABLE). */
5988 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5989 /* or a single channel. */
5990 if (analog_wd_monit_channels != 0UL)
5991 {
5992 if (AWDy == LL_ADC_AWD1)
5993 {
5994 if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL)
5995 {
5996 /* AWD monitoring a group of channels */
5997 analog_wd_monit_channels = ((analog_wd_monit_channels
5998 | (ADC_AWD_CR23_CHANNEL_MASK)
5999 )
6000 & (~(ADC_CFGR_AWD1CH))
6001 );
6002 }
6003 else
6004 {
6005 /* AWD monitoring a single channel */
6006 analog_wd_monit_channels = (analog_wd_monit_channels
6007 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos))
6008 );
6009 }
6010 }
6011 else
6012 {
6013 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
6014 {
6015 /* AWD monitoring a group of channels */
6016 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
6017 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
6018 );
6019 }
6020 else
6021 {
6022 /* AWD monitoring a single channel */
6023 /* AWD monitoring a group of channels */
6024 analog_wd_monit_channels = (analog_wd_monit_channels
6025 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
6026 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos)
6027 );
6028 }
6029 }
6030 }
6031
6032 return analog_wd_monit_channels;
6033 }
6034
6035 /**
6036 * @brief Set ADC analog watchdog thresholds value of both thresholds
6037 * high and low.
6038 * @note If value of only one threshold high or low must be set,
6039 * use function @ref LL_ADC_SetAnalogWDThresholds().
6040 * @note In case of ADC resolution different of 12 bits,
6041 * analog watchdog thresholds data require a specific shift.
6042 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
6043 * @note On this STM32 series, there are 2 kinds of analog watchdog
6044 * instance:
6045 * - AWD standard (instance AWD1):
6046 * - channels monitored: can monitor 1 channel or all channels.
6047 * - groups monitored: ADC groups regular and-or injected.
6048 * - resolution: resolution is not limited (corresponds to
6049 * ADC resolution configured).
6050 * - AWD flexible (instances AWD2, AWD3):
6051 * - channels monitored: flexible on channels monitored, selection is
6052 * channel wise, from from 1 to all channels.
6053 * Specificity of this analog watchdog: Multiple channels can
6054 * be selected. For example:
6055 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6056 * - groups monitored: not selection possible (monitoring on both
6057 * groups regular and injected).
6058 * Channels selected are monitored on groups regular and injected:
6059 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6060 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6061 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6062 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6063 * the 2 LSB are ignored.
6064 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
6065 * impacted: the comparison of analog watchdog thresholds is done on
6066 * oversampling final computation (after ratio and shift application):
6067 * ADC data register bitfield [15:4] (12 most significant bits).
6068 * Examples:
6069 * - Oversampling ratio and shift selected to have ADC conversion data
6070 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
6071 * ADC analog watchdog thresholds must be divided by 16.
6072 * - Oversampling ratio and shift selected to have ADC conversion data
6073 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
6074 * ADC analog watchdog thresholds must be divided by 4.
6075 * - Oversampling ratio and shift selected to have ADC conversion data
6076 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
6077 * ADC analog watchdog thresholds match directly to ADC data register.
6078 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
6079 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
6080 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
6081 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
6082 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
6083 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
6084 * @param ADCx ADC instance
6085 * @param AWDy This parameter can be one of the following values:
6086 * @arg @ref LL_ADC_AWD1
6087 * @arg @ref LL_ADC_AWD2
6088 * @arg @ref LL_ADC_AWD3
6089 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
6090 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
6091 * @retval None
6092 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)6093 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
6094 uint32_t AWDThresholdLowValue)
6095 {
6096 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
6097 /* position in register and register position depending on parameter */
6098 /* "AWDy". */
6099 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
6100 /* containing other bits reserved for other purpose. */
6101 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6102 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6103
6104 MODIFY_REG(*preg,
6105 ADC_TR1_HT1 | ADC_TR1_LT1,
6106 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
6107 }
6108
6109 /**
6110 * @brief Set ADC analog watchdog threshold value of threshold
6111 * high or low.
6112 * @note If values of both thresholds high or low must be set,
6113 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
6114 * @note In case of ADC resolution different of 12 bits,
6115 * analog watchdog thresholds data require a specific shift.
6116 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
6117 * @note On this STM32 series, there are 2 kinds of analog watchdog
6118 * instance:
6119 * - AWD standard (instance AWD1):
6120 * - channels monitored: can monitor 1 channel or all channels.
6121 * - groups monitored: ADC groups regular and-or injected.
6122 * - resolution: resolution is not limited (corresponds to
6123 * ADC resolution configured).
6124 * - AWD flexible (instances AWD2, AWD3):
6125 * - channels monitored: flexible on channels monitored, selection is
6126 * channel wise, from from 1 to all channels.
6127 * Specificity of this analog watchdog: Multiple channels can
6128 * be selected. For example:
6129 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6130 * - groups monitored: not selection possible (monitoring on both
6131 * groups regular and injected).
6132 * Channels selected are monitored on groups regular and injected:
6133 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6134 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6135 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6136 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6137 * the 2 LSB are ignored.
6138 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
6139 * impacted: the comparison of analog watchdog thresholds is done on
6140 * oversampling final computation (after ratio and shift application):
6141 * ADC data register bitfield [15:4] (12 most significant bits).
6142 * Examples:
6143 * - Oversampling ratio and shift selected to have ADC conversion data
6144 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
6145 * ADC analog watchdog thresholds must be divided by 16.
6146 * - Oversampling ratio and shift selected to have ADC conversion data
6147 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
6148 * ADC analog watchdog thresholds must be divided by 4.
6149 * - Oversampling ratio and shift selected to have ADC conversion data
6150 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
6151 * ADC analog watchdog thresholds match directly to ADC data register.
6152 * @note On this STM32 series, setting of this feature is not conditioned to
6153 * ADC state:
6154 * ADC can be disabled, enabled with or without conversion on going
6155 * on either ADC groups regular or injected.
6156 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
6157 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
6158 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
6159 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
6160 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
6161 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
6162 * @param ADCx ADC instance
6163 * @param AWDy This parameter can be one of the following values:
6164 * @arg @ref LL_ADC_AWD1
6165 * @arg @ref LL_ADC_AWD2
6166 * @arg @ref LL_ADC_AWD3
6167 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6168 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6169 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6170 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
6171 * @retval None
6172 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)6173 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
6174 uint32_t AWDThresholdValue)
6175 {
6176 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6177 /* position in register and register position depending on parameters */
6178 /* "AWDThresholdsHighLow" and "AWDy". */
6179 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6180 /* containing other bits reserved for other purpose. */
6181 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6182 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6183
6184 MODIFY_REG(*preg,
6185 AWDThresholdsHighLow,
6186 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
6187 }
6188
6189 /**
6190 * @brief Get ADC analog watchdog threshold value of threshold high,
6191 * threshold low or raw data with ADC thresholds high and low
6192 * concatenated.
6193 * @note If raw data with ADC thresholds high and low is retrieved,
6194 * the data of each threshold high or low can be isolated
6195 * using helper macro:
6196 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
6197 * @note In case of ADC resolution different of 12 bits,
6198 * analog watchdog thresholds data require a specific shift.
6199 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
6200 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
6201 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
6202 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
6203 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
6204 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
6205 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
6206 * @param ADCx ADC instance
6207 * @param AWDy This parameter can be one of the following values:
6208 * @arg @ref LL_ADC_AWD1
6209 * @arg @ref LL_ADC_AWD2
6210 * @arg @ref LL_ADC_AWD3
6211 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6212 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6213 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6214 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
6215 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6216 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)6217 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
6218 uint32_t AWDy, uint32_t AWDThresholdsHighLow)
6219 {
6220 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6221 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6222
6223 return (uint32_t)(READ_BIT(*preg,
6224 (AWDThresholdsHighLow | ADC_TR1_LT1))
6225 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
6226 & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
6227 }
6228
6229 /**
6230 * @brief Set ADC analog watchdog filtering configuration
6231 * @note On this STM32 series, setting of this feature is conditioned to
6232 * ADC state:
6233 * ADC must be disabled or enabled without conversion on going
6234 * on either groups regular or injected.
6235 * @note On this STM32 series, this feature is only available on first
6236 * analog watchdog (AWD1)
6237 * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
6238 * @param ADCx ADC instance
6239 * @param AWDy This parameter can be one of the following values:
6240 * @arg @ref LL_ADC_AWD1
6241 * @param FilteringConfig This parameter can be one of the following values:
6242 * @arg @ref LL_ADC_AWD_FILTERING_NONE
6243 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
6244 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
6245 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
6246 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
6247 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
6248 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
6249 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
6250 * @retval None
6251 */
LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t FilteringConfig)6252 __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
6253 {
6254 /* Prevent unused argument(s) compilation warning */
6255 (void)(AWDy);
6256 MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
6257 }
6258
6259 /**
6260 * @brief Get ADC analog watchdog filtering configuration
6261 * @note On this STM32 series, this feature is only available on first
6262 * analog watchdog (AWD1)
6263 * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
6264 * @param ADCx ADC instance
6265 * @param AWDy This parameter can be one of the following values:
6266 * @arg @ref LL_ADC_AWD1
6267 * @retval Returned value can be:
6268 * @arg @ref LL_ADC_AWD_FILTERING_NONE
6269 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
6270 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
6271 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
6272 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
6273 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
6274 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
6275 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
6276 */
LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef * ADCx,uint32_t AWDy)6277 __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy)
6278 {
6279 /* Prevent unused argument(s) compilation warning */
6280 (void)(AWDy);
6281 return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
6282 }
6283
6284 /**
6285 * @}
6286 */
6287
6288 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
6289 * @{
6290 */
6291
6292 /**
6293 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
6294 * (availability of ADC group injected depends on STM32 series).
6295 * @note If both groups regular and injected are selected,
6296 * specify behavior of ADC group injected interrupting
6297 * group regular: when ADC group injected is triggered,
6298 * the oversampling on ADC group regular is either
6299 * temporary stopped and continued, or resumed from start
6300 * (oversampler buffer reset).
6301 * @note On this STM32 series, setting of this feature is conditioned to
6302 * ADC state:
6303 * ADC must be disabled or enabled without conversion on going
6304 * on either groups regular or injected.
6305 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
6306 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
6307 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
6308 * @param ADCx ADC instance
6309 * @param OvsScope This parameter can be one of the following values:
6310 * @arg @ref LL_ADC_OVS_DISABLE
6311 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6312 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6313 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6314 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6315 * @retval None
6316 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)6317 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
6318 {
6319 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
6320 }
6321
6322 /**
6323 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
6324 * (availability of ADC group injected depends on STM32 series).
6325 * @note If both groups regular and injected are selected,
6326 * specify behavior of ADC group injected interrupting
6327 * group regular: when ADC group injected is triggered,
6328 * the oversampling on ADC group regular is either
6329 * temporary stopped and continued, or resumed from start
6330 * (oversampler buffer reset).
6331 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
6332 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
6333 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
6334 * @param ADCx ADC instance
6335 * @retval Returned value can be one of the following values:
6336 * @arg @ref LL_ADC_OVS_DISABLE
6337 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6338 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6339 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6340 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6341 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)6342 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
6343 {
6344 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
6345 }
6346
6347 /**
6348 * @brief Set ADC oversampling discontinuous mode (triggered mode)
6349 * on the selected ADC group.
6350 * @note Number of oversampled conversions are done either in:
6351 * - continuous mode (all conversions of oversampling ratio
6352 * are done from 1 trigger)
6353 * - discontinuous mode (each conversion of oversampling ratio
6354 * needs a trigger)
6355 * @note On this STM32 series, setting of this feature is conditioned to
6356 * ADC state:
6357 * ADC must be disabled or enabled without conversion on going
6358 * on group regular.
6359 * @note On this STM32 series, oversampling discontinuous mode
6360 * (triggered mode) can be used only when oversampling is
6361 * set on group regular only and in resumed mode.
6362 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
6363 * @param ADCx ADC instance
6364 * @param OverSamplingDiscont This parameter can be one of the following values:
6365 * @arg @ref LL_ADC_OVS_REG_CONT
6366 * @arg @ref LL_ADC_OVS_REG_DISCONT
6367 * @retval None
6368 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)6369 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
6370 {
6371 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
6372 }
6373
6374 /**
6375 * @brief Get ADC oversampling discontinuous mode (triggered mode)
6376 * on the selected ADC group.
6377 * @note Number of oversampled conversions are done either in:
6378 * - continuous mode (all conversions of oversampling ratio
6379 * are done from 1 trigger)
6380 * - discontinuous mode (each conversion of oversampling ratio
6381 * needs a trigger)
6382 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
6383 * @param ADCx ADC instance
6384 * @retval Returned value can be one of the following values:
6385 * @arg @ref LL_ADC_OVS_REG_CONT
6386 * @arg @ref LL_ADC_OVS_REG_DISCONT
6387 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)6388 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
6389 {
6390 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
6391 }
6392
6393 /**
6394 * @brief Set ADC oversampling
6395 * (impacting both ADC groups regular and injected)
6396 * @note This function set the 2 items of oversampling configuration:
6397 * - ratio
6398 * - shift
6399 * @note On this STM32 series, setting of this feature is conditioned to
6400 * ADC state:
6401 * ADC must be disabled or enabled without conversion on going
6402 * on either groups regular or injected.
6403 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
6404 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
6405 * @param ADCx ADC instance
6406 * @param Ratio This parameter can be one of the following values:
6407 * @arg @ref LL_ADC_OVS_RATIO_2
6408 * @arg @ref LL_ADC_OVS_RATIO_4
6409 * @arg @ref LL_ADC_OVS_RATIO_8
6410 * @arg @ref LL_ADC_OVS_RATIO_16
6411 * @arg @ref LL_ADC_OVS_RATIO_32
6412 * @arg @ref LL_ADC_OVS_RATIO_64
6413 * @arg @ref LL_ADC_OVS_RATIO_128
6414 * @arg @ref LL_ADC_OVS_RATIO_256
6415 * @param Shift This parameter can be one of the following values:
6416 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6417 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6418 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6419 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6420 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6421 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6422 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6423 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6424 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6425 * @retval None
6426 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)6427 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
6428 {
6429 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
6430 }
6431
6432 /**
6433 * @brief Get ADC oversampling ratio
6434 * (impacting both ADC groups regular and injected)
6435 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
6436 * @param ADCx ADC instance
6437 * @retval Ratio This parameter can be one of the following values:
6438 * @arg @ref LL_ADC_OVS_RATIO_2
6439 * @arg @ref LL_ADC_OVS_RATIO_4
6440 * @arg @ref LL_ADC_OVS_RATIO_8
6441 * @arg @ref LL_ADC_OVS_RATIO_16
6442 * @arg @ref LL_ADC_OVS_RATIO_32
6443 * @arg @ref LL_ADC_OVS_RATIO_64
6444 * @arg @ref LL_ADC_OVS_RATIO_128
6445 * @arg @ref LL_ADC_OVS_RATIO_256
6446 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)6447 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
6448 {
6449 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
6450 }
6451
6452 /**
6453 * @brief Get ADC oversampling shift
6454 * (impacting both ADC groups regular and injected)
6455 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
6456 * @param ADCx ADC instance
6457 * @retval Shift This parameter can be one of the following values:
6458 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6459 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6460 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6461 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6462 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6463 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6464 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6465 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6466 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6467 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)6468 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
6469 {
6470 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
6471 }
6472
6473 /**
6474 * @}
6475 */
6476
6477 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
6478 * @{
6479 */
6480
6481 #if defined(ADC_MULTIMODE_SUPPORT)
6482 /**
6483 * @brief Set ADC multimode configuration to operate in independent mode
6484 * or multimode (for devices with several ADC instances).
6485 * @note If multimode configuration: the selected ADC instance is
6486 * either master or slave depending on hardware.
6487 * Refer to reference manual.
6488 * @note On this STM32 series, setting of this feature is conditioned to
6489 * ADC state:
6490 * All ADC instances of the ADC common group must be disabled.
6491 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6492 * ADC instance or by using helper macro
6493 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6494 * @rmtoll CCR DUAL LL_ADC_SetMultimode
6495 * @param ADCxy_COMMON ADC common instance
6496 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6497 * @param Multimode This parameter can be one of the following values:
6498 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6499 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6500 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6501 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6502 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6503 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6504 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6505 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6506 * @retval None
6507 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)6508 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
6509 {
6510 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
6511 }
6512
6513 /**
6514 * @brief Get ADC multimode configuration to operate in independent mode
6515 * or multimode (for devices with several ADC instances).
6516 * @note If multimode configuration: the selected ADC instance is
6517 * either master or slave depending on hardware.
6518 * Refer to reference manual.
6519 * @rmtoll CCR DUAL LL_ADC_GetMultimode
6520 * @param ADCxy_COMMON ADC common instance
6521 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6522 * @retval Returned value can be one of the following values:
6523 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6524 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6525 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6526 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6527 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6528 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6529 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6530 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6531 */
LL_ADC_GetMultimode(const ADC_Common_TypeDef * ADCxy_COMMON)6532 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
6533 {
6534 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
6535 }
6536
6537 /**
6538 * @brief Set ADC multimode conversion data transfer: no transfer
6539 * or transfer by DMA.
6540 * @note If ADC multimode transfer by DMA is not selected:
6541 * each ADC uses its own DMA channel, with its individual
6542 * DMA transfer settings.
6543 * If ADC multimode transfer by DMA is selected:
6544 * One DMA channel is used for both ADC (DMA of ADC master)
6545 * Specifies the DMA requests mode:
6546 * - Limited mode (One shot mode): DMA transfer requests are stopped
6547 * when number of DMA data transfers (number of
6548 * ADC conversions) is reached.
6549 * This ADC mode is intended to be used with DMA mode non-circular.
6550 * - Unlimited mode: DMA transfer requests are unlimited,
6551 * whatever number of DMA data transfers (number of
6552 * ADC conversions).
6553 * This ADC mode is intended to be used with DMA mode circular.
6554 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6555 * mode non-circular:
6556 * when DMA transfers size will be reached, DMA will stop transfers of
6557 * ADC conversions data ADC will raise an overrun error
6558 * (overrun flag and interruption if enabled).
6559 * @note How to retrieve multimode conversion data:
6560 * Whatever multimode transfer by DMA setting: using function
6561 * @ref LL_ADC_REG_ReadMultiConversionData32().
6562 * If ADC multimode transfer by DMA is selected: conversion data
6563 * is a raw data with ADC master and slave concatenated.
6564 * A macro is available to get the conversion data of
6565 * ADC master or ADC slave: see helper macro
6566 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6567 * @note On this STM32 series, setting of this feature is conditioned to
6568 * ADC state:
6569 * All ADC instances of the ADC common group must be disabled
6570 * or enabled without conversion on going on group regular.
6571 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
6572 * CCR DMACFG LL_ADC_SetMultiDMATransfer
6573 * @param ADCxy_COMMON ADC common instance
6574 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6575 * @param MultiDMATransfer This parameter can be one of the following values:
6576 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6577 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6578 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6579 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6580 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6581 * @retval None
6582 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)6583 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
6584 {
6585 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
6586 }
6587
6588 /**
6589 * @brief Get ADC multimode conversion data transfer: no transfer
6590 * or transfer by DMA.
6591 * @note If ADC multimode transfer by DMA is not selected:
6592 * each ADC uses its own DMA channel, with its individual
6593 * DMA transfer settings.
6594 * If ADC multimode transfer by DMA is selected:
6595 * One DMA channel is used for both ADC (DMA of ADC master)
6596 * Specifies the DMA requests mode:
6597 * - Limited mode (One shot mode): DMA transfer requests are stopped
6598 * when number of DMA data transfers (number of
6599 * ADC conversions) is reached.
6600 * This ADC mode is intended to be used with DMA mode non-circular.
6601 * - Unlimited mode: DMA transfer requests are unlimited,
6602 * whatever number of DMA data transfers (number of
6603 * ADC conversions).
6604 * This ADC mode is intended to be used with DMA mode circular.
6605 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6606 * mode non-circular:
6607 * when DMA transfers size will be reached, DMA will stop transfers of
6608 * ADC conversions data ADC will raise an overrun error
6609 * (overrun flag and interruption if enabled).
6610 * @note How to retrieve multimode conversion data:
6611 * Whatever multimode transfer by DMA setting: using function
6612 * @ref LL_ADC_REG_ReadMultiConversionData32().
6613 * If ADC multimode transfer by DMA is selected: conversion data
6614 * is a raw data with ADC master and slave concatenated.
6615 * A macro is available to get the conversion data of
6616 * ADC master or ADC slave: see helper macro
6617 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6618 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
6619 * CCR DMACFG LL_ADC_GetMultiDMATransfer
6620 * @param ADCxy_COMMON ADC common instance
6621 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6622 * @retval Returned value can be one of the following values:
6623 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6624 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6625 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6626 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6627 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6628 */
LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef * ADCxy_COMMON)6629 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
6630 {
6631 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
6632 }
6633
6634 /**
6635 * @brief Set ADC multimode delay between 2 sampling phases.
6636 * @note The sampling delay range depends on ADC resolution:
6637 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
6638 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
6639 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
6640 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
6641 * @note On this STM32 series, setting of this feature is conditioned to
6642 * ADC state:
6643 * All ADC instances of the ADC common group must be disabled.
6644 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6645 * ADC instance or by using helper macro helper macro
6646 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6647 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
6648 * @param ADCxy_COMMON ADC common instance
6649 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6650 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
6651 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6652 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6653 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6654 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6655 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6656 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6657 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6658 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6659 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6660 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6661 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6662 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6663 *
6664 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6665 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6666 * (3) Parameter available only if ADC resolution is 12 bits.
6667 * @retval None
6668 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)6669 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
6670 {
6671 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
6672 }
6673
6674 /**
6675 * @brief Get ADC multimode delay between 2 sampling phases.
6676 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
6677 * @param ADCxy_COMMON ADC common instance
6678 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6679 * @retval Returned value can be one of the following values:
6680 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6681 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6682 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6683 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6684 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6685 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6686 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6687 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6688 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6689 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6690 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6691 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6692 *
6693 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6694 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6695 * (3) Parameter available only if ADC resolution is 12 bits.
6696 */
LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef * ADCxy_COMMON)6697 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
6698 {
6699 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
6700 }
6701 #endif /* ADC_MULTIMODE_SUPPORT */
6702
6703 /**
6704 * @}
6705 */
6706 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
6707 * @{
6708 */
6709
6710 /**
6711 * @brief Put ADC instance in deep power down state.
6712 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6713 * state, the internal analog calibration is lost. After exiting from
6714 * deep power down, calibration must be relaunched or calibration factor
6715 * (preliminarily saved) must be set back into calibration register.
6716 * @note On this STM32 series, setting of this feature is conditioned to
6717 * ADC state:
6718 * ADC must be ADC disabled.
6719 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
6720 * @param ADCx ADC instance
6721 * @retval None
6722 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)6723 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6724 {
6725 /* Note: Write register with some additional bits forced to state reset */
6726 /* instead of modifying only the selected bit for this function, */
6727 /* to not interfere with bits with HW property "rs". */
6728 MODIFY_REG(ADCx->CR,
6729 ADC_CR_BITS_PROPERTY_RS,
6730 ADC_CR_DEEPPWD);
6731 }
6732
6733 /**
6734 * @brief Disable ADC deep power down mode.
6735 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6736 * state, the internal analog calibration is lost. After exiting from
6737 * deep power down, calibration must be relaunched or calibration factor
6738 * (preliminarily saved) must be set back into calibration register.
6739 * @note On this STM32 series, setting of this feature is conditioned to
6740 * ADC state:
6741 * ADC must be ADC disabled.
6742 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
6743 * @param ADCx ADC instance
6744 * @retval None
6745 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)6746 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6747 {
6748 /* Note: Write register with some additional bits forced to state reset */
6749 /* instead of modifying only the selected bit for this function, */
6750 /* to not interfere with bits with HW property "rs". */
6751 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6752 }
6753
6754 /**
6755 * @brief Get the selected ADC instance deep power down state.
6756 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
6757 * @param ADCx ADC instance
6758 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
6759 */
LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef * ADCx)6760 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
6761 {
6762 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6763 }
6764
6765 /**
6766 * @brief Enable ADC instance internal voltage regulator.
6767 * @note On this STM32 series, after ADC internal voltage regulator enable,
6768 * a delay for ADC internal voltage regulator stabilization
6769 * is required before performing a ADC calibration or ADC enable.
6770 * Refer to device datasheet, parameter tADCVREG_STUP.
6771 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
6772 * @note On this STM32 series, setting of this feature is conditioned to
6773 * ADC state:
6774 * ADC must be ADC disabled.
6775 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
6776 * @param ADCx ADC instance
6777 * @retval None
6778 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)6779 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
6780 {
6781 /* Note: Write register with some additional bits forced to state reset */
6782 /* instead of modifying only the selected bit for this function, */
6783 /* to not interfere with bits with HW property "rs". */
6784 MODIFY_REG(ADCx->CR,
6785 ADC_CR_BITS_PROPERTY_RS,
6786 ADC_CR_ADVREGEN);
6787 }
6788
6789 /**
6790 * @brief Disable ADC internal voltage regulator.
6791 * @note On this STM32 series, setting of this feature is conditioned to
6792 * ADC state:
6793 * ADC must be ADC disabled.
6794 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
6795 * @param ADCx ADC instance
6796 * @retval None
6797 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)6798 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
6799 {
6800 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
6801 }
6802
6803 /**
6804 * @brief Get the selected ADC instance internal voltage regulator state.
6805 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
6806 * @param ADCx ADC instance
6807 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
6808 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)6809 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
6810 {
6811 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
6812 }
6813
6814 /**
6815 * @brief Enable the selected ADC instance.
6816 * @note On this STM32 series, after ADC enable, a delay for
6817 * ADC internal analog stabilization is required before performing a
6818 * ADC conversion start.
6819 * Refer to device datasheet, parameter tSTAB.
6820 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6821 * is enabled and when conversion clock is active.
6822 * (not only core clock: this ADC has a dual clock domain)
6823 * @note On this STM32 series, setting of this feature is conditioned to
6824 * ADC state:
6825 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
6826 * @rmtoll CR ADEN LL_ADC_Enable
6827 * @param ADCx ADC instance
6828 * @retval None
6829 */
LL_ADC_Enable(ADC_TypeDef * ADCx)6830 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6831 {
6832 /* Note: Write register with some additional bits forced to state reset */
6833 /* instead of modifying only the selected bit for this function, */
6834 /* to not interfere with bits with HW property "rs". */
6835 MODIFY_REG(ADCx->CR,
6836 ADC_CR_BITS_PROPERTY_RS,
6837 ADC_CR_ADEN);
6838 }
6839
6840 /**
6841 * @brief Disable the selected ADC instance.
6842 * @note On this STM32 series, setting of this feature is conditioned to
6843 * ADC state:
6844 * ADC must be not disabled. Must be enabled without conversion on going
6845 * on either groups regular or injected.
6846 * @rmtoll CR ADDIS LL_ADC_Disable
6847 * @param ADCx ADC instance
6848 * @retval None
6849 */
LL_ADC_Disable(ADC_TypeDef * ADCx)6850 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6851 {
6852 /* Note: Write register with some additional bits forced to state reset */
6853 /* instead of modifying only the selected bit for this function, */
6854 /* to not interfere with bits with HW property "rs". */
6855 MODIFY_REG(ADCx->CR,
6856 ADC_CR_BITS_PROPERTY_RS,
6857 ADC_CR_ADDIS);
6858 }
6859
6860 /**
6861 * @brief Get the selected ADC instance enable state.
6862 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6863 * is enabled and when conversion clock is active.
6864 * (not only core clock: this ADC has a dual clock domain)
6865 * @rmtoll CR ADEN LL_ADC_IsEnabled
6866 * @param ADCx ADC instance
6867 * @retval 0: ADC is disabled, 1: ADC is enabled.
6868 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)6869 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
6870 {
6871 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6872 }
6873
6874 /**
6875 * @brief Get the selected ADC instance disable state.
6876 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6877 * @param ADCx ADC instance
6878 * @retval 0: no ADC disable command on going.
6879 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)6880 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
6881 {
6882 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6883 }
6884
6885 /**
6886 * @brief Start ADC calibration in the mode single-ended
6887 * or differential (for devices with differential mode available).
6888 * @note On this STM32 series, a minimum number of ADC clock cycles
6889 * are required between ADC end of calibration and ADC enable.
6890 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6891 * @note For devices with differential mode available:
6892 * Calibration of offset is specific to each of
6893 * single-ended and differential modes
6894 * (calibration run must be performed for each of these
6895 * differential modes, if used afterwards and if the application
6896 * requires their calibration).
6897 * @note On this STM32 series, setting of this feature is conditioned to
6898 * ADC state:
6899 * ADC must be ADC disabled.
6900 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6901 * CR ADCALDIF LL_ADC_StartCalibration
6902 * @param ADCx ADC instance
6903 * @param SingleDiff This parameter can be one of the following values:
6904 * @arg @ref LL_ADC_SINGLE_ENDED
6905 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6906 * @retval None
6907 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)6908 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6909 {
6910 /* Note: Write register with some additional bits forced to state reset */
6911 /* instead of modifying only the selected bit for this function, */
6912 /* to not interfere with bits with HW property "rs". */
6913 MODIFY_REG(ADCx->CR,
6914 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6915 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6916 }
6917
6918 /**
6919 * @brief Get ADC calibration state.
6920 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6921 * @param ADCx ADC instance
6922 * @retval 0: calibration complete, 1: calibration in progress.
6923 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)6924 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
6925 {
6926 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6927 }
6928
6929 /**
6930 * @}
6931 */
6932
6933 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6934 * @{
6935 */
6936
6937 /**
6938 * @brief Start ADC group regular conversion.
6939 * @note On this STM32 series, this function is relevant for both
6940 * internal trigger (SW start) and external trigger:
6941 * - If ADC trigger has been set to software start, ADC conversion
6942 * starts immediately.
6943 * - If ADC trigger has been set to external trigger, ADC conversion
6944 * will start at next trigger event (on the selected trigger edge)
6945 * following the ADC start conversion command.
6946 * @note On this STM32 series, setting of this feature is conditioned to
6947 * ADC state:
6948 * ADC must be enabled without conversion on going on group regular,
6949 * without conversion stop command on going on group regular,
6950 * without ADC disable command on going.
6951 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6952 * @param ADCx ADC instance
6953 * @retval None
6954 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)6955 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6956 {
6957 /* Note: Write register with some additional bits forced to state reset */
6958 /* instead of modifying only the selected bit for this function, */
6959 /* to not interfere with bits with HW property "rs". */
6960 MODIFY_REG(ADCx->CR,
6961 ADC_CR_BITS_PROPERTY_RS,
6962 ADC_CR_ADSTART);
6963 }
6964
6965 /**
6966 * @brief Stop ADC group regular conversion.
6967 * @note On this STM32 series, setting of this feature is conditioned to
6968 * ADC state:
6969 * ADC must be enabled with conversion on going on group regular,
6970 * without ADC disable command on going.
6971 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6972 * @param ADCx ADC instance
6973 * @retval None
6974 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)6975 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6976 {
6977 /* Note: Write register with some additional bits forced to state reset */
6978 /* instead of modifying only the selected bit for this function, */
6979 /* to not interfere with bits with HW property "rs". */
6980 MODIFY_REG(ADCx->CR,
6981 ADC_CR_BITS_PROPERTY_RS,
6982 ADC_CR_ADSTP);
6983 }
6984
6985 /**
6986 * @brief Get ADC group regular conversion state.
6987 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6988 * @param ADCx ADC instance
6989 * @retval 0: no conversion is on going on ADC group regular.
6990 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)6991 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
6992 {
6993 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6994 }
6995
6996 /**
6997 * @brief Get ADC group regular command of conversion stop state
6998 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6999 * @param ADCx ADC instance
7000 * @retval 0: no command of conversion stop is on going on ADC group regular.
7001 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)7002 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
7003 {
7004 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
7005 }
7006
7007 /**
7008 * @brief Start ADC sampling phase for sampling time trigger mode
7009 * @note This function is relevant only when
7010 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
7011 * using @ref LL_ADC_REG_SetSamplingMode
7012 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
7013 * @note On this STM32 series, setting of this feature is conditioned to
7014 * ADC state:
7015 * ADC must be enabled without conversion on going on group regular,
7016 * without conversion stop command on going on group regular,
7017 * without ADC disable command on going.
7018 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
7019 * @param ADCx ADC instance
7020 * @retval None
7021 */
LL_ADC_REG_StartSamplingPhase(ADC_TypeDef * ADCx)7022 __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
7023 {
7024 SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
7025 }
7026
7027 /**
7028 * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion
7029 * @note This function is relevant only when
7030 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
7031 * using @ref LL_ADC_REG_SetSamplingMode
7032 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
7033 * - @ref LL_ADC_REG_StartSamplingPhase has been called to start
7034 * the sampling phase
7035 * @note On this STM32 series, setting of this feature is conditioned to
7036 * ADC state:
7037 * ADC must be enabled without conversion on going on group regular,
7038 * without conversion stop command on going on group regular,
7039 * without ADC disable command on going.
7040 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
7041 * @param ADCx ADC instance
7042 * @retval None
7043 */
LL_ADC_REG_StopSamplingPhase(ADC_TypeDef * ADCx)7044 __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
7045 {
7046 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
7047 }
7048
7049 /**
7050 * @brief Get ADC group regular conversion data, range fit for
7051 * all ADC configurations: all ADC resolutions and
7052 * all oversampling increased data width (for devices
7053 * with feature oversampling).
7054 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
7055 * @param ADCx ADC instance
7056 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7057 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)7058 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
7059 {
7060 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7061 }
7062
7063 /**
7064 * @brief Get ADC group regular conversion data, range fit for
7065 * ADC resolution 12 bits.
7066 * @note For devices with feature oversampling: Oversampling
7067 * can increase data width, function for extended range
7068 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7069 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
7070 * @param ADCx ADC instance
7071 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7072 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)7073 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
7074 {
7075 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7076 }
7077
7078 /**
7079 * @brief Get ADC group regular conversion data, range fit for
7080 * ADC resolution 10 bits.
7081 * @note For devices with feature oversampling: Oversampling
7082 * can increase data width, function for extended range
7083 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7084 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
7085 * @param ADCx ADC instance
7086 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7087 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)7088 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
7089 {
7090 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7091 }
7092
7093 /**
7094 * @brief Get ADC group regular conversion data, range fit for
7095 * ADC resolution 8 bits.
7096 * @note For devices with feature oversampling: Oversampling
7097 * can increase data width, function for extended range
7098 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7099 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
7100 * @param ADCx ADC instance
7101 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7102 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)7103 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
7104 {
7105 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7106 }
7107
7108 /**
7109 * @brief Get ADC group regular conversion data, range fit for
7110 * ADC resolution 6 bits.
7111 * @note For devices with feature oversampling: Oversampling
7112 * can increase data width, function for extended range
7113 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7114 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
7115 * @param ADCx ADC instance
7116 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
7117 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)7118 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
7119 {
7120 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7121 }
7122
7123 #if defined(ADC_MULTIMODE_SUPPORT)
7124 /**
7125 * @brief Get ADC multimode conversion data of ADC master, ADC slave
7126 * or raw data with ADC master and slave concatenated.
7127 * @note If raw data with ADC master and slave concatenated is retrieved,
7128 * a macro is available to get the conversion data of
7129 * ADC master or ADC slave: see helper macro
7130 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
7131 * (however this macro is mainly intended for multimode
7132 * transfer by DMA, because this function can do the same
7133 * by getting multimode conversion data of ADC master or ADC slave
7134 * separately).
7135 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
7136 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
7137 * @param ADCxy_COMMON ADC common instance
7138 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7139 * @param ConversionData This parameter can be one of the following values:
7140 * @arg @ref LL_ADC_MULTI_MASTER
7141 * @arg @ref LL_ADC_MULTI_SLAVE
7142 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
7143 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7144 */
LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)7145 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON,
7146 uint32_t ConversionData)
7147 {
7148 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
7149 ConversionData)
7150 >> (POSITION_VAL(ConversionData) & 0x1FUL)
7151 );
7152 }
7153 #endif /* ADC_MULTIMODE_SUPPORT */
7154
7155 /**
7156 * @}
7157 */
7158
7159 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
7160 * @{
7161 */
7162
7163 /**
7164 * @brief Start ADC group injected conversion.
7165 * @note On this STM32 series, this function is relevant for both
7166 * internal trigger (SW start) and external trigger:
7167 * - If ADC trigger has been set to software start, ADC conversion
7168 * starts immediately.
7169 * - If ADC trigger has been set to external trigger, ADC conversion
7170 * will start at next trigger event (on the selected trigger edge)
7171 * following the ADC start conversion command.
7172 * @note On this STM32 series, setting of this feature is conditioned to
7173 * ADC state:
7174 * ADC must be enabled without conversion on going on group injected,
7175 * without conversion stop command on going on group injected,
7176 * without ADC disable command on going.
7177 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
7178 * @param ADCx ADC instance
7179 * @retval None
7180 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)7181 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
7182 {
7183 /* Note: Write register with some additional bits forced to state reset */
7184 /* instead of modifying only the selected bit for this function, */
7185 /* to not interfere with bits with HW property "rs". */
7186 MODIFY_REG(ADCx->CR,
7187 ADC_CR_BITS_PROPERTY_RS,
7188 ADC_CR_JADSTART);
7189 }
7190
7191 /**
7192 * @brief Stop ADC group injected conversion.
7193 * @note On this STM32 series, setting of this feature is conditioned to
7194 * ADC state:
7195 * ADC must be enabled with conversion on going on group injected,
7196 * without ADC disable command on going.
7197 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
7198 * @param ADCx ADC instance
7199 * @retval None
7200 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)7201 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
7202 {
7203 /* Note: Write register with some additional bits forced to state reset */
7204 /* instead of modifying only the selected bit for this function, */
7205 /* to not interfere with bits with HW property "rs". */
7206 MODIFY_REG(ADCx->CR,
7207 ADC_CR_BITS_PROPERTY_RS,
7208 ADC_CR_JADSTP);
7209 }
7210
7211 /**
7212 * @brief Get ADC group injected conversion state.
7213 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
7214 * @param ADCx ADC instance
7215 * @retval 0: no conversion is on going on ADC group injected.
7216 */
LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef * ADCx)7217 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
7218 {
7219 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
7220 }
7221
7222 /**
7223 * @brief Get ADC group injected command of conversion stop state
7224 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
7225 * @param ADCx ADC instance
7226 * @retval 0: no command of conversion stop is on going on ADC group injected.
7227 */
LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef * ADCx)7228 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
7229 {
7230 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
7231 }
7232
7233 /**
7234 * @brief Get ADC group injected conversion data, range fit for
7235 * all ADC configurations: all ADC resolutions and
7236 * all oversampling increased data width (for devices
7237 * with feature oversampling).
7238 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
7239 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
7240 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
7241 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
7242 * @param ADCx ADC instance
7243 * @param Rank This parameter can be one of the following values:
7244 * @arg @ref LL_ADC_INJ_RANK_1
7245 * @arg @ref LL_ADC_INJ_RANK_2
7246 * @arg @ref LL_ADC_INJ_RANK_3
7247 * @arg @ref LL_ADC_INJ_RANK_4
7248 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7249 */
LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef * ADCx,uint32_t Rank)7250 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
7251 {
7252 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7253 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7254
7255 return (uint32_t)(READ_BIT(*preg,
7256 ADC_JDR1_JDATA)
7257 );
7258 }
7259
7260 /**
7261 * @brief Get ADC group injected conversion data, range fit for
7262 * ADC resolution 12 bits.
7263 * @note For devices with feature oversampling: Oversampling
7264 * can increase data width, function for extended range
7265 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7266 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
7267 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
7268 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
7269 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
7270 * @param ADCx ADC instance
7271 * @param Rank This parameter can be one of the following values:
7272 * @arg @ref LL_ADC_INJ_RANK_1
7273 * @arg @ref LL_ADC_INJ_RANK_2
7274 * @arg @ref LL_ADC_INJ_RANK_3
7275 * @arg @ref LL_ADC_INJ_RANK_4
7276 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7277 */
LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef * ADCx,uint32_t Rank)7278 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
7279 {
7280 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7281 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7282
7283 return (uint16_t)(READ_BIT(*preg,
7284 ADC_JDR1_JDATA)
7285 );
7286 }
7287
7288 /**
7289 * @brief Get ADC group injected conversion data, range fit for
7290 * ADC resolution 10 bits.
7291 * @note For devices with feature oversampling: Oversampling
7292 * can increase data width, function for extended range
7293 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7294 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
7295 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
7296 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
7297 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
7298 * @param ADCx ADC instance
7299 * @param Rank This parameter can be one of the following values:
7300 * @arg @ref LL_ADC_INJ_RANK_1
7301 * @arg @ref LL_ADC_INJ_RANK_2
7302 * @arg @ref LL_ADC_INJ_RANK_3
7303 * @arg @ref LL_ADC_INJ_RANK_4
7304 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7305 */
LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef * ADCx,uint32_t Rank)7306 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
7307 {
7308 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7309 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7310
7311 return (uint16_t)(READ_BIT(*preg,
7312 ADC_JDR1_JDATA)
7313 );
7314 }
7315
7316 /**
7317 * @brief Get ADC group injected conversion data, range fit for
7318 * ADC resolution 8 bits.
7319 * @note For devices with feature oversampling: Oversampling
7320 * can increase data width, function for extended range
7321 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7322 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
7323 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
7324 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
7325 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
7326 * @param ADCx ADC instance
7327 * @param Rank This parameter can be one of the following values:
7328 * @arg @ref LL_ADC_INJ_RANK_1
7329 * @arg @ref LL_ADC_INJ_RANK_2
7330 * @arg @ref LL_ADC_INJ_RANK_3
7331 * @arg @ref LL_ADC_INJ_RANK_4
7332 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7333 */
LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef * ADCx,uint32_t Rank)7334 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
7335 {
7336 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7337 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7338
7339 return (uint8_t)(READ_BIT(*preg,
7340 ADC_JDR1_JDATA)
7341 );
7342 }
7343
7344 /**
7345 * @brief Get ADC group injected conversion data, range fit for
7346 * ADC resolution 6 bits.
7347 * @note For devices with feature oversampling: Oversampling
7348 * can increase data width, function for extended range
7349 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7350 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
7351 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
7352 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
7353 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
7354 * @param ADCx ADC instance
7355 * @param Rank This parameter can be one of the following values:
7356 * @arg @ref LL_ADC_INJ_RANK_1
7357 * @arg @ref LL_ADC_INJ_RANK_2
7358 * @arg @ref LL_ADC_INJ_RANK_3
7359 * @arg @ref LL_ADC_INJ_RANK_4
7360 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
7361 */
LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef * ADCx,uint32_t Rank)7362 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
7363 {
7364 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7365 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7366
7367 return (uint8_t)(READ_BIT(*preg,
7368 ADC_JDR1_JDATA)
7369 );
7370 }
7371
7372 /**
7373 * @}
7374 */
7375
7376 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
7377 * @{
7378 */
7379
7380 /**
7381 * @brief Get flag ADC ready.
7382 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7383 * is enabled and when conversion clock is active.
7384 * (not only core clock: this ADC has a dual clock domain)
7385 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
7386 * @param ADCx ADC instance
7387 * @retval State of bit (1 or 0).
7388 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)7389 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
7390 {
7391 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
7392 }
7393
7394 /**
7395 * @brief Get flag ADC group regular end of unitary conversion.
7396 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
7397 * @param ADCx ADC instance
7398 * @retval State of bit (1 or 0).
7399 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)7400 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
7401 {
7402 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
7403 }
7404
7405 /**
7406 * @brief Get flag ADC group regular end of sequence conversions.
7407 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
7408 * @param ADCx ADC instance
7409 * @retval State of bit (1 or 0).
7410 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)7411 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
7412 {
7413 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
7414 }
7415
7416 /**
7417 * @brief Get flag ADC group regular overrun.
7418 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
7419 * @param ADCx ADC instance
7420 * @retval State of bit (1 or 0).
7421 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)7422 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
7423 {
7424 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
7425 }
7426
7427 /**
7428 * @brief Get flag ADC group regular end of sampling phase.
7429 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
7430 * @param ADCx ADC instance
7431 * @retval State of bit (1 or 0).
7432 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)7433 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
7434 {
7435 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
7436 }
7437
7438 /**
7439 * @brief Get flag ADC group injected end of unitary conversion.
7440 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
7441 * @param ADCx ADC instance
7442 * @retval State of bit (1 or 0).
7443 */
LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef * ADCx)7444 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
7445 {
7446 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
7447 }
7448
7449 /**
7450 * @brief Get flag ADC group injected end of sequence conversions.
7451 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
7452 * @param ADCx ADC instance
7453 * @retval State of bit (1 or 0).
7454 */
LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef * ADCx)7455 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
7456 {
7457 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
7458 }
7459
7460 /**
7461 * @brief Get flag ADC group injected contexts queue overflow.
7462 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
7463 * @param ADCx ADC instance
7464 * @retval State of bit (1 or 0).
7465 */
LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef * ADCx)7466 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx)
7467 {
7468 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
7469 }
7470
7471 /**
7472 * @brief Get flag ADC analog watchdog 1 flag
7473 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
7474 * @param ADCx ADC instance
7475 * @retval State of bit (1 or 0).
7476 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)7477 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
7478 {
7479 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
7480 }
7481
7482 /**
7483 * @brief Get flag ADC analog watchdog 2.
7484 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
7485 * @param ADCx ADC instance
7486 * @retval State of bit (1 or 0).
7487 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)7488 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
7489 {
7490 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
7491 }
7492
7493 /**
7494 * @brief Get flag ADC analog watchdog 3.
7495 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
7496 * @param ADCx ADC instance
7497 * @retval State of bit (1 or 0).
7498 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)7499 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
7500 {
7501 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
7502 }
7503
7504 /**
7505 * @brief Clear flag ADC ready.
7506 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7507 * is enabled and when conversion clock is active.
7508 * (not only core clock: this ADC has a dual clock domain)
7509 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
7510 * @param ADCx ADC instance
7511 * @retval None
7512 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)7513 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
7514 {
7515 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
7516 }
7517
7518 /**
7519 * @brief Clear flag ADC group regular end of unitary conversion.
7520 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
7521 * @param ADCx ADC instance
7522 * @retval None
7523 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)7524 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
7525 {
7526 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
7527 }
7528
7529 /**
7530 * @brief Clear flag ADC group regular end of sequence conversions.
7531 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
7532 * @param ADCx ADC instance
7533 * @retval None
7534 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)7535 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
7536 {
7537 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
7538 }
7539
7540 /**
7541 * @brief Clear flag ADC group regular overrun.
7542 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
7543 * @param ADCx ADC instance
7544 * @retval None
7545 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)7546 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
7547 {
7548 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
7549 }
7550
7551 /**
7552 * @brief Clear flag ADC group regular end of sampling phase.
7553 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
7554 * @param ADCx ADC instance
7555 * @retval None
7556 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)7557 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
7558 {
7559 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
7560 }
7561
7562 /**
7563 * @brief Clear flag ADC group injected end of unitary conversion.
7564 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
7565 * @param ADCx ADC instance
7566 * @retval None
7567 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)7568 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
7569 {
7570 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
7571 }
7572
7573 /**
7574 * @brief Clear flag ADC group injected end of sequence conversions.
7575 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
7576 * @param ADCx ADC instance
7577 * @retval None
7578 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)7579 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
7580 {
7581 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
7582 }
7583
7584 /**
7585 * @brief Clear flag ADC group injected contexts queue overflow.
7586 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
7587 * @param ADCx ADC instance
7588 * @retval None
7589 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)7590 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
7591 {
7592 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
7593 }
7594
7595 /**
7596 * @brief Clear flag ADC analog watchdog 1.
7597 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
7598 * @param ADCx ADC instance
7599 * @retval None
7600 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)7601 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
7602 {
7603 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
7604 }
7605
7606 /**
7607 * @brief Clear flag ADC analog watchdog 2.
7608 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
7609 * @param ADCx ADC instance
7610 * @retval None
7611 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)7612 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
7613 {
7614 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
7615 }
7616
7617 /**
7618 * @brief Clear flag ADC analog watchdog 3.
7619 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
7620 * @param ADCx ADC instance
7621 * @retval None
7622 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)7623 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
7624 {
7625 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
7626 }
7627
7628 #if defined(ADC_MULTIMODE_SUPPORT)
7629 /**
7630 * @brief Get flag multimode ADC ready of the ADC master.
7631 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
7632 * @param ADCxy_COMMON ADC common instance
7633 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7634 * @retval State of bit (1 or 0).
7635 */
LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)7636 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
7637 {
7638 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
7639 }
7640
7641 /**
7642 * @brief Get flag multimode ADC ready of the ADC slave.
7643 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
7644 * @param ADCxy_COMMON ADC common instance
7645 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7646 * @retval State of bit (1 or 0).
7647 */
LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)7648 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
7649 {
7650 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
7651 }
7652
7653 /**
7654 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
7655 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
7656 * @param ADCxy_COMMON ADC common instance
7657 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7658 * @retval State of bit (1 or 0).
7659 */
LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)7660 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7661 {
7662 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7663 }
7664
7665 /**
7666 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
7667 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
7668 * @param ADCxy_COMMON ADC common instance
7669 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7670 * @retval State of bit (1 or 0).
7671 */
LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)7672 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7673 {
7674 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7675 }
7676
7677 /**
7678 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
7679 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
7680 * @param ADCxy_COMMON ADC common instance
7681 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7682 * @retval State of bit (1 or 0).
7683 */
LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)7684 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7685 {
7686 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
7687 }
7688
7689 /**
7690 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
7691 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
7692 * @param ADCxy_COMMON ADC common instance
7693 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7694 * @retval State of bit (1 or 0).
7695 */
LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)7696 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7697 {
7698 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
7699 }
7700
7701 /**
7702 * @brief Get flag multimode ADC group regular overrun of the ADC master.
7703 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
7704 * @param ADCxy_COMMON ADC common instance
7705 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7706 * @retval State of bit (1 or 0).
7707 */
LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)7708 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7709 {
7710 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
7711 }
7712
7713 /**
7714 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
7715 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
7716 * @param ADCxy_COMMON ADC common instance
7717 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7718 * @retval State of bit (1 or 0).
7719 */
LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)7720 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7721 {
7722 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
7723 }
7724
7725 /**
7726 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
7727 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
7728 * @param ADCxy_COMMON ADC common instance
7729 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7730 * @retval State of bit (1 or 0).
7731 */
LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)7732 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7733 {
7734 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
7735 }
7736
7737 /**
7738 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
7739 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
7740 * @param ADCxy_COMMON ADC common instance
7741 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7742 * @retval State of bit (1 or 0).
7743 */
LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)7744 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7745 {
7746 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
7747 }
7748
7749 /**
7750 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
7751 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
7752 * @param ADCxy_COMMON ADC common instance
7753 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7754 * @retval State of bit (1 or 0).
7755 */
LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)7756 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7757 {
7758 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
7759 }
7760
7761 /**
7762 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
7763 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
7764 * @param ADCxy_COMMON ADC common instance
7765 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7766 * @retval State of bit (1 or 0).
7767 */
LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)7768 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7769 {
7770 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
7771 }
7772
7773 /**
7774 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
7775 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
7776 * @param ADCxy_COMMON ADC common instance
7777 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7778 * @retval State of bit (1 or 0).
7779 */
LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)7780 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7781 {
7782 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
7783 }
7784
7785 /**
7786 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
7787 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
7788 * @param ADCxy_COMMON ADC common instance
7789 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7790 * @retval State of bit (1 or 0).
7791 */
LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)7792 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7793 {
7794 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
7795 }
7796
7797 /**
7798 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
7799 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
7800 * @param ADCxy_COMMON ADC common instance
7801 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7802 * @retval State of bit (1 or 0).
7803 */
LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef * ADCxy_COMMON)7804 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
7805 {
7806 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
7807 }
7808
7809 /**
7810 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
7811 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
7812 * @param ADCxy_COMMON ADC common instance
7813 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7814 * @retval State of bit (1 or 0).
7815 */
LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef * ADCxy_COMMON)7816 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
7817 {
7818 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
7819 }
7820
7821 /**
7822 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
7823 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
7824 * @param ADCxy_COMMON ADC common instance
7825 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7826 * @retval State of bit (1 or 0).
7827 */
LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)7828 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7829 {
7830 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
7831 }
7832
7833 /**
7834 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
7835 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
7836 * @param ADCxy_COMMON ADC common instance
7837 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7838 * @retval State of bit (1 or 0).
7839 */
LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)7840 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7841 {
7842 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
7843 }
7844
7845 /**
7846 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
7847 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
7848 * @param ADCxy_COMMON ADC common instance
7849 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7850 * @retval State of bit (1 or 0).
7851 */
LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)7852 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7853 {
7854 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
7855 }
7856
7857 /**
7858 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
7859 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
7860 * @param ADCxy_COMMON ADC common instance
7861 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7862 * @retval State of bit (1 or 0).
7863 */
LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)7864 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7865 {
7866 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
7867 }
7868
7869 /**
7870 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
7871 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
7872 * @param ADCxy_COMMON ADC common instance
7873 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7874 * @retval State of bit (1 or 0).
7875 */
LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)7876 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7877 {
7878 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
7879 }
7880
7881 /**
7882 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
7883 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
7884 * @param ADCxy_COMMON ADC common instance
7885 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7886 * @retval State of bit (1 or 0).
7887 */
LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)7888 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7889 {
7890 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
7891 }
7892 #endif /* ADC_MULTIMODE_SUPPORT */
7893
7894 /**
7895 * @}
7896 */
7897
7898 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
7899 * @{
7900 */
7901
7902 /**
7903 * @brief Enable ADC ready.
7904 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7905 * @param ADCx ADC instance
7906 * @retval None
7907 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)7908 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7909 {
7910 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7911 }
7912
7913 /**
7914 * @brief Enable interruption ADC group regular end of unitary conversion.
7915 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7916 * @param ADCx ADC instance
7917 * @retval None
7918 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)7919 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
7920 {
7921 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
7922 }
7923
7924 /**
7925 * @brief Enable interruption ADC group regular end of sequence conversions.
7926 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
7927 * @param ADCx ADC instance
7928 * @retval None
7929 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)7930 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7931 {
7932 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7933 }
7934
7935 /**
7936 * @brief Enable ADC group regular interruption overrun.
7937 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7938 * @param ADCx ADC instance
7939 * @retval None
7940 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)7941 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7942 {
7943 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7944 }
7945
7946 /**
7947 * @brief Enable interruption ADC group regular end of sampling.
7948 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7949 * @param ADCx ADC instance
7950 * @retval None
7951 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)7952 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7953 {
7954 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7955 }
7956
7957 /**
7958 * @brief Enable interruption ADC group injected end of unitary conversion.
7959 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7960 * @param ADCx ADC instance
7961 * @retval None
7962 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)7963 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7964 {
7965 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7966 }
7967
7968 /**
7969 * @brief Enable interruption ADC group injected end of sequence conversions.
7970 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7971 * @param ADCx ADC instance
7972 * @retval None
7973 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)7974 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7975 {
7976 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7977 }
7978
7979 /**
7980 * @brief Enable interruption ADC group injected context queue overflow.
7981 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
7982 * @param ADCx ADC instance
7983 * @retval None
7984 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)7985 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7986 {
7987 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7988 }
7989
7990 /**
7991 * @brief Enable interruption ADC analog watchdog 1.
7992 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7993 * @param ADCx ADC instance
7994 * @retval None
7995 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)7996 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7997 {
7998 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7999 }
8000
8001 /**
8002 * @brief Enable interruption ADC analog watchdog 2.
8003 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
8004 * @param ADCx ADC instance
8005 * @retval None
8006 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)8007 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
8008 {
8009 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8010 }
8011
8012 /**
8013 * @brief Enable interruption ADC analog watchdog 3.
8014 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
8015 * @param ADCx ADC instance
8016 * @retval None
8017 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)8018 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
8019 {
8020 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8021 }
8022
8023 /**
8024 * @brief Disable interruption ADC ready.
8025 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
8026 * @param ADCx ADC instance
8027 * @retval None
8028 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)8029 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
8030 {
8031 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8032 }
8033
8034 /**
8035 * @brief Disable interruption ADC group regular end of unitary conversion.
8036 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
8037 * @param ADCx ADC instance
8038 * @retval None
8039 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)8040 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
8041 {
8042 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
8043 }
8044
8045 /**
8046 * @brief Disable interruption ADC group regular end of sequence conversions.
8047 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
8048 * @param ADCx ADC instance
8049 * @retval None
8050 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)8051 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
8052 {
8053 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
8054 }
8055
8056 /**
8057 * @brief Disable interruption ADC group regular overrun.
8058 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
8059 * @param ADCx ADC instance
8060 * @retval None
8061 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)8062 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
8063 {
8064 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
8065 }
8066
8067 /**
8068 * @brief Disable interruption ADC group regular end of sampling.
8069 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
8070 * @param ADCx ADC instance
8071 * @retval None
8072 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)8073 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
8074 {
8075 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8076 }
8077
8078 /**
8079 * @brief Disable interruption ADC group regular end of unitary conversion.
8080 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
8081 * @param ADCx ADC instance
8082 * @retval None
8083 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)8084 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
8085 {
8086 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8087 }
8088
8089 /**
8090 * @brief Disable interruption ADC group injected end of sequence conversions.
8091 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
8092 * @param ADCx ADC instance
8093 * @retval None
8094 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)8095 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
8096 {
8097 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8098 }
8099
8100 /**
8101 * @brief Disable interruption ADC group injected context queue overflow.
8102 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
8103 * @param ADCx ADC instance
8104 * @retval None
8105 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)8106 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
8107 {
8108 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
8109 }
8110
8111 /**
8112 * @brief Disable interruption ADC analog watchdog 1.
8113 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
8114 * @param ADCx ADC instance
8115 * @retval None
8116 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)8117 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
8118 {
8119 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8120 }
8121
8122 /**
8123 * @brief Disable interruption ADC analog watchdog 2.
8124 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
8125 * @param ADCx ADC instance
8126 * @retval None
8127 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)8128 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
8129 {
8130 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8131 }
8132
8133 /**
8134 * @brief Disable interruption ADC analog watchdog 3.
8135 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
8136 * @param ADCx ADC instance
8137 * @retval None
8138 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)8139 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
8140 {
8141 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8142 }
8143
8144 /**
8145 * @brief Get state of interruption ADC ready
8146 * (0: interrupt disabled, 1: interrupt enabled).
8147 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
8148 * @param ADCx ADC instance
8149 * @retval State of bit (1 or 0).
8150 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)8151 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
8152 {
8153 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
8154 }
8155
8156 /**
8157 * @brief Get state of interruption ADC group regular end of unitary conversion
8158 * (0: interrupt disabled, 1: interrupt enabled).
8159 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
8160 * @param ADCx ADC instance
8161 * @retval State of bit (1 or 0).
8162 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)8163 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
8164 {
8165 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
8166 }
8167
8168 /**
8169 * @brief Get state of interruption ADC group regular end of sequence conversions
8170 * (0: interrupt disabled, 1: interrupt enabled).
8171 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
8172 * @param ADCx ADC instance
8173 * @retval State of bit (1 or 0).
8174 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)8175 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
8176 {
8177 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
8178 }
8179
8180 /**
8181 * @brief Get state of interruption ADC group regular overrun
8182 * (0: interrupt disabled, 1: interrupt enabled).
8183 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
8184 * @param ADCx ADC instance
8185 * @retval State of bit (1 or 0).
8186 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)8187 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
8188 {
8189 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
8190 }
8191
8192 /**
8193 * @brief Get state of interruption ADC group regular end of sampling
8194 * (0: interrupt disabled, 1: interrupt enabled).
8195 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
8196 * @param ADCx ADC instance
8197 * @retval State of bit (1 or 0).
8198 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)8199 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
8200 {
8201 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
8202 }
8203
8204 /**
8205 * @brief Get state of interruption ADC group injected end of unitary conversion
8206 * (0: interrupt disabled, 1: interrupt enabled).
8207 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
8208 * @param ADCx ADC instance
8209 * @retval State of bit (1 or 0).
8210 */
LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef * ADCx)8211 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
8212 {
8213 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
8214 }
8215
8216 /**
8217 * @brief Get state of interruption ADC group injected end of sequence conversions
8218 * (0: interrupt disabled, 1: interrupt enabled).
8219 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
8220 * @param ADCx ADC instance
8221 * @retval State of bit (1 or 0).
8222 */
LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef * ADCx)8223 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
8224 {
8225 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
8226 }
8227
8228 /**
8229 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
8230 * (0: interrupt disabled, 1: interrupt enabled).
8231 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
8232 * @param ADCx ADC instance
8233 * @retval State of bit (1 or 0).
8234 */
LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef * ADCx)8235 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx)
8236 {
8237 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
8238 }
8239
8240 /**
8241 * @brief Get state of interruption ADC analog watchdog 1
8242 * (0: interrupt disabled, 1: interrupt enabled).
8243 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
8244 * @param ADCx ADC instance
8245 * @retval State of bit (1 or 0).
8246 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)8247 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
8248 {
8249 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
8250 }
8251
8252 /**
8253 * @brief Get state of interruption Get ADC analog watchdog 2
8254 * (0: interrupt disabled, 1: interrupt enabled).
8255 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
8256 * @param ADCx ADC instance
8257 * @retval State of bit (1 or 0).
8258 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)8259 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
8260 {
8261 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
8262 }
8263
8264 /**
8265 * @brief Get state of interruption Get ADC analog watchdog 3
8266 * (0: interrupt disabled, 1: interrupt enabled).
8267 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
8268 * @param ADCx ADC instance
8269 * @retval State of bit (1 or 0).
8270 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)8271 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
8272 {
8273 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
8274 }
8275
8276 /**
8277 * @}
8278 */
8279
8280 #if defined(USE_FULL_LL_DRIVER)
8281 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
8282 * @{
8283 */
8284
8285 /* Initialization of some features of ADC common parameters and multimode */
8286 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
8287 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
8288 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
8289
8290 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
8291 /* (availability of ADC group injected depends on STM32 series) */
8292 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
8293
8294 /* Initialization of some features of ADC instance */
8295 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
8296 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
8297
8298 /* Initialization of some features of ADC instance and ADC group regular */
8299 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
8300 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
8301
8302 /* Initialization of some features of ADC instance and ADC group injected */
8303 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
8304 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
8305
8306 /**
8307 * @}
8308 */
8309 #endif /* USE_FULL_LL_DRIVER */
8310
8311 /**
8312 * @}
8313 */
8314
8315 /**
8316 * @}
8317 */
8318
8319 #endif /* ADC1 || ADC2 */
8320
8321 /**
8322 * @}
8323 */
8324
8325 #ifdef __cplusplus
8326 }
8327 #endif
8328
8329 #endif /* STM32H5xx_LL_ADC_H */
8330
