1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32C0xx_LL_ADC_H
21 #define STM32C0xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32c0xx.h"
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer rank bits position into the selected register */
51
52 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
53
54 /* Definition of ADC group regular sequencer bits information to be inserted */
55 /* into ADC group regular sequencer ranks literals definition. */
56 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
57 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
58 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
59 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
60 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
61 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
62 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
63 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
64
65
66 /* Internal mask for ADC group regular trigger: */
67 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
68 /* - regular trigger source */
69 /* - regular trigger edge */
70 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for
71 compatibility with some ADC on other STM32 series
72 having this setting set by HW default value) */
73
74 /* Mask containing trigger source masks for each of possible */
75 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
76 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
77 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
78 ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
79 ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
80 ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
81
82 /* Mask containing trigger edge masks for each of possible */
83 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
84 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
85 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
86 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
87 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
88 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
89
90 /* Definition of ADC group regular trigger bits information. */
91 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
92 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */
93
94
95 /* Internal mask for ADC channel: */
96 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
97 /* - channel identifier defined by number */
98 /* - channel identifier defined by bitfield */
99 /* - channel differentiation between external channels (connected to */
100 /* GPIO pins) and internal channels (connected to internal paths) */
101 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
102 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
103 #define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to
104 ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
105 if set to mode "fully configurable", can contain channels with a restricted channel number.
106 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
107 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
108 position in register */
109 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
110 ADC_CHANNEL_ID_INTERNAL_CH_MASK)
111 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
112 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
113 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
114
115 /* Channel differentiation between external and internal channels */
116 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
117 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
118
119 /* Definition of channels ID number information to be inserted into */
120 /* channels literals definition. */
121 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
122 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
123 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
124 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
125 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
126 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
127 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
128 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
129 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
130 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
131 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
132 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
133 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
134 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
135 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
136 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
137 ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
138 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
139 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
140 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
141
142 #define ADC_CHANNEL_19_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
143 #define ADC_CHANNEL_20_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 )
144 #define ADC_CHANNEL_21_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
145 #define ADC_CHANNEL_22_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
146
147 /* Definition of channels ID bitfield information to be inserted into */
148 /* channels literals definition. */
149 #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
150 #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
151 #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
152 #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
153 #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
154 #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
155 #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
156 #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
157 #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
158 #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
159 #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
160 #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
161 #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
162 #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
163 #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
164 #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
165 #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
166 #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
167 #define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
168 #define ADC_CHANNEL_19_BITFIELD (ADC_CHSELR_CHSEL19)
169 #define ADC_CHANNEL_20_BITFIELD (ADC_CHSELR_CHSEL20)
170 #define ADC_CHANNEL_21_BITFIELD (ADC_CHSELR_CHSEL21)
171 #define ADC_CHANNEL_22_BITFIELD (ADC_CHSELR_CHSEL22)
172
173 /* Internal mask for ADC channel sampling time: */
174 /* To select into literals LL_ADC_SAMPLINGTIME_x */
175 /* the relevant bits for: */
176 /* (concatenation of multiple bits used in register SMPR) */
177 /* - ADC channels sampling time: setting channel wise, to map each channel */
178 /* on one of the common sampling time available. */
179 /* - ADC channels common sampling time: set a sampling time into one of the */
180 /* common sampling time available. */
181 #define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
182 #define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
183 #define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
184
185 /* Internal mask for ADC analog watchdog: */
186 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
187 /* (concatenation of multiple bits used in different analog watchdogs, */
188 /* (feature of several watchdogs not available on all STM32 series)). */
189 /* - analog watchdog 1: monitored channel defined by number, */
190 /* selection of ADC group (ADC group regular). */
191 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
192 /* selection on groups. */
193
194 /* Internal register offset for ADC analog watchdog channel configuration */
195 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
196 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
197 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
198
199 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
200 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
201 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
202 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
203
204 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
205 #define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
206
207 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
208 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
209 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
210
211 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
212 in ADC_AWD_CRX_REGOFFSET_MASK */
213
214 /* Internal register offset for ADC analog watchdog threshold configuration */
215 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
216 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
217 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
218 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
219 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
220 in ADC_AWD_TRX_REGOFFSET_MASK */
221 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
222 threshold high: mask of bit */
223 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
224 threshold high: position of bit */
225 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
226 position to perform a shift of 4 ranks */
227 #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
228
229
230 /* ADC registers bits positions */
231 #define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */
232 #define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
233 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */
234 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
235 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
236 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
237 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
238 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
239 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
240 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
241 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
242 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
243 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
244 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
245 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
246 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
247 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
248 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
249 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
250 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
251 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
252 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
253 #define ADC_CHSELR_CHSEL19_BITOFFSET_POS (19UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL19" position in register */
254 #define ADC_CHSELR_CHSEL20_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL20" position in register */
255 #define ADC_CHSELR_CHSEL21_BITOFFSET_POS (21UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL21" position in register */
256 #define ADC_CHSELR_CHSEL22_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL22" position in register */
257 #define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */
258 #define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */
259 #define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
260
261
262 /* ADC registers bits groups */
263 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART \
264 | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property
265 "rs": Software can read as well as set this bit. Writing '0' has no effect
266 on the bit value. */
267
268
269 /* ADC internal channels related definitions */
270 /* Internal voltage reference VrefInt */
271 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF756AUL)) /* Internal voltage reference, address of
272 parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
273 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
274 #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+)
275 voltage with which VrefInt has been calibrated in production
276 (tolerance: +-10 mV) (unit: mV). */
277 /* Temperature sensor */
278 /* Note: On all devices of series STM32C0, calibration parameter TS_CAL2 is not available.
279 Therefore, macro "__LL_ADC_CALC_TEMPERATURE()" is not available,
280 macro "__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS()" must be used and parameter TS_CAL1 can improve accuracy:
281 replace datasheet parameter of temperature offset (macro argument __TEMPSENSOR_TYP_CALX_V__)
282 by TEMPSENSOR_CAL1_ADDR
283 (with taking into account conversion from digital value resolution 12 bit, analog voltage reference ratio
284 between calibration and application environments) */
285 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7568UL)) /* Internal temperature sensor, address of
286 parameter TS_CAL1: On STM32C0, temperature sensor ADC raw data acquired at
287 temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V
288 (tolerance: +-10 mV). */
289 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at
290 which temperature sensor has been calibrated in production for data into
291 TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
292 #define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) voltage
293 with which temperature sensor has been calibrated in production
294 (tolerance: +-10 mV) (unit: mV). */
295
296 /**
297 * @}
298 */
299
300
301 /* Private macros ------------------------------------------------------------*/
302 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
303 * @{
304 */
305
306 /**
307 * @brief Driver macro reserved for internal use: set a pointer to
308 * a register from a register basis from which an offset
309 * is applied.
310 * @param __REG__ Register basis from which the offset is applied.
311 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
312 * @retval Pointer to register address
313 */
314 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
315 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
316
317 /**
318 * @}
319 */
320
321
322 /* Exported types ------------------------------------------------------------*/
323 #if defined(USE_FULL_LL_DRIVER)
324 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
325 * @{
326 */
327
328 /**
329 * @brief Structure definition of some features of ADC common parameters
330 * and multimode
331 * (all ADC instances belonging to the same ADC common instance).
332 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
333 * is conditioned to ADC instances state (all ADC instances
334 * sharing the same ADC common instance):
335 * All ADC instances sharing the same ADC common instance must be
336 * disabled.
337 */
338 typedef struct
339 {
340 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
341 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
342 This feature can be modified afterwards using unitary function
343 @ref LL_ADC_SetCommonClock(). */
344
345 } LL_ADC_CommonInitTypeDef;
346
347 /**
348 * @brief Structure definition of some features of ADC instance.
349 * @note These parameters have an impact on ADC scope: ADC instance.
350 * Refer to corresponding unitary functions into
351 * @ref ADC_LL_EF_Configuration_ADC_Instance .
352 * @note The setting of these parameters by function @ref LL_ADC_Init()
353 * is conditioned to ADC state:
354 * ADC instance must be disabled.
355 * This condition is applied to all ADC features, for efficiency
356 * and compatibility over all STM32 series. However, the different
357 * features can be set under different ADC state conditions
358 * (setting possible with ADC enabled without conversion on going,
359 * ADC enabled with conversion on going, ...)
360 * Each feature can be updated afterwards with a unitary function
361 * and potentially with ADC in a different state than disabled,
362 * refer to description of each function for setting
363 * conditioned to ADC state.
364 */
365 typedef struct
366 {
367 uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
368 This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
369 @note On this STM32 series, this parameter has some clock ratio constraints:
370 ADC clock synchronous (from PCLK) with prescaler 1 must be enabled
371 only if PCLK has a 50% duty clock cycle (APB prescaler configured
372 inside the RCC must be bypassed and the system clock must by 50% duty
373 cycle).
374 This feature can be modified afterwards using unitary function
375 @ref LL_ADC_SetClock().
376 For more details, refer to description of this function. */
377
378 uint32_t Resolution; /*!< Set ADC resolution.
379 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
380 This feature can be modified afterwards using unitary function
381 @ref LL_ADC_SetResolution(). */
382
383 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
384 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
385 This feature can be modified afterwards using unitary function
386 @ref LL_ADC_SetDataAlignment(). */
387
388 uint32_t LowPowerMode; /*!< Set ADC low power mode.
389 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
390 This feature can be modified afterwards using unitary function
391 @ref LL_ADC_SetLowPowerMode(). */
392
393 } LL_ADC_InitTypeDef;
394
395 /**
396 * @brief Structure definition of some features of ADC group regular.
397 * @note These parameters have an impact on ADC scope: ADC group regular.
398 * Refer to corresponding unitary functions into
399 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
400 * (functions with prefix "REG").
401 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
402 * is conditioned to ADC state:
403 * ADC instance must be disabled.
404 * This condition is applied to all ADC features, for efficiency
405 * and compatibility over all STM32 series. However, the different
406 * features can be set under different ADC state conditions
407 * (setting possible with ADC enabled without conversion on going,
408 * ADC enabled with conversion on going, ...)
409 * Each feature can be updated afterwards with a unitary function
410 * and potentially with ADC in a different state than disabled,
411 * refer to description of each function for setting
412 * conditioned to ADC state.
413 */
414 typedef struct
415 {
416 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
417 from external peripheral (timer event, external interrupt line).
418 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
419 @note On this STM32 series, setting trigger source to external trigger also
420 set trigger polarity to rising edge(default setting for compatibility
421 with some ADC on other STM32 series having this setting set by HW
422 default value).
423 In case of need to modify trigger edge, use function
424 @ref LL_ADC_REG_SetTriggerEdge().
425 This feature can be modified afterwards using unitary function
426 @ref LL_ADC_REG_SetTriggerSource(). */
427
428 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
429 @note This parameter has an effect only if group regular sequencer is set
430 to mode "fully configurable". Refer to function
431 @ref LL_ADC_REG_SetSequencerConfigurable().
432 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
433 This feature can be modified afterwards using unitary function
434 @ref LL_ADC_REG_SetSequencerLength(). */
435
436 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
437 and scan conversions interrupted every selected number of ranks.
438 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
439 @note This parameter has an effect only if group regular sequencer is
440 enabled (depending on the sequencer mode: scan length of 2 ranks or
441 more, or several ADC channels enabled in group regular sequencer.
442 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
443 This feature can be modified afterwards using unitary function
444 @ref LL_ADC_REG_SetSequencerDiscont(). */
445
446 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
447 conversions are performed in single mode (one conversion per trigger) or in
448 continuous mode (after the first trigger, following conversions launched
449 successively automatically).
450 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
451 Note: It is not possible to enable both ADC group regular continuous mode
452 and discontinuous mode.
453 This feature can be modified afterwards using unitary function
454 @ref LL_ADC_REG_SetContinuousMode(). */
455
456 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
457 by DMA, and DMA requests mode.
458 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
459 This feature can be modified afterwards using unitary function
460 @ref LL_ADC_REG_SetDMATransfer(). */
461
462 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
463 data preserved or overwritten.
464 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
465 This feature can be modified afterwards using unitary function
466 @ref LL_ADC_REG_SetOverrun(). */
467
468 } LL_ADC_REG_InitTypeDef;
469
470 /**
471 * @}
472 */
473 #endif /* USE_FULL_LL_DRIVER */
474
475 /* Exported constants --------------------------------------------------------*/
476 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
477 * @{
478 */
479
480 /** @defgroup ADC_LL_EC_FLAG ADC flags
481 * @brief Flags defines which can be used with LL_ADC_ReadReg function
482 * @{
483 */
484 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
485 #define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */
486 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
487 conversion */
488 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
489 conversions */
490 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
491 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
492 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
493 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
494 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
495 #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
496 /**
497 * @}
498 */
499
500 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
501 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
502 * @{
503 */
504 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
505 #define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */
506 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
507 conversion */
508 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
509 conversions */
510 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
511 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
512 phase */
513 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
514 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
515 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
516 #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
517 /**
518 * @}
519 */
520
521 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
522 * @{
523 */
524 /* List of ADC registers intended to be used (most commonly) with */
525 /* DMA transfer. */
526 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
527 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
528 (corresponding to register DR) to be used with ADC configured in independent
529 mode. Without DMA transfer, register accessed by LL function
530 @ref LL_ADC_REG_ReadConversionData32() and other
531 functions @ref LL_ADC_REG_ReadConversionDatax() */
532 /**
533 * @}
534 */
535
536 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
537 * @{
538 */
539 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without
540 prescaler */
541 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
542 prescaler division by 2. Setting common to ADC instances of ADC common
543 group, applied ADC instance wise to each instance clock set to clock source
544 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
545 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
546 prescaler division by 4. Setting common to ADC instances of ADC common
547 group, applied ADC instance wise to each instance clock set to clock source
548 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
549 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
550 prescaler division by 6. Setting common to ADC instances of ADC common
551 group, applied ADC instance wise to each instance clock set to clock source
552 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
553 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
554 prescaler division by 8. Setting common to ADC instances of ADC common
555 group, applied ADC instance wise to each instance clock set to clock source
556 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
557 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
558 prescaler division by 10. Setting common to ADC instances of ADC common
559 group, applied ADC instance wise to each instance clock set to clock source
560 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
561 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
562 prescaler division by 12. Setting common to ADC instances of ADC common
563 group, applied ADC instance wise to each instance clock set to clock source
564 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
565 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
566 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
567 prescaler division by 16. Setting common to ADC instances of ADC common
568 group, applied ADC instance wise to each instance clock set to clock source
569 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
570 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
571 prescaler division by 32. Setting common to ADC instances of ADC common
572 group, applied ADC instance wise to each instance clock set to clock source
573 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
574 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
575 prescaler division by 64. Setting common to ADC instances of ADC common
576 group, applied ADC instance wise to each instance clock set to clock source
577 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
578 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
579 prescaler division by 128. Setting common to ADC instances of ADC common
580 group, applied ADC instance wise to each instance clock set to clock source
581 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
582 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
583 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
584 prescaler division by 256. Setting common to ADC instances of ADC common
585 group, applied ADC instance wise to each instance clock set to clock source
586 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
587 /**
588 * @}
589 */
590
591 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
592 * @{
593 */
594 /* Note: Other measurement paths to internal channels may be available */
595 /* (connections to other peripherals). */
596 /* If they are not listed below, they do not require any specific */
597 /* path enable. In this case, Access to measurement path is done */
598 /* only by selecting the corresponding ADC internal channel. */
599 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
600 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
601 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel
602 temperature sensor */
603 /**
604 * @}
605 */
606
607 /** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
608 * @{
609 */
610 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock
611 divided by 4 */
612 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
613 divided by 2 */
614 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 \
615 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
616 not divided */
617 #define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock
618 prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
619 /**
620 * @}
621 */
622
623 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
624 * @{
625 */
626 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
627 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
628 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
629 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
630 /**
631 * @}
632 */
633
634 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
635 * @{
636 */
637 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
638 (alignment on data register LSB bit 0)*/
639 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned
640 (alignment on data register MSB bit 15)*/
641 /**
642 * @}
643 */
644
645 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
646 * @{
647 */
648 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
649 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power
650 mode, ADC conversions are performed only when necessary
651 (when previous ADC conversion data is read).
652 See description with function @ref LL_ADC_SetLowPowerMode(). */
653 #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC
654 automatically powers-off after a ADC conversion and automatically wakes up
655 when a new ADC conversion is triggered (with startup time between trigger
656 and start of sampling). See description with function
657 @ref LL_ADC_SetLowPowerMode(). */
658 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait
659 and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
660 /**
661 * @}
662 */
663
664 /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
665 * @{
666 */
667 #define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency.
668 Note: ADC trigger frequency mode must be set to low frequency when a duration
669 is exceeded before ADC conversion start trigger event (between ADC enable
670 and ADC conversion start trigger event or between two ADC conversion start
671 trigger event).
672 Duration value: Refer to device datasheet, parameter "tIdle". */
673 #define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency.
674 Note: ADC trigger frequency mode must be set to low frequency when a duration
675 is exceeded before ADC conversion start trigger event (between ADC enable
676 and ADC conversion start trigger event or between two ADC conversion start
677 trigger event).
678 Duration value: Refer to device datasheet, parameter "tIdle". */
679 /**
680 * @}
681 */
682
683 /** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE ADC common - Clock frequency mode
684 * @{
685 */
686 #define LL_ADC_CLOCK_FREQ_MODE_HIGH LL_ADC_TRIGGER_FREQ_HIGH /*!< LL ADC define maintained for legacy purpose */
687 #define LL_ADC_CLOCK_FREQ_MODE_LOW LL_ADC_TRIGGER_FREQ_LOW /*!< LL ADC define maintained for legacy purpose */
688 /**
689 * @}
690 */
691
692 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
693 * @{
694 */
695 #define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group
696 of channels: sampling time nb 1 */
697 #define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS \
698 | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group
699 of channels: sampling time nb 2 */
700 /**
701 * @}
702 */
703
704 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
705 * @{
706 */
707 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
708 /**
709 * @}
710 */
711
712 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
713 * @{
714 */
715 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \
716 | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */
717 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \
718 | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */
719 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \
720 | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */
721 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \
722 | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */
723 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \
724 | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */
725 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \
726 | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */
727 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \
728 | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */
729 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \
730 | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */
731 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \
732 | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */
733 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \
734 | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */
735 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \
736 | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
737 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \
738 | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
739 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \
740 | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
741 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \
742 | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
743 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \
744 | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
745 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \
746 | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
747 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \
748 | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
749 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \
750 | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
751 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \
752 | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */
753 #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER \
754 | ADC_CHANNEL_19_BITFIELD) /*!< ADC channel ADCx_IN19 */
755 #define LL_ADC_CHANNEL_20 (ADC_CHANNEL_20_NUMBER \
756 | ADC_CHANNEL_20_BITFIELD) /*!< ADC channel ADCx_IN20 */
757 #define LL_ADC_CHANNEL_21 (ADC_CHANNEL_21_NUMBER \
758 | ADC_CHANNEL_21_BITFIELD) /*!< ADC channel ADCx_IN21 */
759 #define LL_ADC_CHANNEL_22 (ADC_CHANNEL_22_NUMBER \
760 | ADC_CHANNEL_22_BITFIELD) /*!< ADC channel ADCx_IN22 */
761 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_10 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
762 connected to VrefInt: Internal voltage reference. */
763 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_9 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
764 connected to Temperature sensor. */
765 #define LL_ADC_CHANNEL_VDDA (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
766 connected to VDDA. */
767 #define LL_ADC_CHANNEL_VSSA (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
768 connected to VSSA. */
769 /**
770 * @}
771 */
772
773 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
774 * @{
775 */
776 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start */
777 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger
778 from external peripheral: TIM1 TRGO.
779 Trigger edge set to rising edge (default setting). */
780 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
781 conversion trigger from external peripheral:
782 TIM1 channel 4 event (capture compare: input capture or output capture).
783 Trigger edge set to rising edge (default setting). */
784 #if defined(TIM2)
785 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
786 conversion trigger from external peripheral: TIM2 TRGO.
787 Trigger edge set to rising edge (default setting). */
788 #endif /* TIM2 */
789 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
790 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger
791 from external peripheral: TIM3 TRGO.
792 Trigger edge set to rising edge (default setting). */
793 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
794 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
795 conversion trigger from external peripheral: external interrupt line 11.
796 Trigger edge set to rising edge (default setting). */
797 /**
798 * @}
799 */
800
801 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
802 * @{
803 */
804 #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
805 trigger polarity set to rising edge */
806 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion
807 trigger polarity set to falling edge */
808 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
809 trigger polarity set to both rising and falling edges */
810 /**
811 * @}
812 */
813
814 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
815 * @{
816 */
817 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
818 one conversion per trigger */
819 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode:
820 after the first trigger, following conversions launched successively
821 automatically */
822 /**
823 * @}
824 */
825
826 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
827 * @{
828 */
829 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
830 #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA,
831 in limited mode (one shot mode): DMA transfer requests are stopped when
832 number of DMA data transfers (number of ADC conversions) is reached.
833 This ADC mode is intended to be used with DMA mode non-circular. */
834 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are
835 transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
836 whatever number of DMA data transferred (number of ADC conversions).
837 This ADC mode is intended to be used with DMA mode circular. */
838 /**
839 * @}
840 */
841
842 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
843 * @{
844 */
845 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
846 data preserved */
847 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun:
848 data overwritten */
849 /**
850 * @}
851 */
852
853 /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
854 * @{
855 */
856 #define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable:
857 sequencer length and each rank affectation to a channel are fixed
858 by channel HW number. Refer to description of function
859 @ref LL_ADC_REG_SetSequencerChannels(). */
860 #define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable:
861 sequencer length and each rank affectation to a channel are configurable.
862 Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
863 /**
864 * @}
865 */
866
867 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
868 * @{
869 */
870 #define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable
871 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
872 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable
873 with 2 ranks in the sequence */
874 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable
875 with 3 ranks in the sequence */
876 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable
877 with 4 ranks in the sequence */
878 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable
879 with 5 ranks in the sequence */
880 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable
881 with 6 ranks in the sequence */
882 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable
883 with 7 ranks in the sequence */
884 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable
885 with 8 ranks in the sequence */
886 /**
887 * @}
888 */
889
890 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
891 * @{
892 */
893 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only if
894 sequencer set to mode not fully configurable, refer to function
895 @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
896 direction forward: from lowest channel number to highest channel number
897 (scan of all ranks, ADC conversion of ranks with channels enabled in
898 sequencer). On some other STM32 series, this setting is not available
899 and the default scan direction is forward. */
900 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if
901 sequencer set to mode not fully configurable, refer to function
902 @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
903 direction backward: from highest channel number to lowest channel number
904 (scan of all ranks, ADC conversion of ranks with channels enabled in
905 sequencer) */
906 /**
907 * @}
908 */
909
910 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
911 * @{
912 */
913 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
914 discontinuous mode disable */
915 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
916 discontinuous mode enable with sequence interruption every rank */
917 /**
918 * @}
919 */
920
921 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
922 * @{
923 */
924 #define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 1 */
925 #define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 2 */
926 #define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 3 */
927 #define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 4 */
928 #define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 5 */
929 #define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 6 */
930 #define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 7 */
931 #define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 8 */
932 /**
933 * @}
934 */
935
936 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
937 * @{
938 */
939 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
940 #define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
941 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
942 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 \
943 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
944 #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
945 #define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 \
946 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
947 #define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 \
948 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
949 #define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 \
950 | ADC_SMPR_SMP1_1 \
951 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
952 /**
953 * @}
954 */
955
956 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
957 * @{
958 */
959 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
960 | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
961 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
962 | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
963 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
964 | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
965 /**
966 * @}
967 */
968
969 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
970 * @{
971 */
972 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
973 disabled */
974 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
975 | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring
976 of all channels, converted by group regular only */
977 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
978 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
979 of ADC channel ADCx_IN0, converted by group regular only */
980 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
981 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
982 of ADC channel ADCx_IN1, converted by group regular only */
983 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
984 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
985 of ADC channel ADCx_IN2, converted by group regular only */
986 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
987 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
988 of ADC channel ADCx_IN3, converted by group regular only */
989 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
990 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
991 of ADC channel ADCx_IN4, converted by group regular only */
992 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
993 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
994 of ADC channel ADCx_IN5, converted by group regular only */
995 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
996 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
997 of ADC channel ADCx_IN6, converted by group regular only */
998 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
999 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1000 of ADC channel ADCx_IN7, converted by group regular only */
1001 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1002 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1003 of ADC channel ADCx_IN8, converted by group regular only */
1004 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1005 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1006 of ADC channel ADCx_IN9, converted by group regular only */
1007 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1008 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1009 of ADC channel ADCx_IN10, converted by group regular only */
1010 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1011 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1012 of ADC channel ADCx_IN11, converted by group regular only */
1013 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1014 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1015 of ADC channel ADCx_IN12, converted by group regular only */
1016 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1017 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1018 of ADC channel ADCx_IN13, converted by group regular only */
1019 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1020 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1021 of ADC channel ADCx_IN14, converted by group regular only */
1022 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1023 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1024 of ADC channel ADCx_IN15, converted by group regular only */
1025 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1026 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1027 of ADC channel ADCx_IN16, converted by group regular only */
1028 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1029 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1030 of ADC channel ADCx_IN17, converted by group regular only */
1031 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1032 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1033 of ADC channel ADCx_IN18, converted by group regular only */
1034 #define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) \
1035 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1036 of ADC channel ADCx_IN19, converted by group regular only */
1037 #define LL_ADC_AWD_CHANNEL_20_REG ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) \
1038 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1039 of ADC channel ADCx_IN20, converted by group regular only */
1040 #define LL_ADC_AWD_CHANNEL_21_REG ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) \
1041 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1042 of ADC channel ADCx_IN21, converted by group regular only */
1043 #define LL_ADC_AWD_CHANNEL_22_REG ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) \
1044 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1045 of ADC channel ADCx_IN22, converted by group regular only */
1046 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1047 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1048 of ADC internal channel connected to VrefInt: Internal voltage reference,
1049 converted by group regular only */
1050 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1051 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1052 of ADC internal channel connected to Temperature sensor,
1053 converted by group regular only */
1054 #define LL_ADC_AWD_CH_VSSA_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1055 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1056 of ADC internal channel connected to VSSA : internal analog supply ground,
1057 converted by group regular only */
1058 #define LL_ADC_AWD_CH_VDDA_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1059 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1060 of ADC internal channel connected to VDDA : internal analog power supply,
1061 converted by group regular only */
1062 /**
1063 * @}
1064 */
1065
1066 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1067 * @{
1068 */
1069 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1) /*!< ADC analog watchdog threshold high */
1070 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */
1071 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 \
1072 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low
1073 concatenated into the same data */
1074 /**
1075 * @}
1076 */
1077
1078 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1079 * @{
1080 */
1081 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1082 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of
1083 ADC group regular. Literal suffix "continued" is kept for compatibility
1084 with other STM32 devices featuring ADC group injected, in this case other
1085 oversampling scope parameters are available. */
1086 /**
1087 * @}
1088 */
1089
1090 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1091 * @{
1092 */
1093 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
1094 (all conversions of oversampling ratio are done from 1 trigger) */
1095 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous
1096 mode (each conversion of oversampling ratio needs a trigger) */
1097 /**
1098 * @}
1099 */
1100
1101 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1102 * @{
1103 */
1104 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2
1105 (sum of conversions data computed to result as oversampling conversion data
1106 (before potential shift) */
1107 #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4
1108 (sum of conversions data computed to result as oversampling conversion data
1109 (before potential shift) */
1110 #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8
1111 (sum of conversions data computed to result as oversampling conversion data
1112 (before potential shift) */
1113 #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
1114 (sum of conversions data computed to result as oversampling conversion data
1115 (before potential shift) */
1116 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32
1117 (sum of conversions data computed to result as oversampling conversion data
1118 (before potential shift) */
1119 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
1120 (sum of conversions data computed to result as oversampling conversion data
1121 (before potential shift) */
1122 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
1123 (sum of conversions data computed to result as oversampling conversion data
1124 (before potential shift) */
1125 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
1126 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256
1127 (sum of conversions data computed to result as oversampling conversion data
1128 (before potential shift) */
1129 /**
1130 * @}
1131 */
1132
1133 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
1134 * @{
1135 */
1136 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
1137 (sum of the ADC conversions data is not divided to result as oversampling
1138 conversion data) */
1139 #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
1140 (sum of the ADC conversions data (after OVS ratio) is divided by 2
1141 to result as oversampling conversion data) */
1142 #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
1143 (sum of the ADC conversions data (after OVS ratio) is divided by 4
1144 to result as oversampling conversion data) */
1145 #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
1146 (sum of the ADC conversions data (after OVS ratio) is divided by 8
1147 to result as oversampling conversion data) */
1148 #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
1149 (sum of the ADC conversions data (after OVS ratio) is divided by 16
1150 to result as oversampling conversion data) */
1151 #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
1152 (sum of the ADC conversions data (after OVS ratio) is divided by 32
1153 to result as oversampling conversion data) */
1154 #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
1155 (sum of the ADC conversions data (after OVS ratio) is divided by 64
1156 to result as oversampling conversion data) */
1157 #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
1158 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
1159 (sum of the ADC conversions data (after OVS ratio) is divided by 128
1160 to result as oversampling conversion data) */
1161 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
1162 (sum of the ADC conversions data (after OVS ratio) is divided by 256
1163 to result as oversampling conversion data) */
1164 /**
1165 * @}
1166 */
1167
1168 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
1169 * @{
1170 */
1171 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
1172 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
1173 calibration parameters. This value is coded on 16 bits
1174 (to fit on signed word or double word) and corresponds
1175 to an inconsistent temperature value. */
1176 /**
1177 * @}
1178 */
1179
1180 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1181 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1182 * not timeout values.
1183 * For details on delays values, refer to descriptions in source code
1184 * above each literal definition.
1185 * @{
1186 */
1187
1188 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1189 /* not timeout values. */
1190 /* Timeout values for ADC operations are dependent to device clock */
1191 /* configuration (system clock versus ADC clock), */
1192 /* and therefore must be defined in user application. */
1193 /* Indications for estimation of ADC timeout delays, for this */
1194 /* STM32 series: */
1195 /* - ADC calibration time: maximum delay is 82/fADC. */
1196 /* (refer to device datasheet, parameter "tCAL") */
1197 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1198 /* (refer to device datasheet, parameter "tSTAB") */
1199 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1200 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1201 /* cycles */
1202 /* - ADC conversion time: duration depending on ADC clock and ADC */
1203 /* configuration. */
1204 /* (refer to device reference manual, section "Timing") */
1205
1206 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1207 /* Delay set to maximum value (refer to device datasheet, */
1208 /* parameter "tADCVREG_STUP"). */
1209 /* Unit: us */
1210 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage
1211 regulator start-up time) */
1212
1213 /* Delay for internal voltage reference stabilization time. */
1214 /* Delay set to maximum value (refer to device datasheet, */
1215 /* parameter "tstart_vrefint"). */
1216 /* Unit: us */
1217 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
1218 time */
1219
1220 /* Delay for temperature sensor stabilization time. */
1221 /* Literal set to maximum value (refer to device datasheet, */
1222 /* parameter "tSTART"). */
1223 /* Unit: us */
1224 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time
1225 (starting from temperature sensor enable, refer to
1226 @ref LL_ADC_SetCommonPathInternalCh()) */
1227 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization
1228 time (starting from ADC enable, refer to
1229 @ref LL_ADC_Enable()) */
1230
1231 /* Delay required between ADC end of calibration and ADC enable. */
1232 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1233 /* are required between ADC end of calibration and ADC enable. */
1234 /* Wait time can be computed in user application by waiting for the */
1235 /* equivalent number of CPU cycles, by taking into account */
1236 /* ratio of CPU clock versus ADC clock prescalers. */
1237 /* Unit: ADC clock cycles. */
1238 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration
1239 and ADC enable */
1240
1241 /**
1242 * @}
1243 */
1244
1245 /**
1246 * @}
1247 */
1248
1249
1250 /* Exported macro ------------------------------------------------------------*/
1251 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1252 * @{
1253 */
1254
1255 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1256 * @{
1257 */
1258
1259 /**
1260 * @brief Write a value in ADC register
1261 * @param __INSTANCE__ ADC Instance
1262 * @param __REG__ Register to be written
1263 * @param __VALUE__ Value to be written in the register
1264 * @retval None
1265 */
1266 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1267
1268 /**
1269 * @brief Read a value in ADC register
1270 * @param __INSTANCE__ ADC Instance
1271 * @param __REG__ Register to be read
1272 * @retval Register value
1273 */
1274 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1275 /**
1276 * @}
1277 */
1278
1279 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1280 * @{
1281 */
1282
1283 /**
1284 * @brief Helper macro to get ADC channel number in decimal format
1285 * from literals LL_ADC_CHANNEL_x.
1286 * @note Example:
1287 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1288 * will return decimal number "4".
1289 * @note The input can be a value from functions where a channel
1290 * number is returned, either defined with number
1291 * or with bitfield (only one bit must be set).
1292 * @param __CHANNEL__ This parameter can be one of the following values:
1293 * @arg @ref ADC_CHANNEL_0
1294 * @arg @ref ADC_CHANNEL_1
1295 * @arg @ref ADC_CHANNEL_2
1296 * @arg @ref ADC_CHANNEL_3
1297 * @arg @ref ADC_CHANNEL_4
1298 * @arg @ref ADC_CHANNEL_5
1299 * @arg @ref ADC_CHANNEL_6
1300 * @arg @ref ADC_CHANNEL_7
1301 * @arg @ref ADC_CHANNEL_8 (1)
1302 * @arg @ref ADC_CHANNEL_9 (1)
1303 * @arg @ref ADC_CHANNEL_10
1304 * @arg @ref ADC_CHANNEL_11
1305 * @arg @ref ADC_CHANNEL_12
1306 * @arg @ref ADC_CHANNEL_13
1307 * @arg @ref ADC_CHANNEL_14
1308 * @arg @ref ADC_CHANNEL_15 (1)
1309 * @arg @ref ADC_CHANNEL_16 (1)
1310 * @arg @ref ADC_CHANNEL_17 (3)
1311 * @arg @ref ADC_CHANNEL_18 (3)
1312 * @arg @ref ADC_CHANNEL_19 (3)
1313 * @arg @ref ADC_CHANNEL_20 (3)
1314 * @arg @ref ADC_CHANNEL_21 (3)
1315 * @arg @ref ADC_CHANNEL_22 (3)
1316 * @arg @ref ADC_CHANNEL_VREFINT (2)
1317 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
1318 * @arg @ref ADC_CHANNEL_VDDA (2)
1319 * @arg @ref ADC_CHANNEL_VSSA (2)
1320 *
1321 * (1) On STM32C0, parameter can be set in ADC group sequencer
1322 * only if sequencer is set in mode "not fully configurable",
1323 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1324 * (2) For ADC channel read back from ADC register,
1325 * comparison with internal channel parameter to be done
1326 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1327 * (3) ADC channels available on STM32C031xx device only.
1328 * @retval Value between Min_Data=0 and Max_Data=18
1329 */
1330 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1331 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1332 ( \
1333 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1334 ) \
1335 : \
1336 ((((__CHANNEL__) & ADC_CHANNEL_0_BITFIELD) == ADC_CHANNEL_0_BITFIELD) ? (0UL) : \
1337 ((((__CHANNEL__) & ADC_CHANNEL_1_BITFIELD) == ADC_CHANNEL_1_BITFIELD) ? (1UL) : \
1338 ((((__CHANNEL__) & ADC_CHANNEL_2_BITFIELD) == ADC_CHANNEL_2_BITFIELD) ? (2UL) : \
1339 ((((__CHANNEL__) & ADC_CHANNEL_3_BITFIELD) == ADC_CHANNEL_3_BITFIELD) ? (3UL) : \
1340 ((((__CHANNEL__) & ADC_CHANNEL_4_BITFIELD) == ADC_CHANNEL_4_BITFIELD) ? (4UL) : \
1341 ((((__CHANNEL__) & ADC_CHANNEL_5_BITFIELD) == ADC_CHANNEL_5_BITFIELD) ? (5UL) : \
1342 ((((__CHANNEL__) & ADC_CHANNEL_6_BITFIELD) == ADC_CHANNEL_6_BITFIELD) ? (6UL) : \
1343 ((((__CHANNEL__) & ADC_CHANNEL_7_BITFIELD) == ADC_CHANNEL_7_BITFIELD) ? (7UL) : \
1344 ((((__CHANNEL__) & ADC_CHANNEL_8_BITFIELD) == ADC_CHANNEL_8_BITFIELD) ? (8UL) : \
1345 ((((__CHANNEL__) & ADC_CHANNEL_9_BITFIELD) == ADC_CHANNEL_9_BITFIELD) ? (9UL) : \
1346 ((((__CHANNEL__) & ADC_CHANNEL_10_BITFIELD) == ADC_CHANNEL_10_BITFIELD) ? (10UL) : \
1347 ((((__CHANNEL__) & ADC_CHANNEL_11_BITFIELD) == ADC_CHANNEL_11_BITFIELD) ? (11UL) : \
1348 ((((__CHANNEL__) & ADC_CHANNEL_12_BITFIELD) == ADC_CHANNEL_12_BITFIELD) ? (12UL) : \
1349 ((((__CHANNEL__) & ADC_CHANNEL_13_BITFIELD) == ADC_CHANNEL_13_BITFIELD) ? (13UL) : \
1350 ((((__CHANNEL__) & ADC_CHANNEL_14_BITFIELD) == ADC_CHANNEL_14_BITFIELD) ? (14UL) : \
1351 ((((__CHANNEL__) & ADC_CHANNEL_15_BITFIELD) == ADC_CHANNEL_15_BITFIELD) ? (15UL) : \
1352 ((((__CHANNEL__) & ADC_CHANNEL_16_BITFIELD) == ADC_CHANNEL_16_BITFIELD) ? (16UL) : \
1353 ((((__CHANNEL__) & ADC_CHANNEL_17_BITFIELD) == ADC_CHANNEL_17_BITFIELD) ? (17UL) : \
1354 ((((__CHANNEL__) & ADC_CHANNEL_18_BITFIELD) == ADC_CHANNEL_18_BITFIELD) ? (18UL) : \
1355 ((((__CHANNEL__) & ADC_CHANNEL_19_BITFIELD) == ADC_CHANNEL_19_BITFIELD) ? (19UL) : \
1356 ((((__CHANNEL__) & ADC_CHANNEL_20_BITFIELD) == ADC_CHANNEL_20_BITFIELD) ? (20UL) : \
1357 ((((__CHANNEL__) & ADC_CHANNEL_21_BITFIELD) == ADC_CHANNEL_21_BITFIELD) ? (21UL) : \
1358 ((((__CHANNEL__) & ADC_CHANNEL_22_BITFIELD) == ADC_CHANNEL_22_BITFIELD) ? (22UL) : \
1359 (0UL)))))))))))))))))))))))))
1360
1361 /**
1362 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1363 * from number in decimal format.
1364 * @note Example:
1365 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1366 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1367 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1368 * @retval Returned value can be one of the following values:
1369 * @arg @ref ADC_CHANNEL_0
1370 * @arg @ref ADC_CHANNEL_1
1371 * @arg @ref ADC_CHANNEL_2
1372 * @arg @ref ADC_CHANNEL_3
1373 * @arg @ref ADC_CHANNEL_4
1374 * @arg @ref ADC_CHANNEL_5
1375 * @arg @ref ADC_CHANNEL_6
1376 * @arg @ref ADC_CHANNEL_7
1377 * @arg @ref ADC_CHANNEL_8 (1)
1378 * @arg @ref ADC_CHANNEL_9 (1)
1379 * @arg @ref ADC_CHANNEL_10
1380 * @arg @ref ADC_CHANNEL_11
1381 * @arg @ref ADC_CHANNEL_12
1382 * @arg @ref ADC_CHANNEL_13
1383 * @arg @ref ADC_CHANNEL_14
1384 * @arg @ref ADC_CHANNEL_15 (1)
1385 * @arg @ref ADC_CHANNEL_16 (1)
1386 * @arg @ref ADC_CHANNEL_17 (3)
1387 * @arg @ref ADC_CHANNEL_18 (3)
1388 * @arg @ref ADC_CHANNEL_19 (3)
1389 * @arg @ref ADC_CHANNEL_20 (3)
1390 * @arg @ref ADC_CHANNEL_21 (3)
1391 * @arg @ref ADC_CHANNEL_22 (3)
1392 * @arg @ref ADC_CHANNEL_VREFINT (2)
1393 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
1394 * @arg @ref ADC_CHANNEL_VDDA (2)
1395 * @arg @ref ADC_CHANNEL_VSSA (2)
1396 *
1397 * (1) On STM32C0, parameter can be set in ADC group sequencer
1398 * only if sequencer is set in mode "not fully configurable",
1399 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1400 * (2) For ADC channel read back from ADC register,
1401 * comparison with internal channel parameter to be done
1402 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1403 * (3) ADC channels available on STM32C031xx device only.
1404 */
1405 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1406 (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1407 (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)))
1408
1409 /**
1410 * @brief Helper macro to determine whether the selected channel
1411 * corresponds to literal definitions of driver.
1412 * @note The different literal definitions of ADC channels are:
1413 * - ADC internal channel:
1414 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1415 * - ADC external channel (channel connected to a GPIO pin):
1416 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1417 * @note The channel parameter must be a value defined from literal
1418 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1419 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1420 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1421 * must not be a value from functions where a channel number is
1422 * returned from ADC registers,
1423 * because internal and external channels share the same channel
1424 * number in ADC registers. The differentiation is made only with
1425 * parameters definitions of driver.
1426 * @param __CHANNEL__ This parameter can be one of the following values:
1427 * @arg @ref ADC_CHANNEL_0
1428 * @arg @ref ADC_CHANNEL_1
1429 * @arg @ref ADC_CHANNEL_2
1430 * @arg @ref ADC_CHANNEL_3
1431 * @arg @ref ADC_CHANNEL_4
1432 * @arg @ref ADC_CHANNEL_5
1433 * @arg @ref ADC_CHANNEL_6
1434 * @arg @ref ADC_CHANNEL_7
1435 * @arg @ref ADC_CHANNEL_8 (1)
1436 * @arg @ref ADC_CHANNEL_9 (1)
1437 * @arg @ref ADC_CHANNEL_10
1438 * @arg @ref ADC_CHANNEL_11
1439 * @arg @ref ADC_CHANNEL_12
1440 * @arg @ref ADC_CHANNEL_13
1441 * @arg @ref ADC_CHANNEL_14
1442 * @arg @ref ADC_CHANNEL_15 (1)
1443 * @arg @ref ADC_CHANNEL_16 (1)
1444 * @arg @ref ADC_CHANNEL_17 (3)
1445 * @arg @ref ADC_CHANNEL_18 (3)
1446 * @arg @ref ADC_CHANNEL_19 (3)
1447 * @arg @ref ADC_CHANNEL_20 (3)
1448 * @arg @ref ADC_CHANNEL_21 (3)
1449 * @arg @ref ADC_CHANNEL_22 (3)
1450 * @arg @ref ADC_CHANNEL_VREFINT (2)
1451 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
1452 * @arg @ref ADC_CHANNEL_VDDA (2)
1453 * @arg @ref ADC_CHANNEL_VSSA (2)
1454 *
1455 * (1) On STM32C0, parameter can be set in ADC group sequencer
1456 * only if sequencer is set in mode "not fully configurable",
1457 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1458 * (2) For ADC channel read back from ADC register,
1459 * comparison with internal channel parameter to be done
1460 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1461 * (3) ADC channels available on STM32C031xx device only.
1462 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
1463 * (channel connected to a GPIO pin).
1464 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1465 */
1466 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1467 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1468
1469 /**
1470 * @brief Helper macro to convert a channel defined from parameter
1471 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1472 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1473 * to its equivalent parameter definition of a ADC external channel
1474 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1475 * @note The channel parameter can be, additionally to a value
1476 * defined from parameter definition of a ADC internal channel
1477 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1478 * a value defined from parameter definition of
1479 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1480 * or a value from functions where a channel number is returned
1481 * from ADC registers.
1482 * @param __CHANNEL__ This parameter can be one of the following values:
1483 * @arg @ref ADC_CHANNEL_0
1484 * @arg @ref ADC_CHANNEL_1
1485 * @arg @ref ADC_CHANNEL_2
1486 * @arg @ref ADC_CHANNEL_3
1487 * @arg @ref ADC_CHANNEL_4
1488 * @arg @ref ADC_CHANNEL_5
1489 * @arg @ref ADC_CHANNEL_6
1490 * @arg @ref ADC_CHANNEL_7
1491 * @arg @ref ADC_CHANNEL_8 (1)
1492 * @arg @ref ADC_CHANNEL_9 (1)
1493 * @arg @ref ADC_CHANNEL_10
1494 * @arg @ref ADC_CHANNEL_11
1495 * @arg @ref ADC_CHANNEL_12
1496 * @arg @ref ADC_CHANNEL_13
1497 * @arg @ref ADC_CHANNEL_14
1498 * @arg @ref ADC_CHANNEL_15 (1)
1499 * @arg @ref ADC_CHANNEL_16 (1)
1500 * @arg @ref ADC_CHANNEL_17 (3)
1501 * @arg @ref ADC_CHANNEL_18 (3)
1502 * @arg @ref ADC_CHANNEL_19 (3)
1503 * @arg @ref ADC_CHANNEL_20 (3)
1504 * @arg @ref ADC_CHANNEL_21 (3)
1505 * @arg @ref ADC_CHANNEL_22 (3)
1506 * @arg @ref ADC_CHANNEL_VREFINT (2)
1507 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
1508 * @arg @ref ADC_CHANNEL_VDDA (2)
1509 * @arg @ref ADC_CHANNEL_VSSA (2)
1510 *
1511 * (1) On STM32C0, parameter can be set in ADC group sequencer
1512 * only if sequencer is set in mode "not fully configurable",
1513 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1514 * (2) For ADC channel read back from ADC register,
1515 * comparison with internal channel parameter to be done
1516 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1517 * (3) ADC channels available on STM32C031xx device only.
1518 * @retval Returned value can be one of the following values:
1519 * @arg @ref LL_ADC_CHANNEL_0
1520 * @arg @ref LL_ADC_CHANNEL_1
1521 * @arg @ref LL_ADC_CHANNEL_2
1522 * @arg @ref LL_ADC_CHANNEL_3
1523 * @arg @ref LL_ADC_CHANNEL_4
1524 * @arg @ref LL_ADC_CHANNEL_5
1525 * @arg @ref LL_ADC_CHANNEL_6
1526 * @arg @ref LL_ADC_CHANNEL_7
1527 * @arg @ref LL_ADC_CHANNEL_8
1528 * @arg @ref LL_ADC_CHANNEL_9
1529 * @arg @ref LL_ADC_CHANNEL_10
1530 * @arg @ref LL_ADC_CHANNEL_11
1531 * @arg @ref LL_ADC_CHANNEL_12
1532 * @arg @ref LL_ADC_CHANNEL_13
1533 * @arg @ref LL_ADC_CHANNEL_14
1534 * @arg @ref LL_ADC_CHANNEL_15
1535 * @arg @ref LL_ADC_CHANNEL_16
1536 * @arg @ref LL_ADC_CHANNEL_17
1537 * @arg @ref LL_ADC_CHANNEL_18
1538 * @arg @ref LL_ADC_CHANNEL_19
1539 * @arg @ref LL_ADC_CHANNEL_20
1540 * @arg @ref LL_ADC_CHANNEL_21
1541 * @arg @ref LL_ADC_CHANNEL_22
1542 */
1543 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1544 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1545
1546 /**
1547 * @brief Helper macro to determine whether the internal channel
1548 * selected is available on the ADC instance selected.
1549 * @note The channel parameter must be a value defined from parameter
1550 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1551 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1552 * must not be a value defined from parameter definition of
1553 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1554 * or a value from functions where a channel number is
1555 * returned from ADC registers,
1556 * because internal and external channels share the same channel
1557 * number in ADC registers. The differentiation is made only with
1558 * parameters definitions of driver.
1559 * @param __ADC_INSTANCE__ ADC instance
1560 * @param __CHANNEL__ This parameter can be one of the following values:
1561 * @arg @ref ADC_CHANNEL_VREFINT
1562 * @arg @ref ADC_CHANNEL_TEMPSENSOR
1563 * @arg @ref ADC_CHANNEL_VDDA
1564 * @arg @ref ADC_CHANNEL_VSSA
1565 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1566 * Value "1" if the internal channel selected is available on the ADC instance selected.
1567 */
1568 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1569 (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1570 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1571 ((__CHANNEL__) == LL_ADC_CHANNEL_VDDA) || \
1572 ((__CHANNEL__) == LL_ADC_CHANNEL_VSSA))
1573
1574 /**
1575 * @brief Helper macro to define ADC analog watchdog parameter:
1576 * define a single channel to monitor with analog watchdog
1577 * from sequencer channel and groups definition.
1578 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1579 * Example:
1580 * LL_ADC_SetAnalogWDMonitChannels(
1581 * ADC1, LL_ADC_AWD1,
1582 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1583 * @param __CHANNEL__ This parameter can be one of the following values:
1584 * @arg @ref ADC_CHANNEL_0
1585 * @arg @ref ADC_CHANNEL_1
1586 * @arg @ref ADC_CHANNEL_2
1587 * @arg @ref ADC_CHANNEL_3
1588 * @arg @ref ADC_CHANNEL_4
1589 * @arg @ref ADC_CHANNEL_5
1590 * @arg @ref ADC_CHANNEL_6
1591 * @arg @ref ADC_CHANNEL_7
1592 * @arg @ref ADC_CHANNEL_8 (1)
1593 * @arg @ref ADC_CHANNEL_9 (1)
1594 * @arg @ref ADC_CHANNEL_10
1595 * @arg @ref ADC_CHANNEL_11
1596 * @arg @ref ADC_CHANNEL_12
1597 * @arg @ref ADC_CHANNEL_13
1598 * @arg @ref ADC_CHANNEL_14
1599 * @arg @ref ADC_CHANNEL_15 (1)
1600 * @arg @ref ADC_CHANNEL_16 (1)
1601 * @arg @ref ADC_CHANNEL_17 (3)
1602 * @arg @ref ADC_CHANNEL_18 (3)
1603 * @arg @ref ADC_CHANNEL_19 (3)
1604 * @arg @ref ADC_CHANNEL_20 (3)
1605 * @arg @ref ADC_CHANNEL_21 (3)
1606 * @arg @ref ADC_CHANNEL_22 (3)
1607 * @arg @ref ADC_CHANNEL_VREFINT (2)
1608 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
1609 * @arg @ref ADC_CHANNEL_VDDA (2)
1610 * @arg @ref ADC_CHANNEL_VSSA (2)
1611 *
1612 * (1) On STM32C0, parameter can be set in ADC group sequencer
1613 * only if sequencer is set in mode "not fully configurable",
1614 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1615 * (2) For ADC channel read back from ADC register,
1616 * comparison with internal channel parameter to be done
1617 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1618 * (3) ADC channels available on STM32C031xx device only.
1619 * @param __GROUP__ This parameter can be one of the following values:
1620 * @arg @ref LL_ADC_GROUP_REGULAR
1621 * @retval Returned value can be one of the following values:
1622 * @arg @ref LL_ADC_AWD_DISABLE
1623 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1624 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1625 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1626 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1627 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1628 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1629 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1630 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1631 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1632 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1633 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1634 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1635 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1636 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1637 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1638 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1639 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1640 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1641 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1642 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
1643 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1)
1644 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1)
1645 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1)
1646 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
1647 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
1648 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
1649 * @arg @ref LL_ADC_AWD_CH_VDDA_REG
1650 * @arg @ref LL_ADC_AWD_CH_VSSA_REG
1651 * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx.
1652 */
1653 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1654 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
1655
1656 /**
1657 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1658 * or low in function of ADC resolution, when ADC resolution is
1659 * different of 12 bits.
1660 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1661 * or @ref LL_ADC_SetAnalogWDThresholds().
1662 * Example, with a ADC resolution of 8 bits, to set the value of
1663 * analog watchdog threshold high (on 8 bits):
1664 * LL_ADC_SetAnalogWDThresholds
1665 * (< ADCx param >,
1666 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1667 * );
1668 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1669 * @arg @ref LL_ADC_RESOLUTION_12B
1670 * @arg @ref LL_ADC_RESOLUTION_10B
1671 * @arg @ref LL_ADC_RESOLUTION_8B
1672 * @arg @ref LL_ADC_RESOLUTION_6B
1673 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1674 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1675 */
1676 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1677 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1678
1679 /**
1680 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1681 * or low in function of ADC resolution, when ADC resolution is
1682 * different of 12 bits.
1683 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1684 * Example, with a ADC resolution of 8 bits, to get the value of
1685 * analog watchdog threshold high (on 8 bits):
1686 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1687 * (LL_ADC_RESOLUTION_8B,
1688 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1689 * );
1690 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1691 * @arg @ref LL_ADC_RESOLUTION_12B
1692 * @arg @ref LL_ADC_RESOLUTION_10B
1693 * @arg @ref LL_ADC_RESOLUTION_8B
1694 * @arg @ref LL_ADC_RESOLUTION_6B
1695 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1696 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1697 */
1698 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1699 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1700
1701 /**
1702 * @brief Helper macro to get the ADC analog watchdog threshold high
1703 * or low from raw value containing both thresholds concatenated.
1704 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1705 * Example, to get analog watchdog threshold high from the register raw value:
1706 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1707 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1708 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1709 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1710 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1711 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1712 */
1713 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1714 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
1715 & LL_ADC_AWD_THRESHOLD_LOW)
1716
1717 /**
1718 * @brief Helper macro to select the ADC common instance
1719 * to which is belonging the selected ADC instance.
1720 * @note ADC common register instance can be used for:
1721 * - Set parameters common to several ADC instances
1722 * - Multimode (for devices with several ADC instances)
1723 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1724 * @param __ADCx__ ADC instance
1725 * @retval ADC common register instance
1726 */
1727 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1728 (ADC1_COMMON)
1729
1730 /**
1731 * @brief Helper macro to check if all ADC instances sharing the same
1732 * ADC common instance are disabled.
1733 * @note This check is required by functions with setting conditioned to
1734 * ADC state:
1735 * All ADC instances of the ADC common group must be disabled.
1736 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1737 * @note On devices with only 1 ADC common instance, parameter of this macro
1738 * is useless and can be ignored (parameter kept for compatibility
1739 * with devices featuring several ADC common instances).
1740 * @param __ADCXY_COMMON__ ADC common instance
1741 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1742 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1743 * are disabled.
1744 * Value "1" if at least one ADC instance sharing the same ADC common instance
1745 * is enabled.
1746 */
1747 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1748 LL_ADC_IsEnabled(ADC1)
1749
1750 /**
1751 * @brief Helper macro to define the ADC conversion data full-scale digital
1752 * value corresponding to the selected ADC resolution.
1753 * @note ADC conversion data full-scale corresponds to voltage range
1754 * determined by analog voltage references Vref+ and Vref-
1755 * (refer to reference manual).
1756 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1757 * @arg @ref LL_ADC_RESOLUTION_12B
1758 * @arg @ref LL_ADC_RESOLUTION_10B
1759 * @arg @ref LL_ADC_RESOLUTION_8B
1760 * @arg @ref LL_ADC_RESOLUTION_6B
1761 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
1762 */
1763 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1764 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))
1765
1766 /**
1767 * @brief Helper macro to convert the ADC conversion data from
1768 * a resolution to another resolution.
1769 * @param __DATA__ ADC conversion data to be converted
1770 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
1771 * This parameter can be one of the following values:
1772 * @arg @ref LL_ADC_RESOLUTION_12B
1773 * @arg @ref LL_ADC_RESOLUTION_10B
1774 * @arg @ref LL_ADC_RESOLUTION_8B
1775 * @arg @ref LL_ADC_RESOLUTION_6B
1776 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1777 * This parameter can be one of the following values:
1778 * @arg @ref LL_ADC_RESOLUTION_12B
1779 * @arg @ref LL_ADC_RESOLUTION_10B
1780 * @arg @ref LL_ADC_RESOLUTION_8B
1781 * @arg @ref LL_ADC_RESOLUTION_6B
1782 * @retval ADC conversion data to the requested resolution
1783 */
1784 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
1785 __ADC_RESOLUTION_CURRENT__,\
1786 __ADC_RESOLUTION_TARGET__) \
1787 (((__DATA__) \
1788 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))) \
1789 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)) \
1790 )
1791
1792 /**
1793 * @brief Helper macro to calculate the voltage (unit: mVolt)
1794 * corresponding to a ADC conversion data (unit: digital value).
1795 * @note Analog reference voltage (Vref+) must be either known from
1796 * user board environment or can be calculated using ADC measurement
1797 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1798 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1799 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1800 * (unit: digital value).
1801 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1802 * @arg @ref LL_ADC_RESOLUTION_12B
1803 * @arg @ref LL_ADC_RESOLUTION_10B
1804 * @arg @ref LL_ADC_RESOLUTION_8B
1805 * @arg @ref LL_ADC_RESOLUTION_6B
1806 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1807 */
1808 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1809 __ADC_DATA__,\
1810 __ADC_RESOLUTION__) \
1811 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1812 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1813 )
1814
1815 /**
1816 * @brief Helper macro to calculate analog reference voltage (Vref+)
1817 * (unit: mVolt) from ADC conversion data of internal voltage
1818 * reference VrefInt.
1819 * @note Computation is using VrefInt calibration value
1820 * stored in system memory for each device during production.
1821 * @note This voltage depends on user board environment: voltage level
1822 * connected to pin Vref+.
1823 * On devices with small package, the pin Vref+ is not present
1824 * and internally bonded to pin Vdda.
1825 * @note On this STM32 series, calibration data of internal voltage reference
1826 * VrefInt corresponds to a resolution of 12 bits,
1827 * this is the recommended ADC resolution to convert voltage of
1828 * internal voltage reference VrefInt.
1829 * Otherwise, this macro performs the processing to scale
1830 * ADC conversion data to 12 bits.
1831 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1832 * of internal voltage reference VrefInt (unit: digital value).
1833 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1834 * @arg @ref LL_ADC_RESOLUTION_12B
1835 * @arg @ref LL_ADC_RESOLUTION_10B
1836 * @arg @ref LL_ADC_RESOLUTION_8B
1837 * @arg @ref LL_ADC_RESOLUTION_6B
1838 * @retval Analog reference voltage (unit: mV)
1839 */
1840 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1841 __ADC_RESOLUTION__) \
1842 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1843 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1844 (__ADC_RESOLUTION__), \
1845 LL_ADC_RESOLUTION_12B) \
1846 )
1847
1848 /**
1849 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1850 * from ADC conversion data of internal temperature sensor.
1851 * @note Computation is using temperature sensor typical values
1852 * (refer to device datasheet).
1853 * @note Calculation formula:
1854 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1855 * / Avg_Slope + CALx_TEMP
1856 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1857 * (unit: digital value)
1858 * Avg_Slope = temperature sensor slope
1859 * (unit: uV/Degree Celsius)
1860 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1861 * temperature CALx_TEMP (unit: mV)
1862 * Caution: Calculation relevancy under reserve the temperature sensor
1863 * of the current device has characteristics in line with
1864 * datasheet typical values.
1865 * @note: On this STM32 series, calibtation parameter TS_CAL1 can be used
1866 * to improve calculation accuracy.
1867 * Refer to @ref TEMPSENSOR_CAL1_ADDR.
1868 * @note As calculation input, the analog reference voltage (Vref+) must be
1869 * defined as it impacts the ADC LSB equivalent voltage.
1870 * @note Analog reference voltage (Vref+) must be either known from
1871 * user board environment or can be calculated using ADC measurement
1872 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1873 * @note ADC measurement data must correspond to a resolution of 12 bits
1874 * (full scale digital value 4095). If not the case, the data must be
1875 * preliminarily rescaled to an equivalent resolution of 12 bits.
1876 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
1877 (unit: uV/DegCelsius).
1878 * On this STM32 series, refer to device datasheet parameter "Avg_Slope".
1879 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
1880 (at temperature and Vref+ defined in parameters below) (unit: mV).
1881 * On this STM32 series, refer to datasheet parameter "V30" (corresponding
1882 * to TS_CAL1).
1883 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
1884 (see parameter above) is corresponding (unit: mV)
1885 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
1886 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1887 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1888 * This parameter can be one of the following values:
1889 * @arg @ref LL_ADC_RESOLUTION_12B
1890 * @arg @ref LL_ADC_RESOLUTION_10B
1891 * @arg @ref LL_ADC_RESOLUTION_8B
1892 * @arg @ref LL_ADC_RESOLUTION_6B
1893 * @retval Temperature (unit: degree Celsius)
1894 */
1895 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1896 __TEMPSENSOR_TYP_CALX_V__,\
1897 __TEMPSENSOR_CALX_TEMP__,\
1898 __VREFANALOG_VOLTAGE__,\
1899 __TEMPSENSOR_ADC_DATA__,\
1900 __ADC_RESOLUTION__) \
1901 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1902 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1903 * 1000UL) \
1904 - \
1905 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1906 * 1000UL) \
1907 ) \
1908 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
1909 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
1910 )
1911
1912 /**
1913 * @}
1914 */
1915
1916 /**
1917 * @}
1918 */
1919
1920
1921 /* Exported functions --------------------------------------------------------*/
1922 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1923 * @{
1924 */
1925
1926 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1927 * @{
1928 */
1929 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1930 /* configuration of ADC instance, groups and multimode (if available): */
1931 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1932
1933 /**
1934 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1935 * ADC register address from ADC instance and a list of ADC registers
1936 * intended to be used (most commonly) with DMA transfer.
1937 * @note These ADC registers are data registers:
1938 * when ADC conversion data is available in ADC data registers,
1939 * ADC generates a DMA transfer request.
1940 * @note This macro is intended to be used with LL DMA driver, refer to
1941 * function "LL_DMA_ConfigAddresses()".
1942 * Example:
1943 * LL_DMA_ConfigAddresses(DMA1,
1944 * LL_DMA_CHANNEL_1,
1945 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1946 * (uint32_t)&< array or variable >,
1947 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1948 * @note For devices with several ADC: in multimode, some devices
1949 * use a different data register outside of ADC instance scope
1950 * (common data register). This macro manages this register difference,
1951 * only ADC instance has to be set as parameter.
1952 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
1953 * @param ADCx ADC instance
1954 * @param Register This parameter can be one of the following values:
1955 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1956 * @retval ADC register address
1957 */
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1958 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1959 {
1960 /* Prevent unused argument(s) compilation warning */
1961 (void)(Register);
1962
1963 /* Retrieve address of register DR */
1964 return (uint32_t) &(ADCx->DR);
1965 }
1966
1967 /**
1968 * @}
1969 */
1970
1971 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
1972 * ADC instances
1973 * @{
1974 */
1975
1976 /**
1977 * @brief Set parameter common to several ADC: Clock source and prescaler.
1978 * @note On this STM32 series, setting of this feature is conditioned to
1979 * ADC state:
1980 * All ADC instances of the ADC common group must be disabled.
1981 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1982 * ADC instance or by using helper macro helper macro
1983 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1984 * @rmtoll CCR PRESC LL_ADC_SetCommonClock
1985 * @param ADCxy_COMMON ADC common instance
1986 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1987 * @param CommonClock This parameter can be one of the following values:
1988 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1989 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1990 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1991 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1992 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1993 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1994 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1995 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1996 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1997 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1998 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1999 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
2000 *
2001 * (1) ADC common clock asynchronous prescaler is applied to
2002 * each ADC instance if the corresponding ADC instance clock
2003 * is set to clock source asynchronous.
2004 * (refer to function @ref LL_ADC_SetClock() ).
2005 * @retval None
2006 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)2007 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2008 {
2009 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
2010 }
2011
2012 /**
2013 * @brief Get parameter common to several ADC: Clock source and prescaler.
2014 * @rmtoll CCR PRESC LL_ADC_GetCommonClock
2015 * @param ADCxy_COMMON ADC common instance
2016 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2017 * @retval Returned value can be one of the following values:
2018 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
2019 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
2020 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
2021 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
2022 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
2023 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
2024 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
2025 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
2026 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
2027 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
2028 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
2029 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
2030 *
2031 * (1) ADC common clock asynchronous prescaler is applied to
2032 * each ADC instance if the corresponding ADC instance clock
2033 * is set to clock source asynchronous.
2034 * (refer to function @ref LL_ADC_SetClock() ).
2035 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)2036 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2037 {
2038 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
2039 }
2040
2041 /**
2042 * @brief Set parameter common to several ADC: measurement path to
2043 * internal channels (VrefInt, temperature sensor, ...).
2044 * Configure all paths (overwrite current configuration).
2045 * @note One or several values can be selected.
2046 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2047 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2048 * The values not selected are removed from configuration.
2049 * @note Stabilization time of measurement path to internal channel:
2050 * After enabling internal paths, before starting ADC conversion,
2051 * a delay is required for internal voltage reference and
2052 * temperature sensor stabilization time.
2053 * Refer to device datasheet.
2054 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2055 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
2056 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
2057 * @note ADC internal channel sampling time constraint:
2058 * For ADC conversion of internal channels,
2059 * a sampling time minimum value is required.
2060 * Refer to device datasheet.
2061 * @note On this STM32 series, setting of this feature is conditioned to
2062 * ADC state:
2063 * All ADC instances of the ADC common group must be disabled.
2064 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2065 * ADC instance or by using helper macro helper macro
2066 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2067 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2068 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2069 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2070 * @param ADCxy_COMMON ADC common instance
2071 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2072 * @param PathInternal This parameter can be a combination of the following values:
2073 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2074 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2075 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2076 * @retval None
2077 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2078 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2079 {
2080 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
2081 }
2082
2083 /**
2084 * @brief Set parameter common to several ADC: measurement path to
2085 * internal channels (VrefInt, temperature sensor, ...).
2086 * Add paths to the current configuration.
2087 * @note One or several values can be selected.
2088 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2089 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2090 * @note Stabilization time of measurement path to internal channel:
2091 * After enabling internal paths, before starting ADC conversion,
2092 * a delay is required for internal voltage reference and
2093 * temperature sensor stabilization time.
2094 * Refer to device datasheet.
2095 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2096 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
2097 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
2098 * @note ADC internal channel sampling time constraint:
2099 * For ADC conversion of internal channels,
2100 * a sampling time minimum value is required.
2101 * Refer to device datasheet.
2102 * @note On this STM32 series, setting of this feature is conditioned to
2103 * ADC state:
2104 * All ADC instances of the ADC common group must be disabled.
2105 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2106 * ADC instance or by using helper macro helper macro
2107 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2108 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
2109 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
2110 * @param ADCxy_COMMON ADC common instance
2111 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2112 * @param PathInternal This parameter can be a combination of the following values:
2113 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2114 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2115 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2116 * @retval None
2117 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2118 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2119 {
2120 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2121 }
2122
2123 /**
2124 * @brief Set parameter common to several ADC: measurement path to
2125 * internal channels (VrefInt, temperature sensor, ...).
2126 * Remove paths to the current configuration.
2127 * @note One or several values can be selected.
2128 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2129 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2130 * @note On this STM32 series, setting of this feature is conditioned to
2131 * ADC state:
2132 * All ADC instances of the ADC common group must be disabled.
2133 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2134 * ADC instance or by using helper macro helper macro
2135 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2136 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
2137 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
2138 * @param ADCxy_COMMON ADC common instance
2139 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2140 * @param PathInternal This parameter can be a combination of the following values:
2141 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2142 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2143 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2144 * @retval None
2145 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2146 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2147 {
2148 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2149 }
2150
2151 /**
2152 * @brief Get parameter common to several ADC: measurement path to internal
2153 * channels (VrefInt, temperature sensor, ...).
2154 * @note One or several values can be selected.
2155 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2156 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2157 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2158 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2159 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2160 * @param ADCxy_COMMON ADC common instance
2161 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2162 * @retval Returned value can be a combination of the following values:
2163 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2164 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2165 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2166 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)2167 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2168 {
2169 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
2170 }
2171
2172 /**
2173 * @}
2174 */
2175
2176 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2177 * @{
2178 */
2179
2180 /**
2181 * @brief Set ADC instance clock source and prescaler.
2182 * @note On this STM32 series, setting of this feature is conditioned to
2183 * ADC state:
2184 * ADC must be disabled.
2185 * @rmtoll CFGR2 CKMODE LL_ADC_SetClock
2186 * @param ADCx ADC instance
2187 * @param ClockSource This parameter can be one of the following values:
2188 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2189 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2190 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
2191 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
2192 *
2193 * (1) Asynchronous clock prescaler can be configured using
2194 * function @ref LL_ADC_SetCommonClock().\n
2195 * (2) Caution: This parameter has some clock ratio constraints:
2196 * This configuration must be enabled only if PCLK has a 50%
2197 * duty clock cycle (APB prescaler configured inside the RCC
2198 * must be bypassed and the system clock must by 50% duty
2199 * cycle).
2200 * Refer to reference manual.
2201 * @retval None
2202 */
LL_ADC_SetClock(ADC_TypeDef * ADCx,uint32_t ClockSource)2203 __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
2204 {
2205 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
2206 }
2207
2208 /**
2209 * @brief Get ADC instance clock source and prescaler.
2210 * @rmtoll CFGR2 CKMODE LL_ADC_GetClock
2211 * @param ADCx ADC instance
2212 * @retval Returned value can be one of the following values:
2213 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2214 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2215 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
2216 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
2217 *
2218 * (1) Asynchronous clock prescaler can be retrieved using
2219 * function @ref LL_ADC_GetCommonClock().\n
2220 * (2) Caution: This parameter has some clock ratio constraints:
2221 * This configuration must be enabled only if PCLK has a 50%
2222 * duty clock cycle (APB prescaler configured inside the RCC
2223 * must be bypassed and the system clock must by 50% duty
2224 * cycle).
2225 * Refer to reference manual.
2226 */
LL_ADC_GetClock(ADC_TypeDef * ADCx)2227 __STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
2228 {
2229 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
2230 }
2231
2232 /**
2233 * @brief Set ADC calibration factor in the mode single-ended
2234 * or differential (for devices with differential mode available).
2235 * @note This function is intended to set calibration parameters
2236 * without having to perform a new calibration using
2237 * @ref LL_ADC_StartCalibration().
2238 * @note On this STM32 series, setting of this feature is conditioned to
2239 * ADC state:
2240 * ADC must be enabled, without calibration on going, without conversion
2241 * on going on group regular.
2242 * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor
2243 * @param ADCx ADC instance
2244 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2245 * @retval None
2246 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t CalibrationFactor)2247 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
2248 {
2249 MODIFY_REG(ADCx->CALFACT,
2250 ADC_CALFACT_CALFACT,
2251 CalibrationFactor);
2252 }
2253
2254 /**
2255 * @brief Get ADC calibration factor in the mode single-ended
2256 * or differential (for devices with differential mode available).
2257 * @note Calibration factors are set by hardware after performing
2258 * a calibration run using function @ref LL_ADC_StartCalibration().
2259 * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor
2260 * @param ADCx ADC instance
2261 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2262 */
LL_ADC_GetCalibrationFactor(ADC_TypeDef * ADCx)2263 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx)
2264 {
2265 return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
2266 }
2267
2268 /**
2269 * @brief Set ADC resolution.
2270 * Refer to reference manual for alignments formats
2271 * dependencies to ADC resolutions.
2272 * @note On this STM32 series, setting of this feature is conditioned to
2273 * ADC state:
2274 * ADC must be disabled.
2275 * @rmtoll CFGR1 RES LL_ADC_SetResolution
2276 * @param ADCx ADC instance
2277 * @param Resolution This parameter can be one of the following values:
2278 * @arg @ref LL_ADC_RESOLUTION_12B
2279 * @arg @ref LL_ADC_RESOLUTION_10B
2280 * @arg @ref LL_ADC_RESOLUTION_8B
2281 * @arg @ref LL_ADC_RESOLUTION_6B
2282 * @retval None
2283 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2284 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2285 {
2286 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
2287 }
2288
2289 /**
2290 * @brief Get ADC resolution.
2291 * Refer to reference manual for alignments formats
2292 * dependencies to ADC resolutions.
2293 * @rmtoll CFGR1 RES LL_ADC_GetResolution
2294 * @param ADCx ADC instance
2295 * @retval Returned value can be one of the following values:
2296 * @arg @ref LL_ADC_RESOLUTION_12B
2297 * @arg @ref LL_ADC_RESOLUTION_10B
2298 * @arg @ref LL_ADC_RESOLUTION_8B
2299 * @arg @ref LL_ADC_RESOLUTION_6B
2300 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)2301 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2302 {
2303 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
2304 }
2305
2306 /**
2307 * @brief Set ADC conversion data alignment.
2308 * @note Refer to reference manual for alignments formats
2309 * dependencies to ADC resolutions.
2310 * @note On this STM32 series, setting of this feature is conditioned to
2311 * ADC state:
2312 * ADC must be disabled.
2313 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
2314 * @param ADCx ADC instance
2315 * @param DataAlignment This parameter can be one of the following values:
2316 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2317 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2318 * @retval None
2319 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2320 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2321 {
2322 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
2323 }
2324
2325 /**
2326 * @brief Get ADC conversion data alignment.
2327 * @note Refer to reference manual for alignments formats
2328 * dependencies to ADC resolutions.
2329 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
2330 * @param ADCx ADC instance
2331 * @retval Returned value can be one of the following values:
2332 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2333 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2334 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2335 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2336 {
2337 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
2338 }
2339
2340 /**
2341 * @brief Set ADC low power mode.
2342 * @note Description of ADC low power modes:
2343 * - ADC low power mode "auto wait": Dynamic low power mode,
2344 * ADC conversions occurrences are limited to the minimum necessary
2345 * in order to reduce power consumption.
2346 * New ADC conversion starts only when the previous
2347 * unitary conversion data (for ADC group regular)
2348 * has been retrieved by user software.
2349 * In the meantime, ADC remains idle: does not performs any
2350 * other conversion.
2351 * This mode allows to automatically adapt the ADC conversions
2352 * triggers to the speed of the software that reads the data.
2353 * Moreover, this avoids risk of overrun for low frequency
2354 * applications.
2355 * How to use this low power mode:
2356 * - It is not recommended to use with interruption or DMA
2357 * since these modes have to clear immediately the EOC flag
2358 * (by CPU to free the IRQ pending event or by DMA).
2359 * Auto wait will work but fort a very short time, discarding
2360 * its intended benefit (except specific case of high load of CPU
2361 * or DMA transfers which can justify usage of auto wait).
2362 * - Do use with polling: 1. Start conversion,
2363 * 2. Later on, when conversion data is needed: poll for end of
2364 * conversion to ensure that conversion is completed and
2365 * retrieve ADC conversion data. This will trig another
2366 * ADC conversion start.
2367 * - ADC low power mode "auto power-off" (feature available on
2368 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2369 * the ADC automatically powers-off after a conversion and
2370 * automatically wakes up when a new conversion is triggered
2371 * (with startup time between trigger and start of sampling).
2372 * This feature can be combined with low power mode "auto wait".
2373 * @note With ADC low power mode "auto wait", the ADC conversion data read
2374 * is corresponding to previous ADC conversion start, independently
2375 * of delay during which ADC was idle.
2376 * Therefore, the ADC conversion data may be outdated: does not
2377 * correspond to the current voltage level on the selected
2378 * ADC channel.
2379 * @note On this STM32 series, setting of this feature is conditioned to
2380 * ADC state:
2381 * ADC must be disabled.
2382 * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n
2383 * CFGR1 AUTOFF LL_ADC_SetLowPowerMode
2384 * @param ADCx ADC instance
2385 * @param LowPowerMode This parameter can be one of the following values:
2386 * @arg @ref LL_ADC_LP_MODE_NONE
2387 * @arg @ref LL_ADC_LP_AUTOWAIT
2388 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2389 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2390 * @retval None
2391 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2392 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2393 {
2394 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
2395 }
2396
2397 /**
2398 * @brief Get ADC low power mode:
2399 * @note Description of ADC low power modes:
2400 * - ADC low power mode "auto wait": Dynamic low power mode,
2401 * ADC conversions occurrences are limited to the minimum necessary
2402 * in order to reduce power consumption.
2403 * New ADC conversion starts only when the previous
2404 * unitary conversion data (for ADC group regular)
2405 * has been retrieved by user software.
2406 * In the meantime, ADC remains idle: does not performs any
2407 * other conversion.
2408 * This mode allows to automatically adapt the ADC conversions
2409 * triggers to the speed of the software that reads the data.
2410 * Moreover, this avoids risk of overrun for low frequency
2411 * applications.
2412 * How to use this low power mode:
2413 * - It is not recommended to use with interruption or DMA
2414 * since these modes have to clear immediately the EOC flag
2415 * (by CPU to free the IRQ pending event or by DMA).
2416 * Auto wait will work but fort a very short time, discarding
2417 * its intended benefit (except specific case of high load of CPU
2418 * or DMA transfers which can justify usage of auto wait).
2419 * - Do use with polling: 1. Start conversion,
2420 * 2. Later on, when conversion data is needed: poll for end of
2421 * conversion to ensure that conversion is completed and
2422 * retrieve ADC conversion data. This will trig another
2423 * ADC conversion start.
2424 * - ADC low power mode "auto power-off" (feature available on
2425 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2426 * the ADC automatically powers-off after a conversion and
2427 * automatically wakes up when a new conversion is triggered
2428 * (with startup time between trigger and start of sampling).
2429 * This feature can be combined with low power mode "auto wait".
2430 * @note With ADC low power mode "auto wait", the ADC conversion data read
2431 * is corresponding to previous ADC conversion start, independently
2432 * of delay during which ADC was idle.
2433 * Therefore, the ADC conversion data may be outdated: does not
2434 * correspond to the current voltage level on the selected
2435 * ADC channel.
2436 * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n
2437 * CFGR1 AUTOFF LL_ADC_GetLowPowerMode
2438 * @param ADCx ADC instance
2439 * @retval Returned value can be one of the following values:
2440 * @arg @ref LL_ADC_LP_MODE_NONE
2441 * @arg @ref LL_ADC_LP_AUTOWAIT
2442 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2443 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2444 */
LL_ADC_GetLowPowerMode(ADC_TypeDef * ADCx)2445 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
2446 {
2447 return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
2448 }
2449
2450 /**
2451 * @brief Set ADC trigger frequency mode.
2452 * @note ADC trigger frequency mode must be set to low frequency when
2453 * a duration is exceeded before ADC conversion start trigger event
2454 * (between ADC enable and ADC conversion start trigger event
2455 * or between two ADC conversion start trigger event).
2456 * Duration value: Refer to device datasheet, parameter "tIdle".
2457 * @note When ADC trigger frequency mode is set to low frequency,
2458 * some rearm cycles are inserted before performing ADC conversion
2459 * start, inducing a delay of 2 ADC clock cycles.
2460 * @note Usage of ADC trigger frequency mode with ADC low power mode:
2461 * - Low power mode auto wait: Only the first ADC conversion
2462 * start trigger inserts the rearm delay.
2463 * - Low power mode auto power-off: ADC trigger frequency mode
2464 * is discarded.
2465 * @note On this STM32 series, setting of this feature is conditioned to
2466 * ADC state:
2467 * ADC must be disabled.
2468 * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
2469 * @param ADCx ADC instance
2470 * @param TriggerFrequencyMode This parameter can be one of the following values:
2471 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2472 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2473 * @retval None
2474 */
LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef * ADCx,uint32_t TriggerFrequencyMode)2475 __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
2476 {
2477 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);
2478 }
2479
2480 /**
2481 * @brief Get ADC trigger frequency mode.
2482 * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
2483 * @param ADCx ADC instance
2484 * @retval Returned value can be one of the following values:
2485 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2486 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2487 */
LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef * ADCx)2488 __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx)
2489 {
2490 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
2491 }
2492
2493 /**
2494 * @brief Set sampling time common to a group of channels.
2495 * @note Unit: ADC clock cycles.
2496 * @note On this STM32 series, sampling time scope is on ADC instance:
2497 * Sampling time common to all channels.
2498 * (on some other STM32 families, sampling time is channel wise)
2499 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
2500 * converted:
2501 * sampling time constraints must be respected (sampling time can be
2502 * adjusted in function of ADC clock frequency and sampling time
2503 * setting).
2504 * Refer to device datasheet for timings values (parameters TS_vrefint,
2505 * TS_temp, ...).
2506 * @note Conversion time is the addition of sampling time and processing time.
2507 * On this STM32 series, ADC processing time is:
2508 * - 12.5 ADC clock cycles at ADC resolution 12 bits
2509 * - 10.5 ADC clock cycles at ADC resolution 10 bits
2510 * - 8.5 ADC clock cycles at ADC resolution 8 bits
2511 * - 6.5 ADC clock cycles at ADC resolution 6 bits
2512 * @note In case of ADC conversion of internal channel (VrefInt,
2513 * temperature sensor, ...), a sampling time minimum value
2514 * is required.
2515 * Refer to device datasheet.
2516 * @note On this STM32 series, setting of this feature is conditioned to
2517 * ADC state:
2518 * ADC must be disabled or enabled without conversion on going
2519 * on group regular.
2520 * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n
2521 * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
2522 * @param ADCx ADC instance
2523 * @param SamplingTimeY This parameter can be one of the following values:
2524 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2525 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2526 * @param SamplingTime This parameter can be one of the following values:
2527 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2528 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2529 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2530 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2531 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2532 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2533 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2534 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2535 * @retval None
2536 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY,uint32_t SamplingTime)2537 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
2538 uint32_t SamplingTime)
2539 {
2540 MODIFY_REG(ADCx->SMPR,
2541 ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
2542 SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2543 }
2544
2545 /**
2546 * @brief Get sampling time common to a group of channels.
2547 * @note Unit: ADC clock cycles.
2548 * @note On this STM32 series, sampling time scope is on ADC instance:
2549 * Sampling time common to all channels.
2550 * (on some other STM32 families, sampling time is channel wise)
2551 * @note Conversion time is the addition of sampling time and processing time.
2552 * Refer to reference manual for ADC processing time of
2553 * this STM32 series.
2554 * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n
2555 * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
2556 * @param ADCx ADC instance
2557 * @param SamplingTimeY This parameter can be one of the following values:
2558 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2559 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2560 * @retval Returned value can be one of the following values:
2561 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2562 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2563 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2564 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2565 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2566 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2567 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2568 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2569 */
LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY)2570 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
2571 {
2572 return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
2573 >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2574 }
2575
2576 /**
2577 * @}
2578 */
2579
2580 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2581 * @{
2582 */
2583
2584 /**
2585 * @brief Set ADC group regular conversion trigger source:
2586 * internal (SW start) or from external peripheral (timer event,
2587 * external interrupt line).
2588 * @note On this STM32 series, setting trigger source to external trigger
2589 * also set trigger polarity to rising edge
2590 * (default setting for compatibility with some ADC on other
2591 * STM32 families having this setting set by HW default value).
2592 * In case of need to modify trigger edge, use
2593 * function @ref LL_ADC_REG_SetTriggerEdge().
2594 * @note On this STM32 series, ADC trigger frequency mode must be set
2595 * in function of frequency of ADC group regular conversion trigger.
2596 * Refer to description of function
2597 * @ref LL_ADC_SetTriggerFrequencyMode().
2598 * @note Availability of parameters of trigger sources from timer
2599 * depends on timers availability on the selected device.
2600 * @note On this STM32 series, setting of this feature is conditioned to
2601 * ADC state:
2602 * ADC must be disabled.
2603 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
2604 * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
2605 * @param ADCx ADC instance
2606 * @param TriggerSource This parameter can be one of the following values:
2607 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2608 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2609 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2610 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
2611 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2612 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2613 * (1) ADC external trigger available on STM32C071xx device only.
2614 * @retval None
2615 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2616 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2617 {
2618 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
2619 }
2620
2621 /**
2622 * @brief Get ADC group regular conversion trigger source:
2623 * internal (SW start) or from external peripheral (timer event,
2624 * external interrupt line).
2625 * @note To determine whether group regular trigger source is
2626 * internal (SW start) or external, without detail
2627 * of which peripheral is selected as external trigger,
2628 * (equivalent to
2629 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2630 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2631 * @note Availability of parameters of trigger sources from timer
2632 * depends on timers availability on the selected device.
2633 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
2634 * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
2635 * @param ADCx ADC instance
2636 * @retval Returned value can be one of the following values:
2637 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2638 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2639 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2640 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
2641 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2642 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2643 * (1) ADC external trigger available on STM32C071xx device only.
2644 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)2645 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2646 {
2647 __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
2648
2649 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2650 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
2651 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2652
2653 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
2654 /* to match with triggers literals definition. */
2655 return ((TriggerSource
2656 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
2657 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
2658 );
2659 }
2660
2661 /**
2662 * @brief Get ADC group regular conversion trigger source internal (SW start)
2663 * or external.
2664 * @note In case of group regular trigger source set to external trigger,
2665 * to determine which peripheral is selected as external trigger,
2666 * use function @ref LL_ADC_REG_GetTriggerSource().
2667 * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2668 * @param ADCx ADC instance
2669 * @retval Value "0" if trigger source external trigger
2670 * Value "1" if trigger source SW start.
2671 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2672 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2673 {
2674 return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
2675 }
2676
2677 /**
2678 * @brief Set ADC group regular conversion trigger polarity.
2679 * @note Applicable only for trigger source set to external trigger.
2680 * @note On this STM32 series, setting of this feature is conditioned to
2681 * ADC state:
2682 * ADC must be disabled or enabled without conversion on going
2683 * on group regular.
2684 * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
2685 * @param ADCx ADC instance
2686 * @param ExternalTriggerEdge This parameter can be one of the following values:
2687 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2688 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2689 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2690 * @retval None
2691 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)2692 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
2693 {
2694 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
2695 }
2696
2697 /**
2698 * @brief Get ADC group regular conversion trigger polarity.
2699 * @note Applicable only for trigger source set to external trigger.
2700 * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
2701 * @param ADCx ADC instance
2702 * @retval Returned value can be one of the following values:
2703 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2704 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2705 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2706 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)2707 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2708 {
2709 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
2710 }
2711
2712 /**
2713 * @brief Set ADC group regular sequencer configuration flexibility.
2714 * @note On this STM32 series, ADC group regular sequencer both modes
2715 * "fully configurable" or "not fully configurable" are
2716 * available:
2717 * - sequencer configured to fully configurable:
2718 * sequencer length and each rank
2719 * affectation to a channel are configurable.
2720 * Refer to description of function
2721 * @ref LL_ADC_REG_SetSequencerLength().
2722 * - sequencer configured to not fully configurable:
2723 * sequencer length and each rank affectation to a channel
2724 * are fixed by channel HW number.
2725 * Refer to description of function
2726 * @ref LL_ADC_REG_SetSequencerChannels().
2727 * @note On this STM32 series, after modifying sequencer (functions
2728 * @ref LL_ADC_REG_SetSequencerLength()
2729 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2730 * it is mandatory to wait for the assertion of CCRDY flag
2731 * Otherwise, some actions may be ignored.
2732 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2733 * for more details.
2734 * @note On this STM32 series, setting of this feature is conditioned to
2735 * ADC state:
2736 * ADC must be disabled.
2737 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2738 * @param ADCx ADC instance
2739 * @param Configurability This parameter can be one of the following values:
2740 * @arg @ref LL_ADC_REG_SEQ_FIXED
2741 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2742 * @retval None
2743 */
LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef * ADCx,uint32_t Configurability)2744 __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
2745 {
2746 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);
2747 }
2748
2749 /**
2750 * @brief Get ADC group regular sequencer configuration flexibility.
2751 * @note On this STM32 series, ADC group regular sequencer both modes
2752 * "fully configurable" or "not fully configurable" are
2753 * available:
2754 * - sequencer configured to fully configurable:
2755 * sequencer length and each rank
2756 * affectation to a channel are configurable.
2757 * Refer to description of function
2758 * @ref LL_ADC_REG_SetSequencerLength().
2759 * - sequencer configured to not fully configurable:
2760 * sequencer length and each rank affectation to a channel
2761 * are fixed by channel HW number.
2762 * Refer to description of function
2763 * @ref LL_ADC_REG_SetSequencerChannels().
2764 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2765 * @param ADCx ADC instance
2766 * @retval Returned value can be one of the following values:
2767 * @arg @ref LL_ADC_REG_SEQ_FIXED
2768 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2769 */
LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef * ADCx)2770 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx)
2771 {
2772 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
2773 }
2774
2775 /**
2776 * @brief Set ADC group regular sequencer length and scan direction.
2777 * @note Description of ADC group regular sequencer features:
2778 * - For devices with sequencer fully configurable
2779 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2780 * sequencer length and each rank affectation to a channel
2781 * are configurable.
2782 * This function performs configuration of:
2783 * - Sequence length: Number of ranks in the scan sequence.
2784 * - Sequence direction: Unless specified in parameters, sequencer
2785 * scan direction is forward (from rank 1 to rank n).
2786 * Sequencer ranks are selected using
2787 * function "LL_ADC_REG_SetSequencerRanks()".
2788 * - For devices with sequencer not fully configurable
2789 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2790 * sequencer length and each rank affectation to a channel
2791 * are defined by channel number.
2792 * This function performs configuration of:
2793 * - Sequence length: Number of ranks in the scan sequence is
2794 * defined by number of channels set in the sequence,
2795 * rank of each channel is fixed by channel HW number.
2796 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2797 * - Sequence direction: Unless specified in parameters, sequencer
2798 * scan direction is forward (from lowest channel number to
2799 * highest channel number).
2800 * Sequencer ranks are selected using
2801 * function "LL_ADC_REG_SetSequencerChannels()".
2802 * To set scan direction differently, refer to function
2803 * @ref LL_ADC_REG_SetSequencerScanDirection().
2804 * @note On this STM32 series, ADC group regular sequencer both modes
2805 * "fully configurable" or "not fully configurable"
2806 * are available, they can be chosen using
2807 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2808 * @note On this STM32 series, after modifying sequencer (functions
2809 * @ref LL_ADC_REG_SetSequencerLength()
2810 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2811 * it is mandatory to wait for the assertion of CCRDY flag
2812 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2813 * Otherwise, some actions may be ignored.
2814 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2815 * for more details.
2816 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2817 * ADC conversion on only 1 channel.
2818 * @note On this STM32 series, setting of this feature is conditioned to
2819 * ADC state:
2820 * ADC must be disabled or enabled without conversion on going
2821 * on group regular.
2822 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n
2823 * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n
2824 * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n
2825 * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n
2826 * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n
2827 * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n
2828 * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n
2829 * CHSELR SQ8 LL_ADC_REG_SetSequencerLength
2830 * @param ADCx ADC instance
2831 * @param SequencerNbRanks This parameter can be one of the following values:
2832 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2833 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2834 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2835 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2836 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2837 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2838 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2839 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2840 * @retval None
2841 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2842 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2843 {
2844 SET_BIT(ADCx->CHSELR, SequencerNbRanks);
2845 }
2846
2847 /**
2848 * @brief Get ADC group regular sequencer length and scan direction.
2849 * @note Description of ADC group regular sequencer features:
2850 * - For devices with sequencer fully configurable
2851 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2852 * sequencer length and each rank affectation to a channel
2853 * are configurable.
2854 * This function retrieves:
2855 * - Sequence length: Number of ranks in the scan sequence.
2856 * - Sequence direction: Unless specified in parameters, sequencer
2857 * scan direction is forward (from rank 1 to rank n).
2858 * Sequencer ranks are selected using
2859 * function "LL_ADC_REG_SetSequencerRanks()".
2860 * - For devices with sequencer not fully configurable
2861 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2862 * sequencer length and each rank affectation to a channel
2863 * are defined by channel number.
2864 * This function retrieves:
2865 * - Sequence length: Number of ranks in the scan sequence is
2866 * defined by number of channels set in the sequence,
2867 * rank of each channel is fixed by channel HW number.
2868 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2869 * - Sequence direction: Unless specified in parameters, sequencer
2870 * scan direction is forward (from lowest channel number to
2871 * highest channel number).
2872 * Sequencer ranks are selected using
2873 * function "LL_ADC_REG_SetSequencerChannels()".
2874 * To set scan direction differently, refer to function
2875 * @ref LL_ADC_REG_SetSequencerScanDirection().
2876 * @note On this STM32 series, ADC group regular sequencer both modes
2877 * "fully configurable" or "not fully configurable"
2878 * are available, they can be chosen using
2879 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2880 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2881 * ADC conversion on only 1 channel.
2882 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n
2883 * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n
2884 * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n
2885 * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n
2886 * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n
2887 * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n
2888 * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n
2889 * CHSELR SQ8 LL_ADC_REG_GetSequencerLength
2890 * @param ADCx ADC instance
2891 * @retval Returned value can be one of the following values:
2892 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2893 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2894 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2895 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2896 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2897 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2898 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2899 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2900 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)2901 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2902 {
2903 __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
2904 uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
2905 uint32_t RankIndex;
2906
2907 /* Parse register for end of sequence identifier */
2908 for (RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex += 4U)
2909 {
2910 if ((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex))
2911 {
2912 SequencerLength = (ADC_CHSELR_SQ2 << RankIndex);
2913 break;
2914 }
2915 }
2916
2917 return SequencerLength;
2918 }
2919
2920 /**
2921 * @brief Set ADC group regular sequencer scan direction.
2922 * @note On this STM32 series, parameter relevant only is sequencer is set
2923 * to mode not fully configurable,
2924 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2925 * @note On some other STM32 series, this setting is not available and
2926 * the default scan direction is forward.
2927 * @note On this STM32 series, after modifying sequencer (functions
2928 * @ref LL_ADC_REG_SetSequencerLength()
2929 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2930 * it is mandatory to wait for the assertion of CCRDY flag
2931 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2932 * Otherwise, some actions may be ignored.
2933 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2934 * for more details.
2935 * @note On this STM32 series, setting of this feature is conditioned to
2936 * ADC state:
2937 * ADC must be disabled.
2938 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
2939 * @param ADCx ADC instance
2940 * @param ScanDirection This parameter can be one of the following values:
2941 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2942 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2943 * @retval None
2944 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)2945 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
2946 {
2947 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
2948 }
2949
2950 /**
2951 * @brief Get ADC group regular sequencer scan direction.
2952 * @note On this STM32 series, parameter relevant only is sequencer is set
2953 * to mode not fully configurable,
2954 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2955 * @note On some other STM32 families, this setting is not available and
2956 * the default scan direction is forward.
2957 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
2958 * @param ADCx ADC instance
2959 * @retval Returned value can be one of the following values:
2960 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2961 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2962 */
LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef * ADCx)2963 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
2964 {
2965 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
2966 }
2967
2968 /**
2969 * @brief Set ADC group regular sequencer discontinuous mode:
2970 * sequence subdivided and scan conversions interrupted every selected
2971 * number of ranks.
2972 * @note It is not possible to enable both ADC group regular
2973 * continuous mode and sequencer discontinuous mode.
2974 * @note On this STM32 series, setting of this feature is conditioned to
2975 * ADC state:
2976 * ADC must be disabled.
2977 * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2978 * @param ADCx ADC instance
2979 * @param SeqDiscont This parameter can be one of the following values:
2980 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2981 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2982 * @retval None
2983 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2984 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2985 {
2986 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
2987 }
2988
2989 /**
2990 * @brief Get ADC group regular sequencer discontinuous mode:
2991 * sequence subdivided and scan conversions interrupted every selected
2992 * number of ranks.
2993 * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2994 * @param ADCx ADC instance
2995 * @retval Returned value can be one of the following values:
2996 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2997 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2998 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)2999 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
3000 {
3001 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
3002 }
3003
3004 /**
3005 * @brief Set ADC group regular sequence: channel on the selected
3006 * scan sequence rank.
3007 * @note This function performs configuration of:
3008 * - Channels ordering into each rank of scan sequence:
3009 * whatever channel can be placed into whatever rank.
3010 * @note On this STM32 series, ADC group regular sequencer is
3011 * fully configurable: sequencer length and each rank
3012 * affectation to a channel are configurable.
3013 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3014 * @note Depending on devices and packages, some channels may not be available.
3015 * Refer to device datasheet for channels availability.
3016 * @note On this STM32 series, to measure internal channels (VrefInt,
3017 * TempSensor, ...), measurement paths to internal channels must be
3018 * enabled separately.
3019 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3020 * @note On this STM32 series, after modifying sequencer (functions
3021 * @ref LL_ADC_REG_SetSequencerLength()
3022 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3023 * it is mandatory to wait for the assertion of CCRDY flag
3024 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3025 * Otherwise, some actions may be ignored.
3026 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3027 * for more details.
3028 * @note On this STM32 series, setting of this feature is conditioned to
3029 * ADC state:
3030 * ADC must be disabled or enabled without conversion on going
3031 * on group regular.
3032 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerRanks\n
3033 * CHSELR SQ2 LL_ADC_REG_SetSequencerRanks\n
3034 * CHSELR SQ3 LL_ADC_REG_SetSequencerRanks\n
3035 * CHSELR SQ4 LL_ADC_REG_SetSequencerRanks\n
3036 * CHSELR SQ5 LL_ADC_REG_SetSequencerRanks\n
3037 * CHSELR SQ6 LL_ADC_REG_SetSequencerRanks\n
3038 * CHSELR SQ7 LL_ADC_REG_SetSequencerRanks\n
3039 * CHSELR SQ8 LL_ADC_REG_SetSequencerRanks
3040 * @param ADCx ADC instance
3041 * @param Rank This parameter can be one of the following values:
3042 * @arg @ref LL_ADC_REG_RANK_1
3043 * @arg @ref LL_ADC_REG_RANK_2
3044 * @arg @ref LL_ADC_REG_RANK_3
3045 * @arg @ref LL_ADC_REG_RANK_4
3046 * @arg @ref LL_ADC_REG_RANK_5
3047 * @arg @ref LL_ADC_REG_RANK_6
3048 * @arg @ref LL_ADC_REG_RANK_7
3049 * @arg @ref LL_ADC_REG_RANK_8
3050 * @param Channel This parameter can be one of the following values:
3051 * @arg @ref ADC_CHANNEL_0
3052 * @arg @ref ADC_CHANNEL_1
3053 * @arg @ref ADC_CHANNEL_2
3054 * @arg @ref ADC_CHANNEL_3
3055 * @arg @ref ADC_CHANNEL_4
3056 * @arg @ref ADC_CHANNEL_5
3057 * @arg @ref ADC_CHANNEL_6
3058 * @arg @ref ADC_CHANNEL_7
3059 * @arg @ref ADC_CHANNEL_8 (1)
3060 * @arg @ref ADC_CHANNEL_9 (1)
3061 * @arg @ref ADC_CHANNEL_10
3062 * @arg @ref ADC_CHANNEL_11
3063 * @arg @ref ADC_CHANNEL_12
3064 * @arg @ref ADC_CHANNEL_13
3065 * @arg @ref ADC_CHANNEL_14
3066 * @arg @ref ADC_CHANNEL_15 (1)
3067 * @arg @ref ADC_CHANNEL_16 (1)
3068 * @arg @ref ADC_CHANNEL_17 (3)
3069 * @arg @ref ADC_CHANNEL_18 (3)
3070 * @arg @ref ADC_CHANNEL_19 (3)
3071 * @arg @ref ADC_CHANNEL_20 (3)
3072 * @arg @ref ADC_CHANNEL_21 (3)
3073 * @arg @ref ADC_CHANNEL_22 (3)
3074 * @arg @ref ADC_CHANNEL_VREFINT (2)
3075 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3076 * @arg @ref ADC_CHANNEL_VDDA (2)
3077 * @arg @ref ADC_CHANNEL_VSSA (2)
3078 *
3079 * (1) On STM32C0, parameter can be set in ADC group sequencer
3080 * only if sequencer is set in mode "not fully configurable",
3081 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3082 * (2) For ADC channel read back from ADC register,
3083 * comparison with internal channel parameter to be done
3084 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3085 * (3) ADC channels available on STM32C031xx device only.
3086 * @retval None
3087 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3088 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3089 {
3090 /* Set bits with content of parameter "Channel" with bits position */
3091 /* in register depending on parameter "Rank". */
3092 /* Parameters "Rank" and "Channel" are used with masks because containing */
3093 /* other bits reserved for other purpose. */
3094 MODIFY_REG(ADCx->CHSELR,
3095 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3096 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3097 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3098 }
3099
3100 /**
3101 * @brief Get ADC group regular sequence: channel on the selected
3102 * scan sequence rank.
3103 * @note On this STM32 series, ADC group regular sequencer is
3104 * fully configurable: sequencer length and each rank
3105 * affectation to a channel are configurable.
3106 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3107 * @note Depending on devices and packages, some channels may not be available.
3108 * Refer to device datasheet for channels availability.
3109 * @note Usage of the returned channel number:
3110 * - To reinject this channel into another function LL_ADC_xxx:
3111 * the returned channel number is only partly formatted on definition
3112 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3113 * with parts of literals LL_ADC_CHANNEL_x or using
3114 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3115 * Then the selected literal LL_ADC_CHANNEL_x can be used
3116 * as parameter for another function.
3117 * - To get the channel number in decimal format:
3118 * process the returned value with the helper macro
3119 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3120 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerRanks\n
3121 * CHSELR SQ2 LL_ADC_REG_GetSequencerRanks\n
3122 * CHSELR SQ3 LL_ADC_REG_GetSequencerRanks\n
3123 * CHSELR SQ4 LL_ADC_REG_GetSequencerRanks\n
3124 * CHSELR SQ5 LL_ADC_REG_GetSequencerRanks\n
3125 * CHSELR SQ6 LL_ADC_REG_GetSequencerRanks\n
3126 * CHSELR SQ7 LL_ADC_REG_GetSequencerRanks\n
3127 * CHSELR SQ8 LL_ADC_REG_GetSequencerRanks
3128 * @param ADCx ADC instance
3129 * @param Rank This parameter can be one of the following values:
3130 * @arg @ref LL_ADC_REG_RANK_1
3131 * @arg @ref LL_ADC_REG_RANK_2
3132 * @arg @ref LL_ADC_REG_RANK_3
3133 * @arg @ref LL_ADC_REG_RANK_4
3134 * @arg @ref LL_ADC_REG_RANK_5
3135 * @arg @ref LL_ADC_REG_RANK_6
3136 * @arg @ref LL_ADC_REG_RANK_7
3137 * @arg @ref LL_ADC_REG_RANK_8
3138 * @retval Returned value can be one of the following values:
3139 * @arg @ref ADC_CHANNEL_0
3140 * @arg @ref ADC_CHANNEL_1
3141 * @arg @ref ADC_CHANNEL_2
3142 * @arg @ref ADC_CHANNEL_3
3143 * @arg @ref ADC_CHANNEL_4
3144 * @arg @ref ADC_CHANNEL_5
3145 * @arg @ref ADC_CHANNEL_6
3146 * @arg @ref ADC_CHANNEL_7
3147 * @arg @ref ADC_CHANNEL_8 (1)
3148 * @arg @ref ADC_CHANNEL_9 (1)
3149 * @arg @ref ADC_CHANNEL_10
3150 * @arg @ref ADC_CHANNEL_11
3151 * @arg @ref ADC_CHANNEL_12
3152 * @arg @ref ADC_CHANNEL_13
3153 * @arg @ref ADC_CHANNEL_14
3154 * @arg @ref ADC_CHANNEL_15 (1)
3155 * @arg @ref ADC_CHANNEL_16 (1)
3156 * @arg @ref ADC_CHANNEL_17 (3)
3157 * @arg @ref ADC_CHANNEL_18 (3)
3158 * @arg @ref ADC_CHANNEL_19 (3)
3159 * @arg @ref ADC_CHANNEL_20 (3)
3160 * @arg @ref ADC_CHANNEL_21 (3)
3161 * @arg @ref ADC_CHANNEL_22 (3)
3162 * @arg @ref ADC_CHANNEL_VREFINT (2)
3163 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3164 * @arg @ref ADC_CHANNEL_VDDA (2)
3165 * @arg @ref ADC_CHANNEL_VSSA (2)
3166 *
3167 * (1) On STM32C0, parameter can be set in ADC group sequencer
3168 * only if sequencer is set in mode "not fully configurable",
3169 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3170 * (2) For ADC channel read back from ADC register,
3171 * comparison with internal channel parameter to be done
3172 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3173 * (3) ADC channels available on STM32C031xx device only.
3174 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)3175 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3176 {
3177 return (uint32_t)((READ_BIT(ADCx->CHSELR,
3178 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
3179 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
3180 ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3181 );
3182 }
3183
3184 /**
3185 * @brief Set ADC group regular sequence: channel on rank corresponding to
3186 * channel number.
3187 * @note This function performs:
3188 * - Channels ordering into each rank of scan sequence:
3189 * rank of each channel is fixed by channel HW number
3190 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3191 * - Set channels selected by overwriting the current sequencer
3192 * configuration.
3193 * @note On this STM32 series, ADC group regular sequencer both modes
3194 * "fully configurable" or "not fully configurable"
3195 * are available, they can be chosen using
3196 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3197 * This function can be used with setting "not fully configurable".
3198 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3199 * and @ref LL_ADC_REG_SetSequencerLength().
3200 * @note On this STM32 series, after modifying sequencer (functions
3201 * @ref LL_ADC_REG_SetSequencerLength()
3202 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3203 * it is mandatory to wait for the assertion of CCRDY flag
3204 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3205 * Otherwise, some actions may be ignored.
3206 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3207 * for more details.
3208 * @note Depending on devices and packages, some channels may not be available.
3209 * Refer to device datasheet for channels availability.
3210 * @note On this STM32 series, to measure internal channels (VrefInt,
3211 * TempSensor, ...), measurement paths to internal channels must be
3212 * enabled separately.
3213 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3214 * @note On this STM32 series, setting of this feature is conditioned to
3215 * ADC state:
3216 * ADC must be disabled or enabled without conversion on going
3217 * on group regular.
3218 * @note One or several values can be selected.
3219 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3220 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
3221 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
3222 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
3223 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
3224 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
3225 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
3226 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
3227 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
3228 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
3229 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
3230 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
3231 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
3232 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
3233 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
3234 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
3235 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
3236 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
3237 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
3238 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
3239 * @param ADCx ADC instance
3240 * @param Channel This parameter can be a combination of the following values:
3241 * @arg @ref ADC_CHANNEL_0
3242 * @arg @ref ADC_CHANNEL_1
3243 * @arg @ref ADC_CHANNEL_2
3244 * @arg @ref ADC_CHANNEL_3
3245 * @arg @ref ADC_CHANNEL_4
3246 * @arg @ref ADC_CHANNEL_5
3247 * @arg @ref ADC_CHANNEL_6
3248 * @arg @ref ADC_CHANNEL_7
3249 * @arg @ref ADC_CHANNEL_8 (1)
3250 * @arg @ref ADC_CHANNEL_9 (1)
3251 * @arg @ref ADC_CHANNEL_10
3252 * @arg @ref ADC_CHANNEL_11
3253 * @arg @ref ADC_CHANNEL_12
3254 * @arg @ref ADC_CHANNEL_13
3255 * @arg @ref ADC_CHANNEL_14
3256 * @arg @ref ADC_CHANNEL_15 (1)
3257 * @arg @ref ADC_CHANNEL_16 (1)
3258 * @arg @ref ADC_CHANNEL_17 (3)
3259 * @arg @ref ADC_CHANNEL_18 (3)
3260 * @arg @ref ADC_CHANNEL_19 (3)
3261 * @arg @ref ADC_CHANNEL_20 (3)
3262 * @arg @ref ADC_CHANNEL_21 (3)
3263 * @arg @ref ADC_CHANNEL_22 (3)
3264 * @arg @ref ADC_CHANNEL_VREFINT (2)
3265 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3266 * @arg @ref ADC_CHANNEL_VDDA (2)
3267 * @arg @ref ADC_CHANNEL_VSSA (2)
3268 *
3269 * (1) On STM32C0, parameter can be set in ADC group sequencer
3270 * only if sequencer is set in mode "not fully configurable",
3271 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3272 * (2) For ADC channel read back from ADC register,
3273 * comparison with internal channel parameter to be done
3274 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3275 * (3) ADC channels available on STM32C031xx device only.
3276 * @retval None
3277 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)3278 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
3279 {
3280 /* Parameter "Channel" is used with masks because containing */
3281 /* other bits reserved for other purpose. */
3282 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3283 }
3284
3285 /**
3286 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
3287 * channel number.
3288 * @note This function performs:
3289 * - Channels ordering into each rank of scan sequence:
3290 * rank of each channel is fixed by channel HW number
3291 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3292 * - Set channels selected by adding them to the current sequencer
3293 * configuration.
3294 * @note On this STM32 series, ADC group regular sequencer both modes
3295 * "fully configurable" or "not fully configurable"
3296 * are available, they can be chosen using
3297 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3298 * This function can be used with setting "not fully configurable".
3299 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3300 * and @ref LL_ADC_REG_SetSequencerLength().
3301 * @note On this STM32 series, after modifying sequencer (functions
3302 * @ref LL_ADC_REG_SetSequencerLength()
3303 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3304 * it is mandatory to wait for the assertion of CCRDY flag
3305 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3306 * Otherwise, some actions may be ignored.
3307 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3308 * for more details.
3309 * @note Depending on devices and packages, some channels may not be available.
3310 * Refer to device datasheet for channels availability.
3311 * @note On this STM32 series, to measure internal channels (VrefInt,
3312 * TempSensor, ...), measurement paths to internal channels must be
3313 * enabled separately.
3314 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3315 * @note On this STM32 series, setting of this feature is conditioned to
3316 * ADC state:
3317 * ADC must be disabled or enabled without conversion on going
3318 * on group regular.
3319 * @note One or several values can be selected.
3320 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3321 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
3322 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
3323 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
3324 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
3325 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
3326 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
3327 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
3328 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
3329 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
3330 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
3331 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
3332 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
3333 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
3334 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
3335 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
3336 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
3337 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
3338 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
3339 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
3340 * @param ADCx ADC instance
3341 * @param Channel This parameter can be a combination of the following values:
3342 * @arg @ref ADC_CHANNEL_0
3343 * @arg @ref ADC_CHANNEL_1
3344 * @arg @ref ADC_CHANNEL_2
3345 * @arg @ref ADC_CHANNEL_3
3346 * @arg @ref ADC_CHANNEL_4
3347 * @arg @ref ADC_CHANNEL_5
3348 * @arg @ref ADC_CHANNEL_6
3349 * @arg @ref ADC_CHANNEL_7
3350 * @arg @ref ADC_CHANNEL_8 (1)
3351 * @arg @ref ADC_CHANNEL_9 (1)
3352 * @arg @ref ADC_CHANNEL_10
3353 * @arg @ref ADC_CHANNEL_11
3354 * @arg @ref ADC_CHANNEL_12
3355 * @arg @ref ADC_CHANNEL_13
3356 * @arg @ref ADC_CHANNEL_14
3357 * @arg @ref ADC_CHANNEL_15 (1)
3358 * @arg @ref ADC_CHANNEL_16 (1)
3359 * @arg @ref ADC_CHANNEL_17 (3)
3360 * @arg @ref ADC_CHANNEL_18 (3)
3361 * @arg @ref ADC_CHANNEL_19 (3)
3362 * @arg @ref ADC_CHANNEL_20 (3)
3363 * @arg @ref ADC_CHANNEL_21 (3)
3364 * @arg @ref ADC_CHANNEL_22 (3)
3365 * @arg @ref ADC_CHANNEL_VREFINT (2)
3366 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3367 * @arg @ref ADC_CHANNEL_VDDA (2)
3368 * @arg @ref ADC_CHANNEL_VSSA (2)
3369 *
3370 * (1) On STM32C0, parameter can be set in ADC group sequencer
3371 * only if sequencer is set in mode "not fully configurable",
3372 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3373 * (2) For ADC channel read back from ADC register,
3374 * comparison with internal channel parameter to be done
3375 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3376 * (3) ADC channels available on STM32C031xx device only.
3377 * @retval None
3378 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)3379 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
3380 {
3381 /* Parameter "Channel" is used with masks because containing */
3382 /* other bits reserved for other purpose. */
3383 SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3384 }
3385
3386 /**
3387 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
3388 * channel number.
3389 * @note This function performs:
3390 * - Channels ordering into each rank of scan sequence:
3391 * rank of each channel is fixed by channel HW number
3392 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3393 * - Set channels selected by removing them to the current sequencer
3394 * configuration.
3395 * @note On this STM32 series, ADC group regular sequencer both modes
3396 * "fully configurable" or "not fully configurable"
3397 * are available, they can be chosen using
3398 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3399 * This function can be used with setting "not fully configurable".
3400 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3401 * and @ref LL_ADC_REG_SetSequencerLength().
3402 * @note On this STM32 series, after modifying sequencer (functions
3403 * @ref LL_ADC_REG_SetSequencerLength()
3404 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3405 * it is mandatory to wait for the assertion of CCRDY flag
3406 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3407 * Otherwise, some actions may be ignored.
3408 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3409 * for more details.
3410 * @note Depending on devices and packages, some channels may not be available.
3411 * Refer to device datasheet for channels availability.
3412 * @note On this STM32 series, to measure internal channels (VrefInt,
3413 * TempSensor, ...), measurement paths to internal channels must be
3414 * enabled separately.
3415 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3416 * @note On this STM32 series, setting of this feature is conditioned to
3417 * ADC state:
3418 * ADC must be disabled or enabled without conversion on going
3419 * on group regular.
3420 * @note One or several values can be selected.
3421 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3422 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
3423 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
3424 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
3425 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
3426 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
3427 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
3428 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
3429 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
3430 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
3431 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
3432 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
3433 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
3434 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
3435 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
3436 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
3437 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
3438 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
3439 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
3440 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
3441 * @param ADCx ADC instance
3442 * @param Channel This parameter can be a combination of the following values:
3443 * @arg @ref ADC_CHANNEL_0
3444 * @arg @ref ADC_CHANNEL_1
3445 * @arg @ref ADC_CHANNEL_2
3446 * @arg @ref ADC_CHANNEL_3
3447 * @arg @ref ADC_CHANNEL_4
3448 * @arg @ref ADC_CHANNEL_5
3449 * @arg @ref ADC_CHANNEL_6
3450 * @arg @ref ADC_CHANNEL_7
3451 * @arg @ref ADC_CHANNEL_8 (1)
3452 * @arg @ref ADC_CHANNEL_9 (1)
3453 * @arg @ref ADC_CHANNEL_10
3454 * @arg @ref ADC_CHANNEL_11
3455 * @arg @ref ADC_CHANNEL_12
3456 * @arg @ref ADC_CHANNEL_13
3457 * @arg @ref ADC_CHANNEL_14
3458 * @arg @ref ADC_CHANNEL_15 (1)
3459 * @arg @ref ADC_CHANNEL_16 (1)
3460 * @arg @ref ADC_CHANNEL_17 (3)
3461 * @arg @ref ADC_CHANNEL_18 (3)
3462 * @arg @ref ADC_CHANNEL_19 (3)
3463 * @arg @ref ADC_CHANNEL_20 (3)
3464 * @arg @ref ADC_CHANNEL_21 (3)
3465 * @arg @ref ADC_CHANNEL_22 (3)
3466 * @arg @ref ADC_CHANNEL_VREFINT (2)
3467 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3468 * @arg @ref ADC_CHANNEL_VDDA (2)
3469 * @arg @ref ADC_CHANNEL_VSSA (2)
3470 *
3471 * (1) On STM32C0, parameter can be set in ADC group sequencer
3472 * only if sequencer is set in mode "not fully configurable",
3473 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3474 * (2) For ADC channel read back from ADC register,
3475 * comparison with internal channel parameter to be done
3476 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3477 * (3) ADC channels available on STM32C031xx device only.
3478 * @retval None
3479 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)3480 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
3481 {
3482 /* Parameter "Channel" is used with masks because containing */
3483 /* other bits reserved for other purpose. */
3484 CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3485 }
3486
3487 /**
3488 * @brief Get ADC group regular sequence: channel on rank corresponding to
3489 * channel number.
3490 * @note This function performs:
3491 * - Channels order reading into each rank of scan sequence:
3492 * rank of each channel is fixed by channel HW number
3493 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3494 * @note On this STM32 series, ADC group regular sequencer both modes
3495 * "fully configurable" or "not fully configurable"
3496 * are available, they can be chosen using
3497 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3498 * This function can be used with setting "not fully configurable".
3499 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3500 * and @ref LL_ADC_REG_SetSequencerLength().
3501 * @note Depending on devices and packages, some channels may not be available.
3502 * Refer to device datasheet for channels availability.
3503 * @note On this STM32 series, to measure internal channels (VrefInt,
3504 * TempSensor, ...), measurement paths to internal channels must be
3505 * enabled separately.
3506 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3507 * @note On this STM32 series, setting of this feature is conditioned to
3508 * ADC state:
3509 * ADC must be disabled or enabled without conversion on going
3510 * on group regular.
3511 * @note One or several values can be retrieved.
3512 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3513 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
3514 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
3515 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
3516 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
3517 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
3518 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
3519 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
3520 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
3521 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
3522 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
3523 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
3524 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
3525 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
3526 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
3527 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
3528 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
3529 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
3530 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
3531 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
3532 * @param ADCx ADC instance
3533 * @retval Returned value can be a combination of the following values:
3534 * @arg @ref ADC_CHANNEL_0
3535 * @arg @ref ADC_CHANNEL_1
3536 * @arg @ref ADC_CHANNEL_2
3537 * @arg @ref ADC_CHANNEL_3
3538 * @arg @ref ADC_CHANNEL_4
3539 * @arg @ref ADC_CHANNEL_5
3540 * @arg @ref ADC_CHANNEL_6
3541 * @arg @ref ADC_CHANNEL_7
3542 * @arg @ref ADC_CHANNEL_8 (1)
3543 * @arg @ref ADC_CHANNEL_9 (1)
3544 * @arg @ref ADC_CHANNEL_10
3545 * @arg @ref ADC_CHANNEL_11
3546 * @arg @ref ADC_CHANNEL_12
3547 * @arg @ref ADC_CHANNEL_13
3548 * @arg @ref ADC_CHANNEL_14
3549 * @arg @ref ADC_CHANNEL_15 (1)
3550 * @arg @ref ADC_CHANNEL_16 (1)
3551 * @arg @ref ADC_CHANNEL_17 (3)
3552 * @arg @ref ADC_CHANNEL_18 (3)
3553 * @arg @ref ADC_CHANNEL_19 (3)
3554 * @arg @ref ADC_CHANNEL_20 (3)
3555 * @arg @ref ADC_CHANNEL_21 (3)
3556 * @arg @ref ADC_CHANNEL_22 (3)
3557 * @arg @ref ADC_CHANNEL_VREFINT (2)
3558 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3559 * @arg @ref ADC_CHANNEL_VDDA (2)
3560 * @arg @ref ADC_CHANNEL_VSSA (2)
3561 *
3562 * (1) On STM32C0, parameter can be set in ADC group sequencer
3563 * only if sequencer is set in mode "not fully configurable",
3564 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3565 * (2) For ADC channel read back from ADC register,
3566 * comparison with internal channel parameter to be done
3567 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3568 * (3) ADC channels available on STM32C031xx device only.
3569 */
LL_ADC_REG_GetSequencerChannels(ADC_TypeDef * ADCx)3570 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
3571 {
3572 uint32_t ChannelsBitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
3573
3574 return ((((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
3575 | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
3576 | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
3577 | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
3578 | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
3579 | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
3580 | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
3581 | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
3582 | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
3583 | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
3584 | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
3585 | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
3586 | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
3587 | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
3588 | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
3589 | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
3590 | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
3591 | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
3592 | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
3593 | (((ChannelsBitfield & ADC_CHSELR_CHSEL19) >> ADC_CHSELR_CHSEL19_BITOFFSET_POS) * LL_ADC_CHANNEL_19)
3594 | (((ChannelsBitfield & ADC_CHSELR_CHSEL20) >> ADC_CHSELR_CHSEL20_BITOFFSET_POS) * LL_ADC_CHANNEL_20)
3595 | (((ChannelsBitfield & ADC_CHSELR_CHSEL21) >> ADC_CHSELR_CHSEL21_BITOFFSET_POS) * LL_ADC_CHANNEL_21)
3596 | (((ChannelsBitfield & ADC_CHSELR_CHSEL22) >> ADC_CHSELR_CHSEL22_BITOFFSET_POS) * LL_ADC_CHANNEL_22)
3597 );
3598 }
3599
3600 /**
3601 * @brief Set ADC continuous conversion mode on ADC group regular.
3602 * @note Description of ADC continuous conversion mode:
3603 * - single mode: one conversion per trigger
3604 * - continuous mode: after the first trigger, following
3605 * conversions launched successively automatically.
3606 * @note It is not possible to enable both ADC group regular
3607 * continuous mode and sequencer discontinuous mode.
3608 * @note On this STM32 series, setting of this feature is conditioned to
3609 * ADC state:
3610 * ADC must be disabled.
3611 * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
3612 * @param ADCx ADC instance
3613 * @param Continuous This parameter can be one of the following values:
3614 * @arg @ref LL_ADC_REG_CONV_SINGLE
3615 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3616 * @retval None
3617 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3618 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3619 {
3620 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
3621 }
3622
3623 /**
3624 * @brief Get ADC continuous conversion mode on ADC group regular.
3625 * @note Description of ADC continuous conversion mode:
3626 * - single mode: one conversion per trigger
3627 * - continuous mode: after the first trigger, following
3628 * conversions launched successively automatically.
3629 * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
3630 * @param ADCx ADC instance
3631 * @retval Returned value can be one of the following values:
3632 * @arg @ref LL_ADC_REG_CONV_SINGLE
3633 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3634 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)3635 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
3636 {
3637 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
3638 }
3639
3640 /**
3641 * @brief Set ADC group regular conversion data transfer: no transfer or
3642 * transfer by DMA, and DMA requests mode.
3643 * @note If transfer by DMA selected, specifies the DMA requests
3644 * mode:
3645 * - Limited mode (One shot mode): DMA transfer requests are stopped
3646 * when number of DMA data transfers (number of
3647 * ADC conversions) is reached.
3648 * This ADC mode is intended to be used with DMA mode non-circular.
3649 * - Unlimited mode: DMA transfer requests are unlimited,
3650 * whatever number of DMA data transfers (number of
3651 * ADC conversions).
3652 * This ADC mode is intended to be used with DMA mode circular.
3653 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3654 * mode non-circular:
3655 * when DMA transfers size will be reached, DMA will stop transfers of
3656 * ADC conversions data ADC will raise an overrun error
3657 * (overrun flag and interruption if enabled).
3658 * @note To configure DMA source address (peripheral address),
3659 * use function @ref LL_ADC_DMA_GetRegAddr().
3660 * @note On this STM32 series, setting of this feature is conditioned to
3661 * ADC state:
3662 * ADC must be disabled.
3663 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
3664 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
3665 * @param ADCx ADC instance
3666 * @param DMATransfer This parameter can be one of the following values:
3667 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3668 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3669 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3670 * @retval None
3671 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)3672 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3673 {
3674 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
3675 }
3676
3677 /**
3678 * @brief Get ADC group regular conversion data transfer: no transfer or
3679 * transfer by DMA, and DMA requests mode.
3680 * @note If transfer by DMA selected, specifies the DMA requests
3681 * mode:
3682 * - Limited mode (One shot mode): DMA transfer requests are stopped
3683 * when number of DMA data transfers (number of
3684 * ADC conversions) is reached.
3685 * This ADC mode is intended to be used with DMA mode non-circular.
3686 * - Unlimited mode: DMA transfer requests are unlimited,
3687 * whatever number of DMA data transfers (number of
3688 * ADC conversions).
3689 * This ADC mode is intended to be used with DMA mode circular.
3690 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3691 * mode non-circular:
3692 * when DMA transfers size will be reached, DMA will stop transfers of
3693 * ADC conversions data ADC will raise an overrun error
3694 * (overrun flag and interruption if enabled).
3695 * @note To configure DMA source address (peripheral address),
3696 * use function @ref LL_ADC_DMA_GetRegAddr().
3697 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
3698 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
3699 * @param ADCx ADC instance
3700 * @retval Returned value can be one of the following values:
3701 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3702 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3703 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3704 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)3705 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
3706 {
3707 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
3708 }
3709
3710 /**
3711 * @brief Set ADC group regular behavior in case of overrun:
3712 * data preserved or overwritten.
3713 * @note Compatibility with devices without feature overrun:
3714 * other devices without this feature have a behavior
3715 * equivalent to data overwritten.
3716 * The default setting of overrun is data preserved.
3717 * Therefore, for compatibility with all devices, parameter
3718 * overrun should be set to data overwritten.
3719 * @note On this STM32 series, setting of this feature is conditioned to
3720 * ADC state:
3721 * ADC must be disabled.
3722 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
3723 * @param ADCx ADC instance
3724 * @param Overrun This parameter can be one of the following values:
3725 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3726 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3727 * @retval None
3728 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3729 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3730 {
3731 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
3732 }
3733
3734 /**
3735 * @brief Get ADC group regular behavior in case of overrun:
3736 * data preserved or overwritten.
3737 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
3738 * @param ADCx ADC instance
3739 * @retval Returned value can be one of the following values:
3740 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3741 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3742 */
LL_ADC_REG_GetOverrun(ADC_TypeDef * ADCx)3743 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
3744 {
3745 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
3746 }
3747
3748 /**
3749 * @}
3750 */
3751
3752 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3753 * @{
3754 */
3755
3756 /**
3757 * @brief Set sampling time of the selected ADC channel
3758 * Unit: ADC clock cycles.
3759 * @note On this device, sampling time is on channel scope: independently
3760 * of channel mapped on ADC group regular or injected.
3761 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3762 * converted:
3763 * sampling time constraints must be respected (sampling time can be
3764 * adjusted in function of ADC clock frequency and sampling time
3765 * setting).
3766 * Refer to device datasheet for timings values (parameters TS_vrefint,
3767 * TS_temp, ...).
3768 * @note Conversion time is the addition of sampling time and processing time.
3769 * Refer to reference manual for ADC processing time of
3770 * this STM32 series.
3771 * @note In case of ADC conversion of internal channel (VrefInt,
3772 * temperature sensor, ...), a sampling time minimum value
3773 * is required.
3774 * Refer to device datasheet.
3775 * @note On this STM32 series, setting of this feature is conditioned to
3776 * ADC state:
3777 * ADC must be disabled or enabled without conversion on going
3778 * on group regular.
3779 * @rmtoll SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime\n
3780 * SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime\n
3781 * SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime\n
3782 * SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime\n
3783 * SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime\n
3784 * SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime\n
3785 * SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime\n
3786 * SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime\n
3787 * SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime\n
3788 * SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime\n
3789 * SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime\n
3790 * SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime\n
3791 * SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime\n
3792 * SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime\n
3793 * SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime\n
3794 * SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime\n
3795 * SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime\n
3796 * SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime\n
3797 * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime
3798 * @param ADCx ADC instance
3799 * @param Channel This parameter can be a combination of the following values:
3800 * @arg @ref ADC_CHANNEL_0
3801 * @arg @ref ADC_CHANNEL_1
3802 * @arg @ref ADC_CHANNEL_2
3803 * @arg @ref ADC_CHANNEL_3
3804 * @arg @ref ADC_CHANNEL_4
3805 * @arg @ref ADC_CHANNEL_5
3806 * @arg @ref ADC_CHANNEL_6
3807 * @arg @ref ADC_CHANNEL_7
3808 * @arg @ref ADC_CHANNEL_8 (1)
3809 * @arg @ref ADC_CHANNEL_9 (1)
3810 * @arg @ref ADC_CHANNEL_10
3811 * @arg @ref ADC_CHANNEL_11
3812 * @arg @ref ADC_CHANNEL_12
3813 * @arg @ref ADC_CHANNEL_13
3814 * @arg @ref ADC_CHANNEL_14
3815 * @arg @ref ADC_CHANNEL_15 (1)
3816 * @arg @ref ADC_CHANNEL_16 (1)
3817 * @arg @ref ADC_CHANNEL_17 (3)
3818 * @arg @ref ADC_CHANNEL_18 (3)
3819 * @arg @ref ADC_CHANNEL_19 (3)
3820 * @arg @ref ADC_CHANNEL_20 (3)
3821 * @arg @ref ADC_CHANNEL_21 (3)
3822 * @arg @ref ADC_CHANNEL_22 (3)
3823 * @arg @ref ADC_CHANNEL_VREFINT (2)
3824 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3825 * @arg @ref ADC_CHANNEL_VDDA (2)
3826 * @arg @ref ADC_CHANNEL_VSSA (2)
3827 *
3828 * (1) On STM32C0, parameter can be set in ADC group sequencer
3829 * only if sequencer is set in mode "not fully configurable",
3830 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3831 * (2) For ADC channel read back from ADC register,
3832 * comparison with internal channel parameter to be done
3833 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3834 * (3) ADC channels available on STM32C031xx device only.
3835 * @param SamplingTimeY This parameter can be one of the following values:
3836 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3837 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3838 * @retval None
3839 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTimeY)3840 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
3841 {
3842 /* Parameter "Channel" is used with masks because containing */
3843 /* other bits reserved for other purpose. */
3844 MODIFY_REG(ADCx->SMPR,
3845 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
3846 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
3847 );
3848 }
3849
3850 /**
3851 * @brief Get sampling time of the selected ADC channel
3852 * Unit: ADC clock cycles.
3853 * @note On this device, sampling time is on channel scope: independently
3854 * of channel mapped on ADC group regular or injected.
3855 * @note Conversion time is the addition of sampling time and processing time.
3856 * Refer to reference manual for ADC processing time of
3857 * this STM32 series.
3858 * @rmtoll SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime\n
3859 * SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime\n
3860 * SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime\n
3861 * SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime\n
3862 * SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime\n
3863 * SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime\n
3864 * SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime\n
3865 * SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime\n
3866 * SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime\n
3867 * SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime\n
3868 * SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime\n
3869 * SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime\n
3870 * SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime\n
3871 * SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime\n
3872 * SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime\n
3873 * SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime\n
3874 * SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime\n
3875 * SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime\n
3876 * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime
3877 * @param ADCx ADC instance
3878 * @param Channel This parameter can be one of the following values:
3879 * @arg @ref ADC_CHANNEL_0
3880 * @arg @ref ADC_CHANNEL_1
3881 * @arg @ref ADC_CHANNEL_2
3882 * @arg @ref ADC_CHANNEL_3
3883 * @arg @ref ADC_CHANNEL_4
3884 * @arg @ref ADC_CHANNEL_5
3885 * @arg @ref ADC_CHANNEL_6
3886 * @arg @ref ADC_CHANNEL_7
3887 * @arg @ref ADC_CHANNEL_8 (1)
3888 * @arg @ref ADC_CHANNEL_9 (1)
3889 * @arg @ref ADC_CHANNEL_10
3890 * @arg @ref ADC_CHANNEL_11
3891 * @arg @ref ADC_CHANNEL_12
3892 * @arg @ref ADC_CHANNEL_13
3893 * @arg @ref ADC_CHANNEL_14
3894 * @arg @ref ADC_CHANNEL_15 (1)
3895 * @arg @ref ADC_CHANNEL_16 (1)
3896 * @arg @ref ADC_CHANNEL_17 (3)
3897 * @arg @ref ADC_CHANNEL_18 (3)
3898 * @arg @ref ADC_CHANNEL_19 (3)
3899 * @arg @ref ADC_CHANNEL_20 (3)
3900 * @arg @ref ADC_CHANNEL_21 (3)
3901 * @arg @ref ADC_CHANNEL_22 (3)
3902 * @arg @ref ADC_CHANNEL_VREFINT (2)
3903 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3904 * @arg @ref ADC_CHANNEL_VDDA (2)
3905 * @arg @ref ADC_CHANNEL_VSSA (2)
3906 *
3907 * (1) On STM32C0, parameter can be set in ADC group sequencer
3908 * only if sequencer is set in mode "not fully configurable",
3909 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3910 * (2) For ADC channel read back from ADC register,
3911 * comparison with internal channel parameter to be done
3912 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3913 * (3) ADC channels available on STM32C031xx device only.
3914 * @retval Returned value can be one of the following values:
3915 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3916 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3917 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)3918 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
3919 {
3920 __IO uint32_t smpr = READ_REG(ADCx->SMPR);
3921
3922 /* Retrieve sampling time bit corresponding to the selected channel */
3923 /* and shift it to position 0. */
3924 uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
3925 >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3926 + ADC_SMPR_SMPSEL0_BITOFFSET_POS)
3927 & 0x1FUL));
3928
3929 /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
3930 return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
3931 | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
3932 }
3933
3934 /**
3935 * @}
3936 */
3937
3938 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3939 * @{
3940 */
3941
3942 /**
3943 * @brief Set ADC analog watchdog monitored channels:
3944 * a single channel or all channels,
3945 * on ADC group regular.
3946 * @note Once monitored channels are selected, analog watchdog
3947 * is enabled.
3948 * @note In case of need to define a single channel to monitor
3949 * with analog watchdog from sequencer channel definition,
3950 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3951 * @note On this STM32 series, there is only 1 kind of analog watchdog
3952 * instance:
3953 * - AWD standard (instance AWD1):
3954 * - channels monitored: can monitor 1 channel or all channels.
3955 * - groups monitored: ADC group regular.
3956 * - resolution: resolution is not limited (corresponds to
3957 * ADC resolution configured).
3958 * @note On this STM32 series, setting of this feature is conditioned to
3959 * ADC state:
3960 * ADC must be disabled.
3961 * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3962 * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3963 * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
3964 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
3965 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
3966 * @param ADCx ADC instance
3967 * @param AWDy This parameter can be one of the following values:
3968 * @arg @ref LL_ADC_AWD1
3969 * @arg @ref LL_ADC_AWD2
3970 * @arg @ref LL_ADC_AWD3
3971 * @param AWDChannelGroup This parameter can be one of the following values:
3972 * @arg @ref LL_ADC_AWD_DISABLE
3973 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3974 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3975 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3976 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3977 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3978 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3979 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3980 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3981 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3982 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3983 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3984 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3985 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3986 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3987 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3988 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3989 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3990 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3991 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3992 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
3993 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1)
3994 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1)
3995 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1)
3996 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
3997 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
3998 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
3999 * @arg @ref LL_ADC_AWD_CH_VDDA_REG
4000 * @arg @ref LL_ADC_AWD_CH_VSSA_REG
4001 * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx.
4002 * @retval None
4003 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)4004 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
4005 {
4006 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
4007 /* in register and register position depending on parameter "AWDy". */
4008 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
4009 /* containing other bits reserved for other purpose. */
4010 register __IO uint32_t *preg;
4011
4012 if (AWDy == LL_ADC_AWD1)
4013 {
4014 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
4015 }
4016 else
4017 {
4018 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR,
4019 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
4020 }
4021
4022 MODIFY_REG(*preg,
4023 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
4024 AWDChannelGroup & AWDy);
4025 }
4026
4027 /**
4028 * @brief Get ADC analog watchdog monitored channel.
4029 * @note Usage of the returned channel number:
4030 * - To reinject this channel into another function LL_ADC_xxx:
4031 * the returned channel number is only partly formatted on definition
4032 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4033 * with parts of literals LL_ADC_CHANNEL_x or using
4034 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4035 * Then the selected literal LL_ADC_CHANNEL_x can be used
4036 * as parameter for another function.
4037 * - To get the channel number in decimal format:
4038 * process the returned value with the helper macro
4039 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4040 * Applicable only when the analog watchdog is set to monitor
4041 * one channel.
4042 * @note On this STM32 series, there is only 1 kind of analog watchdog
4043 * instance:
4044 * - AWD standard (instance AWD1):
4045 * - channels monitored: can monitor 1 channel or all channels.
4046 * - groups monitored: ADC group regular.
4047 * - resolution: resolution is not limited (corresponds to
4048 * ADC resolution configured).
4049 * - AWD flexible (instances AWD2, AWD3):
4050 * - channels monitored: flexible on channels monitored, selection is
4051 * channel wise, from from 1 to all channels.
4052 * Specificity of this analog watchdog: Multiple channels can
4053 * be selected. For example:
4054 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4055 * - groups monitored: not selection possible (monitoring on both
4056 * groups regular and injected).
4057 * Channels selected are monitored on groups regular and injected:
4058 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4059 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4060 * - resolution: resolution is not limited (corresponds to
4061 * ADC resolution configured).
4062 * @note On this STM32 series, setting of this feature is conditioned to
4063 * ADC state:
4064 * ADC must be disabled or enabled without conversion on going
4065 * on group regular.
4066 * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
4067 * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
4068 * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
4069 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
4070 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
4071 * @param ADCx ADC instance
4072 * @param AWDy This parameter can be one of the following values:
4073 * @arg @ref LL_ADC_AWD1
4074 * @arg @ref LL_ADC_AWD2 (1)
4075 * @arg @ref LL_ADC_AWD3 (1)
4076 *
4077 * (1) On this AWD number, monitored channel can be retrieved
4078 * if only 1 channel is programmed (or none or all channels).
4079 * This function cannot retrieve monitored channel if
4080 * multiple channels are programmed simultaneously
4081 * by bitfield.
4082 * @retval Returned value can be one of the following values:
4083 * @arg @ref LL_ADC_AWD_DISABLE
4084 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
4085 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
4086 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
4087 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
4088 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
4089 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
4090 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
4091 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
4092 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
4093 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
4094 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
4095 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
4096 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
4097 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
4098 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
4099 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
4100 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
4101 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
4102 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
4103 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
4104 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1)
4105 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1)
4106 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1)
4107 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
4108 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
4109 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
4110 * @arg @ref LL_ADC_AWD_CH_VDDA_REG
4111 * @arg @ref LL_ADC_AWD_CH_VSSA_REG
4112 * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx.
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy)4113 */__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
4114 {
4115 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,
4116 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
4117 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
4118 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
4119
4120 register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
4121
4122 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
4123 /* (parameter value LL_ADC_AWD_DISABLE). */
4124 /* Else, the selected AWD is enabled and is monitoring a group of channels */
4125 /* or a single channel. */
4126 if (AnalogWDMonitChannels != 0UL)
4127 {
4128 if (AWDy == LL_ADC_AWD1)
4129 {
4130 if ((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL)
4131 {
4132 /* AWD monitoring a group of channels */
4133 AnalogWDMonitChannels = ((AnalogWDMonitChannels
4134 | (ADC_AWD_CR23_CHANNEL_MASK)
4135 )
4136 & (~(ADC_CFGR1_AWD1CH))
4137 );
4138 }
4139 else
4140 {
4141 /* AWD monitoring a single channel */
4142 AnalogWDMonitChannels = (AnalogWDMonitChannels
4143 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos))
4144 );
4145 }
4146 }
4147 else
4148 {
4149 if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
4150 {
4151 /* AWD monitoring a group of channels */
4152 AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
4153 | (ADC_CFGR1_AWD1EN)
4154 );
4155 }
4156 else
4157 {
4158 /* AWD monitoring a single channel */
4159 /* AWD monitoring a group of channels */
4160 AnalogWDMonitChannels = (AnalogWDMonitChannels
4161 | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
4162 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR1_AWD1CH_Pos)
4163 );
4164 }
4165 }
4166 }
4167
4168 return AnalogWDMonitChannels;
4169 }
4170 /**
4171 * @brief Set ADC analog watchdog thresholds value of both thresholds
4172 * high and low.
4173 * @note If value of only one threshold high or low must be set,
4174 * use function @ref LL_ADC_SetAnalogWDThresholds().
4175 * @note In case of ADC resolution different of 12 bits,
4176 * analog watchdog thresholds data require a specific shift.
4177 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
4178 * @note On this STM32 series, there is only 2 kind of analog watchdog
4179 * instance:
4180 * - AWD standard (instance AWD1):
4181 * - channels monitored: can monitor 1 channel or all channels.
4182 * - groups monitored: ADC group regular.
4183 * - resolution: resolution is not limited (corresponds to
4184 * ADC resolution configured).
4185 * - AWD flexible (instances AWD2, AWD3):
4186 * - channels monitored: flexible on channels monitored, selection is
4187 * channel wise, from from 1 to all channels.
4188 * Specificity of this analog watchdog: Multiple channels can
4189 * be selected. For example:
4190 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4191 * - groups monitored: not selection possible (monitoring on both
4192 * groups regular and injected).
4193 * Channels selected are monitored on groups regular and injected:
4194 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4195 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4196 * - resolution: resolution is not limited (corresponds to
4197 * ADC resolution configured).
4198 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
4199 * impacted: the comparison of analog watchdog thresholds is done on
4200 * oversampling final computation (after ratio and shift application):
4201 * ADC data register bitfield [15:4] (12 most significant bits).
4202 * Examples:
4203 * - Oversampling ratio and shift selected to have ADC conversion data
4204 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
4205 * ADC analog watchdog thresholds must be divided by 16.
4206 * - Oversampling ratio and shift selected to have ADC conversion data
4207 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
4208 * ADC analog watchdog thresholds must be divided by 4.
4209 * - Oversampling ratio and shift selected to have ADC conversion data
4210 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
4211 * ADC analog watchdog thresholds match directly to ADC data register.
4212 * @note On this STM32 series, setting of this feature is conditioned to
4213 * ADC state:
4214 * ADC must be disabled or enabled without conversion on going
4215 * on group regular.
4216 * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n
4217 * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n
4218 * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n
4219 * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n
4220 * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n
4221 * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds
4222 * @param ADCx ADC instance
4223 * @param AWDy This parameter can be one of the following values:
4224 * @arg @ref LL_ADC_AWD1
4225 * @arg @ref LL_ADC_AWD2
4226 * @arg @ref LL_ADC_AWD3
4227 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
4228 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
4229 * @retval None
4230 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)4231 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
4232 uint32_t AWDThresholdLowValue)
4233 {
4234 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
4235 /* position in register and register position depending on parameter */
4236 /* "AWDy". */
4237 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
4238 /* containing other bits reserved for other purpose. */
4239 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
4240 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
4241 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
4242 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
4243 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))
4244 );
4245
4246 MODIFY_REG(*preg,
4247 ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
4248 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
4249 }
4250 /**
4251 * @brief Set ADC analog watchdog threshold value of threshold
4252 * high or low.
4253 * @note If values of both thresholds high or low must be set,
4254 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
4255 * @note In case of ADC resolution different of 12 bits,
4256 * analog watchdog thresholds data require a specific shift.
4257 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
4258 * @note On this STM32 series, there is only 2 kinds of analog watchdog
4259 * instance:
4260 * - AWD standard (instance AWD1):
4261 * - channels monitored: can monitor 1 channel or all channels.
4262 * - groups monitored: ADC group regular.
4263 * - resolution: resolution is not limited (corresponds to
4264 * ADC resolution configured).
4265 * - AWD flexible (instances AWD2, AWD3):
4266 * - channels monitored: flexible on channels monitored, selection is
4267 * channel wise, from from 1 to all channels.
4268 * Specificity of this analog watchdog: Multiple channels can
4269 * be selected. For example:
4270 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4271 * - groups monitored: not selection possible (monitoring on both
4272 * groups regular and injected).
4273 * Channels selected are monitored on groups regular and injected:
4274 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4275 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4276 * - resolution: resolution is not limited (corresponds to
4277 * ADC resolution configured).
4278 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
4279 * impacted: the comparison of analog watchdog thresholds is done on
4280 * oversampling final computation (after ratio and shift application):
4281 * ADC data register bitfield [15:4] (12 most significant bits).
4282 * Examples:
4283 * - Oversampling ratio and shift selected to have ADC conversion data
4284 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
4285 * ADC analog watchdog thresholds must be divided by 16.
4286 * - Oversampling ratio and shift selected to have ADC conversion data
4287 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
4288 * ADC analog watchdog thresholds must be divided by 4.
4289 * - Oversampling ratio and shift selected to have ADC conversion data
4290 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
4291 * ADC analog watchdog thresholds match directly to ADC data register.
4292 * @note On this STM32 series, setting of this feature is not conditioned to
4293 * ADC state:
4294 * ADC can be disabled, enabled with or without conversion on going
4295 * on ADC group regular.
4296 * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n
4297 * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n
4298 * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n
4299 * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n
4300 * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n
4301 * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds
4302 * @param ADCx ADC instance
4303 * @param AWDy This parameter can be one of the following values:
4304 * @arg @ref LL_ADC_AWD1
4305 * @arg @ref LL_ADC_AWD2
4306 * @arg @ref LL_ADC_AWD3
4307 * @param AWDThresholdsHighLow This parameter can be one of the following values:
4308 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
4309 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
4310 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
4311 * @retval None
4312 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)4313 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
4314 uint32_t AWDThresholdValue)
4315 {
4316 /* Set bits with content of parameter "AWDThresholdValue" with bits */
4317 /* position in register and register position depending on parameters */
4318 /* "AWDThresholdsHighLow" and "AWDy". */
4319 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
4320 /* containing other bits reserved for other purpose. */
4321 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
4322 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
4323 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
4324 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
4325 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
4326
4327 MODIFY_REG(*preg,
4328 AWDThresholdsHighLow,
4329 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
4330 }
4331
4332 /**
4333 * @brief Get ADC analog watchdog threshold value of threshold high,
4334 * threshold low or raw data with ADC thresholds high and low
4335 * concatenated.
4336 * @note If raw data with ADC thresholds high and low is retrieved,
4337 * the data of each threshold high or low can be isolated
4338 * using helper macro:
4339 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
4340 * @note In case of ADC resolution different of 12 bits,
4341 * analog watchdog thresholds data require a specific shift.
4342 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
4343 * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n
4344 * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n
4345 * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n
4346 * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n
4347 * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n
4348 * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds
4349 * @param ADCx ADC instance
4350 * @param AWDy This parameter can be one of the following values:
4351 * @arg @ref LL_ADC_AWD1
4352 * @arg @ref LL_ADC_AWD2
4353 * @arg @ref LL_ADC_AWD3
4354 * @param AWDThresholdsHighLow This parameter can be one of the following values:
4355 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
4356 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
4357 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
4358 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4359 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)4360 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
4361 {
4362 /* Set bits with content of parameter "AWDThresholdValue" with bits */
4363 /* position in register and register position depending on parameters */
4364 /* "AWDThresholdsHighLow" and "AWDy". */
4365 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
4366 /* containing other bits reserved for other purpose. */
4367 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
4368 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
4369 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
4370 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
4371 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
4372
4373 return (uint32_t)(READ_BIT(*preg,
4374 (AWDThresholdsHighLow | ADC_AWD1TR_LT1))
4375 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~
4376 (AWDThresholdsHighLow & ADC_AWD1TR_LT1))
4377 );
4378 }
4379
4380 /**
4381 * @}
4382 */
4383
4384 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
4385 * @{
4386 */
4387
4388 /**
4389 * @brief Set ADC oversampling scope.
4390 * @note On this STM32 series, setting of this feature is conditioned to
4391 * ADC state:
4392 * ADC must be disabled.
4393 * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope
4394 * @param ADCx ADC instance
4395 * @param OvsScope This parameter can be one of the following values:
4396 * @arg @ref LL_ADC_OVS_DISABLE
4397 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
4398 * @retval None
4399 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)4400 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
4401 {
4402 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
4403 }
4404
4405 /**
4406 * @brief Get ADC oversampling scope.
4407 * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope
4408 * @param ADCx ADC instance
4409 * @retval Returned value can be one of the following values:
4410 * @arg @ref LL_ADC_OVS_DISABLE
4411 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
4412 */
LL_ADC_GetOverSamplingScope(ADC_TypeDef * ADCx)4413 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
4414 {
4415 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
4416 }
4417
4418 /**
4419 * @brief Set ADC oversampling discontinuous mode (triggered mode)
4420 * on the selected ADC group.
4421 * @note Number of oversampled conversions are done either in:
4422 * - continuous mode (all conversions of oversampling ratio
4423 * are done from 1 trigger)
4424 * - discontinuous mode (each conversion of oversampling ratio
4425 * needs a trigger)
4426 * @note On this STM32 series, setting of this feature is conditioned to
4427 * ADC state:
4428 * ADC must be disabled.
4429 * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont
4430 * @param ADCx ADC instance
4431 * @param OverSamplingDiscont This parameter can be one of the following values:
4432 * @arg @ref LL_ADC_OVS_REG_CONT
4433 * @arg @ref LL_ADC_OVS_REG_DISCONT
4434 * @retval None
4435 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)4436 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
4437 {
4438 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
4439 }
4440
4441 /**
4442 * @brief Get ADC oversampling discontinuous mode (triggered mode)
4443 * on the selected ADC group.
4444 * @note Number of oversampled conversions are done either in:
4445 * - continuous mode (all conversions of oversampling ratio
4446 * are done from 1 trigger)
4447 * - discontinuous mode (each conversion of oversampling ratio
4448 * needs a trigger)
4449 * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont
4450 * @param ADCx ADC instance
4451 * @retval Returned value can be one of the following values:
4452 * @arg @ref LL_ADC_OVS_REG_CONT
4453 * @arg @ref LL_ADC_OVS_REG_DISCONT
4454 */
LL_ADC_GetOverSamplingDiscont(ADC_TypeDef * ADCx)4455 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
4456 {
4457 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
4458 }
4459
4460 /**
4461 * @brief Set ADC oversampling
4462 * @note This function set the 2 items of oversampling configuration:
4463 * - ratio
4464 * - shift
4465 * @note On this STM32 series, setting of this feature is conditioned to
4466 * ADC state:
4467 * ADC must be disabled.
4468 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
4469 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
4470 * @param ADCx ADC instance
4471 * @param Ratio This parameter can be one of the following values:
4472 * @arg @ref LL_ADC_OVS_RATIO_2
4473 * @arg @ref LL_ADC_OVS_RATIO_4
4474 * @arg @ref LL_ADC_OVS_RATIO_8
4475 * @arg @ref LL_ADC_OVS_RATIO_16
4476 * @arg @ref LL_ADC_OVS_RATIO_32
4477 * @arg @ref LL_ADC_OVS_RATIO_64
4478 * @arg @ref LL_ADC_OVS_RATIO_128
4479 * @arg @ref LL_ADC_OVS_RATIO_256
4480 * @param Shift This parameter can be one of the following values:
4481 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4482 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4483 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4484 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4485 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4486 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4487 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4488 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4489 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4490 * @retval None
4491 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)4492 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
4493 {
4494 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
4495 }
4496
4497 /**
4498 * @brief Get ADC oversampling ratio
4499 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
4500 * @param ADCx ADC instance
4501 * @retval Ratio This parameter can be one of the following values:
4502 * @arg @ref LL_ADC_OVS_RATIO_2
4503 * @arg @ref LL_ADC_OVS_RATIO_4
4504 * @arg @ref LL_ADC_OVS_RATIO_8
4505 * @arg @ref LL_ADC_OVS_RATIO_16
4506 * @arg @ref LL_ADC_OVS_RATIO_32
4507 * @arg @ref LL_ADC_OVS_RATIO_64
4508 * @arg @ref LL_ADC_OVS_RATIO_128
4509 * @arg @ref LL_ADC_OVS_RATIO_256
4510 */
LL_ADC_GetOverSamplingRatio(ADC_TypeDef * ADCx)4511 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
4512 {
4513 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
4514 }
4515
4516 /**
4517 * @brief Get ADC oversampling shift
4518 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
4519 * @param ADCx ADC instance
4520 * @retval Shift This parameter can be one of the following values:
4521 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4522 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4523 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4524 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4525 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4526 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4527 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4528 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4529 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4530 */
LL_ADC_GetOverSamplingShift(ADC_TypeDef * ADCx)4531 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
4532 {
4533 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
4534 }
4535
4536 /**
4537 * @}
4538 */
4539
4540 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
4541 * @{
4542 */
4543
4544 /**
4545 * @brief Enable ADC instance internal voltage regulator.
4546 * @note On this STM32 series, there are three possibilities to enable
4547 * the voltage regulator:
4548 * - by enabling it manually
4549 * using function @ref LL_ADC_EnableInternalRegulator().
4550 * - by launching a calibration
4551 * using function @ref LL_ADC_StartCalibration().
4552 * - by enabling the ADC
4553 * using function @ref LL_ADC_Enable().
4554 * @note On this STM32 series, after ADC internal voltage regulator enable,
4555 * a delay for ADC internal voltage regulator stabilization
4556 * is required before performing a ADC calibration or ADC enable.
4557 * Refer to device datasheet, parameter "tADCVREG_STUP".
4558 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
4559 * @note On this STM32 series, setting of this feature is conditioned to
4560 * ADC state:
4561 * ADC must be ADC disabled.
4562 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
4563 * @param ADCx ADC instance
4564 * @retval None
4565 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)4566 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
4567 {
4568 /* Note: Write register with some additional bits forced to state reset */
4569 /* instead of modifying only the selected bit for this function, */
4570 /* to not interfere with bits with HW property "rs". */
4571 MODIFY_REG(ADCx->CR,
4572 ADC_CR_BITS_PROPERTY_RS,
4573 ADC_CR_ADVREGEN);
4574 }
4575
4576 /**
4577 * @brief Disable ADC internal voltage regulator.
4578 * @note On this STM32 series, setting of this feature is conditioned to
4579 * ADC state:
4580 * ADC must be ADC disabled.
4581 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
4582 * @param ADCx ADC instance
4583 * @retval None
4584 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)4585 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
4586 {
4587 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
4588 }
4589
4590 /**
4591 * @brief Get the selected ADC instance internal voltage regulator state.
4592 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
4593 * @param ADCx ADC instance
4594 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
4595 */
LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef * ADCx)4596 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
4597 {
4598 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
4599 }
4600
4601 /**
4602 * @brief Enable the selected ADC instance.
4603 * @note On this STM32 series, after ADC enable, a delay for
4604 * ADC internal analog stabilization is required before performing a
4605 * ADC conversion start.
4606 * Refer to device datasheet, parameter tSTAB.
4607 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4608 * is enabled and when conversion clock is active.
4609 * (not only core clock: this ADC has a dual clock domain)
4610 * @note On this STM32 series, setting of this feature is conditioned to
4611 * ADC state:
4612 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
4613 * @rmtoll CR ADEN LL_ADC_Enable
4614 * @param ADCx ADC instance
4615 * @retval None
4616 */
LL_ADC_Enable(ADC_TypeDef * ADCx)4617 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
4618 {
4619 /* Note: Write register with some additional bits forced to state reset */
4620 /* instead of modifying only the selected bit for this function, */
4621 /* to not interfere with bits with HW property "rs". */
4622 MODIFY_REG(ADCx->CR,
4623 ADC_CR_BITS_PROPERTY_RS,
4624 ADC_CR_ADEN);
4625 }
4626
4627 /**
4628 * @brief Disable the selected ADC instance.
4629 * @note On this STM32 series, setting of this feature is conditioned to
4630 * ADC state:
4631 * ADC must be not disabled. Must be enabled without conversion on going
4632 * on group regular.
4633 * @rmtoll CR ADDIS LL_ADC_Disable
4634 * @param ADCx ADC instance
4635 * @retval None
4636 */
LL_ADC_Disable(ADC_TypeDef * ADCx)4637 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
4638 {
4639 /* Note: Write register with some additional bits forced to state reset */
4640 /* instead of modifying only the selected bit for this function, */
4641 /* to not interfere with bits with HW property "rs". */
4642 MODIFY_REG(ADCx->CR,
4643 ADC_CR_BITS_PROPERTY_RS,
4644 ADC_CR_ADDIS);
4645 }
4646
4647 /**
4648 * @brief Get the selected ADC instance enable state.
4649 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4650 * is enabled and when conversion clock is active.
4651 * (not only core clock: this ADC has a dual clock domain)
4652 * @rmtoll CR ADEN LL_ADC_IsEnabled
4653 * @param ADCx ADC instance
4654 * @retval 0: ADC is disabled, 1: ADC is enabled.
4655 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)4656 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
4657 {
4658 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
4659 }
4660
4661 /**
4662 * @brief Get the selected ADC instance disable state.
4663 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
4664 * @param ADCx ADC instance
4665 * @retval 0: no ADC disable command on going.
4666 */
LL_ADC_IsDisableOngoing(ADC_TypeDef * ADCx)4667 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
4668 {
4669 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
4670 }
4671
4672 /**
4673 * @brief Start ADC calibration in the mode single-ended
4674 * or differential (for devices with differential mode available).
4675 * @note On this STM32 series, a minimum number of ADC clock cycles
4676 * are required between ADC end of calibration and ADC enable.
4677 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
4678 * @note In case of usage of ADC with DMA transfer:
4679 * On this STM32 series, ADC DMA transfer request should be disabled
4680 * during calibration:
4681 * Calibration factor is available in data register
4682 * and also transferred by DMA.
4683 * To not insert ADC calibration factor among ADC conversion data
4684 * in array variable, DMA transfer must be disabled during
4685 * calibration.
4686 * (DMA transfer setting backup and disable before calibration,
4687 * DMA transfer setting restore after calibration.
4688 * Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
4689 * @ref LL_ADC_REG_SetDMATransfer() ).
4690 * @note In case of usage of feature auto power-off:
4691 * This mode must be disabled during calibration
4692 * Refer to function @ref LL_ADC_SetLowPowerMode().
4693 * @note On this STM32 series, setting of this feature is conditioned to
4694 * ADC state:
4695 * ADC must be ADC disabled.
4696 * @rmtoll CR ADCAL LL_ADC_StartCalibration
4697 * @param ADCx ADC instance
4698 * @retval None
4699 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx)4700 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
4701 {
4702 /* Note: Write register with some additional bits forced to state reset */
4703 /* instead of modifying only the selected bit for this function, */
4704 /* to not interfere with bits with HW property "rs". */
4705 MODIFY_REG(ADCx->CR,
4706 ADC_CR_BITS_PROPERTY_RS,
4707 ADC_CR_ADCAL);
4708 }
4709
4710 /**
4711 * @brief Get ADC calibration state.
4712 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
4713 * @param ADCx ADC instance
4714 * @retval 0: calibration complete, 1: calibration in progress.
4715 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)4716 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
4717 {
4718 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
4719 }
4720
4721 /**
4722 * @}
4723 */
4724
4725 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
4726 * @{
4727 */
4728
4729 /**
4730 * @brief Start ADC group regular conversion.
4731 * @note On this STM32 series, this function is relevant for both
4732 * internal trigger (SW start) and external trigger:
4733 * - If ADC trigger has been set to software start, ADC conversion
4734 * starts immediately.
4735 * - If ADC trigger has been set to external trigger, ADC conversion
4736 * will start at next trigger event (on the selected trigger edge)
4737 * following the ADC start conversion command.
4738 * @note On this STM32 series, setting of this feature is conditioned to
4739 * ADC state:
4740 * ADC must be enabled without conversion on going on group regular,
4741 * without conversion stop command on going on group regular,
4742 * without ADC disable command on going.
4743 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
4744 * @param ADCx ADC instance
4745 * @retval None
4746 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)4747 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
4748 {
4749 /* Note: Write register with some additional bits forced to state reset */
4750 /* instead of modifying only the selected bit for this function, */
4751 /* to not interfere with bits with HW property "rs". */
4752 MODIFY_REG(ADCx->CR,
4753 ADC_CR_BITS_PROPERTY_RS,
4754 ADC_CR_ADSTART);
4755 }
4756
4757 /**
4758 * @brief Stop ADC group regular conversion.
4759 * @note On this STM32 series, setting of this feature is conditioned to
4760 * ADC state:
4761 * ADC must be enabled with conversion on going on group regular,
4762 * without ADC disable command on going.
4763 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
4764 * @param ADCx ADC instance
4765 * @retval None
4766 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)4767 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
4768 {
4769 /* Note: Write register with some additional bits forced to state reset */
4770 /* instead of modifying only the selected bit for this function, */
4771 /* to not interfere with bits with HW property "rs". */
4772 MODIFY_REG(ADCx->CR,
4773 ADC_CR_BITS_PROPERTY_RS,
4774 ADC_CR_ADSTP);
4775 }
4776
4777 /**
4778 * @brief Get ADC group regular conversion state.
4779 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
4780 * @param ADCx ADC instance
4781 * @retval 0: no conversion is on going on ADC group regular.
4782 */
LL_ADC_REG_IsConversionOngoing(ADC_TypeDef * ADCx)4783 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
4784 {
4785 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
4786 }
4787
4788 /**
4789 * @brief Get ADC group regular command of conversion stop state
4790 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
4791 * @param ADCx ADC instance
4792 * @retval 0: no command of conversion stop is on going on ADC group regular.
4793 */
LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef * ADCx)4794 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
4795 {
4796 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
4797 }
4798
4799 /**
4800 * @brief Get ADC group regular conversion data, range fit for
4801 * all ADC configurations: all ADC resolutions and
4802 * all oversampling increased data width (for devices
4803 * with feature oversampling).
4804 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
4805 * @param ADCx ADC instance
4806 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4807 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)4808 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
4809 {
4810 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4811 }
4812
4813 /**
4814 * @brief Get ADC group regular conversion data, range fit for
4815 * ADC resolution 12 bits.
4816 * @note For devices with feature oversampling: Oversampling
4817 * can increase data width, function for extended range
4818 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4819 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
4820 * @param ADCx ADC instance
4821 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4822 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)4823 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
4824 {
4825 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4826 }
4827
4828 /**
4829 * @brief Get ADC group regular conversion data, range fit for
4830 * ADC resolution 10 bits.
4831 * @note For devices with feature oversampling: Oversampling
4832 * can increase data width, function for extended range
4833 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4834 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
4835 * @param ADCx ADC instance
4836 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4837 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)4838 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
4839 {
4840 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4841 }
4842
4843 /**
4844 * @brief Get ADC group regular conversion data, range fit for
4845 * ADC resolution 8 bits.
4846 * @note For devices with feature oversampling: Oversampling
4847 * can increase data width, function for extended range
4848 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4849 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
4850 * @param ADCx ADC instance
4851 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4852 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)4853 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
4854 {
4855 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4856 }
4857
4858 /**
4859 * @brief Get ADC group regular conversion data, range fit for
4860 * ADC resolution 6 bits.
4861 * @note For devices with feature oversampling: Oversampling
4862 * can increase data width, function for extended range
4863 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4864 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
4865 * @param ADCx ADC instance
4866 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4867 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)4868 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
4869 {
4870 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4871 }
4872
4873 /**
4874 * @}
4875 */
4876
4877 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4878 * @{
4879 */
4880
4881 /**
4882 * @brief Get flag ADC ready.
4883 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4884 * is enabled and when conversion clock is active.
4885 * (not only core clock: this ADC has a dual clock domain)
4886 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
4887 * @param ADCx ADC instance
4888 * @retval State of bit (1 or 0).
4889 */
LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef * ADCx)4890 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
4891 {
4892 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
4893 }
4894
4895 /**
4896 * @brief Get flag ADC channel configuration ready.
4897 * @note On this STM32 series, after modifying sequencer
4898 * it is mandatory to wait for the assertion of CCRDY flag
4899 * using @ref LL_ADC_IsActiveFlag_CCRDY().
4900 * Otherwise, performing some actions (configuration update,
4901 * ADC conversion start, ... ) will be ignored.
4902 * Functions requiring wait for CCRDY flag are:
4903 * @ref LL_ADC_REG_SetSequencerLength()
4904 * @ref LL_ADC_REG_SetSequencerRanks()
4905 * @ref LL_ADC_REG_SetSequencerChannels()
4906 * @ref LL_ADC_REG_SetSequencerChAdd()
4907 * @ref LL_ADC_REG_SetSequencerChRem()
4908 * @ref LL_ADC_REG_SetSequencerScanDirection()
4909 * @ref LL_ADC_REG_SetSequencerConfigurable()
4910 * @note Duration of ADC channel configuration ready: CCRDY handshake
4911 * requires 1APB + 2 ADC + 3 APB cycles after the channel configuration
4912 * has been changed.
4913 * @rmtoll ISR CCRDY LL_ADC_IsActiveFlag_CCRDY
4914 * @param ADCx ADC instance
4915 * @retval State of bit (1 or 0).
4916 */
LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef * ADCx)4917 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx)
4918 {
4919 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
4920 }
4921
4922 /**
4923 * @brief Get flag ADC group regular end of unitary conversion.
4924 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
4925 * @param ADCx ADC instance
4926 * @retval State of bit (1 or 0).
4927 */
LL_ADC_IsActiveFlag_EOC(ADC_TypeDef * ADCx)4928 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
4929 {
4930 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
4931 }
4932
4933 /**
4934 * @brief Get flag ADC group regular end of sequence conversions.
4935 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
4936 * @param ADCx ADC instance
4937 * @retval State of bit (1 or 0).
4938 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)4939 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
4940 {
4941 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
4942 }
4943
4944 /**
4945 * @brief Get flag ADC group regular overrun.
4946 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
4947 * @param ADCx ADC instance
4948 * @retval State of bit (1 or 0).
4949 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)4950 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
4951 {
4952 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
4953 }
4954
4955 /**
4956 * @brief Get flag ADC group regular end of sampling phase.
4957 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
4958 * @param ADCx ADC instance
4959 * @retval State of bit (1 or 0).
4960 */
LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef * ADCx)4961 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
4962 {
4963 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
4964 }
4965
4966 /**
4967 * @brief Get flag ADC analog watchdog 1 flag
4968 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
4969 * @param ADCx ADC instance
4970 * @retval State of bit (1 or 0).
4971 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)4972 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
4973 {
4974 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
4975 }
4976
4977 /**
4978 * @brief Get flag ADC analog watchdog 2.
4979 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
4980 * @param ADCx ADC instance
4981 * @retval State of bit (1 or 0).
4982 */
LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef * ADCx)4983 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
4984 {
4985 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
4986 }
4987
4988 /**
4989 * @brief Get flag ADC analog watchdog 3.
4990 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
4991 * @param ADCx ADC instance
4992 * @retval State of bit (1 or 0).
4993 */
LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef * ADCx)4994 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
4995 {
4996 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
4997 }
4998
4999 /**
5000 * @brief Get flag ADC end of calibration.
5001 * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
5002 * @param ADCx ADC instance
5003 * @retval State of bit (1 or 0).
5004 */
LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef * ADCx)5005 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx)
5006 {
5007 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
5008 }
5009
5010 /**
5011 * @brief Clear flag ADC ready.
5012 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
5013 * is enabled and when conversion clock is active.
5014 * (not only core clock: this ADC has a dual clock domain)
5015 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
5016 * @param ADCx ADC instance
5017 * @retval None
5018 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)5019 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
5020 {
5021 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
5022 }
5023
5024 /**
5025 * @brief Clear flag ADC channel configuration ready.
5026 * @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY
5027 * @param ADCx ADC instance
5028 * @retval State of bit (1 or 0).
5029 */
LL_ADC_ClearFlag_CCRDY(ADC_TypeDef * ADCx)5030 __STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx)
5031 {
5032 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY);
5033 }
5034
5035 /**
5036 * @brief Clear flag ADC group regular end of unitary conversion.
5037 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
5038 * @param ADCx ADC instance
5039 * @retval None
5040 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)5041 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
5042 {
5043 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
5044 }
5045
5046 /**
5047 * @brief Clear flag ADC group regular end of sequence conversions.
5048 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
5049 * @param ADCx ADC instance
5050 * @retval None
5051 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)5052 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
5053 {
5054 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
5055 }
5056
5057 /**
5058 * @brief Clear flag ADC group regular overrun.
5059 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
5060 * @param ADCx ADC instance
5061 * @retval None
5062 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)5063 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
5064 {
5065 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
5066 }
5067
5068 /**
5069 * @brief Clear flag ADC group regular end of sampling phase.
5070 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
5071 * @param ADCx ADC instance
5072 * @retval None
5073 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)5074 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
5075 {
5076 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
5077 }
5078
5079 /**
5080 * @brief Clear flag ADC analog watchdog 1.
5081 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
5082 * @param ADCx ADC instance
5083 * @retval None
5084 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)5085 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
5086 {
5087 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
5088 }
5089
5090 /**
5091 * @brief Clear flag ADC analog watchdog 2.
5092 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
5093 * @param ADCx ADC instance
5094 * @retval None
5095 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)5096 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
5097 {
5098 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
5099 }
5100
5101 /**
5102 * @brief Clear flag ADC analog watchdog 3.
5103 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
5104 * @param ADCx ADC instance
5105 * @retval None
5106 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)5107 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
5108 {
5109 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
5110 }
5111
5112 /**
5113 * @brief Clear flag ADC end of calibration.
5114 * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL
5115 * @param ADCx ADC instance
5116 * @retval None
5117 */
LL_ADC_ClearFlag_EOCAL(ADC_TypeDef * ADCx)5118 __STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
5119 {
5120 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
5121 }
5122
5123 /**
5124 * @}
5125 */
5126
5127 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
5128 * @{
5129 */
5130
5131 /**
5132 * @brief Enable ADC ready.
5133 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
5134 * @param ADCx ADC instance
5135 * @retval None
5136 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)5137 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
5138 {
5139 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
5140 }
5141
5142 /**
5143 * @brief Enable interruption ADC channel configuration ready.
5144 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_CCRDY
5145 * @param ADCx ADC instance
5146 * @retval State of bit (1 or 0).
5147 */
LL_ADC_EnableIT_CCRDY(ADC_TypeDef * ADCx)5148 __STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx)
5149 {
5150 SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
5151 }
5152
5153 /**
5154 * @brief Enable interruption ADC group regular end of unitary conversion.
5155 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
5156 * @param ADCx ADC instance
5157 * @retval None
5158 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)5159 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
5160 {
5161 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
5162 }
5163
5164 /**
5165 * @brief Enable interruption ADC group regular end of sequence conversions.
5166 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
5167 * @param ADCx ADC instance
5168 * @retval None
5169 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)5170 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
5171 {
5172 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
5173 }
5174
5175 /**
5176 * @brief Enable ADC group regular interruption overrun.
5177 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
5178 * @param ADCx ADC instance
5179 * @retval None
5180 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)5181 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
5182 {
5183 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
5184 }
5185
5186 /**
5187 * @brief Enable interruption ADC group regular end of sampling.
5188 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
5189 * @param ADCx ADC instance
5190 * @retval None
5191 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)5192 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
5193 {
5194 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
5195 }
5196
5197 /**
5198 * @brief Enable interruption ADC analog watchdog 1.
5199 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
5200 * @param ADCx ADC instance
5201 * @retval None
5202 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)5203 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
5204 {
5205 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
5206 }
5207
5208 /**
5209 * @brief Enable interruption ADC analog watchdog 2.
5210 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
5211 * @param ADCx ADC instance
5212 * @retval None
5213 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)5214 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
5215 {
5216 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
5217 }
5218
5219 /**
5220 * @brief Enable interruption ADC analog watchdog 3.
5221 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
5222 * @param ADCx ADC instance
5223 * @retval None
5224 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)5225 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
5226 {
5227 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
5228 }
5229 /**
5230 * @brief Enable interruption ADC end of calibration.
5231 * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
5232 * @param ADCx ADC instance
5233 * @retval None
5234 */
LL_ADC_EnableIT_EOCAL(ADC_TypeDef * ADCx)5235 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
5236 {
5237 SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
5238 }
5239
5240 /**
5241 * @brief Disable interruption ADC ready.
5242 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
5243 * @param ADCx ADC instance
5244 * @retval None
5245 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)5246 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
5247 {
5248 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
5249 }
5250
5251 /**
5252 * @brief Disable interruption ADC channel configuration ready.
5253 * @rmtoll IER CCRDYIE LL_ADC_DisableIT_CCRDY
5254 * @param ADCx ADC instance
5255 * @retval State of bit (1 or 0).
5256 */
LL_ADC_DisableIT_CCRDY(ADC_TypeDef * ADCx)5257 __STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx)
5258 {
5259 CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
5260 }
5261
5262 /**
5263 * @brief Disable interruption ADC group regular end of unitary conversion.
5264 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
5265 * @param ADCx ADC instance
5266 * @retval None
5267 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)5268 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
5269 {
5270 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
5271 }
5272
5273 /**
5274 * @brief Disable interruption ADC group regular end of sequence conversions.
5275 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
5276 * @param ADCx ADC instance
5277 * @retval None
5278 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)5279 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
5280 {
5281 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
5282 }
5283
5284 /**
5285 * @brief Disable interruption ADC group regular overrun.
5286 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
5287 * @param ADCx ADC instance
5288 * @retval None
5289 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)5290 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
5291 {
5292 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
5293 }
5294
5295 /**
5296 * @brief Disable interruption ADC group regular end of sampling.
5297 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
5298 * @param ADCx ADC instance
5299 * @retval None
5300 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)5301 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
5302 {
5303 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
5304 }
5305
5306 /**
5307 * @brief Disable interruption ADC analog watchdog 1.
5308 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
5309 * @param ADCx ADC instance
5310 * @retval None
5311 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)5312 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
5313 {
5314 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
5315 }
5316
5317 /**
5318 * @brief Disable interruption ADC analog watchdog 2.
5319 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
5320 * @param ADCx ADC instance
5321 * @retval None
5322 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)5323 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
5324 {
5325 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
5326 }
5327
5328 /**
5329 * @brief Disable interruption ADC analog watchdog 3.
5330 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
5331 * @param ADCx ADC instance
5332 * @retval None
5333 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)5334 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
5335 {
5336 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
5337 }
5338
5339 /**
5340 * @brief Disable interruption ADC end of calibration.
5341 * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
5342 * @param ADCx ADC instance
5343 * @retval None
5344 */
LL_ADC_DisableIT_EOCAL(ADC_TypeDef * ADCx)5345 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
5346 {
5347 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
5348 }
5349
5350 /**
5351 * @brief Get state of interruption ADC ready
5352 * (0: interrupt disabled, 1: interrupt enabled).
5353 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
5354 * @param ADCx ADC instance
5355 * @retval State of bit (1 or 0).
5356 */
LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef * ADCx)5357 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
5358 {
5359 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
5360 }
5361
5362 /**
5363 * @brief Get state of interruption ADC channel configuration ready.
5364 * @rmtoll IER CCRDYIE LL_ADC_IsEnabledIT_CCRDY
5365 * @param ADCx ADC instance
5366 * @retval State of bit (1 or 0).
5367 */
LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef * ADCx)5368 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx)
5369 {
5370 return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
5371 }
5372
5373 /**
5374 * @brief Get state of interruption ADC group regular end of unitary conversion
5375 * (0: interrupt disabled, 1: interrupt enabled).
5376 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
5377 * @param ADCx ADC instance
5378 * @retval State of bit (1 or 0).
5379 */
LL_ADC_IsEnabledIT_EOC(ADC_TypeDef * ADCx)5380 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
5381 {
5382 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
5383 }
5384
5385 /**
5386 * @brief Get state of interruption ADC group regular end of sequence conversions
5387 * (0: interrupt disabled, 1: interrupt enabled).
5388 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
5389 * @param ADCx ADC instance
5390 * @retval State of bit (1 or 0).
5391 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)5392 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
5393 {
5394 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
5395 }
5396
5397 /**
5398 * @brief Get state of interruption ADC group regular overrun
5399 * (0: interrupt disabled, 1: interrupt enabled).
5400 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
5401 * @param ADCx ADC instance
5402 * @retval State of bit (1 or 0).
5403 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)5404 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
5405 {
5406 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
5407 }
5408
5409 /**
5410 * @brief Get state of interruption ADC group regular end of sampling
5411 * (0: interrupt disabled, 1: interrupt enabled).
5412 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
5413 * @param ADCx ADC instance
5414 * @retval State of bit (1 or 0).
5415 */
LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef * ADCx)5416 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
5417 {
5418 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
5419 }
5420
5421 /**
5422 * @brief Get state of interruption ADC analog watchdog 1
5423 * (0: interrupt disabled, 1: interrupt enabled).
5424 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
5425 * @param ADCx ADC instance
5426 * @retval State of bit (1 or 0).
5427 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)5428 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
5429 {
5430 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
5431 }
5432
5433 /**
5434 * @brief Get state of interruption Get ADC analog watchdog 2
5435 * (0: interrupt disabled, 1: interrupt enabled).
5436 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
5437 * @param ADCx ADC instance
5438 * @retval State of bit (1 or 0).
5439 */
LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef * ADCx)5440 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
5441 {
5442 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
5443 }
5444
5445 /**
5446 * @brief Get state of interruption Get ADC analog watchdog 3
5447 * (0: interrupt disabled, 1: interrupt enabled).
5448 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
5449 * @param ADCx ADC instance
5450 * @retval State of bit (1 or 0).
5451 */
LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef * ADCx)5452 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
5453 {
5454 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
5455 }
5456
5457 /**
5458 * @brief Get state of interruption ADC end of calibration
5459 * (0: interrupt disabled, 1: interrupt enabled).
5460 * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
5461 * @param ADCx ADC instance
5462 * @retval State of bit (1 or 0).
5463 */
LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef * ADCx)5464 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx)
5465 {
5466 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
5467 }
5468
5469 /**
5470 * @}
5471 */
5472
5473 #if defined(USE_FULL_LL_DRIVER)
5474 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
5475 * @{
5476 */
5477
5478 /* Initialization of some features of ADC common parameters and multimode */
5479 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
5480 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
5481 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
5482
5483 /* De-initialization of ADC instance */
5484 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
5485 /* Initialization of some features of ADC instance */
5486 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
5487 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
5488
5489 /* Initialization of some features of ADC instance and ADC group regular */
5490 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
5491 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
5492
5493 /**
5494 * @}
5495 */
5496 #endif /* USE_FULL_LL_DRIVER */
5497
5498 /**
5499 * @}
5500 */
5501
5502 /**
5503 * @}
5504 */
5505
5506 #endif /* ADC1 */
5507
5508 /**
5509 * @}
5510 */
5511
5512 #ifdef __cplusplus
5513 }
5514 #endif
5515
5516 #endif /* STM32C0xx_LL_ADC_H */
5517
