1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G4xx_LL_ADC_H
21 #define STM32G4xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET (0x00000000UL)
56 #define ADC_SQR2_REGOFFSET (0x00000100UL)
57 #define ADC_SQR3_REGOFFSET (0x00000200UL)
58 #define ADC_SQR4_REGOFFSET (0x00000300UL)
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
61 | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/
63 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
64
65 /* Definition of ADC group regular sequencer bits information to be inserted */
66 /* into ADC group regular sequencer ranks literals definition. */
67 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
68 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
69 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
70 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
71 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)
72 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)
73 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)
74 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
75 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
76 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
77 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
78 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
79 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
80 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
81 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
82 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
83
84
85
86 /* Internal mask for ADC group injected sequencer: */
87 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
88 /* - data register offset */
89 /* - sequencer rank bits position into the selected register */
90
91 /* Internal register offset for ADC group injected data register */
92 /* (offset placed into a spare area of literal definition) */
93 #define ADC_JDR1_REGOFFSET (0x00000000UL)
94 #define ADC_JDR2_REGOFFSET (0x00000100UL)
95 #define ADC_JDR3_REGOFFSET (0x00000200UL)
96 #define ADC_JDR4_REGOFFSET (0x00000300UL)
97
98 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
99 | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
100 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
101 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/
102
103 /* Definition of ADC group injected sequencer bits information to be inserted */
104 /* into ADC group injected sequencer ranks literals definition. */
105 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
106 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
107 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
108 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
109
110
111
112 /* Internal mask for ADC group regular trigger: */
113 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
114 /* - regular trigger source */
115 /* - regular trigger edge */
116 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for
117 compatibility with some ADC on other STM32 series
118 having this setting set by HW default value) */
119
120 /* Mask containing trigger source masks for each of possible */
121 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
122 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
123 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
124 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
125 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
126 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
127
128 /* Mask containing trigger edge masks for each of possible */
129 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
130 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
131 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
132 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
133 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
134 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
135
136 /* Definition of ADC group regular trigger bits information. */
137 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)
138 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)
139
140
141
142 /* Internal mask for ADC group injected trigger: */
143 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
144 /* - injected trigger source */
145 /* - injected trigger edge */
146 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
147 compatibility with some ADC on other STM32 series
148 having this setting set by HW default value) */
149
150 /* Mask containing trigger source masks for each of possible */
151 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
152 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
153 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
154 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
155 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
156 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
157
158 /* Mask containing trigger edge masks for each of possible */
159 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
160 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
161 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
162 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
163 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
164 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
165
166 /* Definition of ADC group injected trigger bits information. */
167 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
168 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
169
170
171
172
173
174
175 /* Internal mask for ADC channel: */
176 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
177 /* - channel identifier defined by number */
178 /* - channel identifier defined by bitfield */
179 /* - channel differentiation between external channels (connected to */
180 /* GPIO pins) and internal channels (connected to internal paths) */
181 /* - channel sampling time defined by SMPRx register offset */
182 /* and SMPx bits positions into SMPRx register */
183 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
184 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
185 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
186 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
187 | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
188 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
189 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
190 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
191
192 /* Channel differentiation between external and internal channels */
193 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
194 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case
195 of different ADC internal channels mapped on same channel
196 number on different ADC instances */
197 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
198
199 /* Internal register offset for ADC channel sampling time configuration */
200 /* (offset placed into a spare area of literal definition) */
201 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
202 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
203 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
204 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET
205 in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
206
207 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
208 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK"
209 position in register */
210
211 /* Definition of channels ID number information to be inserted into */
212 /* channels literals definition. */
213 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
214 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
215 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
216 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
217 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
218 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
219 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
220 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
221 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
222 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
223 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
224 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
225 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
226 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
227 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
228 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
229 ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
230 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
231 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
232 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
233
234 /* Definition of channels ID bitfield information to be inserted into */
235 /* channels literals definition. */
236 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
237 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
238 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
239 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
240 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
241 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
242 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
243 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
244 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
245 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
246 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
247 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
248 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
249 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
250 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
251 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
252 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
253 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
254 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
255
256 /* Definition of channels sampling time information to be inserted into */
257 /* channels literals definition. */
258 /* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position */
259 /* in register. */
260 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
261 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
262 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
263 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
264 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
265 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
266 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
267 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
268 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
269 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
270 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
271 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
272 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
273 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
274 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
275 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
276 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
277 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
278 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
279
280
281 /* Internal mask for ADC mode single or differential ended: */
282 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
283 /* the relevant bits for: */
284 /* (concatenation of multiple bits used in different registers) */
285 /* - ADC calibration: calibration start, calibration factor get or set */
286 /* - ADC channels: set each ADC channel ending mode */
287 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
288 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
289 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
290 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen
291 to perform of shift when single mode is selected, shift value out of
292 channels bits range. */
293 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
294 mask of bit */
295 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode:
296 position of bit */
297 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
298 ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */
299
300 /* Internal mask for ADC analog watchdog: */
301 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
302 /* (concatenation of multiple bits used in different analog watchdogs, */
303 /* (feature of several watchdogs not available on all STM32 series)). */
304 /* - analog watchdog 1: monitored channel defined by number, */
305 /* selection of ADC group (ADC groups regular and-or injected). */
306 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
307 /* selection on groups. */
308
309 /* Internal register offset for ADC analog watchdog channel configuration */
310 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
311 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
312 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
313
314 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
315 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
316 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
317 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
318
319 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
320
321 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
322 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
323 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
324
325 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
326 in ADC_AWD_CRX_REGOFFSET_MASK */
327
328 /* Internal register offset for ADC analog watchdog threshold configuration */
329 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
330 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
331 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
332 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
333 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
334 in ADC_AWD_TRX_REGOFFSET_MASK */
335 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
336 threshold high: mask of bit */
337 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
338 threshold high: position of bit */
339 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
340 position to perform a shift of 4 ranks */
341
342 /* Internal mask for ADC offset: */
343 /* Internal register offset for ADC offset instance configuration */
344 #define ADC_OFR1_REGOFFSET (0x00000000UL)
345 #define ADC_OFR2_REGOFFSET (0x00000001UL)
346 #define ADC_OFR3_REGOFFSET (0x00000002UL)
347 #define ADC_OFR4_REGOFFSET (0x00000003UL)
348 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
349 | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
350
351
352 /* ADC registers bits positions */
353 #define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
354 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
355 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
356 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
357 #define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)
358
359
360 /* ADC registers bits groups */
361 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
362 | ADC_CR_JADSTART | ADC_CR_JADSTP \
363 | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
364 HW property "rs": Software can read as well as set this bit.
365 Writing '0' has no effect on the bit value. */
366
367
368 /* ADC internal channels related definitions */
369 /* Internal voltage reference VrefInt */
370 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of
371 parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
372 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
373 #define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value
374 with which VrefInt has been calibrated in production
375 (tolerance: +-10 mV) (unit: mV). */
376 /* Temperature sensor */
377 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G4,
378 temperature sensor ADC raw data acquired at temperature 30 DegC
379 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
380 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G4,
381 temperature sensor ADC raw data acquired at temperature 110 DegC
382 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
383 #define TEMPSENSOR_CAL1_TEMP (30L) /* Temperature at which temperature sensor
384 has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
385 (tolerance: +-5 DegC) (unit: DegC). */
386 #define TEMPSENSOR_CAL2_TEMP (110L) /* Temperature at which temperature sensor
387 has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
388 (tolerance: +-5 DegC) (unit: DegC). */
389 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) value
390 with which temperature sensor has been calibrated in production
391 (tolerance +-10 mV) (unit: mV). */
392
393 /**
394 * @}
395 */
396
397
398 /* Private macros ------------------------------------------------------------*/
399 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
400 * @{
401 */
402
403 /**
404 * @brief Driver macro reserved for internal use: set a pointer to
405 * a register from a register basis from which an offset
406 * is applied.
407 * @param __REG__ Register basis from which the offset is applied.
408 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
409 * @retval Pointer to register address
410 */
411 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
412 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
413
414 /**
415 * @}
416 */
417
418
419 /* Exported types ------------------------------------------------------------*/
420 #if defined(USE_FULL_LL_DRIVER)
421 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
422 * @{
423 */
424
425 /**
426 * @brief Structure definition of some features of ADC common parameters
427 * and multimode
428 * (all ADC instances belonging to the same ADC common instance).
429 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
430 * is conditioned to ADC instances state (all ADC instances
431 * sharing the same ADC common instance):
432 * All ADC instances sharing the same ADC common instance must be
433 * disabled.
434 */
435 typedef struct
436 {
437 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
438 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
439 @note On this STM32 series, if ADC group injected is used, some clock ratio
440 constraints between ADC clock and AHB clock must be respected.
441 Refer to reference manual.
442 This feature can be modified afterwards using unitary function
443 @ref LL_ADC_SetCommonClock(). */
444
445 #if defined(ADC_MULTIMODE_SUPPORT)
446 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode
447 (for devices with several ADC instances).
448 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
449 This feature can be modified afterwards using unitary function
450 @ref LL_ADC_SetMultimode(). */
451
452 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
453 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
454 This feature can be modified afterwards using unitary function
455 @ref LL_ADC_SetMultiDMATransfer(). */
456
457 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
458 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
459 This feature can be modified afterwards using unitary function
460 @ref LL_ADC_SetMultiTwoSamplingDelay(). */
461 #endif /* ADC_MULTIMODE_SUPPORT */
462
463 } LL_ADC_CommonInitTypeDef;
464
465 /**
466 * @brief Structure definition of some features of ADC instance.
467 * @note These parameters have an impact on ADC scope: ADC instance.
468 * Affects both group regular and group injected (availability
469 * of ADC group injected depends on STM32 series).
470 * Refer to corresponding unitary functions into
471 * @ref ADC_LL_EF_Configuration_ADC_Instance .
472 * @note The setting of these parameters by function @ref LL_ADC_Init()
473 * is conditioned to ADC state:
474 * ADC instance must be disabled.
475 * This condition is applied to all ADC features, for efficiency
476 * and compatibility over all STM32 series. However, the different
477 * features can be set under different ADC state conditions
478 * (setting possible with ADC enabled without conversion on going,
479 * ADC enabled with conversion on going, ...)
480 * Each feature can be updated afterwards with a unitary function
481 * and potentially with ADC in a different state than disabled,
482 * refer to description of each function for setting
483 * conditioned to ADC state.
484 */
485 typedef struct
486 {
487 uint32_t Resolution; /*!< Set ADC resolution.
488 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
489 This feature can be modified afterwards using unitary function
490 @ref LL_ADC_SetResolution(). */
491
492 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
493 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
494 This feature can be modified afterwards using unitary function
495 @ref LL_ADC_SetDataAlignment(). */
496
497 uint32_t LowPowerMode; /*!< Set ADC low power mode.
498 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
499 This feature can be modified afterwards using unitary function
500 @ref LL_ADC_SetLowPowerMode(). */
501
502 } LL_ADC_InitTypeDef;
503
504 /**
505 * @brief Structure definition of some features of ADC group regular.
506 * @note These parameters have an impact on ADC scope: ADC group regular.
507 * Refer to corresponding unitary functions into
508 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
509 * (functions with prefix "REG").
510 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
511 * is conditioned to ADC state:
512 * ADC instance must be disabled.
513 * This condition is applied to all ADC features, for efficiency
514 * and compatibility over all STM32 series. However, the different
515 * features can be set under different ADC state conditions
516 * (setting possible with ADC enabled without conversion on going,
517 * ADC enabled with conversion on going, ...)
518 * Each feature can be updated afterwards with a unitary function
519 * and potentially with ADC in a different state than disabled,
520 * refer to description of each function for setting
521 * conditioned to ADC state.
522 */
523 typedef struct
524 {
525 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
526 from external peripheral (timer event, external interrupt line).
527 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
528 @note On this STM32 series, setting trigger source to external trigger also
529 set trigger polarity to rising edge(default setting for compatibility
530 with some ADC on other STM32 series having this setting set by HW
531 default value).
532 In case of need to modify trigger edge, use function
533 @ref LL_ADC_REG_SetTriggerEdge().
534 This feature can be modified afterwards using unitary function
535 @ref LL_ADC_REG_SetTriggerSource(). */
536
537 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
538 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
539 This feature can be modified afterwards using unitary function
540 @ref LL_ADC_REG_SetSequencerLength(). */
541
542 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
543 and scan conversions interrupted every selected number of ranks.
544 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
545 @note This parameter has an effect only if group regular sequencer is
546 enabled (scan length of 2 ranks or more).
547 This feature can be modified afterwards using unitary function
548 @ref LL_ADC_REG_SetSequencerDiscont(). */
549
550 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
551 conversions are performed in single mode (one conversion per trigger) or in
552 continuous mode (after the first trigger, following conversions launched
553 successively automatically).
554 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
555 Note: It is not possible to enable both ADC group regular continuous mode
556 and discontinuous mode.
557 This feature can be modified afterwards using unitary function
558 @ref LL_ADC_REG_SetContinuousMode(). */
559
560 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
561 by DMA, and DMA requests mode.
562 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
563 This feature can be modified afterwards using unitary function
564 @ref LL_ADC_REG_SetDMATransfer(). */
565
566 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
567 data preserved or overwritten.
568 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
569 This feature can be modified afterwards using unitary function
570 @ref LL_ADC_REG_SetOverrun(). */
571
572 } LL_ADC_REG_InitTypeDef;
573
574 /**
575 * @brief Structure definition of some features of ADC group injected.
576 * @note These parameters have an impact on ADC scope: ADC group injected.
577 * Refer to corresponding unitary functions into
578 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
579 * (functions with prefix "INJ").
580 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
581 * is conditioned to ADC state:
582 * ADC instance must be disabled.
583 * This condition is applied to all ADC features, for efficiency
584 * and compatibility over all STM32 series. However, the different
585 * features can be set under different ADC state conditions
586 * (setting possible with ADC enabled without conversion on going,
587 * ADC enabled with conversion on going, ...)
588 * Each feature can be updated afterwards with a unitary function
589 * and potentially with ADC in a different state than disabled,
590 * refer to description of each function for setting
591 * conditioned to ADC state.
592 */
593 typedef struct
594 {
595 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start)
596 or from external peripheral (timer event, external interrupt line).
597 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
598 @note On this STM32 series, setting trigger source to external trigger also
599 set trigger polarity to rising edge (default setting for
600 compatibility with some ADC on other STM32 series having this
601 setting set by HW default value).
602 In case of need to modify trigger edge, use function
603 @ref LL_ADC_INJ_SetTriggerEdge().
604 This feature can be modified afterwards using unitary function
605 @ref LL_ADC_INJ_SetTriggerSource(). */
606
607 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
608 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
609 This feature can be modified afterwards using unitary function
610 @ref LL_ADC_INJ_SetSequencerLength(). */
611
612 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
613 and scan conversions interrupted every selected number of ranks.
614 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
615 @note This parameter has an effect only if group injected sequencer is
616 enabled (scan length of 2 ranks or more).
617 This feature can be modified afterwards using unitary function
618 @ref LL_ADC_INJ_SetSequencerDiscont(). */
619
620 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group
621 regular.
622 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
623 Note: This parameter must be set to set to independent trigger if injected
624 trigger source is set to an external trigger.
625 This feature can be modified afterwards using unitary function
626 @ref LL_ADC_INJ_SetTrigAuto(). */
627
628 } LL_ADC_INJ_InitTypeDef;
629
630 /**
631 * @}
632 */
633 #endif /* USE_FULL_LL_DRIVER */
634
635 /* Exported constants --------------------------------------------------------*/
636 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
637 * @{
638 */
639
640 /** @defgroup ADC_LL_EC_FLAG ADC flags
641 * @brief Flags defines which can be used with LL_ADC_ReadReg function
642 * @{
643 */
644 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
645 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
646 conversion */
647 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
648 conversions */
649 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
650 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
651 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary
652 conversion */
653 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence
654 conversions */
655 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue
656 overflow */
657 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
658 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
659 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
660 #if defined(ADC_MULTIMODE_SUPPORT)
661 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
662 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
663 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of
664 unitary conversion */
665 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of
666 unitary conversion */
667 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of
668 sequence conversions */
669 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of
670 sequence conversions */
671 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular
672 overrun */
673 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular
674 overrun */
675 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of
676 sampling phase */
677 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of
678 sampling phase */
679 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of
680 unitary conversion */
681 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of
682 unitary conversion */
683 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of
684 sequence conversions */
685 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of
686 sequence conversions */
687 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected
688 contexts queue overflow */
689 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected
690 contexts queue overflow */
691 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1
692 of the ADC master */
693 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1
694 of the ADC slave */
695 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2
696 of the ADC master */
697 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2
698 of the ADC slave */
699 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3
700 of the ADC master */
701 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3
702 of the ADC slave */
703 #endif /* ADC_MULTIMODE_SUPPORT */
704 /**
705 * @}
706 */
707
708 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
709 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
710 * @{
711 */
712 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
713 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
714 conversion */
715 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
716 conversions */
717 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
718 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
719 phase */
720 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary
721 conversion */
722 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence
723 conversions */
724 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue
725 overflow */
726 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
727 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
728 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
729 /**
730 * @}
731 */
732
733 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
734 * @{
735 */
736 /* List of ADC registers intended to be used (most commonly) with */
737 /* DMA transfer. */
738 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
739 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
740 (corresponding to register DR) to be used with ADC configured in independent
741 mode. Without DMA transfer, register accessed by LL function
742 @ref LL_ADC_REG_ReadConversionData32() and other
743 functions @ref LL_ADC_REG_ReadConversionDatax() */
744 #if defined(ADC_MULTIMODE_SUPPORT)
745 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register
746 (corresponding to register CDR) to be used with ADC configured in multimode
747 (available on STM32 devices with several ADC instances).
748 Without DMA transfer, register accessed by LL function
749 @ref LL_ADC_REG_ReadMultiConversionData32() */
750 #endif /* ADC_MULTIMODE_SUPPORT */
751 /**
752 * @}
753 */
754
755 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
756 * @{
757 */
758 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
759 AHB clock without prescaler */
760 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from
761 AHB clock with prescaler division by 2 */
762 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
763 AHB clock with prescaler division by 4 */
764 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without
765 prescaler */
766 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
767 prescaler division by 2 */
768 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
769 prescaler division by 4 */
770 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
771 prescaler division by 6 */
772 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
773 prescaler division by 8 */
774 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
775 prescaler division by 10 */
776 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
777 prescaler division by 12 */
778 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
779 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
780 prescaler division by 16 */
781 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
782 prescaler division by 32 */
783 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
784 prescaler division by 64 */
785 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
786 prescaler division by 128 */
787 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
788 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
789 prescaler division by 256 */
790 /**
791 * @}
792 */
793
794 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
795 * @{
796 */
797 /* Note: Other measurement paths to internal channels may be available */
798 /* (connections to other peripherals). */
799 /* If they are not listed below, they do not require any specific */
800 /* path enable. In this case, Access to measurement path is done */
801 /* only by selecting the corresponding ADC internal channel. */
802 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
803 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
804 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel
805 temperature sensor */
806 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */
807 /**
808 * @}
809 */
810
811 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
812 * @{
813 */
814 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
815 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
816 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
817 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
818 /**
819 * @}
820 */
821
822 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
823 * @{
824 */
825 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
826 (alignment on data register LSB bit 0)*/
827 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned
828 (alignment on data register MSB bit 15)*/
829 /**
830 * @}
831 */
832
833 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
834 * @{
835 */
836 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
837 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power
838 mode, ADC conversions are performed only when necessary
839 (when previous ADC conversion data is read).
840 See description with function @ref LL_ADC_SetLowPowerMode(). */
841 /**
842 * @}
843 */
844
845 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset instance
846 * @{
847 */
848 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level
849 to which the offset programmed will be applied (independently of channel
850 mapped on ADC group regular or injected) */
851 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level
852 to which the offset programmed will be applied (independently of channel
853 mapped on ADC group regular or injected) */
854 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level
855 to which the offset programmed will be applied (independently of channel
856 mapped on ADC group regular or injected) */
857 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level
858 to which the offset programmed will be applied (independently of channel
859 mapped on ADC group regular or injected) */
860 /**
861 * @}
862 */
863
864 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
865 * @{
866 */
867 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled
868 (setting offset instance wise) */
869 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled
870 (setting offset instance wise) */
871 /**
872 * @}
873 */
874
875 /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
876 * @{
877 */
878 #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative */
879 #define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive */
880 /**
881 * @}
882 */
883
884 /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
885 * @{
886 */
887 #define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC
888 selected offset instance 1, 2, 3 or 4) */
889 #define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC
890 selected offset instance 1, 2, 3 or 4) */
891 /**
892 * @}
893 */
894 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
895 * @{
896 */
897 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
898 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32
899 devices)*/
900 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
901 /**
902 * @}
903 */
904
905 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
906 * @{
907 */
908 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP \
909 | ADC_CHANNEL_0_BITFIELD) /*!< ADC channel ADCx_IN0 */
910 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP \
911 | ADC_CHANNEL_1_BITFIELD) /*!< ADC channel ADCx_IN1 */
912 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP \
913 | ADC_CHANNEL_2_BITFIELD) /*!< ADC channel ADCx_IN2 */
914 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP \
915 | ADC_CHANNEL_3_BITFIELD) /*!< ADC channel ADCx_IN3 */
916 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP \
917 | ADC_CHANNEL_4_BITFIELD) /*!< ADC channel ADCx_IN4 */
918 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP \
919 | ADC_CHANNEL_5_BITFIELD) /*!< ADC channel ADCx_IN5 */
920 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP \
921 | ADC_CHANNEL_6_BITFIELD) /*!< ADC channel ADCx_IN6 */
922 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP \
923 | ADC_CHANNEL_7_BITFIELD) /*!< ADC channel ADCx_IN7 */
924 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP \
925 | ADC_CHANNEL_8_BITFIELD) /*!< ADC channel ADCx_IN8 */
926 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP \
927 | ADC_CHANNEL_9_BITFIELD) /*!< ADC channel ADCx_IN9 */
928 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP \
929 | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
930 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP \
931 | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
932 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP \
933 | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
934 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP \
935 | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
936 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP \
937 | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
938 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP \
939 | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
940 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | \
941 ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
942 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | \
943 ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
944 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | \
945 ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */
946 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
947 connected to VrefInt: Internal voltage reference.
948 On this STM32 series, ADC channel available on all instances but ADC2. */
949 #define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
950 connected to internal temperature sensor.
951 On this STM32 series, ADC channel available only on ADC1 instance. */
952 #define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
953 connected to internal temperature sensor.
954 On this STM32 series, ADC channel available only on ADC5 instance.
955 Refer to device datasheet for ADC5 availability */
956 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
957 connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3
958 to have channel voltage always below Vdda. On this STM32 series, ADC channel
959 available on all ADC instances but ADC2 & ADC4. Refer to device datasheet
960 for ADC4 availability */
961 #define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
962 connected to OPAMP1 output.
963 On this STM32 series, ADC channel available only on ADC1 instance. */
964 #define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | \
965 ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2
966 output. On this STM32 series, ADC channel available only on ADC2 instance. */
967 #define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | \
968 ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3
969 output. On this STM32 series, ADC channel available only on ADC2 instance. */
970 #define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | \
971 ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3
972 output. On this STM32 series, ADC channel available only on ADC3 instance.
973 Refer to device datasheet for ADC3 availability */
974 #define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
975 connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance.
976 Refer to device datasheet for ADC5 & OPAMP4 availability */
977 #define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
978 connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance.
979 Refer to device datasheet for ADC5 & OPAMP5 availability */
980 #define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | \
981 ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel
982 connected to OPAMP6 output.
983 On this STM32 series, ADC channel available only on ADC4 instance.
984 Refer to device datasheet for ADC4 & OPAMP6 availability */
985 /**
986 * @}
987 */
988
989 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
990 * @{
991 */
992 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular
993 conversion trigger internal: SW start. */
994 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | \
995 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
996 conversion trigger from external peripheral: TIM1 TRGO.
997 Trigger edge set to rising edge (default setting). */
998 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
999 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1000 conversion trigger from external peripheral: TIM1 TRGO2.
1001 Trigger edge set to rising edge (default setting). */
1002 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1003 conversion trigger from external peripheral: TIM1 channel 1 event (capture
1004 compare: input capture or output capture).
1005 Trigger edge set to rising edge (default setting).
1006 Note: On this STM32 series, this trigger is available only on
1007 ADC1/2 instances */
1008 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1009 conversion trigger from external peripheral: TIM1 channel 2 event (capture
1010 compare: input capture or output capture).
1011 Trigger edge set to rising edge (default setting).
1012 Note: On this STM32 series, this trigger is available only on
1013 ADC1/2 instances */
1014 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1015 conversion trigger from external peripheral: TIM1 channel 3 event (capture
1016 compare: input capture or output capture).
1017 Trigger edge set to rising edge (default setting). */
1018 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
1019 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1020 conversion trigger from external peripheral: TIM2 TRGO.
1021 Trigger edge set to rising edge (default setting). */
1022 #define LL_ADC_REG_TRIG_EXT_TIM2_CH1 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
1023 ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
1024 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
1025 conversion trigger from external peripheral: TIM2 channel 1 event (capture
1026 compare: input capture or output capture).
1027 Trigger edge set to rising edge (default setting).
1028 Note: On this STM32 series, this trigger is available only on
1029 ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
1030 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
1031 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1032 conversion trigger from external peripheral: TIM2 channel 2 event (capture
1033 compare: input capture or output capture).
1034 Trigger edge set to rising edge (default setting).
1035 Note: On this STM32 series, this trigger is available only on
1036 ADC1/2 instances */
1037 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1038 conversion trigger from external peripheral: TIM2 channel 3 event (capture
1039 compare: input capture or output capture).
1040 Trigger edge set to rising edge (default setting).
1041 Note: On this STM32 series, this trigger is available only on
1042 ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
1043 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1044 conversion trigger from external peripheral: TIM3 TRGO.
1045 Trigger edge set to rising edge (default setting). */
1046 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1047 conversion trigger from external peripheral: TIM3 channel 1 event (capture
1048 compare: input capture or output capture).
1049 Trigger edge set to rising edge (default setting).
1050 Note: On this STM32 series, this trigger is available only on
1051 ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
1052 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
1053 ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
1054 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1055 conversion trigger from external peripheral: TIM3 channel 4 event (capture
1056 compare: input capture or output capture).
1057 Trigger edge set to rising edge (default setting).
1058 Note: On this STM32 series, this trigger is available only on
1059 ADC1/2 instances */
1060 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
1061 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1062 conversion trigger from external peripheral: TIM4 TRGO.
1063 Trigger edge set to rising edge (default setting). */
1064 #define LL_ADC_REG_TRIG_EXT_TIM4_CH1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
1065 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1066 conversion trigger from external peripheral: TIM4 channel 1 event (capture
1067 compare: input capture or output capture).
1068 Trigger edge set to rising edge (default setting).
1069 Note: On this STM32 series, this trigger is available only on
1070 ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
1071 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
1072 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1073 conversion trigger from external peripheral: TIM4 channel 4 event (capture
1074 compare: input capture or output capture).
1075 Trigger edge set to rising edge (default setting).
1076 Note: On this STM32 series, this trigger is available only on
1077 ADC1/2 instances */
1078 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
1079 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1080 conversion trigger from external peripheral: TIM6 TRGO.
1081 Trigger edge set to rising edge (default setting). */
1082 #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
1083 ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
1084 conversion trigger from external peripheral: TIM7 TRGO.
1085 Trigger edge set to rising edge (default setting). */
1086 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
1087 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1088 conversion trigger from external peripheral: TIM8 TRGO.
1089 Trigger edge set to rising edge (default setting). */
1090 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1091 conversion trigger from external peripheral: TIM8 TRGO2.
1092 Trigger edge set to rising edge (default setting). */
1093 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
1094 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1095 conversion trigger from external peripheral: TIM8 channel 1 event (capture
1096 compare: input capture or output capture).
1097 Trigger edge set to rising edge (default setting).
1098 Note: On this STM32 series, this trigger is available only on
1099 ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
1100 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
1101 ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1102 conversion trigger from external peripheral: TIM15 TRGO.
1103 Trigger edge set to rising edge (default setting). */
1104 #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1105 conversion trigger from external peripheral: TIM20 TRGO.
1106 Trigger edge set to rising edge (default setting).
1107 Note: On this STM32 series, TIM20 is not available on all devices.
1108 Refer to device datasheet for more details */
1109 #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | \
1110 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1111 conversion trigger from external peripheral: TIM20 TRGO2.
1112 Trigger edge set to rising edge (default setting).
1113 Note: On this STM32 series, TIM20 is not available on all devices.
1114 Refer to device datasheet for more details */
1115 #define LL_ADC_REG_TRIG_EXT_TIM20_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
1116 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1117 conversion trigger from external peripheral: TIM20 channel 1 event (capture
1118 compare: input capture or output capture).
1119 Trigger edge set to rising edge (default setting).
1120 Note: On this STM32 series, TIM20 is not available on all devices.
1121 Refer to device datasheet for more details */
1122 #define LL_ADC_REG_TRIG_EXT_TIM20_CH2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
1123 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1124 conversion trigger from external peripheral: TIM20 channel 2 event (capture
1125 compare: input capture or output capture).
1126 Trigger edge set to rising edge (default setting).
1127 Note: On this STM32 series, this trigger is available only on
1128 ADC1/2 instances, and TIM20 is not available on all devices.
1129 Refer to device datasheet for more details */
1130 #define LL_ADC_REG_TRIG_EXT_TIM20_CH3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
1131 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1132 conversion trigger from external peripheral: TIM20 channel 3 event (capture
1133 compare: input capture or output capture).
1134 Trigger edge set to rising edge (default setting).
1135 Note: On this STM32 series, this trigger is available only on
1136 ADC1/2 instances, and TIM20 is not available on all devices.
1137 Refer to device datasheet for more details */
1138 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
1139 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1140 conversion trigger from external peripheral: HRTIMER ADC trigger 1 event.
1141 Trigger edge set to rising edge (default setting).
1142 Note: On this STM32 series, HRTIM is not available on all devices.
1143 Refer to device datasheet for more details */
1144 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
1145 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1146 conversion trigger from external peripheral: HRTIMER ADC trigger 2 event.
1147 Trigger edge set to rising edge (default setting).
1148 Note: On this STM32 series, this trigger is available only on
1149 ADC3/4/5 instances, and HRTIM is not available on all devices.
1150 Refer to device datasheet for more details */
1151 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
1152 ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1153 conversion trigger from external peripheral: HRTIMER ADC trigger 3 event.
1154 Trigger edge set to rising edge (default setting).
1155 Note: On this STM32 series, HRTIM is not available on all devices.
1156 Refer to device datasheet for more details */
1157 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
1158 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1159 conversion trigger from external peripheral: HRTIMER ADC trigger 4 event.
1160 Trigger edge set to rising edge (default setting).
1161 Note: On this STM32 series, this trigger is available only on
1162 ADC3/4/5 instances, and HRTIM is not available on all devices.
1163 Refer to device datasheet for more details */
1164 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
1165 ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
1166 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1167 conversion trigger from external peripheral: HRTIMER ADC trigger 5 event.
1168 Trigger edge set to rising edge (default setting).
1169 Note: On this STM32 series, HRTIM is not available on all devices.
1170 Refer to device datasheet for more details */
1171 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
1172 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1173 conversion trigger from external peripheral: HRTIMER ADC trigger 6 event.
1174 Trigger edge set to rising edge (default setting).
1175 Note: On this STM32 series, HRTIM is not available on all devices.
1176 Refer to device datasheet for more details */
1177 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
1178 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1179 conversion trigger from external peripheral: HRTIMER ADC trigger 7 event.
1180 Trigger edge set to rising edge (default setting).
1181 Note: On this STM32 series, HRTIM is not available on all devices.
1182 Refer to device datasheet for more details */
1183 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
1184 ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1185 conversion trigger from external peripheral: HRTIMER ADC trigger 8 event.
1186 Trigger edge set to rising edge (default setting).
1187 Note: On this STM32 series, HRTIM is not available on all devices.
1188 Refer to device datasheet for more details */
1189 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
1190 ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
1191 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1192 conversion trigger from external peripheral: HRTIMER ADC trigger 9 event.
1193 Trigger edge set to rising edge (default setting).
1194 Note: On this STM32 series, HRTIM is not available on all devices.
1195 Refer to device datasheet for more details */
1196 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
1197 ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1198 conversion trigger from external peripheral: HRTIMER ADC trigger 10 event.
1199 Trigger edge set to rising edge (default setting).
1200 Note: On this STM32 series, HRTIM is not available on all devices.
1201 Refer to device datasheet for more details */
1202 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
1203 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1204 conversion trigger from external peripheral: external interrupt line 11.
1205 Trigger edge set to rising edge (default setting).
1206 Note: On this STM32 series, this trigger is available only on
1207 ADC1/2 instances */
1208 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
1209 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1210 conversion trigger from external peripheral: external interrupt line 2.
1211 Trigger edge set to rising edge (default setting).
1212 Note: On this STM32 series, this trigger is available only on
1213 ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
1214 #define LL_ADC_REG_TRIG_EXT_LPTIM_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
1215 ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
1216 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1217 conversion trigger from external peripheral: LPTIMER OUT event.
1218 Trigger edge set to rising edge (default setting). */
1219 /**
1220 * @}
1221 */
1222
1223 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
1224 * @{
1225 */
1226 #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion
1227 trigger polarity set to rising edge */
1228 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1) /*!< ADC group regular conversion
1229 trigger polarity set to falling edge */
1230 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion
1231 trigger polarity set to both rising and falling edges */
1232 /**
1233 * @}
1234 */
1235
1236 /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
1237 * @{
1238 */
1239 #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration
1240 is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */
1241 #define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts
1242 immediately after end of conversion, and stops upon trigger event.
1243 Note: First conversion is using minimal sampling time
1244 (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */
1245 #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is
1246 controlled by trigger events: trigger rising edge for start sampling,
1247 trigger falling edge for stop sampling and start conversion */
1248 /**
1249 * @}
1250 */
1251
1252 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
1253 * @{
1254 */
1255 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
1256 one conversion per trigger */
1257 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions performed in continuous mode:
1258 after the first trigger, following conversions launched successively
1259 automatically */
1260 /**
1261 * @}
1262 */
1263
1264 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
1265 * @{
1266 */
1267 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
1268 #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA
1269 in limited mode (one shot mode): DMA transfer requests are stopped when
1270 number of DMA data transfers (number of ADC conversions) is reached.
1271 This ADC mode is intended to be used with DMA mode non-circular. */
1272 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are
1273 transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
1274 whatever number of DMA data transferred (number of ADC conversions).
1275 This ADC mode is intended to be used with DMA mode circular. */
1276 /**
1277 * @}
1278 */
1279
1280 #if defined(ADC_SMPR1_SMPPLUS)
1281 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
1282 * @{
1283 */
1284 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */
1285 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock
1286 cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped
1287 with selection sampling time 2.5 ADC clock cycles, whatever channels mapped
1288 on ADC groups regular or injected). */
1289 /**
1290 * @}
1291 */
1292 #endif /* ADC_SMPR1_SMPPLUS */
1293
1294 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
1295 * @{
1296 */
1297 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
1298 data preserved */
1299 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun:
1300 data overwritten */
1301 /**
1302 * @}
1303 */
1304
1305 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1306 * @{
1307 */
1308 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable
1309 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1310 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1311 with 2 ranks in the sequence */
1312 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1313 with 3 ranks in the sequence */
1314 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1315 with 4 ranks in the sequence */
1316 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1317 with 5 ranks in the sequence */
1318 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1319 with 6 ranks in the sequence */
1320 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1321 with 7 ranks in the sequence */
1322 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1 \
1323 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1324 with 8 ranks in the sequence */
1325 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3) /*!< ADC group regular sequencer enable
1326 with 9 ranks in the sequence */
1327 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1328 with 10 ranks in the sequence */
1329 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1330 with 11 ranks in the sequence */
1331 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \
1332 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1333 with 12 ranks in the sequence */
1334 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1335 with 13 ranks in the sequence */
1336 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1337 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1338 with 14 ranks in the sequence */
1339 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1340 | ADC_SQR1_L_1) /*!< ADC group regular sequencerenable
1341 with 15 ranks in the sequence */
1342 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1343 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1344 with 16 ranks in the sequence */
1345 /**
1346 * @}
1347 */
1348
1349 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1350 * @{
1351 */
1352 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
1353 discontinuous mode disable */
1354 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1355 discontinuous mode enable with sequence interruption every rank */
1356 #define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1357 discontinuous mode enabled with sequence interruption every 2 ranks */
1358 #define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1359 discontinuous mode enable with sequence interruption every 3 ranks */
1360 #define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 \
1361 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1362 discontinuous mode enable with sequence interruption every 4 ranks */
1363 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1364 discontinuous mode enable with sequence interruption every 5 ranks */
1365 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 \
1366 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1367 discontinuous mode enable with sequence interruption every 6 ranks */
1368 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
1369 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1370 discontinuous mode enable with sequence interruption every 7 ranks */
1371 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
1372 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1373 discontinuous mode enable with sequence interruption every 8 ranks */
1374 /**
1375 * @}
1376 */
1377
1378 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1379 * @{
1380 */
1381 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group
1382 regular sequencer rank 1 */
1383 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group
1384 regular sequencer rank 2 */
1385 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group
1386 regular sequencer rank 3 */
1387 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group
1388 regular sequencer rank 4 */
1389 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group
1390 regular sequencer rank 5 */
1391 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group
1392 regular sequencer rank 6 */
1393 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group
1394 regular sequencer rank 7 */
1395 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group
1396 regular sequencer rank 8 */
1397 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group
1398 regular sequencer rank 9 */
1399 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group
1400 regular sequencer rank 10 */
1401 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group
1402 regular sequencer rank 11 */
1403 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group
1404 regular sequencer rank 12 */
1405 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group
1406 regular sequencer rank 13 */
1407 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group
1408 regular sequencer rank 14 */
1409 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group
1410 regular sequencer rank 15 */
1411 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group
1412 regular sequencer rank 16 */
1413 /**
1414 * @}
1415 */
1416
1417 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1418 * @{
1419 */
1420 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected
1421 conversion trigger internal: SW start. */
1422 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1423 ADC group injected conversion trigger from external peripheral: TIM1 TRGO.
1424 Trigger edge set to rising edge (default setting). */
1425 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1426 ADC group injected conversion trigger from external peripheral: TIM1 TRGO2.
1427 Trigger edge set to rising edge (default setting). */
1428 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
1429 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1430 ADC group injected conversion trigger from external peripheral: TIM1
1431 channel 3 event (capture compare: input capture or output capture).
1432 Trigger edge set to rising edge (default setting).
1433 Note: On this STM32 series, this trigger is available only on ADC3/4/5
1434 instances. Refer to device datasheet for ADCx availability */
1435 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1436 ADC group injected conversion trigger from external peripheral: TIM1
1437 channel 4 event (capture compare: input capture or output capture).
1438 Trigger edge set to rising edge (default setting). */
1439 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1440 ADC group injected conversion trigger from external peripheral: TIM2 TRGO.
1441 Trigger edge set to rising edge (default setting). */
1442 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
1443 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1444 ADC group injected conversion trigger from external peripheral: TIM2
1445 channel 1 event (capture compare: input capture or output capture).
1446 Trigger edge set to rising edge (default setting).
1447 Note: On this STM32 series, this trigger is available only on ADC1/2
1448 instances */
1449 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1450 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1451 ADC group injected conversion trigger from external peripheral: TIM3 TRGO.
1452 Trigger edge set to rising edge (default setting). */
1453 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1454 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1455 ADC group injected conversion trigger from external peripheral: TIM3
1456 channel 1 event (capture compare: input capture or output capture).
1457 Trigger edge set to rising edge (default setting).
1458 Note: On this STM32 series, this trigger is available only on ADC1/2
1459 instances */
1460 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
1461 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1462 ADC group injected conversion trigger from external peripheral: TIM3
1463 channel 3 event (capture compare: input capture or output capture).
1464 Trigger edge set to rising edge (default setting).
1465 Note: On this STM32 series, this trigger is available only on ADC1/2
1466 instances */
1467 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1468 ADC group injected conversion trigger from external peripheral: TIM3
1469 channel 4 event (capture compare: input capture or output capture).
1470 Trigger edge set to rising edge (default setting).
1471 Note: On this STM32 series, this trigger is available only on ADC1/2
1472 instances */
1473 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
1474 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1475 ADC group injected conversion trigger from external peripheral: TIM4 TRGO.
1476 Trigger edge set to rising edge (default setting). */
1477 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1478 ADC group injected conversion trigger from external peripheral: TIM4
1479 channel 3 event (capture compare: input capture or output capture).
1480 Trigger edge set to rising edge (default setting).
1481 Note: On this STM32 series, this trigger is available only on ADC3/4/5
1482 instances. Refer to device datasheet for ADCx availability */
1483 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
1484 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1485 ADC group injected conversion trigger from external peripheral: TIM4
1486 channel 4 event (capture compare: input capture or output capture).
1487 Trigger edge set to rising edge (default setting).
1488 Note: On this STM32 series, this trigger is available only on ADC3/4/5
1489 instances. Refer to device datasheet for ADCx availability */
1490 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1491 ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1492 ADC group injected conversion trigger from external peripheral: TIM6 TRGO.
1493 Trigger edge set to rising edge (default setting). */
1494 #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
1495 ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1496 ADC group injected conversion trigger from external peripheral: TIM7 TRGO.
1497 Trigger edge set to rising edge (default setting). */
1498 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \
1499 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1500 ADC group injected conversion trigger from external peripheral: TIM8 TRGO.
1501 Trigger edge set to rising edge (default setting). */
1502 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
1503 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1504 ADC group injected conversion trigger from external peripheral: TIM8 TRGO2.
1505 Trigger edge set to rising edge (default setting). */
1506 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
1507 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1508 ADC group injected conversion trigger from external peripheral: TIM8
1509 channel 2 event (capture compare: input capture or output capture).
1510 Trigger edge set to rising edge (default setting).
1511 Note: On this STM32 series, this trigger is available only on ADC3/4/5
1512 instances. Refer to device datasheet for ADCx availability */
1513 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
1514 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1515 ADC group injected conversion trigger from external peripheral: TIM8
1516 channel 4 event (capture compare: input capture or output capture).
1517 Trigger edge set to rising edge (default setting). */
1518 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1519 ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1520 ADC group injected conversion trigger from external peripheral: TIM15 TRGO.
1521 Trigger edge set to rising edge (default setting). */
1522 #define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
1523 ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1524 ADC group injected conversion trigger from external peripheral: TIM8
1525 channel 4 event (capture compare: input capture or output capture).
1526 Trigger edge set to rising edge (default setting).
1527 Note: On this STM32 series, this trigger is available only on ADC1/2
1528 instances */
1529 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1530 ADC group injected conversion trigger from external peripheral: TIM20 TRGO.
1531 Trigger edge set to rising edge (default setting).
1532 Note: On this STM32 series, TIM20 is not available on all devices. Refer to
1533 device datasheet for more details */
1534 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | \
1535 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1536 ADC group injected conversion trigger from external peripheral: TIM20 TRGO2.
1537 Trigger edge set to rising edge (default setting).
1538 Note: On this STM32 series, TIM20 is not available on all devices. Refer to
1539 device datasheet for more details */
1540 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
1541 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1542 ADC group injected conversion trigger from external peripheral: TIM20
1543 channel 2 event (capture compare: input capture or output capture).
1544 Trigger edge set to rising edge (default setting).
1545 Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is
1546 not available on all devices. Refer to device datasheet for more details */
1547 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
1548 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1549 ADC group injected conversion trigger from external peripheral: TIM20
1550 channel 4 event (capture compare: input capture or output capture).
1551 Trigger edge set to rising edge (default setting).
1552 Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is
1553 not available on all devices. Refer to device datasheet for more details */
1554 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
1555 ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1556 ADC group injected conversion trigger from external peripheral: HRTIMER
1557 ADC trigger 1 event. Trigger edge set to rising edge (default setting).
1558 Note: On this STM32 series, this trigger is available only on ADC3/4/5
1559 instances, and HRTIM is not available on all devices. Refer to device
1560 datasheet for more details */
1561 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
1562 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1563 ADC group injected conversion trigger from external peripheral: HRTIMER ADC
1564 trigger 2 event. Trigger edge set to rising edge (default setting).
1565 Note: On this STM32 series, HRTIM is not available on all devices. Refer to
1566 device datasheet for more details */
1567 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
1568 ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1569 ADC group injected conversion trigger from external peripheral: HRTIMER
1570 ADC trigger 3 event. Trigger edge set to rising edge (default setting).
1571 Note: On this STM32 series, this trigger is available only on ADC3/4/5
1572 instances, and HRTIM is not available on all devices. Refer to device
1573 datasheet for more details */
1574 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
1575 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1576 ADC group injected conversion trigger from external peripheral: HRTIMER ADC
1577 trigger 4 event. Trigger edge set to rising edge (default setting).
1578 Note: On this STM32 series, HRTIM is not available on all devices. Refer to
1579 device datasheet for more details */
1580 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
1581 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1582 ADC group injected conversion trigger from external peripheral: HRTIMER ADC
1583 trigger 5 event. Trigger edge set to rising edge (default setting).
1584 Note: On this STM32 series, HRTIM is not available on all devices. Refer to
1585 device datasheet for more details */
1586 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
1587 ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1588 ADC group injected conversion trigger from external peripheral: HRTIMER ADC
1589 trigger 6 event. Trigger edge set to rising edge (default setting).
1590 Note: On this STM32 series, HRTIM is not available on all devices. Refer to
1591 device datasheet for more details */
1592 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
1593 ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1594 ADC group injected conversion trigger from external peripheral: HRTIMER ADC
1595 trigger 7 event. Trigger edge set to rising edge (default setting).
1596 Note: On this STM32 series, HRTIM is not available on all devices. Refer to
1597 device datasheet for more details */
1598 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
1599 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1600 ADC group injected conversion trigger from external peripheral: HRTIMER ADC
1601 trigger 8 event. Trigger edge set to rising edge (default setting).
1602 Note: On this STM32 series, HRTIM is not available on all devices. Refer to
1603 device datasheet for more details */
1604 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
1605 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1606 ADC group injected conversion trigger from external peripheral: HRTIMER ADC
1607 trigger 9 event. Trigger edge set to rising edge (default setting).
1608 Note: On this STM32 series, HRTIM is not available on all devices. Refer to
1609 device datasheet for more details */
1610 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
1611 ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1612 ADC group injected conversion trigger from external peripheral: HRTIMER ADC
1613 trigger 10 event. Trigger edge set to rising edge (default setting).
1614 Note: On this STM32 series, HRTIM is not available on all devices.Refer to
1615 device datasheet for more details */
1616 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1617 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1618 ADC group injected conversion trigger from external peripheral: external
1619 interrupt line 3. Trigger edge set to rising edge (default setting).
1620 Note: On this STM32 series, this trigger is available only on ADC3/4/5
1621 instances. Refer to device datasheet for ADCx availability */
1622 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
1623 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1624 ADC group injected conversion trigger from external peripheral: external
1625 interrupt line 15. Trigger edge set to rising edge (default setting).
1626 Note: On this STM32 series, this trigger is available only on ADC1/2
1627 instances. */
1628 #define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
1629 ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1630 ADC group injected conversion trigger from external peripheral: LPTIMER OUT
1631 event. Trigger edge set to rising edge (default setting). */
1632 /**
1633 * @}
1634 */
1635
1636 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1637 * @{
1638 */
1639 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
1640 trigger polarity set to rising edge */
1641 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion
1642 trigger polarity set to falling edge */
1643 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
1644 trigger polarity set to both rising and falling edges */
1645 /**
1646 * @}
1647 */
1648
1649 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1650 * @{
1651 */
1652 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent.
1653 Setting mandatory if ADC group injected injected trigger source is set to
1654 an external trigger. */
1655 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group
1656 regular. Setting compliant only with group injected trigger source set to
1657 SW start, without any further action on ADC group injected conversion start
1658 or stop: in this case, ADC group injected is controlled only from ADC group
1659 regular. */
1660 /**
1661 * @}
1662 */
1663
1664 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1665 * @{
1666 */
1667 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled
1668 and can contain up to 2 contexts. When all contexts have been processed,
1669 the queue maintains the last context active perpetually. */
1670 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled
1671 and can contain up to 2 contexts. When all contexts have been processed,
1672 the queue is empty and injected group triggers are disabled. */
1673 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled:
1674 only 1 sequence can be configured and is active perpetually. */
1675 /**
1676 * @}
1677 */
1678
1679 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1680 * @{
1681 */
1682 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable
1683 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1684 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
1685 with 2 ranks in the sequence */
1686 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable
1687 with 3 ranks in the sequence */
1688 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
1689 with 4 ranks in the sequence */
1690 /**
1691 * @}
1692 */
1693
1694 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1695 * @{
1696 */
1697 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode
1698 disable */
1699 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode
1700 enable with sequence interruption every rank */
1701 /**
1702 * @}
1703 */
1704
1705 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1706 * @{
1707 */
1708 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \
1709 | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 1 */
1710 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \
1711 | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 2 */
1712 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \
1713 | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 3 */
1714 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \
1715 | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 4 */
1716 /**
1717 * @}
1718 */
1719
1720 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1721 * @{
1722 */
1723 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
1724 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
1725 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */
1726 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 (ADC_SMPR2_SMP10_1 \
1727 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
1728 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */
1729 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 \
1730 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
1731 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 \
1732 | ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */
1733 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 \
1734 | ADC_SMPR2_SMP10_1 \
1735 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
1736 /**
1737 * @}
1738 */
1739
1740 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1741 * @{
1742 */
1743 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending
1744 set to single ended (literal also used to set calibration mode) */
1745 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending
1746 set to differential (literal also used to set calibration mode) */
1747 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending
1748 set to both single ended and differential (literal used only to set
1749 calibration factors) */
1750 /**
1751 * @}
1752 */
1753
1754 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1755 * @{
1756 */
1757 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
1758 | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1759 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
1760 | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1761 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
1762 | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1763 /**
1764 * @}
1765 */
1766
1767 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1768 * @{
1769 */
1770 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
1771 disabled */
1772 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
1773 | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring
1774 of all channels, converted by group regular only */
1775 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1776 | ADC_CFGR_JAWD1EN) /*!< ADC analog watchdog monitoring
1777 of all channels, converted by group injected only */
1778 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1779 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring
1780 of all channels, converted by either group regular or injected */
1781 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1782 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1783 of ADC channel ADCx_IN0, converted by group regular only */
1784 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1785 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1786 of ADC channel ADCx_IN0, converted by group injected only */
1787 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1788 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1789 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1790 of ADC channel ADCx_IN0, converted by either group regular or injected */
1791 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1792 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1793 of ADC channel ADCx_IN1, converted by group regular only */
1794 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1795 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1796 of ADC channel ADCx_IN1, converted by group injected only */
1797 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1798 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1799 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1800 of ADC channel ADCx_IN1, converted by either group regular or injected */
1801 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1802 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1803 of ADC channel ADCx_IN2, converted by group regular only */
1804 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1805 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1806 of ADC channel ADCx_IN2, converted by group injected only */
1807 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1808 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1809 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1810 of ADC channel ADCx_IN2, converted by either group regular or injected */
1811 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1812 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1813 of ADC channel ADCx_IN3, converted by group regular only */
1814 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1815 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1816 of ADC channel ADCx_IN3, converted by group injected only */
1817 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1818 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1819 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1820 of ADC channel ADCx_IN3, converted by either group regular or injected */
1821 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1822 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1823 of ADC channel ADCx_IN4, converted by group regular only */
1824 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1825 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1826 of ADC channel ADCx_IN4, converted by group injected only */
1827 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1828 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1829 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1830 of ADC channel ADCx_IN4, converted by either group regular or injected */
1831 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1832 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1833 of ADC channel ADCx_IN5, converted by group regular only */
1834 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1835 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1836 of ADC channel ADCx_IN5, converted by group injected only */
1837 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1838 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1839 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1840 of ADC channel ADCx_IN5, converted by either group regular or injected */
1841 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1842 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1843 of ADC channel ADCx_IN6, converted by group regular only */
1844 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1845 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1846 of ADC channel ADCx_IN6, converted by group injected only */
1847 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1848 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1849 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1850 of ADC channel ADCx_IN6, converted by either group regular or injected */
1851 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1852 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1853 of ADC channel ADCx_IN7, converted by group regular only */
1854 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1855 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1856 of ADC channel ADCx_IN7, converted by group injected only */
1857 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1858 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1859 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1860 of ADC channel ADCx_IN7, converted by either group regular or injected */
1861 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1862 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1863 of ADC channel ADCx_IN8, converted by group regular only */
1864 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1865 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1866 of ADC channel ADCx_IN8, converted by group injected only */
1867 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1868 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1869 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1870 of ADC channel ADCx_IN8, converted by either group regular or injected */
1871 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1872 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1873 of ADC channel ADCx_IN9, converted by group regular only */
1874 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1875 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1876 of ADC channel ADCx_IN9, converted by group injected only */
1877 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1878 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1879 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1880 of ADC channel ADCx_IN9, converted by either group regular or injected */
1881 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1882 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1883 of ADC channel ADCx_IN10, converted by group regular only */
1884 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1885 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1886 of ADC channel ADCx_IN10, converted by group injected only */
1887 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)\
1888 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1889 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1890 of ADC channel ADCx_IN10, converted by either group regular or injected */
1891 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1892 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1893 of ADC channel ADCx_IN11, converted by group regular only */
1894 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1895 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1896 of ADC channel ADCx_IN11, converted by group injected only */
1897 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1898 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1899 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1900 of ADC channel ADCx_IN11, converted by either group regular or injected */
1901 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1902 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1903 of ADC channel ADCx_IN12, converted by group regular only */
1904 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1905 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1906 of ADC channel ADCx_IN12, converted by group injected only */
1907 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1908 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1909 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1910 of ADC channel ADCx_IN12, converted by either group regular or injected */
1911 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1912 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1913 of ADC channel ADCx_IN13, converted by group regular only */
1914 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1915 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1916 of ADC channel ADCx_IN13, converted by group injected only */
1917 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1918 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1919 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1920 of ADC channel ADCx_IN13, converted by either group regular or injected */
1921 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1922 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1923 of ADC channel ADCx_IN14, converted by group regular only */
1924 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1925 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1926 of ADC channel ADCx_IN14, converted by group only */
1927 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1928 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1929 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1930 of ADC channel ADCx_IN14, converted by either group regular or injected */
1931 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1932 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1933 monitoring of ADC channel ADCx_IN15, converted by group regular only */
1934 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1935 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1936 of ADC channel ADCx_IN15, converted by group injected only */
1937 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1938 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1939 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1940 of ADC channel ADCx_IN15, converted by either group
1941 regular or injected */
1942 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1943 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1944 of ADC channel ADCx_IN16, converted by group regular only */
1945 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1946 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1947 of ADC channel ADCx_IN16, converted by group injected only */
1948 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1949 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1950 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1951 of ADC channel ADCx_IN16, converted by either group regular or injected */
1952 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1953 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1954 of ADC channel ADCx_IN17, converted by group regular only */
1955 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1956 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1957 of ADC channel ADCx_IN17, converted by group injected only */
1958 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1959 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1960 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1961 of ADC channel ADCx_IN17, converted by either group regular or injected */
1962 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1963 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1964 of ADC channel ADCx_IN18, converted by group regular only */
1965 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1966 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1967 of ADC channel ADCx_IN18, converted by group injected only */
1968 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1969 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1970 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1971 of ADC channel ADCx_IN18, converted by either group regular or injected */
1972 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1973 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1974 of ADC internal channel connected to VrefInt: Internal
1975 voltage reference, converted by group regular only */
1976 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1977 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1978 of ADC internal channel connected to VrefInt: Internal
1979 voltage reference, converted by group injected only */
1980 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1981 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1982 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1983 of ADC internal channel connected to VrefInt: Internal
1984 voltage reference, converted by either group regular or injected */
1985 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
1986 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1987 of ADC1 internal channel connected to internal temperature sensor,
1988 converted by group regular only */
1989 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
1990 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog
1991 of ADC1 internal channel connected to internal temperature sensor,
1992 converted by group injected only */
1993 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
1994 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1995 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1996 of ADC1 internal channel connected to internal temperature sensor,
1997 converted by either group regular or injected */
1998 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
1999 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2000 of ADC5 internal channel connected to internal temperature sensor,
2001 converted by group regular only */
2002 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
2003 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog
2004 of ADC5 internal channel connected to internal temperature sensor,
2005 converted by group injected only */
2006 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
2007 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
2008 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2009 of ADC5 internal channel connected to internal temperature sensor,
2010 converted by either group regular or injected */
2011 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
2012 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2013 of ADC internal channel connected to Vbat/3: Vbat
2014 voltage through a divider ladder of factor 1/3 to have channel voltage always below
2015 Vdda, converted by group regular only */
2016 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
2017 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2018 of ADC internal channel connected to Vbat/3: Vbat
2019 voltage through a divider ladder of factor 1/3 to have channel voltage always below
2020 Vdda, converted by group injected only */
2021 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
2022 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
2023 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2024 of ADC internal channel connected to Vbat/3: Vbat
2025 voltage through a divider ladder of factor 1/3 to have channel voltage always below
2026 Vdda */
2027 #define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \
2028 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2029 of ADC internal channel connected to OPAMP1 output,
2030 channel specific to ADC1, converted by group regular only */
2031 #define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \
2032 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2033 of ADC internal channel connected to OPAMP1 output,
2034 channel specific to ADC1, converted by group injected only */
2035 #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \
2036 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
2037 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2038 of ADC internal channel connected to OPAMP1 output,
2039 channel specific to ADC1, converted by either group regular or injected */
2040 #define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \
2041 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2042 channel specific to ADC2, converted by group regular only */
2043 #define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \
2044 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2045 of ADC internal channel connected to OPAMP2 output,
2046 channel specific to ADC2, converted by group injected only */
2047 #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \
2048 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
2049 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2050 of ADC internal channel connected to OPAMP2 output,
2051 channel specific to ADC2, converted by either group regular or injected */
2052 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) \
2053 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2054 of ADC internal channel connected to OPAMP3 output,
2055 channel specific to ADC2, converted by group regular only */
2056 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) \
2057 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2058 of ADC internal channel connected to OPAMP3 output,
2059 channel specific to ADC2, converted by group injected only */
2060 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) \
2061 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
2062 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2063 of ADC internal channel connected to OPAMP3 output,
2064 channel specific to ADC2, converted by either group regular or injected */
2065 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) \
2066 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2067 of ADC internal channel connected to OPAMP3 output,
2068 channel specific to ADC3, converted by group regular only */
2069 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) \
2070 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2071 of ADC internal channel connected to OPAMP3 output,
2072 channel specific to ADC3, converted by group injected only */
2073 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) \
2074 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
2075 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2076 of ADC internal channel connected to OPAMP3 output,
2077 channel specific to ADC3, converted by either group regular or injected */
2078 #define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) \
2079 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2080 of ADC internal channel connected to OPAMP4 output,
2081 channel specific to ADC5, converted by group regular only */
2082 #define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) \
2083 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2084 of ADC internal channel connected to OPAMP4 output,
2085 channel specific to ADC5, converted by group injected only */
2086 #define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) \
2087 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
2088 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2089 of ADC internal channel connected to OPAMP4 output,
2090 channel specific to ADC5, converted by either group regular or injected */
2091 #define LL_ADC_AWD_CH_VOPAMP5_REG ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) \
2092 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2093 of ADC internal channel connected to OPAMP5 output,
2094 channel specific to ADC5, converted by group regular only */
2095 #define LL_ADC_AWD_CH_VOPAMP5_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) \
2096 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2097 of ADC internal channel connected to OPAMP5 output,
2098 channel specific to ADC5, converted by group injected only */
2099 #define LL_ADC_AWD_CH_VOPAMP5_REG_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) \
2100 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
2101 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2102 of ADC internal channel connected to OPAMP5 output,
2103 channel specific to ADC5, converted by either group regular or injected */
2104 #define LL_ADC_AWD_CH_VOPAMP6_REG ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) \
2105 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2106 of ADC internal channel connected to OPAMP6 output,
2107 channel specific to ADC4, converted by group regular only */
2108 #define LL_ADC_AWD_CH_VOPAMP6_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) \
2109 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2110 of ADC internal channel connected to OPAMP6 output,
2111 channel specific to ADC4, converted by group injected only */
2112 #define LL_ADC_AWD_CH_VOPAMP6_REG_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) \
2113 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
2114 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
2115 of ADC internal channel connected to OPAMP6 output,
2116 channel specific to ADC4, converted by either group regular or injected */
2117 /**
2118 * @}
2119 */
2120
2121 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
2122 * @{
2123 */
2124 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1) /*!< ADC analog watchdog threshold high */
2125 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
2126 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 \
2127 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low
2128 concatenated into the same data */
2129 /**
2130 * @}
2131 */
2132
2133 /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
2134 * @{
2135 */
2136 #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering,
2137 one out-of-window sample is needed to raise flag or interrupt */
2138 #define LL_ADC_AWD_FILTERING_2SAMPLES (ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 2
2139 out-of-window samples are needed to raise flag or interrupt */
2140 #define LL_ADC_AWD_FILTERING_3SAMPLES (ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 3
2141 consecutives out-of-window samples are needed to raise flag or interrupt */
2142 #define LL_ADC_AWD_FILTERING_4SAMPLES (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 4
2143 consecutives out-of-window samples are needed to raise flag or interrupt */
2144 #define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2) /*!< ADC analog watchdog 5
2145 consecutives out-of-window samples are needed to raise flag or interrupt */
2146 #define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 6
2147 consecutives out-of-window samples are needed to raise flag or interrupt */
2148 #define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 7
2149 consecutives out-of-window samples are needed to raise flag or interrupt */
2150 #define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \
2151 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 8
2152 consecutives out-of-window samples are needed to raise flag or interrupt */
2153 /**
2154 * @}
2155 */
2156
2157 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
2158 * @{
2159 */
2160 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
2161 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
2162 ADC group regular. If group injected interrupts group regular:
2163 when ADC group injected is triggered, the oversampling on ADC group regular
2164 is temporary stopped and continued afterwards. */
2165 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
2166 ADC group regular. If group injected interrupts group regular:
2167 when ADC group injected is triggered, the oversampling on ADC group regular
2168 is resumed from start (oversampler buffer reset). */
2169 #define LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of
2170 ADC group injected. */
2171 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
2172 both ADC groups regular and injected. If group injected interrupting group
2173 regular: when ADC group injected is triggered, the oversampling on ADC group
2174 regular is resumed from start (oversampler buffer reset). */
2175 /**
2176 * @}
2177 */
2178
2179 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
2180 * @{
2181 */
2182 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
2183 (all conversions of oversampling ratio are done from 1 trigger) */
2184 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous
2185 mode (each conversion of oversampling ratio needs a trigger) */
2186 /**
2187 * @}
2188 */
2189
2190 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
2191 * @{
2192 */
2193 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2
2194 (sum of conversions data computed to result as oversampling conversion data
2195 (before potential shift) */
2196 #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4
2197 (sum of conversions data computed to result as oversampling conversion data
2198 (before potential shift) */
2199 #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8
2200 (sum of conversions data computed to result as oversampling conversion data
2201 (before potential shift) */
2202 #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
2203 (sum of conversions data computed to result as oversampling conversion data
2204 (before potential shift) */
2205 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32
2206 (sum of conversions data computed to result as oversampling conversion data
2207 (before potential shift) */
2208 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
2209 (sum of conversions data computed to result as oversampling conversion data
2210 (before potential shift) */
2211 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
2212 (sum of conversions data computed to result as oversampling conversion data
2213 (before potential shift) */
2214 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
2215 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256
2216 (sum of conversions data computed to result as oversampling conversion data
2217 (before potential shift) */
2218 /**
2219 * @}
2220 */
2221
2222 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
2223 * @{
2224 */
2225 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
2226 (sum of the ADC conversions data is not divided to result as oversampling
2227 conversion data) */
2228 #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
2229 (sum of the ADC conversions data (after OVS ratio) is divided by 2
2230 to result as oversampling conversion data) */
2231 #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
2232 (sum of the ADC conversions data (after OVS ratio) is divided by 4
2233 to result as oversampling conversion data) */
2234 #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
2235 (sum of the ADC conversions data (after OVS ratio) is divided by 8
2236 to result as oversampling conversion data) */
2237 #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
2238 (sum of the ADC conversions data (after OVS ratio) is divided by 16
2239 to result as oversampling conversion data) */
2240 #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
2241 (sum of the ADC conversions data (after OVS ratio) is divided by 32
2242 to result as oversampling conversion data) */
2243 #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
2244 (sum of the ADC conversions data (after OVS ratio) is divided by 64
2245 to result as oversampling conversion data) */
2246 #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
2247 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
2248 (sum of the ADC conversions data (after OVS ratio) is divided by 128
2249 to result as oversampling conversion data) */
2250 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
2251 (sum of the ADC conversions data (after OVS ratio) is divided by 256
2252 to result as oversampling conversion data) */
2253 /**
2254 * @}
2255 */
2256
2257 #if defined(ADC_MULTIMODE_SUPPORT)
2258 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
2259 * @{
2260 */
2261 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC
2262 independent mode) */
2263 #define LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular
2264 simultaneous */
2265 #define LL_ADC_MULTI_DUAL_REG_INTERL (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \
2266 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
2267 regular interleaved */
2268 #define LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
2269 simultaneous */
2270 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
2271 alternate trigger. Works only with external triggers (not SW start) */
2272 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
2273 regular simultaneous + group injected simultaneous */
2274 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group
2275 regular simultaneous + group injected alternate trigger */
2276 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
2277 regular interleaved + group injected simultaneous */
2278 /**
2279 * @}
2280 */
2281
2282 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
2283 * @{
2284 */
2285 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular
2286 conversions are transferred by DMA: each ADC uses its own DMA channel,
2287 with its individual DMA transfer settings */
2288 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1) /*!< ADC multimode group regular
2289 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
2290 ADC master), in limited mode (one shot mode): DMA transfer requests
2291 are stopped when number of DMA data transfers (number of ADC conversions)
2292 is reached. This ADC mode is intended to be used with DMA mode
2293 non-circular. Setting for ADC resolution of 12 and 10 bits */
2294 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
2295 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
2296 ADC master), in limited mode (one shot mode): DMA transfer requests
2297 are stopped when number of DMA data transfers (number of ADC conversions)
2298 is reached. This ADC mode is intended to be used with DMA mode
2299 non-circular. Setting for ADC resolution of 8 and 6 bits */
2300 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1) /*!< ADC multimode group regular
2301 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
2302 ADC master), in unlimited mode: DMA transfer requests are unlimited,
2303 whatever number of DMA data transferred (number of ADC conversions).
2304 This ADC mode is intended to be used with DMA mode circular.
2305 Setting for ADC resolution of 12 and 10 bits */
2306 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 \
2307 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
2308 conversions are transferred by DMA, one DMA channel for both ADC (DMA of
2309 ADC master), in unlimited mode: DMA transfer requests are unlimited,
2310 whatever number of DMA data transferred (number of ADC conversions).
2311 This ADC mode is intended to be used with DMA mode circular.
2312 Setting for ADC resolution of 8 and 6 bits */
2313 /**
2314 * @}
2315 */
2316
2317 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
2318 * @{
2319 */
2320 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two
2321 sampling phases: 1 ADC clock cycle */
2322 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
2323 sampling phases: 2 ADC clock cycles */
2324 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
2325 sampling phases: 3 ADC clock cycles */
2326 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
2327 sampling phases: 4 ADC clock cycles */
2328 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2) /*!< ADC multimode delay between two
2329 sampling phases: 5 ADC clock cycles */
2330 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
2331 sampling phases: 6 ADC clock cycles */
2332 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
2333 sampling phases: 7 ADC clock cycles */
2334 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \
2335 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
2336 sampling phases: 8 ADC clock cycles */
2337 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3) /*!< ADC multimode delay between two
2338 sampling phases: 9 ADC clock cycles */
2339 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
2340 sampling phases: 10 ADC clock cycles */
2341 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
2342 sampling phases: 11 ADC clock cycles */
2343 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \
2344 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
2345 sampling phases: 12 ADC clock cycles */
2346 /**
2347 * @}
2348 */
2349
2350 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
2351 * @{
2352 */
2353 #define LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
2354 instances: ADC master */
2355 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC
2356 instances: ADC slave */
2357 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \
2358 | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
2359 instances: both ADC master and ADC slave */
2360 /**
2361 * @}
2362 */
2363
2364 #endif /* ADC_MULTIMODE_SUPPORT */
2365
2366 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
2367 * @{
2368 */
2369 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
2370 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
2371 calibration parameters. This value is coded on 16 bits
2372 (to fit on signed word or double word) and corresponds
2373 to an inconsistent temperature value. */
2374 /**
2375 * @}
2376 */
2377
2378 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
2379 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
2380 * not timeout values.
2381 * For details on delays values, refer to descriptions in source code
2382 * above each literal definition.
2383 * @{
2384 */
2385
2386 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
2387 /* not timeout values. */
2388 /* Timeout values for ADC operations are dependent to device clock */
2389 /* configuration (system clock versus ADC clock), */
2390 /* and therefore must be defined in user application. */
2391 /* Indications for estimation of ADC timeout delays, for this */
2392 /* STM32 series: */
2393 /* - ADC calibration time: maximum delay is 112/fADC. */
2394 /* (refer to device datasheet, parameter "tCAL") */
2395 /* - ADC enable time: maximum delay is 1 conversion cycle. */
2396 /* (refer to device datasheet, parameter "tSTAB") */
2397 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
2398 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
2399 /* cycles */
2400 /* - ADC conversion time: duration depending on ADC clock and ADC */
2401 /* configuration. */
2402 /* (refer to device reference manual, section "Timing") */
2403
2404 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
2405 /* Delay set to maximum value (refer to device datasheet, */
2406 /* parameter "tADCVREG_STUP"). */
2407 /* Unit: us */
2408 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage
2409 regulator start-up time) */
2410
2411 /* Delay for internal voltage reference stabilization time. */
2412 /* Delay set to maximum value (refer to device datasheet, */
2413 /* parameter "tstart_vrefint"). */
2414 /* Unit: us */
2415 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
2416 time */
2417
2418 /* Delay for temperature sensor stabilization time. */
2419 /* Literal set to maximum value (refer to device datasheet, */
2420 /* parameter "tSTART"). */
2421 /* Unit: us */
2422 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
2423 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization
2424 time (starting from ADC enable, refer to
2425 @ref LL_ADC_Enable()) */
2426
2427 /* Delay required between ADC end of calibration and ADC enable. */
2428 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
2429 /* are required between ADC end of calibration and ADC enable. */
2430 /* Wait time can be computed in user application by waiting for the */
2431 /* equivalent number of CPU cycles, by taking into account */
2432 /* ratio of CPU clock versus ADC clock prescalers. */
2433 /* Unit: ADC clock cycles. */
2434 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration
2435 and ADC enable */
2436
2437 /**
2438 * @}
2439 */
2440
2441 /**
2442 * @}
2443 */
2444
2445
2446 /* Exported macro ------------------------------------------------------------*/
2447 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
2448 * @{
2449 */
2450
2451 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
2452 * @{
2453 */
2454
2455 /**
2456 * @brief Write a value in ADC register
2457 * @param __INSTANCE__ ADC Instance
2458 * @param __REG__ Register to be written
2459 * @param __VALUE__ Value to be written in the register
2460 * @retval None
2461 */
2462 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2463
2464 /**
2465 * @brief Read a value in ADC register
2466 * @param __INSTANCE__ ADC Instance
2467 * @param __REG__ Register to be read
2468 * @retval Register value
2469 */
2470 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2471 /**
2472 * @}
2473 */
2474
2475 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
2476 * @{
2477 */
2478
2479 /**
2480 * @brief Helper macro to get ADC channel number in decimal format
2481 * from literals LL_ADC_CHANNEL_x.
2482 * @note Example:
2483 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
2484 * will return decimal number "4".
2485 * @note The input can be a value from functions where a channel
2486 * number is returned, either defined with number
2487 * or with bitfield (only one bit must be set).
2488 * @param __CHANNEL__ This parameter can be one of the following values:
2489 * @arg @ref LL_ADC_CHANNEL_0
2490 * @arg @ref LL_ADC_CHANNEL_1 (8)
2491 * @arg @ref LL_ADC_CHANNEL_2 (8)
2492 * @arg @ref LL_ADC_CHANNEL_3 (8)
2493 * @arg @ref LL_ADC_CHANNEL_4 (8)
2494 * @arg @ref LL_ADC_CHANNEL_5 (8)
2495 * @arg @ref LL_ADC_CHANNEL_6
2496 * @arg @ref LL_ADC_CHANNEL_7
2497 * @arg @ref LL_ADC_CHANNEL_8
2498 * @arg @ref LL_ADC_CHANNEL_9
2499 * @arg @ref LL_ADC_CHANNEL_10
2500 * @arg @ref LL_ADC_CHANNEL_11
2501 * @arg @ref LL_ADC_CHANNEL_12
2502 * @arg @ref LL_ADC_CHANNEL_13
2503 * @arg @ref LL_ADC_CHANNEL_14
2504 * @arg @ref LL_ADC_CHANNEL_15
2505 * @arg @ref LL_ADC_CHANNEL_16
2506 * @arg @ref LL_ADC_CHANNEL_17
2507 * @arg @ref LL_ADC_CHANNEL_18
2508 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
2509 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
2510 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
2511 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
2512 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
2513 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
2514 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
2515 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
2516 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
2517 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
2518 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
2519 *
2520 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
2521 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
2522 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
2523 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
2524 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
2525 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
2526 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
2527 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
2528 * for more details.
2529 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
2530 * convert in 12-bit resolution.
2531 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
2532 * (fADC) to convert in 12-bit resolution.\n
2533 * @retval Value between Min_Data=0 and Max_Data=18
2534 */
2535 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
2536 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
2537 ( \
2538 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
2539 ) \
2540 : \
2541 ( \
2542 (uint32_t)POSITION_VAL((__CHANNEL__)) \
2543 ) \
2544 )
2545
2546 /**
2547 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
2548 * from number in decimal format.
2549 * @note Example:
2550 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
2551 * will return a data equivalent to "LL_ADC_CHANNEL_4".
2552 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
2553 * @retval Returned value can be one of the following values:
2554 * @arg @ref LL_ADC_CHANNEL_0
2555 * @arg @ref LL_ADC_CHANNEL_1 (8)
2556 * @arg @ref LL_ADC_CHANNEL_2 (8)
2557 * @arg @ref LL_ADC_CHANNEL_3 (8)
2558 * @arg @ref LL_ADC_CHANNEL_4 (8)
2559 * @arg @ref LL_ADC_CHANNEL_5 (8)
2560 * @arg @ref LL_ADC_CHANNEL_6
2561 * @arg @ref LL_ADC_CHANNEL_7
2562 * @arg @ref LL_ADC_CHANNEL_8
2563 * @arg @ref LL_ADC_CHANNEL_9
2564 * @arg @ref LL_ADC_CHANNEL_10
2565 * @arg @ref LL_ADC_CHANNEL_11
2566 * @arg @ref LL_ADC_CHANNEL_12
2567 * @arg @ref LL_ADC_CHANNEL_13
2568 * @arg @ref LL_ADC_CHANNEL_14
2569 * @arg @ref LL_ADC_CHANNEL_15
2570 * @arg @ref LL_ADC_CHANNEL_16
2571 * @arg @ref LL_ADC_CHANNEL_17
2572 * @arg @ref LL_ADC_CHANNEL_18
2573 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
2574 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
2575 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
2576 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
2577 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
2578 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
2579 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
2580 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
2581 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
2582 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
2583 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
2584 *
2585 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
2586 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
2587 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
2588 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
2589 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
2590 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
2591 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
2592 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
2593 * more details.
2594 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
2595 * convert in 12-bit resolution.
2596 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
2597 * (fADC) to convert in 12-bit resolution.\n
2598 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
2599 * comparison with internal channel parameter to be done
2600 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2601 */
2602 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
2603 (((__DECIMAL_NB__) <= 9UL) ? \
2604 ( \
2605 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2606 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2607 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
2608 ) \
2609 : \
2610 ( \
2611 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2612 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2613 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
2614 ) \
2615 )
2616
2617 /**
2618 * @brief Helper macro to determine whether the selected channel
2619 * corresponds to literal definitions of driver.
2620 * @note The different literal definitions of ADC channels are:
2621 * - ADC internal channel:
2622 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
2623 * - ADC external channel (channel connected to a GPIO pin):
2624 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
2625 * @note The channel parameter must be a value defined from literal
2626 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2627 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2628 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
2629 * must not be a value from functions where a channel number is
2630 * returned from ADC registers,
2631 * because internal and external channels share the same channel
2632 * number in ADC registers. The differentiation is made only with
2633 * parameters definitions of driver.
2634 * @param __CHANNEL__ This parameter can be one of the following values:
2635 * @arg @ref LL_ADC_CHANNEL_0
2636 * @arg @ref LL_ADC_CHANNEL_1 (8)
2637 * @arg @ref LL_ADC_CHANNEL_2 (8)
2638 * @arg @ref LL_ADC_CHANNEL_3 (8)
2639 * @arg @ref LL_ADC_CHANNEL_4 (8)
2640 * @arg @ref LL_ADC_CHANNEL_5 (8)
2641 * @arg @ref LL_ADC_CHANNEL_6
2642 * @arg @ref LL_ADC_CHANNEL_7
2643 * @arg @ref LL_ADC_CHANNEL_8
2644 * @arg @ref LL_ADC_CHANNEL_9
2645 * @arg @ref LL_ADC_CHANNEL_10
2646 * @arg @ref LL_ADC_CHANNEL_11
2647 * @arg @ref LL_ADC_CHANNEL_12
2648 * @arg @ref LL_ADC_CHANNEL_13
2649 * @arg @ref LL_ADC_CHANNEL_14
2650 * @arg @ref LL_ADC_CHANNEL_15
2651 * @arg @ref LL_ADC_CHANNEL_16
2652 * @arg @ref LL_ADC_CHANNEL_17
2653 * @arg @ref LL_ADC_CHANNEL_18
2654 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
2655 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
2656 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
2657 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
2658 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
2659 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
2660 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
2661 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
2662 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
2663 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
2664 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
2665 *
2666 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
2667 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
2668 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
2669 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
2670 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
2671 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
2672 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
2673 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
2674 * for more details.
2675 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
2676 * convert in 12-bit resolution.
2677 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
2678 * (fADC) to convert in 12-bit resolution.\n
2679 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
2680 connected to a GPIO pin).
2681 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
2682 */
2683 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
2684 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
2685
2686 /**
2687 * @brief Helper macro to convert a channel defined from parameter
2688 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2689 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2690 * to its equivalent parameter definition of a ADC external channel
2691 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
2692 * @note The channel parameter can be, additionally to a value
2693 * defined from parameter definition of a ADC internal channel
2694 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
2695 * a value defined from parameter definition of
2696 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2697 * or a value from functions where a channel number is returned
2698 * from ADC registers.
2699 * @param __CHANNEL__ This parameter can be one of the following values:
2700 * @arg @ref LL_ADC_CHANNEL_0
2701 * @arg @ref LL_ADC_CHANNEL_1 (8)
2702 * @arg @ref LL_ADC_CHANNEL_2 (8)
2703 * @arg @ref LL_ADC_CHANNEL_3 (8)
2704 * @arg @ref LL_ADC_CHANNEL_4 (8)
2705 * @arg @ref LL_ADC_CHANNEL_5 (8)
2706 * @arg @ref LL_ADC_CHANNEL_6
2707 * @arg @ref LL_ADC_CHANNEL_7
2708 * @arg @ref LL_ADC_CHANNEL_8
2709 * @arg @ref LL_ADC_CHANNEL_9
2710 * @arg @ref LL_ADC_CHANNEL_10
2711 * @arg @ref LL_ADC_CHANNEL_11
2712 * @arg @ref LL_ADC_CHANNEL_12
2713 * @arg @ref LL_ADC_CHANNEL_13
2714 * @arg @ref LL_ADC_CHANNEL_14
2715 * @arg @ref LL_ADC_CHANNEL_15
2716 * @arg @ref LL_ADC_CHANNEL_16
2717 * @arg @ref LL_ADC_CHANNEL_17
2718 * @arg @ref LL_ADC_CHANNEL_18
2719 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
2720 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
2721 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
2722 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
2723 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
2724 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
2725 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
2726 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
2727 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
2728 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
2729 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
2730 *
2731 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
2732 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
2733 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
2734 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
2735 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
2736 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
2737 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
2738 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
2739 * for more details.
2740 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
2741 * convert in 12-bit resolution.
2742 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
2743 * (fADC) to convert in 12-bit resolution.\n
2744 * @retval Returned value can be one of the following values:
2745 * @arg @ref LL_ADC_CHANNEL_0
2746 * @arg @ref LL_ADC_CHANNEL_1
2747 * @arg @ref LL_ADC_CHANNEL_2
2748 * @arg @ref LL_ADC_CHANNEL_3
2749 * @arg @ref LL_ADC_CHANNEL_4
2750 * @arg @ref LL_ADC_CHANNEL_5
2751 * @arg @ref LL_ADC_CHANNEL_6
2752 * @arg @ref LL_ADC_CHANNEL_7
2753 * @arg @ref LL_ADC_CHANNEL_8
2754 * @arg @ref LL_ADC_CHANNEL_9
2755 * @arg @ref LL_ADC_CHANNEL_10
2756 * @arg @ref LL_ADC_CHANNEL_11
2757 * @arg @ref LL_ADC_CHANNEL_12
2758 * @arg @ref LL_ADC_CHANNEL_13
2759 * @arg @ref LL_ADC_CHANNEL_14
2760 * @arg @ref LL_ADC_CHANNEL_15
2761 * @arg @ref LL_ADC_CHANNEL_16
2762 * @arg @ref LL_ADC_CHANNEL_17
2763 * @arg @ref LL_ADC_CHANNEL_18
2764 */
2765 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
2766 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
2767
2768 /**
2769 * @brief Helper macro to determine whether the internal channel
2770 * selected is available on the ADC instance selected.
2771 * @note The channel parameter must be a value defined from parameter
2772 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2773 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2774 * must not be a value defined from parameter definition of
2775 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2776 * or a value from functions where a channel number is
2777 * returned from ADC registers,
2778 * because internal and external channels share the same channel
2779 * number in ADC registers. The differentiation is made only with
2780 * parameters definitions of driver.
2781 * @param __ADC_INSTANCE__ ADC instance
2782 * @param __CHANNEL__ This parameter can be one of the following values:
2783 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
2784 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
2785 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
2786 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
2787 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
2788 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
2789 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
2790 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
2791 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
2792 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
2793 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
2794 *
2795 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
2796 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
2797 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
2798 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
2799 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
2800 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
2801 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
2802 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
2803 * for more details.
2804 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
2805 * Value "1" if the internal channel selected is available on the ADC instance selected.
2806 */
2807 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
2808 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2809 ((((__ADC_INSTANCE__) == ADC1) \
2810 &&( \
2811 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
2812 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
2813 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2814 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
2815 ) \
2816 ) \
2817 || \
2818 (((__ADC_INSTANCE__) == ADC2) \
2819 &&( \
2820 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
2821 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
2822 ) \
2823 ) \
2824 || \
2825 (((__ADC_INSTANCE__) == ADC3) \
2826 &&( \
2827 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
2828 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2829 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
2830 ) \
2831 ) \
2832 || \
2833 (((__ADC_INSTANCE__) == ADC4) \
2834 &&( \
2835 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \
2836 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
2837 ) \
2838 ) \
2839 || \
2840 (((__ADC_INSTANCE__) == ADC5) \
2841 &&( \
2842 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5) || \
2843 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) || \
2844 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) || \
2845 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2846 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
2847 ) \
2848 ) \
2849 )
2850 #elif defined(STM32G471xx)
2851 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2852 ((((__ADC_INSTANCE__) == ADC1) \
2853 &&( \
2854 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
2855 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
2856 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2857 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
2858 ) \
2859 ) \
2860 || \
2861 (((__ADC_INSTANCE__) == ADC2) \
2862 &&( \
2863 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
2864 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
2865 ) \
2866 ) \
2867 || \
2868 (((__ADC_INSTANCE__) == ADC3) \
2869 &&( \
2870 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
2871 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2872 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
2873 ) \
2874 ) \
2875 )
2876 #elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
2877 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2878 ((((__ADC_INSTANCE__) == ADC1) \
2879 &&( \
2880 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
2881 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
2882 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2883 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
2884 ) \
2885 ) \
2886 || \
2887 (((__ADC_INSTANCE__) == ADC2) \
2888 &&( \
2889 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
2890 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
2891 ) \
2892 ) \
2893 )
2894 #elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
2895 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2896 ((((__ADC_INSTANCE__) == ADC1) \
2897 &&( \
2898 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
2899 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
2900 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2901 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
2902 ) \
2903 ) \
2904 || \
2905 (((__ADC_INSTANCE__) == ADC2) \
2906 &&( \
2907 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
2908 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
2909 ) \
2910 ) \
2911 || \
2912 (((__ADC_INSTANCE__) == ADC3) \
2913 &&( \
2914 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
2915 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \
2916 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
2917 ) \
2918 ) \
2919 )
2920 #endif /* STM32G4xx */
2921
2922 /**
2923 * @brief Helper macro to define ADC analog watchdog parameter:
2924 * define a single channel to monitor with analog watchdog
2925 * from sequencer channel and groups definition.
2926 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2927 * Example:
2928 * LL_ADC_SetAnalogWDMonitChannels(
2929 * ADC1, LL_ADC_AWD1,
2930 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
2931 * @param __CHANNEL__ This parameter can be one of the following values:
2932 * @arg @ref LL_ADC_CHANNEL_0
2933 * @arg @ref LL_ADC_CHANNEL_1 (8)
2934 * @arg @ref LL_ADC_CHANNEL_2 (8)
2935 * @arg @ref LL_ADC_CHANNEL_3 (8)
2936 * @arg @ref LL_ADC_CHANNEL_4 (8)
2937 * @arg @ref LL_ADC_CHANNEL_5 (8)
2938 * @arg @ref LL_ADC_CHANNEL_6
2939 * @arg @ref LL_ADC_CHANNEL_7
2940 * @arg @ref LL_ADC_CHANNEL_8
2941 * @arg @ref LL_ADC_CHANNEL_9
2942 * @arg @ref LL_ADC_CHANNEL_10
2943 * @arg @ref LL_ADC_CHANNEL_11
2944 * @arg @ref LL_ADC_CHANNEL_12
2945 * @arg @ref LL_ADC_CHANNEL_13
2946 * @arg @ref LL_ADC_CHANNEL_14
2947 * @arg @ref LL_ADC_CHANNEL_15
2948 * @arg @ref LL_ADC_CHANNEL_16
2949 * @arg @ref LL_ADC_CHANNEL_17
2950 * @arg @ref LL_ADC_CHANNEL_18
2951 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
2952 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
2953 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
2954 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
2955 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
2956 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
2957 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
2958 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
2959 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
2960 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
2961 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
2962 *
2963 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
2964 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
2965 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
2966 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
2967 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
2968 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
2969 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
2970 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
2971 * more details.
2972 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
2973 * convert in 12-bit resolution.
2974 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
2975 * (fADC) to convert in 12-bit resolution.\n
2976 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
2977 * comparison with internal channel parameter to be done
2978 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2979 * @param __GROUP__ This parameter can be one of the following values:
2980 * @arg @ref LL_ADC_GROUP_REGULAR
2981 * @arg @ref LL_ADC_GROUP_INJECTED
2982 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
2983 * @retval Returned value can be one of the following values:
2984 * @arg @ref LL_ADC_AWD_DISABLE
2985 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
2986 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
2987 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
2988 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
2989 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
2990 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
2991 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
2992 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
2993 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
2994 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
2995 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
2996 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
2997 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
2998 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
2999 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3000 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
3001 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
3002 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3003 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
3004 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
3005 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3006 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
3007 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
3008 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3009 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
3010 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
3011 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3012 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
3013 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
3014 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3015 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
3016 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
3017 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3018 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
3019 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
3020 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3021 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
3022 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
3023 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3024 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
3025 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
3026 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3027 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
3028 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
3029 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3030 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
3031 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
3032 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3033 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
3034 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
3035 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3036 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
3037 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
3038 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3039 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
3040 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
3041 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3042 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
3043 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
3044 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3045 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
3046 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
3047 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
3048 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
3049 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
3050 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
3051 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
3052 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
3053 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
3054 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
3055 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
3056 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
3057 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
3058 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
3059 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
3060 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
3061 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
3062 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
3063 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
3064 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
3065 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
3066 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
3067 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
3068 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
3069 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
3070 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
3071 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
3072 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
3073 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
3074 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
3075 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
3076 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
3077 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
3078 *
3079 * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
3080 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
3081 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
3082 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
3083 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
3084 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
3085 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
3086 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
3087 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
3088 * for more details.
3089 */
3090 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
3091 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
3092 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
3093 : \
3094 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
3095 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
3096 : \
3097 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
3098 )
3099
3100 /**
3101 * @brief Helper macro to set the value of ADC analog watchdog threshold high
3102 * or low in function of ADC resolution, when ADC resolution is
3103 * different of 12 bits.
3104 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
3105 * or @ref LL_ADC_SetAnalogWDThresholds().
3106 * Example, with a ADC resolution of 8 bits, to set the value of
3107 * analog watchdog threshold high (on 8 bits):
3108 * LL_ADC_SetAnalogWDThresholds
3109 * (< ADCx param >,
3110 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
3111 * );
3112 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
3113 * @arg @ref LL_ADC_RESOLUTION_12B
3114 * @arg @ref LL_ADC_RESOLUTION_10B
3115 * @arg @ref LL_ADC_RESOLUTION_8B
3116 * @arg @ref LL_ADC_RESOLUTION_6B
3117 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
3118 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3119 */
3120 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
3121 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
3122
3123 /**
3124 * @brief Helper macro to get the value of ADC analog watchdog threshold high
3125 * or low in function of ADC resolution, when ADC resolution is
3126 * different of 12 bits.
3127 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
3128 * Example, with a ADC resolution of 8 bits, to get the value of
3129 * analog watchdog threshold high (on 8 bits):
3130 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
3131 * (LL_ADC_RESOLUTION_8B,
3132 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
3133 * );
3134 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
3135 * @arg @ref LL_ADC_RESOLUTION_12B
3136 * @arg @ref LL_ADC_RESOLUTION_10B
3137 * @arg @ref LL_ADC_RESOLUTION_8B
3138 * @arg @ref LL_ADC_RESOLUTION_6B
3139 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
3140 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3141 */
3142 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
3143 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
3144
3145 /**
3146 * @brief Helper macro to get the ADC analog watchdog threshold high
3147 * or low from raw value containing both thresholds concatenated.
3148 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
3149 * Example, to get analog watchdog threshold high from the register raw value:
3150 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
3151 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
3152 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3153 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3154 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3155 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3156 */
3157 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
3158 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
3159 & LL_ADC_AWD_THRESHOLD_LOW)
3160
3161 /**
3162 * @brief Helper macro to set the ADC calibration value with both single ended
3163 * and differential modes calibration factors concatenated.
3164 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
3165 * Example, to set calibration factors single ended to 0x55
3166 * and differential ended to 0x2A:
3167 * LL_ADC_SetCalibrationFactor(
3168 * ADC1,
3169 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
3170 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
3171 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
3172 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3173 */
3174 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
3175 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
3176
3177 #if defined(ADC_MULTIMODE_SUPPORT)
3178 /**
3179 * @brief Helper macro to get the ADC multimode conversion data of ADC master
3180 * or ADC slave from raw value with both ADC conversion data concatenated.
3181 * @note This macro is intended to be used when multimode transfer by DMA
3182 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
3183 * In this case the transferred data need to processed with this macro
3184 * to separate the conversion data of ADC master and ADC slave.
3185 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
3186 * @arg @ref LL_ADC_MULTI_MASTER
3187 * @arg @ref LL_ADC_MULTI_SLAVE
3188 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
3189 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3190 */
3191 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
3192 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
3193 #endif /* ADC_MULTIMODE_SUPPORT */
3194
3195 #if defined(ADC_MULTIMODE_SUPPORT)
3196 /**
3197 * @brief Helper macro to select, from a ADC instance, to which ADC instance
3198 * it has a dependence in multimode (ADC master of the corresponding
3199 * ADC common instance).
3200 * @note In case of device with multimode available and a mix of
3201 * ADC instances compliant and not compliant with multimode feature,
3202 * ADC instances not compliant with multimode feature are
3203 * considered as master instances (do not depend to
3204 * any other ADC instance).
3205 * @param __ADCx__ ADC instance
3206 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
3207 */
3208 #if defined(ADC5)
3209 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
3210 ( ( ((__ADCx__) == ADC2) \
3211 )? \
3212 (ADC1) \
3213 : \
3214 ( ( ((__ADCx__) == ADC4) \
3215 )? \
3216 (ADC3) \
3217 : \
3218 (__ADCx__) \
3219 ) \
3220 )
3221 #else
3222 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
3223 ( ( ((__ADCx__) == ADC2) \
3224 )? \
3225 (ADC1) \
3226 : \
3227 (__ADCx__) \
3228 )
3229 #endif /* ADC5 */
3230 #endif /* ADC_MULTIMODE_SUPPORT */
3231
3232 /**
3233 * @brief Helper macro to select the ADC common instance
3234 * to which is belonging the selected ADC instance.
3235 * @note ADC common register instance can be used for:
3236 * - Set parameters common to several ADC instances
3237 * - Multimode (for devices with several ADC instances)
3238 * Refer to functions having argument "ADCxy_COMMON" as parameter.
3239 * @param __ADCx__ ADC instance
3240 * @retval ADC common register instance
3241 */
3242 #if defined(ADC345_COMMON)
3243 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
3244 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
3245 ? ( \
3246 (ADC12_COMMON) \
3247 ) \
3248 : \
3249 ( \
3250 (ADC345_COMMON) \
3251 ) \
3252 )
3253 #else
3254 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
3255 #endif /* ADC345_COMMON */
3256 /**
3257 * @brief Helper macro to check if all ADC instances sharing the same
3258 * ADC common instance are disabled.
3259 * @note This check is required by functions with setting conditioned to
3260 * ADC state:
3261 * All ADC instances of the ADC common group must be disabled.
3262 * Refer to functions having argument "ADCxy_COMMON" as parameter.
3263 * @note On devices with only 1 ADC common instance, parameter of this macro
3264 * is useless and can be ignored (parameter kept for compatibility
3265 * with devices featuring several ADC common instances).
3266 * @param __ADCXY_COMMON__ ADC common instance
3267 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3268 * @retval Value "0" if all ADC instances sharing the same ADC common instance
3269 * are disabled.
3270 * Value "1" if at least one ADC instance sharing the same ADC common instance
3271 * is enabled.
3272 */
3273 #if defined(ADC345_COMMON)
3274 #if defined(ADC4) && defined(ADC5)
3275 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
3276 (((__ADCXY_COMMON__) == ADC12_COMMON) \
3277 ? ( \
3278 (LL_ADC_IsEnabled(ADC1) | \
3279 LL_ADC_IsEnabled(ADC2) ) \
3280 ) \
3281 : \
3282 ( \
3283 (LL_ADC_IsEnabled(ADC3) | \
3284 LL_ADC_IsEnabled(ADC4) | \
3285 LL_ADC_IsEnabled(ADC5) ) \
3286 ) \
3287 )
3288 #else
3289 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
3290 (((__ADCXY_COMMON__) == ADC12_COMMON) \
3291 ? ( \
3292 (LL_ADC_IsEnabled(ADC1) | \
3293 LL_ADC_IsEnabled(ADC2) ) \
3294 ) \
3295 : \
3296 (LL_ADC_IsEnabled(ADC3)) \
3297 )
3298 #endif /* ADC4 && ADC5 */
3299 #else
3300 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
3301 (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
3302 #endif /* ADC345_COMMON */
3303
3304 /**
3305 * @brief Helper macro to define the ADC conversion data full-scale digital
3306 * value corresponding to the selected ADC resolution.
3307 * @note ADC conversion data full-scale corresponds to voltage range
3308 * determined by analog voltage references Vref+ and Vref-
3309 * (refer to reference manual).
3310 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
3311 * @arg @ref LL_ADC_RESOLUTION_12B
3312 * @arg @ref LL_ADC_RESOLUTION_10B
3313 * @arg @ref LL_ADC_RESOLUTION_8B
3314 * @arg @ref LL_ADC_RESOLUTION_6B
3315 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
3316 */
3317 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
3318 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
3319
3320 /**
3321 * @brief Helper macro to convert the ADC conversion data from
3322 * a resolution to another resolution.
3323 * @param __DATA__ ADC conversion data to be converted
3324 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
3325 * This parameter can be one of the following values:
3326 * @arg @ref LL_ADC_RESOLUTION_12B
3327 * @arg @ref LL_ADC_RESOLUTION_10B
3328 * @arg @ref LL_ADC_RESOLUTION_8B
3329 * @arg @ref LL_ADC_RESOLUTION_6B
3330 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
3331 * This parameter can be one of the following values:
3332 * @arg @ref LL_ADC_RESOLUTION_12B
3333 * @arg @ref LL_ADC_RESOLUTION_10B
3334 * @arg @ref LL_ADC_RESOLUTION_8B
3335 * @arg @ref LL_ADC_RESOLUTION_6B
3336 * @retval ADC conversion data to the requested resolution
3337 */
3338 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
3339 __ADC_RESOLUTION_CURRENT__,\
3340 __ADC_RESOLUTION_TARGET__) \
3341 (((__DATA__) \
3342 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
3343 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
3344 )
3345
3346 /**
3347 * @brief Helper macro to calculate the voltage (unit: mVolt)
3348 * corresponding to a ADC conversion data (unit: digital value).
3349 * @note Analog reference voltage (Vref+) must be either known from
3350 * user board environment or can be calculated using ADC measurement
3351 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
3352 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
3353 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
3354 * (unit: digital value).
3355 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
3356 * @arg @ref LL_ADC_RESOLUTION_12B
3357 * @arg @ref LL_ADC_RESOLUTION_10B
3358 * @arg @ref LL_ADC_RESOLUTION_8B
3359 * @arg @ref LL_ADC_RESOLUTION_6B
3360 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
3361 */
3362 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
3363 __ADC_DATA__,\
3364 __ADC_RESOLUTION__) \
3365 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
3366 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
3367 )
3368
3369 /**
3370 * @brief Helper macro to calculate the voltage (unit: mVolt)
3371 * corresponding to a ADC conversion data (unit: digital value) in
3372 * differential ended mode.
3373 * @note ADC data from ADC data register is unsigned and centered around
3374 * middle code in. Converted voltage can be positive or negative
3375 * depending on differential input voltages.
3376 * @note Analog reference voltage (Vref+) must be either known from
3377 * user board environment or can be calculated using ADC measurement
3378 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
3379 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
3380 * @param __ADC_DATA__ ADC conversion data (unit: digital value).
3381 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
3382 * @arg @ref LL_ADC_RESOLUTION_12B
3383 * @arg @ref LL_ADC_RESOLUTION_10B
3384 * @arg @ref LL_ADC_RESOLUTION_8B
3385 * @arg @ref LL_ADC_RESOLUTION_6B
3386 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
3387 */
3388 #define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
3389 __ADC_DATA__,\
3390 __ADC_RESOLUTION__)\
3391 ((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\
3392 / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\
3393 - (int32_t)(__VREFANALOG_VOLTAGE__))
3394
3395 /**
3396 * @brief Helper macro to calculate analog reference voltage (Vref+)
3397 * (unit: mVolt) from ADC conversion data of internal voltage
3398 * reference VrefInt.
3399 * @note Computation is using VrefInt calibration value
3400 * stored in system memory for each device during production.
3401 * @note This voltage depends on user board environment: voltage level
3402 * connected to pin Vref+.
3403 * On devices with small package, the pin Vref+ is not present
3404 * and internally bonded to pin Vdda.
3405 * @note On this STM32 series, calibration data of internal voltage reference
3406 * VrefInt corresponds to a resolution of 12 bits,
3407 * this is the recommended ADC resolution to convert voltage of
3408 * internal voltage reference VrefInt.
3409 * Otherwise, this macro performs the processing to scale
3410 * ADC conversion data to 12 bits.
3411 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
3412 * of internal voltage reference VrefInt (unit: digital value).
3413 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
3414 * @arg @ref LL_ADC_RESOLUTION_12B
3415 * @arg @ref LL_ADC_RESOLUTION_10B
3416 * @arg @ref LL_ADC_RESOLUTION_8B
3417 * @arg @ref LL_ADC_RESOLUTION_6B
3418 * @retval Analog reference voltage (unit: mV)
3419 */
3420 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
3421 __ADC_RESOLUTION__) \
3422 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
3423 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
3424 (__ADC_RESOLUTION__), \
3425 LL_ADC_RESOLUTION_12B) \
3426 )
3427
3428 /**
3429 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
3430 * from ADC conversion data of internal temperature sensor.
3431 * @note Computation is using temperature sensor calibration values
3432 * stored in system memory for each device during production.
3433 * @note Calculation formula:
3434 * Temperature = ((TS_ADC_DATA - TS_CAL1)
3435 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
3436 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
3437 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
3438 * Avg_Slope = (TS_CAL2 - TS_CAL1)
3439 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
3440 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
3441 * TEMP_DEGC_CAL1 (calibrated in factory)
3442 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
3443 * TEMP_DEGC_CAL2 (calibrated in factory)
3444 * Caution: Calculation relevancy under reserve that calibration
3445 * parameters are correct (address and data).
3446 * To calculate temperature using temperature sensor
3447 * datasheet typical values (generic values less, therefore
3448 * less accurate than calibrated values),
3449 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
3450 * @note As calculation input, the analog reference voltage (Vref+) must be
3451 * defined as it impacts the ADC LSB equivalent voltage.
3452 * @note Analog reference voltage (Vref+) must be either known from
3453 * user board environment or can be calculated using ADC measurement
3454 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
3455 * @note On this STM32 series, calibration data of temperature sensor
3456 * corresponds to a resolution of 12 bits,
3457 * this is the recommended ADC resolution to convert voltage of
3458 * temperature sensor.
3459 * Otherwise, this macro performs the processing to scale
3460 * ADC conversion data to 12 bits.
3461 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
3462 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
3463 * temperature sensor (unit: digital value).
3464 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
3465 * sensor voltage has been measured.
3466 * This parameter can be one of the following values:
3467 * @arg @ref LL_ADC_RESOLUTION_12B
3468 * @arg @ref LL_ADC_RESOLUTION_10B
3469 * @arg @ref LL_ADC_RESOLUTION_8B
3470 * @arg @ref LL_ADC_RESOLUTION_6B
3471 * @retval Temperature (unit: degree Celsius)
3472 * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
3473 */
3474 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
3475 __TEMPSENSOR_ADC_DATA__,\
3476 __ADC_RESOLUTION__)\
3477 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \
3478 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
3479 (__ADC_RESOLUTION__), \
3480 LL_ADC_RESOLUTION_12B) \
3481 * (__VREFANALOG_VOLTAGE__)) \
3482 / TEMPSENSOR_CAL_VREFANALOG) \
3483 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
3484 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
3485 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
3486 ) + TEMPSENSOR_CAL1_TEMP \
3487 ) \
3488 : \
3489 ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \
3490 )
3491
3492 /**
3493 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
3494 * from ADC conversion data of internal temperature sensor.
3495 * @note Computation is using temperature sensor typical values
3496 * (refer to device datasheet).
3497 * @note Calculation formula:
3498 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
3499 * / Avg_Slope + CALx_TEMP
3500 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
3501 * (unit: digital value)
3502 * Avg_Slope = temperature sensor slope
3503 * (unit: uV/Degree Celsius)
3504 * TS_TYP_CALx_VOLT = temperature sensor digital value at
3505 * temperature CALx_TEMP (unit: mV)
3506 * Caution: Calculation relevancy under reserve the temperature sensor
3507 * of the current device has characteristics in line with
3508 * datasheet typical values.
3509 * If temperature sensor calibration values are available on
3510 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
3511 * temperature calculation will be more accurate using
3512 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
3513 * @note As calculation input, the analog reference voltage (Vref+) must be
3514 * defined as it impacts the ADC LSB equivalent voltage.
3515 * @note Analog reference voltage (Vref+) must be either known from
3516 * user board environment or can be calculated using ADC measurement
3517 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
3518 * @note ADC measurement data must correspond to a resolution of 12 bits
3519 * (full scale digital value 4095). If not the case, the data must be
3520 * preliminarily rescaled to an equivalent resolution of 12 bits.
3521 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
3522 * (unit: uV/DegCelsius).
3523 * On STM32G4, refer to device datasheet parameter "Avg_Slope".
3524 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
3525 * (at temperature and Vref+ defined in parameters below) (unit: mV).
3526 * On STM32G4, refer to datasheet parameter "V30" (corresponding to TS_CAL1).
3527 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
3528 * (see parameter above) is corresponding (unit: mV)
3529 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
3530 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
3531 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
3532 * This parameter can be one of the following values:
3533 * @arg @ref LL_ADC_RESOLUTION_12B
3534 * @arg @ref LL_ADC_RESOLUTION_10B
3535 * @arg @ref LL_ADC_RESOLUTION_8B
3536 * @arg @ref LL_ADC_RESOLUTION_6B
3537 * @retval Temperature (unit: degree Celsius)
3538 */
3539 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
3540 __TEMPSENSOR_TYP_CALX_V__,\
3541 __TEMPSENSOR_CALX_TEMP__,\
3542 __VREFANALOG_VOLTAGE__,\
3543 __TEMPSENSOR_ADC_DATA__,\
3544 __ADC_RESOLUTION__) \
3545 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
3546 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
3547 * 1000UL) \
3548 - \
3549 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
3550 * 1000UL) \
3551 ) \
3552 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
3553 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
3554 )
3555
3556 /**
3557 * @}
3558 */
3559
3560 /**
3561 * @}
3562 */
3563
3564
3565 /* Exported functions --------------------------------------------------------*/
3566 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
3567 * @{
3568 */
3569
3570 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
3571 * @{
3572 */
3573 /* Note: LL ADC functions to set DMA transfer are located into sections of */
3574 /* configuration of ADC instance, groups and multimode (if available): */
3575 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
3576
3577 /**
3578 * @brief Function to help to configure DMA transfer from ADC: retrieve the
3579 * ADC register address from ADC instance and a list of ADC registers
3580 * intended to be used (most commonly) with DMA transfer.
3581 * @note These ADC registers are data registers:
3582 * when ADC conversion data is available in ADC data registers,
3583 * ADC generates a DMA transfer request.
3584 * @note This macro is intended to be used with LL DMA driver, refer to
3585 * function "LL_DMA_ConfigAddresses()".
3586 * Example:
3587 * LL_DMA_ConfigAddresses(DMA1,
3588 * LL_DMA_CHANNEL_1,
3589 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
3590 * (uint32_t)&< array or variable >,
3591 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
3592 * @note For devices with several ADC: in multimode, some devices
3593 * use a different data register outside of ADC instance scope
3594 * (common data register). This macro manages this register difference,
3595 * only ADC instance has to be set as parameter.
3596 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
3597 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
3598 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
3599 * @param ADCx ADC instance
3600 * @param Register This parameter can be one of the following values:
3601 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
3602 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
3603 *
3604 * (1) Available on devices with several ADC instances.
3605 * @retval ADC register address
3606 */
3607 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)3608 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
3609 {
3610 uint32_t data_reg_addr;
3611
3612 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
3613 {
3614 /* Retrieve address of register DR */
3615 data_reg_addr = (uint32_t) &(ADCx->DR);
3616 }
3617 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
3618 {
3619 /* Retrieve address of register CDR */
3620 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
3621 }
3622
3623 return data_reg_addr;
3624 }
3625 #else
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)3626 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
3627 {
3628 /* Prevent unused argument(s) compilation warning */
3629 (void)(Register);
3630
3631 /* Retrieve address of register DR */
3632 return (uint32_t) &(ADCx->DR);
3633 }
3634 #endif /* ADC_MULTIMODE_SUPPORT */
3635
3636 /**
3637 * @}
3638 */
3639
3640 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
3641 * ADC instances
3642 * @{
3643 */
3644
3645 /**
3646 * @brief Set parameter common to several ADC: Clock source and prescaler.
3647 * @note On this STM32 series, if ADC group injected is used, some
3648 * clock ratio constraints between ADC clock and AHB clock
3649 * must be respected.
3650 * Refer to reference manual.
3651 * @note On this STM32 series, setting of this feature is conditioned to
3652 * ADC state:
3653 * All ADC instances of the ADC common group must be disabled.
3654 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3655 * ADC instance or by using helper macro helper macro
3656 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3657 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
3658 * CCR PRESC LL_ADC_SetCommonClock
3659 * @param ADCxy_COMMON ADC common instance
3660 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3661 * @param CommonClock This parameter can be one of the following values:
3662 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
3663 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
3664 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
3665 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
3666 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
3667 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
3668 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
3669 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
3670 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
3671 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
3672 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
3673 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
3674 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
3675 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
3676 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3677 * @retval None
3678 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)3679 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
3680 {
3681 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
3682 }
3683
3684 /**
3685 * @brief Get parameter common to several ADC: Clock source and prescaler.
3686 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
3687 * CCR PRESC LL_ADC_GetCommonClock
3688 * @param ADCxy_COMMON ADC common instance
3689 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3690 * @retval Returned value can be one of the following values:
3691 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
3692 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
3693 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
3694 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
3695 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
3696 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
3697 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
3698 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
3699 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
3700 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
3701 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
3702 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
3703 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
3704 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
3705 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3706 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)3707 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
3708 {
3709 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
3710 }
3711
3712 /**
3713 * @brief Set parameter common to several ADC: measurement path to
3714 * internal channels (VrefInt, temperature sensor, ...).
3715 * Configure all paths (overwrite current configuration).
3716 * @note One or several values can be selected.
3717 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3718 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3719 * The values not selected are removed from configuration.
3720 * @note Stabilization time of measurement path to internal channel:
3721 * After enabling internal paths, before starting ADC conversion,
3722 * a delay is required for internal voltage reference and
3723 * temperature sensor stabilization time.
3724 * Refer to device datasheet.
3725 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3726 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3727 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
3728 * @note ADC internal channel sampling time constraint:
3729 * For ADC conversion of internal channels,
3730 * a sampling time minimum value is required.
3731 * Refer to device datasheet.
3732 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
3733 * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n
3734 * CCR VBATSEL LL_ADC_SetCommonPathInternalCh
3735 * @param ADCxy_COMMON ADC common instance
3736 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3737 * @param PathInternal This parameter can be a combination of the following values:
3738 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3739 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3740 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3741 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3742 * @retval None
3743 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3744 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3745 {
3746 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
3747 }
3748
3749 /**
3750 * @brief Set parameter common to several ADC: measurement path to
3751 * internal channels (VrefInt, temperature sensor, ...).
3752 * Add paths to the current configuration.
3753 * @note One or several values can be selected.
3754 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3755 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3756 * @note Stabilization time of measurement path to internal channel:
3757 * After enabling internal paths, before starting ADC conversion,
3758 * a delay is required for internal voltage reference and
3759 * temperature sensor stabilization time.
3760 * Refer to device datasheet.
3761 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3762 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3763 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
3764 * @note ADC internal channel sampling time constraint:
3765 * For ADC conversion of internal channels,
3766 * a sampling time minimum value is required.
3767 * Refer to device datasheet.
3768 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
3769 * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n
3770 * CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd
3771 * @param ADCxy_COMMON ADC common instance
3772 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3773 * @param PathInternal This parameter can be a combination of the following values:
3774 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3775 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3776 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3777 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3778 * @retval None
3779 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3780 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3781 {
3782 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
3783 }
3784
3785 /**
3786 * @brief Set parameter common to several ADC: measurement path to
3787 * internal channels (VrefInt, temperature sensor, ...).
3788 * Remove paths to the current configuration.
3789 * @note One or several values can be selected.
3790 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3791 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3792 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
3793 * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n
3794 * CCR VBATSEL LL_ADC_SetCommonPathInternalChRem
3795 * @param ADCxy_COMMON ADC common instance
3796 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3797 * @param PathInternal This parameter can be a combination of the following values:
3798 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3799 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3800 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3801 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3802 * @retval None
3803 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3804 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3805 {
3806 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
3807 }
3808
3809 /**
3810 * @brief Get parameter common to several ADC: measurement path to internal
3811 * channels (VrefInt, temperature sensor, ...).
3812 * @note One or several values can be selected.
3813 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3814 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3815 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
3816 * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n
3817 * CCR VBATSEL LL_ADC_GetCommonPathInternalCh
3818 * @param ADCxy_COMMON ADC common instance
3819 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3820 * @retval Returned value can be a combination of the following values:
3821 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3822 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3823 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3824 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3825 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)3826 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
3827 {
3828 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
3829 }
3830
3831 /**
3832 * @}
3833 */
3834
3835 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
3836 * @{
3837 */
3838
3839 /**
3840 * @brief Set ADC calibration factor in the mode single-ended
3841 * or differential (for devices with differential mode available).
3842 * @note This function is intended to set calibration parameters
3843 * without having to perform a new calibration using
3844 * @ref LL_ADC_StartCalibration().
3845 * @note For devices with differential mode available:
3846 * Calibration of offset is specific to each of
3847 * single-ended and differential modes
3848 * (calibration factor must be specified for each of these
3849 * differential modes, if used afterwards and if the application
3850 * requires their calibration).
3851 * @note In case of setting calibration factors of both modes single ended
3852 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
3853 * both calibration factors must be concatenated.
3854 * To perform this processing, use helper macro
3855 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
3856 * @note On this STM32 series, setting of this feature is conditioned to
3857 * ADC state:
3858 * ADC must be enabled, without calibration on going, without conversion
3859 * on going on group regular.
3860 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
3861 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
3862 * @param ADCx ADC instance
3863 * @param SingleDiff This parameter can be one of the following values:
3864 * @arg @ref LL_ADC_SINGLE_ENDED
3865 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3866 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
3867 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
3868 * @retval None
3869 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)3870 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
3871 {
3872 MODIFY_REG(ADCx->CALFACT,
3873 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
3874 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK)
3875 >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)
3876 & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
3877 }
3878
3879 /**
3880 * @brief Get ADC calibration factor in the mode single-ended
3881 * or differential (for devices with differential mode available).
3882 * @note Calibration factors are set by hardware after performing
3883 * a calibration run using function @ref LL_ADC_StartCalibration().
3884 * @note For devices with differential mode available:
3885 * Calibration of offset is specific to each of
3886 * single-ended and differential modes
3887 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
3888 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
3889 * @param ADCx ADC instance
3890 * @param SingleDiff This parameter can be one of the following values:
3891 * @arg @ref LL_ADC_SINGLE_ENDED
3892 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3893 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
3894 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx,uint32_t SingleDiff)3895 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
3896 {
3897 /* Retrieve bits with position in register depending on parameter */
3898 /* "SingleDiff". */
3899 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
3900 /* containing other bits reserved for other purpose. */
3901 return (uint32_t)(READ_BIT(ADCx->CALFACT,
3902 (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK))
3903 >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
3904 ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
3905 }
3906
3907 /**
3908 * @brief Set ADC resolution.
3909 * Refer to reference manual for alignments formats
3910 * dependencies to ADC resolutions.
3911 * @note On this STM32 series, setting of this feature is conditioned to
3912 * ADC state:
3913 * ADC must be disabled or enabled without conversion on going
3914 * on either groups regular or injected.
3915 * @rmtoll CFGR RES LL_ADC_SetResolution
3916 * @param ADCx ADC instance
3917 * @param Resolution This parameter can be one of the following values:
3918 * @arg @ref LL_ADC_RESOLUTION_12B
3919 * @arg @ref LL_ADC_RESOLUTION_10B
3920 * @arg @ref LL_ADC_RESOLUTION_8B
3921 * @arg @ref LL_ADC_RESOLUTION_6B
3922 * @retval None
3923 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)3924 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
3925 {
3926 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3927 }
3928
3929 /**
3930 * @brief Get ADC resolution.
3931 * Refer to reference manual for alignments formats
3932 * dependencies to ADC resolutions.
3933 * @rmtoll CFGR RES LL_ADC_GetResolution
3934 * @param ADCx ADC instance
3935 * @retval Returned value can be one of the following values:
3936 * @arg @ref LL_ADC_RESOLUTION_12B
3937 * @arg @ref LL_ADC_RESOLUTION_10B
3938 * @arg @ref LL_ADC_RESOLUTION_8B
3939 * @arg @ref LL_ADC_RESOLUTION_6B
3940 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)3941 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
3942 {
3943 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3944 }
3945
3946 /**
3947 * @brief Set ADC conversion data alignment.
3948 * @note Refer to reference manual for alignments formats
3949 * dependencies to ADC resolutions.
3950 * @note On this STM32 series, setting of this feature is conditioned to
3951 * ADC state:
3952 * ADC must be disabled or enabled without conversion on going
3953 * on either groups regular or injected.
3954 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
3955 * @param ADCx ADC instance
3956 * @param DataAlignment This parameter can be one of the following values:
3957 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3958 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3959 * @retval None
3960 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)3961 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
3962 {
3963 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
3964 }
3965
3966 /**
3967 * @brief Get ADC conversion data alignment.
3968 * @note Refer to reference manual for alignments formats
3969 * dependencies to ADC resolutions.
3970 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
3971 * @param ADCx ADC instance
3972 * @retval Returned value can be one of the following values:
3973 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3974 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3975 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)3976 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
3977 {
3978 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
3979 }
3980
3981 /**
3982 * @brief Set ADC low power mode.
3983 * @note Description of ADC low power modes:
3984 * - ADC low power mode "auto wait": Dynamic low power mode,
3985 * ADC conversions occurrences are limited to the minimum necessary
3986 * in order to reduce power consumption.
3987 * New ADC conversion starts only when the previous
3988 * unitary conversion data (for ADC group regular)
3989 * or previous sequence conversions data (for ADC group injected)
3990 * has been retrieved by user software.
3991 * In the meantime, ADC remains idle: does not performs any
3992 * other conversion.
3993 * This mode allows to automatically adapt the ADC conversions
3994 * triggers to the speed of the software that reads the data.
3995 * Moreover, this avoids risk of overrun for low frequency
3996 * applications.
3997 * How to use this low power mode:
3998 * - It is not recommended to use with interruption or DMA
3999 * since these modes have to clear immediately the EOC flag
4000 * (by CPU to free the IRQ pending event or by DMA).
4001 * Auto wait will work but fort a very short time, discarding
4002 * its intended benefit (except specific case of high load of CPU
4003 * or DMA transfers which can justify usage of auto wait).
4004 * - Do use with polling: 1. Start conversion,
4005 * 2. Later on, when conversion data is needed: poll for end of
4006 * conversion to ensure that conversion is completed and
4007 * retrieve ADC conversion data. This will trig another
4008 * ADC conversion start.
4009 * @note With ADC low power mode "auto wait", the ADC conversion data read
4010 * is corresponding to previous ADC conversion start, independently
4011 * of delay during which ADC was idle.
4012 * Therefore, the ADC conversion data may be outdated: does not
4013 * correspond to the current voltage level on the selected
4014 * ADC channel.
4015 * @note On this STM32 series, setting of this feature is conditioned to
4016 * ADC state:
4017 * ADC must be disabled or enabled without conversion on going
4018 * on either groups regular or injected.
4019 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
4020 * @param ADCx ADC instance
4021 * @param LowPowerMode This parameter can be one of the following values:
4022 * @arg @ref LL_ADC_LP_MODE_NONE
4023 * @arg @ref LL_ADC_LP_AUTOWAIT
4024 * @retval None
4025 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)4026 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
4027 {
4028 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
4029 }
4030
4031 /**
4032 * @brief Get ADC low power mode:
4033 * @note Description of ADC low power modes:
4034 * - ADC low power mode "auto wait": Dynamic low power mode,
4035 * ADC conversions occurrences are limited to the minimum necessary
4036 * in order to reduce power consumption.
4037 * New ADC conversion starts only when the previous
4038 * unitary conversion data (for ADC group regular)
4039 * or previous sequence conversions data (for ADC group injected)
4040 * has been retrieved by user software.
4041 * In the meantime, ADC remains idle: does not performs any
4042 * other conversion.
4043 * This mode allows to automatically adapt the ADC conversions
4044 * triggers to the speed of the software that reads the data.
4045 * Moreover, this avoids risk of overrun for low frequency
4046 * applications.
4047 * How to use this low power mode:
4048 * - It is not recommended to use with interruption or DMA
4049 * since these modes have to clear immediately the EOC flag
4050 * (by CPU to free the IRQ pending event or by DMA).
4051 * Auto wait will work but fort a very short time, discarding
4052 * its intended benefit (except specific case of high load of CPU
4053 * or DMA transfers which can justify usage of auto wait).
4054 * - Do use with polling: 1. Start conversion,
4055 * 2. Later on, when conversion data is needed: poll for end of
4056 * conversion to ensure that conversion is completed and
4057 * retrieve ADC conversion data. This will trig another
4058 * ADC conversion start.
4059 * @note With ADC low power mode "auto wait", the ADC conversion data read
4060 * is corresponding to previous ADC conversion start, independently
4061 * of delay during which ADC was idle.
4062 * Therefore, the ADC conversion data may be outdated: does not
4063 * correspond to the current voltage level on the selected
4064 * ADC channel.
4065 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
4066 * @param ADCx ADC instance
4067 * @retval Returned value can be one of the following values:
4068 * @arg @ref LL_ADC_LP_MODE_NONE
4069 * @arg @ref LL_ADC_LP_AUTOWAIT
4070 */
LL_ADC_GetLowPowerMode(const ADC_TypeDef * ADCx)4071 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
4072 {
4073 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
4074 }
4075
4076 /**
4077 * @brief Set ADC selected offset instance 1, 2, 3 or 4.
4078 * @note This function set the 2 items of offset configuration:
4079 * - ADC channel to which the offset programmed will be applied
4080 * (independently of channel mapped on ADC group regular
4081 * or group injected)
4082 * - Offset level (offset to be subtracted from the raw
4083 * converted data).
4084 * @note Caution: Offset format is dependent to ADC resolution:
4085 * offset has to be left-aligned on bit 11, the LSB (right bits)
4086 * are set to 0.
4087 * @note This function enables the offset, by default. It can be forced
4088 * to disable state using function LL_ADC_SetOffsetState().
4089 * @note If a channel is mapped on several offsets numbers, only the offset
4090 * with the lowest value is considered for the subtraction.
4091 * @note On this STM32 series, setting of this feature is conditioned to
4092 * ADC state:
4093 * ADC must be disabled or enabled without conversion on going
4094 * on either groups regular or injected.
4095 * @note On STM32G4, some fast channels are available: fast analog inputs
4096 * coming from GPIO pads (ADC_IN1..5).
4097 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
4098 * OFR1 OFFSET1 LL_ADC_SetOffset\n
4099 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
4100 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
4101 * OFR2 OFFSET2 LL_ADC_SetOffset\n
4102 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
4103 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
4104 * OFR3 OFFSET3 LL_ADC_SetOffset\n
4105 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
4106 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
4107 * OFR4 OFFSET4 LL_ADC_SetOffset\n
4108 * OFR4 OFFSET4_EN LL_ADC_SetOffset
4109 * @param ADCx ADC instance
4110 * @param Offsety This parameter can be one of the following values:
4111 * @arg @ref LL_ADC_OFFSET_1
4112 * @arg @ref LL_ADC_OFFSET_2
4113 * @arg @ref LL_ADC_OFFSET_3
4114 * @arg @ref LL_ADC_OFFSET_4
4115 * @param Channel This parameter can be one of the following values:
4116 * @arg @ref LL_ADC_CHANNEL_0
4117 * @arg @ref LL_ADC_CHANNEL_1 (8)
4118 * @arg @ref LL_ADC_CHANNEL_2 (8)
4119 * @arg @ref LL_ADC_CHANNEL_3 (8)
4120 * @arg @ref LL_ADC_CHANNEL_4 (8)
4121 * @arg @ref LL_ADC_CHANNEL_5 (8)
4122 * @arg @ref LL_ADC_CHANNEL_6
4123 * @arg @ref LL_ADC_CHANNEL_7
4124 * @arg @ref LL_ADC_CHANNEL_8
4125 * @arg @ref LL_ADC_CHANNEL_9
4126 * @arg @ref LL_ADC_CHANNEL_10
4127 * @arg @ref LL_ADC_CHANNEL_11
4128 * @arg @ref LL_ADC_CHANNEL_12
4129 * @arg @ref LL_ADC_CHANNEL_13
4130 * @arg @ref LL_ADC_CHANNEL_14
4131 * @arg @ref LL_ADC_CHANNEL_15
4132 * @arg @ref LL_ADC_CHANNEL_16
4133 * @arg @ref LL_ADC_CHANNEL_17
4134 * @arg @ref LL_ADC_CHANNEL_18
4135 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4136 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4137 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4138 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4139 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4140 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4141 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4142 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4143 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4144 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4145 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4146 *
4147 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4148 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4149 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4150 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4151 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
4152 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
4153 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
4154 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
4155 * for more details.
4156 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
4157 * convert in 12-bit resolution.
4158 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
4159 * (fADC) to convert in 12-bit resolution.\n
4160 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
4161 * @retval None
4162 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)4163 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
4164 {
4165 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
4166
4167 MODIFY_REG(*preg,
4168 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
4169 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
4170 }
4171
4172 /**
4173 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
4174 * Channel to which the offset programmed will be applied
4175 * (independently of channel mapped on ADC group regular
4176 * or group injected)
4177 * @note Usage of the returned channel number:
4178 * - To reinject this channel into another function LL_ADC_xxx:
4179 * the returned channel number is only partly formatted on definition
4180 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4181 * with parts of literals LL_ADC_CHANNEL_x or using
4182 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4183 * Then the selected literal LL_ADC_CHANNEL_x can be used
4184 * as parameter for another function.
4185 * - To get the channel number in decimal format:
4186 * process the returned value with the helper macro
4187 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4188 * @note On STM32G4, some fast channels are available: fast analog inputs
4189 * coming from GPIO pads (ADC_IN1..5).
4190 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
4191 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
4192 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
4193 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
4194 * @param ADCx ADC instance
4195 * @param Offsety This parameter can be one of the following values:
4196 * @arg @ref LL_ADC_OFFSET_1
4197 * @arg @ref LL_ADC_OFFSET_2
4198 * @arg @ref LL_ADC_OFFSET_3
4199 * @arg @ref LL_ADC_OFFSET_4
4200 * @retval Returned value can be one of the following values:
4201 * @arg @ref LL_ADC_CHANNEL_0
4202 * @arg @ref LL_ADC_CHANNEL_1 (8)
4203 * @arg @ref LL_ADC_CHANNEL_2 (8)
4204 * @arg @ref LL_ADC_CHANNEL_3 (8)
4205 * @arg @ref LL_ADC_CHANNEL_4 (8)
4206 * @arg @ref LL_ADC_CHANNEL_5 (8)
4207 * @arg @ref LL_ADC_CHANNEL_6
4208 * @arg @ref LL_ADC_CHANNEL_7
4209 * @arg @ref LL_ADC_CHANNEL_8
4210 * @arg @ref LL_ADC_CHANNEL_9
4211 * @arg @ref LL_ADC_CHANNEL_10
4212 * @arg @ref LL_ADC_CHANNEL_11
4213 * @arg @ref LL_ADC_CHANNEL_12
4214 * @arg @ref LL_ADC_CHANNEL_13
4215 * @arg @ref LL_ADC_CHANNEL_14
4216 * @arg @ref LL_ADC_CHANNEL_15
4217 * @arg @ref LL_ADC_CHANNEL_16
4218 * @arg @ref LL_ADC_CHANNEL_17
4219 * @arg @ref LL_ADC_CHANNEL_18
4220 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4221 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4222 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4223 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4224 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4225 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4226 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4227 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4228 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4229 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4230 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4231 *
4232 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4233 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4234 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4235 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4236 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
4237 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
4238 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
4239 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
4240 * more details.
4241 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
4242 * convert in 12-bit resolution.
4243 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
4244 * (fADC) to convert in 12-bit resolution.\n
4245 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
4246 * comparison with internal channel parameter to be done
4247 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4248 */
LL_ADC_GetOffsetChannel(const ADC_TypeDef * ADCx,uint32_t Offsety)4249 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
4250 {
4251 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
4252
4253 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
4254 }
4255
4256 /**
4257 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
4258 * Offset level (offset to be subtracted from the raw
4259 * converted data).
4260 * @note Caution: Offset format is dependent to ADC resolution:
4261 * offset has to be left-aligned on bit 11, the LSB (right bits)
4262 * are set to 0.
4263 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
4264 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
4265 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
4266 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
4267 * @param ADCx ADC instance
4268 * @param Offsety This parameter can be one of the following values:
4269 * @arg @ref LL_ADC_OFFSET_1
4270 * @arg @ref LL_ADC_OFFSET_2
4271 * @arg @ref LL_ADC_OFFSET_3
4272 * @arg @ref LL_ADC_OFFSET_4
4273 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4274 */
LL_ADC_GetOffsetLevel(const ADC_TypeDef * ADCx,uint32_t Offsety)4275 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
4276 {
4277 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
4278
4279 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
4280 }
4281
4282 /**
4283 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
4284 * force offset state disable or enable
4285 * without modifying offset channel or offset value.
4286 * @note This function should be needed only in case of offset to be
4287 * enabled-disabled dynamically, and should not be needed in other cases:
4288 * function LL_ADC_SetOffset() automatically enables the offset.
4289 * @note On this STM32 series, setting of this feature is conditioned to
4290 * ADC state:
4291 * ADC must be disabled or enabled without conversion on going
4292 * on either groups regular or injected.
4293 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
4294 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
4295 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
4296 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
4297 * @param ADCx ADC instance
4298 * @param Offsety This parameter can be one of the following values:
4299 * @arg @ref LL_ADC_OFFSET_1
4300 * @arg @ref LL_ADC_OFFSET_2
4301 * @arg @ref LL_ADC_OFFSET_3
4302 * @arg @ref LL_ADC_OFFSET_4
4303 * @param OffsetState This parameter can be one of the following values:
4304 * @arg @ref LL_ADC_OFFSET_DISABLE
4305 * @arg @ref LL_ADC_OFFSET_ENABLE
4306 * @retval None
4307 */
LL_ADC_SetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetState)4308 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
4309 {
4310 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
4311
4312 MODIFY_REG(*preg,
4313 ADC_OFR1_OFFSET1_EN,
4314 OffsetState);
4315 }
4316
4317 /**
4318 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
4319 * offset state disabled or enabled.
4320 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
4321 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
4322 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
4323 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
4324 * @param ADCx ADC instance
4325 * @param Offsety This parameter can be one of the following values:
4326 * @arg @ref LL_ADC_OFFSET_1
4327 * @arg @ref LL_ADC_OFFSET_2
4328 * @arg @ref LL_ADC_OFFSET_3
4329 * @arg @ref LL_ADC_OFFSET_4
4330 * @retval Returned value can be one of the following values:
4331 * @arg @ref LL_ADC_OFFSET_DISABLE
4332 * @arg @ref LL_ADC_OFFSET_ENABLE
4333 */
LL_ADC_GetOffsetState(const ADC_TypeDef * ADCx,uint32_t Offsety)4334 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety)
4335 {
4336 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
4337
4338 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
4339 }
4340
4341 /**
4342 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
4343 * choose offset sign.
4344 * @note On this STM32 series, setting of this feature is conditioned to
4345 * ADC state:
4346 * ADC must be disabled or enabled without conversion on going
4347 * on either groups regular or injected.
4348 * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
4349 * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
4350 * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
4351 * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
4352 * @param ADCx ADC instance
4353 * @param Offsety This parameter can be one of the following values:
4354 * @arg @ref LL_ADC_OFFSET_1
4355 * @arg @ref LL_ADC_OFFSET_2
4356 * @arg @ref LL_ADC_OFFSET_3
4357 * @arg @ref LL_ADC_OFFSET_4
4358 * @param OffsetSign This parameter can be one of the following values:
4359 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
4360 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
4361 * @retval None
4362 */
LL_ADC_SetOffsetSign(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSign)4363 __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
4364 {
4365 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
4366
4367 MODIFY_REG(*preg,
4368 ADC_OFR1_OFFSETPOS,
4369 OffsetSign);
4370 }
4371
4372 /**
4373 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
4374 * offset sign if positive or negative.
4375 * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
4376 * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
4377 * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
4378 * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
4379 * @param ADCx ADC instance
4380 * @param Offsety This parameter can be one of the following values:
4381 * @arg @ref LL_ADC_OFFSET_1
4382 * @arg @ref LL_ADC_OFFSET_2
4383 * @arg @ref LL_ADC_OFFSET_3
4384 * @arg @ref LL_ADC_OFFSET_4
4385 * @retval Returned value can be one of the following values:
4386 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
4387 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
4388 */
LL_ADC_GetOffsetSign(const ADC_TypeDef * ADCx,uint32_t Offsety)4389 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety)
4390 {
4391 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
4392
4393 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
4394 }
4395
4396 /**
4397 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
4398 * choose offset saturation mode.
4399 * @note On this STM32 series, setting of this feature is conditioned to
4400 * ADC state:
4401 * ADC must be disabled or enabled without conversion on going
4402 * on either groups regular or injected.
4403 * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n
4404 * OFR2 SATEN LL_ADC_SetOffsetSaturation\n
4405 * OFR3 SATEN LL_ADC_SetOffsetSaturation\n
4406 * OFR4 SATEN LL_ADC_SetOffsetSaturation
4407 * @param ADCx ADC instance
4408 * @param Offsety This parameter can be one of the following values:
4409 * @arg @ref LL_ADC_OFFSET_1
4410 * @arg @ref LL_ADC_OFFSET_2
4411 * @arg @ref LL_ADC_OFFSET_3
4412 * @arg @ref LL_ADC_OFFSET_4
4413 * @param OffsetSaturation This parameter can be one of the following values:
4414 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
4415 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
4416 * @retval None
4417 */
LL_ADC_SetOffsetSaturation(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSaturation)4418 __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
4419 {
4420 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
4421
4422 MODIFY_REG(*preg,
4423 ADC_OFR1_SATEN,
4424 OffsetSaturation);
4425 }
4426
4427 /**
4428 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
4429 * offset saturation if enabled or disabled.
4430 * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n
4431 * OFR2 SATEN LL_ADC_GetOffsetSaturation\n
4432 * OFR3 SATEN LL_ADC_GetOffsetSaturation\n
4433 * OFR4 SATEN LL_ADC_GetOffsetSaturation
4434 * @param ADCx ADC instance
4435 * @param Offsety This parameter can be one of the following values:
4436 * @arg @ref LL_ADC_OFFSET_1
4437 * @arg @ref LL_ADC_OFFSET_2
4438 * @arg @ref LL_ADC_OFFSET_3
4439 * @arg @ref LL_ADC_OFFSET_4
4440 * @retval Returned value can be one of the following values:
4441 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
4442 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
4443 */
LL_ADC_GetOffsetSaturation(const ADC_TypeDef * ADCx,uint32_t Offsety)4444 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
4445 {
4446 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
4447
4448 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN);
4449 }
4450
4451 /**
4452 * @brief Set ADC gain compensation.
4453 * @note This function set the gain compensation coefficient
4454 * that is applied to raw converted data using the formula:
4455 * DATA = DATA(raw) * (gain compensation coef) / 4096
4456 * @note This function enables the gain compensation if given
4457 * coefficient is above 0, otherwise it disables it.
4458 * @note Gain compensation when enabled is applied to all channels.
4459 * @note On this STM32 series, setting of this feature is conditioned to
4460 * ADC state:
4461 * ADC must be disabled or enabled without conversion on going
4462 * on either groups regular or injected.
4463 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n
4464 * CFGR2 GCOMP LL_ADC_SetGainCompensation
4465 * @param ADCx ADC instance
4466 * @param GainCompensation This parameter can be:
4467 * 0 Gain compensation will be disabled and value set to 0
4468 * 1 -> 16393 Gain compensation will be enabled with specified value
4469 * @retval None
4470 */
LL_ADC_SetGainCompensation(ADC_TypeDef * ADCx,uint32_t GainCompensation)4471 __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
4472 {
4473 MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
4474 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos);
4475 }
4476
4477 /**
4478 * @brief Get the ADC gain compensation value
4479 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n
4480 * CFGR2 GCOMP LL_ADC_GetGainCompensation
4481 * @param ADCx ADC instance
4482 * @retval Returned value can be:
4483 * 0 Gain compensation is disabled
4484 * 1 -> 16393 Gain compensation is enabled with returned value
4485 */
LL_ADC_GetGainCompensation(const ADC_TypeDef * ADCx)4486 __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx)
4487 {
4488 return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ?
4489 READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
4490 }
4491
4492 #if defined(ADC_SMPR1_SMPPLUS)
4493 /**
4494 * @brief Set ADC sampling time common configuration impacting
4495 * settings of sampling time channel wise.
4496 * @note On this STM32 series, setting of this feature is conditioned to
4497 * ADC state:
4498 * ADC must be disabled or enabled without conversion on going
4499 * on either groups regular or injected.
4500 * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
4501 * @param ADCx ADC instance
4502 * @param SamplingTimeCommonConfig This parameter can be one of the following values:
4503 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
4504 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
4505 * @retval None
4506 */
LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef * ADCx,uint32_t SamplingTimeCommonConfig)4507 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
4508 {
4509 MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
4510 }
4511
4512 /**
4513 * @brief Get ADC sampling time common configuration impacting
4514 * settings of sampling time channel wise.
4515 * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
4516 * @param ADCx ADC instance
4517 * @retval Returned value can be one of the following values:
4518 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
4519 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
4520 */
LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef * ADCx)4521 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef *ADCx)
4522 {
4523 return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
4524 }
4525 #endif /* ADC_SMPR1_SMPPLUS */
4526
4527 /**
4528 * @}
4529 */
4530
4531 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
4532 * @{
4533 */
4534
4535 /**
4536 * @brief Set ADC group regular conversion trigger source:
4537 * internal (SW start) or from external peripheral (timer event,
4538 * external interrupt line).
4539 * @note On this STM32 series, setting trigger source to external trigger
4540 * also set trigger polarity to rising edge
4541 * (default setting for compatibility with some ADC on other
4542 * STM32 series having this setting set by HW default value).
4543 * In case of need to modify trigger edge, use
4544 * function @ref LL_ADC_REG_SetTriggerEdge().
4545 * @note Availability of parameters of trigger sources from timer
4546 * depends on timers availability on the selected device.
4547 * @note On this STM32 series, setting of this feature is conditioned to
4548 * ADC state:
4549 * ADC must be disabled or enabled without conversion on going
4550 * on group regular.
4551 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
4552 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
4553 * @param ADCx ADC instance
4554 * @param TriggerSource This parameter can be one of the following values:
4555 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
4556 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
4557 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
4558 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
4559 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
4560 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
4561 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
4562 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
4563 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
4564 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
4565 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
4566 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
4567 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
4568 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
4569 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
4570 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
4571 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
4572 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
4573 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
4574 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
4575 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
4576 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
4577 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
4578 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
4579 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
4580 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
4581 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
4582 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
4583 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
4584 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
4585 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
4586 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
4587 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
4588 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
4589 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
4590 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
4591 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
4592 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
4593 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
4594 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
4595 *
4596 * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
4597 * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
4598 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
4599 * more details.
4600 * @retval None
4601 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)4602 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4603 {
4604 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
4605 }
4606
4607 /**
4608 * @brief Get ADC group regular conversion trigger source:
4609 * internal (SW start) or from external peripheral (timer event,
4610 * external interrupt line).
4611 * @note To determine whether group regular trigger source is
4612 * internal (SW start) or external, without detail
4613 * of which peripheral is selected as external trigger,
4614 * (equivalent to
4615 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
4616 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
4617 * @note Availability of parameters of trigger sources from timer
4618 * depends on timers availability on the selected device.
4619 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
4620 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
4621 * @param ADCx ADC instance
4622 * @retval Returned value can be one of the following values:
4623 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
4624 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
4625 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
4626 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
4627 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
4628 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
4629 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
4630 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
4631 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
4632 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
4633 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
4634 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
4635 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
4636 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
4637 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
4638 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
4639 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
4640 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
4641 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
4642 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
4643 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
4644 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
4645 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
4646 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
4647 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
4648 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
4649 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
4650 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
4651 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
4652 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
4653 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
4654 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
4655 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
4656 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
4657 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
4658 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
4659 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
4660 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
4661 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
4662 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
4663 *
4664 * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
4665 * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
4666 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
4667 * more details.
4668 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)4669 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
4670 {
4671 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
4672
4673 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4674 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
4675 uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4676
4677 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
4678 /* to match with triggers literals definition. */
4679 return ((trigger_source
4680 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL)
4681 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN)
4682 );
4683 }
4684
4685 /**
4686 * @brief Get ADC group regular conversion trigger source internal (SW start)
4687 * or external.
4688 * @note In case of group regular trigger source set to external trigger,
4689 * to determine which peripheral is selected as external trigger,
4690 * use function @ref LL_ADC_REG_GetTriggerSource().
4691 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
4692 * @param ADCx ADC instance
4693 * @retval Value "0" if trigger source external trigger
4694 * Value "1" if trigger source SW start.
4695 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)4696 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4697 {
4698 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
4699 }
4700
4701 /**
4702 * @brief Set ADC group regular conversion trigger polarity.
4703 * @note Applicable only for trigger source set to external trigger.
4704 * @note On this STM32 series, setting of this feature is conditioned to
4705 * ADC state:
4706 * ADC must be disabled or enabled without conversion on going
4707 * on group regular.
4708 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
4709 * @param ADCx ADC instance
4710 * @param ExternalTriggerEdge This parameter can be one of the following values:
4711 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4712 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4713 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4714 * @retval None
4715 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4716 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4717 {
4718 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
4719 }
4720
4721 /**
4722 * @brief Get ADC group regular conversion trigger polarity.
4723 * @note Applicable only for trigger source set to external trigger.
4724 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
4725 * @param ADCx ADC instance
4726 * @retval Returned value can be one of the following values:
4727 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4728 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4729 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4730 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)4731 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
4732 {
4733 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
4734 }
4735
4736 /**
4737 * @brief Set ADC sampling mode.
4738 * @note This function set the ADC conversion sampling mode
4739 * @note This mode applies to regular group only.
4740 * @note Set sampling mode is applied to all conversion of regular group.
4741 * @note On this STM32 series, setting of this feature is conditioned to
4742 * ADC state:
4743 * ADC must be disabled or enabled without conversion on going
4744 * on group regular.
4745 * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
4746 * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
4747 * @param ADCx ADC instance
4748 * @param SamplingMode This parameter can be one of the following values:
4749 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
4750 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
4751 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
4752 * @retval None
4753 */
LL_ADC_REG_SetSamplingMode(ADC_TypeDef * ADCx,uint32_t SamplingMode)4754 __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
4755 {
4756 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
4757 }
4758
4759 /**
4760 * @brief Get the ADC sampling mode
4761 * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n
4762 * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
4763 * @param ADCx ADC instance
4764 * @retval Returned value can be one of the following values:
4765 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
4766 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
4767 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
4768 */
LL_ADC_REG_GetSamplingMode(const ADC_TypeDef * ADCx)4769 __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx)
4770 {
4771 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
4772 }
4773
4774 /**
4775 * @brief Set ADC group regular sequencer length and scan direction.
4776 * @note Description of ADC group regular sequencer features:
4777 * - For devices with sequencer fully configurable
4778 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4779 * sequencer length and each rank affectation to a channel
4780 * are configurable.
4781 * This function performs configuration of:
4782 * - Sequence length: Number of ranks in the scan sequence.
4783 * - Sequence direction: Unless specified in parameters, sequencer
4784 * scan direction is forward (from rank 1 to rank n).
4785 * Sequencer ranks are selected using
4786 * function "LL_ADC_REG_SetSequencerRanks()".
4787 * - For devices with sequencer not fully configurable
4788 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4789 * sequencer length and each rank affectation to a channel
4790 * are defined by channel number.
4791 * This function performs configuration of:
4792 * - Sequence length: Number of ranks in the scan sequence is
4793 * defined by number of channels set in the sequence,
4794 * rank of each channel is fixed by channel HW number.
4795 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4796 * - Sequence direction: Unless specified in parameters, sequencer
4797 * scan direction is forward (from lowest channel number to
4798 * highest channel number).
4799 * Sequencer ranks are selected using
4800 * function "LL_ADC_REG_SetSequencerChannels()".
4801 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4802 * ADC conversion on only 1 channel.
4803 * @note On this STM32 series, setting of this feature is conditioned to
4804 * ADC state:
4805 * ADC must be disabled or enabled without conversion on going
4806 * on group regular.
4807 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
4808 * @param ADCx ADC instance
4809 * @param SequencerNbRanks This parameter can be one of the following values:
4810 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4811 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4812 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4813 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4814 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4815 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4816 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4817 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4818 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4819 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4820 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4821 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4822 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4823 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4824 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4825 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4826 * @retval None
4827 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4828 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4829 {
4830 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
4831 }
4832
4833 /**
4834 * @brief Get ADC group regular sequencer length and scan direction.
4835 * @note Description of ADC group regular sequencer features:
4836 * - For devices with sequencer fully configurable
4837 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4838 * sequencer length and each rank affectation to a channel
4839 * are configurable.
4840 * This function retrieves:
4841 * - Sequence length: Number of ranks in the scan sequence.
4842 * - Sequence direction: Unless specified in parameters, sequencer
4843 * scan direction is forward (from rank 1 to rank n).
4844 * Sequencer ranks are selected using
4845 * function "LL_ADC_REG_SetSequencerRanks()".
4846 * - For devices with sequencer not fully configurable
4847 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4848 * sequencer length and each rank affectation to a channel
4849 * are defined by channel number.
4850 * This function retrieves:
4851 * - Sequence length: Number of ranks in the scan sequence is
4852 * defined by number of channels set in the sequence,
4853 * rank of each channel is fixed by channel HW number.
4854 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4855 * - Sequence direction: Unless specified in parameters, sequencer
4856 * scan direction is forward (from lowest channel number to
4857 * highest channel number).
4858 * Sequencer ranks are selected using
4859 * function "LL_ADC_REG_SetSequencerChannels()".
4860 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4861 * ADC conversion on only 1 channel.
4862 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
4863 * @param ADCx ADC instance
4864 * @retval Returned value can be one of the following values:
4865 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4866 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4867 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4868 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4869 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4870 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4871 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4872 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4873 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4874 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4875 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4876 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4877 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4878 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4879 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4880 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4881 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)4882 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
4883 {
4884 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
4885 }
4886
4887 /**
4888 * @brief Set ADC group regular sequencer discontinuous mode:
4889 * sequence subdivided and scan conversions interrupted every selected
4890 * number of ranks.
4891 * @note It is not possible to enable both ADC group regular
4892 * continuous mode and sequencer discontinuous mode.
4893 * @note It is not possible to enable both ADC auto-injected mode
4894 * and ADC group regular sequencer discontinuous mode.
4895 * @note On this STM32 series, setting of this feature is conditioned to
4896 * ADC state:
4897 * ADC must be disabled or enabled without conversion on going
4898 * on group regular.
4899 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
4900 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
4901 * @param ADCx ADC instance
4902 * @param SeqDiscont This parameter can be one of the following values:
4903 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4904 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4905 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4906 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4907 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4908 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4909 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4910 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4911 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4912 * @retval None
4913 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4914 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4915 {
4916 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
4917 }
4918
4919 /**
4920 * @brief Get ADC group regular sequencer discontinuous mode:
4921 * sequence subdivided and scan conversions interrupted every selected
4922 * number of ranks.
4923 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
4924 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
4925 * @param ADCx ADC instance
4926 * @retval Returned value can be one of the following values:
4927 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4928 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4929 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4930 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4931 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4932 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4933 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4934 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4935 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4936 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)4937 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4938 {
4939 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
4940 }
4941
4942 /**
4943 * @brief Set ADC group regular sequence: channel on the selected
4944 * scan sequence rank.
4945 * @note This function performs configuration of:
4946 * - Channels ordering into each rank of scan sequence:
4947 * whatever channel can be placed into whatever rank.
4948 * @note On this STM32 series, ADC group regular sequencer is
4949 * fully configurable: sequencer length and each rank
4950 * affectation to a channel are configurable.
4951 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4952 * @note Depending on devices and packages, some channels may not be available.
4953 * Refer to device datasheet for channels availability.
4954 * @note On this STM32 series, to measure internal channels (VrefInt,
4955 * TempSensor, ...), measurement paths to internal channels must be
4956 * enabled separately.
4957 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4958 * @note On this STM32 series, setting of this feature is conditioned to
4959 * ADC state:
4960 * ADC must be disabled or enabled without conversion on going
4961 * on group regular.
4962 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
4963 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
4964 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
4965 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
4966 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
4967 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
4968 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
4969 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
4970 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
4971 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
4972 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
4973 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
4974 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
4975 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
4976 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
4977 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
4978 * @param ADCx ADC instance
4979 * @param Rank This parameter can be one of the following values:
4980 * @arg @ref LL_ADC_REG_RANK_1
4981 * @arg @ref LL_ADC_REG_RANK_2
4982 * @arg @ref LL_ADC_REG_RANK_3
4983 * @arg @ref LL_ADC_REG_RANK_4
4984 * @arg @ref LL_ADC_REG_RANK_5
4985 * @arg @ref LL_ADC_REG_RANK_6
4986 * @arg @ref LL_ADC_REG_RANK_7
4987 * @arg @ref LL_ADC_REG_RANK_8
4988 * @arg @ref LL_ADC_REG_RANK_9
4989 * @arg @ref LL_ADC_REG_RANK_10
4990 * @arg @ref LL_ADC_REG_RANK_11
4991 * @arg @ref LL_ADC_REG_RANK_12
4992 * @arg @ref LL_ADC_REG_RANK_13
4993 * @arg @ref LL_ADC_REG_RANK_14
4994 * @arg @ref LL_ADC_REG_RANK_15
4995 * @arg @ref LL_ADC_REG_RANK_16
4996 * @param Channel This parameter can be one of the following values:
4997 * @arg @ref LL_ADC_CHANNEL_0
4998 * @arg @ref LL_ADC_CHANNEL_1 (8)
4999 * @arg @ref LL_ADC_CHANNEL_2 (8)
5000 * @arg @ref LL_ADC_CHANNEL_3 (8)
5001 * @arg @ref LL_ADC_CHANNEL_4 (8)
5002 * @arg @ref LL_ADC_CHANNEL_5 (8)
5003 * @arg @ref LL_ADC_CHANNEL_6
5004 * @arg @ref LL_ADC_CHANNEL_7
5005 * @arg @ref LL_ADC_CHANNEL_8
5006 * @arg @ref LL_ADC_CHANNEL_9
5007 * @arg @ref LL_ADC_CHANNEL_10
5008 * @arg @ref LL_ADC_CHANNEL_11
5009 * @arg @ref LL_ADC_CHANNEL_12
5010 * @arg @ref LL_ADC_CHANNEL_13
5011 * @arg @ref LL_ADC_CHANNEL_14
5012 * @arg @ref LL_ADC_CHANNEL_15
5013 * @arg @ref LL_ADC_CHANNEL_16
5014 * @arg @ref LL_ADC_CHANNEL_17
5015 * @arg @ref LL_ADC_CHANNEL_18
5016 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5017 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5018 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5019 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5020 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5021 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5022 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5023 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5024 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5025 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5026 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5027 *
5028 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5029 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5030 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5031 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5032 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5033 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5034 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5035 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
5036 * for more details.
5037 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
5038 * convert in 12-bit resolution.
5039 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
5040 * (fADC) to convert in 12-bit resolution.\n
5041 * @retval None
5042 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)5043 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
5044 {
5045 /* Set bits with content of parameter "Channel" with bits position */
5046 /* in register and register position depending on parameter "Rank". */
5047 /* Parameters "Rank" and "Channel" are used with masks because containing */
5048 /* other bits reserved for other purpose. */
5049 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
5050 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
5051
5052 MODIFY_REG(*preg,
5053 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
5054 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5055 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
5056 }
5057
5058 /**
5059 * @brief Get ADC group regular sequence: channel on the selected
5060 * scan sequence rank.
5061 * @note On this STM32 series, ADC group regular sequencer is
5062 * fully configurable: sequencer length and each rank
5063 * affectation to a channel are configurable.
5064 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
5065 * @note Depending on devices and packages, some channels may not be available.
5066 * Refer to device datasheet for channels availability.
5067 * @note Usage of the returned channel number:
5068 * - To reinject this channel into another function LL_ADC_xxx:
5069 * the returned channel number is only partly formatted on definition
5070 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5071 * with parts of literals LL_ADC_CHANNEL_x or using
5072 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5073 * Then the selected literal LL_ADC_CHANNEL_x can be used
5074 * as parameter for another function.
5075 * - To get the channel number in decimal format:
5076 * process the returned value with the helper macro
5077 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5078 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
5079 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
5080 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
5081 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
5082 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
5083 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
5084 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
5085 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
5086 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
5087 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
5088 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
5089 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
5090 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
5091 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
5092 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
5093 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
5094 * @param ADCx ADC instance
5095 * @param Rank This parameter can be one of the following values:
5096 * @arg @ref LL_ADC_REG_RANK_1
5097 * @arg @ref LL_ADC_REG_RANK_2
5098 * @arg @ref LL_ADC_REG_RANK_3
5099 * @arg @ref LL_ADC_REG_RANK_4
5100 * @arg @ref LL_ADC_REG_RANK_5
5101 * @arg @ref LL_ADC_REG_RANK_6
5102 * @arg @ref LL_ADC_REG_RANK_7
5103 * @arg @ref LL_ADC_REG_RANK_8
5104 * @arg @ref LL_ADC_REG_RANK_9
5105 * @arg @ref LL_ADC_REG_RANK_10
5106 * @arg @ref LL_ADC_REG_RANK_11
5107 * @arg @ref LL_ADC_REG_RANK_12
5108 * @arg @ref LL_ADC_REG_RANK_13
5109 * @arg @ref LL_ADC_REG_RANK_14
5110 * @arg @ref LL_ADC_REG_RANK_15
5111 * @arg @ref LL_ADC_REG_RANK_16
5112 * @retval Returned value can be one of the following values:
5113 * @arg @ref LL_ADC_CHANNEL_0
5114 * @arg @ref LL_ADC_CHANNEL_1 (8)
5115 * @arg @ref LL_ADC_CHANNEL_2 (8)
5116 * @arg @ref LL_ADC_CHANNEL_3 (8)
5117 * @arg @ref LL_ADC_CHANNEL_4 (8)
5118 * @arg @ref LL_ADC_CHANNEL_5 (8)
5119 * @arg @ref LL_ADC_CHANNEL_6
5120 * @arg @ref LL_ADC_CHANNEL_7
5121 * @arg @ref LL_ADC_CHANNEL_8
5122 * @arg @ref LL_ADC_CHANNEL_9
5123 * @arg @ref LL_ADC_CHANNEL_10
5124 * @arg @ref LL_ADC_CHANNEL_11
5125 * @arg @ref LL_ADC_CHANNEL_12
5126 * @arg @ref LL_ADC_CHANNEL_13
5127 * @arg @ref LL_ADC_CHANNEL_14
5128 * @arg @ref LL_ADC_CHANNEL_15
5129 * @arg @ref LL_ADC_CHANNEL_16
5130 * @arg @ref LL_ADC_CHANNEL_17
5131 * @arg @ref LL_ADC_CHANNEL_18
5132 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5133 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5134 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5135 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5136 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5137 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5138 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5139 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5140 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5141 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5142 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5143 *
5144 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5145 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5146 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5147 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5148 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5149 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5150 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5151 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
5152 * more details.
5153 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
5154 * convert in 12-bit resolution.
5155 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
5156 * (fADC) to convert in 12-bit resolution.\n
5157 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
5158 * comparison with internal channel parameter to be done
5159 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
5160 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)5161 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
5162 {
5163 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
5164 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
5165
5166 return (uint32_t)((READ_BIT(*preg,
5167 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
5168 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
5169 );
5170 }
5171
5172 /**
5173 * @brief Set ADC continuous conversion mode on ADC group regular.
5174 * @note Description of ADC continuous conversion mode:
5175 * - single mode: one conversion per trigger
5176 * - continuous mode: after the first trigger, following
5177 * conversions launched successively automatically.
5178 * @note It is not possible to enable both ADC group regular
5179 * continuous mode and sequencer discontinuous mode.
5180 * @note On this STM32 series, setting of this feature is conditioned to
5181 * ADC state:
5182 * ADC must be disabled or enabled without conversion on going
5183 * on group regular.
5184 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
5185 * @param ADCx ADC instance
5186 * @param Continuous This parameter can be one of the following values:
5187 * @arg @ref LL_ADC_REG_CONV_SINGLE
5188 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
5189 * @retval None
5190 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)5191 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
5192 {
5193 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
5194 }
5195
5196 /**
5197 * @brief Get ADC continuous conversion mode on ADC group regular.
5198 * @note Description of ADC continuous conversion mode:
5199 * - single mode: one conversion per trigger
5200 * - continuous mode: after the first trigger, following
5201 * conversions launched successively automatically.
5202 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
5203 * @param ADCx ADC instance
5204 * @retval Returned value can be one of the following values:
5205 * @arg @ref LL_ADC_REG_CONV_SINGLE
5206 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
5207 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)5208 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
5209 {
5210 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
5211 }
5212
5213 /**
5214 * @brief Set ADC group regular conversion data transfer: no transfer or
5215 * transfer by DMA, and DMA requests mode.
5216 * @note If transfer by DMA selected, specifies the DMA requests
5217 * mode:
5218 * - Limited mode (One shot mode): DMA transfer requests are stopped
5219 * when number of DMA data transfers (number of
5220 * ADC conversions) is reached.
5221 * This ADC mode is intended to be used with DMA mode non-circular.
5222 * - Unlimited mode: DMA transfer requests are unlimited,
5223 * whatever number of DMA data transfers (number of
5224 * ADC conversions).
5225 * This ADC mode is intended to be used with DMA mode circular.
5226 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5227 * mode non-circular:
5228 * when DMA transfers size will be reached, DMA will stop transfers of
5229 * ADC conversions data ADC will raise an overrun error
5230 * (overrun flag and interruption if enabled).
5231 * @note For devices with several ADC instances: ADC multimode DMA
5232 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
5233 * @note To configure DMA source address (peripheral address),
5234 * use function @ref LL_ADC_DMA_GetRegAddr().
5235 * @note On this STM32 series, setting of this feature is conditioned to
5236 * ADC state:
5237 * ADC must be disabled or enabled without conversion on going
5238 * on either groups regular or injected.
5239 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
5240 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
5241 * @param ADCx ADC instance
5242 * @param DMATransfer This parameter can be one of the following values:
5243 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
5244 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
5245 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
5246 * @retval None
5247 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)5248 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
5249 {
5250 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
5251 }
5252
5253 /**
5254 * @brief Get ADC group regular conversion data transfer: no transfer or
5255 * transfer by DMA, and DMA requests mode.
5256 * @note If transfer by DMA selected, specifies the DMA requests
5257 * mode:
5258 * - Limited mode (One shot mode): DMA transfer requests are stopped
5259 * when number of DMA data transfers (number of
5260 * ADC conversions) is reached.
5261 * This ADC mode is intended to be used with DMA mode non-circular.
5262 * - Unlimited mode: DMA transfer requests are unlimited,
5263 * whatever number of DMA data transfers (number of
5264 * ADC conversions).
5265 * This ADC mode is intended to be used with DMA mode circular.
5266 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5267 * mode non-circular:
5268 * when DMA transfers size will be reached, DMA will stop transfers of
5269 * ADC conversions data ADC will raise an overrun error
5270 * (overrun flag and interruption if enabled).
5271 * @note For devices with several ADC instances: ADC multimode DMA
5272 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
5273 * @note To configure DMA source address (peripheral address),
5274 * use function @ref LL_ADC_DMA_GetRegAddr().
5275 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
5276 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
5277 * @param ADCx ADC instance
5278 * @retval Returned value can be one of the following values:
5279 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
5280 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
5281 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
5282 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)5283 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
5284 {
5285 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
5286 }
5287
5288 /**
5289 * @brief Set ADC group regular behavior in case of overrun:
5290 * data preserved or overwritten.
5291 * @note Compatibility with devices without feature overrun:
5292 * other devices without this feature have a behavior
5293 * equivalent to data overwritten.
5294 * The default setting of overrun is data preserved.
5295 * Therefore, for compatibility with all devices, parameter
5296 * overrun should be set to data overwritten.
5297 * @note On this STM32 series, setting of this feature is conditioned to
5298 * ADC state:
5299 * ADC must be disabled or enabled without conversion on going
5300 * on group regular.
5301 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
5302 * @param ADCx ADC instance
5303 * @param Overrun This parameter can be one of the following values:
5304 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
5305 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
5306 * @retval None
5307 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)5308 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
5309 {
5310 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
5311 }
5312
5313 /**
5314 * @brief Get ADC group regular behavior in case of overrun:
5315 * data preserved or overwritten.
5316 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
5317 * @param ADCx ADC instance
5318 * @retval Returned value can be one of the following values:
5319 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
5320 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
5321 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)5322 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
5323 {
5324 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
5325 }
5326
5327 /**
5328 * @}
5329 */
5330
5331 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
5332 * @{
5333 */
5334
5335 /**
5336 * @brief Set ADC group injected conversion trigger source:
5337 * internal (SW start) or from external peripheral (timer event,
5338 * external interrupt line).
5339 * @note On this STM32 series, setting trigger source to external trigger
5340 * also set trigger polarity to rising edge
5341 * (default setting for compatibility with some ADC on other
5342 * STM32 series having this setting set by HW default value).
5343 * In case of need to modify trigger edge, use
5344 * function @ref LL_ADC_INJ_SetTriggerEdge().
5345 * @note Availability of parameters of trigger sources from timer
5346 * depends on timers availability on the selected device.
5347 * @note On this STM32 series, setting of this feature is conditioned to
5348 * ADC state:
5349 * ADC must not be disabled. Can be enabled with or without conversion
5350 * on going on either groups regular or injected.
5351 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
5352 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
5353 * @param ADCx ADC instance
5354 * @param TriggerSource This parameter can be one of the following values:
5355 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5356 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5357 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5358 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
5359 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5360 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5361 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
5362 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5363 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
5364 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
5365 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
5366 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
5367 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
5368 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
5369 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5370 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
5371 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
5372 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
5373 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
5374 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
5375 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
5376 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
5377 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
5378 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
5379 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
5380 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
5381 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
5382 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
5383 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
5384 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
5385 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
5386 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
5387 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
5388 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
5389 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
5390 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
5391 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
5392 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
5393 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
5394 *
5395 * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
5396 * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
5397 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
5398 * more details.
5399 * @retval None
5400 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)5401 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
5402 {
5403 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
5404 }
5405
5406 /**
5407 * @brief Get ADC group injected conversion trigger source:
5408 * internal (SW start) or from external peripheral (timer event,
5409 * external interrupt line).
5410 * @note To determine whether group injected trigger source is
5411 * internal (SW start) or external, without detail
5412 * of which peripheral is selected as external trigger,
5413 * (equivalent to
5414 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
5415 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
5416 * @note Availability of parameters of trigger sources from timer
5417 * depends on timers availability on the selected device.
5418 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
5419 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
5420 * @param ADCx ADC instance
5421 * @retval Returned value can be one of the following values:
5422 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5423 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5424 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5425 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
5426 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5427 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5428 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
5429 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5430 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
5431 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
5432 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
5433 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
5434 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
5435 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
5436 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5437 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
5438 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
5439 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
5440 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
5441 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
5442 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
5443 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
5444 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
5445 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
5446 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
5447 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
5448 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
5449 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
5450 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
5451 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
5452 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
5453 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
5454 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
5455 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
5456 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
5457 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
5458 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
5459 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
5460 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
5461 *
5462 * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
5463 * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
5464 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
5465 * more details.
5466 */
LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef * ADCx)5467 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
5468 {
5469 __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
5470
5471 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
5472 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
5473 uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
5474
5475 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
5476 /* to match with triggers literals definition. */
5477 return ((trigger_source
5478 & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
5479 | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
5480 );
5481 }
5482
5483 /**
5484 * @brief Get ADC group injected conversion trigger source internal (SW start)
5485 or external
5486 * @note In case of group injected trigger source set to external trigger,
5487 * to determine which peripheral is selected as external trigger,
5488 * use function @ref LL_ADC_INJ_GetTriggerSource.
5489 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
5490 * @param ADCx ADC instance
5491 * @retval Value "0" if trigger source external trigger
5492 * Value "1" if trigger source SW start.
5493 */
LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)5494 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
5495 {
5496 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
5497 }
5498
5499 /**
5500 * @brief Set ADC group injected conversion trigger polarity.
5501 * Applicable only for trigger source set to external trigger.
5502 * @note On this STM32 series, setting of this feature is conditioned to
5503 * ADC state:
5504 * ADC must not be disabled. Can be enabled with or without conversion
5505 * on going on either groups regular or injected.
5506 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
5507 * @param ADCx ADC instance
5508 * @param ExternalTriggerEdge This parameter can be one of the following values:
5509 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5510 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5511 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5512 * @retval None
5513 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)5514 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
5515 {
5516 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
5517 }
5518
5519 /**
5520 * @brief Get ADC group injected conversion trigger polarity.
5521 * Applicable only for trigger source set to external trigger.
5522 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
5523 * @param ADCx ADC instance
5524 * @retval Returned value can be one of the following values:
5525 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5526 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5527 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5528 */
LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef * ADCx)5529 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
5530 {
5531 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
5532 }
5533
5534 /**
5535 * @brief Set ADC group injected sequencer length and scan direction.
5536 * @note This function performs configuration of:
5537 * - Sequence length: Number of ranks in the scan sequence.
5538 * - Sequence direction: Unless specified in parameters, sequencer
5539 * scan direction is forward (from rank 1 to rank n).
5540 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
5541 * ADC conversion on only 1 channel.
5542 * @note On this STM32 series, setting of this feature is conditioned to
5543 * ADC state:
5544 * ADC must not be disabled. Can be enabled with or without conversion
5545 * on going on either groups regular or injected.
5546 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
5547 * @param ADCx ADC instance
5548 * @param SequencerNbRanks This parameter can be one of the following values:
5549 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5550 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5551 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5552 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5553 * @retval None
5554 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)5555 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
5556 {
5557 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
5558 }
5559
5560 /**
5561 * @brief Get ADC group injected sequencer length and scan direction.
5562 * @note This function retrieves:
5563 * - Sequence length: Number of ranks in the scan sequence.
5564 * - Sequence direction: Unless specified in parameters, sequencer
5565 * scan direction is forward (from rank 1 to rank n).
5566 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
5567 * ADC conversion on only 1 channel.
5568 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
5569 * @param ADCx ADC instance
5570 * @retval Returned value can be one of the following values:
5571 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5572 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5573 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5574 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5575 */
LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef * ADCx)5576 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
5577 {
5578 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
5579 }
5580
5581 /**
5582 * @brief Set ADC group injected sequencer discontinuous mode:
5583 * sequence subdivided and scan conversions interrupted every selected
5584 * number of ranks.
5585 * @note It is not possible to enable both ADC group injected
5586 * auto-injected mode and sequencer discontinuous mode.
5587 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
5588 * @param ADCx ADC instance
5589 * @param SeqDiscont This parameter can be one of the following values:
5590 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
5591 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
5592 * @retval None
5593 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)5594 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
5595 {
5596 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
5597 }
5598
5599 /**
5600 * @brief Get ADC group injected sequencer discontinuous mode:
5601 * sequence subdivided and scan conversions interrupted every selected
5602 * number of ranks.
5603 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
5604 * @param ADCx ADC instance
5605 * @retval Returned value can be one of the following values:
5606 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
5607 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
5608 */
LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef * ADCx)5609 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
5610 {
5611 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
5612 }
5613
5614 /**
5615 * @brief Set ADC group injected sequence: channel on the selected
5616 * sequence rank.
5617 * @note Depending on devices and packages, some channels may not be available.
5618 * Refer to device datasheet for channels availability.
5619 * @note On this STM32 series, to measure internal channels (VrefInt,
5620 * TempSensor, ...), measurement paths to internal channels must be
5621 * enabled separately.
5622 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5623 * @note On STM32G4, some fast channels are available: fast analog inputs
5624 * coming from GPIO pads (ADC_IN1..5).
5625 * @note On this STM32 series, setting of this feature is conditioned to
5626 * ADC state:
5627 * ADC must not be disabled. Can be enabled with or without conversion
5628 * on going on either groups regular or injected.
5629 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
5630 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
5631 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
5632 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
5633 * @param ADCx ADC instance
5634 * @param Rank This parameter can be one of the following values:
5635 * @arg @ref LL_ADC_INJ_RANK_1
5636 * @arg @ref LL_ADC_INJ_RANK_2
5637 * @arg @ref LL_ADC_INJ_RANK_3
5638 * @arg @ref LL_ADC_INJ_RANK_4
5639 * @param Channel This parameter can be one of the following values:
5640 * @arg @ref LL_ADC_CHANNEL_0
5641 * @arg @ref LL_ADC_CHANNEL_1 (8)
5642 * @arg @ref LL_ADC_CHANNEL_2 (8)
5643 * @arg @ref LL_ADC_CHANNEL_3 (8)
5644 * @arg @ref LL_ADC_CHANNEL_4 (8)
5645 * @arg @ref LL_ADC_CHANNEL_5 (8)
5646 * @arg @ref LL_ADC_CHANNEL_6
5647 * @arg @ref LL_ADC_CHANNEL_7
5648 * @arg @ref LL_ADC_CHANNEL_8
5649 * @arg @ref LL_ADC_CHANNEL_9
5650 * @arg @ref LL_ADC_CHANNEL_10
5651 * @arg @ref LL_ADC_CHANNEL_11
5652 * @arg @ref LL_ADC_CHANNEL_12
5653 * @arg @ref LL_ADC_CHANNEL_13
5654 * @arg @ref LL_ADC_CHANNEL_14
5655 * @arg @ref LL_ADC_CHANNEL_15
5656 * @arg @ref LL_ADC_CHANNEL_16
5657 * @arg @ref LL_ADC_CHANNEL_17
5658 * @arg @ref LL_ADC_CHANNEL_18
5659 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5660 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5661 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5662 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5663 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5664 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5665 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5666 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5667 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5668 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5669 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5670 *
5671 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5672 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5673 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5674 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5675 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5676 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5677 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5678 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
5679 * for more details.
5680 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
5681 * convert in 12-bit resolution.
5682 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
5683 * (fADC) to convert in 12-bit resolution.\n
5684 * @retval None
5685 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)5686 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
5687 {
5688 /* Set bits with content of parameter "Channel" with bits position */
5689 /* in register depending on parameter "Rank". */
5690 /* Parameters "Rank" and "Channel" are used with masks because containing */
5691 /* other bits reserved for other purpose. */
5692 MODIFY_REG(ADCx->JSQR,
5693 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5694 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
5695 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5696 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
5697 }
5698
5699 /**
5700 * @brief Get ADC group injected sequence: channel on the selected
5701 * sequence rank.
5702 * @note Depending on devices and packages, some channels may not be available.
5703 * Refer to device datasheet for channels availability.
5704 * @note Usage of the returned channel number:
5705 * - To reinject this channel into another function LL_ADC_xxx:
5706 * the returned channel number is only partly formatted on definition
5707 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5708 * with parts of literals LL_ADC_CHANNEL_x or using
5709 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5710 * Then the selected literal LL_ADC_CHANNEL_x can be used
5711 * as parameter for another function.
5712 * - To get the channel number in decimal format:
5713 * process the returned value with the helper macro
5714 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5715 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
5716 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
5717 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
5718 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
5719 * @param ADCx ADC instance
5720 * @param Rank This parameter can be one of the following values:
5721 * @arg @ref LL_ADC_INJ_RANK_1
5722 * @arg @ref LL_ADC_INJ_RANK_2
5723 * @arg @ref LL_ADC_INJ_RANK_3
5724 * @arg @ref LL_ADC_INJ_RANK_4
5725 * @retval Returned value can be one of the following values:
5726 * @arg @ref LL_ADC_CHANNEL_0
5727 * @arg @ref LL_ADC_CHANNEL_1 (8)
5728 * @arg @ref LL_ADC_CHANNEL_2 (8)
5729 * @arg @ref LL_ADC_CHANNEL_3 (8)
5730 * @arg @ref LL_ADC_CHANNEL_4 (8)
5731 * @arg @ref LL_ADC_CHANNEL_5 (8)
5732 * @arg @ref LL_ADC_CHANNEL_6
5733 * @arg @ref LL_ADC_CHANNEL_7
5734 * @arg @ref LL_ADC_CHANNEL_8
5735 * @arg @ref LL_ADC_CHANNEL_9
5736 * @arg @ref LL_ADC_CHANNEL_10
5737 * @arg @ref LL_ADC_CHANNEL_11
5738 * @arg @ref LL_ADC_CHANNEL_12
5739 * @arg @ref LL_ADC_CHANNEL_13
5740 * @arg @ref LL_ADC_CHANNEL_14
5741 * @arg @ref LL_ADC_CHANNEL_15
5742 * @arg @ref LL_ADC_CHANNEL_16
5743 * @arg @ref LL_ADC_CHANNEL_17
5744 * @arg @ref LL_ADC_CHANNEL_18
5745 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5746 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5747 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5748 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5749 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5750 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5751 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5752 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5753 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5754 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5755 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5756 *
5757 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5758 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5759 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5760 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5761 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5762 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5763 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5764 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
5765 * more details.
5766 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
5767 * convert in 12-bit resolution.
5768 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
5769 * (fADC) to convert in 12-bit resolution.\n
5770 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
5771 * comparison with internal channel parameter to be done
5772 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
5773 */
LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)5774 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
5775 {
5776 return (uint32_t)((READ_BIT(ADCx->JSQR,
5777 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5778 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
5779 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
5780 );
5781 }
5782
5783 /**
5784 * @brief Set ADC group injected conversion trigger:
5785 * independent or from ADC group regular.
5786 * @note This mode can be used to extend number of data registers
5787 * updated after one ADC conversion trigger and with data
5788 * permanently kept (not erased by successive conversions of scan of
5789 * ADC sequencer ranks), up to 5 data registers:
5790 * 1 data register on ADC group regular, 4 data registers
5791 * on ADC group injected.
5792 * @note If ADC group injected injected trigger source is set to an
5793 * external trigger, this feature must be must be set to
5794 * independent trigger.
5795 * ADC group injected automatic trigger is compliant only with
5796 * group injected trigger source set to SW start, without any
5797 * further action on ADC group injected conversion start or stop:
5798 * in this case, ADC group injected is controlled only
5799 * from ADC group regular.
5800 * @note It is not possible to enable both ADC group injected
5801 * auto-injected mode and sequencer discontinuous mode.
5802 * @note On this STM32 series, setting of this feature is conditioned to
5803 * ADC state:
5804 * ADC must be disabled or enabled without conversion on going
5805 * on either groups regular or injected.
5806 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
5807 * @param ADCx ADC instance
5808 * @param TrigAuto This parameter can be one of the following values:
5809 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5810 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5811 * @retval None
5812 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)5813 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
5814 {
5815 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
5816 }
5817
5818 /**
5819 * @brief Get ADC group injected conversion trigger:
5820 * independent or from ADC group regular.
5821 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
5822 * @param ADCx ADC instance
5823 * @retval Returned value can be one of the following values:
5824 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5825 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5826 */
LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef * ADCx)5827 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
5828 {
5829 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
5830 }
5831
5832 /**
5833 * @brief Set ADC group injected contexts queue mode.
5834 * @note A context is a setting of group injected sequencer:
5835 * - group injected trigger
5836 * - sequencer length
5837 * - sequencer ranks
5838 * If contexts queue is disabled:
5839 * - only 1 sequence can be configured
5840 * and is active perpetually.
5841 * If contexts queue is enabled:
5842 * - up to 2 contexts can be queued
5843 * and are checked in and out as a FIFO stack (first-in, first-out).
5844 * - If a new context is set when queues is full, error is triggered
5845 * by interruption "Injected Queue Overflow".
5846 * - Two behaviors are possible when all contexts have been processed:
5847 * the contexts queue can maintain the last context active perpetually
5848 * or can be empty and injected group triggers are disabled.
5849 * - Triggers can be only external (not internal SW start)
5850 * - Caution: The sequence must be fully configured in one time
5851 * (one write of register JSQR makes a check-in of a new context
5852 * into the queue).
5853 * Therefore functions to set separately injected trigger and
5854 * sequencer channels cannot be used, register JSQR must be set
5855 * using function @ref LL_ADC_INJ_ConfigQueueContext().
5856 * @note This parameter can be modified only when no conversion is on going
5857 * on either groups regular or injected.
5858 * @note A modification of the context mode (bit JQDIS) causes the contexts
5859 * queue to be flushed and the register JSQR is cleared.
5860 * @note On this STM32 series, setting of this feature is conditioned to
5861 * ADC state:
5862 * ADC must be disabled or enabled without conversion on going
5863 * on either groups regular or injected.
5864 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
5865 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
5866 * @param ADCx ADC instance
5867 * @param QueueMode This parameter can be one of the following values:
5868 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5869 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5870 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5871 * @retval None
5872 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)5873 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
5874 {
5875 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
5876 }
5877
5878 /**
5879 * @brief Get ADC group injected context queue mode.
5880 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
5881 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
5882 * @param ADCx ADC instance
5883 * @retval Returned value can be one of the following values:
5884 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5885 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5886 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5887 */
LL_ADC_INJ_GetQueueMode(const ADC_TypeDef * ADCx)5888 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx)
5889 {
5890 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
5891 }
5892
5893 /**
5894 * @brief Set one context on ADC group injected that will be checked in
5895 * contexts queue.
5896 * @note A context is a setting of group injected sequencer:
5897 * - group injected trigger
5898 * - sequencer length
5899 * - sequencer ranks
5900 * This function is intended to be used when contexts queue is enabled,
5901 * because the sequence must be fully configured in one time
5902 * (functions to set separately injected trigger and sequencer channels
5903 * cannot be used):
5904 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
5905 * @note In the contexts queue, only the active context can be read.
5906 * The parameters of this function can be read using functions:
5907 * @arg @ref LL_ADC_INJ_GetTriggerSource()
5908 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
5909 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
5910 * @note On this STM32 series, to measure internal channels (VrefInt,
5911 * TempSensor, ...), measurement paths to internal channels must be
5912 * enabled separately.
5913 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5914 * @note On STM32G4, some fast channels are available: fast analog inputs
5915 * coming from GPIO pads (ADC_IN1..5).
5916 * @note On this STM32 series, setting of this feature is conditioned to
5917 * ADC state:
5918 * ADC must not be disabled. Can be enabled with or without conversion
5919 * on going on either groups regular or injected.
5920 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
5921 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
5922 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
5923 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
5924 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
5925 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
5926 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
5927 * @param ADCx ADC instance
5928 * @param TriggerSource This parameter can be one of the following values:
5929 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5930 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5931 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5932 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
5933 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5934 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5935 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
5936 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5937 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
5938 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
5939 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
5940 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
5941 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
5942 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
5943 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5944 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
5945 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
5946 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
5947 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
5948 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
5949 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
5950 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
5951 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
5952 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
5953 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
5954 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
5955 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
5956 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
5957 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
5958 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
5959 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
5960 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
5961 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
5962 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
5963 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
5964 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
5965 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
5966 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
5967 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
5968 *
5969 * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
5970 * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
5971 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
5972 * more details.
5973 * @param ExternalTriggerEdge This parameter can be one of the following values:
5974 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5975 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5976 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5977 *
5978 * Note: This parameter is discarded in case of SW start:
5979 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
5980 * @param SequencerNbRanks This parameter can be one of the following values:
5981 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5982 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5983 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5984 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5985 * @param Rank1_Channel This parameter can be one of the following values:
5986 * @arg @ref LL_ADC_CHANNEL_0
5987 * @arg @ref LL_ADC_CHANNEL_1 (8)
5988 * @arg @ref LL_ADC_CHANNEL_2 (8)
5989 * @arg @ref LL_ADC_CHANNEL_3 (8)
5990 * @arg @ref LL_ADC_CHANNEL_4 (8)
5991 * @arg @ref LL_ADC_CHANNEL_5 (8)
5992 * @arg @ref LL_ADC_CHANNEL_6
5993 * @arg @ref LL_ADC_CHANNEL_7
5994 * @arg @ref LL_ADC_CHANNEL_8
5995 * @arg @ref LL_ADC_CHANNEL_9
5996 * @arg @ref LL_ADC_CHANNEL_10
5997 * @arg @ref LL_ADC_CHANNEL_11
5998 * @arg @ref LL_ADC_CHANNEL_12
5999 * @arg @ref LL_ADC_CHANNEL_13
6000 * @arg @ref LL_ADC_CHANNEL_14
6001 * @arg @ref LL_ADC_CHANNEL_15
6002 * @arg @ref LL_ADC_CHANNEL_16
6003 * @arg @ref LL_ADC_CHANNEL_17
6004 * @arg @ref LL_ADC_CHANNEL_18
6005 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
6006 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
6007 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
6008 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
6009 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
6010 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
6011 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
6012 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
6013 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
6014 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
6015 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
6016 *
6017 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
6018 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
6019 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
6020 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
6021 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
6022 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
6023 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
6024 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
6025 * for more details.
6026 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
6027 * convert in 12-bit resolution.
6028 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
6029 * (fADC) to convert in 12-bit resolution.\n
6030 * @param Rank2_Channel This parameter can be one of the following values:
6031 * @arg @ref LL_ADC_CHANNEL_0
6032 * @arg @ref LL_ADC_CHANNEL_1 (8)
6033 * @arg @ref LL_ADC_CHANNEL_2 (8)
6034 * @arg @ref LL_ADC_CHANNEL_3 (8)
6035 * @arg @ref LL_ADC_CHANNEL_4 (8)
6036 * @arg @ref LL_ADC_CHANNEL_5 (8)
6037 * @arg @ref LL_ADC_CHANNEL_6
6038 * @arg @ref LL_ADC_CHANNEL_7
6039 * @arg @ref LL_ADC_CHANNEL_8
6040 * @arg @ref LL_ADC_CHANNEL_9
6041 * @arg @ref LL_ADC_CHANNEL_10
6042 * @arg @ref LL_ADC_CHANNEL_11
6043 * @arg @ref LL_ADC_CHANNEL_12
6044 * @arg @ref LL_ADC_CHANNEL_13
6045 * @arg @ref LL_ADC_CHANNEL_14
6046 * @arg @ref LL_ADC_CHANNEL_15
6047 * @arg @ref LL_ADC_CHANNEL_16
6048 * @arg @ref LL_ADC_CHANNEL_17
6049 * @arg @ref LL_ADC_CHANNEL_18
6050 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
6051 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
6052 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
6053 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
6054 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
6055 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
6056 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
6057 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
6058 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
6059 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
6060 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
6061 *
6062 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
6063 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
6064 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
6065 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
6066 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
6067 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
6068 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
6069 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
6070 * for more details.
6071 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
6072 * convert in 12-bit resolution.
6073 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
6074 * (fADC) to convert in 12-bit resolution.\n
6075 * @param Rank3_Channel This parameter can be one of the following values:
6076 * @arg @ref LL_ADC_CHANNEL_0
6077 * @arg @ref LL_ADC_CHANNEL_1 (8)
6078 * @arg @ref LL_ADC_CHANNEL_2 (8)
6079 * @arg @ref LL_ADC_CHANNEL_3 (8)
6080 * @arg @ref LL_ADC_CHANNEL_4 (8)
6081 * @arg @ref LL_ADC_CHANNEL_5 (8)
6082 * @arg @ref LL_ADC_CHANNEL_6
6083 * @arg @ref LL_ADC_CHANNEL_7
6084 * @arg @ref LL_ADC_CHANNEL_8
6085 * @arg @ref LL_ADC_CHANNEL_9
6086 * @arg @ref LL_ADC_CHANNEL_10
6087 * @arg @ref LL_ADC_CHANNEL_11
6088 * @arg @ref LL_ADC_CHANNEL_12
6089 * @arg @ref LL_ADC_CHANNEL_13
6090 * @arg @ref LL_ADC_CHANNEL_14
6091 * @arg @ref LL_ADC_CHANNEL_15
6092 * @arg @ref LL_ADC_CHANNEL_16
6093 * @arg @ref LL_ADC_CHANNEL_17
6094 * @arg @ref LL_ADC_CHANNEL_18
6095 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
6096 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
6097 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
6098 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
6099 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
6100 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
6101 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
6102 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
6103 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
6104 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
6105 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
6106 *
6107 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
6108 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
6109 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
6110 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
6111 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
6112 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
6113 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
6114 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
6115 * for more details.
6116 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
6117 * convert in 12-bit resolution.
6118 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
6119 * (fADC) to convert in 12-bit resolution.\n
6120 * @param Rank4_Channel This parameter can be one of the following values:
6121 * @arg @ref LL_ADC_CHANNEL_0
6122 * @arg @ref LL_ADC_CHANNEL_1 (8)
6123 * @arg @ref LL_ADC_CHANNEL_2 (8)
6124 * @arg @ref LL_ADC_CHANNEL_3 (8)
6125 * @arg @ref LL_ADC_CHANNEL_4 (8)
6126 * @arg @ref LL_ADC_CHANNEL_5 (8)
6127 * @arg @ref LL_ADC_CHANNEL_6
6128 * @arg @ref LL_ADC_CHANNEL_7
6129 * @arg @ref LL_ADC_CHANNEL_8
6130 * @arg @ref LL_ADC_CHANNEL_9
6131 * @arg @ref LL_ADC_CHANNEL_10
6132 * @arg @ref LL_ADC_CHANNEL_11
6133 * @arg @ref LL_ADC_CHANNEL_12
6134 * @arg @ref LL_ADC_CHANNEL_13
6135 * @arg @ref LL_ADC_CHANNEL_14
6136 * @arg @ref LL_ADC_CHANNEL_15
6137 * @arg @ref LL_ADC_CHANNEL_16
6138 * @arg @ref LL_ADC_CHANNEL_17
6139 * @arg @ref LL_ADC_CHANNEL_18
6140 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
6141 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
6142 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
6143 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
6144 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
6145 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
6146 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
6147 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
6148 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
6149 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
6150 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
6151 *
6152 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
6153 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
6154 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
6155 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
6156 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
6157 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
6158 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
6159 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
6160 * for more details.
6161 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
6162 * convert in 12-bit resolution.
6163 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
6164 * (fADC) to convert in 12-bit resolution.\n
6165 * @retval None
6166 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)6167 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
6168 uint32_t TriggerSource,
6169 uint32_t ExternalTriggerEdge,
6170 uint32_t SequencerNbRanks,
6171 uint32_t Rank1_Channel,
6172 uint32_t Rank2_Channel,
6173 uint32_t Rank3_Channel,
6174 uint32_t Rank4_Channel)
6175 {
6176 /* Set bits with content of parameter "Rankx_Channel" with bits position */
6177 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
6178 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
6179 /* because containing other bits reserved for other purpose. */
6180 /* If parameter "TriggerSource" is set to SW start, then parameter */
6181 /* "ExternalTriggerEdge" is discarded. */
6182 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
6183 MODIFY_REG(ADCx->JSQR,
6184 ADC_JSQR_JEXTSEL |
6185 ADC_JSQR_JEXTEN |
6186 ADC_JSQR_JSQ4 |
6187 ADC_JSQR_JSQ3 |
6188 ADC_JSQR_JSQ2 |
6189 ADC_JSQR_JSQ1 |
6190 ADC_JSQR_JL,
6191 (TriggerSource & ADC_JSQR_JEXTSEL) |
6192 (ExternalTriggerEdge * (is_trigger_not_sw)) |
6193 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
6194 << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6195 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
6196 << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6197 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
6198 << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6199 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
6200 << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6201 SequencerNbRanks
6202 );
6203 }
6204
6205 /**
6206 * @}
6207 */
6208
6209 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
6210 * @{
6211 */
6212
6213 /**
6214 * @brief Set sampling time of the selected ADC channel
6215 * Unit: ADC clock cycles.
6216 * @note On this device, sampling time is on channel scope: independently
6217 * of channel mapped on ADC group regular or injected.
6218 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
6219 * converted:
6220 * sampling time constraints must be respected (sampling time can be
6221 * adjusted in function of ADC clock frequency and sampling time
6222 * setting).
6223 * Refer to device datasheet for timings values (parameters TS_vrefint,
6224 * TS_temp, ...).
6225 * @note Conversion time is the addition of sampling time and processing time.
6226 * On this STM32 series, ADC processing time is:
6227 * - 12.5 ADC clock cycles at ADC resolution 12 bits
6228 * - 10.5 ADC clock cycles at ADC resolution 10 bits
6229 * - 8.5 ADC clock cycles at ADC resolution 8 bits
6230 * - 6.5 ADC clock cycles at ADC resolution 6 bits
6231 * @note In case of ADC conversion of internal channel (VrefInt,
6232 * temperature sensor, ...), a sampling time minimum value
6233 * is required.
6234 * Refer to device datasheet.
6235 * @note On this STM32 series, setting of this feature is conditioned to
6236 * ADC state:
6237 * ADC must be disabled or enabled without conversion on going
6238 * on either groups regular or injected.
6239 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
6240 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
6241 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
6242 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
6243 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
6244 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
6245 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
6246 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
6247 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
6248 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
6249 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
6250 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
6251 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
6252 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
6253 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
6254 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
6255 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
6256 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
6257 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
6258 * @param ADCx ADC instance
6259 * @param Channel This parameter can be one of the following values:
6260 * @arg @ref LL_ADC_CHANNEL_0
6261 * @arg @ref LL_ADC_CHANNEL_1 (8)
6262 * @arg @ref LL_ADC_CHANNEL_2 (8)
6263 * @arg @ref LL_ADC_CHANNEL_3 (8)
6264 * @arg @ref LL_ADC_CHANNEL_4 (8)
6265 * @arg @ref LL_ADC_CHANNEL_5 (8)
6266 * @arg @ref LL_ADC_CHANNEL_6
6267 * @arg @ref LL_ADC_CHANNEL_7
6268 * @arg @ref LL_ADC_CHANNEL_8
6269 * @arg @ref LL_ADC_CHANNEL_9
6270 * @arg @ref LL_ADC_CHANNEL_10
6271 * @arg @ref LL_ADC_CHANNEL_11
6272 * @arg @ref LL_ADC_CHANNEL_12
6273 * @arg @ref LL_ADC_CHANNEL_13
6274 * @arg @ref LL_ADC_CHANNEL_14
6275 * @arg @ref LL_ADC_CHANNEL_15
6276 * @arg @ref LL_ADC_CHANNEL_16
6277 * @arg @ref LL_ADC_CHANNEL_17
6278 * @arg @ref LL_ADC_CHANNEL_18
6279 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
6280 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
6281 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
6282 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
6283 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
6284 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
6285 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
6286 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
6287 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
6288 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
6289 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
6290 *
6291 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
6292 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
6293 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
6294 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
6295 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
6296 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
6297 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
6298 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
6299 * for more details.
6300 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
6301 * convert in 12-bit resolution.
6302 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
6303 * (fADC) to convert in 12-bit resolution.\n
6304 * @param SamplingTime This parameter can be one of the following values:
6305 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
6306 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
6307 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
6308 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
6309 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
6310 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
6311 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
6312 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
6313 *
6314 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
6315 * can be replaced by 3.5 ADC clock cycles.
6316 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
6317 * @retval None
6318 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)6319 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
6320 {
6321 /* Set bits with content of parameter "SamplingTime" with bits position */
6322 /* in register and register position depending on parameter "Channel". */
6323 /* Parameter "Channel" is used with masks because containing */
6324 /* other bits reserved for other purpose. */
6325 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
6326 ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
6327
6328 MODIFY_REG(*preg,
6329 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
6330 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
6331 }
6332
6333 /**
6334 * @brief Get sampling time of the selected ADC channel
6335 * Unit: ADC clock cycles.
6336 * @note On this device, sampling time is on channel scope: independently
6337 * of channel mapped on ADC group regular or injected.
6338 * @note Conversion time is the addition of sampling time and processing time.
6339 * On this STM32 series, ADC processing time is:
6340 * - 12.5 ADC clock cycles at ADC resolution 12 bits
6341 * - 10.5 ADC clock cycles at ADC resolution 10 bits
6342 * - 8.5 ADC clock cycles at ADC resolution 8 bits
6343 * - 6.5 ADC clock cycles at ADC resolution 6 bits
6344 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
6345 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
6346 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
6347 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
6348 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
6349 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
6350 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
6351 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
6352 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
6353 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
6354 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
6355 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
6356 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
6357 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
6358 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
6359 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
6360 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
6361 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
6362 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
6363 * @param ADCx ADC instance
6364 * @param Channel This parameter can be one of the following values:
6365 * @arg @ref LL_ADC_CHANNEL_0
6366 * @arg @ref LL_ADC_CHANNEL_1 (8)
6367 * @arg @ref LL_ADC_CHANNEL_2 (8)
6368 * @arg @ref LL_ADC_CHANNEL_3 (8)
6369 * @arg @ref LL_ADC_CHANNEL_4 (8)
6370 * @arg @ref LL_ADC_CHANNEL_5 (8)
6371 * @arg @ref LL_ADC_CHANNEL_6
6372 * @arg @ref LL_ADC_CHANNEL_7
6373 * @arg @ref LL_ADC_CHANNEL_8
6374 * @arg @ref LL_ADC_CHANNEL_9
6375 * @arg @ref LL_ADC_CHANNEL_10
6376 * @arg @ref LL_ADC_CHANNEL_11
6377 * @arg @ref LL_ADC_CHANNEL_12
6378 * @arg @ref LL_ADC_CHANNEL_13
6379 * @arg @ref LL_ADC_CHANNEL_14
6380 * @arg @ref LL_ADC_CHANNEL_15
6381 * @arg @ref LL_ADC_CHANNEL_16
6382 * @arg @ref LL_ADC_CHANNEL_17
6383 * @arg @ref LL_ADC_CHANNEL_18
6384 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
6385 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
6386 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
6387 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
6388 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
6389 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
6390 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
6391 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
6392 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
6393 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
6394 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
6395 *
6396 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
6397 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
6398 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
6399 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
6400 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
6401 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
6402 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
6403 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
6404 * for more details.
6405 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
6406 * convert in 12-bit resolution.
6407 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
6408 * (fADC) to convert in 12-bit resolution.\n
6409 * @retval Returned value can be one of the following values:
6410 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
6411 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
6412 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
6413 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
6414 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
6415 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
6416 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
6417 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
6418 *
6419 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
6420 * can be replaced by 3.5 ADC clock cycles.
6421 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
6422 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)6423 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
6424 {
6425 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK)
6426 >> ADC_SMPRX_REGOFFSET_POS));
6427
6428 return (uint32_t)(READ_BIT(*preg,
6429 ADC_SMPR1_SMP0
6430 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
6431 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
6432 );
6433 }
6434
6435 /**
6436 * @brief Set mode single-ended or differential input of the selected
6437 * ADC channel.
6438 * @note Channel ending is on channel scope: independently of channel mapped
6439 * on ADC group regular or injected.
6440 * In differential mode: Differential measurement is carried out
6441 * between the selected channel 'i' (positive input) and
6442 * channel 'i+1' (negative input). Only channel 'i' has to be
6443 * configured, channel 'i+1' is configured automatically.
6444 * @note Refer to Reference Manual to ensure the selected channel is
6445 * available in differential mode.
6446 * For example, internal channels (VrefInt, TempSensor, ...) are
6447 * not available in differential mode.
6448 * @note When configuring a channel 'i' in differential mode,
6449 * the channel 'i+1' is not usable separately.
6450 * @note On STM32G4, some channels are internally fixed to single-ended inputs
6451 * configuration:
6452 * - ADC1: Channels 12, 15, 16, 17 and 18
6453 * - ADC2: Channels 15, 17 and 18
6454 * - ADC3: Channels 12, 16, 17 and 18 (1)
6455 * - ADC4: Channels 16, 17 and 18 (1)
6456 * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
6457 * (1) ADC3/4/5 are not available on all devices, refer to device datasheet
6458 * for more details.
6459 * @note For ADC channels configured in differential mode, both inputs
6460 * should be biased at (Vref+)/2 +/-200mV.
6461 * (Vref+ is the analog voltage reference)
6462 * @note On this STM32 series, setting of this feature is conditioned to
6463 * ADC state:
6464 * ADC must be ADC disabled.
6465 * @note One or several values can be selected.
6466 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
6467 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
6468 * @param ADCx ADC instance
6469 * @param Channel This parameter can be one of the following values:
6470 * @arg @ref LL_ADC_CHANNEL_1
6471 * @arg @ref LL_ADC_CHANNEL_2
6472 * @arg @ref LL_ADC_CHANNEL_3
6473 * @arg @ref LL_ADC_CHANNEL_4
6474 * @arg @ref LL_ADC_CHANNEL_5
6475 * @arg @ref LL_ADC_CHANNEL_6
6476 * @arg @ref LL_ADC_CHANNEL_7
6477 * @arg @ref LL_ADC_CHANNEL_8
6478 * @arg @ref LL_ADC_CHANNEL_9
6479 * @arg @ref LL_ADC_CHANNEL_10
6480 * @arg @ref LL_ADC_CHANNEL_11
6481 * @arg @ref LL_ADC_CHANNEL_12
6482 * @arg @ref LL_ADC_CHANNEL_13
6483 * @arg @ref LL_ADC_CHANNEL_14
6484 * @arg @ref LL_ADC_CHANNEL_15
6485 * @param SingleDiff This parameter can be a combination of the following values:
6486 * @arg @ref LL_ADC_SINGLE_ENDED
6487 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6488 * @retval None
6489 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)6490 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
6491 {
6492 /* Bits of channels in single or differential mode are set only for */
6493 /* differential mode (for single mode, mask of bits allowed to be set is */
6494 /* shifted out of range of bits of channels in single or differential mode. */
6495 MODIFY_REG(ADCx->DIFSEL,
6496 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
6497 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
6498 & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
6499 }
6500
6501 /**
6502 * @brief Get mode single-ended or differential input of the selected
6503 * ADC channel.
6504 * @note When configuring a channel 'i' in differential mode,
6505 * the channel 'i+1' is not usable separately.
6506 * Therefore, to ensure a channel is configured in single-ended mode,
6507 * the configuration of channel itself and the channel 'i-1' must be
6508 * read back (to ensure that the selected channel channel has not been
6509 * configured in differential mode by the previous channel).
6510 * @note Refer to Reference Manual to ensure the selected channel is
6511 * available in differential mode.
6512 * For example, internal channels (VrefInt, TempSensor, ...) are
6513 * not available in differential mode.
6514 * @note When configuring a channel 'i' in differential mode,
6515 * the channel 'i+1' is not usable separately.
6516 * @note On STM32G4, some channels are internally fixed to single-ended inputs
6517 * configuration:
6518 * - ADC1: Channels 12, 15, 16, 17 and 18
6519 * - ADC2: Channels 15, 17 and 18
6520 * - ADC3: Channels 12, 16, 17 and 18 (1)
6521 * - ADC4: Channels 16, 17 and 18 (1)
6522 * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
6523 * (1) ADC3/4/5 are not available on all devices, refer to device datasheet
6524 * for more details.
6525 * @note One or several values can be selected. In this case, the value
6526 * returned is null if all channels are in single ended-mode.
6527 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
6528 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
6529 * @param ADCx ADC instance
6530 * @param Channel This parameter can be a combination of the following values:
6531 * @arg @ref LL_ADC_CHANNEL_1
6532 * @arg @ref LL_ADC_CHANNEL_2
6533 * @arg @ref LL_ADC_CHANNEL_3
6534 * @arg @ref LL_ADC_CHANNEL_4
6535 * @arg @ref LL_ADC_CHANNEL_5
6536 * @arg @ref LL_ADC_CHANNEL_6
6537 * @arg @ref LL_ADC_CHANNEL_7
6538 * @arg @ref LL_ADC_CHANNEL_8
6539 * @arg @ref LL_ADC_CHANNEL_9
6540 * @arg @ref LL_ADC_CHANNEL_10
6541 * @arg @ref LL_ADC_CHANNEL_11
6542 * @arg @ref LL_ADC_CHANNEL_12
6543 * @arg @ref LL_ADC_CHANNEL_13
6544 * @arg @ref LL_ADC_CHANNEL_14
6545 * @arg @ref LL_ADC_CHANNEL_15
6546 * @retval 0: channel in single-ended mode, else: channel in differential mode
6547 */
LL_ADC_GetChannelSingleDiff(const ADC_TypeDef * ADCx,uint32_t Channel)6548 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
6549 {
6550 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
6551 }
6552
6553 /**
6554 * @}
6555 */
6556
6557 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
6558 * @{
6559 */
6560
6561 /**
6562 * @brief Set ADC analog watchdog monitored channels:
6563 * a single channel, multiple channels or all channels,
6564 * on ADC groups regular and-or injected.
6565 * @note Once monitored channels are selected, analog watchdog
6566 * is enabled.
6567 * @note In case of need to define a single channel to monitor
6568 * with analog watchdog from sequencer channel definition,
6569 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
6570 * @note On this STM32 series, there are 2 kinds of analog watchdog
6571 * instance:
6572 * - AWD standard (instance AWD1):
6573 * - channels monitored: can monitor 1 channel or all channels.
6574 * - groups monitored: ADC groups regular and-or injected.
6575 * - resolution: resolution is not limited (corresponds to
6576 * ADC resolution configured).
6577 * - AWD flexible (instances AWD2, AWD3):
6578 * - channels monitored: flexible on channels monitored, selection is
6579 * channel wise, from from 1 to all channels.
6580 * Specificity of this analog watchdog: Multiple channels can
6581 * be selected. For example:
6582 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6583 * - groups monitored: not selection possible (monitoring on both
6584 * groups regular and injected).
6585 * Channels selected are monitored on groups regular and injected:
6586 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6587 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6588 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6589 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6590 * the 2 LSB are ignored.
6591 * @note On this STM32 series, setting of this feature is conditioned to
6592 * ADC state:
6593 * ADC must be disabled or enabled without conversion on going
6594 * on either groups regular or injected.
6595 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
6596 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
6597 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
6598 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
6599 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
6600 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
6601 * @param ADCx ADC instance
6602 * @param AWDy This parameter can be one of the following values:
6603 * @arg @ref LL_ADC_AWD1
6604 * @arg @ref LL_ADC_AWD2
6605 * @arg @ref LL_ADC_AWD3
6606 * @param AWDChannelGroup This parameter can be one of the following values:
6607 * @arg @ref LL_ADC_AWD_DISABLE
6608 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
6609 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
6610 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
6611 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
6612 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
6613 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
6614 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
6615 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
6616 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
6617 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
6618 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
6619 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
6620 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
6621 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
6622 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
6623 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
6624 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
6625 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
6626 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
6627 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
6628 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
6629 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
6630 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
6631 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
6632 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
6633 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
6634 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
6635 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
6636 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
6637 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
6638 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
6639 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
6640 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
6641 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
6642 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
6643 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
6644 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
6645 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
6646 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
6647 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
6648 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
6649 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
6650 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
6651 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
6652 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
6653 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
6654 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
6655 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
6656 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
6657 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
6658 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
6659 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
6660 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
6661 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
6662 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
6663 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
6664 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
6665 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
6666 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
6667 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
6668 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
6669 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
6670 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
6671 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
6672 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
6673 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
6674 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
6675 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
6676 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
6677 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
6678 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
6679 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
6680 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
6681 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
6682 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
6683 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
6684 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
6685 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
6686 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
6687 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
6688 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
6689 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
6690 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
6691 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
6692 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
6693 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
6694 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
6695 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
6696 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
6697 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
6698 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
6699 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
6700 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
6701 *
6702 * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
6703 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
6704 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
6705 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
6706 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
6707 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
6708 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
6709 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
6710 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
6711 * for more details.
6712 * @retval None
6713 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)6714 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
6715 {
6716 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
6717 /* in register and register position depending on parameter "AWDy". */
6718 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
6719 /* containing other bits reserved for other purpose. */
6720 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
6721 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
6722 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
6723 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
6724
6725 MODIFY_REG(*preg,
6726 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
6727 AWDChannelGroup & AWDy);
6728 }
6729
6730 /**
6731 * @brief Get ADC analog watchdog monitored channel.
6732 * @note Usage of the returned channel number:
6733 * - To reinject this channel into another function LL_ADC_xxx:
6734 * the returned channel number is only partly formatted on definition
6735 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
6736 * with parts of literals LL_ADC_CHANNEL_x or using
6737 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
6738 * Then the selected literal LL_ADC_CHANNEL_x can be used
6739 * as parameter for another function.
6740 * - To get the channel number in decimal format:
6741 * process the returned value with the helper macro
6742 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
6743 * Applicable only when the analog watchdog is set to monitor
6744 * one channel.
6745 * @note On this STM32 series, there are 2 kinds of analog watchdog
6746 * instance:
6747 * - AWD standard (instance AWD1):
6748 * - channels monitored: can monitor 1 channel or all channels.
6749 * - groups monitored: ADC groups regular and-or injected.
6750 * - resolution: resolution is not limited (corresponds to
6751 * ADC resolution configured).
6752 * - AWD flexible (instances AWD2, AWD3):
6753 * - channels monitored: flexible on channels monitored, selection is
6754 * channel wise, from from 1 to all channels.
6755 * Specificity of this analog watchdog: Multiple channels can
6756 * be selected. For example:
6757 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6758 * - groups monitored: not selection possible (monitoring on both
6759 * groups regular and injected).
6760 * Channels selected are monitored on groups regular and injected:
6761 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6762 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6763 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6764 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6765 * the 2 LSB are ignored.
6766 * @note On this STM32 series, setting of this feature is conditioned to
6767 * ADC state:
6768 * ADC must be disabled or enabled without conversion on going
6769 * on either groups regular or injected.
6770 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
6771 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
6772 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
6773 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
6774 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
6775 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
6776 * @param ADCx ADC instance
6777 * @param AWDy This parameter can be one of the following values:
6778 * @arg @ref LL_ADC_AWD1
6779 * @arg @ref LL_ADC_AWD2 (1)
6780 * @arg @ref LL_ADC_AWD3 (1)
6781 *
6782 * (1) On this AWD number, monitored channel can be retrieved
6783 * if only 1 channel is programmed (or none or all channels).
6784 * This function cannot retrieve monitored channel if
6785 * multiple channels are programmed simultaneously
6786 * by bitfield.
6787 * @retval Returned value can be one of the following values:
6788 * @arg @ref LL_ADC_AWD_DISABLE
6789 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
6790 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
6791 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
6792 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
6793 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
6794 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
6795 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
6796 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
6797 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
6798 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
6799 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
6800 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
6801 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
6802 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
6803 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
6804 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
6805 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
6806 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
6807 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
6808 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
6809 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
6810 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
6811 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
6812 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
6813 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
6814 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
6815 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
6816 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
6817 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
6818 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
6819 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
6820 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
6821 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
6822 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
6823 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
6824 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
6825 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
6826 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
6827 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
6828 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
6829 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
6830 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
6831 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
6832 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
6833 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
6834 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
6835 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
6836 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
6837 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
6838 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
6839 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
6840 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
6841 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
6842 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
6843 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
6844 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
6845 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
6846 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
6847 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
6848 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
6849 *
6850 * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.
6851 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)6852 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
6853 {
6854 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
6855 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
6856 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
6857 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
6858
6859 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
6860
6861 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
6862 /* (parameter value LL_ADC_AWD_DISABLE). */
6863 /* Else, the selected AWD is enabled and is monitoring a group of channels */
6864 /* or a single channel. */
6865 if (analog_wd_monit_channels != 0UL)
6866 {
6867 if (AWDy == LL_ADC_AWD1)
6868 {
6869 if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL)
6870 {
6871 /* AWD monitoring a group of channels */
6872 analog_wd_monit_channels = ((analog_wd_monit_channels
6873 | (ADC_AWD_CR23_CHANNEL_MASK)
6874 )
6875 & (~(ADC_CFGR_AWD1CH))
6876 );
6877 }
6878 else
6879 {
6880 /* AWD monitoring a single channel */
6881 analog_wd_monit_channels = (analog_wd_monit_channels
6882 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos))
6883 );
6884 }
6885 }
6886 else
6887 {
6888 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
6889 {
6890 /* AWD monitoring a group of channels */
6891 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
6892 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
6893 );
6894 }
6895 else
6896 {
6897 /* AWD monitoring a single channel */
6898 /* AWD monitoring a group of channels */
6899 analog_wd_monit_channels = (analog_wd_monit_channels
6900 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
6901 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos)
6902 );
6903 }
6904 }
6905 }
6906
6907 return analog_wd_monit_channels;
6908 }
6909
6910 /**
6911 * @brief Set ADC analog watchdog thresholds value of both thresholds
6912 * high and low.
6913 * @note If value of only one threshold high or low must be set,
6914 * use function @ref LL_ADC_SetAnalogWDThresholds().
6915 * @note In case of ADC resolution different of 12 bits,
6916 * analog watchdog thresholds data require a specific shift.
6917 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
6918 * @note On this STM32 series, there are 2 kinds of analog watchdog
6919 * instance:
6920 * - AWD standard (instance AWD1):
6921 * - channels monitored: can monitor 1 channel or all channels.
6922 * - groups monitored: ADC groups regular and-or injected.
6923 * - resolution: resolution is not limited (corresponds to
6924 * ADC resolution configured).
6925 * - AWD flexible (instances AWD2, AWD3):
6926 * - channels monitored: flexible on channels monitored, selection is
6927 * channel wise, from from 1 to all channels.
6928 * Specificity of this analog watchdog: Multiple channels can
6929 * be selected. For example:
6930 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6931 * - groups monitored: not selection possible (monitoring on both
6932 * groups regular and injected).
6933 * Channels selected are monitored on groups regular and injected:
6934 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6935 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6936 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6937 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6938 * the 2 LSB are ignored.
6939 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
6940 * impacted: the comparison of analog watchdog thresholds is done on
6941 * oversampling final computation (after ratio and shift application):
6942 * ADC data register bitfield [15:4] (12 most significant bits).
6943 * Examples:
6944 * - Oversampling ratio and shift selected to have ADC conversion data
6945 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
6946 * ADC analog watchdog thresholds must be divided by 16.
6947 * - Oversampling ratio and shift selected to have ADC conversion data
6948 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
6949 * ADC analog watchdog thresholds must be divided by 4.
6950 * - Oversampling ratio and shift selected to have ADC conversion data
6951 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
6952 * ADC analog watchdog thresholds match directly to ADC data register.
6953 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
6954 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
6955 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
6956 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
6957 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
6958 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
6959 * @param ADCx ADC instance
6960 * @param AWDy This parameter can be one of the following values:
6961 * @arg @ref LL_ADC_AWD1
6962 * @arg @ref LL_ADC_AWD2
6963 * @arg @ref LL_ADC_AWD3
6964 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
6965 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
6966 * @retval None
6967 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)6968 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
6969 uint32_t AWDThresholdLowValue)
6970 {
6971 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
6972 /* position in register and register position depending on parameter */
6973 /* "AWDy". */
6974 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
6975 /* containing other bits reserved for other purpose. */
6976 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6977 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6978
6979 MODIFY_REG(*preg,
6980 ADC_TR1_HT1 | ADC_TR1_LT1,
6981 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
6982 }
6983
6984 /**
6985 * @brief Set ADC analog watchdog threshold value of threshold
6986 * high or low.
6987 * @note If values of both thresholds high or low must be set,
6988 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
6989 * @note In case of ADC resolution different of 12 bits,
6990 * analog watchdog thresholds data require a specific shift.
6991 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
6992 * @note On this STM32 series, there are 2 kinds of analog watchdog
6993 * instance:
6994 * - AWD standard (instance AWD1):
6995 * - channels monitored: can monitor 1 channel or all channels.
6996 * - groups monitored: ADC groups regular and-or injected.
6997 * - resolution: resolution is not limited (corresponds to
6998 * ADC resolution configured).
6999 * - AWD flexible (instances AWD2, AWD3):
7000 * - channels monitored: flexible on channels monitored, selection is
7001 * channel wise, from from 1 to all channels.
7002 * Specificity of this analog watchdog: Multiple channels can
7003 * be selected. For example:
7004 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
7005 * - groups monitored: not selection possible (monitoring on both
7006 * groups regular and injected).
7007 * Channels selected are monitored on groups regular and injected:
7008 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
7009 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
7010 * - resolution: resolution is limited to 8 bits: if ADC resolution is
7011 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
7012 * the 2 LSB are ignored.
7013 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
7014 * impacted: the comparison of analog watchdog thresholds is done on
7015 * oversampling final computation (after ratio and shift application):
7016 * ADC data register bitfield [15:4] (12 most significant bits).
7017 * Examples:
7018 * - Oversampling ratio and shift selected to have ADC conversion data
7019 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
7020 * ADC analog watchdog thresholds must be divided by 16.
7021 * - Oversampling ratio and shift selected to have ADC conversion data
7022 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
7023 * ADC analog watchdog thresholds must be divided by 4.
7024 * - Oversampling ratio and shift selected to have ADC conversion data
7025 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
7026 * ADC analog watchdog thresholds match directly to ADC data register.
7027 * @note On this STM32 series, setting of this feature is not conditioned to
7028 * ADC state:
7029 * ADC can be disabled, enabled with or without conversion on going
7030 * on either ADC groups regular or injected.
7031 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
7032 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
7033 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
7034 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
7035 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
7036 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
7037 * @param ADCx ADC instance
7038 * @param AWDy This parameter can be one of the following values:
7039 * @arg @ref LL_ADC_AWD1
7040 * @arg @ref LL_ADC_AWD2
7041 * @arg @ref LL_ADC_AWD3
7042 * @param AWDThresholdsHighLow This parameter can be one of the following values:
7043 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
7044 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
7045 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
7046 * @retval None
7047 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)7048 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
7049 uint32_t AWDThresholdValue)
7050 {
7051 /* Set bits with content of parameter "AWDThresholdValue" with bits */
7052 /* position in register and register position depending on parameters */
7053 /* "AWDThresholdsHighLow" and "AWDy". */
7054 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
7055 /* containing other bits reserved for other purpose. */
7056 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
7057 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
7058
7059 MODIFY_REG(*preg,
7060 AWDThresholdsHighLow,
7061 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
7062 }
7063
7064 /**
7065 * @brief Get ADC analog watchdog threshold value of threshold high,
7066 * threshold low or raw data with ADC thresholds high and low
7067 * concatenated.
7068 * @note If raw data with ADC thresholds high and low is retrieved,
7069 * the data of each threshold high or low can be isolated
7070 * using helper macro:
7071 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
7072 * @note In case of ADC resolution different of 12 bits,
7073 * analog watchdog thresholds data require a specific shift.
7074 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
7075 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
7076 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
7077 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
7078 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
7079 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
7080 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
7081 * @param ADCx ADC instance
7082 * @param AWDy This parameter can be one of the following values:
7083 * @arg @ref LL_ADC_AWD1
7084 * @arg @ref LL_ADC_AWD2
7085 * @arg @ref LL_ADC_AWD3
7086 * @param AWDThresholdsHighLow This parameter can be one of the following values:
7087 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
7088 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
7089 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
7090 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7091 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)7092 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
7093 uint32_t AWDy, uint32_t AWDThresholdsHighLow)
7094 {
7095 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
7096 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
7097
7098 return (uint32_t)(READ_BIT(*preg,
7099 (AWDThresholdsHighLow | ADC_TR1_LT1))
7100 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
7101 & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
7102 }
7103
7104 /**
7105 * @brief Set ADC analog watchdog filtering configuration
7106 * @note On this STM32 series, setting of this feature is conditioned to
7107 * ADC state:
7108 * ADC must be disabled or enabled without conversion on going
7109 * on either groups regular or injected.
7110 * @note On this STM32 series, this feature is only available on first
7111 * analog watchdog (AWD1)
7112 * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
7113 * @param ADCx ADC instance
7114 * @param AWDy This parameter can be one of the following values:
7115 * @arg @ref LL_ADC_AWD1
7116 * @param FilteringConfig This parameter can be one of the following values:
7117 * @arg @ref LL_ADC_AWD_FILTERING_NONE
7118 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
7119 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
7120 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
7121 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
7122 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
7123 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
7124 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
7125 * @retval None
7126 */
LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t FilteringConfig)7127 __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
7128 {
7129 /* Prevent unused argument(s) compilation warning */
7130 (void)(AWDy);
7131 MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
7132 }
7133
7134 /**
7135 * @brief Get ADC analog watchdog filtering configuration
7136 * @note On this STM32 series, this feature is only available on first
7137 * analog watchdog (AWD1)
7138 * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
7139 * @param ADCx ADC instance
7140 * @param AWDy This parameter can be one of the following values:
7141 * @arg @ref LL_ADC_AWD1
7142 * @retval Returned value can be:
7143 * @arg @ref LL_ADC_AWD_FILTERING_NONE
7144 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
7145 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
7146 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
7147 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
7148 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
7149 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
7150 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
7151 */
LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef * ADCx,uint32_t AWDy)7152 __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy)
7153 {
7154 /* Prevent unused argument(s) compilation warning */
7155 (void)(AWDy);
7156 return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
7157 }
7158
7159 /**
7160 * @}
7161 */
7162
7163 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
7164 * @{
7165 */
7166
7167 /**
7168 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
7169 * (availability of ADC group injected depends on STM32 series).
7170 * @note If both groups regular and injected are selected,
7171 * specify behavior of ADC group injected interrupting
7172 * group regular: when ADC group injected is triggered,
7173 * the oversampling on ADC group regular is either
7174 * temporary stopped and continued, or resumed from start
7175 * (oversampler buffer reset).
7176 * @note On this STM32 series, setting of this feature is conditioned to
7177 * ADC state:
7178 * ADC must be disabled or enabled without conversion on going
7179 * on either groups regular or injected.
7180 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
7181 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
7182 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
7183 * @param ADCx ADC instance
7184 * @param OvsScope This parameter can be one of the following values:
7185 * @arg @ref LL_ADC_OVS_DISABLE
7186 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
7187 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
7188 * @arg @ref LL_ADC_OVS_GRP_INJECTED
7189 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
7190 * @retval None
7191 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)7192 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
7193 {
7194 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
7195 }
7196
7197 /**
7198 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
7199 * (availability of ADC group injected depends on STM32 series).
7200 * @note If both groups regular and injected are selected,
7201 * specify behavior of ADC group injected interrupting
7202 * group regular: when ADC group injected is triggered,
7203 * the oversampling on ADC group regular is either
7204 * temporary stopped and continued, or resumed from start
7205 * (oversampler buffer reset).
7206 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
7207 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
7208 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
7209 * @param ADCx ADC instance
7210 * @retval Returned value can be one of the following values:
7211 * @arg @ref LL_ADC_OVS_DISABLE
7212 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
7213 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
7214 * @arg @ref LL_ADC_OVS_GRP_INJECTED
7215 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
7216 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)7217 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
7218 {
7219 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
7220 }
7221
7222 /**
7223 * @brief Set ADC oversampling discontinuous mode (triggered mode)
7224 * on the selected ADC group.
7225 * @note Number of oversampled conversions are done either in:
7226 * - continuous mode (all conversions of oversampling ratio
7227 * are done from 1 trigger)
7228 * - discontinuous mode (each conversion of oversampling ratio
7229 * needs a trigger)
7230 * @note On this STM32 series, setting of this feature is conditioned to
7231 * ADC state:
7232 * ADC must be disabled or enabled without conversion on going
7233 * on group regular.
7234 * @note On this STM32 series, oversampling discontinuous mode
7235 * (triggered mode) can be used only when oversampling is
7236 * set on group regular only and in resumed mode.
7237 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
7238 * @param ADCx ADC instance
7239 * @param OverSamplingDiscont This parameter can be one of the following values:
7240 * @arg @ref LL_ADC_OVS_REG_CONT
7241 * @arg @ref LL_ADC_OVS_REG_DISCONT
7242 * @retval None
7243 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)7244 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
7245 {
7246 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
7247 }
7248
7249 /**
7250 * @brief Get ADC oversampling discontinuous mode (triggered mode)
7251 * on the selected ADC group.
7252 * @note Number of oversampled conversions are done either in:
7253 * - continuous mode (all conversions of oversampling ratio
7254 * are done from 1 trigger)
7255 * - discontinuous mode (each conversion of oversampling ratio
7256 * needs a trigger)
7257 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
7258 * @param ADCx ADC instance
7259 * @retval Returned value can be one of the following values:
7260 * @arg @ref LL_ADC_OVS_REG_CONT
7261 * @arg @ref LL_ADC_OVS_REG_DISCONT
7262 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)7263 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
7264 {
7265 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
7266 }
7267
7268 /**
7269 * @brief Set ADC oversampling
7270 * (impacting both ADC groups regular and injected)
7271 * @note This function set the 2 items of oversampling configuration:
7272 * - ratio
7273 * - shift
7274 * @note On this STM32 series, setting of this feature is conditioned to
7275 * ADC state:
7276 * ADC must be disabled or enabled without conversion on going
7277 * on either groups regular or injected.
7278 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
7279 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
7280 * @param ADCx ADC instance
7281 * @param Ratio This parameter can be one of the following values:
7282 * @arg @ref LL_ADC_OVS_RATIO_2
7283 * @arg @ref LL_ADC_OVS_RATIO_4
7284 * @arg @ref LL_ADC_OVS_RATIO_8
7285 * @arg @ref LL_ADC_OVS_RATIO_16
7286 * @arg @ref LL_ADC_OVS_RATIO_32
7287 * @arg @ref LL_ADC_OVS_RATIO_64
7288 * @arg @ref LL_ADC_OVS_RATIO_128
7289 * @arg @ref LL_ADC_OVS_RATIO_256
7290 * @param Shift This parameter can be one of the following values:
7291 * @arg @ref LL_ADC_OVS_SHIFT_NONE
7292 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
7293 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
7294 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
7295 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
7296 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
7297 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
7298 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
7299 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
7300 * @retval None
7301 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)7302 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
7303 {
7304 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
7305 }
7306
7307 /**
7308 * @brief Get ADC oversampling ratio
7309 * (impacting both ADC groups regular and injected)
7310 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
7311 * @param ADCx ADC instance
7312 * @retval Ratio This parameter can be one of the following values:
7313 * @arg @ref LL_ADC_OVS_RATIO_2
7314 * @arg @ref LL_ADC_OVS_RATIO_4
7315 * @arg @ref LL_ADC_OVS_RATIO_8
7316 * @arg @ref LL_ADC_OVS_RATIO_16
7317 * @arg @ref LL_ADC_OVS_RATIO_32
7318 * @arg @ref LL_ADC_OVS_RATIO_64
7319 * @arg @ref LL_ADC_OVS_RATIO_128
7320 * @arg @ref LL_ADC_OVS_RATIO_256
7321 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)7322 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
7323 {
7324 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
7325 }
7326
7327 /**
7328 * @brief Get ADC oversampling shift
7329 * (impacting both ADC groups regular and injected)
7330 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
7331 * @param ADCx ADC instance
7332 * @retval Shift This parameter can be one of the following values:
7333 * @arg @ref LL_ADC_OVS_SHIFT_NONE
7334 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
7335 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
7336 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
7337 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
7338 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
7339 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
7340 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
7341 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
7342 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)7343 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
7344 {
7345 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
7346 }
7347
7348 /**
7349 * @}
7350 */
7351
7352 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
7353 * @{
7354 */
7355
7356 #if defined(ADC_MULTIMODE_SUPPORT)
7357 /**
7358 * @brief Set ADC multimode configuration to operate in independent mode
7359 * or multimode (for devices with several ADC instances).
7360 * @note If multimode configuration: the selected ADC instance is
7361 * either master or slave depending on hardware.
7362 * Refer to reference manual.
7363 * @note On this STM32 series, setting of this feature is conditioned to
7364 * ADC state:
7365 * All ADC instances of the ADC common group must be disabled.
7366 * This check can be done with function @ref LL_ADC_IsEnabled() for each
7367 * ADC instance or by using helper macro
7368 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
7369 * @rmtoll CCR DUAL LL_ADC_SetMultimode
7370 * @param ADCxy_COMMON ADC common instance
7371 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7372 * @param Multimode This parameter can be one of the following values:
7373 * @arg @ref LL_ADC_MULTI_INDEPENDENT
7374 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
7375 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
7376 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
7377 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
7378 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
7379 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
7380 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
7381 * @retval None
7382 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)7383 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
7384 {
7385 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
7386 }
7387
7388 /**
7389 * @brief Get ADC multimode configuration to operate in independent mode
7390 * or multimode (for devices with several ADC instances).
7391 * @note If multimode configuration: the selected ADC instance is
7392 * either master or slave depending on hardware.
7393 * Refer to reference manual.
7394 * @rmtoll CCR DUAL LL_ADC_GetMultimode
7395 * @param ADCxy_COMMON ADC common instance
7396 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7397 * @retval Returned value can be one of the following values:
7398 * @arg @ref LL_ADC_MULTI_INDEPENDENT
7399 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
7400 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
7401 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
7402 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
7403 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
7404 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
7405 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
7406 */
LL_ADC_GetMultimode(const ADC_Common_TypeDef * ADCxy_COMMON)7407 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
7408 {
7409 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
7410 }
7411
7412 /**
7413 * @brief Set ADC multimode conversion data transfer: no transfer
7414 * or transfer by DMA.
7415 * @note If ADC multimode transfer by DMA is not selected:
7416 * each ADC uses its own DMA channel, with its individual
7417 * DMA transfer settings.
7418 * If ADC multimode transfer by DMA is selected:
7419 * One DMA channel is used for both ADC (DMA of ADC master)
7420 * Specifies the DMA requests mode:
7421 * - Limited mode (One shot mode): DMA transfer requests are stopped
7422 * when number of DMA data transfers (number of
7423 * ADC conversions) is reached.
7424 * This ADC mode is intended to be used with DMA mode non-circular.
7425 * - Unlimited mode: DMA transfer requests are unlimited,
7426 * whatever number of DMA data transfers (number of
7427 * ADC conversions).
7428 * This ADC mode is intended to be used with DMA mode circular.
7429 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
7430 * mode non-circular:
7431 * when DMA transfers size will be reached, DMA will stop transfers of
7432 * ADC conversions data ADC will raise an overrun error
7433 * (overrun flag and interruption if enabled).
7434 * @note How to retrieve multimode conversion data:
7435 * Whatever multimode transfer by DMA setting: using function
7436 * @ref LL_ADC_REG_ReadMultiConversionData32().
7437 * If ADC multimode transfer by DMA is selected: conversion data
7438 * is a raw data with ADC master and slave concatenated.
7439 * A macro is available to get the conversion data of
7440 * ADC master or ADC slave: see helper macro
7441 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
7442 * @note On this STM32 series, setting of this feature is conditioned to
7443 * ADC state:
7444 * All ADC instances of the ADC common group must be disabled
7445 * or enabled without conversion on going on group regular.
7446 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
7447 * CCR DMACFG LL_ADC_SetMultiDMATransfer
7448 * @param ADCxy_COMMON ADC common instance
7449 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7450 * @param MultiDMATransfer This parameter can be one of the following values:
7451 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
7452 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
7453 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
7454 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
7455 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
7456 * @retval None
7457 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)7458 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
7459 {
7460 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
7461 }
7462
7463 /**
7464 * @brief Get ADC multimode conversion data transfer: no transfer
7465 * or transfer by DMA.
7466 * @note If ADC multimode transfer by DMA is not selected:
7467 * each ADC uses its own DMA channel, with its individual
7468 * DMA transfer settings.
7469 * If ADC multimode transfer by DMA is selected:
7470 * One DMA channel is used for both ADC (DMA of ADC master)
7471 * Specifies the DMA requests mode:
7472 * - Limited mode (One shot mode): DMA transfer requests are stopped
7473 * when number of DMA data transfers (number of
7474 * ADC conversions) is reached.
7475 * This ADC mode is intended to be used with DMA mode non-circular.
7476 * - Unlimited mode: DMA transfer requests are unlimited,
7477 * whatever number of DMA data transfers (number of
7478 * ADC conversions).
7479 * This ADC mode is intended to be used with DMA mode circular.
7480 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
7481 * mode non-circular:
7482 * when DMA transfers size will be reached, DMA will stop transfers of
7483 * ADC conversions data ADC will raise an overrun error
7484 * (overrun flag and interruption if enabled).
7485 * @note How to retrieve multimode conversion data:
7486 * Whatever multimode transfer by DMA setting: using function
7487 * @ref LL_ADC_REG_ReadMultiConversionData32().
7488 * If ADC multimode transfer by DMA is selected: conversion data
7489 * is a raw data with ADC master and slave concatenated.
7490 * A macro is available to get the conversion data of
7491 * ADC master or ADC slave: see helper macro
7492 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
7493 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
7494 * CCR DMACFG LL_ADC_GetMultiDMATransfer
7495 * @param ADCxy_COMMON ADC common instance
7496 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7497 * @retval Returned value can be one of the following values:
7498 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
7499 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
7500 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
7501 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
7502 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
7503 */
LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef * ADCxy_COMMON)7504 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
7505 {
7506 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
7507 }
7508
7509 /**
7510 * @brief Set ADC multimode delay between 2 sampling phases.
7511 * @note The sampling delay range depends on ADC resolution:
7512 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
7513 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
7514 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
7515 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
7516 * @note On this STM32 series, setting of this feature is conditioned to
7517 * ADC state:
7518 * All ADC instances of the ADC common group must be disabled.
7519 * This check can be done with function @ref LL_ADC_IsEnabled() for each
7520 * ADC instance or by using helper macro helper macro
7521 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
7522 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
7523 * @param ADCxy_COMMON ADC common instance
7524 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7525 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
7526 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
7527 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
7528 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
7529 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
7530 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
7531 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
7532 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
7533 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
7534 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
7535 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
7536 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
7537 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
7538 *
7539 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
7540 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
7541 * (3) Parameter available only if ADC resolution is 12 bits.
7542 * @retval None
7543 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)7544 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
7545 {
7546 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
7547 }
7548
7549 /**
7550 * @brief Get ADC multimode delay between 2 sampling phases.
7551 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
7552 * @param ADCxy_COMMON ADC common instance
7553 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7554 * @retval Returned value can be one of the following values:
7555 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
7556 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
7557 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
7558 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
7559 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
7560 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
7561 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
7562 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
7563 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
7564 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
7565 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
7566 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
7567 *
7568 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
7569 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
7570 * (3) Parameter available only if ADC resolution is 12 bits.
7571 */
LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef * ADCxy_COMMON)7572 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
7573 {
7574 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
7575 }
7576 #endif /* ADC_MULTIMODE_SUPPORT */
7577
7578 /**
7579 * @}
7580 */
7581 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
7582 * @{
7583 */
7584
7585 /**
7586 * @brief Put ADC instance in deep power down state.
7587 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
7588 * state, the internal analog calibration is lost. After exiting from
7589 * deep power down, calibration must be relaunched or calibration factor
7590 * (preliminarily saved) must be set back into calibration register.
7591 * @note On this STM32 series, setting of this feature is conditioned to
7592 * ADC state:
7593 * ADC must be ADC disabled.
7594 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
7595 * @param ADCx ADC instance
7596 * @retval None
7597 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)7598 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
7599 {
7600 /* Note: Write register with some additional bits forced to state reset */
7601 /* instead of modifying only the selected bit for this function, */
7602 /* to not interfere with bits with HW property "rs". */
7603 MODIFY_REG(ADCx->CR,
7604 ADC_CR_BITS_PROPERTY_RS,
7605 ADC_CR_DEEPPWD);
7606 }
7607
7608 /**
7609 * @brief Disable ADC deep power down mode.
7610 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
7611 * state, the internal analog calibration is lost. After exiting from
7612 * deep power down, calibration must be relaunched or calibration factor
7613 * (preliminarily saved) must be set back into calibration register.
7614 * @note On this STM32 series, setting of this feature is conditioned to
7615 * ADC state:
7616 * ADC must be ADC disabled.
7617 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
7618 * @param ADCx ADC instance
7619 * @retval None
7620 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)7621 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
7622 {
7623 /* Note: Write register with some additional bits forced to state reset */
7624 /* instead of modifying only the selected bit for this function, */
7625 /* to not interfere with bits with HW property "rs". */
7626 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
7627 }
7628
7629 /**
7630 * @brief Get the selected ADC instance deep power down state.
7631 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
7632 * @param ADCx ADC instance
7633 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
7634 */
LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef * ADCx)7635 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
7636 {
7637 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
7638 }
7639
7640 /**
7641 * @brief Enable ADC instance internal voltage regulator.
7642 * @note On this STM32 series, after ADC internal voltage regulator enable,
7643 * a delay for ADC internal voltage regulator stabilization
7644 * is required before performing a ADC calibration or ADC enable.
7645 * Refer to device datasheet, parameter tADCVREG_STUP.
7646 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
7647 * @note On this STM32 series, setting of this feature is conditioned to
7648 * ADC state:
7649 * ADC must be ADC disabled.
7650 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
7651 * @param ADCx ADC instance
7652 * @retval None
7653 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)7654 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
7655 {
7656 /* Note: Write register with some additional bits forced to state reset */
7657 /* instead of modifying only the selected bit for this function, */
7658 /* to not interfere with bits with HW property "rs". */
7659 MODIFY_REG(ADCx->CR,
7660 ADC_CR_BITS_PROPERTY_RS,
7661 ADC_CR_ADVREGEN);
7662 }
7663
7664 /**
7665 * @brief Disable ADC internal voltage regulator.
7666 * @note On this STM32 series, setting of this feature is conditioned to
7667 * ADC state:
7668 * ADC must be ADC disabled.
7669 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
7670 * @param ADCx ADC instance
7671 * @retval None
7672 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)7673 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
7674 {
7675 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
7676 }
7677
7678 /**
7679 * @brief Get the selected ADC instance internal voltage regulator state.
7680 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
7681 * @param ADCx ADC instance
7682 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
7683 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)7684 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
7685 {
7686 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
7687 }
7688
7689 /**
7690 * @brief Enable the selected ADC instance.
7691 * @note On this STM32 series, after ADC enable, a delay for
7692 * ADC internal analog stabilization is required before performing a
7693 * ADC conversion start.
7694 * Refer to device datasheet, parameter tSTAB.
7695 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7696 * is enabled and when conversion clock is active.
7697 * (not only core clock: this ADC has a dual clock domain)
7698 * @note On this STM32 series, setting of this feature is conditioned to
7699 * ADC state:
7700 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
7701 * @rmtoll CR ADEN LL_ADC_Enable
7702 * @param ADCx ADC instance
7703 * @retval None
7704 */
LL_ADC_Enable(ADC_TypeDef * ADCx)7705 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
7706 {
7707 /* Note: Write register with some additional bits forced to state reset */
7708 /* instead of modifying only the selected bit for this function, */
7709 /* to not interfere with bits with HW property "rs". */
7710 MODIFY_REG(ADCx->CR,
7711 ADC_CR_BITS_PROPERTY_RS,
7712 ADC_CR_ADEN);
7713 }
7714
7715 /**
7716 * @brief Disable the selected ADC instance.
7717 * @note On this STM32 series, setting of this feature is conditioned to
7718 * ADC state:
7719 * ADC must be not disabled. Must be enabled without conversion on going
7720 * on either groups regular or injected.
7721 * @rmtoll CR ADDIS LL_ADC_Disable
7722 * @param ADCx ADC instance
7723 * @retval None
7724 */
LL_ADC_Disable(ADC_TypeDef * ADCx)7725 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
7726 {
7727 /* Note: Write register with some additional bits forced to state reset */
7728 /* instead of modifying only the selected bit for this function, */
7729 /* to not interfere with bits with HW property "rs". */
7730 MODIFY_REG(ADCx->CR,
7731 ADC_CR_BITS_PROPERTY_RS,
7732 ADC_CR_ADDIS);
7733 }
7734
7735 /**
7736 * @brief Get the selected ADC instance enable state.
7737 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7738 * is enabled and when conversion clock is active.
7739 * (not only core clock: this ADC has a dual clock domain)
7740 * @rmtoll CR ADEN LL_ADC_IsEnabled
7741 * @param ADCx ADC instance
7742 * @retval 0: ADC is disabled, 1: ADC is enabled.
7743 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)7744 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
7745 {
7746 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
7747 }
7748
7749 /**
7750 * @brief Get the selected ADC instance disable state.
7751 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
7752 * @param ADCx ADC instance
7753 * @retval 0: no ADC disable command on going.
7754 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)7755 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
7756 {
7757 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
7758 }
7759
7760 /**
7761 * @brief Start ADC calibration in the mode single-ended
7762 * or differential (for devices with differential mode available).
7763 * @note On this STM32 series, a minimum number of ADC clock cycles
7764 * are required between ADC end of calibration and ADC enable.
7765 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
7766 * @note For devices with differential mode available:
7767 * Calibration of offset is specific to each of
7768 * single-ended and differential modes
7769 * (calibration run must be performed for each of these
7770 * differential modes, if used afterwards and if the application
7771 * requires their calibration).
7772 * @note On this STM32 series, setting of this feature is conditioned to
7773 * ADC state:
7774 * ADC must be ADC disabled.
7775 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
7776 * CR ADCALDIF LL_ADC_StartCalibration
7777 * @param ADCx ADC instance
7778 * @param SingleDiff This parameter can be one of the following values:
7779 * @arg @ref LL_ADC_SINGLE_ENDED
7780 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
7781 * @retval None
7782 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)7783 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
7784 {
7785 /* Note: Write register with some additional bits forced to state reset */
7786 /* instead of modifying only the selected bit for this function, */
7787 /* to not interfere with bits with HW property "rs". */
7788 MODIFY_REG(ADCx->CR,
7789 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
7790 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
7791 }
7792
7793 /**
7794 * @brief Get ADC calibration state.
7795 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
7796 * @param ADCx ADC instance
7797 * @retval 0: calibration complete, 1: calibration in progress.
7798 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)7799 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
7800 {
7801 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
7802 }
7803
7804 /**
7805 * @}
7806 */
7807
7808 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
7809 * @{
7810 */
7811
7812 /**
7813 * @brief Start ADC group regular conversion.
7814 * @note On this STM32 series, this function is relevant for both
7815 * internal trigger (SW start) and external trigger:
7816 * - If ADC trigger has been set to software start, ADC conversion
7817 * starts immediately.
7818 * - If ADC trigger has been set to external trigger, ADC conversion
7819 * will start at next trigger event (on the selected trigger edge)
7820 * following the ADC start conversion command.
7821 * @note On this STM32 series, setting of this feature is conditioned to
7822 * ADC state:
7823 * ADC must be enabled without conversion on going on group regular,
7824 * without conversion stop command on going on group regular,
7825 * without ADC disable command on going.
7826 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
7827 * @param ADCx ADC instance
7828 * @retval None
7829 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)7830 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
7831 {
7832 /* Note: Write register with some additional bits forced to state reset */
7833 /* instead of modifying only the selected bit for this function, */
7834 /* to not interfere with bits with HW property "rs". */
7835 MODIFY_REG(ADCx->CR,
7836 ADC_CR_BITS_PROPERTY_RS,
7837 ADC_CR_ADSTART);
7838 }
7839
7840 /**
7841 * @brief Stop ADC group regular conversion.
7842 * @note On this STM32 series, setting of this feature is conditioned to
7843 * ADC state:
7844 * ADC must be enabled with conversion on going on group regular,
7845 * without ADC disable command on going.
7846 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
7847 * @param ADCx ADC instance
7848 * @retval None
7849 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)7850 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
7851 {
7852 /* Note: Write register with some additional bits forced to state reset */
7853 /* instead of modifying only the selected bit for this function, */
7854 /* to not interfere with bits with HW property "rs". */
7855 MODIFY_REG(ADCx->CR,
7856 ADC_CR_BITS_PROPERTY_RS,
7857 ADC_CR_ADSTP);
7858 }
7859
7860 /**
7861 * @brief Get ADC group regular conversion state.
7862 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
7863 * @param ADCx ADC instance
7864 * @retval 0: no conversion is on going on ADC group regular.
7865 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)7866 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
7867 {
7868 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
7869 }
7870
7871 /**
7872 * @brief Get ADC group regular command of conversion stop state
7873 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
7874 * @param ADCx ADC instance
7875 * @retval 0: no command of conversion stop is on going on ADC group regular.
7876 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)7877 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
7878 {
7879 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
7880 }
7881
7882 /**
7883 * @brief Start ADC sampling phase for sampling time trigger mode
7884 * @note This function is relevant only when
7885 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
7886 * using @ref LL_ADC_REG_SetSamplingMode
7887 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
7888 * @note On this STM32 series, setting of this feature is conditioned to
7889 * ADC state:
7890 * ADC must be enabled without conversion on going on group regular,
7891 * without conversion stop command on going on group regular,
7892 * without ADC disable command on going.
7893 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
7894 * @param ADCx ADC instance
7895 * @retval None
7896 */
LL_ADC_REG_StartSamplingPhase(ADC_TypeDef * ADCx)7897 __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
7898 {
7899 SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
7900 }
7901
7902 /**
7903 * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion
7904 * @note This function is relevant only when
7905 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
7906 * using @ref LL_ADC_REG_SetSamplingMode
7907 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
7908 * - @ref LL_ADC_REG_StartSamplingPhase has been called to start
7909 * the sampling phase
7910 * @note On this STM32 series, setting of this feature is conditioned to
7911 * ADC state:
7912 * ADC must be enabled without conversion on going on group regular,
7913 * without conversion stop command on going on group regular,
7914 * without ADC disable command on going.
7915 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
7916 * @param ADCx ADC instance
7917 * @retval None
7918 */
LL_ADC_REG_StopSamplingPhase(ADC_TypeDef * ADCx)7919 __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
7920 {
7921 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
7922 }
7923
7924 /**
7925 * @brief Get ADC group regular conversion data, range fit for
7926 * all ADC configurations: all ADC resolutions and
7927 * all oversampling increased data width (for devices
7928 * with feature oversampling).
7929 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
7930 * @param ADCx ADC instance
7931 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7932 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)7933 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
7934 {
7935 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7936 }
7937
7938 /**
7939 * @brief Get ADC group regular conversion data, range fit for
7940 * ADC resolution 12 bits.
7941 * @note For devices with feature oversampling: Oversampling
7942 * can increase data width, function for extended range
7943 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7944 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
7945 * @param ADCx ADC instance
7946 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7947 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)7948 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
7949 {
7950 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7951 }
7952
7953 /**
7954 * @brief Get ADC group regular conversion data, range fit for
7955 * ADC resolution 10 bits.
7956 * @note For devices with feature oversampling: Oversampling
7957 * can increase data width, function for extended range
7958 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7959 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
7960 * @param ADCx ADC instance
7961 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7962 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)7963 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
7964 {
7965 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7966 }
7967
7968 /**
7969 * @brief Get ADC group regular conversion data, range fit for
7970 * ADC resolution 8 bits.
7971 * @note For devices with feature oversampling: Oversampling
7972 * can increase data width, function for extended range
7973 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7974 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
7975 * @param ADCx ADC instance
7976 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7977 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)7978 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
7979 {
7980 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7981 }
7982
7983 /**
7984 * @brief Get ADC group regular conversion data, range fit for
7985 * ADC resolution 6 bits.
7986 * @note For devices with feature oversampling: Oversampling
7987 * can increase data width, function for extended range
7988 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7989 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
7990 * @param ADCx ADC instance
7991 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
7992 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)7993 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
7994 {
7995 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7996 }
7997
7998 #if defined(ADC_MULTIMODE_SUPPORT)
7999 /**
8000 * @brief Get ADC multimode conversion data of ADC master, ADC slave
8001 * or raw data with ADC master and slave concatenated.
8002 * @note If raw data with ADC master and slave concatenated is retrieved,
8003 * a macro is available to get the conversion data of
8004 * ADC master or ADC slave: see helper macro
8005 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
8006 * (however this macro is mainly intended for multimode
8007 * transfer by DMA, because this function can do the same
8008 * by getting multimode conversion data of ADC master or ADC slave
8009 * separately).
8010 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
8011 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
8012 * @param ADCxy_COMMON ADC common instance
8013 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8014 * @param ConversionData This parameter can be one of the following values:
8015 * @arg @ref LL_ADC_MULTI_MASTER
8016 * @arg @ref LL_ADC_MULTI_SLAVE
8017 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
8018 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
8019 */
LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)8020 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON,
8021 uint32_t ConversionData)
8022 {
8023 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
8024 ConversionData)
8025 >> (POSITION_VAL(ConversionData) & 0x1FUL)
8026 );
8027 }
8028 #endif /* ADC_MULTIMODE_SUPPORT */
8029
8030 /**
8031 * @}
8032 */
8033
8034 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
8035 * @{
8036 */
8037
8038 /**
8039 * @brief Start ADC group injected conversion.
8040 * @note On this STM32 series, this function is relevant for both
8041 * internal trigger (SW start) and external trigger:
8042 * - If ADC trigger has been set to software start, ADC conversion
8043 * starts immediately.
8044 * - If ADC trigger has been set to external trigger, ADC conversion
8045 * will start at next trigger event (on the selected trigger edge)
8046 * following the ADC start conversion command.
8047 * @note On this STM32 series, setting of this feature is conditioned to
8048 * ADC state:
8049 * ADC must be enabled without conversion on going on group injected,
8050 * without conversion stop command on going on group injected,
8051 * without ADC disable command on going.
8052 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
8053 * @param ADCx ADC instance
8054 * @retval None
8055 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)8056 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
8057 {
8058 /* Note: Write register with some additional bits forced to state reset */
8059 /* instead of modifying only the selected bit for this function, */
8060 /* to not interfere with bits with HW property "rs". */
8061 MODIFY_REG(ADCx->CR,
8062 ADC_CR_BITS_PROPERTY_RS,
8063 ADC_CR_JADSTART);
8064 }
8065
8066 /**
8067 * @brief Stop ADC group injected conversion.
8068 * @note On this STM32 series, setting of this feature is conditioned to
8069 * ADC state:
8070 * ADC must be enabled with conversion on going on group injected,
8071 * without ADC disable command on going.
8072 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
8073 * @param ADCx ADC instance
8074 * @retval None
8075 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)8076 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
8077 {
8078 /* Note: Write register with some additional bits forced to state reset */
8079 /* instead of modifying only the selected bit for this function, */
8080 /* to not interfere with bits with HW property "rs". */
8081 MODIFY_REG(ADCx->CR,
8082 ADC_CR_BITS_PROPERTY_RS,
8083 ADC_CR_JADSTP);
8084 }
8085
8086 /**
8087 * @brief Get ADC group injected conversion state.
8088 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
8089 * @param ADCx ADC instance
8090 * @retval 0: no conversion is on going on ADC group injected.
8091 */
LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef * ADCx)8092 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
8093 {
8094 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
8095 }
8096
8097 /**
8098 * @brief Get ADC group injected command of conversion stop state
8099 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
8100 * @param ADCx ADC instance
8101 * @retval 0: no command of conversion stop is on going on ADC group injected.
8102 */
LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef * ADCx)8103 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
8104 {
8105 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
8106 }
8107
8108 /**
8109 * @brief Get ADC group injected conversion data, range fit for
8110 * all ADC configurations: all ADC resolutions and
8111 * all oversampling increased data width (for devices
8112 * with feature oversampling).
8113 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
8114 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
8115 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
8116 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
8117 * @param ADCx ADC instance
8118 * @param Rank This parameter can be one of the following values:
8119 * @arg @ref LL_ADC_INJ_RANK_1
8120 * @arg @ref LL_ADC_INJ_RANK_2
8121 * @arg @ref LL_ADC_INJ_RANK_3
8122 * @arg @ref LL_ADC_INJ_RANK_4
8123 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
8124 */
LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef * ADCx,uint32_t Rank)8125 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
8126 {
8127 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
8128 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
8129
8130 return (uint32_t)(READ_BIT(*preg,
8131 ADC_JDR1_JDATA)
8132 );
8133 }
8134
8135 /**
8136 * @brief Get ADC group injected conversion data, range fit for
8137 * ADC resolution 12 bits.
8138 * @note For devices with feature oversampling: Oversampling
8139 * can increase data width, function for extended range
8140 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8141 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
8142 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
8143 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
8144 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
8145 * @param ADCx ADC instance
8146 * @param Rank This parameter can be one of the following values:
8147 * @arg @ref LL_ADC_INJ_RANK_1
8148 * @arg @ref LL_ADC_INJ_RANK_2
8149 * @arg @ref LL_ADC_INJ_RANK_3
8150 * @arg @ref LL_ADC_INJ_RANK_4
8151 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
8152 */
LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef * ADCx,uint32_t Rank)8153 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
8154 {
8155 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
8156 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
8157
8158 return (uint16_t)(READ_BIT(*preg,
8159 ADC_JDR1_JDATA)
8160 );
8161 }
8162
8163 /**
8164 * @brief Get ADC group injected conversion data, range fit for
8165 * ADC resolution 10 bits.
8166 * @note For devices with feature oversampling: Oversampling
8167 * can increase data width, function for extended range
8168 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8169 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
8170 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
8171 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
8172 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
8173 * @param ADCx ADC instance
8174 * @param Rank This parameter can be one of the following values:
8175 * @arg @ref LL_ADC_INJ_RANK_1
8176 * @arg @ref LL_ADC_INJ_RANK_2
8177 * @arg @ref LL_ADC_INJ_RANK_3
8178 * @arg @ref LL_ADC_INJ_RANK_4
8179 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
8180 */
LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef * ADCx,uint32_t Rank)8181 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
8182 {
8183 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
8184 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
8185
8186 return (uint16_t)(READ_BIT(*preg,
8187 ADC_JDR1_JDATA)
8188 );
8189 }
8190
8191 /**
8192 * @brief Get ADC group injected conversion data, range fit for
8193 * ADC resolution 8 bits.
8194 * @note For devices with feature oversampling: Oversampling
8195 * can increase data width, function for extended range
8196 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8197 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
8198 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
8199 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
8200 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
8201 * @param ADCx ADC instance
8202 * @param Rank This parameter can be one of the following values:
8203 * @arg @ref LL_ADC_INJ_RANK_1
8204 * @arg @ref LL_ADC_INJ_RANK_2
8205 * @arg @ref LL_ADC_INJ_RANK_3
8206 * @arg @ref LL_ADC_INJ_RANK_4
8207 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
8208 */
LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef * ADCx,uint32_t Rank)8209 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
8210 {
8211 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
8212 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
8213
8214 return (uint8_t)(READ_BIT(*preg,
8215 ADC_JDR1_JDATA)
8216 );
8217 }
8218
8219 /**
8220 * @brief Get ADC group injected conversion data, range fit for
8221 * ADC resolution 6 bits.
8222 * @note For devices with feature oversampling: Oversampling
8223 * can increase data width, function for extended range
8224 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8225 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
8226 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
8227 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
8228 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
8229 * @param ADCx ADC instance
8230 * @param Rank This parameter can be one of the following values:
8231 * @arg @ref LL_ADC_INJ_RANK_1
8232 * @arg @ref LL_ADC_INJ_RANK_2
8233 * @arg @ref LL_ADC_INJ_RANK_3
8234 * @arg @ref LL_ADC_INJ_RANK_4
8235 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
8236 */
LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef * ADCx,uint32_t Rank)8237 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
8238 {
8239 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
8240 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
8241
8242 return (uint8_t)(READ_BIT(*preg,
8243 ADC_JDR1_JDATA)
8244 );
8245 }
8246
8247 /**
8248 * @}
8249 */
8250
8251 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
8252 * @{
8253 */
8254
8255 /**
8256 * @brief Get flag ADC ready.
8257 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
8258 * is enabled and when conversion clock is active.
8259 * (not only core clock: this ADC has a dual clock domain)
8260 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
8261 * @param ADCx ADC instance
8262 * @retval State of bit (1 or 0).
8263 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)8264 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
8265 {
8266 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
8267 }
8268
8269 /**
8270 * @brief Get flag ADC group regular end of unitary conversion.
8271 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
8272 * @param ADCx ADC instance
8273 * @retval State of bit (1 or 0).
8274 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)8275 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
8276 {
8277 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
8278 }
8279
8280 /**
8281 * @brief Get flag ADC group regular end of sequence conversions.
8282 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
8283 * @param ADCx ADC instance
8284 * @retval State of bit (1 or 0).
8285 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)8286 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
8287 {
8288 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
8289 }
8290
8291 /**
8292 * @brief Get flag ADC group regular overrun.
8293 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
8294 * @param ADCx ADC instance
8295 * @retval State of bit (1 or 0).
8296 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)8297 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
8298 {
8299 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
8300 }
8301
8302 /**
8303 * @brief Get flag ADC group regular end of sampling phase.
8304 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
8305 * @param ADCx ADC instance
8306 * @retval State of bit (1 or 0).
8307 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)8308 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
8309 {
8310 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
8311 }
8312
8313 /**
8314 * @brief Get flag ADC group injected end of unitary conversion.
8315 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
8316 * @param ADCx ADC instance
8317 * @retval State of bit (1 or 0).
8318 */
LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef * ADCx)8319 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
8320 {
8321 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
8322 }
8323
8324 /**
8325 * @brief Get flag ADC group injected end of sequence conversions.
8326 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
8327 * @param ADCx ADC instance
8328 * @retval State of bit (1 or 0).
8329 */
LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef * ADCx)8330 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
8331 {
8332 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
8333 }
8334
8335 /**
8336 * @brief Get flag ADC group injected contexts queue overflow.
8337 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
8338 * @param ADCx ADC instance
8339 * @retval State of bit (1 or 0).
8340 */
LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef * ADCx)8341 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx)
8342 {
8343 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
8344 }
8345
8346 /**
8347 * @brief Get flag ADC analog watchdog 1 flag
8348 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
8349 * @param ADCx ADC instance
8350 * @retval State of bit (1 or 0).
8351 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)8352 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
8353 {
8354 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
8355 }
8356
8357 /**
8358 * @brief Get flag ADC analog watchdog 2.
8359 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
8360 * @param ADCx ADC instance
8361 * @retval State of bit (1 or 0).
8362 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)8363 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
8364 {
8365 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
8366 }
8367
8368 /**
8369 * @brief Get flag ADC analog watchdog 3.
8370 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
8371 * @param ADCx ADC instance
8372 * @retval State of bit (1 or 0).
8373 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)8374 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
8375 {
8376 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
8377 }
8378
8379 /**
8380 * @brief Clear flag ADC ready.
8381 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
8382 * is enabled and when conversion clock is active.
8383 * (not only core clock: this ADC has a dual clock domain)
8384 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
8385 * @param ADCx ADC instance
8386 * @retval None
8387 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)8388 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
8389 {
8390 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
8391 }
8392
8393 /**
8394 * @brief Clear flag ADC group regular end of unitary conversion.
8395 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
8396 * @param ADCx ADC instance
8397 * @retval None
8398 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)8399 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
8400 {
8401 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
8402 }
8403
8404 /**
8405 * @brief Clear flag ADC group regular end of sequence conversions.
8406 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
8407 * @param ADCx ADC instance
8408 * @retval None
8409 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)8410 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
8411 {
8412 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
8413 }
8414
8415 /**
8416 * @brief Clear flag ADC group regular overrun.
8417 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
8418 * @param ADCx ADC instance
8419 * @retval None
8420 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)8421 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
8422 {
8423 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
8424 }
8425
8426 /**
8427 * @brief Clear flag ADC group regular end of sampling phase.
8428 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
8429 * @param ADCx ADC instance
8430 * @retval None
8431 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)8432 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
8433 {
8434 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
8435 }
8436
8437 /**
8438 * @brief Clear flag ADC group injected end of unitary conversion.
8439 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
8440 * @param ADCx ADC instance
8441 * @retval None
8442 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)8443 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
8444 {
8445 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
8446 }
8447
8448 /**
8449 * @brief Clear flag ADC group injected end of sequence conversions.
8450 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
8451 * @param ADCx ADC instance
8452 * @retval None
8453 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)8454 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
8455 {
8456 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
8457 }
8458
8459 /**
8460 * @brief Clear flag ADC group injected contexts queue overflow.
8461 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
8462 * @param ADCx ADC instance
8463 * @retval None
8464 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)8465 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
8466 {
8467 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
8468 }
8469
8470 /**
8471 * @brief Clear flag ADC analog watchdog 1.
8472 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
8473 * @param ADCx ADC instance
8474 * @retval None
8475 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)8476 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
8477 {
8478 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
8479 }
8480
8481 /**
8482 * @brief Clear flag ADC analog watchdog 2.
8483 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
8484 * @param ADCx ADC instance
8485 * @retval None
8486 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)8487 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
8488 {
8489 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
8490 }
8491
8492 /**
8493 * @brief Clear flag ADC analog watchdog 3.
8494 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
8495 * @param ADCx ADC instance
8496 * @retval None
8497 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)8498 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
8499 {
8500 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
8501 }
8502
8503 #if defined(ADC_MULTIMODE_SUPPORT)
8504 /**
8505 * @brief Get flag multimode ADC ready of the ADC master.
8506 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
8507 * @param ADCxy_COMMON ADC common instance
8508 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8509 * @retval State of bit (1 or 0).
8510 */
LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)8511 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
8512 {
8513 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
8514 }
8515
8516 /**
8517 * @brief Get flag multimode ADC ready of the ADC slave.
8518 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
8519 * @param ADCxy_COMMON ADC common instance
8520 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8521 * @retval State of bit (1 or 0).
8522 */
LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)8523 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
8524 {
8525 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
8526 }
8527
8528 /**
8529 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
8530 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
8531 * @param ADCxy_COMMON ADC common instance
8532 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8533 * @retval State of bit (1 or 0).
8534 */
LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)8535 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
8536 {
8537 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
8538 }
8539
8540 /**
8541 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
8542 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
8543 * @param ADCxy_COMMON ADC common instance
8544 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8545 * @retval State of bit (1 or 0).
8546 */
LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)8547 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
8548 {
8549 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
8550 }
8551
8552 /**
8553 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
8554 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
8555 * @param ADCxy_COMMON ADC common instance
8556 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8557 * @retval State of bit (1 or 0).
8558 */
LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)8559 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
8560 {
8561 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
8562 }
8563
8564 /**
8565 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
8566 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
8567 * @param ADCxy_COMMON ADC common instance
8568 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8569 * @retval State of bit (1 or 0).
8570 */
LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)8571 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
8572 {
8573 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
8574 }
8575
8576 /**
8577 * @brief Get flag multimode ADC group regular overrun of the ADC master.
8578 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
8579 * @param ADCxy_COMMON ADC common instance
8580 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8581 * @retval State of bit (1 or 0).
8582 */
LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)8583 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
8584 {
8585 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
8586 }
8587
8588 /**
8589 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
8590 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
8591 * @param ADCxy_COMMON ADC common instance
8592 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8593 * @retval State of bit (1 or 0).
8594 */
LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)8595 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
8596 {
8597 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
8598 }
8599
8600 /**
8601 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
8602 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
8603 * @param ADCxy_COMMON ADC common instance
8604 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8605 * @retval State of bit (1 or 0).
8606 */
LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)8607 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
8608 {
8609 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
8610 }
8611
8612 /**
8613 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
8614 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
8615 * @param ADCxy_COMMON ADC common instance
8616 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8617 * @retval State of bit (1 or 0).
8618 */
LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)8619 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
8620 {
8621 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
8622 }
8623
8624 /**
8625 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
8626 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
8627 * @param ADCxy_COMMON ADC common instance
8628 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8629 * @retval State of bit (1 or 0).
8630 */
LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)8631 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
8632 {
8633 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
8634 }
8635
8636 /**
8637 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
8638 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
8639 * @param ADCxy_COMMON ADC common instance
8640 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8641 * @retval State of bit (1 or 0).
8642 */
LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)8643 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
8644 {
8645 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
8646 }
8647
8648 /**
8649 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
8650 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
8651 * @param ADCxy_COMMON ADC common instance
8652 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8653 * @retval State of bit (1 or 0).
8654 */
LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)8655 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
8656 {
8657 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
8658 }
8659
8660 /**
8661 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
8662 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
8663 * @param ADCxy_COMMON ADC common instance
8664 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8665 * @retval State of bit (1 or 0).
8666 */
LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)8667 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
8668 {
8669 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
8670 }
8671
8672 /**
8673 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
8674 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
8675 * @param ADCxy_COMMON ADC common instance
8676 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8677 * @retval State of bit (1 or 0).
8678 */
LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef * ADCxy_COMMON)8679 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
8680 {
8681 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
8682 }
8683
8684 /**
8685 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
8686 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
8687 * @param ADCxy_COMMON ADC common instance
8688 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8689 * @retval State of bit (1 or 0).
8690 */
LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef * ADCxy_COMMON)8691 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
8692 {
8693 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
8694 }
8695
8696 /**
8697 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
8698 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
8699 * @param ADCxy_COMMON ADC common instance
8700 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8701 * @retval State of bit (1 or 0).
8702 */
LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)8703 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
8704 {
8705 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
8706 }
8707
8708 /**
8709 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
8710 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
8711 * @param ADCxy_COMMON ADC common instance
8712 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8713 * @retval State of bit (1 or 0).
8714 */
LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)8715 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
8716 {
8717 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
8718 }
8719
8720 /**
8721 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
8722 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
8723 * @param ADCxy_COMMON ADC common instance
8724 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8725 * @retval State of bit (1 or 0).
8726 */
LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)8727 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
8728 {
8729 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
8730 }
8731
8732 /**
8733 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
8734 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
8735 * @param ADCxy_COMMON ADC common instance
8736 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8737 * @retval State of bit (1 or 0).
8738 */
LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)8739 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
8740 {
8741 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
8742 }
8743
8744 /**
8745 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
8746 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
8747 * @param ADCxy_COMMON ADC common instance
8748 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8749 * @retval State of bit (1 or 0).
8750 */
LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)8751 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
8752 {
8753 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
8754 }
8755
8756 /**
8757 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
8758 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
8759 * @param ADCxy_COMMON ADC common instance
8760 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8761 * @retval State of bit (1 or 0).
8762 */
LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)8763 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
8764 {
8765 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
8766 }
8767 #endif /* ADC_MULTIMODE_SUPPORT */
8768
8769 /**
8770 * @}
8771 */
8772
8773 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
8774 * @{
8775 */
8776
8777 /**
8778 * @brief Enable ADC ready.
8779 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
8780 * @param ADCx ADC instance
8781 * @retval None
8782 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)8783 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
8784 {
8785 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8786 }
8787
8788 /**
8789 * @brief Enable interruption ADC group regular end of unitary conversion.
8790 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
8791 * @param ADCx ADC instance
8792 * @retval None
8793 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)8794 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
8795 {
8796 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
8797 }
8798
8799 /**
8800 * @brief Enable interruption ADC group regular end of sequence conversions.
8801 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
8802 * @param ADCx ADC instance
8803 * @retval None
8804 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)8805 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
8806 {
8807 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
8808 }
8809
8810 /**
8811 * @brief Enable ADC group regular interruption overrun.
8812 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
8813 * @param ADCx ADC instance
8814 * @retval None
8815 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)8816 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
8817 {
8818 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
8819 }
8820
8821 /**
8822 * @brief Enable interruption ADC group regular end of sampling.
8823 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
8824 * @param ADCx ADC instance
8825 * @retval None
8826 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)8827 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
8828 {
8829 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8830 }
8831
8832 /**
8833 * @brief Enable interruption ADC group injected end of unitary conversion.
8834 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
8835 * @param ADCx ADC instance
8836 * @retval None
8837 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)8838 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
8839 {
8840 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8841 }
8842
8843 /**
8844 * @brief Enable interruption ADC group injected end of sequence conversions.
8845 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
8846 * @param ADCx ADC instance
8847 * @retval None
8848 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)8849 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
8850 {
8851 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8852 }
8853
8854 /**
8855 * @brief Enable interruption ADC group injected context queue overflow.
8856 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
8857 * @param ADCx ADC instance
8858 * @retval None
8859 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)8860 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
8861 {
8862 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
8863 }
8864
8865 /**
8866 * @brief Enable interruption ADC analog watchdog 1.
8867 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
8868 * @param ADCx ADC instance
8869 * @retval None
8870 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)8871 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
8872 {
8873 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8874 }
8875
8876 /**
8877 * @brief Enable interruption ADC analog watchdog 2.
8878 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
8879 * @param ADCx ADC instance
8880 * @retval None
8881 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)8882 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
8883 {
8884 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8885 }
8886
8887 /**
8888 * @brief Enable interruption ADC analog watchdog 3.
8889 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
8890 * @param ADCx ADC instance
8891 * @retval None
8892 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)8893 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
8894 {
8895 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8896 }
8897
8898 /**
8899 * @brief Disable interruption ADC ready.
8900 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
8901 * @param ADCx ADC instance
8902 * @retval None
8903 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)8904 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
8905 {
8906 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8907 }
8908
8909 /**
8910 * @brief Disable interruption ADC group regular end of unitary conversion.
8911 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
8912 * @param ADCx ADC instance
8913 * @retval None
8914 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)8915 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
8916 {
8917 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
8918 }
8919
8920 /**
8921 * @brief Disable interruption ADC group regular end of sequence conversions.
8922 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
8923 * @param ADCx ADC instance
8924 * @retval None
8925 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)8926 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
8927 {
8928 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
8929 }
8930
8931 /**
8932 * @brief Disable interruption ADC group regular overrun.
8933 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
8934 * @param ADCx ADC instance
8935 * @retval None
8936 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)8937 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
8938 {
8939 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
8940 }
8941
8942 /**
8943 * @brief Disable interruption ADC group regular end of sampling.
8944 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
8945 * @param ADCx ADC instance
8946 * @retval None
8947 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)8948 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
8949 {
8950 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8951 }
8952
8953 /**
8954 * @brief Disable interruption ADC group regular end of unitary conversion.
8955 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
8956 * @param ADCx ADC instance
8957 * @retval None
8958 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)8959 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
8960 {
8961 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8962 }
8963
8964 /**
8965 * @brief Disable interruption ADC group injected end of sequence conversions.
8966 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
8967 * @param ADCx ADC instance
8968 * @retval None
8969 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)8970 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
8971 {
8972 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8973 }
8974
8975 /**
8976 * @brief Disable interruption ADC group injected context queue overflow.
8977 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
8978 * @param ADCx ADC instance
8979 * @retval None
8980 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)8981 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
8982 {
8983 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
8984 }
8985
8986 /**
8987 * @brief Disable interruption ADC analog watchdog 1.
8988 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
8989 * @param ADCx ADC instance
8990 * @retval None
8991 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)8992 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
8993 {
8994 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8995 }
8996
8997 /**
8998 * @brief Disable interruption ADC analog watchdog 2.
8999 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
9000 * @param ADCx ADC instance
9001 * @retval None
9002 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)9003 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
9004 {
9005 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
9006 }
9007
9008 /**
9009 * @brief Disable interruption ADC analog watchdog 3.
9010 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
9011 * @param ADCx ADC instance
9012 * @retval None
9013 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)9014 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
9015 {
9016 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
9017 }
9018
9019 /**
9020 * @brief Get state of interruption ADC ready
9021 * (0: interrupt disabled, 1: interrupt enabled).
9022 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
9023 * @param ADCx ADC instance
9024 * @retval State of bit (1 or 0).
9025 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)9026 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
9027 {
9028 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
9029 }
9030
9031 /**
9032 * @brief Get state of interruption ADC group regular end of unitary conversion
9033 * (0: interrupt disabled, 1: interrupt enabled).
9034 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
9035 * @param ADCx ADC instance
9036 * @retval State of bit (1 or 0).
9037 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)9038 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
9039 {
9040 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
9041 }
9042
9043 /**
9044 * @brief Get state of interruption ADC group regular end of sequence conversions
9045 * (0: interrupt disabled, 1: interrupt enabled).
9046 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
9047 * @param ADCx ADC instance
9048 * @retval State of bit (1 or 0).
9049 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)9050 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
9051 {
9052 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
9053 }
9054
9055 /**
9056 * @brief Get state of interruption ADC group regular overrun
9057 * (0: interrupt disabled, 1: interrupt enabled).
9058 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
9059 * @param ADCx ADC instance
9060 * @retval State of bit (1 or 0).
9061 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)9062 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
9063 {
9064 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
9065 }
9066
9067 /**
9068 * @brief Get state of interruption ADC group regular end of sampling
9069 * (0: interrupt disabled, 1: interrupt enabled).
9070 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
9071 * @param ADCx ADC instance
9072 * @retval State of bit (1 or 0).
9073 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)9074 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
9075 {
9076 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
9077 }
9078
9079 /**
9080 * @brief Get state of interruption ADC group injected end of unitary conversion
9081 * (0: interrupt disabled, 1: interrupt enabled).
9082 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
9083 * @param ADCx ADC instance
9084 * @retval State of bit (1 or 0).
9085 */
LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef * ADCx)9086 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
9087 {
9088 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
9089 }
9090
9091 /**
9092 * @brief Get state of interruption ADC group injected end of sequence conversions
9093 * (0: interrupt disabled, 1: interrupt enabled).
9094 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
9095 * @param ADCx ADC instance
9096 * @retval State of bit (1 or 0).
9097 */
LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef * ADCx)9098 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
9099 {
9100 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
9101 }
9102
9103 /**
9104 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
9105 * (0: interrupt disabled, 1: interrupt enabled).
9106 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
9107 * @param ADCx ADC instance
9108 * @retval State of bit (1 or 0).
9109 */
LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef * ADCx)9110 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx)
9111 {
9112 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
9113 }
9114
9115 /**
9116 * @brief Get state of interruption ADC analog watchdog 1
9117 * (0: interrupt disabled, 1: interrupt enabled).
9118 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
9119 * @param ADCx ADC instance
9120 * @retval State of bit (1 or 0).
9121 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)9122 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
9123 {
9124 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
9125 }
9126
9127 /**
9128 * @brief Get state of interruption Get ADC analog watchdog 2
9129 * (0: interrupt disabled, 1: interrupt enabled).
9130 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
9131 * @param ADCx ADC instance
9132 * @retval State of bit (1 or 0).
9133 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)9134 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
9135 {
9136 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
9137 }
9138
9139 /**
9140 * @brief Get state of interruption Get ADC analog watchdog 3
9141 * (0: interrupt disabled, 1: interrupt enabled).
9142 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
9143 * @param ADCx ADC instance
9144 * @retval State of bit (1 or 0).
9145 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)9146 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
9147 {
9148 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
9149 }
9150
9151 /**
9152 * @}
9153 */
9154
9155 #if defined(USE_FULL_LL_DRIVER)
9156 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
9157 * @{
9158 */
9159
9160 /* Initialization of some features of ADC common parameters and multimode */
9161 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
9162 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
9163 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
9164
9165 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
9166 /* (availability of ADC group injected depends on STM32 series) */
9167 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
9168
9169 /* Initialization of some features of ADC instance */
9170 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
9171 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
9172
9173 /* Initialization of some features of ADC instance and ADC group regular */
9174 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
9175 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
9176
9177 /* Initialization of some features of ADC instance and ADC group injected */
9178 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
9179 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
9180
9181 /**
9182 * @}
9183 */
9184 #endif /* USE_FULL_LL_DRIVER */
9185
9186 /**
9187 * @}
9188 */
9189
9190 /**
9191 * @}
9192 */
9193
9194 #endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
9195
9196 /**
9197 * @}
9198 */
9199
9200 #ifdef __cplusplus
9201 }
9202 #endif
9203
9204 #endif /* STM32G4xx_LL_ADC_H */
9205
