1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_ADC_H
21 #define STM32U5xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC4)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC calibration: */
49 /* Internal register offset for ADC calibration factors configuration */
50
51 /* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ... */
52 /* the relevant bits for: */
53 /* (concatenation of multiple bits used in different registers) */
54 /* - ADC calibration configuration: configuration before calibration start */
55 /* - ADC calibration factors: register offset */
56 #define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
57 #define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
58 #define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
59 #define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
60 #define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of
61 calibration mode: 0 for offset,
62 1 for linearity */
63 /* Internal algorithm for resolution parameters */
64 /* ADC instances ADC1, ADC2 and ADC4 do not have same resolution and same bitfield value for equivalent resolution
65 in ADC bitfield ADC_CFGR1_RES_1 */
66 #define ADC_RESOLUTION_ADC4_PROCESSING (1UL) /* Value to be subtracted to literals LL_ADC_RESOLUTION_xB
67 to have equivalent setting for ADC4 */
68
69 /* Internal mask for ADC group regular sequencer: */
70 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
71 /* - sequencer register offset */
72 /* - sequencer rank bits position into the selected register */
73
74 /* Internal register offset for ADC group regular sequencer configuration */
75 /* (offset placed into a spare area of literal definition) */
76 #define ADC_SQR1_REGOFFSET (0x00000000UL)
77 #define ADC_SQR2_REGOFFSET (0x00000100UL)
78 #define ADC_SQR3_REGOFFSET (0x00000200UL)
79 #define ADC_SQR4_REGOFFSET (0x00000300UL)
80
81 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET\
82 | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
83 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
84 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
85
86 /* Definition of ADC group regular sequencer bits information to be inserted */
87 /* into ADC group regular sequencer ranks literals definition. */
88 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR1_SQ1" position in register */
89 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR1_SQ2" position in register */
90 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR1_SQ3" position in register */
91 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR1_SQ4" position in register */
92 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR2_SQ5" position in register */
93 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR2_SQ6" position in register */
94 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR2_SQ7" position in register */
95 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR2_SQ8" position in register */
96 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR2_SQ9" position in register */
97 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR3_SQ10" position in register */
98 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR3_SQ11" position in register */
99 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR3_SQ12" position in register */
100 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR3_SQ13" position in register */
101 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR3_SQ14" position in register */
102 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR4_SQ15" position in register */
103 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR4_SQ16" position in register */
104
105 #define ADC4_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ1" position in register */
106 #define ADC4_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ2" position in register */
107 #define ADC4_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ3" position in register */
108 #define ADC4_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ4" position in register */
109 #define ADC4_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ5" position in register */
110 #define ADC4_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ6" position in register */
111 #define ADC4_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ7" position in register */
112 #define ADC4_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ8" position in register */
113
114 /* Internal mask for ADC group injected sequencer: */
115 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
116 /* - data register offset */
117 /* - sequencer rank bits position into the selected register */
118
119 /* Internal register offset for ADC group injected data register */
120 /* (offset placed into a spare area of literal definition) */
121 #define ADC_JDR1_REGOFFSET (0x00000000UL)
122 #define ADC_JDR2_REGOFFSET (0x00000100UL)
123 #define ADC_JDR3_REGOFFSET (0x00000200UL)
124 #define ADC_JDR4_REGOFFSET (0x00000300UL)
125
126 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET\
127 | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
128 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
129 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
130
131 /* Definition of ADC group injected sequencer bits information to be inserted */
132 /* into ADC group injected sequencer ranks literals definition. */
133 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
134 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
135 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
136 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
137
138 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_TR1_HT1" position in register */
139 #define ADC4_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL0" position in register */
140 #define ADC4_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL1" position in register */
141 #define ADC4_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL2" position in register */
142 #define ADC4_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL3" position in register */
143 #define ADC4_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL4" position in register */
144 #define ADC4_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL5" position in register */
145 #define ADC4_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL6" position in register */
146 #define ADC4_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL7" position in register */
147 #define ADC4_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL8" position in register */
148 #define ADC4_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL9" position in register */
149 #define ADC4_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL10" position in register */
150 #define ADC4_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL11" position in register */
151 #define ADC4_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL12" position in register */
152 #define ADC4_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL13" position in register */
153 #define ADC4_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL14" position in register */
154 #define ADC4_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL15" position in register */
155 #define ADC4_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL16" position in register */
156 #define ADC4_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL17" position in register */
157 #define ADC4_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL18" position in register */
158 #define ADC4_CHSELR_CHSEL19_BITOFFSET_POS (19UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL19" position in register */
159 #define ADC4_CHSELR_CHSEL20_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL20" position in register */
160 #define ADC4_CHSELR_CHSEL21_BITOFFSET_POS (21UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL21" position in register */
161 #define ADC4_CHSELR_CHSEL22_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL22" position in register */
162 #define ADC4_CHSELR_CHSEL23_BITOFFSET_POS (23UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL23" position in register */
163 #define ADC4_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_SMPR_SMP1" position in register */
164 #define ADC4_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_SMPR_SMP2" position in register */
165 #define ADC4_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_SMPR_SMPSEL0" position in register */
166
167 /* Internal mask for ADC group regular trigger: */
168 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
169 /* - regular trigger source */
170 /* - regular trigger edge */
171 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting
172 for compatibility with some ADC on other STM32
173 families having this setting set by HW default value) */
174
175 /* Mask containing trigger source masks for each of possible */
176 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
177 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
178 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
179 ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
180 ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
181 ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
182
183 #define ADC4_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC4_CFGR1_EXTSEL) << (4U * 0UL)) | \
184 ((ADC4_CFGR1_EXTSEL) << (4U * 1UL)) | \
185 ((ADC4_CFGR1_EXTSEL) << (4U * 2UL)) | \
186 ((ADC4_CFGR1_EXTSEL) << (4U * 3UL)) )
187
188 /* Mask containing trigger edge masks for each of possible */
189 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
190 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
191 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
192 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
193 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
194 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
195
196 /* Definition of ADC group regular trigger bits information. */
197 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTSEL"
198 position in register */
199 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTEN"
200 position in register */
201
202 /* Internal mask for ADC group injected trigger: */
203 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
204 /* - injected trigger source */
205 /* - injected trigger edge */
206 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
207 compatibility with some ADC on other STM32 families
208 having this setting set by HW default value) */
209
210 /* Mask containing trigger source masks for each of possible */
211 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
212 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
213 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
214 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
215 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
216 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
217
218 /* Mask containing trigger edge masks for each of possible */
219 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
220 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
221 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
222 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
223 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
224 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
225
226 /* Definition of ADC group injected trigger bits information. */
227 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL"
228 position in register */
229 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN"
230 position in register */
231
232 /* Internal mask for ADC channel: */
233 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
234 /* - channel identifier defined by number */
235 /* - channel identifier defined by bitfield */
236 /* - channel differentiation between external channels (connected to */
237 /* GPIO pins) and internal channels (connected to internal paths) */
238 /* - channel sampling time defined by SMPRx register offset */
239 /* and SMPx bits positions into SMPRx register */
240 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
241 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
242 #define ADC_CHANNEL_ID_OFFSET_NUMBER_MASK (ADC_OFR1_OFFSET1_CH)
243 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
244 position in register */
245 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
246 | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK
247 aligned on register LSB (bit 0) */
248 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >>
249 [Position of bitfield "ADC_CHANNEL_NUMBER_MASK"
250 in register]) */
251
252 /* Channel differentiation between external and internal channels */
253 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
254 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
255
256 /* Internal register offset for ADC channel sampling time configuration */
257 /* (offset placed into a spare area of literal definition) */
258 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
259 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
260 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
261 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in
262 ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
263
264 #define ADC4_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
265 #define ADC4_SAMPLING_TIME_CH_MASK (ADC4_CHANNEL_ID_BITFIELD_MASK << ADC4_SMPR_SMPSEL0_BITOFFSET_POS)
266 #define ADC4_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 \
267 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to
268 ADC_CHANNEL_ID_NUMBER_MASK with
269 reduced range: on this STM32 series,
270 ADC group regular sequencer, if set
271 to mode "fully configurable", can
272 contain channels with a restricted
273 channel number. */
274
275 /* Definition of channels ID number information to be inserted into */
276 /* channels literals definition. */
277 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
278 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
279 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
280 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
281 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
282 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
283 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
284 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
285 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
286 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
287 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
288 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
289 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
290 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
291 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
292 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
293 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
294 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
295 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
296 #define ADC_CHANNEL_19_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
297 #if defined(ADC4)
298 #define ADC_CHANNEL_20_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 )
299 #define ADC_CHANNEL_21_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
300 #define ADC_CHANNEL_22_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
301 #define ADC_CHANNEL_23_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
302 #endif /* ADC4 */
303 /* Definition of channels ID bitfield information to be inserted into */
304 /* channels literals definition. */
305 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
306 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
307 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
308 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
309 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
310 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
311 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
312 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
313 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
314 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
315 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
316 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
317 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
318 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
319 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
320 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
321 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
322 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
323 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
324 #define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
325 #define ADC_CHANNEL_20_BITFIELD (ADC_AWD2CR_AWD2CH_20)
326 #define ADC_CHANNEL_21_BITFIELD (ADC_AWD2CR_AWD2CH_21)
327 #define ADC_CHANNEL_22_BITFIELD (ADC_AWD2CR_AWD2CH_22)
328 #define ADC_CHANNEL_23_BITFIELD (ADC_AWD2CR_AWD2CH_23)
329
330 #define ADC4_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
331 #define ADC4_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
332 #define ADC4_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
333 #define ADC4_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
334 #define ADC4_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
335 #define ADC4_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
336 #define ADC4_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
337 #define ADC4_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
338 #define ADC4_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
339 #define ADC4_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
340 #define ADC4_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
341 #define ADC4_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
342 #define ADC4_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
343 #define ADC4_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
344 #define ADC4_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
345 #define ADC4_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
346 #define ADC4_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
347 #define ADC4_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
348 #define ADC4_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
349 #define ADC4_CHANNEL_19_BITFIELD (ADC_CHSELR_CHSEL19)
350 #define ADC4_CHANNEL_20_BITFIELD (ADC_CHSELR_CHSEL20)
351 #define ADC4_CHANNEL_21_BITFIELD (ADC_CHSELR_CHSEL21)
352 #define ADC4_CHANNEL_22_BITFIELD (ADC_CHSELR_CHSEL22)
353 #define ADC4_CHANNEL_23_BITFIELD (ADC_CHSELR_CHSEL23)
354
355 /* Definition of channels sampling time information to be inserted into */
356 /* channels literals definition. */
357 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP0" register */
358 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP1" register */
359 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP2" register */
360 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP3" register */
361 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP4" register */
362 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP5" register */
363 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP6" register */
364 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP7" register */
365 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP8" register */
366 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP9" register */
367 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP10" register */
368 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP11" register */
369 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP12" register */
370 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP13" register */
371 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP14" register */
372 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP15" register */
373 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP16" register */
374 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP17" register */
375 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP18" register */
376 #define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP19" register */
377 #define ADC_CHANNEL_20_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP20" register */
378 #define ADC_CHANNEL_21_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP21" register */
379 #define ADC_CHANNEL_22_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP22" register */
380 #define ADC_CHANNEL_23_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP23" register */
381
382 /* Internal mask for ADC mode single or differential ended: */
383 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
384 /* the relevant bits for: */
385 /* (concatenation of multiple bits used in different registers) */
386 /* - ADC calibration: calibration start, calibration factor get or set */
387 /* - ADC channels: set each ADC channel ending mode */
388 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT2_CALFACT)
389 #define ADC_CALFACT2_CALFACT_S (0x0000FFFFUL)
390 #define ADC_CALFACT2_CALFACT_D (0xFFFF0000UL)
391 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
392 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_I_APB_ADDR_4 \
393 | ADC_CALFACT_I_APB_ADDR_3) /* Bits chosen to perform of shift when single
394 mode is selected, shift value out of
395 channels bits range. */
396 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
397 mask of bit */
398 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode:
399 position of bit */
400 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
401 ADC_SINGLEDIFF_CALIB_F_BIT_D
402 to position to perform a shift
403 of 4 ranks */
404
405 /* Internal mask for ADC analog watchdog: */
406 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
407 /* (concatenation of multiple bits used in different analog watchdogs, */
408 /* (feature of several watchdogs not available on all STM32 families)). */
409 /* - analog watchdog 1: monitored channel defined by number, */
410 /* selection of ADC group (ADC groups regular and-or injected). */
411 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
412 /* selection on groups. */
413
414 /* Internal register offset for ADC analog watchdog channel configuration */
415 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
416 #define ADC_AWD_CR2_REGOFFSET (0x01000000UL)
417 #define ADC_AWD_CR3_REGOFFSET (0x02000000UL)
418
419 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
420 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
421 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
422 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
423
424 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
425
426 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
427 #define ADC_AWD_CHANNEL_MASK (ADC_CHANNEL_ID_NUMBER_MASK)
428 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
429 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
430
431 #define ADC_AWD_CRX_REGOFFSET_POS (24UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK*/
432
433 /* Internal register offset for ADC analog watchdog threshold configuration */
434 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
435 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
436 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
437 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
438 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in
439 ADC_AWD_TRX_REGOFFSET_MASK */
440
441 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
442 threshold high: mask of bit */
443 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
444 threshold high: position of bit */
445 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH
446 to position to perform a shift of 4 ranks */
447 #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
448
449 /* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
450 /* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
451 #define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
452 #define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
453
454 /* Legacy literals */
455 #define LL_ADC_AWD1_TR LL_ADC_AWD1
456 #define LL_ADC_AWD2_TR LL_ADC_AWD2
457 #define LL_ADC_AWD3_TR LL_ADC_AWD3
458
459 /* Internal mask for ADC offset: */
460 /* Internal register offset for ADC offset number configuration */
461 #define ADC_OFR1_REGOFFSET (0x00000000UL)
462 #define ADC_OFR2_REGOFFSET (0x00000001UL)
463 #define ADC_OFR3_REGOFFSET (0x00000002UL)
464 #define ADC_OFR4_REGOFFSET (0x00000003UL)
465 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET\
466 | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
467
468 /* ADC registers bits positions */
469 #define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR1_RES_Pos)
470 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR1_AWD1SGL_Pos)
471 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR1_AWD1EN_Pos)
472 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR1_JAWD1EN_Pos)
473
474 /* ADC instance differentiation between ADC1 and ADC4 oversampling ratio */
475 #define ADC4_OVERSAMPLING_RATIO_PARAMETER (0x80000000UL)
476 #define ADC4_OVERSAMPLING_RATIO_PARAMETER_MASK (ADC4_OVERSAMPLING_RATIO_PARAMETER)
477
478 /* ADC registers bits groups */
479 #define ADC_CR_BITS_PROPERTY_RS ( ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART \
480 | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs":
481 Software can read as well as set this bit.
482 Writing '0' has no effect on the bit value. */
483
484 /* ADC internal channels related definitions */
485 /* Internal voltage reference VrefInt */
486 #define VREFINT_CAL_ADDR ((uint16_t*) (0x0BFA07A5UL)) /* Internal voltage reference, address of parameter
487 VREFINT_CAL: VrefInt ADC raw data acquired at
488 temperature 30 DegC (tolerance: +-5 DegC),
489 Vref+ = 3.0 V (tolerance: +-10 mV). */
490 #define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which
491 VrefInt has been calibrated in production
492 (tolerance: +-10 mV) (unit: mV). */
493 /* Temperature sensor */
494 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BFA0710UL)) /* Internal temperature sensor, address of parameter
495 TS_CAL1: On STM32U5, temperature sensor ADC raw
496 data acquired at temperature 30 DegC
497 (tolerance: +-5 DegC),Vref+ = 3.0 V
498 (tolerance: +-10 mV). */
499 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BFA0742UL)) /* Internal temperature sensor, address of parameter
500 TS_CAL2: On STM32U5, temperature sensor ADC raw
501 data acquired at temperature 110 DegC
502 (tolerance: +-5 DegC), Vref+ = 3.0 V
503 (tolerance: +-10 mV). */
504 #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which
505 temperature sensor has been calibrated in
506 production for data into TEMPSENSOR_CAL1_ADDR
507 (tolerance: +-5 DegC) (unit: DegC). */
508 #define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which
509 temperature sensor has been calibrated in
510 production for data into TEMPSENSOR_CAL2_ADDR
511 (tolerance: +-5 DegC) (unit: DegC). */
512 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with
513 which temperature sensor has been calibrated in
514 production (+-10 mV) (unit: mV). */
515
516 /**
517 * @}
518 */
519
520 /* Private macros ------------------------------------------------------------*/
521 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
522 * @{
523 */
524
525 /**
526 * @brief Driver macro reserved for internal use: isolate bits with the
527 * selected mask and shift them to the register LSB
528 * (shift mask on register position bit 0).
529 * @param __BITS__ Bits in register 32 bits
530 * @param __MASK__ Mask in register 32 bits
531 * @retval Bits in register 32 bits
532 */
533 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
534 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
535
536 /**
537 * @brief Driver macro reserved for internal use: set a pointer to
538 * a register from a register basis from which an offset
539 * is applied.
540 * @param __REG__ Register basis from which the offset is applied.
541 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
542 * @retval Pointer to register address
543 */
544 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
545 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
546
547 /**
548 * @}
549 */
550
551 /* Exported types ------------------------------------------------------------*/
552 #if defined(USE_FULL_LL_DRIVER)
553 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
554 * @{
555 */
556
557 /**
558 * @brief Structure definition of some features of ADC common parameters
559 * and multimode
560 * (all ADC instances belonging to the same ADC common instance).
561 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
562 * is conditioned to ADC instances state (all ADC instances
563 * sharing the same ADC common instance):
564 * All ADC instances sharing the same ADC common instance must be
565 * disabled.
566 */
567 typedef struct
568 {
569 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
570 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
571 This feature can be modified afterwards using unitary function
572 @ref LL_ADC_SetCommonClock(). */
573
574 #if defined(ADC_MULTIMODE_SUPPORT)
575 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode
576 or multimode (for devices with several ADC instances).
577 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
578
579 This feature can be modified afterwards using unitary function
580 @ref LL_ADC_SetMultimode(). */
581
582 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
583 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
584
585 This feature can be modified afterwards using unitary function
586 @ref LL_ADC_SetMultiDMATransfer(). */
587
588 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
589 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
590
591 This feature can be modified afterwards using unitary function
592 @ref LL_ADC_SetMultiTwoSamplingDelay(). */
593 #endif /* ADC_MULTIMODE_SUPPORT */
594
595 } LL_ADC_CommonInitTypeDef;
596
597 /**
598 * @brief Structure definition of some features of ADC instance.
599 * @note These parameters have an impact on ADC scope: ADC instance.
600 * Affects both group regular and group injected (availability
601 * of ADC group injected depends on STM32 families).
602 * Refer to corresponding unitary functions into
603 * @ref ADC_LL_EF_Configuration_ADC_Instance .
604 * @note The setting of these parameters by function @ref LL_ADC_Init()
605 * is conditioned to ADC state:
606 * ADC instance must be disabled.
607 * This condition is applied to all ADC features, for efficiency
608 * and compatibility over all STM32 families. However, the different
609 * features can be set under different ADC state conditions
610 * (setting possible with ADC enabled without conversion on going,
611 * ADC enabled with conversion on going, ...)
612 * Each feature can be updated afterwards with a unitary function
613 * and potentially with ADC in a different state than disabled,
614 * refer to description of each function for setting
615 * conditioned to ADC state.
616 */
617 typedef struct
618 {
619 uint32_t Resolution; /*!< Set ADC resolution.
620 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
621 This feature can be modified afterwards using unitary function
622 @ref LL_ADC_SetResolution(). */
623
624 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
625 This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
626
627 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
628 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
629 This feature can be modified afterwards using unitary function
630 @ref LL_ADC_SetDataAlignment(). */
631
632 uint32_t LowPowerMode; /*!< Set ADC low power mode.
633 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
634 This feature can be modified afterwards using unitary function
635 @ref LL_ADC_SetLowPowerMode(). */
636
637 } LL_ADC_InitTypeDef;
638
639 /**
640 * @brief Structure definition of some features of ADC group regular.
641 * @note These parameters have an impact on ADC scope: ADC group regular.
642 * Refer to corresponding unitary functions into
643 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
644 * (functions with prefix "REG").
645 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
646 * is conditioned to ADC state:
647 * ADC instance must be disabled.
648 * This condition is applied to all ADC features, for efficiency
649 * and compatibility over all STM32 families. However, the different
650 * features can be set under different ADC state conditions
651 * (setting possible with ADC enabled without conversion on going,
652 * ADC enabled with conversion on going, ...)
653 * Each feature can be updated afterwards with a unitary function
654 * and potentially with ADC in a different state than disabled,
655 * refer to description of each function for setting
656 * conditioned to ADC state.
657 */
658 typedef struct
659 {
660 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start)
661 or from external peripheral (timer event, external interrupt line).
662 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
663 @note On this STM32 series, setting trigger source to external trigger
664 also set trigger polarity to rising edge (default setting for
665 compatibility with some ADC on other STM32 families having this
666 setting set by HW default value).
667 In case of need to modify trigger edge, use function
668 @ref LL_ADC_REG_SetTriggerEdge().
669 This feature can be modified afterwards using unitary function
670 @ref LL_ADC_REG_SetTriggerSource(). */
671
672 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
673 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
674 This feature can be modified afterwards using unitary function
675 @ref LL_ADC_REG_SetSequencerLength(). */
676
677 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
678 and scan conversions interrupted every selected number of ranks.
679 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
680 @note This parameter has an effect only if group regular sequencer is
681 enabled (scan length of 2 ranks or more).
682 This feature can be modified afterwards using unitary function
683 @ref LL_ADC_REG_SetSequencerDiscont(). */
684
685 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular,
686 whether ADC conversions are performed in single mode (one conversion per
687 trigger) or in continuous mode (after the first trigger, following
688 conversions launched successively automatically).
689 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
690 Note: It is not possible to enable both ADC group regular continuous
691 mode and discontinuous mode.
692 This feature can be modified afterwards using unitary function
693 @ref LL_ADC_REG_SetContinuousMode(). */
694
695 uint32_t DataTransferMode; /*!< Set ADC group regular conversion data transfer mode: no transfer,
696 transfer by DMA (Limited/Unlimited) or MDF.
697 This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE
698 This feature can be modified afterwards using unitary function
699 @ref LL_ADC_REG_SetDataTransferMode(). */
700
701 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
702 by DMA, and DMA requests mode.
703 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
704 This feature can be modified afterwards using unitary function
705 @ref LL_ADC_REG_SetDMATransfer(). */
706
707 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
708 data preserved or overwritten.
709 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
710 This feature can be modified afterwards using unitary function
711 @ref LL_ADC_REG_SetOverrun(). */
712
713 } LL_ADC_REG_InitTypeDef;
714
715 /**
716 * @brief Structure definition of some features of ADC group injected.
717 * @note These parameters have an impact on ADC scope: ADC group injected.
718 * Refer to corresponding unitary functions into
719 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
720 * (functions with prefix "INJ").
721 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
722 * is conditioned to ADC state:
723 * ADC instance must be disabled.
724 * This condition is applied to all ADC features, for efficiency
725 * and compatibility over all STM32 families. However, the different
726 * features can be set under different ADC state conditions
727 * (setting possible with ADC enabled without conversion on going,
728 * ADC enabled with conversion on going, ...)
729 * Each feature can be updated afterwards with a unitary function
730 * and potentially with ADC in a different state than disabled,
731 * refer to description of each function for setting
732 * conditioned to ADC state.
733 */
734 typedef struct
735 {
736 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start)
737 or from external peripheral (timer event, external interrupt line).
738 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
739 @note On this STM32 series, setting trigger source to external trigger
740 also set trigger polarity to rising edge (default setting for
741 compatibility with some ADC on other STM32 families having this
742 setting set by HW default value).
743 In case of need to modify trigger edge, use function
744 @ref LL_ADC_INJ_SetTriggerEdge().
745 This feature can be modified afterwards using unitary function
746 @ref LL_ADC_INJ_SetTriggerSource(). */
747
748 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
749 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
750 This feature can be modified afterwards using unitary function
751 @ref LL_ADC_INJ_SetSequencerLength(). */
752
753 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
754 and scan conversions interrupted every selected number of ranks.
755 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
756 @note This parameter has an effect only if group injected sequencer
757 is enabled (scan length of 2 ranks or more).
758 This feature can be modified afterwards using unitary function
759 @ref LL_ADC_INJ_SetSequencerDiscont(). */
760
761 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
762 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
763 Note: This parameter must be set to set to independent trigger if injected
764 trigger source is set to an external trigger.
765 This feature can be modified afterwards using unitary function
766 @ref LL_ADC_INJ_SetTrigAuto(). */
767
768 } LL_ADC_INJ_InitTypeDef;
769
770 /**
771 * @}
772 */
773 #endif /* USE_FULL_LL_DRIVER */
774
775 /* Exported constants --------------------------------------------------------*/
776 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
777 * @{
778 */
779
780 /** @defgroup ADC_LL_EC_FLAG ADC flags
781 * @brief Flags defines which can be used with LL_ADC_ReadReg function
782 * @{
783 */
784 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
785 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
786 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
787 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
788 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
789 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
790 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
791 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
792 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
793 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
794 #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
795 #define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC flag Voltage Regulator (LDO) Ready */
796
797 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
798 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
799 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end
800 of unitary conversion */
801 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end
802 of unitary conversion */
803 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end
804 of sequence conversions */
805 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end
806 of sequence conversions */
807 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
808 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
809 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end
810 of sampling phase */
811 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end
812 of sampling phase */
813 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end
814 of unitary conversion */
815 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end
816 of unitary conversion */
817 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end
818 of sequence conversions */
819 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end
820 of sequence conversions */
821 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1
822 of the ADC master */
823 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1
824 of the ADC slave */
825 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2
826 of the ADC master */
827 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2
828 of the ADC slave */
829 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3
830 of the ADC master */
831 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3
832 of the ADC slave */
833 /**
834 * @}
835 */
836
837 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
838 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
839 * @{
840 */
841 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
842 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of
843 unitary conversion */
844 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of
845 sequence conversions */
846 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
847 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of
848 sampling phase */
849 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of
850 unitary conversion */
851 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of
852 sequence conversions */
853 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
854 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
855 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
856 #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
857 #define LL_ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC interruption ADC Voltage Regulator (LDO) Ready */
858 /**
859 * @}
860 */
861
862 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
863 * @{
864 */
865 /* List of ADC registers intended to be used (most commonly) with */
866 /* DMA transfer. */
867 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
868 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
869 (corresponding to register DR) to be used with ADC
870 configured in independent mode. Without DMA transfer,
871 register accessed by LL function
872 @ref LL_ADC_REG_ReadConversionData32() and
873 other functions @ref LL_ADC_REG_ReadConversionDatax() */
874 #if defined(ADC_MULTIMODE_SUPPORT)
875 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register
876 (corresponding to register CDR) to be used with
877 ADC configured in multimode (available on STM32 devices
878 with several ADC instances). Without DMA transfer,
879 register accessed by LL function
880 @ref LL_ADC_REG_ReadMultiConversionData32() */
881 #endif /* ADC_MULTIMODE_SUPPORT */
882 /**
883 * @}
884 */
885
886 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
887 * @{
888 */
889 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock
890 without prescaler */
891 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
892 with prescaler division
893 by 2 */
894 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
895 with prescaler division
896 by 4 */
897 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
898 with prescaler division
899 by 6 */
900 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock
901 with prescaler division
902 by 8 */
903 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
904 with prescaler division
905 by 10 */
906 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
907 with prescaler division
908 by 12 */
909 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
910 with prescaler division
911 by 16 */
912 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock
913 with prescaler division
914 by 32 */
915 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
916 with prescaler division
917 by 64 */
918 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
919 with prescaler division
920 by 128 */
921 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
922 with prescaler division
923 by 256 */
924 /**
925 * @}
926 */
927
928 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
929 * @{
930 */
931 /* Note: Other measurement paths to internal channels may be available */
932 /* (connections to other peripherals). */
933 /* If they are not listed below, they do not require any specific */
934 /* path enable. In this case, Access to measurement path is done */
935 /* only by selecting the corresponding ADC internal channel. */
936 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
937 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
938 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN) /*!< ADC measurement path to internal channel
939 temperature sensor */
940 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
941
942 #define LL_ADC_PATH_INTERNAL_VCORE (LL_ADC_PATH_INTERNAL_VREFINT \
943 | LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE) /*!< ADC measurement path
944 to internal channel VCore */
945 /**
946 * @}
947 */
948
949 /** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY ADC instance - Calibration mode for offset and linearity
950 * @{
951 */
952 #define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET) /*!< Calibration of ADC offset.
953 Duration of calibration of offset
954 duration: 1280 ADC clock cycles.
955 For devices with differential mode
956 available: Calibration of offset
957 is specific to each of single-ended
958 and differential modes. */
959 #define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)/*!< Calibration of ADC linearity.
960 Duration of calibration of
961 linearity: 15104 ADC clock cycles.
962 For devices with differential mode
963 available: Calibration of linearity
964 is common to both single-ended and
965 differential modes. */
966 #define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET \
967 | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and
968 linearity. Duration of calibration
969 of offset and linearity: 16384 ADC
970 clock cycles. For devices with
971 differential mode available:
972 Calibration of offset is specific
973 to each of single-ended and
974 differential modes, calibration of
975 linearity is common to both
976 single-ended and differential modes. */
977 /**
978 * @}
979 */
980
981 /** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_INDEX ADC indexes for linear calibration
982 * @{
983 */
984 #define LL_ADC_CALIB_OFFSET_INDEX (0x00000000UL) /*!< Offset Calibration Index */
985 #define LL_ADC_CALIB_LINEARITY_INDEX1 (ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 1*/
986 #define LL_ADC_CALIB_LINEARITY_INDEX2 (ADC_CR_CALINDEX1) /*!< Linearity Calibration Index 2*/
987 #define LL_ADC_CALIB_LINEARITY_INDEX3 (ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 3*/
988 #define LL_ADC_CALIB_LINEARITY_INDEX4 (ADC_CR_CALINDEX2) /*!< Linearity Calibration Index 4*/
989 #define LL_ADC_CALIB_LINEARITY_INDEX5 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 5*/
990 #define LL_ADC_CALIB_LINEARITY_INDEX6 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1) /*!< Linearity Calibration Index 6*/
991 #define LL_ADC_CALIB_LINEARITY_INDEX7 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 \
992 | ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 7*/
993 #define LL_ADC_CALIB_INTEROFFSET_INDEX (ADC_CR_CALINDEX3) /*!< Linearity Calibration Index 8*/
994 /**
995 * @}
996 */
997
998 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
999 * @{
1000 */
1001 #define LL_ADC_RESOLUTION_14B (0x00000000UL) /*!< ADC resolution 14 bits (ADC1, ADC2 only) */
1002 #define LL_ADC_RESOLUTION_12B ( ADC_CFGR1_RES_0) /*!< ADC resolution 12 bits */
1003 #define LL_ADC_RESOLUTION_10B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 10 bits */
1004 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 8 bits */
1005 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 \
1006 << ADC_RESOLUTION_ADC4_PROCESSING) /*!< ADC resolution 6 bits (ADC4 only)
1007 (value shift out of ADC_CFGR1_RES range,
1008 post-processing when applied with ADC4) */
1009
1010 /* Legacy literals */
1011 #define LL_ADC_RESOLUTION_12B_ADC4 LL_ADC_RESOLUTION_12B
1012 #define LL_ADC_RESOLUTION_10B_ADC4 LL_ADC_RESOLUTION_10B
1013 #define LL_ADC_RESOLUTION_8B_ADC4 LL_ADC_RESOLUTION_8B
1014 #define LL_ADC_RESOLUTION_6B_ADC4 LL_ADC_RESOLUTION_6B
1015 /**
1016 * @}
1017 */
1018 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
1019 * @{
1020 */
1021 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
1022 (alignment on data register LSB bit 0)*/
1023 #define LL_ADC_DATA_ALIGN_LEFT (ADC4_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned
1024 (alignment on data register MSB bit 15)*/
1025 /**
1026 * @}
1027 */
1028
1029 /** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
1030 * @{
1031 */
1032 #define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC conversion data */
1033 #define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC conversion data */
1034 #define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC conversion data */
1035 #define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC conversion data */
1036 #define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC conversion data */
1037 #define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC conversion data */
1038 #define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC conversion data */
1039 #define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC conversion data */
1040 #define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC conversion data */
1041 #define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC conversion data */
1042 #define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC conversion data */
1043 #define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC conversion data */
1044 #define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC conversion data */
1045 #define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC conversion data */
1046 #define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC conversion data */
1047 #define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC conversion data */
1048 /**
1049 * @}
1050 */
1051
1052 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
1053 * @{
1054 */
1055 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
1056 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
1057 /**
1058 * @}
1059 */
1060
1061 /** @defgroup ADC_LL_EC_AUTOPOWEROFF_MODE ADC instance - Low power mode auto power-off
1062 * @{
1063 */
1064 #define LL_ADC_LP_AUTOPOWEROFF_DISABLE (0x00000000UL) /*!< ADC low power mode auto power-off disabled */
1065 #define LL_ADC_LP_AUTOPOWEROFF_ENABLE (ADC4_PWRR_AUTOFF) /*!< ADC low power mode auto power-off enabled: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLPModeAutoPowerOff(). It can be combined with mode low power mode auto wait. */
1066 /**
1067 * @}
1068 */
1069
1070 /** @defgroup ADC_LL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE ADC instance - Autonomous deep power down mode
1071 * @{
1072 */
1073 #define LL_ADC_LP_AUTONOMOUS_DPD_DISABLE (0x00000000UL) /*!< ADC deep power down in autonomous mode disabled */
1074 #define LL_ADC_LP_AUTONOMOUS_DPD_ENABLE (ADC4_PWRR_DPD) /*!< ADC deep power down in autonomous mode enabled */
1075 /**
1076 * @}
1077 */
1078
1079 /** @defgroup ADC_LL_EC_VREF_PROTECTION_MODE ADC instance - VREF protection mode
1080 * @{
1081 */
1082 #define LL_ADC_VREF_PROT_DISABLE (0x00000000UL) /*!< ADC Vref+ protection disabled */
1083 #define LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE (ADC4_PWRR_VREFPROT) /*!< ADC Vref+ protection enabled: In case of simultaneous sampling phase of ADC4 and ADC1/2, ADC4 is put on hold during one ADC4 clock cycle to avoid noise on Vref+. */
1084 #define LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE (ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP) /*!< ADC Vref+ protection enabled: In case of simultaneous sampling phase of ADC4 and ADC1/2, ADC4 is put on hold during two ADC4 clock cycles to avoid noise on Vref+. */
1085 /**
1086 * @}
1087 */
1088
1089 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
1090 * @{
1091 */
1092 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
1093 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
1094 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
1095 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
1096 /**
1097 * @}
1098 */
1099
1100 /** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode
1101 * @{
1102 */
1103 #define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
1104 #define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSAT) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
1105 /**
1106 * @}
1107 */
1108
1109 /** @defgroup ADC_LL_EC_OFFSET_UNSIGNED_SATURATION ADC instance - Offset unsigned saturation mode
1110 * @{
1111 */
1112 #define LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset unsigned saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
1113 #define LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE (ADC_OFR1_USAT) /*!< ADC offset unsigned saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
1114 /**
1115 * @}
1116 */
1117
1118 /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
1119 * @{
1120 */
1121 #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4) */
1122 #define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4) */
1123 /**
1124 * @}
1125 */
1126
1127 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
1128 * @{
1129 */
1130 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
1131 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
1132 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
1133 /**
1134 * @}
1135 */
1136
1137 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
1138 * @{
1139 */
1140 #define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC4_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
1141 #define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC4_SMPR_SMP2_BITOFFSET_POS | ADC4_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
1142 /* Internal mask for ADC channel sampling time: */
1143 /* To select into literals LL_ADC_SAMPLINGTIME_x */
1144 /* the relevant bits for: */
1145 /* (concatenation of multiple bits used in register SMPR) */
1146 /* - ADC channels sampling time: setting channel wise, to map each channel */
1147 /* on one of the common sampling time available. */
1148 /* - ADC channels common sampling time: set a sampling time into one of the */
1149 /* common sampling time available. */
1150 #define ADC4_SAMPLING_TIME_SMP_MASK (ADC4_SMPR_SMP2 | ADC4_SMPR_SMP1)
1151 #define ADC4_SAMPLING_TIME_SMP_SHIFT_MASK (ADC4_SMPR_SMP2_BITOFFSET_POS | ADC4_SMPR_SMP1_BITOFFSET_POS)
1152
1153 /**
1154 * @}
1155 */
1156
1157 /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
1158 * @{
1159 */
1160 #define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
1161 #define LL_ADC_TRIGGER_FREQ_LOW (ADC4_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
1162 /**
1163 * @}
1164 */
1165
1166 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
1167 * @{
1168 */
1169 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
1170 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
1171 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
1172 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
1173 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
1174 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
1175 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
1176 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
1177 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
1178 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
1179 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
1180 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
1181 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
1182 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
1183 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
1184 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
1185 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
1186 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
1187 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
1188 #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
1189 #define LL_ADC_CHANNEL_20 (ADC_CHANNEL_20_NUMBER | ADC_CHANNEL_20_SMP | ADC_CHANNEL_20_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20 */
1190 #define LL_ADC_CHANNEL_21 (ADC_CHANNEL_21_NUMBER | ADC_CHANNEL_21_SMP | ADC_CHANNEL_21_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21 */
1191 #define LL_ADC_CHANNEL_22 (ADC_CHANNEL_22_NUMBER | ADC_CHANNEL_22_SMP | ADC_CHANNEL_22_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22 */
1192 #define LL_ADC_CHANNEL_23 (ADC_CHANNEL_23_NUMBER | ADC_CHANNEL_23_SMP | ADC_CHANNEL_23_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN23 */
1193
1194 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. . */
1195 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
1196 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. */
1197
1198 #define LL_ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vcore. On STM32U5, ADC channel available only on ADC instance: ADC4. */
1199 #define LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32U5, ADC channel available only on ADC instance: ADC4. */
1200 #define LL_ADC_CHANNEL_VBAT_ADC4 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32U5, ADC channel available only on ADC instance: ADC4. */
1201 #define LL_ADC_CHANNEL_DAC1CH1_ADC4 (LL_ADC_CHANNEL_21 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC4 */
1202 #define LL_ADC_CHANNEL_DAC1CH2_ADC4 (LL_ADC_CHANNEL_DAC1CH1_ADC4 | LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC4 */
1203
1204 #define LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE (0x01000000UL) /*!< Dummy bit for driver internal usage, not used in ADC channel setting registers CHSELR or SQRx */
1205
1206 /**
1207 * @}
1208 */
1209
1210 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
1211 * @{
1212 */
1213 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
1214 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1215 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1216 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1217 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1218 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
1219 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1220 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
1221 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
1222 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
1223 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR1_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
1224 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
1225 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
1226 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
1227 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
1228 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
1229 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
1230 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
1231 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
1232 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
1233 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
1234 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1235 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE15 (ADC_CFGR1_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 15 event. Trigger edge set to rising edge (default setting). */
1236 #define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 channel 1 event. Trigger edge set to rising edge (default setting). */
1237 #define LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
1238 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 channel 1 event. Trigger edge set to rising edge (default setting). */
1239 #define LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 channel 1 event. Trigger edge set to rising edge (default setting). */
1240 #define LL_ADC_REG_TRIG_EXT_LPTIM4_OUT (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
1241 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM4 OUT event. Trigger edge set to rising edge (default setting). */
1242
1243 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
1244 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4 (ADC4_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1245 #if defined(TIM2)
1246 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
1247 #endif /* TIM2 */
1248 #if defined(TIM15)
1249 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_1 | ADC4_CFGR1_EXTSEL_0 \
1250 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
1251 #endif /* TIM5 */
1252 #if defined(TIM6)
1253 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
1254 #endif /* TIM6 */
1255 #if defined(LPTIM1)
1256 #define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_0 \
1257 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: LPTIM1 CH1. Trigger edge set to rising edge (default setting). */
1258 #endif /* LPTIM1 */
1259 #if defined(LPTIM3)
1260 #define LL_ADC_REG_TRIG_EXT_LPTIM3_CH2_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_1 \
1261 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: LPTIM3 CH2. Trigger edge set to rising edge (default setting). */
1262 #endif /* LPTIM3 */
1263 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE15_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_1 \
1264 | ADC4_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1265
1266 /**
1267 * @}
1268 */
1269
1270 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
1271 * @{
1272 */
1273 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
1274 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
1275 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
1276 /**
1277 * @}
1278 */
1279
1280 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
1281 * @{
1282 */
1283 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
1284 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
1285 /**
1286 * @}
1287 */
1288
1289 /** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE ADC group regular - Data transfer mode of ADC conversion data
1290 * @{
1291 */
1292 #define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are transferred to DR rigister */
1293 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversion data are not transferred by DMA but to DR register */
1294 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
1295 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMNGT_1 | ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
1296 #define LL_ADC_REG_MDF_TRANSFER (ADC_CFGR1_DMNGT_1 ) /*!< ADC conversion data are transferred to DFSDM */
1297 /**
1298 * @}
1299 */
1300 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
1301 * @{
1302 */
1303 #define LL_ADC_REG_DMA_TRANSFER_NONE_ADC4 (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
1304 #define LL_ADC_REG_DMA_TRANSFER_LIMITED_ADC4 ( ADC4_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
1305 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED_ADC4 (ADC4_CFGR1_DMACFG | ADC4_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
1306 /**
1307 * @}
1308 */
1309
1310 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
1311 * @{
1312 */
1313 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
1314 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
1315 /**
1316 * @}
1317 */
1318
1319 /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
1320 * @{
1321 */
1322 #define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */
1323 #define LL_ADC_REG_SEQ_CONFIGURABLE (ADC4_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
1324 /**
1325 * @}
1326 */
1327
1328 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1329 * @{
1330 */
1331 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1332 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
1333 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
1334 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
1335 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
1336 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
1337 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
1338 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
1339 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
1340 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
1341 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
1342 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
1343 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
1344 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
1345 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
1346 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
1347 /**
1348 * @}
1349 */
1350 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1351 * @{
1352 */
1353 #define LL_ADC4_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1354 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
1355 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
1356 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
1357 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
1358 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
1359 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
1360 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
1361 /**
1362 * @}
1363 */
1364
1365 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1366 * @{
1367 */
1368 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
1369 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
1370 #define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
1371 #define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
1372 #define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
1373 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
1374 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
1375 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
1376 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 \
1377 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
1378 /**
1379 * @}
1380 */
1381
1382 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
1383 * @{
1384 */
1385 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
1386 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC4_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
1387 /**
1388 * @}
1389 */
1390
1391 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1392 * @{
1393 */
1394 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1395 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1396 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1397 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1398 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1399 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1400 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1401 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1402 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
1403 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
1404 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
1405 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
1406 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
1407 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
1408 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
1409 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
1410
1411 #define LL_ADC_REG_RANK_1_ADC4 (ADC4_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1412 #define LL_ADC_REG_RANK_2_ADC4 (ADC4_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1413 #define LL_ADC_REG_RANK_3_ADC4 (ADC4_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1414 #define LL_ADC_REG_RANK_4_ADC4 (ADC4_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1415 #define LL_ADC_REG_RANK_5_ADC4 (ADC4_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1416 #define LL_ADC_REG_RANK_6_ADC4 (ADC4_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1417 #define LL_ADC_REG_RANK_7_ADC4 (ADC4_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1418 #define LL_ADC_REG_RANK_8_ADC4 (ADC4_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1419 /**
1420 * @}
1421 */
1422
1423 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1424 * @{
1425 */
1426 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */
1427 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
1428 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1429 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
1430 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1431 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1432 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
1433 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1434 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1435 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1436 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
1437 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
1438 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
1439 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1440 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1441 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
1442 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
1443 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1444 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
1445 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
1446 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
1447 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
1448 #define LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
1449 #define LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
1450 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
1451 #define LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1452 #define LL_ADC_INJ_TRIG_EXT_LPTIM4_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
1453 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1454
1455 /**
1456 * @}
1457 */
1458
1459 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1460 * @{
1461 */
1462 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
1463 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
1464 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
1465 /**
1466 * @}
1467 */
1468
1469 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1470 * @{
1471 */
1472 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
1473 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
1474 /**
1475 * @}
1476 */
1477
1478 /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
1479 * @{
1480 */
1481 #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME. */
1482 #define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
1483 Note: First conversion is using minimal
1484 sampling time (see @ref
1485 ADC_LL_EC_CHANNEL_SAMPLINGTIME). */
1486 #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG)/*!< ADC conversions sampling phase is controlled by trigger events:
1487 Trigger rising edge = start sampling
1488 Trigger falling edge = stop sampling and
1489 start conversion. */
1490 /**
1491 * @}
1492 */
1493
1494 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1495 * @{
1496 */
1497 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1498 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1499 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1500 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1501 /**
1502 * @}
1503 */
1504
1505 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1506 * @{
1507 */
1508 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
1509 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1510 /**
1511 * @}
1512 */
1513
1514 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1515 * @{
1516 */
1517 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1518 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1519 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1520 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1521 /**
1522 * @}
1523 */
1524
1525 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1526 * @{
1527 */
1528 #define LL_ADC_SAMPLINGTIME_5CYCLES (0x00000000UL) /*!< Sampling time 5 ADC clock cycles */
1529 #define LL_ADC_SAMPLINGTIME_6CYCLES ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6 ADC clock cycles */
1530 #define LL_ADC_SAMPLINGTIME_12CYCLES ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12 ADC clock cycles */
1531 #define LL_ADC_SAMPLINGTIME_20CYCLES ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 20 ADC clock cycles */
1532 #define LL_ADC_SAMPLINGTIME_36CYCLES (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 36 ADC clock cycles */
1533 #define LL_ADC_SAMPLINGTIME_68CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 68 ADC clock cycles */
1534 #define LL_ADC_SAMPLINGTIME_391CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 391 ADC clock cycles */
1535 #define LL_ADC_SAMPLINGTIME_814CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 814 ADC clock cycles */
1536
1537 #define LL_ADC_SAMPLINGTIME_5CYCLE LL_ADC_SAMPLINGTIME_5CYCLES /*!< Keep old definition for compatibility */
1538 #define LL_ADC_SAMPLINGTIME_391CYCLES_5 LL_ADC_SAMPLINGTIME_391CYCLES /*!< Keep old definition for compatibility */
1539 /**
1540 * @}
1541 */
1542
1543 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1544 * @{
1545 */
1546 #define LL_ADC4_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
1547 #define LL_ADC4_SAMPLINGTIME_3CYCLES_5 (ADC4_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
1548 #define LL_ADC4_SAMPLINGTIME_7CYCLES_5 (ADC4_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
1549 #define LL_ADC4_SAMPLINGTIME_12CYCLES_5 (ADC4_SMPR_SMP1_1 | ADC4_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
1550 #define LL_ADC4_SAMPLINGTIME_19CYCLES_5 (ADC4_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
1551 #define LL_ADC4_SAMPLINGTIME_39CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
1552 #define LL_ADC4_SAMPLINGTIME_79CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
1553 #define LL_ADC4_SAMPLINGTIME_814CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1 | ADC4_SMPR_SMP1_0) /*!< Sampling time 814.5 ADC clock cycles */
1554
1555 #define LL_ADC4_SAMPLINGTIME_160CYCLES_5 LL_ADC4_SAMPLINGTIME_814CYCLES_5 /*!< Keep old definition for compatibility */
1556 /**
1557 * @}
1558 */
1559
1560 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1561 * @{
1562 */
1563 #define LL_ADC_SINGLE_ENDED (0x0000FFFFUL) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1564 #define LL_ADC_DIFFERENTIAL_ENDED (0xFFFF0000UL) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1565 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1566 /**
1567 * @}
1568 */
1569
1570 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1571 * @{
1572 */
1573 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1574 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1575 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1576 /**
1577 * @}
1578 */
1579
1580 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1581 * @{
1582 */
1583 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1584 #define LL_ADC_AWD_ALL_CHANNELS_REG ((0x000FFFFFUL) | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1585 #define LL_ADC_AWD_ALL_CHANNELS_INJ ((0x000FFFFFUL) | ADC_CFGR1_JAWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1586 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ((0x000FFFFFUL) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1587 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1588 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1589 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1590 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1591 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1592 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1593 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1594 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1595 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1596 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1597 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1598 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1599 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1600 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1601 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1602 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1603 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1604 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1605 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1606 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1607 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1608 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1609 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1610 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1611 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1612 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1613 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1614 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1615 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1616 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1617 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1618 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1619 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1620 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1621 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1622 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1623 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1624 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1625 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1626 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1627 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1628 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1629 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1630 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1631 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1632 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1633 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1634 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1635 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1636 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1637 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1638 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1639 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1640 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1641 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1642 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1643 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1644 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1645 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1646 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1647 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1648 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1649 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1650 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1651 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1652 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1653 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1654 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1655 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1656 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1657 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1658 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1659 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1660 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1661 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1662 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1663 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1664 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1665 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1666 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1667 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1668 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1669 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1670 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1671 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1672 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1673 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1674 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1675 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1676 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1677 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1678 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1679 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1680 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1681 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1682 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1683 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1684 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1685 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1686 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1687 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1688 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1689 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1690 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1691 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1692 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1693 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1694 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1695 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1696 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1697 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1698 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1699 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1700 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1701 #define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1702 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1703 #define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1704 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1705 #define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1706 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1707 #define LL_ADC_AWD_CHANNEL_20_REG ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1708 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1709 #define LL_ADC_AWD_CHANNEL_20_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1710 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1711 #define LL_ADC_AWD_CHANNEL_20_REG_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1712 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1713 #define LL_ADC_AWD_CHANNEL_21_REG ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1714 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1715 #define LL_ADC_AWD_CHANNEL_21_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1716 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1717 #define LL_ADC_AWD_CHANNEL_21_REG_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1718 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1719 #define LL_ADC_AWD_CHANNEL_22_REG ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1720 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1721 #define LL_ADC_AWD_CHANNEL_22_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1722 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1723 #define LL_ADC_AWD_CHANNEL_22_REG_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1724 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1725 #define LL_ADC_AWD_CHANNEL_23_REG ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
1726 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1727 #define LL_ADC_AWD_CHANNEL_23_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1728 | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1729 #define LL_ADC_AWD_CHANNEL_23_REG_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
1730 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1731 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
1732 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1733 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
1734 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1735 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
1736 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1737 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
1738 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1739 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
1740 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
1741 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
1742 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
1743 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
1744 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */
1745 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
1746 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */
1747 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
1748 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */
1749 #define LL_ADC_AWD_CH_VCORE_REG ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
1750 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1751 #define LL_ADC_AWD_CH_VCORE_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
1752 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1753 #define LL_ADC_AWD_CH_VCORE_REG_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
1754 | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1755
1756 #define LL_ADC_AWD_CH_DAC1CH1_ADC4_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
1757 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC4, converted by group regular only */
1758 #define LL_ADC_AWD_CH_DAC1CH2_ADC4_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
1759 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC4, converted by group regular only */
1760 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC4_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
1761 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to emperature sensor, channel specific to ADC4, converted by group regular only */
1762 #define LL_ADC_AWD_CH_VBAT_ADC4_REG ((LL_ADC_CHANNEL_VBAT_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
1763 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC4, converted by group regular only */
1764 /**
1765 * @}
1766 */
1767
1768 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1769 * @{
1770 */
1771 #define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */
1772 #define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */
1773 /**
1774 * @}
1775 */
1776
1777 /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
1778 * @{
1779 */
1780 #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
1781 #define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
1782 #define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_HTR_AWDFILT_1 ) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
1783 #define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
1784 #define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_HTR_AWDFILT_2 ) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
1785 #define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
1786 #define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 ) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
1787 #define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
1788 /**
1789 * @}
1790 */
1791
1792 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1793 * @{
1794 */
1795 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1796 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
1797 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1798 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
1799 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1800 /**
1801 * @}
1802 */
1803
1804 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1805 * @{
1806 */
1807 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
1808 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1809 /**
1810 * @}
1811 */
1812 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1813 * @{
1814 */
1815 #define LL_ADC_OVS_RATIO_2 (ADC4_OVERSAMPLING_RATIO_PARAMETER | 0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1816 #define LL_ADC_OVS_RATIO_4 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1817 #define LL_ADC_OVS_RATIO_8 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1818 #define LL_ADC_OVS_RATIO_16 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1819 #define LL_ADC_OVS_RATIO_32 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1820 #define LL_ADC_OVS_RATIO_64 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1821 #define LL_ADC_OVS_RATIO_128 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1822 #define LL_ADC_OVS_RATIO_256 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1823 /**
1824 * @}
1825 */
1826
1827 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
1828 * @{
1829 */
1830 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
1831 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
1832 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
1833 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
1834 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
1835 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
1836 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
1837 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
1838 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
1839 #define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
1840 #define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
1841 #define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
1842 /**
1843 * @}
1844 */
1845
1846 #if defined(ADC_MULTIMODE_SUPPORT)
1847 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1848 * @{
1849 */
1850 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
1851 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1852 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1853 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1854 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1855 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1856 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1857 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1858 /**
1859 * @}
1860 */
1861
1862 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1863 * @{
1864 */
1865 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1866 #define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */
1867 #define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */
1868 /**
1869 * @}
1870 */
1871
1872 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1873 * @{
1874 */
1875 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle for all resolution */
1876 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles for all resolution */
1877 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles for all resolution */
1878 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles for all resolution */
1879 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles for all resolution */
1880 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for all resolution */
1881 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles for all resolution */
1882 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for all resolution */
1883 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for all resolution */
1884 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles for all resolution */
1885 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles for all resolution */
1886 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles for all resolution */
1887 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles for all resolution */
1888 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles for 8 bits resolution */
1889 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles for all resolution */
1890 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles for all resolution */
1891 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles for 10 bits resolution */
1892 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles for all resolution */
1893 /**
1894 * @}
1895 */
1896
1897 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1898 * @{
1899 */
1900 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1901 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1902 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1903 /**
1904 * @}
1905 */
1906
1907 #endif /* ADC_MULTIMODE_SUPPORT */
1908
1909 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1910 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1911 * not timeout values.
1912 * For details on delays values, refer to descriptions in source code
1913 * above each literal definition.
1914 * @{
1915 */
1916
1917 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1918 /* not timeout values. */
1919 /* Timeout values for ADC operations are dependent to device clock */
1920 /* configuration (system clock versus ADC clock), */
1921 /* and therefore must be defined in user application. */
1922 /* Indications for estimation of ADC timeout delays, for this */
1923 /* STM32 series: */
1924 /* - ADC calibration time: maximum delay is 16384/fADC. */
1925 /* (refer to device datasheet, parameter "tCAL") */
1926 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1927 /* (refer to device datasheet, parameter "tSTAB") */
1928 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1929 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1930 /* cycles */
1931 /* - ADC conversion time: duration depending on ADC clock and ADC */
1932 /* configuration. */
1933 /* (refer to device reference manual, section "Timing") */
1934
1935 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1936 /* Delay set to maximum value (refer to device datasheet, */
1937 /* parameter "tADCVREG_STUP"). */
1938 /* Unit: us */
1939 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1940
1941 /* Delay for internal voltage reference stabilization time. */
1942 /* Delay set to maximum value (refer to device datasheet, */
1943 /* parameter "ts_vrefint"). */
1944 /* Unit: us */
1945 #define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */
1946
1947 /* Delay for temperature sensor stabilization time. */
1948 /* Literal set to maximum value (refer to device datasheet, */
1949 /* parameter "tSTART_RUN"). */
1950 /* Unit: us */
1951 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
1952
1953 /* Delay required between ADC end of calibration and ADC enable. */
1954 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1955 /* are required between ADC end of calibration and ADC enable. */
1956 /* Wait time can be computed in user application by waiting for the */
1957 /* equivalent number of CPU cycles, by taking into account */
1958 /* ratio of CPU clock versus ADC clock prescalers. */
1959 /* Unit: ADC clock cycles. */
1960 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
1961
1962 /* Fixed timeout value for ADC linearity word bit set/clear delay. */
1963 /* Values defined to be higher than worst cases: maximum ratio between ADC */
1964 /* and CPU clock frequencies. */
1965 /* Example of profile low frequency : ADC frequency minimum 140kHz (cf */
1966 /* datasheet for ADC4), CPU frequency 160MHz. */
1967 /* Calibration time max = 25502 / fADC (refer to datasheet) */
1968 /* = 29M CPU cycles */
1969 #define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (29000000UL) /*!< ADC linearity calibration set/clear bit delay */
1970
1971 /**
1972 * @}
1973 */
1974
1975 /**
1976 * @}
1977 */
1978
1979 /* Exported macro ------------------------------------------------------------*/
1980 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1981 * @{
1982 */
1983
1984 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1985 * @{
1986 */
1987
1988 /**
1989 * @brief Write a value in ADC register
1990 * @param __INSTANCE__ ADC Instance
1991 * @param __REG__ Register to be written
1992 * @param __VALUE__ Value to be written in the register
1993 * @retval None
1994 */
1995 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1996
1997 /**
1998 * @brief Read a value in ADC register
1999 * @param __INSTANCE__ ADC Instance
2000 * @param __REG__ Register to be read
2001 * @retval Register value
2002 */
2003 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2004 /**
2005 * @}
2006 */
2007
2008 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
2009 * @{
2010 */
2011
2012 /**
2013 * @brief Helper macro to get ADC channel number in decimal format
2014 * from literals LL_ADC_CHANNEL_x.
2015 * @note Example:
2016 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
2017 * will return decimal number "4".
2018 * @note The input can be a value from functions where a channel
2019 * number is returned, either defined with number
2020 * or with bitfield (only one bit must be set).
2021 * @param __CHANNEL__ This parameter can be one of the following values:
2022 * @arg @ref LL_ADC_CHANNEL_0 (3)
2023 * @arg @ref LL_ADC_CHANNEL_1 (3)
2024 * @arg @ref LL_ADC_CHANNEL_2 (3)
2025 * @arg @ref LL_ADC_CHANNEL_3 (3)
2026 * @arg @ref LL_ADC_CHANNEL_4 (3)
2027 * @arg @ref LL_ADC_CHANNEL_5 (3)
2028 * @arg @ref LL_ADC_CHANNEL_6
2029 * @arg @ref LL_ADC_CHANNEL_7
2030 * @arg @ref LL_ADC_CHANNEL_8
2031 * @arg @ref LL_ADC_CHANNEL_9
2032 * @arg @ref LL_ADC_CHANNEL_10
2033 * @arg @ref LL_ADC_CHANNEL_11
2034 * @arg @ref LL_ADC_CHANNEL_12
2035 * @arg @ref LL_ADC_CHANNEL_13
2036 * @arg @ref LL_ADC_CHANNEL_14
2037 * @arg @ref LL_ADC_CHANNEL_15
2038 * @arg @ref LL_ADC_CHANNEL_16
2039 * @arg @ref LL_ADC_CHANNEL_17
2040 * @arg @ref LL_ADC_CHANNEL_18
2041 * @arg @ref LL_ADC_CHANNEL_19
2042 * @arg @ref LL_ADC_CHANNEL_VREFINT
2043 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2044 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2045 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2046 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2047 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2048 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2049 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2050 *
2051 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2052 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2053 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2054 * Other channels are slow channels (conversion rate: refer to reference manual).
2055 * @retval Value between Min_Data=0 and Max_Data=18
2056 */
2057 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
2058 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
2059 ? ( ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ) \
2060 : ( (uint32_t)POSITION_VAL((__CHANNEL__)) ) \
2061 )
2062
2063 /**
2064 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
2065 * from number in decimal format.
2066 * @note Example:
2067 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
2068 * will return a data equivalent to "LL_ADC_CHANNEL_4".
2069 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
2070 * @retval Returned value can be one of the following values:
2071 * @arg @ref LL_ADC_CHANNEL_0 (3)
2072 * @arg @ref LL_ADC_CHANNEL_1 (3)
2073 * @arg @ref LL_ADC_CHANNEL_2 (3)
2074 * @arg @ref LL_ADC_CHANNEL_3 (3)
2075 * @arg @ref LL_ADC_CHANNEL_4 (3)
2076 * @arg @ref LL_ADC_CHANNEL_5 (3)
2077 * @arg @ref LL_ADC_CHANNEL_6
2078 * @arg @ref LL_ADC_CHANNEL_7
2079 * @arg @ref LL_ADC_CHANNEL_8
2080 * @arg @ref LL_ADC_CHANNEL_9
2081 * @arg @ref LL_ADC_CHANNEL_10
2082 * @arg @ref LL_ADC_CHANNEL_11
2083 * @arg @ref LL_ADC_CHANNEL_12
2084 * @arg @ref LL_ADC_CHANNEL_13
2085 * @arg @ref LL_ADC_CHANNEL_14
2086 * @arg @ref LL_ADC_CHANNEL_15
2087 * @arg @ref LL_ADC_CHANNEL_16
2088 * @arg @ref LL_ADC_CHANNEL_17
2089 * @arg @ref LL_ADC_CHANNEL_18
2090 * @arg @ref LL_ADC_CHANNEL_19
2091 * @arg @ref LL_ADC_CHANNEL_VREFINT
2092 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2093 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2094 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2095 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2096 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2097 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2098 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2099 *
2100 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2101 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2102 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2103 * Other channels are slow channels (conversion rate: refer to reference manual).
2104 * (1, 2) For ADC channel read back from ADC register,
2105 * comparison with internal channel parameter to be done
2106 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2107 */
2108 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
2109 (((__DECIMAL_NB__) <= 9UL) \
2110 ? (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2111 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2112 (ADC_SMPR1_REGOFFSET)) \
2113 : (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2114 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2115 (ADC_SMPR2_REGOFFSET)) \
2116 )
2117
2118 /**
2119 * @brief Helper macro to determine whether the selected channel
2120 * corresponds to literal definitions of driver.
2121 * @note The different literal definitions of ADC channels are:
2122 * - ADC internal channel:
2123 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
2124 * - ADC external channel (channel connected to a GPIO pin):
2125 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
2126 * @note The channel parameter must be a value defined from literal
2127 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2128 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2129 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
2130 * must not be a value from functions where a channel number is
2131 * returned from ADC registers,
2132 * because internal and external channels share the same channel
2133 * number in ADC registers. The differentiation is made only with
2134 * parameters definitions of driver.
2135 * @param __CHANNEL__ This parameter can be one of the following values:
2136 * @arg @ref LL_ADC_CHANNEL_0 (3)
2137 * @arg @ref LL_ADC_CHANNEL_1 (3)
2138 * @arg @ref LL_ADC_CHANNEL_2 (3)
2139 * @arg @ref LL_ADC_CHANNEL_3 (3)
2140 * @arg @ref LL_ADC_CHANNEL_4 (3)
2141 * @arg @ref LL_ADC_CHANNEL_5 (3)
2142 * @arg @ref LL_ADC_CHANNEL_6
2143 * @arg @ref LL_ADC_CHANNEL_7
2144 * @arg @ref LL_ADC_CHANNEL_8
2145 * @arg @ref LL_ADC_CHANNEL_9
2146 * @arg @ref LL_ADC_CHANNEL_10
2147 * @arg @ref LL_ADC_CHANNEL_11
2148 * @arg @ref LL_ADC_CHANNEL_12
2149 * @arg @ref LL_ADC_CHANNEL_13
2150 * @arg @ref LL_ADC_CHANNEL_14
2151 * @arg @ref LL_ADC_CHANNEL_15
2152 * @arg @ref LL_ADC_CHANNEL_16
2153 * @arg @ref LL_ADC_CHANNEL_17
2154 * @arg @ref LL_ADC_CHANNEL_18
2155 * @arg @ref LL_ADC_CHANNEL_19
2156 * @arg @ref LL_ADC_CHANNEL_VREFINT
2157 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2158 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2159 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2160 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2161 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2162 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2163 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2164 *
2165 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2166 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2167 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2168 * Other channels are slow channels (conversion rate: refer to reference manual).
2169 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
2170 * (channel connected to a GPIO pin).
2171 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
2172 */
2173 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
2174 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
2175
2176 /**
2177 * @brief Helper macro to convert a channel defined from parameter
2178 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2179 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2180 * to its equivalent parameter definition of a ADC external channel
2181 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
2182 * @note The channel parameter can be, additionally to a value
2183 * defined from parameter definition of a ADC internal channel
2184 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
2185 * a value defined from parameter definition of
2186 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2187 * or a value from functions where a channel number is returned
2188 * from ADC registers.
2189 * @param __CHANNEL__ This parameter can be one of the following values:
2190 * @arg @ref LL_ADC_CHANNEL_0 (3)
2191 * @arg @ref LL_ADC_CHANNEL_1 (3)
2192 * @arg @ref LL_ADC_CHANNEL_2 (3)
2193 * @arg @ref LL_ADC_CHANNEL_3 (3)
2194 * @arg @ref LL_ADC_CHANNEL_4 (3)
2195 * @arg @ref LL_ADC_CHANNEL_5 (3)
2196 * @arg @ref LL_ADC_CHANNEL_6
2197 * @arg @ref LL_ADC_CHANNEL_7
2198 * @arg @ref LL_ADC_CHANNEL_8
2199 * @arg @ref LL_ADC_CHANNEL_9
2200 * @arg @ref LL_ADC_CHANNEL_10
2201 * @arg @ref LL_ADC_CHANNEL_11
2202 * @arg @ref LL_ADC_CHANNEL_12
2203 * @arg @ref LL_ADC_CHANNEL_13
2204 * @arg @ref LL_ADC_CHANNEL_14
2205 * @arg @ref LL_ADC_CHANNEL_15
2206 * @arg @ref LL_ADC_CHANNEL_16
2207 * @arg @ref LL_ADC_CHANNEL_17
2208 * @arg @ref LL_ADC_CHANNEL_18
2209 * @arg @ref LL_ADC_CHANNEL_19
2210 * @arg @ref LL_ADC_CHANNEL_VREFINT
2211 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2212 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2213 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2214 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2215 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2216 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2217 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2218 *
2219 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2220 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2221 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2222 * Other channels are slow channels (conversion rate: refer to reference manual).
2223 * @retval Returned value can be one of the following values:
2224 * @arg @ref LL_ADC_CHANNEL_0
2225 * @arg @ref LL_ADC_CHANNEL_1
2226 * @arg @ref LL_ADC_CHANNEL_2
2227 * @arg @ref LL_ADC_CHANNEL_3
2228 * @arg @ref LL_ADC_CHANNEL_4
2229 * @arg @ref LL_ADC_CHANNEL_5
2230 * @arg @ref LL_ADC_CHANNEL_6
2231 * @arg @ref LL_ADC_CHANNEL_7
2232 * @arg @ref LL_ADC_CHANNEL_8
2233 * @arg @ref LL_ADC_CHANNEL_9
2234 * @arg @ref LL_ADC_CHANNEL_10
2235 * @arg @ref LL_ADC_CHANNEL_11
2236 * @arg @ref LL_ADC_CHANNEL_12
2237 * @arg @ref LL_ADC_CHANNEL_13
2238 * @arg @ref LL_ADC_CHANNEL_14
2239 * @arg @ref LL_ADC_CHANNEL_15
2240 * @arg @ref LL_ADC_CHANNEL_16
2241 * @arg @ref LL_ADC_CHANNEL_17
2242 * @arg @ref LL_ADC_CHANNEL_18
2243 * @arg @ref LL_ADC_CHANNEL_19
2244 */
2245 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
2246 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
2247
2248 /**
2249 * @brief Helper macro to determine whether the internal channel
2250 * selected is available on the ADC instance selected.
2251 * @note The channel parameter must be a value defined from parameter
2252 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2253 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2254 * must not be a value defined from parameter definition of
2255 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2256 * or a value from functions where a channel number is
2257 * returned from ADC registers,
2258 * because internal and external channels share the same channel
2259 * number in ADC registers. The differentiation is made only with
2260 * parameters definitions of driver.
2261 * @param __ADC_INSTANCE__ ADC instance
2262 * @param __CHANNEL__ This parameter can be one of the following values:
2263 * @arg @ref LL_ADC_CHANNEL_VREFINT
2264 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2265 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2266 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2267 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2268 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2269 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2270 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2271 *
2272 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2273 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2274 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
2275 * Value "1" if the internal channel selected is available on the ADC instance selected.
2276 */
2277 #if defined(ADC2)
2278 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2279 ((((__ADC_INSTANCE__) == ADC4) \
2280 &&(((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2281 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \
2282 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC4) || \
2283 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC4) || \
2284 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC4) ) \
2285 ) \
2286 || \
2287 (((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2) \
2288 &&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
2289 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2290 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) ) \
2291 ) \
2292 )
2293 #else
2294 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2295 ((((__ADC_INSTANCE__) == ADC4) \
2296 &&(((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2297 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \
2298 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC4) || \
2299 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC4) || \
2300 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC4) ) \
2301 ) \
2302 || \
2303 (((__ADC_INSTANCE__) == ADC1) \
2304 &&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
2305 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2306 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) ) \
2307 ) \
2308 )
2309 #endif /* ADC2 */
2310 /**
2311 * @brief Helper macro to define ADC analog watchdog parameter:
2312 * define a single channel to monitor with analog watchdog
2313 * from sequencer channel and groups definition.
2314 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2315 * Example:
2316 * LL_ADC_SetAnalogWDMonitChannels(
2317 * ADC1, LL_ADC_AWD1,
2318 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
2319 * @param __CHANNEL__ This parameter can be one of the following values:
2320 * @arg @ref LL_ADC_CHANNEL_0 (3)
2321 * @arg @ref LL_ADC_CHANNEL_1 (3)
2322 * @arg @ref LL_ADC_CHANNEL_2 (3)
2323 * @arg @ref LL_ADC_CHANNEL_3 (3)
2324 * @arg @ref LL_ADC_CHANNEL_4 (3)
2325 * @arg @ref LL_ADC_CHANNEL_5 (3)
2326 * @arg @ref LL_ADC_CHANNEL_6
2327 * @arg @ref LL_ADC_CHANNEL_7
2328 * @arg @ref LL_ADC_CHANNEL_8
2329 * @arg @ref LL_ADC_CHANNEL_9
2330 * @arg @ref LL_ADC_CHANNEL_10
2331 * @arg @ref LL_ADC_CHANNEL_11
2332 * @arg @ref LL_ADC_CHANNEL_12
2333 * @arg @ref LL_ADC_CHANNEL_13
2334 * @arg @ref LL_ADC_CHANNEL_14
2335 * @arg @ref LL_ADC_CHANNEL_15
2336 * @arg @ref LL_ADC_CHANNEL_16
2337 * @arg @ref LL_ADC_CHANNEL_17
2338 * @arg @ref LL_ADC_CHANNEL_18
2339 * @arg @ref LL_ADC_CHANNEL_19
2340 * @arg @ref LL_ADC_CHANNEL_VREFINT
2341 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2342 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2343 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
2344 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
2345 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
2346 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
2347 * @arg @ref LL_ADC_CHANNEL_VCORE (2)
2348 *
2349 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
2350 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2351 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2352 * Other channels are slow channels (conversion rate: refer to reference manual).
2353 * (1, 2) For ADC channel read back from ADC register,
2354 * comparison with internal channel parameter to be done
2355 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2356 * @param __GROUP__ This parameter can be one of the following values:
2357 * @arg @ref LL_ADC_GROUP_REGULAR
2358 * @arg @ref LL_ADC_GROUP_INJECTED
2359 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
2360 * @retval Returned value can be one of the following values:
2361 * @arg @ref LL_ADC_AWD_DISABLE
2362 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
2363 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
2364 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
2365 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
2366 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
2367 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
2368 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
2369 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
2370 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
2371 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
2372 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
2373 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
2374 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
2375 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
2376 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
2377 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
2378 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
2379 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
2380 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
2381 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
2382 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
2383 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
2384 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
2385 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
2386 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
2387 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
2388 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2389 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
2390 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
2391 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2392 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2393 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2394 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2395 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2396 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2397 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2398 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2399 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2400 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2401 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2402 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2403 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2404 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2405 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2406 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2407 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2408 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2409 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2410 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2411 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2412 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2413 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2414 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2415 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2416 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2417 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2418 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2419 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2420 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2421 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2422 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
2423 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
2424 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
2425 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
2426 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
2427 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
2428 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
2429 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
2430 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
2431 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
2432 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
2433 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
2434 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC4_REG (0)(2)
2435 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC4_REG (0)(2)
2436 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC4_REG (2)
2437 * @arg @ref LL_ADC_AWD_CH_VBAT_ADC4_REG (2)
2438 * @arg @ref LL_ADC_AWD_CH_VCORE_REG (2)
2439 *
2440 * (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
2441 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
2442 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
2443 */
2444 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2445 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2446 ? (((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) \
2447 : \
2448 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2449 ? (((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) \
2450 : \
2451 (((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) \
2452 )
2453
2454 /**
2455 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2456 * or low in function of ADC resolution, when ADC resolution is
2457 * different of 14 bits in case of ADC1 or ADC2, 12 bits in case of ADC4.
2458 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
2459 * Example, with a ADC resolution of 8 bits, to set the value of
2460 * analog watchdog threshold high (on 8 bits):
2461 * LL_ADC_SetAnalogWDThresholds
2462 * (< ADCx param >,
2463 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
2464 * );
2465 * @param __ADC_INSTANCE__ ADC instance
2466 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2467 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2468 * @arg @ref LL_ADC_RESOLUTION_12B
2469 * @arg @ref LL_ADC_RESOLUTION_10B
2470 * @arg @ref LL_ADC_RESOLUTION_8B
2471 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2472 * (1): Specific to ADC instance: ADC1, ADC2
2473 * (2): Specific to ADC instance: ADC4
2474 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 instance
2475 * __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 instance
2476 * @retval In case of ADC1 instance, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF
2477 * In case of ADC4 instance, Value between Min_Data=0x000 and Max_Data=0xFFF
2478 */
2479 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2480 (((__ADC_INSTANCE__) == ADC4) \
2481 ? \
2482 ((__AWD_THRESHOLD__) << (((((__ADC_RESOLUTION__) - ADC_RESOLUTION_ADC4_PROCESSING) & ADC_CFGR1_RES)) \
2483 >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
2484 : \
2485 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
2486 )
2487
2488 /**
2489 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2490 * or low in function of ADC resolution, when ADC resolution is
2491 * different of 14 bits in case of ADC1 or ADC2, 12 bits in case of ADC4.
2492 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2493 * Example, with a ADC resolution of 8 bits, to get the value of
2494 * analog watchdog threshold high (on 8 bits):
2495 * < threshold_value_8_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2496 * (LL_ADC_RESOLUTION_8B,
2497 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2498 * );
2499 * @param __ADC_INSTANCE__ ADC instance
2500 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2501 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2502 * @arg @ref LL_ADC_RESOLUTION_12B
2503 * @arg @ref LL_ADC_RESOLUTION_10B
2504 * @arg @ref LL_ADC_RESOLUTION_8B
2505 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2506 * (1): Specific to ADC instance: ADC1, ADC2
2507 * (2): Specific to ADC instance: ADC4
2508 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 instance
2509 * __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 instance
2510 * @retval In case of ADC1 instance, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF
2511 * In case of ADC4 instance, Value between Min_Data=0x000 and Max_Data=0xFFF
2512 */
2513 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2514 (((__ADC_INSTANCE__) == ADC4) \
2515 ? \
2516 ((__AWD_THRESHOLD__) >> (((((__ADC_RESOLUTION__) - ADC_RESOLUTION_ADC4_PROCESSING) & ADC_CFGR1_RES)) \
2517 >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
2518 : \
2519 ((__AWD_THRESHOLD__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
2520 )
2521
2522 /**
2523 * @brief Helper macro to set the ADC calibration value with both single ended
2524 * and differential modes calibration factors concatenated.
2525 * @note To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().
2526 * Example, to set calibration factors single ended to 0x55
2527 * and differential ended to 0x2A:
2528 * LL_ADC_SetCalibrationOffsetFactor(
2529 * ADC1,
2530 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2531 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2532 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2533 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2534 */
2535 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2536 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_SINGLEDIFF_CALIB_F_BIT_D_POS) | (__CALIB_FACTOR_SINGLE_ENDED__))
2537
2538 #if defined(ADC_MULTIMODE_SUPPORT)
2539 /**
2540 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2541 * or ADC slave from raw value with both ADC conversion data concatenated.
2542 * @note This macro is intended to be used when multimode transfer by DMA
2543 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2544 * In this case the transferred data need to processed with this macro
2545 * to separate the conversion data of ADC master and ADC slave.
2546 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2547 * @arg @ref LL_ADC_MULTI_MASTER
2548 * @arg @ref LL_ADC_MULTI_SLAVE
2549 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2550 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2551 */
2552 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2553 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2554 #endif /* ADC_MULTIMODE_SUPPORT */
2555
2556 /**
2557 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2558 * it has a dependence in multimode (ADC master of the corresponding
2559 * ADC common instance).
2560 * @note In case of device with multimode available and a mix of
2561 * ADC instances compliant and not compliant with multimode feature,
2562 * ADC instances not compliant with multimode feature are
2563 * considered as master instances (do not depend to
2564 * any other ADC instance).
2565 * @param __ADCx__ ADC instance
2566 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2567 */
2568 #if defined(ADC2)
2569 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2570 (((__ADCx__) == ADC2) ? (ADC1) : (__ADCx__))
2571 #else
2572 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) (__ADCx__)
2573 #endif /* ADC2 */
2574 /**
2575 * @brief Helper macro to select the ADC common instance
2576 * to which is belonging the selected ADC instance.
2577 * @note ADC common register instance can be used for:
2578 * - Set parameters common to several ADC instances
2579 * - Multimode (for devices with several ADC instances)
2580 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2581 * @param __ADCx__ ADC instance
2582 * @retval ADC common register instance
2583 */
2584 #if defined(ADC2)
2585 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2586 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) ? (ADC12_COMMON) : (ADC4_COMMON))
2587 #else
2588 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2589 (((__ADCx__) == ADC1) ? (ADC12_COMMON) : (ADC4_COMMON))
2590 #endif /* ADC2 */
2591
2592 /**
2593 * @brief Helper macro to check if all ADC instances sharing the same
2594 * ADC common instance are disabled.
2595 * @note This check is required by functions with setting conditioned to
2596 * ADC state:
2597 * All ADC instances of the ADC common group must be disabled.
2598 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2599 * @note On devices with only 1 ADC common instance, parameter of this macro
2600 * is useless and can be ignored (parameter kept for compatibility
2601 * with devices featuring several ADC common instances).
2602 * @param __ADCXY_COMMON__ ADC common instance
2603 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2604 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2605 * are disabled.
2606 * Value "1" if at least one ADC instance sharing the same ADC common instance
2607 * is enabled.
2608 */
2609 #if defined(ADC2)
2610 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2611 (((__ADCXY_COMMON__) == ADC12_COMMON) ? (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2)) : (LL_ADC_IsEnabled(ADC4)))
2612 #else
2613 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2614 (((__ADCXY_COMMON__) == ADC12_COMMON) ? (LL_ADC_IsEnabled(ADC1)) : (LL_ADC_IsEnabled(ADC4)))
2615 #endif /* ADC2 */
2616
2617 /**
2618 * @brief Helper macro to define the ADC conversion data full-scale digital
2619 * value corresponding to the selected ADC resolution.
2620 * @note ADC conversion data full-scale corresponds to voltage range
2621 * determined by analog voltage references Vref+ and Vref-
2622 * (refer to reference manual).
2623 * @param __ADC_INSTANCE__ ADC instance
2624 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2625 * @arg @ref LL_ADC_RESOLUTION_14B
2626 * @arg @ref LL_ADC_RESOLUTION_12B
2627 * @arg @ref LL_ADC_RESOLUTION_10B
2628 * @arg @ref LL_ADC_RESOLUTION_8B
2629 * @arg @ref LL_ADC_RESOLUTION_6B
2630 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2631 */
2632 #define __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \
2633 (0x3FFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2634
2635 /**
2636 * @brief Helper macro to convert the ADC conversion data from
2637 * a resolution to another resolution.
2638 * @param __ADC_INSTANCE__ ADC instance
2639 * @param __DATA__ ADC conversion data to be converted
2640 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2641 * This parameter can be one of the following values:
2642 * @arg @ref LL_ADC_RESOLUTION_14B
2643 * @arg @ref LL_ADC_RESOLUTION_12B
2644 * @arg @ref LL_ADC_RESOLUTION_10B
2645 * @arg @ref LL_ADC_RESOLUTION_8B
2646 * @arg @ref LL_ADC_RESOLUTION_6B
2647 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2648 * This parameter can be one of the following values:
2649 * @arg @ref LL_ADC_RESOLUTION_14B
2650 * @arg @ref LL_ADC_RESOLUTION_12B
2651 * @arg @ref LL_ADC_RESOLUTION_10B
2652 * @arg @ref LL_ADC_RESOLUTION_8B
2653 * @arg @ref LL_ADC_RESOLUTION_6B
2654 * @retval ADC conversion data to the requested resolution
2655 */
2656 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__ADC_INSTANCE__, __DATA__,\
2657 __ADC_RESOLUTION_CURRENT__,\
2658 __ADC_RESOLUTION_TARGET__) \
2659 (((__DATA__) \
2660 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2661 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2662 )
2663
2664 /**
2665 * @brief Helper macro to calculate the voltage (unit: mVolt)
2666 * corresponding to a ADC conversion data (unit: digital value).
2667 * @note Analog reference voltage (Vref+) must be either known from
2668 * user board environment or can be calculated using ADC measurement
2669 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2670 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2671 * @param __ADC_DATA__ ADC conversion data (resolution 16 bits)
2672 * (unit: digital value).
2673 * @param __ADC_INSTANCE__ ADC instance
2674 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2675 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2676 * @arg @ref LL_ADC_RESOLUTION_12B
2677 * @arg @ref LL_ADC_RESOLUTION_10B
2678 * @arg @ref LL_ADC_RESOLUTION_8B
2679 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2680 * (1): Specific to ADC instance: ADC1, ADC2
2681 * (2): Specific to ADC instance: ADC4
2682 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2683 */
2684 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__,\
2685 __ADC_DATA__, \
2686 __ADC_RESOLUTION__) \
2687 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2688 / __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \
2689 )
2690
2691 /**
2692 * @brief Helper macro to calculate analog reference voltage (Vref+)
2693 * (unit: mVolt) from ADC conversion data of internal voltage
2694 * reference VrefInt.
2695 * @note Computation is using VrefInt calibration value
2696 * stored in system memory for each device during production.
2697 * @note This voltage depends on user board environment: voltage level
2698 * connected to pin Vref+.
2699 * On devices with small package, the pin Vref+ is not present
2700 * and internally bonded to pin Vdda.
2701 * @note On this STM32 series, calibration data of internal voltage reference
2702 * VrefInt corresponds to a resolution of 16 bits,
2703 * this is the recommended ADC resolution to convert voltage of
2704 * internal voltage reference VrefInt.
2705 * Otherwise, this macro performs the processing to scale
2706 * ADC conversion data to 14 bits.
2707 * @param __ADC_INSTANCE__ ADC instance
2708 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)
2709 * of internal voltage reference VrefInt (unit: digital value).
2710 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2711 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2712 * @arg @ref LL_ADC_RESOLUTION_12B
2713 * @arg @ref LL_ADC_RESOLUTION_10B
2714 * @arg @ref LL_ADC_RESOLUTION_8B
2715 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2716 * (1): Specific to ADC instance: ADC1, ADC2
2717 * (2): Specific to ADC instance: ADC4
2718 * @retval Analog reference voltage (unit: mV)
2719 */
2720 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__ADC_INSTANCE__, __VREFINT_ADC_DATA__, \
2721 __ADC_RESOLUTION__) \
2722 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2723 / __LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), \
2724 (__VREFINT_ADC_DATA__), \
2725 (__ADC_RESOLUTION__), \
2726 LL_ADC_RESOLUTION_14B) \
2727 )
2728
2729 /**
2730 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2731 * from ADC conversion data of internal temperature sensor.
2732 * @note Computation is using temperature sensor calibration values
2733 * stored in system memory for each device during production.
2734 * @note Calculation formula:
2735 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2736 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2737 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2738 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2739 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2740 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2741 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2742 * TEMP_DEGC_CAL1 (calibrated in factory)
2743 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2744 * TEMP_DEGC_CAL2 (calibrated in factory)
2745 * Caution: Calculation relevancy under reserve that calibration
2746 * parameters are correct (address and data).
2747 * To calculate temperature using temperature sensor
2748 * datasheet typical values (generic values less, therefore
2749 * less accurate than calibrated values),
2750 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2751 * @note As calculation input, the analog reference voltage (Vref+) must be
2752 * defined as it impacts the ADC LSB equivalent voltage.
2753 * @note Analog reference voltage (Vref+) must be either known from
2754 * user board environment or can be calculated using ADC measurement
2755 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2756 * @note On this STM32 series, calibration data of temperature sensor
2757 * corresponds to a resolution of 14 bits,
2758 * this is the recommended ADC resolution to convert voltage of
2759 * temperature sensor.
2760 * Otherwise, this macro performs the processing to scale
2761 * ADC conversion data to 14 bits.
2762 * @param __ADC_INSTANCE__ ADC instance
2763 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2764 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2765 * temperature sensor (unit: digital value).
2766 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2767 * sensor voltage has been measured.
2768 * This parameter can be one of the following values:
2769 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2770 * @arg @ref LL_ADC_RESOLUTION_12B
2771 * @arg @ref LL_ADC_RESOLUTION_10B
2772 * @arg @ref LL_ADC_RESOLUTION_8B
2773 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2774 * (1): Specific to ADC instance: ADC1, ADC2
2775 * (2): Specific to ADC instance: ADC4
2776 * @retval Temperature (unit: degree Celsius)
2777 */
2778 #define __LL_ADC_CALC_TEMPERATURE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__,\
2779 __TEMPSENSOR_ADC_DATA__,\
2780 __ADC_RESOLUTION__) \
2781 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), \
2782 (__TEMPSENSOR_ADC_DATA__), \
2783 (__ADC_RESOLUTION__), \
2784 LL_ADC_RESOLUTION_14B) \
2785 * (__VREFANALOG_VOLTAGE__)) \
2786 / TEMPSENSOR_CAL_VREFANALOG) \
2787 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2788 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2789 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2790 ) + TEMPSENSOR_CAL1_TEMP \
2791 )
2792
2793 /**
2794 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2795 * from ADC conversion data of internal temperature sensor.
2796 * @note Computation is using temperature sensor typical values
2797 * (refer to device datasheet).
2798 * @note Calculation formula:
2799 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2800 * / Avg_Slope + CALx_TEMP
2801 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2802 * (unit: digital value)
2803 * Avg_Slope = temperature sensor slope
2804 * (unit: uV/Degree Celsius)
2805 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2806 * temperature CALx_TEMP (unit: mV)
2807 * Caution: Calculation relevancy under reserve the temperature sensor
2808 * of the current device has characteristics in line with
2809 * datasheet typical values.
2810 * If temperature sensor calibration values are available on
2811 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2812 * temperature calculation will be more accurate using
2813 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2814 * @note As calculation input, the analog reference voltage (Vref+) must be
2815 * defined as it impacts the ADC LSB equivalent voltage.
2816 * @note Analog reference voltage (Vref+) must be either known from
2817 * user board environment or can be calculated using ADC measurement
2818 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2819 * @note ADC measurement data must correspond to a resolution of 14 bits
2820 * (full scale digital value 4095). If not the case, the data must be
2821 * preliminarily rescaled to an equivalent resolution of 14 bits.
2822 * @param __ADC_INSTANCE__ ADC instance
2823 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
2824 * (unit: uV/DegCelsius).
2825 * On STM32U5, refer to device datasheet parameter "Avg_Slope".
2826 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
2827 * (at temperature and Vref+ defined in parameters below) (unit: mV).
2828 * On STM32U5, refer to device datasheet parameter "V30"
2829 * (corresponding to TS_CAL1).
2830 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
2831 * see parameter above) is corresponding (unit: mV)
2832 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2833 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2834 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2835 * This parameter can be one of the following values:
2836 * @arg @ref LL_ADC_RESOLUTION_14B (1)
2837 * @arg @ref LL_ADC_RESOLUTION_12B
2838 * @arg @ref LL_ADC_RESOLUTION_10B
2839 * @arg @ref LL_ADC_RESOLUTION_8B
2840 * @arg @ref LL_ADC_RESOLUTION_6B (2)
2841 * (1): Specific to ADC instance: ADC1, ADC2
2842 * (2): Specific to ADC instance: ADC4
2843 * @retval Temperature (unit: degree Celsius)
2844 */
2845 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__ADC_INSTANCE__, __TEMPSENSOR_TYP_AVGSLOPE__, \
2846 __TEMPSENSOR_TYP_CALX_V__, \
2847 __TEMPSENSOR_CALX_TEMP__, \
2848 __VREFANALOG_VOLTAGE__, \
2849 __TEMPSENSOR_ADC_DATA__, \
2850 __ADC_RESOLUTION__) \
2851 ((( ((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2852 / __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__)) \
2853 * 1000UL) \
2854 - \
2855 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2856 * 1000UL) \
2857 ) \
2858 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2859 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2860 )
2861
2862 /**
2863 * @}
2864 */
2865
2866 /**
2867 * @}
2868 */
2869
2870 /* Exported functions --------------------------------------------------------*/
2871 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2872 * @{
2873 */
2874
2875 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2876 * @{
2877 */
2878 #if defined(ADC_MULTIMODE_SUPPORT)
2879 /**
2880 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2881 * ADC register address from ADC instance and a list of ADC registers
2882 * intended to be used (most commonly) with DMA transfer.
2883 * @note These ADC registers are data registers:
2884 * when ADC conversion data is available in ADC data registers,
2885 * ADC generates a DMA transfer request.
2886 * @note This macro is intended to be used with LL DMA driver, refer to
2887 * function "LL_DMA_ConfigAddresses()".
2888 * Example:
2889 * LL_DMA_ConfigAddresses(DMA1,
2890 * LL_DMA_CHANNEL_1,
2891 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2892 * (uint32_t)&< array or variable >,
2893 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2894 * @note For devices with several ADC: in multimode, some devices
2895 * use a different data register outside of ADC instance scope
2896 * (common data register). This macro manages this register difference,
2897 * only ADC instance has to be set as parameter.
2898 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr
2899 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr
2900 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2901 * @param ADCx ADC instance
2902 * @param RegisterValue This parameter can be one of the following values:
2903 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2904 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2905 *
2906 * (1) Available on devices with several ADC instances.
2907 * @retval ADC register address
2908 */
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t RegisterValue)2909 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t RegisterValue)
2910 {
2911 uint32_t data_reg_addr;
2912
2913 if (RegisterValue == LL_ADC_DMA_REG_REGULAR_DATA)
2914 {
2915 /* Retrieve address of register DR */
2916 data_reg_addr = (uint32_t) &(ADCx->DR);
2917 }
2918 else /* (RegisterValue == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2919 {
2920 /* Retrieve address of register CDR */
2921 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2922 }
2923
2924 return data_reg_addr;
2925 }
2926 #else
2927 /**
2928 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2929 * ADC register address from ADC instance and a list of ADC registers
2930 * intended to be used (most commonly) with DMA transfer.
2931 * @note These ADC registers are data registers:
2932 * when ADC conversion data is available in ADC data registers,
2933 * ADC generates a DMA transfer request.
2934 * @note This macro is intended to be used with LL DMA driver, refer to
2935 * function "LL_DMA_ConfigAddresses()".
2936 * Example:
2937 * LL_DMA_ConfigAddresses(DMA1,
2938 * LL_DMA_CHANNEL_1,
2939 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2940 * (uint32_t)&< array or variable >,
2941 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2942 * @note For devices with several ADC: in multimode, some devices
2943 * use a different data register outside of ADC instance scope
2944 * (common data register). This macro manages this register difference,
2945 * only ADC instance has to be set as parameter.
2946 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr
2947 * @param ADCx ADC instance
2948 * @param RegisterValue This parameter can be one of the following values:
2949 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2950 * @retval ADC register address
2951 */
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t RegisterValue)2952 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t RegisterValue)
2953 {
2954 /* Prevent unused argument(s) compilation warning */
2955 (void)(RegisterValue);
2956
2957 /* Retrieve address of register DR */
2958 return (uint32_t) &(ADCx->DR);
2959 }
2960 #endif /* ADC_MULTIMODE_SUPPORT */
2961
2962 /**
2963 * @}
2964 */
2965
2966 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope:
2967 * common to several ADC instances
2968 * @{
2969 */
2970
2971 /**
2972 * @brief Set parameter common to several ADC: Clock source and prescaler.
2973 * @note On this STM32 series, if ADC group injected is used, some
2974 * clock ratio constraints between ADC clock and AHB clock
2975 * must be respected.
2976 * Refer to reference manual.
2977 * @note On this STM32 series, setting of this feature is conditioned to
2978 * ADC state:
2979 * All ADC instances of the ADC common group must be disabled.
2980 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2981 * ADC instance or by using helper macro helper macro
2982 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2983 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock
2984 * CCR PRESC LL_ADC_SetCommonClock
2985 * @param ADCxy_COMMON ADC common instance
2986 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2987 * @param CommonClock This parameter can be one of the following values:
2988 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2989 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2990 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2991 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2992 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2993 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2994 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2995 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2996 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2997 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2998 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2999 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3000 * @retval None
3001 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)3002 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
3003 {
3004 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
3005 }
3006
3007 /**
3008 * @brief Get parameter common to several ADC: Clock source and prescaler.
3009 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock
3010 * CCR PRESC LL_ADC_GetCommonClock
3011 * @param ADCxy_COMMON ADC common instance
3012 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3013 * @retval Returned value can be one of the following values:
3014 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
3015 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
3016 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
3017 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
3018 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
3019 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
3020 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
3021 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
3022 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
3023 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
3024 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
3025 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3026 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)3027 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
3028 {
3029 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
3030 }
3031
3032 /**
3033 * @brief Set parameter common to several ADC: measurement path to
3034 * internal channels (VrefInt, temperature sensor, ...).
3035 * Add paths to the current configuration.
3036 * @note One or several values can be selected.
3037 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3038 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3039 * @note Stabilization time of measurement path to internal channel:
3040 * After enabling internal paths, before starting ADC conversion,
3041 * a delay is required for internal voltage reference and
3042 * temperature sensor stabilization time.
3043 * Refer to device datasheet.
3044 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3045 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3046 * @note ADC internal channel sampling time constraint:
3047 * For ADC conversion of internal channels,
3048 * a sampling time minimum value is required.
3049 * Refer to device datasheet.
3050 * @note On this STM32 series, setting of this feature is conditioned to
3051 * ADC state:
3052 * All ADC instances of the ADC common group must be disabled.
3053 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3054 * ADC instance or by using helper macro helper macro
3055 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3056 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd
3057 * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd
3058 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
3059 * @param ADCxy_COMMON ADC common instance
3060 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3061 * @param PathInternal This parameter can be a combination of the following values:
3062 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3063 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3064 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3065 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3066 * @retval None
3067 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3068 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3069 {
3070 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
3071 }
3072
3073 /**
3074 * @brief Set parameter common to several ADC: measurement path to
3075 * internal channels (VrefInt, temperature sensor, ...).
3076 * Remove paths to the current configuration.
3077 * @note One or several values can be selected.
3078 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3079 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3080 * @note On this STM32 series, setting of this feature is conditioned to
3081 * ADC state:
3082 * All ADC instances of the ADC common group must be disabled.
3083 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3084 * ADC instance or by using helper macro helper macro
3085 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3086 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem
3087 * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem
3088 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
3089 * @param ADCxy_COMMON ADC common instance
3090 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3091 * @param PathInternal This parameter can be a combination of the following values:
3092 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3093 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3094 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3095 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3096 * @retval None
3097 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3098 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3099 {
3100 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
3101 }
3102
3103 /**
3104 * @brief Set parameter common to several ADC: measurement path to internal
3105 * channels (VrefInt, temperature sensor, ...).
3106 * @note One or several values can be selected.
3107 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3108 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3109 * @note Stabilization time of measurement path to internal channel:
3110 * After enabling internal paths, before starting ADC conversion,
3111 * a delay is required for internal voltage reference and
3112 * temperature sensor stabilization time.
3113 * Refer to device datasheet.
3114 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3115 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
3116 * @note ADC internal channel sampling time constraint:
3117 * For ADC conversion of internal channels,
3118 * a sampling time minimum value is required.
3119 * Refer to device datasheet.
3120 * @note On this STM32 series, setting of this feature is conditioned to
3121 * ADC state:
3122 * All ADC instances of the ADC common group must be disabled.
3123 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3124 * ADC instance or by using helper macro helper macro
3125 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3126 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh
3127 * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh
3128 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
3129 * @param ADCxy_COMMON ADC common instance
3130 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3131 * @param PathInternal This parameter can be a combination of the following values:
3132 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3133 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3134 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3135 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3136 * @retval None
3137 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3138 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3139 {
3140 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN, PathInternal);
3141 }
3142
3143 /**
3144 * @brief Get parameter common to several ADC: measurement path to internal
3145 * channels (VrefInt, temperature sensor, ...).
3146 * @note One or several values can be selected.
3147 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3148 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3149 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh
3150 * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh
3151 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
3152 * @param ADCxy_COMMON ADC common instance
3153 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3154 * @retval Returned value can be a combination of the following values:
3155 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3156 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3157 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3158 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3159 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)3160 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
3161 {
3162 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN));
3163 }
3164
3165 /**
3166 * @}
3167 */
3168
3169 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
3170 * @{
3171 */
3172
3173 /**
3174 * @brief Set ADC calibration factor in the mode single-ended
3175 * or differential (for devices with differential mode available).
3176 * @note This function is intended to set calibration parameters
3177 * without having to perform a new calibration using
3178 * @ref LL_ADC_StartCalibration().
3179 * @note For devices with differential mode available:
3180 * Calibration of offset is specific to each of
3181 * single-ended and differential modes
3182 * (calibration factor must be specified for each of these
3183 * differential modes, if used afterwards and if the application
3184 * requires their calibration).
3185 * Calibration of linearity is common to both
3186 * single-ended and differential modes
3187 * (calibration factor can be specified only once).
3188 * @note In case of setting calibration factors of both modes single ended
3189 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
3190 * both calibration factors must be concatenated.
3191 * To perform this processing, use helper macro
3192 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
3193 * @note On this STM32 series, setting of this feature is conditioned to
3194 * ADC state:
3195 * ADC must be enabled, without calibration on going, without conversion
3196 * on going on group regular.
3197 * @param ADCx ADC instance
3198 * @param SingleDiff This parameter can be one of the following values:
3199 * @arg @ref LL_ADC_SINGLE_ENDED
3200 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3201 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
3202 * @param CalibrationFactor Value between Min_Data=0x0000 and Max_Data=0xFFFF
3203 * @retval None
3204 */
LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)3205 __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff,
3206 uint32_t CalibrationFactor)
3207 {
3208 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
3209 {
3210 /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
3211 therefore they are not cleared in this function. */
3212 MODIFY_REG(ADCx->CR, ADC_CR_CALINDEX, (0UL << ADC_CR_CALINDEX_Pos)); /* CalibIndex == 0 */
3213 MODIFY_REG(ADCx->CALFACT2,
3214 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
3215 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) \
3216 >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) \
3217 & ~(SingleDiff & ADC_CALFACT2_CALFACT_S)));
3218 SET_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
3219 }
3220 else
3221 {
3222 MODIFY_REG(ADCx->CALFACT, ADC4_CALFACT_CALFACT, CalibrationFactor);
3223 }
3224 }
3225
3226 /**
3227 * @brief Get ADC calibration factor in the mode single-ended
3228 * or differential (for devices with differential mode available).
3229 * @note Calibration factors are set by hardware after performing
3230 * a calibration run using function @ref LL_ADC_StartCalibration().
3231 * @note For devices with differential mode available:
3232 * Calibration of offset is specific to each of
3233 * single-ended and differential modes
3234 * Calibration of linearity is common to both
3235 * single-ended and differential modes
3236 * @param ADCx ADC instance
3237 * @param SingleDiff This parameter can be one of the following values:
3238 * @arg @ref LL_ADC_SINGLE_ENDED
3239 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3240 * @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF
3241 */
LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff)3242 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
3243 {
3244 /* Retrieve bits with position in register depending on parameter */
3245 /* "SingleDiff". */
3246 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
3247 /* containing other bits reserved for other purpose. */
3248 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
3249 {
3250 /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
3251 therefore they are not cleared in this function. */
3252 uint32_t temp_CalibOffset;
3253 SET_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
3254 MODIFY_REG(ADCx->CR, ADC_CR_CALINDEX, (0UL << ADC_CR_CALINDEX_Pos)); /* CalibIndex == 0 */
3255 temp_CalibOffset = (READ_BIT(ADCx->CALFACT2, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) \
3256 >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
3257 return temp_CalibOffset;
3258 }
3259 else
3260 {
3261 return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC4_CALFACT_CALFACT));
3262 }
3263 }
3264
3265 /**
3266 * @brief Set ADC Linear calibration factor in the mode single-ended.
3267 * @note This function is intended to set linear calibration parameters
3268 * without having to perform a new calibration using
3269 * @ref LL_ADC_StartCalibration().
3270 * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2.
3271 * @note On this STM32 series, setting of this feature is conditioned to
3272 * ADC state:
3273 * ADC must be enabled, without calibration on going, without conversion
3274 * on going on group regular.
3275 * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
3276 * CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
3277 * @param ADCx ADC instance (on STM32U5, feature available on ADC instances: ADC1, ADC2)
3278 * @param LinearityWord This parameter can be one of the following values:
3279 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX1
3280 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX2
3281 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX3
3282 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX4
3283 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX5
3284 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX6
3285 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX7
3286 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
3287 * @retval None
3288 */
LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef * ADCx,uint32_t LinearityWord,uint32_t CalibrationFactor)3289 __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord,
3290 uint32_t CalibrationFactor)
3291 {
3292 /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
3293 therefore they are not cleared in this function. */
3294 MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX),
3295 LinearityWord); /* LinearityWord == CalibIndex (1 to 7 for linearity reading) */
3296 MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_CALFACT, CalibrationFactor);
3297 SET_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
3298 }
3299
3300 /**
3301 * @brief Get ADC Linear calibration factor in the mode single-ended.
3302 * @note Calibration factors are set by hardware after performing
3303 * a calibration run using function @ref LL_ADC_StartCalibration().
3304 * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2.
3305 * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
3306 * CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
3307 * @param ADCx ADC instance (on STM32U5, feature available on ADC instances: ADC1, ADC2)
3308 * @param LinearityWord This parameter can be one of the following values:
3309 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX1
3310 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX2
3311 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX3
3312 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX4
3313 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX5
3314 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX6
3315 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX7
3316 * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
3317 */
LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef * ADCx,uint32_t LinearityWord)3318 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
3319 {
3320 uint32_t temp_calib_linearity;
3321
3322 /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
3323 therefore they are not cleared in this function. */
3324 SET_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
3325 MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX),
3326 LinearityWord); /* LinearityWord == CalibIndex (1 to 7 for linearity reading) */
3327 temp_calib_linearity = (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_CALFACT_Msk));
3328 return temp_calib_linearity;
3329 }
3330 /**
3331 * @brief Set ADC resolution.
3332 * Refer to reference manual for alignments formats
3333 * dependencies to ADC resolutions.
3334 * @note On this STM32 series, setting of this feature is conditioned to
3335 * ADC state:
3336 * ADC must be disabled or enabled without conversion on going
3337 * on either groups regular or injected.
3338 * @rmtoll CFGR RES LL_ADC_SetResolution
3339 * @param ADCx ADC instance
3340 * @param Resolution This parameter can be one of the following values:
3341 * @arg @ref LL_ADC_RESOLUTION_14B (1)
3342 * @arg @ref LL_ADC_RESOLUTION_12B
3343 * @arg @ref LL_ADC_RESOLUTION_10B
3344 * @arg @ref LL_ADC_RESOLUTION_8B
3345 * @arg @ref LL_ADC_RESOLUTION_6B (2)
3346 * (1): Specific to ADC instance: ADC1, ADC2
3347 * (2): Specific to ADC instance: ADC4
3348 * @retval None
3349 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)3350 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
3351 {
3352 uint32_t tmp_resolution = Resolution;
3353 if (ADCx == ADC4)
3354 {
3355 tmp_resolution = ((tmp_resolution - ADC_RESOLUTION_ADC4_PROCESSING) & ADC_CFGR1_RES);
3356 }
3357
3358 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, tmp_resolution);
3359 }
3360
3361 /**
3362 * @brief Get ADC resolution.
3363 * Refer to reference manual for alignments formats
3364 * dependencies to ADC resolutions.
3365 * @rmtoll CFGR RES LL_ADC_GetResolution
3366 * @param ADCx ADC instance
3367 * @retval Returned value can be one of the following values:
3368 * @arg @ref LL_ADC_RESOLUTION_14B (1)
3369 * @arg @ref LL_ADC_RESOLUTION_12B
3370 * @arg @ref LL_ADC_RESOLUTION_10B
3371 * @arg @ref LL_ADC_RESOLUTION_8B
3372 * @arg @ref LL_ADC_RESOLUTION_6B (2)
3373 * (1): Specific to ADC instance: ADC1, ADC2
3374 * (2): Specific to ADC instance: ADC4
3375 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)3376 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
3377 {
3378 uint32_t tmp_resolution = (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
3379
3380 if (ADCx == ADC4)
3381 {
3382 tmp_resolution = (tmp_resolution + (ADC_RESOLUTION_ADC4_PROCESSING << ADC_CFGR1_RES_Pos));
3383 }
3384
3385 return tmp_resolution;
3386 }
3387
3388 /**
3389 * @brief Set ADC conversion data alignment.
3390 * @note Refer to reference manual for alignments formats
3391 * dependencies to ADC resolutions.
3392 * @note On this STM32 series, setting of this feature is conditioned to
3393 * ADC state:
3394 * ADC must be disabled or enabled without conversion on going
3395 * on group regular.
3396 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
3397 * @param ADCx ADC instance
3398 * @param DataAlignment This parameter can be one of the following values:
3399 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3400 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3401 * @retval None
3402 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)3403 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
3404 {
3405 MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_ALIGN, DataAlignment);
3406 }
3407
3408 /**
3409 * @brief Get ADC conversion data alignment.
3410 * @note Refer to reference manual for alignments formats
3411 * dependencies to ADC resolutions.
3412 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
3413 * @param ADCx ADC instance
3414 * @retval Returned value can be one of the following values:
3415 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3416 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3417 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)3418 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
3419 {
3420 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_ALIGN));
3421 }
3422
3423 /**
3424 * @brief Set ADC low power mode.
3425 * @note Description of ADC low power modes:
3426 * - ADC low power mode "auto wait": Dynamic low power mode,
3427 * ADC conversions occurrences are limited to the minimum necessary
3428 * in order to reduce power consumption.
3429 * New ADC conversion starts only when the previous
3430 * unitary conversion data (for ADC group regular)
3431 * or previous sequence conversions data (for ADC group injected)
3432 * has been retrieved by user software.
3433 * In the meantime, ADC remains idle: does not performs any
3434 * other conversion.
3435 * This mode allows to automatically adapt the ADC conversions
3436 * triggers to the speed of the software that reads the data.
3437 * Moreover, this avoids risk of overrun for low frequency
3438 * applications.
3439 * How to use this low power mode:
3440 * - It is not recommended to use with interruption or DMA
3441 * since these modes have to clear immediately the EOC flag
3442 * (by CPU to free the IRQ pending event or by DMA).
3443 * Auto wait will work but fort a very short time, discarding
3444 * its intended benefit (except specific case of high load of CPU
3445 * or DMA transfers which can justify usage of auto wait).
3446 * - Do use with polling: 1. Start conversion,
3447 * 2. Later on, when conversion data is needed: poll for end of
3448 * conversion to ensure that conversion is completed and
3449 * retrieve ADC conversion data. This will trig another
3450 * ADC conversion start.
3451 * - ADC low power mode "auto power-off" (feature available on
3452 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3453 * the ADC automatically powers-off after a conversion and
3454 * automatically wakes up when a new conversion is triggered
3455 * (with startup time between trigger and start of sampling).
3456 * This feature can be combined with low power mode "auto wait".
3457 * @note With ADC low power mode "auto wait", the ADC conversion data read
3458 * is corresponding to previous ADC conversion start, independently
3459 * of delay during which ADC was idle.
3460 * Therefore, the ADC conversion data may be outdated: does not
3461 * correspond to the current voltage level on the selected
3462 * ADC channel.
3463 * @note On this STM32 series, setting of this feature is conditioned to
3464 * ADC state:
3465 * ADC must be disabled or enabled without conversion on going
3466 * on either groups regular or injected.
3467 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
3468 * @param ADCx ADC instance
3469 * @param LowPowerMode This parameter can be one of the following values:
3470 * @arg @ref LL_ADC_LP_MODE_NONE
3471 * @arg @ref LL_ADC_LP_AUTOWAIT
3472 * @retval None
3473 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)3474 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3475 {
3476 if (ADCx != ADC4) /* ADC1 or ADC2 */
3477 {
3478 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_AUTDLY, LowPowerMode);
3479 }
3480 else
3481 {
3482 MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_WAIT, LowPowerMode);
3483 MODIFY_REG(ADCx->PWRR, ADC4_PWRR_AUTOFF, LowPowerMode);
3484 }
3485 }
3486
3487 /**
3488 * @brief Get ADC low power mode:
3489 * @note Description of ADC low power modes:
3490 * - ADC low power mode "auto wait": Dynamic low power mode,
3491 * ADC conversions occurrences are limited to the minimum necessary
3492 * in order to reduce power consumption.
3493 * New ADC conversion starts only when the previous
3494 * unitary conversion data (for ADC group regular)
3495 * or previous sequence conversions data (for ADC group injected)
3496 * has been retrieved by user software.
3497 * In the meantime, ADC remains idle: does not performs any
3498 * other conversion.
3499 * This mode allows to automatically adapt the ADC conversions
3500 * triggers to the speed of the software that reads the data.
3501 * Moreover, this avoids risk of overrun for low frequency
3502 * applications.
3503 * How to use this low power mode:
3504 * - It is not recommended to use with interruption or DMA
3505 * since these modes have to clear immediately the EOC flag
3506 * (by CPU to free the IRQ pending event or by DMA).
3507 * Auto wait will work but fort a very short time, discarding
3508 * its intended benefit (except specific case of high load of CPU
3509 * or DMA transfers which can justify usage of auto wait).
3510 * - Do use with polling: 1. Start conversion,
3511 * 2. Later on, when conversion data is needed: poll for end of
3512 * conversion to ensure that conversion is completed and
3513 * retrieve ADC conversion data. This will trig another
3514 * ADC conversion start.
3515 * - ADC low power mode "auto power-off" (feature available on
3516 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3517 * the ADC automatically powers-off after a conversion and
3518 * automatically wakes up when a new conversion is triggered
3519 * (with startup time between trigger and start of sampling).
3520 * This feature can be combined with low power mode "auto wait".
3521 * @note With ADC low power mode "auto wait", the ADC conversion data read
3522 * is corresponding to previous ADC conversion start, independently
3523 * of delay during which ADC was idle.
3524 * Therefore, the ADC conversion data may be outdated: does not
3525 * correspond to the current voltage level on the selected
3526 * ADC channel.
3527 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
3528 * @param ADCx ADC instance
3529 * @retval Returned value can be one of the following values:
3530 * @arg @ref LL_ADC_LP_MODE_NONE
3531 * @arg @ref LL_ADC_LP_AUTOWAIT
3532 */
LL_ADC_GetLowPowerMode(const ADC_TypeDef * ADCx)3533 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
3534 {
3535 if (ADCx != ADC4) /* ADC1 or ADC2 */
3536 {
3537 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_AUTDLY));
3538 }
3539 else
3540 {
3541 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_WAIT));
3542 }
3543
3544 }
3545
3546 /**
3547 * @brief Set ADC selected offset number 1, 2, 3 or 4.
3548 * @note This function set the 2 items of offset configuration:
3549 * - ADC channel to which the offset programmed will be applied
3550 * (independently of channel mapped on ADC group regular
3551 * or group injected)
3552 * - Offset level (offset to be subtracted from the raw
3553 * converted data).
3554 * @note Caution: Offset format is dependent to ADC resolution:
3555 * offset has to be left-aligned on bit 11, the LSB (right bits)
3556 * are set to 0.
3557 * @note This function enables the offset, by default. It can be forced
3558 * to disable state using function LL_ADC_SetOffsetState().
3559 * @note If a channel is mapped on several offsets numbers, only the offset
3560 * with the lowest value is considered for the subtraction.
3561 * @note On this STM32 series, setting of this feature is conditioned to
3562 * ADC state:
3563 * ADC must be disabled or enabled without conversion on going
3564 * on either groups regular or injected.
3565 * @note On STM32U5, some fast channels are available: fast analog inputs
3566 * coming from GPIO pads (ADC_IN0..5).
3567 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset
3568 * OFR1 OFFSET1 LL_ADC_SetOffset
3569 * OFR1 OFFSET1_EN LL_ADC_SetOffset
3570 * OFR2 OFFSET2_CH LL_ADC_SetOffset
3571 * OFR2 OFFSET2 LL_ADC_SetOffset
3572 * OFR2 OFFSET2_EN LL_ADC_SetOffset
3573 * OFR3 OFFSET3_CH LL_ADC_SetOffset
3574 * OFR3 OFFSET3 LL_ADC_SetOffset
3575 * OFR3 OFFSET3_EN LL_ADC_SetOffset
3576 * OFR4 OFFSET4_CH LL_ADC_SetOffset
3577 * OFR4 OFFSET4 LL_ADC_SetOffset
3578 * OFR4 OFFSET4_EN LL_ADC_SetOffset
3579 * @param ADCx ADC instance
3580 * @param Offsety This parameter can be one of the following values:
3581 * @arg @ref LL_ADC_OFFSET_1
3582 * @arg @ref LL_ADC_OFFSET_2
3583 * @arg @ref LL_ADC_OFFSET_3
3584 * @arg @ref LL_ADC_OFFSET_4
3585 * @param Channel This parameter can be one of the following values:
3586 * @arg @ref LL_ADC_CHANNEL_0 (3)
3587 * @arg @ref LL_ADC_CHANNEL_1 (3)
3588 * @arg @ref LL_ADC_CHANNEL_2 (3)
3589 * @arg @ref LL_ADC_CHANNEL_3 (3)
3590 * @arg @ref LL_ADC_CHANNEL_4 (3)
3591 * @arg @ref LL_ADC_CHANNEL_5 (3)
3592 * @arg @ref LL_ADC_CHANNEL_6
3593 * @arg @ref LL_ADC_CHANNEL_7
3594 * @arg @ref LL_ADC_CHANNEL_8
3595 * @arg @ref LL_ADC_CHANNEL_9
3596 * @arg @ref LL_ADC_CHANNEL_10
3597 * @arg @ref LL_ADC_CHANNEL_11
3598 * @arg @ref LL_ADC_CHANNEL_12
3599 * @arg @ref LL_ADC_CHANNEL_13
3600 * @arg @ref LL_ADC_CHANNEL_14
3601 * @arg @ref LL_ADC_CHANNEL_15
3602 * @arg @ref LL_ADC_CHANNEL_16
3603 * @arg @ref LL_ADC_CHANNEL_17
3604 * @arg @ref LL_ADC_CHANNEL_18
3605 * @arg @ref LL_ADC_CHANNEL_19
3606 * @arg @ref LL_ADC_CHANNEL_VREFINT
3607 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3608 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3609 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
3610 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
3611 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
3612 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
3613 *
3614 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
3615 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
3616 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
3617 * Other channels are slow channels (conversion rate: refer to reference manual).
3618 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
3619 * @retval None
3620 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)3621 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3622 {
3623 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3624
3625 MODIFY_REG(*preg,
3626 ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3627 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) << 1UL) | OffsetLevel);
3628 }
3629
3630 /**
3631 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3632 * Channel to which the offset programmed will be applied
3633 * (independently of channel mapped on ADC group regular
3634 * or group injected)
3635 * @note Usage of the returned channel number:
3636 * - To reinject this channel into another function LL_ADC_xxx:
3637 * the returned channel number is only partly formatted on definition
3638 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3639 * with parts of literals LL_ADC_CHANNEL_x or using
3640 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3641 * Then the selected literal LL_ADC_CHANNEL_x can be used
3642 * as parameter for another function.
3643 * - To get the channel number in decimal format:
3644 * process the returned value with the helper macro
3645 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3646 * @note On STM32U5, some fast channels are available: fast analog inputs
3647 * coming from GPIO pads (ADC_IN0..5).
3648 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel
3649 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel
3650 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel
3651 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
3652 * @param ADCx ADC instance
3653 * @param Offsety This parameter can be one of the following values:
3654 * @arg @ref LL_ADC_OFFSET_1
3655 * @arg @ref LL_ADC_OFFSET_2
3656 * @arg @ref LL_ADC_OFFSET_3
3657 * @arg @ref LL_ADC_OFFSET_4
3658 * @retval Returned value can be one of the following values:
3659 * @arg @ref LL_ADC_CHANNEL_0 (3)
3660 * @arg @ref LL_ADC_CHANNEL_1 (3)
3661 * @arg @ref LL_ADC_CHANNEL_2 (3)
3662 * @arg @ref LL_ADC_CHANNEL_3 (3)
3663 * @arg @ref LL_ADC_CHANNEL_4 (3)
3664 * @arg @ref LL_ADC_CHANNEL_5 (3)
3665 * @arg @ref LL_ADC_CHANNEL_6
3666 * @arg @ref LL_ADC_CHANNEL_7
3667 * @arg @ref LL_ADC_CHANNEL_8
3668 * @arg @ref LL_ADC_CHANNEL_9
3669 * @arg @ref LL_ADC_CHANNEL_10
3670 * @arg @ref LL_ADC_CHANNEL_11
3671 * @arg @ref LL_ADC_CHANNEL_12
3672 * @arg @ref LL_ADC_CHANNEL_13
3673 * @arg @ref LL_ADC_CHANNEL_14
3674 * @arg @ref LL_ADC_CHANNEL_15
3675 * @arg @ref LL_ADC_CHANNEL_16
3676 * @arg @ref LL_ADC_CHANNEL_17
3677 * @arg @ref LL_ADC_CHANNEL_18
3678 * @arg @ref LL_ADC_CHANNEL_19
3679 * @arg @ref LL_ADC_CHANNEL_VREFINT
3680 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3681 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3682 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
3683 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
3684 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
3685 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
3686 *
3687 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
3688 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
3689 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
3690 * Other channels are slow channels (conversion rate: refer to reference manual).
3691 * (1, 2) For ADC channel read back from ADC register,
3692 * comparison with internal channel parameter to be done
3693 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3694 */
LL_ADC_GetOffsetChannel(const ADC_TypeDef * ADCx,uint32_t Offsety)3695 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3696 {
3697 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3698
3699 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3700 }
3701
3702 /**
3703 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3704 * Offset level (offset to be subtracted from the raw
3705 * converted data).
3706 * @note Caution: Offset format is dependent to ADC resolution:
3707 * offset has to be left-aligned on bit 11, the LSB (right bits)
3708 * are set to 0.
3709 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel
3710 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel
3711 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel
3712 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3713 * @param ADCx ADC instance
3714 * @param Offsety This parameter can be one of the following values:
3715 * @arg @ref LL_ADC_OFFSET_1
3716 * @arg @ref LL_ADC_OFFSET_2
3717 * @arg @ref LL_ADC_OFFSET_3
3718 * @arg @ref LL_ADC_OFFSET_4
3719 * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
3720 */
LL_ADC_GetOffsetLevel(const ADC_TypeDef * ADCx,uint32_t Offsety)3721 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3722 {
3723 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3724
3725 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3726 }
3727
3728 /**
3729 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3730 * choose offset sign.
3731 * @note On this STM32 series, setting of this feature is conditioned to
3732 * ADC state:
3733 * ADC must be disabled or enabled without conversion on going
3734 * on either groups regular or injected.
3735 * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign
3736 * OFR2 OFFSETPOS LL_ADC_SetOffsetSign
3737 * OFR3 OFFSETPOS LL_ADC_SetOffsetSign
3738 * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
3739 * @param ADCx ADC instance
3740 * @param Offsety This parameter can be one of the following values:
3741 * @arg @ref LL_ADC_OFFSET_1
3742 * @arg @ref LL_ADC_OFFSET_2
3743 * @arg @ref LL_ADC_OFFSET_3
3744 * @arg @ref LL_ADC_OFFSET_4
3745 * @param OffsetSign This parameter can be one of the following values:
3746 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3747 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3748 * @retval None
3749 */
LL_ADC_SetOffsetSign(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSign)3750 __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
3751 {
3752 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3753
3754 MODIFY_REG(*preg, ADC_OFR1_OFFSETPOS, OffsetSign);
3755 }
3756
3757 /**
3758 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3759 * offset sign if positive or negative.
3760 * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign
3761 * OFR2 OFFSETPOS LL_ADC_GetOffsetSign
3762 * OFR3 OFFSETPOS LL_ADC_GetOffsetSign
3763 * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
3764 * @param ADCx ADC instance
3765 * @param Offsety This parameter can be one of the following values:
3766 * @arg @ref LL_ADC_OFFSET_1
3767 * @arg @ref LL_ADC_OFFSET_2
3768 * @arg @ref LL_ADC_OFFSET_3
3769 * @arg @ref LL_ADC_OFFSET_4
3770 * @retval Returned value can be one of the following values:
3771 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3772 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3773 */
LL_ADC_GetOffsetSign(const ADC_TypeDef * ADCx,uint32_t Offsety)3774 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety)
3775 {
3776 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3777
3778 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
3779 }
3780
3781 /**
3782 * @brief Set Signed saturation for the ADC selected offset number 1, 2, 3 or 4:
3783 * signed offset saturation if enabled or disabled.
3784 * @rmtoll OFR1 SSAT LL_ADC_SetOffsetSignedSaturation
3785 * OFR2 SSAT LL_ADC_SetOffsetSignedSaturation
3786 * OFR3 SSAT LL_ADC_SetOffsetSignedSaturation
3787 * OFR4 SSAT LL_ADC_SetOffsetSignedSaturation
3788 * @param ADCx ADC instance
3789 * @param Offsety This parameter can be one of the following values:
3790 * @arg @ref LL_ADC_OFFSET_1
3791 * @arg @ref LL_ADC_OFFSET_2
3792 * @arg @ref LL_ADC_OFFSET_3
3793 * @arg @ref LL_ADC_OFFSET_4
3794 * @param OffsetSignedSaturation This parameter can be one of the following values:
3795 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
3796 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
3797 * @retval Returned None
3798 */
LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSignedSaturation)3799 __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
3800 uint32_t OffsetSignedSaturation)
3801 {
3802 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3803 MODIFY_REG(*preg, ADC_OFR1_SSAT, OffsetSignedSaturation);
3804 }
3805
3806 /**
3807 * @brief Get Signed saturation for the ADC selected offset number 1, 2, 3 or 4:
3808 * signed offset saturation if enabled or disabled.
3809 * @rmtoll OFR1 SSAT LL_ADC_GetOffsetSignedSaturation
3810 * OFR2 SSAT LL_ADC_GetOffsetSignedSaturation
3811 * OFR3 SSAT LL_ADC_GetOffsetSignedSaturation
3812 * OFR4 SSAT LL_ADC_GetOffsetSignedSaturation
3813 * @param ADCx ADC instance
3814 * @param Offsety This parameter can be one of the following values:
3815 * @arg @ref LL_ADC_OFFSET_1
3816 * @arg @ref LL_ADC_OFFSET_2
3817 * @arg @ref LL_ADC_OFFSET_3
3818 * @arg @ref LL_ADC_OFFSET_4
3819 * @retval Returned value can be one of the following values:
3820 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
3821 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
3822 */
LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef * ADCx,uint32_t Offsety)3823 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
3824 {
3825 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3826 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSAT);
3827 }
3828
3829 /**
3830 * @brief Set Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4:
3831 * signed offset saturation if enabled or disabled.
3832 * @rmtoll OFR1 USAT LL_ADC_SetOffsetUnsignedSaturation
3833 * OFR2 USAT LL_ADC_SetOffsetUnsignedSaturation
3834 * OFR3 USAT LL_ADC_SetOffsetUnsignedSaturation
3835 * OFR4 USAT LL_ADC_SetOffsetUnsignedSaturation
3836 * @param ADCx ADC instance
3837 * @param Offsety This parameter can be one of the following values:
3838 * @arg @ref LL_ADC_OFFSET_1
3839 * @arg @ref LL_ADC_OFFSET_2
3840 * @arg @ref LL_ADC_OFFSET_3
3841 * @arg @ref LL_ADC_OFFSET_4
3842 * @param OffsetUnsignedSaturation This parameter can be one of the following values:
3843 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE
3844 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE
3845 * @retval Returned None
3846 */
LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetUnsignedSaturation)3847 __STATIC_INLINE void LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
3848 uint32_t OffsetUnsignedSaturation)
3849 {
3850 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3851 MODIFY_REG(*preg, ADC_OFR1_USAT, OffsetUnsignedSaturation);
3852 }
3853
3854 /**
3855 * @brief Get Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4:
3856 * signed offset saturation if enabled or disabled.
3857 * @rmtoll OFR1 USAT LL_ADC_GetOffsetUnsignedSaturation
3858 * OFR2 USAT LL_ADC_GetOffsetUnsignedSaturation
3859 * OFR3 USAT LL_ADC_GetOffsetUnsignedSaturation
3860 * OFR4 USAT LL_ADC_GetOffsetUnsignedSaturation
3861 * @param ADCx ADC instance
3862 * @param Offsety This parameter can be one of the following values:
3863 * @arg @ref LL_ADC_OFFSET_1
3864 * @arg @ref LL_ADC_OFFSET_2
3865 * @arg @ref LL_ADC_OFFSET_3
3866 * @arg @ref LL_ADC_OFFSET_4
3867 * @retval Returned value can be one of the following values:
3868 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE
3869 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE
3870 */
LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef * ADCx,uint32_t Offsety)3871 __STATIC_INLINE uint32_t LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
3872 {
3873 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3874 return (uint32_t) READ_BIT(*preg, ADC_OFR1_USAT);
3875 }
3876
3877 /**
3878 * @brief Set ADC gain compensation.
3879 * @note This function set the gain compensation coefficient
3880 * that is applied to raw converted data using the formula:
3881 * DATA = DATA(raw) * (gain compensation coef) / 4096
3882 * @note This function enables the gain compensation if given
3883 * coefficient is above 0, otherwise it disables it.
3884 * @note Gain compensation when enabled is applied to all channels.
3885 * @note On this STM32 series, setting of this feature is conditioned to
3886 * ADC state:
3887 * ADC must be disabled or enabled without conversion on going
3888 * on either groups regular or injected.
3889 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation
3890 * CFGR2 GCOMP LL_ADC_SetGainCompensation
3891 * @param ADCx ADC instance
3892 * @param GainCompensation This parameter can be:
3893 * 0 Gain compensation will be disabled and value set to 0
3894 * 1 -> 16393 Gain compensation will be enabled with specified value
3895 * @retval None
3896 */
LL_ADC_SetGainCompensation(ADC_TypeDef * ADCx,uint32_t GainCompensation)3897 __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
3898 {
3899 MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
3900 MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_GCOMP_GCOMP_Pos);
3901 }
3902
3903 /**
3904 * @brief Get the ADC gain compensation value
3905 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation
3906 * CFGR2 GCOMP LL_ADC_GetGainCompensation
3907 * @param ADCx ADC instance
3908 * @retval Returned value can be:
3909 * 0 Gain compensation is disabled
3910 * 1 -> 16393 Gain compensation is enabled with returned value
3911 */
LL_ADC_GetGainCompensation(const ADC_TypeDef * ADCx)3912 __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx)
3913 {
3914 return ((READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMP) == ADC_GCOMP_GCOMP) \
3915 ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
3916 }
3917
3918 /**
3919 * @}
3920 */
3921
3922 /**
3923 * @brief Set sampling time common to a group of channels.
3924 * @note Unit: ADC clock cycles.
3925 * @note On this STM32 series, sampling time scope is on ADC instance:
3926 * Sampling time common to all channels.
3927 * (on some other STM32 families, sampling time is channel wise)
3928 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3929 * converted:
3930 * sampling time constraints must be respected (sampling time can be
3931 * adjusted in function of ADC clock frequency and sampling time
3932 * setting).
3933 * Refer to device datasheet for timings values (parameters TS_vrefint,
3934 * TS_temp, ...).
3935 * @note Conversion time is the addition of sampling time and processing time.
3936 * On this STM32 series, ADC processing time is:
3937 * - 12.5 ADC clock cycles at ADC resolution 12 bits
3938 * - 10.5 ADC clock cycles at ADC resolution 10 bits
3939 * - 8.5 ADC clock cycles at ADC resolution 8 bits
3940 * - 6.5 ADC clock cycles at ADC resolution 6 bits
3941 * @note In case of ADC conversion of internal channel (VrefInt,
3942 * temperature sensor, ...), a sampling time minimum value
3943 * is required.
3944 * Refer to device datasheet.
3945 * @note On this STM32 series, setting of this feature is conditioned to
3946 * ADC state:
3947 * ADC must be disabled or enabled without conversion on going
3948 * on group regular.
3949 * @note Applicable only on ADC4 instance
3950 * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels
3951 * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
3952 * @param ADCx ADC instance
3953 * @param SamplingTimeY This parameter can be one of the following values:
3954 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3955 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3956 * @param SamplingTime This parameter can be one of the following values:
3957 * @arg @ref LL_ADC4_SAMPLINGTIME_1CYCLE_5
3958 * @arg @ref LL_ADC4_SAMPLINGTIME_3CYCLES_5
3959 * @arg @ref LL_ADC4_SAMPLINGTIME_7CYCLES_5
3960 * @arg @ref LL_ADC4_SAMPLINGTIME_12CYCLES_5
3961 * @arg @ref LL_ADC4_SAMPLINGTIME_19CYCLES_5
3962 * @arg @ref LL_ADC4_SAMPLINGTIME_39CYCLES_5
3963 * @arg @ref LL_ADC4_SAMPLINGTIME_79CYCLES_5
3964 * @arg @ref LL_ADC4_SAMPLINGTIME_814CYCLES_5
3965 * @retval None
3966 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY,uint32_t SamplingTime)3967 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
3968 uint32_t SamplingTime)
3969 {
3970 MODIFY_REG(ADCx->SMPR1,
3971 ADC4_SMPR_SMP1 << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK),
3972 SamplingTime << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK));
3973 }
3974
3975 /**
3976 * @brief Get sampling time common to a group of channels.
3977 * @note Unit: ADC clock cycles.
3978 * @note On this STM32 series, sampling time scope is on ADC instance:
3979 * Sampling time common to all channels.
3980 * (on some other STM32 families, sampling time is channel wise)
3981 * @note Conversion time is the addition of sampling time and processing time.
3982 * Refer to reference manual for ADC processing time of
3983 * this STM32 series.
3984 * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels
3985 * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
3986 * @param ADCx ADC instance (ADC4 for this device)
3987 * @param SamplingTimeY This parameter can be one of the following values:
3988 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3989 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3990 * @retval Returned value can be one of the following values:
3991 * @arg @ref LL_ADC4_SAMPLINGTIME_1CYCLE_5
3992 * @arg @ref LL_ADC4_SAMPLINGTIME_3CYCLES_5
3993 * @arg @ref LL_ADC4_SAMPLINGTIME_7CYCLES_5
3994 * @arg @ref LL_ADC4_SAMPLINGTIME_12CYCLES_5
3995 * @arg @ref LL_ADC4_SAMPLINGTIME_19CYCLES_5
3996 * @arg @ref LL_ADC4_SAMPLINGTIME_39CYCLES_5
3997 * @arg @ref LL_ADC4_SAMPLINGTIME_79CYCLES_5
3998 * @arg @ref LL_ADC4_SAMPLINGTIME_814CYCLES_5
3999 */
LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef * ADCx,uint32_t SamplingTimeY)4000 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
4001 {
4002 return (uint32_t)((READ_BIT(ADCx->SMPR1, ADC4_SMPR_SMP1 << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK)))
4003 >> (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK));
4004 }
4005
4006 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
4007 * @{
4008 */
4009
4010 /**
4011 * @brief Set ADC group regular conversion trigger source:
4012 * internal (SW start) or from external peripheral (timer event,
4013 * external interrupt line).
4014 * @note On this STM32 series, setting trigger source to external trigger
4015 * also set trigger polarity to rising edge
4016 * (default setting for compatibility with some ADC on other
4017 * STM32 families having this setting set by HW default value).
4018 * In case of need to modify trigger edge, use
4019 * function @ref LL_ADC_REG_SetTriggerEdge().
4020 * @note Availability of parameters of trigger sources from timer
4021 * depends on timers availability on the selected device.
4022 * @note On this STM32 series, setting of this feature is conditioned to
4023 * ADC state:
4024 * ADC must be disabled or enabled without conversion on going
4025 * on group regular.
4026 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource
4027 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
4028 * @param ADCx ADC instance
4029 * @param TriggerSource This parameter can be one of the following values:
4030 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
4031 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
4032 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
4033 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
4034 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
4035 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
4036 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
4037 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
4038 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
4039 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
4040 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
4041 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
4042 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
4043 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
4044 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
4045 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
4046 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
4047 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
4048 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
4049 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
4050 * @retval None
4051 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)4052 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4053 {
4054 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
4055 {
4056 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
4057 }
4058 else /* ADCx == ADC4 */
4059 {
4060 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC4_CFGR1_EXTSEL, TriggerSource);
4061 }
4062 }
4063
4064 /**
4065 * @brief Get ADC group regular conversion trigger source:
4066 * internal (SW start) or from external peripheral (timer event,
4067 * external interrupt line).
4068 * @note To determine whether group regular trigger source is
4069 * internal (SW start) or external, without detail
4070 * of which peripheral is selected as external trigger,
4071 * (equivalent to
4072 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
4073 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
4074 * @note Availability of parameters of trigger sources from timer
4075 * depends on timers availability on the selected device.
4076 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource
4077 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
4078 * @param ADCx ADC instance
4079 * @retval Returned value can be one of the following values:
4080 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
4081 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
4082 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
4083 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
4084 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
4085 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
4086 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
4087 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
4088 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
4089 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
4090 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
4091 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
4092 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
4093 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
4094 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
4095 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
4096 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
4097 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
4098 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
4099 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
4100 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)4101 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
4102 {
4103 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
4104 {
4105 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
4106
4107 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4108 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
4109 uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4110
4111 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
4112 /* to match with triggers literals definition. */
4113 return ((trigger_source
4114 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
4115 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
4116 );
4117 }
4118 else /* ADCx == ADC4 */
4119 {
4120 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC4_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
4121
4122 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4123 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
4124 uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4125
4126 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
4127 /* to match with triggers literals definition. */
4128 return ((trigger_source
4129 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC4_CFGR1_EXTSEL)
4130 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
4131 );
4132 }
4133 }
4134
4135 /**
4136 * @brief Get ADC group regular conversion trigger source internal (SW start)
4137 * or external.
4138 * @note In case of group regular trigger source set to external trigger,
4139 * to determine which peripheral is selected as external trigger,
4140 * use function @ref LL_ADC_REG_GetTriggerSource().
4141 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
4142 * @param ADCx ADC instance
4143 * @retval Value "0" if trigger source external trigger
4144 * Value "1" if trigger source SW start.
4145 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)4146 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4147 {
4148 return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
4149 }
4150
4151 /**
4152 * @brief Set ADC group regular conversion trigger polarity.
4153 * @note Applicable only for trigger source set to external trigger.
4154 * @note On this STM32 series, setting of this feature is conditioned to
4155 * ADC state:
4156 * ADC must be disabled or enabled without conversion on going
4157 * on group regular.
4158 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
4159 * @param ADCx ADC instance
4160 * @param ExternalTriggerEdge This parameter can be one of the following values:
4161 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4162 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4163 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4164 * @retval None
4165 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4166 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4167 {
4168 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
4169 }
4170
4171 /**
4172 * @brief Get ADC group regular conversion trigger polarity.
4173 * @note Applicable only for trigger source set to external trigger.
4174 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
4175 * @param ADCx ADC instance
4176 * @retval Returned value can be one of the following values:
4177 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4178 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4179 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4180 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)4181 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
4182 {
4183 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
4184 }
4185
4186 /**
4187 * @brief Set ADC trigger frequency mode.
4188 * @note ADC trigger frequency mode must be set to low frequency when
4189 * a duration is exceeded before ADC conversion start trigger event
4190 * (between ADC enable and ADC conversion start trigger event
4191 * or between two ADC conversion start trigger event).
4192 * Duration value: Refer to device datasheet, parameter "tIdle".
4193 * @note When ADC trigger frequency mode is set to low frequency,
4194 * some rearm cycles are inserted before performing ADC conversion
4195 * start, inducing a delay of 2 ADC clock cycles.
4196 * @note Usage of ADC trigger frequency mode with ADC low power mode:
4197 * - Low power mode auto wait: Only the first ADC conversion
4198 * start trigger inserts the rearm delay.
4199 * - Low power mode auto power-off: ADC trigger frequency mode
4200 * is discarded.
4201 * @note On this STM32 series, setting of this feature is conditioned to
4202 * ADC state:
4203 * ADC must be disabled or enabled without conversion on going
4204 * on group regular.
4205 * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
4206 * @param ADCx ADC instance
4207 * @param TriggerFrequencyMode This parameter can be one of the following values:
4208 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
4209 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
4210 * @retval None
4211 */
LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef * ADCx,uint32_t TriggerFrequencyMode)4212 __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
4213 {
4214 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
4215 {
4216 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, (TriggerFrequencyMode >> 2U));
4217 }
4218 else /* ADCx == ADC4 */
4219 {
4220 MODIFY_REG(ADCx->CFGR2, ADC4_CFGR2_LFTRIG, TriggerFrequencyMode);
4221 }
4222 }
4223
4224 /**
4225 * @brief Get ADC trigger frequency mode.
4226 * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
4227 * @param ADCx ADC instance
4228 * @retval Returned value can be one of the following values:
4229 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
4230 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
4231 */
LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef * ADCx)4232 __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx)
4233 {
4234 if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
4235 {
4236 return (uint32_t)((READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)) << 2U);
4237 }
4238 else /* ADCx == ADC4 */
4239 {
4240 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_LFTRIG));
4241 }
4242 }
4243
4244 /**
4245 * @brief Set ADC sampling mode.
4246 * @note This function set the ADC conversion sampling mode
4247 * @note This mode applies to regular group only.
4248 * @note Set sampling mode is applied to all conversion of regular group.
4249 * @note On this STM32 series, setting of this feature is conditioned to
4250 * ADC state:
4251 * ADC must be disabled or enabled without conversion on going
4252 * on group regular.
4253 * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode
4254 * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
4255 * @param ADCx ADC instance
4256 * @param SamplingMode This parameter can be one of the following values:
4257 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
4258 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
4259 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
4260 * @retval None
4261 */
LL_ADC_REG_SetSamplingMode(ADC_TypeDef * ADCx,uint32_t SamplingMode)4262 __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
4263 {
4264 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
4265 }
4266
4267 /**
4268 * @brief Get the ADC sampling mode
4269 * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode
4270 * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
4271 * @param ADCx ADC instance
4272 * @retval Returned value can be one of the following values:
4273 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
4274 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
4275 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
4276 */
LL_ADC_REG_GetSamplingMode(const ADC_TypeDef * ADCx)4277 __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx)
4278 {
4279 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
4280 }
4281
4282 /**
4283 * @brief Start ADC sampling phase for sampling time trigger mode
4284 * @note This function is relevant only when
4285 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
4286 * using @ref LL_ADC_REG_SetSamplingMode
4287 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
4288 * @note On this STM32 series, setting of this feature is conditioned to
4289 * ADC state:
4290 * ADC must be enabled without conversion on going on group regular,
4291 * without conversion stop command on going on group regular,
4292 * without ADC disable command on going.
4293 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
4294 * @param ADCx ADC instance
4295 * @retval None
4296 */
LL_ADC_REG_StartSamplingPhase(ADC_TypeDef * ADCx)4297 __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
4298 {
4299 SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
4300 }
4301
4302 /**
4303 * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion
4304 * @note This function is relevant only when
4305 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
4306 * using @ref LL_ADC_REG_SetSamplingMode
4307 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
4308 * - @ref LL_ADC_REG_StartSamplingPhase has been called to start
4309 * the sampling phase
4310 * @note On this STM32 series, setting of this feature is conditioned to
4311 * ADC state:
4312 * ADC must be enabled without conversion on going on group regular,
4313 * without conversion stop command on going on group regular,
4314 * without ADC disable command on going.
4315 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
4316 * @param ADCx ADC instance
4317 * @retval None
4318 */
LL_ADC_REG_StopSamplingPhase(ADC_TypeDef * ADCx)4319 __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
4320 {
4321 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
4322 }
4323
4324 /**
4325 * @brief Set ADC group regular sequencer configuration flexibility.
4326 * @note On this STM32 series, ADC group regular sequencer both modes
4327 * "fully configurable" or "not fully configurable" are
4328 * available:
4329 * - sequencer configured to fully configurable:
4330 * sequencer length and each rank
4331 * affectation to a channel are configurable.
4332 * Refer to description of function
4333 * @ref LL_ADC_REG_SetSequencerLength().
4334 * - sequencer configured to not fully configurable:
4335 * sequencer length and each rank affectation to a channel
4336 * are fixed by channel HW number.
4337 * Refer to description of function
4338 * @ref LL_ADC_REG_SetSequencerChannels().
4339 * @note On this STM32 series, setting of this feature is conditioned to
4340 * ADC state:
4341 * ADC must be disabled or enabled without conversion on going
4342 * on group regular.
4343 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
4344 * @param ADCx ADC instance
4345 * @param Configurability This parameter can be one of the following values:
4346 * @arg @ref LL_ADC_REG_SEQ_FIXED
4347 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
4348 * @retval None
4349 * @note On this STM32U5 series, this is applicable on ADC4 only.
4350 */
LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef * ADCx,uint32_t Configurability)4351 __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
4352 {
4353 MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_CHSELRMOD, Configurability);
4354 }
4355
4356 /**
4357 * @brief Get ADC group regular sequencer configuration flexibility.
4358 * @note On this STM32 series, ADC group regular sequencer both modes
4359 * "fully configurable" or "not fully configurable" are
4360 * available:
4361 * - sequencer configured to fully configurable:
4362 * sequencer length and each rank
4363 * affectation to a channel are configurable.
4364 * Refer to description of function
4365 * @ref LL_ADC_REG_SetSequencerLength().
4366 * - sequencer configured to not fully configurable:
4367 * sequencer length and each rank affectation to a channel
4368 * are fixed by channel HW number.
4369 * Refer to description of function
4370 * @ref LL_ADC_REG_SetSequencerChannels().
4371 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
4372 * @param ADCx ADC instance
4373 * @retval Returned value can be one of the following values:
4374 * @arg @ref LL_ADC_REG_SEQ_FIXED
4375 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
4376 * @note On this STM32U5 series, this is applicable on ADC4 only.
4377 */
LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef * ADCx)4378 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx)
4379 {
4380 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_CHSELRMOD));
4381 }
4382
4383 /**
4384 * @brief Set ADC group regular sequencer length and scan direction.
4385 * @note Description of ADC group regular sequencer features:
4386 * - For devices with sequencer fully configurable
4387 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4388 * sequencer length and each rank affectation to a channel
4389 * are configurable.
4390 * This function performs configuration of:
4391 * - Sequence length: Number of ranks in the scan sequence.
4392 * - Sequence direction: Unless specified in parameters, sequencer
4393 * scan direction is forward (from rank 1 to rank n).
4394 * Sequencer ranks are selected using
4395 * function "LL_ADC_REG_SetSequencerRanks()".
4396 * - For devices with sequencer not fully configurable
4397 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4398 * sequencer length and each rank affectation to a channel
4399 * are defined by channel number.
4400 * This function performs configuration of:
4401 * - Sequence length: Number of ranks in the scan sequence is
4402 * defined by number of channels set in the sequence,
4403 * rank of each channel is fixed by channel HW number.
4404 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4405 * - Sequence direction: Unless specified in parameters, sequencer
4406 * scan direction is forward (from lowest channel number to
4407 * highest channel number).
4408 * Sequencer ranks are selected using
4409 * function "LL_ADC_REG_SetSequencerChannels()".
4410 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4411 * ADC conversion on only 1 channel.
4412 * @note On this STM32 series, setting of this feature is conditioned to
4413 * ADC state:
4414 * ADC must be disabled or enabled without conversion on going
4415 * on group regular.
4416 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
4417 * @param ADCx ADC instance
4418 * @param SequencerNbRanks This parameter can be one of the following values:
4419 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4420 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4421 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4422 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4423 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4424 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4425 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4426 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4427 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4428 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4429 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4430 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4431 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4432 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4433 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4434 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4435 * Note: Specific case for ADC4, use literals LL_ADC4_REG_SEQ_SCAN_x
4436 * @retval None
4437 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4438 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4439 {
4440 if (ADCx != ADC4) /* ADC1 or ADC2 */
4441 {
4442 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
4443 }
4444 else
4445 {
4446 SET_BIT(ADCx->CHSELR, SequencerNbRanks);
4447 }
4448 }
4449
4450 /**
4451 * @brief Get ADC group regular sequencer length and scan direction.
4452 * @note Description of ADC group regular sequencer features:
4453 * - For devices with sequencer fully configurable
4454 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4455 * sequencer length and each rank affectation to a channel
4456 * are configurable.
4457 * This function retrieves:
4458 * - Sequence length: Number of ranks in the scan sequence.
4459 * - Sequence direction: Unless specified in parameters, sequencer
4460 * scan direction is forward (from rank 1 to rank n).
4461 * Sequencer ranks are selected using
4462 * function "LL_ADC_REG_SetSequencerRanks()".
4463 * - For devices with sequencer not fully configurable
4464 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4465 * sequencer length and each rank affectation to a channel
4466 * are defined by channel number.
4467 * This function retrieves:
4468 * - Sequence length: Number of ranks in the scan sequence is
4469 * defined by number of channels set in the sequence,
4470 * rank of each channel is fixed by channel HW number.
4471 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4472 * - Sequence direction: Unless specified in parameters, sequencer
4473 * scan direction is forward (from lowest channel number to
4474 * highest channel number).
4475 * Sequencer ranks are selected using
4476 * function "LL_ADC_REG_SetSequencerChannels()".
4477 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4478 * ADC conversion on only 1 channel.
4479 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
4480 * @param ADCx ADC instance
4481 * @retval Returned value can be one of the following values:
4482 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4483 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4484 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4485 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4486 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4487 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4488 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4489 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4490 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4491 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4492 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4493 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4494 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4495 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4496 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4497 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4498 * Note: Specific case for ADC4, use literals LL_ADC4_REG_SEQ_SCAN_x
4499 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)4500 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
4501 {
4502 if (ADCx != ADC4) /* ADC1 or ADC2 */
4503 {
4504 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
4505 }
4506 else
4507 {
4508 uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
4509 uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
4510 uint32_t rank_index;
4511 uint32_t rank_shifted;
4512
4513 /* Parse register for end of sequence identifier */
4514 /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
4515 (ADC_CHSELR_SQ2), value "4" to length of end of sequence
4516 identifier (0xF)*/
4517 for (rank_index = 0UL; rank_index <= (28U - 4U); rank_index += 4U)
4518 {
4519 rank_shifted = (uint32_t)(0xF0UL << rank_index);
4520 if ((channels_ranks & rank_shifted) == rank_shifted)
4521 {
4522 sequencer_length = rank_shifted;
4523 break;
4524 }
4525 }
4526
4527 return sequencer_length;
4528 }
4529 }
4530
4531 /**
4532 * @brief Set ADC group regular sequencer discontinuous mode:
4533 * sequence subdivided and scan conversions interrupted every selected
4534 * number of ranks.
4535 * @note It is not possible to enable both ADC group regular
4536 * continuous mode and sequencer discontinuous mode.
4537 * @note It is not possible to enable both ADC auto-injected mode
4538 * and ADC group regular sequencer discontinuous mode.
4539 * @note On this STM32 series, setting of this feature is conditioned to
4540 * ADC state:
4541 * ADC must be disabled or enabled without conversion on going
4542 * on group regular.
4543 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont
4544 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
4545 * @param ADCx ADC instance
4546 * @param SeqDiscont This parameter can be one of the following values:
4547 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4548 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4549 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4550 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4551 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4552 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4553 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4554 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4555 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4556 * @retval None
4557 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4558 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4559 {
4560 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM, SeqDiscont);
4561 }
4562
4563 /**
4564 * @brief Get ADC group regular sequencer discontinuous mode:
4565 * sequence subdivided and scan conversions interrupted every selected
4566 * number of ranks.
4567 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont
4568 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
4569 * @param ADCx ADC instance
4570 * @retval Returned value can be one of the following values:
4571 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4572 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4573 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4574 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4575 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4576 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4577 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4578 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4579 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4580 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)4581 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4582 {
4583 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM));
4584 }
4585
4586 /**
4587 * @brief Set ADC group regular sequence: channel on the selected
4588 * scan sequence rank.
4589 * @note This function performs configuration of:
4590 * - Channels ordering into each rank of scan sequence:
4591 * whatever channel can be placed into whatever rank.
4592 * @note On this STM32 series, ADC group regular sequencer is
4593 * fully configurable: sequencer length and each rank
4594 * affectation to a channel are configurable.
4595 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4596 * @note Depending on devices and packages, some channels may not be available.
4597 * Refer to device datasheet for channels availability.
4598 * @note On this STM32 series, to measure internal channels (VrefInt,
4599 * TempSensor, ...), measurement paths to internal channels must be
4600 * enabled separately.
4601 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4602 * @note On this STM32 series, setting of this feature is conditioned to
4603 * ADC state:
4604 * ADC must be disabled or enabled without conversion on going
4605 * on group regular.
4606 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks
4607 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks
4608 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks
4609 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks
4610 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks
4611 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks
4612 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks
4613 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks
4614 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks
4615 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks
4616 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks
4617 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks
4618 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks
4619 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks
4620 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks
4621 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
4622 * @param ADCx ADC instance
4623 * @param Rank This parameter can be one of the following values:
4624 * @arg @ref LL_ADC_REG_RANK_1
4625 * @arg @ref LL_ADC_REG_RANK_2
4626 * @arg @ref LL_ADC_REG_RANK_3
4627 * @arg @ref LL_ADC_REG_RANK_4
4628 * @arg @ref LL_ADC_REG_RANK_5
4629 * @arg @ref LL_ADC_REG_RANK_6
4630 * @arg @ref LL_ADC_REG_RANK_7
4631 * @arg @ref LL_ADC_REG_RANK_8
4632 * @arg @ref LL_ADC_REG_RANK_9
4633 * @arg @ref LL_ADC_REG_RANK_10
4634 * @arg @ref LL_ADC_REG_RANK_11
4635 * @arg @ref LL_ADC_REG_RANK_12
4636 * @arg @ref LL_ADC_REG_RANK_13
4637 * @arg @ref LL_ADC_REG_RANK_14
4638 * @arg @ref LL_ADC_REG_RANK_15
4639 * @arg @ref LL_ADC_REG_RANK_16
4640 * Note: Specific case for ADC4, use literals LL_ADC_REG_RANK_x_ADC4
4641 * @param Channel This parameter can be one of the following values:
4642 * @arg @ref LL_ADC_CHANNEL_0 (3)
4643 * @arg @ref LL_ADC_CHANNEL_1 (3)
4644 * @arg @ref LL_ADC_CHANNEL_2 (3)
4645 * @arg @ref LL_ADC_CHANNEL_3 (3)
4646 * @arg @ref LL_ADC_CHANNEL_4 (3)
4647 * @arg @ref LL_ADC_CHANNEL_5 (3)
4648 * @arg @ref LL_ADC_CHANNEL_6
4649 * @arg @ref LL_ADC_CHANNEL_7
4650 * @arg @ref LL_ADC_CHANNEL_8
4651 * @arg @ref LL_ADC_CHANNEL_9
4652 * @arg @ref LL_ADC_CHANNEL_10
4653 * @arg @ref LL_ADC_CHANNEL_11
4654 * @arg @ref LL_ADC_CHANNEL_12
4655 * @arg @ref LL_ADC_CHANNEL_13
4656 * @arg @ref LL_ADC_CHANNEL_14
4657 * @arg @ref LL_ADC_CHANNEL_15
4658 * @arg @ref LL_ADC_CHANNEL_16
4659 * @arg @ref LL_ADC_CHANNEL_17
4660 * @arg @ref LL_ADC_CHANNEL_18
4661 * @arg @ref LL_ADC_CHANNEL_19
4662 * @arg @ref LL_ADC_CHANNEL_VREFINT
4663 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4664 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4665 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
4666 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
4667 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
4668 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
4669 *
4670 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
4671 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
4672 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4673 * Other channels are slow channels (conversion rate: refer to reference manual).
4674 * @retval None
4675 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4676 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4677 {
4678 /* Set bits with content of parameter "Channel" with bits position */
4679 /* in register and register position depending on parameter "Rank". */
4680 /* Parameters "Rank" and "Channel" are used with masks because containing */
4681 /* other bits reserved for other purpose. */
4682 if (ADCx != ADC4) /* ADC1 or ADC2 */
4683 {
4684 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) \
4685 >> ADC_SQRX_REGOFFSET_POS));
4686
4687 MODIFY_REG(*preg,
4688 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4689 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
4690 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4691 }
4692 else
4693 {
4694 MODIFY_REG(ADCx->CHSELR,
4695 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4696 (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
4697 }
4698 }
4699
4700 /**
4701 * @brief Get ADC group regular sequence: channel on the selected
4702 * scan sequence rank.
4703 * @note On this STM32 series, ADC group regular sequencer is
4704 * fully configurable: sequencer length and each rank
4705 * affectation to a channel are configurable.
4706 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4707 * @note Depending on devices and packages, some channels may not be available.
4708 * Refer to device datasheet for channels availability.
4709 * @note Usage of the returned channel number:
4710 * - To reinject this channel into another function LL_ADC_xxx:
4711 * the returned channel number is only partly formatted on definition
4712 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4713 * with parts of literals LL_ADC_CHANNEL_x or using
4714 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4715 * Then the selected literal LL_ADC_CHANNEL_x can be used
4716 * as parameter for another function.
4717 * - To get the channel number in decimal format:
4718 * process the returned value with the helper macro
4719 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4720 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks
4721 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks
4722 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks
4723 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks
4724 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks
4725 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks
4726 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks
4727 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks
4728 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks
4729 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks
4730 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks
4731 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks
4732 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks
4733 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks
4734 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks
4735 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4736 * @param ADCx ADC instance
4737 * @param Rank This parameter can be one of the following values:
4738 * @arg @ref LL_ADC_REG_RANK_1
4739 * @arg @ref LL_ADC_REG_RANK_2
4740 * @arg @ref LL_ADC_REG_RANK_3
4741 * @arg @ref LL_ADC_REG_RANK_4
4742 * @arg @ref LL_ADC_REG_RANK_5
4743 * @arg @ref LL_ADC_REG_RANK_6
4744 * @arg @ref LL_ADC_REG_RANK_7
4745 * @arg @ref LL_ADC_REG_RANK_8
4746 * @arg @ref LL_ADC_REG_RANK_9
4747 * @arg @ref LL_ADC_REG_RANK_10
4748 * @arg @ref LL_ADC_REG_RANK_11
4749 * @arg @ref LL_ADC_REG_RANK_12
4750 * @arg @ref LL_ADC_REG_RANK_13
4751 * @arg @ref LL_ADC_REG_RANK_14
4752 * @arg @ref LL_ADC_REG_RANK_15
4753 * @arg @ref LL_ADC_REG_RANK_16
4754 * Note: Specific case for ADC4, use literals LL_ADC_REG_RANK_x_ADC4
4755 * @retval Returned value can be one of the following values:
4756 * @arg @ref LL_ADC_CHANNEL_0 (3)
4757 * @arg @ref LL_ADC_CHANNEL_1 (3)
4758 * @arg @ref LL_ADC_CHANNEL_2 (3)
4759 * @arg @ref LL_ADC_CHANNEL_3 (3)
4760 * @arg @ref LL_ADC_CHANNEL_4 (3)
4761 * @arg @ref LL_ADC_CHANNEL_5 (3)
4762 * @arg @ref LL_ADC_CHANNEL_6
4763 * @arg @ref LL_ADC_CHANNEL_7
4764 * @arg @ref LL_ADC_CHANNEL_8
4765 * @arg @ref LL_ADC_CHANNEL_9
4766 * @arg @ref LL_ADC_CHANNEL_10
4767 * @arg @ref LL_ADC_CHANNEL_11
4768 * @arg @ref LL_ADC_CHANNEL_12
4769 * @arg @ref LL_ADC_CHANNEL_13
4770 * @arg @ref LL_ADC_CHANNEL_14
4771 * @arg @ref LL_ADC_CHANNEL_15
4772 * @arg @ref LL_ADC_CHANNEL_16
4773 * @arg @ref LL_ADC_CHANNEL_17
4774 * @arg @ref LL_ADC_CHANNEL_18
4775 * @arg @ref LL_ADC_CHANNEL_19
4776 * @arg @ref LL_ADC_CHANNEL_VREFINT
4777 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4778 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4779 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
4780 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
4781 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
4782 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
4783 *
4784 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
4785 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
4786 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4787 * Other channels are slow channels (conversion rate: refer to reference manual).
4788 * (1, 2) For ADC channel read back from ADC register,
4789 * comparison with internal channel parameter to be done
4790 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4791 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4792 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4793 {
4794 if (ADCx != ADC4) /* ADC1 or ADC2 */
4795 {
4796 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) \
4797 >> ADC_SQRX_REGOFFSET_POS));
4798
4799 return (uint32_t)((READ_BIT(*preg,
4800 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4801 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4802 );
4803 }
4804 else
4805 {
4806 return (uint32_t)((READ_BIT(ADCx->CHSELR,
4807 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4808 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
4809 ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4810 );
4811 }
4812 }
4813
4814 /**
4815 * @brief Set ADC group regular sequencer scan direction.
4816 * @note On this STM32 series, parameter relevant only is sequencer is set
4817 * to mode not fully configurable,
4818 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
4819 * @note On some other STM32 families, this setting is not available and
4820 * the default scan direction is forward.
4821 * @note On this STM32 series, setting of this feature is conditioned to
4822 * ADC state:
4823 * ADC must be disabled or enabled without conversion on going
4824 * on group regular.
4825 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
4826 * @param ADCx ADC instance
4827 * @param ScanDirection This parameter can be one of the following values:
4828 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
4829 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
4830 * @retval None
4831 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)4832 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
4833 {
4834 MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_SCANDIR, ScanDirection);
4835 }
4836
4837 /**
4838 * @brief Get ADC group regular sequencer scan direction.
4839 * @note On this STM32 series, parameter relevant only is sequencer is set
4840 * to mode not fully configurable,
4841 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
4842 * @note On some other STM32 families, this setting is not available and
4843 * the default scan direction is forward.
4844 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
4845 * @param ADCx ADC instance
4846 * @retval Returned value can be one of the following values:
4847 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
4848 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
4849 */
LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef * ADCx)4850 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx)
4851 {
4852 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_SCANDIR));
4853 }
4854
4855 /**
4856 * @brief Set ADC group regular sequence: channel on rank corresponding to
4857 * channel number.
4858 * @note This function performs:
4859 * - Channels ordering into each rank of scan sequence:
4860 * rank of each channel is fixed by channel HW number
4861 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4862 * - Set channels selected by overwriting the current sequencer
4863 * configuration.
4864 * @note On this STM32 series, ADC group regular sequencer both modes
4865 * "fully configurable" or "not fully configurable"
4866 * are available, they can be chosen using
4867 * function @ref LL_ADC_REG_SetSequencerConfigurable().
4868 * This function can be used with setting "not fully configurable".
4869 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
4870 * and @ref LL_ADC_REG_SetSequencerLength().
4871 * @note Depending on devices and packages, some channels may not be available.
4872 * Refer to device datasheet for channels availability.
4873 * @note On this STM32 series, to measure internal channels (VrefInt,
4874 * TempSensor, ...), measurement paths to internal channels must be
4875 * enabled separately.
4876 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4877 * @note On this STM32 series, setting of this feature is conditioned to
4878 * ADC state:
4879 * ADC must be disabled or enabled without conversion on going
4880 * on group regular.
4881 * @note One or several values can be selected.
4882 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4883 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels
4884 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels
4885 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels
4886 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels
4887 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels
4888 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels
4889 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels
4890 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels
4891 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels
4892 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels
4893 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels
4894 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels
4895 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels
4896 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels
4897 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels
4898 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels
4899 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels
4900 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels
4901 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
4902 * @param ADCx ADC instance
4903 * @param Channel This parameter can be a combination of the following values:
4904 * @arg @ref LL_ADC_CHANNEL_0
4905 * @arg @ref LL_ADC_CHANNEL_1
4906 * @arg @ref LL_ADC_CHANNEL_2
4907 * @arg @ref LL_ADC_CHANNEL_3
4908 * @arg @ref LL_ADC_CHANNEL_4
4909 * @arg @ref LL_ADC_CHANNEL_5
4910 * @arg @ref LL_ADC_CHANNEL_6
4911 * @arg @ref LL_ADC_CHANNEL_7
4912 * @arg @ref LL_ADC_CHANNEL_8
4913 * @arg @ref LL_ADC_CHANNEL_9
4914 * @arg @ref LL_ADC_CHANNEL_10
4915 * @arg @ref LL_ADC_CHANNEL_11
4916 * @arg @ref LL_ADC_CHANNEL_12
4917 * @arg @ref LL_ADC_CHANNEL_13
4918 * @arg @ref LL_ADC_CHANNEL_14
4919 * @arg @ref LL_ADC_CHANNEL_15 (1)
4920 * @arg @ref LL_ADC_CHANNEL_16 (1)
4921 * @arg @ref LL_ADC_CHANNEL_17 (1)
4922 * @arg @ref LL_ADC_CHANNEL_18
4923 * @arg @ref LL_ADC_CHANNEL_VREFINT
4924 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4925 * @arg @ref LL_ADC_CHANNEL_VBAT
4926 *
4927 * (1) On STM32U5, parameter can be set in ADC group sequencer
4928 * only if sequencer is set in mode "not fully configurable",
4929 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
4930 * @retval None
4931 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)4932 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
4933 {
4934 /* Parameter "Channel" is used with masks because containing */
4935 /* other bits reserved for other purpose. */
4936 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
4937 }
4938
4939 /**
4940 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
4941 * channel number.
4942 * @note This function performs:
4943 * - Channels ordering into each rank of scan sequence:
4944 * rank of each channel is fixed by channel HW number
4945 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4946 * - Set channels selected by adding them to the current sequencer
4947 * configuration.
4948 * @note On this STM32 series, ADC group regular sequencer both modes
4949 * "fully configurable" or "not fully configurable"
4950 * are available, they can be chosen using
4951 * function @ref LL_ADC_REG_SetSequencerConfigurable().
4952 * This function can be used with setting "not fully configurable".
4953 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
4954 * and @ref LL_ADC_REG_SetSequencerLength().
4955 * @note Depending on devices and packages, some channels may not be available.
4956 * Refer to device datasheet for channels availability.
4957 * @note On this STM32 series, to measure internal channels (VrefInt,
4958 * TempSensor, ...), measurement paths to internal channels must be
4959 * enabled separately.
4960 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4961 * @note On this STM32 series, setting of this feature is conditioned to
4962 * ADC state:
4963 * ADC must be disabled or enabled without conversion on going
4964 * on group regular.
4965 * @note One or several values can be selected.
4966 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4967 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd
4968 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd
4969 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd
4970 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd
4971 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd
4972 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd
4973 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd
4974 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd
4975 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd
4976 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd
4977 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd
4978 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd
4979 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd
4980 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd
4981 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd
4982 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd
4983 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd
4984 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd
4985 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
4986 * @param ADCx ADC instance
4987 * @param Channel This parameter can be a combination of the following values:
4988 * @arg @ref LL_ADC_CHANNEL_0
4989 * @arg @ref LL_ADC_CHANNEL_1
4990 * @arg @ref LL_ADC_CHANNEL_2
4991 * @arg @ref LL_ADC_CHANNEL_3
4992 * @arg @ref LL_ADC_CHANNEL_4
4993 * @arg @ref LL_ADC_CHANNEL_5
4994 * @arg @ref LL_ADC_CHANNEL_6
4995 * @arg @ref LL_ADC_CHANNEL_7
4996 * @arg @ref LL_ADC_CHANNEL_8
4997 * @arg @ref LL_ADC_CHANNEL_9
4998 * @arg @ref LL_ADC_CHANNEL_10
4999 * @arg @ref LL_ADC_CHANNEL_11
5000 * @arg @ref LL_ADC_CHANNEL_12
5001 * @arg @ref LL_ADC_CHANNEL_13
5002 * @arg @ref LL_ADC_CHANNEL_14
5003 * @arg @ref LL_ADC_CHANNEL_15 (1)
5004 * @arg @ref LL_ADC_CHANNEL_16 (1)
5005 * @arg @ref LL_ADC_CHANNEL_17 (1)
5006 * @arg @ref LL_ADC_CHANNEL_18
5007 * @arg @ref LL_ADC_CHANNEL_VREFINT
5008 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5009 * @arg @ref LL_ADC_CHANNEL_VBAT
5010 *
5011 * (1) On STM32U5, parameter can be set in ADC group sequencer
5012 * only if sequencer is set in mode "not fully configurable",
5013 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
5014 * @retval None
5015 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)5016 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
5017 {
5018 /* Parameter "Channel" is used with masks because containing */
5019 /* other bits reserved for other purpose. */
5020 SET_BIT(ADCx->CHSELR, (1UL << ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & ADC_CHSELR_CHSEL) & 0x1FUL)));
5021 }
5022
5023 /**
5024 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
5025 * channel number.
5026 * @note This function performs:
5027 * - Channels ordering into each rank of scan sequence:
5028 * rank of each channel is fixed by channel HW number
5029 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
5030 * - Set channels selected by removing them to the current sequencer
5031 * configuration.
5032 * @note On this STM32 series, ADC group regular sequencer both modes
5033 * "fully configurable" or "not fully configurable"
5034 * are available, they can be chosen using
5035 * function @ref LL_ADC_REG_SetSequencerConfigurable().
5036 * This function can be used with setting "not fully configurable".
5037 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
5038 * and @ref LL_ADC_REG_SetSequencerLength().
5039 * @note Depending on devices and packages, some channels may not be available.
5040 * Refer to device datasheet for channels availability.
5041 * @note On this STM32 series, to measure internal channels (VrefInt,
5042 * TempSensor, ...), measurement paths to internal channels must be
5043 * enabled separately.
5044 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5045 * @note On this STM32 series, setting of this feature is conditioned to
5046 * ADC state:
5047 * ADC must be disabled or enabled without conversion on going
5048 * on group regular.
5049 * @note One or several values can be selected.
5050 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5051 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem
5052 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem
5053 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem
5054 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem
5055 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem
5056 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem
5057 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem
5058 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem
5059 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem
5060 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem
5061 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem
5062 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem
5063 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem
5064 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem
5065 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem
5066 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem
5067 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem
5068 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem
5069 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
5070 * @param ADCx ADC instance
5071 * @param Channel This parameter can be a combination of the following values:
5072 * @arg @ref LL_ADC_CHANNEL_0
5073 * @arg @ref LL_ADC_CHANNEL_1
5074 * @arg @ref LL_ADC_CHANNEL_2
5075 * @arg @ref LL_ADC_CHANNEL_3
5076 * @arg @ref LL_ADC_CHANNEL_4
5077 * @arg @ref LL_ADC_CHANNEL_5
5078 * @arg @ref LL_ADC_CHANNEL_6
5079 * @arg @ref LL_ADC_CHANNEL_7
5080 * @arg @ref LL_ADC_CHANNEL_8
5081 * @arg @ref LL_ADC_CHANNEL_9
5082 * @arg @ref LL_ADC_CHANNEL_10
5083 * @arg @ref LL_ADC_CHANNEL_11
5084 * @arg @ref LL_ADC_CHANNEL_12
5085 * @arg @ref LL_ADC_CHANNEL_13
5086 * @arg @ref LL_ADC_CHANNEL_14
5087 * @arg @ref LL_ADC_CHANNEL_15 (1)
5088 * @arg @ref LL_ADC_CHANNEL_16 (1)
5089 * @arg @ref LL_ADC_CHANNEL_17 (1)
5090 * @arg @ref LL_ADC_CHANNEL_18
5091 * @arg @ref LL_ADC_CHANNEL_VREFINT
5092 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5093 * @arg @ref LL_ADC_CHANNEL_VBAT
5094 *
5095 * (1) On STM32U5, parameter can be set in ADC group sequencer
5096 * only if sequencer is set in mode "not fully configurable",
5097 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
5098 * @retval None
5099 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)5100 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
5101 {
5102 /* Parameter "Channel" is used with masks because containing */
5103 /* other bits reserved for other purpose. */
5104 CLEAR_BIT(ADCx->CHSELR, (1UL << ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)));
5105 }
5106
5107 /**
5108 * @brief Get ADC group regular sequence: channel on rank corresponding to
5109 * channel number.
5110 * @note This function performs:
5111 * - Channels order reading into each rank of scan sequence:
5112 * rank of each channel is fixed by channel HW number
5113 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
5114 * @note On this STM32 series, ADC group regular sequencer both modes
5115 * "fully configurable" or "not fully configurable"
5116 * are available, they can be chosen using
5117 * function @ref LL_ADC_REG_SetSequencerConfigurable().
5118 * This function can be used with setting "not fully configurable".
5119 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
5120 * and @ref LL_ADC_REG_SetSequencerLength().
5121 * @note Depending on devices and packages, some channels may not be available.
5122 * Refer to device datasheet for channels availability.
5123 * @note On this STM32 series, to measure internal channels (VrefInt,
5124 * TempSensor, ...), measurement paths to internal channels must be
5125 * enabled separately.
5126 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5127 * @note On this STM32 series, setting of this feature is conditioned to
5128 * ADC state:
5129 * ADC must be disabled or enabled without conversion on going
5130 * on group regular.
5131 * @note One or several values can be retrieved.
5132 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5133 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels
5134 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels
5135 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels
5136 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels
5137 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels
5138 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels
5139 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels
5140 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels
5141 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels
5142 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels
5143 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels
5144 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels
5145 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels
5146 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels
5147 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels
5148 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels
5149 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels
5150 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels
5151 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
5152 * @param ADCx ADC instance
5153 * @retval Returned value can be a combination of the following values:
5154 * @arg @ref LL_ADC_CHANNEL_0
5155 * @arg @ref LL_ADC_CHANNEL_1
5156 * @arg @ref LL_ADC_CHANNEL_2
5157 * @arg @ref LL_ADC_CHANNEL_3
5158 * @arg @ref LL_ADC_CHANNEL_4
5159 * @arg @ref LL_ADC_CHANNEL_5
5160 * @arg @ref LL_ADC_CHANNEL_6
5161 * @arg @ref LL_ADC_CHANNEL_7
5162 * @arg @ref LL_ADC_CHANNEL_8
5163 * @arg @ref LL_ADC_CHANNEL_9
5164 * @arg @ref LL_ADC_CHANNEL_10
5165 * @arg @ref LL_ADC_CHANNEL_11
5166 * @arg @ref LL_ADC_CHANNEL_12
5167 * @arg @ref LL_ADC_CHANNEL_13
5168 * @arg @ref LL_ADC_CHANNEL_14
5169 * @arg @ref LL_ADC_CHANNEL_15 (1)
5170 * @arg @ref LL_ADC_CHANNEL_16 (1)
5171 * @arg @ref LL_ADC_CHANNEL_17 (1)
5172 * @arg @ref LL_ADC_CHANNEL_18
5173 * @arg @ref LL_ADC_CHANNEL_VREFINT
5174 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5175 * @arg @ref LL_ADC_CHANNEL_VBAT
5176 *
5177 * (1) On STM32U5, parameter can be set in ADC group sequencer
5178 * only if sequencer is set in mode "not fully configurable",
5179 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
5180 */
LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef * ADCx)5181 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx)
5182 {
5183 uint32_t channels_bitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
5184
5185 return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC4_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
5186 | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC4_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
5187 | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC4_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
5188 | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC4_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
5189 | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC4_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
5190 | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC4_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
5191 | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC4_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
5192 | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC4_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
5193 | (((channels_bitfield & ADC_CHSELR_CHSEL8) >> ADC4_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
5194 | (((channels_bitfield & ADC_CHSELR_CHSEL9) >> ADC4_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
5195 | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC4_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
5196 | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC4_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
5197 | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC4_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
5198 | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC4_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
5199 | (((channels_bitfield & ADC_CHSELR_CHSEL14) >> ADC4_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
5200 | (((channels_bitfield & ADC_CHSELR_CHSEL15) >> ADC4_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
5201 | (((channels_bitfield & ADC_CHSELR_CHSEL16) >> ADC4_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
5202 | (((channels_bitfield & ADC_CHSELR_CHSEL17) >> ADC4_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
5203 | (((channels_bitfield & ADC_CHSELR_CHSEL18) >> ADC4_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
5204 | (((channels_bitfield & ADC_CHSELR_CHSEL19) >> ADC4_CHSELR_CHSEL19_BITOFFSET_POS) * LL_ADC_CHANNEL_19)
5205 | (((channels_bitfield & ADC_CHSELR_CHSEL20) >> ADC4_CHSELR_CHSEL20_BITOFFSET_POS) * LL_ADC_CHANNEL_20)
5206 | (((channels_bitfield & ADC_CHSELR_CHSEL21) >> ADC4_CHSELR_CHSEL21_BITOFFSET_POS) * LL_ADC_CHANNEL_21)
5207 | (((channels_bitfield & ADC_CHSELR_CHSEL22) >> ADC4_CHSELR_CHSEL22_BITOFFSET_POS) * LL_ADC_CHANNEL_22)
5208 | (((channels_bitfield & ADC_CHSELR_CHSEL23) >> ADC4_CHSELR_CHSEL23_BITOFFSET_POS) * LL_ADC_CHANNEL_23)
5209
5210 );
5211 }
5212
5213 /**
5214 * @brief Set ADC Channel Preselection to LL_ADC_CHANNEL_x, x = 0 to 19.
5215 * @note This function set the the value for the channel preselection register
5216 * corresponding to ADC channel to be selected.
5217 * @note Caution: This is not valid for ADC4.
5218 * @param ADCx ADC instance.
5219 * @param Channel This parameter can be one of the following values:
5220 * @arg @ref LL_ADC_CHANNEL_0
5221 * @arg @ref LL_ADC_CHANNEL_1
5222 * @arg @ref LL_ADC_CHANNEL_2
5223 * @arg @ref LL_ADC_CHANNEL_3
5224 * @arg @ref LL_ADC_CHANNEL_4
5225 * @arg @ref LL_ADC_CHANNEL_5
5226 * @arg @ref LL_ADC_CHANNEL_6
5227 * @arg @ref LL_ADC_CHANNEL_7
5228 * @arg @ref LL_ADC_CHANNEL_8
5229 * @arg @ref LL_ADC_CHANNEL_9
5230 * @arg @ref LL_ADC_CHANNEL_10
5231 * @arg @ref LL_ADC_CHANNEL_11
5232 * @arg @ref LL_ADC_CHANNEL_12
5233 * @arg @ref LL_ADC_CHANNEL_13
5234 * @arg @ref LL_ADC_CHANNEL_14
5235 * @arg @ref LL_ADC_CHANNEL_15
5236 * @arg @ref LL_ADC_CHANNEL_16
5237 * @arg @ref LL_ADC_CHANNEL_17
5238 * @arg @ref LL_ADC_CHANNEL_18
5239 * @arg @ref LL_ADC_CHANNEL_19
5240 * @arg @ref LL_ADC_CHANNEL_VREFINT
5241 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5242 * @arg @ref LL_ADC_CHANNEL_VBAT
5243 *
5244 * @retval None
5245 */
LL_ADC_SetChannelPreselection(ADC_TypeDef * ADCx,uint32_t Channel)5246 __STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
5247 {
5248 __IO uint32_t channel_preselectione = READ_REG(ADCx->PCSEL);
5249 WRITE_REG(ADCx->PCSEL,
5250 channel_preselectione | (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)Channel) & 0x1FUL)));
5251 }
5252
5253 /**
5254 * @brief Get ADC Channel Preselection register value.
5255 * @note This function set the the value for the channel preselection register
5256 * corresponding to ADC channel to be selected.
5257 * @note Caution: This is not valid for ADC4.
5258 * @param ADCx ADC instance.
5259 *
5260 * @retval Returned decimal value that can correspend to one or multiple channels:
5261 * @rmtoll PCSEL PCSEL0 LL_ADC_CHANNEL_0
5262 * PCSEL PCSEL1 LL_ADC_CHANNEL_1
5263 * PCSEL PCSEL2 LL_ADC_CHANNEL_2
5264 * PCSEL PCSEL3 LL_ADC_CHANNEL_3
5265 * PCSEL PCSEL4 LL_ADC_CHANNEL_4
5266 * PCSEL PCSEL5 LL_ADC_CHANNEL_5
5267 * PCSEL PCSEL6 LL_ADC_CHANNEL_6
5268 * PCSEL PCSEL7 LL_ADC_CHANNEL_7
5269 * PCSEL PCSEL8 LL_ADC_CHANNEL_8
5270 * PCSEL PCSEL9 LL_ADC_CHANNEL_9
5271 * PCSEL PCSEL10 LL_ADC_CHANNEL_10
5272 * PCSEL PCSEL11 LL_ADC_CHANNEL_11
5273 * PCSEL PCSEL12 LL_ADC_CHANNEL_12
5274 * PCSEL PCSEL13 LL_ADC_CHANNEL_13
5275 * PCSEL PCSEL14 LL_ADC_CHANNEL_14
5276 * PCSEL PCSEL15 LL_ADC_CHANNEL_15
5277 * PCSEL PCSEL16 LL_ADC_CHANNEL_16
5278 * PCSEL PCSEL17 LL_ADC_CHANNEL_17
5279 * PCSEL PCSEL18 LL_ADC_CHANNEL_18
5280 * PCSEL PCSEL19 LL_ADC_CHANNEL_19
5281 *
5282 * @note User helper macro @ref __LL_ADC_DECIMAL_NB_TO_CHANNEL().
5283 */
LL_ADC_GetChannelPreselection(const ADC_TypeDef * ADCx)5284 __STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *ADCx)
5285 {
5286 return (uint32_t)(READ_BIT(ADCx->PCSEL, ADC_PCSEL_PCSEL));
5287 }
5288
5289 /**
5290 * @brief Set ADC low power mode.
5291 * @note Description of ADC low power mode:
5292 * - ADC low power mode "auto power-off":
5293 * the ADC automatically powers-off after a conversion and
5294 * automatically wakes up when a new conversion is triggered
5295 * (with startup time between trigger and start of sampling).
5296 * This feature can be combined with low power mode "auto wait".
5297 * @note On this STM32 series, setting of this feature is conditioned to
5298 * ADC state:
5299 * ADC must be disabled.
5300 * @rmtoll PWRR AUTOFF LL_ADC_SetLPModeAutoPowerOff
5301 * @param ADCx ADC instance
5302 * @param LowPowerMode This parameter can be one of the following values:
5303 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
5304 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
5305 * @retval None
5306 */
LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef * ADCx,uint32_t LowPowerMode)5307 __STATIC_INLINE void LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
5308 {
5309 MODIFY_REG(ADCx->PWRR, ADC4_PWRR_AUTOFF, LowPowerMode);
5310 }
5311
5312 /**
5313 * @brief Get ADC low power mode.
5314 * @note Description of ADC low power mode:
5315 * - ADC low power mode "auto power-off":
5316 * the ADC automatically powers-off after a conversion and
5317 * automatically wakes up when a new conversion is triggered
5318 * (with startup time between trigger and start of sampling).
5319 * This feature can be combined with low power mode "auto wait".
5320 * @rmtoll PW AUTOFF LL_ADC_GetLPModeAutoPowerOff
5321 * @param ADCx ADC instance
5322 * @retval Returned value can be one of the following values:
5323 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
5324 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
5325 */
LL_ADC_GetLPModeAutoPowerOff(const ADC_TypeDef * ADCx)5326 __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoPowerOff(const ADC_TypeDef *ADCx)
5327 {
5328 return (uint32_t)(READ_BIT(ADCx->PWRR, ADC4_PWRR_AUTOFF));
5329 }
5330
5331 /**
5332 * @brief Set ADC low power mode: deep power down in autonomous mode
5333 * @note On this STM32 series, setting of this feature is conditioned to
5334 * ADC state:
5335 * ADC must be disabled.
5336 * @rmtoll PWRR DPD LL_ADC_SetLPModeAutonomousDPD
5337 * @param ADCx ADC instance
5338 * @param LowPowerMode This parameter can be one of the following values:
5339 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
5340 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
5341 * @retval None
5342 */
LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef * ADCx,uint32_t LowPowerMode)5343 __STATIC_INLINE void LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
5344 {
5345 MODIFY_REG(ADCx->PWRR, ADC4_PWRR_DPD, LowPowerMode);
5346 }
5347
5348 /**
5349 * @brief Get ADC low power mode: deep power down in autonomous mode
5350 * @rmtoll PWRR DPD LL_ADC_GetLPModeAutonomousDPD
5351 * @param ADCx ADC instance
5352 * @retval Returned value can be one of the following values:
5353 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
5354 * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
5355 */
LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef * ADCx)5356 __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef *ADCx)
5357 {
5358 return (uint32_t)(READ_BIT(ADCx->PWRR, ADC4_PWRR_DPD));
5359 }
5360
5361 /**
5362 * @brief Set ADC VREF protection when multiple ADCs are working simultaneously
5363 * @note In case of simultaneous sampling phase of ADC4 and ADC1/2,
5364 * ADC4 is put on hold during one or two ADC4 clock cycles to avoid noise on Vref+.
5365 * ADC state:
5366 * ADC must be disabled.
5367 * @rmtoll PWRR VREFPROT LL_ADC_SetVrefProtection
5368 * PWRR VREFSECSMP LL_ADC_SetVrefProtection
5369 * @param ADCx ADC instance
5370 * @param VrefProtection This parameter can be one of the following values:
5371 * @arg @ref LL_ADC_VREF_PROT_DISABLE
5372 * @arg @ref LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE
5373 * @arg @ref LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE
5374 * @retval None
5375 */
LL_ADC_SetVrefProtection(ADC_TypeDef * ADCx,uint32_t VrefProtection)5376 __STATIC_INLINE void LL_ADC_SetVrefProtection(ADC_TypeDef *ADCx, uint32_t VrefProtection)
5377 {
5378 MODIFY_REG(ADCx->PWRR, ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP, VrefProtection);
5379 }
5380
5381 /**
5382 * @brief ADC VREF protection when multiple ADCs are working simultaneously
5383 * @rmtoll PWRR VREFPROT LL_ADC_GetVrefProtection
5384 * PWRR VREFSECSMP LL_ADC_GetVrefProtection
5385 * @param ADCx ADC instance
5386 * @retval Returned value can be one of the following values:
5387 * @arg @ref LL_ADC_VREF_PROT_DISABLE
5388 * @arg @ref LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE
5389 * @arg @ref LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE
5390 */
LL_ADC_GetVrefProtection(const ADC_TypeDef * ADCx)5391 __STATIC_INLINE uint32_t LL_ADC_GetVrefProtection(const ADC_TypeDef *ADCx)
5392 {
5393 return (uint32_t)(READ_BIT(ADCx->PWRR, ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP));
5394 }
5395
5396 /**
5397 * @brief Set ADC continuous conversion mode on ADC group regular.
5398 * @note Description of ADC continuous conversion mode:
5399 * - single mode: one conversion per trigger
5400 * - continuous mode: after the first trigger, following
5401 * conversions launched successively automatically.
5402 * @note It is not possible to enable both ADC group regular
5403 * continuous mode and sequencer discontinuous mode.
5404 * @note On this STM32 series, setting of this feature is conditioned to
5405 * ADC state:
5406 * ADC must be disabled or enabled without conversion on going
5407 * on group regular.
5408 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
5409 * @param ADCx ADC instance
5410 * @param Continuous This parameter can be one of the following values:
5411 * @arg @ref LL_ADC_REG_CONV_SINGLE
5412 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
5413 * @retval None
5414 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)5415 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
5416 {
5417 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
5418 }
5419
5420 /**
5421 * @brief Get ADC continuous conversion mode on ADC group regular.
5422 * @note Description of ADC continuous conversion mode:
5423 * - single mode: one conversion per trigger
5424 * - continuous mode: after the first trigger, following
5425 * conversions launched successively automatically.
5426 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
5427 * @param ADCx ADC instance
5428 * @retval Returned value can be one of the following values:
5429 * @arg @ref LL_ADC_REG_CONV_SINGLE
5430 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
5431 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)5432 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
5433 {
5434 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
5435 }
5436
5437 /**
5438 * @brief Set ADC data transfer mode
5439 * @note Conversion data can be either:
5440 * - Available in Data Register
5441 * - Transferred by DMA in one shot mode
5442 * - Transferred by DMA in circular mode
5443 * - Transferred to MDF data register
5444 * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode
5445 * @param ADCx ADC instance
5446 * @param DataTransferMode This parameter can be one of the following values:
5447 * @arg @ref LL_ADC_REG_DR_TRANSFER
5448 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
5449 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
5450 * @arg @ref LL_ADC_REG_MDF_TRANSFER
5451 * @retval None
5452 */
LL_ADC_REG_SetDataTransferMode(ADC_TypeDef * ADCx,uint32_t DataTransferMode)5453 __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
5454 {
5455 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMNGT, DataTransferMode);
5456 }
5457
5458 /**
5459 * @brief Get ADC data transfer mode
5460 * @note Conversion data can be either:
5461 * - Available in Data Register
5462 * - Transferred by DMA in one shot mode
5463 * - Transferred by DMA in circular mode
5464 * - Transferred to DFSDM data register
5465 * @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode
5466 * @param ADCx ADC instance
5467 * @retval Returned value can be one of the following values:
5468 * @arg @ref LL_ADC_REG_DR_TRANSFER
5469 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
5470 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
5471 * @arg @ref LL_ADC_REG_MDF_TRANSFER
5472 */
LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef * ADCx)5473 __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx)
5474 {
5475 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMNGT));
5476 }
5477
5478 /**
5479 * @brief Set ADC group regular conversion data transfer: no transfer or
5480 * transfer by DMA, and DMA requests mode.
5481 * @note If transfer by DMA selected, specifies the DMA requests
5482 * mode:
5483 * - Limited mode (One shot mode): DMA transfer requests are stopped
5484 * when number of DMA data transfers (number of
5485 * ADC conversions) is reached.
5486 * This ADC mode is intended to be used with DMA mode non-circular.
5487 * - Unlimited mode: DMA transfer requests are unlimited,
5488 * whatever number of DMA data transfers (number of
5489 * ADC conversions).
5490 * This ADC mode is intended to be used with DMA mode circular.
5491 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5492 * mode non-circular:
5493 * when DMA transfers size will be reached, DMA will stop transfers of
5494 * ADC conversions data ADC will raise an overrun error
5495 * (overrun flag and interruption if enabled).
5496 * @note To configure DMA source address (peripheral address),
5497 * use function @ref LL_ADC_DMA_GetRegAddr().
5498 * @note On this STM32 series, setting of this feature is conditioned to
5499 * ADC state:
5500 * ADC must be disabled or enabled without conversion on going
5501 * on group regular.
5502 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer
5503 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
5504 * @param ADCx ADC instance
5505 * @param DMATransfer This parameter can be one of the following values:
5506 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
5507 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
5508 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
5509 * @retval None
5510 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)5511 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
5512 {
5513 MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG, DMATransfer);
5514 }
5515
5516 /**
5517 * @brief Get ADC group regular conversion data transfer: no transfer or
5518 * transfer by DMA, and DMA requests mode.
5519 * @note If transfer by DMA selected, specifies the DMA requests
5520 * mode:
5521 * - Limited mode (One shot mode): DMA transfer requests are stopped
5522 * when number of DMA data transfers (number of
5523 * ADC conversions) is reached.
5524 * This ADC mode is intended to be used with DMA mode non-circular.
5525 * - Unlimited mode: DMA transfer requests are unlimited,
5526 * whatever number of DMA data transfers (number of
5527 * ADC conversions).
5528 * This ADC mode is intended to be used with DMA mode circular.
5529 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5530 * mode non-circular:
5531 * when DMA transfers size will be reached, DMA will stop transfers of
5532 * ADC conversions data ADC will raise an overrun error
5533 * (overrun flag and interruption if enabled).
5534 * @note To configure DMA source address (peripheral address),
5535 * use function @ref LL_ADC_DMA_GetRegAddr().
5536 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer
5537 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
5538 * @param ADCx ADC instance
5539 * @retval Returned value can be one of the following values:
5540 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
5541 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
5542 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
5543 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)5544 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
5545 {
5546 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG));
5547 }
5548
5549 /**
5550 * @brief Set ADC group regular behavior in case of overrun:
5551 * data preserved or overwritten.
5552 * @note Compatibility with devices without feature overrun:
5553 * other devices without this feature have a behavior
5554 * equivalent to data overwritten.
5555 * The default setting of overrun is data preserved.
5556 * Therefore, for compatibility with all devices, parameter
5557 * overrun should be set to data overwritten.
5558 * @note On this STM32 series, setting of this feature is conditioned to
5559 * ADC state:
5560 * ADC must be disabled or enabled without conversion on going
5561 * on group regular.
5562 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
5563 * @param ADCx ADC instance
5564 * @param Overrun This parameter can be one of the following values:
5565 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
5566 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
5567 * @retval None
5568 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)5569 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
5570 {
5571 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
5572 }
5573
5574 /**
5575 * @brief Get ADC group regular behavior in case of overrun:
5576 * data preserved or overwritten.
5577 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
5578 * @param ADCx ADC instance
5579 * @retval Returned value can be one of the following values:
5580 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
5581 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
5582 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)5583 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
5584 {
5585 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
5586 }
5587
5588 /**
5589 * @}
5590 */
5591
5592 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
5593 * @{
5594 */
5595
5596 /**
5597 * @brief Set ADC group injected conversion trigger source:
5598 * internal (SW start) or from external peripheral (timer event,
5599 * external interrupt line).
5600 * @note On this STM32 series, setting trigger source to external trigger
5601 * also set trigger polarity to rising edge
5602 * (default setting for compatibility with some ADC on other
5603 * STM32 families having this setting set by HW default value).
5604 * In case of need to modify trigger edge, use
5605 * function @ref LL_ADC_INJ_SetTriggerEdge().
5606 * @note Availability of parameters of trigger sources from timer
5607 * depends on timers availability on the selected device.
5608 * @note On this STM32 series, setting of this feature is conditioned to
5609 * ADC state:
5610 * ADC must not be disabled. Can be enabled with or without conversion
5611 * on going on either groups regular or injected.
5612 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource
5613 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
5614 * @param ADCx ADC instance
5615 * @param TriggerSource This parameter can be one of the following values:
5616 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5617 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5618 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5619 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5620 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
5621 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
5622 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
5623 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
5624 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
5625 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5626 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
5627 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
5628 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
5629 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5630 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
5631 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5632 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
5633 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
5634 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
5635 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
5636 * @retval None
5637 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)5638 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
5639 {
5640 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
5641 }
5642
5643 /**
5644 * @brief Get ADC group injected conversion trigger source:
5645 * internal (SW start) or from external peripheral (timer event,
5646 * external interrupt line).
5647 * @note To determine whether group injected trigger source is
5648 * internal (SW start) or external, without detail
5649 * of which peripheral is selected as external trigger,
5650 * (equivalent to
5651 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
5652 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
5653 * @note Availability of parameters of trigger sources from timer
5654 * depends on timers availability on the selected device.
5655 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource
5656 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
5657 * @param ADCx ADC instance
5658 * @retval Returned value can be one of the following values:
5659 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5660 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5661 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5662 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5663 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
5664 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
5665 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
5666 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
5667 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
5668 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5669 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
5670 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
5671 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
5672 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5673 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
5674 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5675 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
5676 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
5677 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
5678 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
5679 */
LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef * ADCx)5680 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
5681 {
5682 __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
5683
5684 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
5685 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
5686 uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
5687
5688 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
5689 /* to match with triggers literals definition. */
5690 return ((trigger_source
5691 & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
5692 | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
5693 );
5694 }
5695
5696 /**
5697 * @brief Get ADC group injected conversion trigger source internal (SW start)
5698 or external
5699 * @note In case of group injected trigger source set to external trigger,
5700 * to determine which peripheral is selected as external trigger,
5701 * use function @ref LL_ADC_INJ_GetTriggerSource.
5702 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
5703 * @param ADCx ADC instance
5704 * @retval Value "0" if trigger source external trigger
5705 * Value "1" if trigger source SW start.
5706 */
LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)5707 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
5708 {
5709 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
5710 }
5711
5712 /**
5713 * @brief Set ADC group injected conversion trigger polarity.
5714 * Applicable only for trigger source set to external trigger.
5715 * @note On this STM32 series, setting of this feature is conditioned to
5716 * ADC state:
5717 * ADC must not be disabled. Can be enabled with or without conversion
5718 * on going on either groups regular or injected.
5719 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
5720 * @param ADCx ADC instance
5721 * @param ExternalTriggerEdge This parameter can be one of the following values:
5722 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5723 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5724 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5725 * @retval None
5726 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)5727 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
5728 {
5729 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
5730 }
5731
5732 /**
5733 * @brief Get ADC group injected conversion trigger polarity.
5734 * Applicable only for trigger source set to external trigger.
5735 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
5736 * @param ADCx ADC instance
5737 * @retval Returned value can be one of the following values:
5738 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5739 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5740 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5741 */
LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef * ADCx)5742 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
5743 {
5744 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
5745 }
5746
5747 /**
5748 * @brief Set ADC group injected sequencer length and scan direction.
5749 * @note This function performs configuration of:
5750 * - Sequence length: Number of ranks in the scan sequence.
5751 * - Sequence direction: Unless specified in parameters, sequencer
5752 * scan direction is forward (from rank 1 to rank n).
5753 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
5754 * ADC conversion on only 1 channel.
5755 * @note On this STM32 series, setting of this feature is conditioned to
5756 * ADC state:
5757 * ADC must not be disabled. Can be enabled with or without conversion
5758 * on going on either groups regular or injected.
5759 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
5760 * @param ADCx ADC instance
5761 * @param SequencerNbRanks This parameter can be one of the following values:
5762 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5763 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5764 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5765 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5766 * @retval None
5767 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)5768 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
5769 {
5770 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
5771 }
5772
5773 /**
5774 * @brief Get ADC group injected sequencer length and scan direction.
5775 * @note This function retrieves:
5776 * - Sequence length: Number of ranks in the scan sequence.
5777 * - Sequence direction: Unless specified in parameters, sequencer
5778 * scan direction is forward (from rank 1 to rank n).
5779 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
5780 * ADC conversion on only 1 channel.
5781 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
5782 * @param ADCx ADC instance
5783 * @retval Returned value can be one of the following values:
5784 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5785 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5786 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5787 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5788 */
LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef * ADCx)5789 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
5790 {
5791 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
5792 }
5793
5794 /**
5795 * @brief Set ADC group injected sequencer discontinuous mode:
5796 * sequence subdivided and scan conversions interrupted every selected
5797 * number of ranks.
5798 * @note It is not possible to enable both ADC group injected
5799 * auto-injected mode and sequencer discontinuous mode.
5800 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
5801 * @param ADCx ADC instance
5802 * @param SeqDiscont This parameter can be one of the following values:
5803 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
5804 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
5805 * @retval None
5806 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)5807 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
5808 {
5809 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JDISCEN, SeqDiscont);
5810 }
5811
5812 /**
5813 * @brief Get ADC group injected sequencer discontinuous mode:
5814 * sequence subdivided and scan conversions interrupted every selected
5815 * number of ranks.
5816 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
5817 * @param ADCx ADC instance
5818 * @retval Returned value can be one of the following values:
5819 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
5820 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
5821 */
LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef * ADCx)5822 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
5823 {
5824 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JDISCEN));
5825 }
5826
5827 /**
5828 * @brief Set ADC group injected sequence: channel on the selected
5829 * sequence rank.
5830 * @note Depending on devices and packages, some channels may not be available.
5831 * Refer to device datasheet for channels availability.
5832 * @note On this STM32 series, to measure internal channels (VrefInt,
5833 * TempSensor, ...), measurement paths to internal channels must be
5834 * enabled separately.
5835 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5836 * @note On STM32U5, some fast channels are available: fast analog inputs
5837 * coming from GPIO pads (ADC_IN0..5).
5838 * @note On this STM32 series, setting of this feature is conditioned to
5839 * ADC state:
5840 * ADC must not be disabled. Can be enabled with or without conversion
5841 * on going on either groups regular or injected.
5842 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
5843 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
5844 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
5845 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
5846 * @param ADCx ADC instance
5847 * @param Rank This parameter can be one of the following values:
5848 * @arg @ref LL_ADC_INJ_RANK_1
5849 * @arg @ref LL_ADC_INJ_RANK_2
5850 * @arg @ref LL_ADC_INJ_RANK_3
5851 * @arg @ref LL_ADC_INJ_RANK_4
5852 * @param Channel This parameter can be one of the following values:
5853 * @arg @ref LL_ADC_CHANNEL_0 (3)
5854 * @arg @ref LL_ADC_CHANNEL_1 (3)
5855 * @arg @ref LL_ADC_CHANNEL_2 (3)
5856 * @arg @ref LL_ADC_CHANNEL_3 (3)
5857 * @arg @ref LL_ADC_CHANNEL_4 (3)
5858 * @arg @ref LL_ADC_CHANNEL_5 (3)
5859 * @arg @ref LL_ADC_CHANNEL_6
5860 * @arg @ref LL_ADC_CHANNEL_7
5861 * @arg @ref LL_ADC_CHANNEL_8
5862 * @arg @ref LL_ADC_CHANNEL_9
5863 * @arg @ref LL_ADC_CHANNEL_10
5864 * @arg @ref LL_ADC_CHANNEL_11
5865 * @arg @ref LL_ADC_CHANNEL_12
5866 * @arg @ref LL_ADC_CHANNEL_13
5867 * @arg @ref LL_ADC_CHANNEL_14
5868 * @arg @ref LL_ADC_CHANNEL_15
5869 * @arg @ref LL_ADC_CHANNEL_16
5870 * @arg @ref LL_ADC_CHANNEL_17
5871 * @arg @ref LL_ADC_CHANNEL_18
5872 * @arg @ref LL_ADC_CHANNEL_19
5873 * @arg @ref LL_ADC_CHANNEL_VREFINT
5874 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5875 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5876 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
5877 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
5878 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
5879 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
5880 *
5881 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
5882 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
5883 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5884 * Other channels are slow channels (conversion rate: refer to reference manual).
5885 * @retval None
5886 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)5887 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
5888 {
5889 /* Set bits with content of parameter "Channel" with bits position */
5890 /* in register depending on parameter "Rank". */
5891 /* Parameters "Rank" and "Channel" are used with masks because containing */
5892 /* other bits reserved for other purpose. */
5893 MODIFY_REG(ADCx->JSQR,
5894 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
5895 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
5896 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
5897 }
5898
5899 /**
5900 * @brief Get ADC group injected sequence: channel on the selected
5901 * sequence rank.
5902 * @note Depending on devices and packages, some channels may not be available.
5903 * Refer to device datasheet for channels availability.
5904 * @note Usage of the returned channel number:
5905 * - To reinject this channel into another function LL_ADC_xxx:
5906 * the returned channel number is only partly formatted on definition
5907 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5908 * with parts of literals LL_ADC_CHANNEL_x or using
5909 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5910 * Then the selected literal LL_ADC_CHANNEL_x can be used
5911 * as parameter for another function.
5912 * - To get the channel number in decimal format:
5913 * process the returned value with the helper macro
5914 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5915 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks
5916 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks
5917 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks
5918 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
5919 * @param ADCx ADC instance
5920 * @param Rank This parameter can be one of the following values:
5921 * @arg @ref LL_ADC_INJ_RANK_1
5922 * @arg @ref LL_ADC_INJ_RANK_2
5923 * @arg @ref LL_ADC_INJ_RANK_3
5924 * @arg @ref LL_ADC_INJ_RANK_4
5925 * @retval Returned value can be one of the following values:
5926 * @arg @ref LL_ADC_CHANNEL_0 (3)
5927 * @arg @ref LL_ADC_CHANNEL_1 (3)
5928 * @arg @ref LL_ADC_CHANNEL_2 (3)
5929 * @arg @ref LL_ADC_CHANNEL_3 (3)
5930 * @arg @ref LL_ADC_CHANNEL_4 (3)
5931 * @arg @ref LL_ADC_CHANNEL_5 (3)
5932 * @arg @ref LL_ADC_CHANNEL_6
5933 * @arg @ref LL_ADC_CHANNEL_7
5934 * @arg @ref LL_ADC_CHANNEL_8
5935 * @arg @ref LL_ADC_CHANNEL_9
5936 * @arg @ref LL_ADC_CHANNEL_10
5937 * @arg @ref LL_ADC_CHANNEL_11
5938 * @arg @ref LL_ADC_CHANNEL_12
5939 * @arg @ref LL_ADC_CHANNEL_13
5940 * @arg @ref LL_ADC_CHANNEL_14
5941 * @arg @ref LL_ADC_CHANNEL_15
5942 * @arg @ref LL_ADC_CHANNEL_16
5943 * @arg @ref LL_ADC_CHANNEL_17
5944 * @arg @ref LL_ADC_CHANNEL_18
5945 * @arg @ref LL_ADC_CHANNEL_19
5946 * @arg @ref LL_ADC_CHANNEL_VREFINT
5947 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5948 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5949 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
5950 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
5951 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
5952 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
5953 *
5954 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
5955 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
5956 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5957 * Other channels are slow channels (conversion rate: refer to reference manual).
5958 * (1, 2) For ADC channel read back from ADC register,
5959 * comparison with internal channel parameter to be done
5960 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
5961 */
LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)5962 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
5963 {
5964 return (uint32_t)((READ_BIT(ADCx->JSQR,
5965 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
5966 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
5967 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
5968 );
5969 }
5970
5971 /**
5972 * @brief Set ADC group injected conversion trigger:
5973 * independent or from ADC group regular.
5974 * @note This mode can be used to extend number of data registers
5975 * updated after one ADC conversion trigger and with data
5976 * permanently kept (not erased by successive conversions of scan of
5977 * ADC sequencer ranks), up to 5 data registers:
5978 * 1 data register on ADC group regular, 4 data registers
5979 * on ADC group injected.
5980 * @note If ADC group injected injected trigger source is set to an
5981 * external trigger, this feature must be must be set to
5982 * independent trigger.
5983 * ADC group injected automatic trigger is compliant only with
5984 * group injected trigger source set to SW start, without any
5985 * further action on ADC group injected conversion start or stop:
5986 * in this case, ADC group injected is controlled only
5987 * from ADC group regular.
5988 * @note It is not possible to enable both ADC group injected
5989 * auto-injected mode and sequencer discontinuous mode.
5990 * @note On this STM32 series, setting of this feature is conditioned to
5991 * ADC state:
5992 * ADC must be disabled or enabled without conversion on going
5993 * on either groups regular or injected.
5994 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
5995 * @param ADCx ADC instance
5996 * @param TrigAuto This parameter can be one of the following values:
5997 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5998 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5999 * @retval None
6000 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)6001 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
6002 {
6003 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JAUTO, TrigAuto);
6004 }
6005
6006 /**
6007 * @brief Get ADC group injected conversion trigger:
6008 * independent or from ADC group regular.
6009 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
6010 * @param ADCx ADC instance
6011 * @retval Returned value can be one of the following values:
6012 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
6013 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
6014 */
LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef * ADCx)6015 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
6016 {
6017 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JAUTO));
6018 }
6019
6020 /**
6021 * @brief Set one context on ADC group injected that will be checked in
6022 * contexts queue.
6023 * @note A context is a setting of group injected sequencer:
6024 * - group injected trigger
6025 * - sequencer length
6026 * - sequencer ranks
6027 * This function is intended to be used when contexts queue is enabled,
6028 * because the sequence must be fully configured in one time
6029 * (functions to set separately injected trigger and sequencer channels
6030 * cannot be used):
6031 * @note In the contexts queue, only the active context can be read.
6032 * The parameters of this function can be read using functions:
6033 * @arg @ref LL_ADC_INJ_GetTriggerSource()
6034 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
6035 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
6036 * @note On this STM32 series, to measure internal channels (VrefInt,
6037 * TempSensor, ...), measurement paths to internal channels must be
6038 * enabled separately.
6039 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
6040 * @note On STM32U5, some fast channels are available: fast analog inputs
6041 * coming from GPIO pads (ADC_IN0..5).
6042 * @note On this STM32 series, setting of this feature is conditioned to
6043 * ADC state:
6044 * ADC must not be disabled. Can be enabled with or without conversion
6045 * on going on either groups regular or injected.
6046 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext
6047 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext
6048 * JSQR JL LL_ADC_INJ_ConfigQueueContext
6049 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext
6050 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext
6051 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext
6052 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
6053 * @param ADCx ADC instance
6054 * @param TriggerSource This parameter can be one of the following values:
6055 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
6056 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
6057 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
6058 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
6059 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
6060 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
6061 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
6062 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
6063 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
6064 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
6065 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
6066 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
6067 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
6068 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
6069 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
6070 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
6071 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
6072 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
6073 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
6074 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
6075 * @param ExternalTriggerEdge This parameter can be one of the following values:
6076 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
6077 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
6078 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
6079 *
6080 * Note: This parameter is discarded in case of SW start:
6081 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
6082 * @param SequencerNbRanks This parameter can be one of the following values:
6083 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
6084 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
6085 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
6086 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
6087 * @param Rank1_Channel This parameter can be one of the following values:
6088 * @arg @ref LL_ADC_CHANNEL_0 (3)
6089 * @arg @ref LL_ADC_CHANNEL_1 (3)
6090 * @arg @ref LL_ADC_CHANNEL_2 (3)
6091 * @arg @ref LL_ADC_CHANNEL_3 (3)
6092 * @arg @ref LL_ADC_CHANNEL_4 (3)
6093 * @arg @ref LL_ADC_CHANNEL_5 (3)
6094 * @arg @ref LL_ADC_CHANNEL_6
6095 * @arg @ref LL_ADC_CHANNEL_7
6096 * @arg @ref LL_ADC_CHANNEL_8
6097 * @arg @ref LL_ADC_CHANNEL_9
6098 * @arg @ref LL_ADC_CHANNEL_10
6099 * @arg @ref LL_ADC_CHANNEL_11
6100 * @arg @ref LL_ADC_CHANNEL_12
6101 * @arg @ref LL_ADC_CHANNEL_13
6102 * @arg @ref LL_ADC_CHANNEL_14
6103 * @arg @ref LL_ADC_CHANNEL_15
6104 * @arg @ref LL_ADC_CHANNEL_16
6105 * @arg @ref LL_ADC_CHANNEL_17
6106 * @arg @ref LL_ADC_CHANNEL_18
6107 * @arg @ref LL_ADC_CHANNEL_19
6108 * @arg @ref LL_ADC_CHANNEL_VREFINT
6109 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6110 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6111 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6112 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6113 *
6114 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6115 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6116 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6117 * Other channels are slow channels (conversion rate: refer to reference manual).
6118 * @param Rank2_Channel This parameter can be one of the following values:
6119 * @arg @ref LL_ADC_CHANNEL_0 (3)
6120 * @arg @ref LL_ADC_CHANNEL_1 (3)
6121 * @arg @ref LL_ADC_CHANNEL_2 (3)
6122 * @arg @ref LL_ADC_CHANNEL_3 (3)
6123 * @arg @ref LL_ADC_CHANNEL_4 (3)
6124 * @arg @ref LL_ADC_CHANNEL_5 (3)
6125 * @arg @ref LL_ADC_CHANNEL_6
6126 * @arg @ref LL_ADC_CHANNEL_7
6127 * @arg @ref LL_ADC_CHANNEL_8
6128 * @arg @ref LL_ADC_CHANNEL_9
6129 * @arg @ref LL_ADC_CHANNEL_10
6130 * @arg @ref LL_ADC_CHANNEL_11
6131 * @arg @ref LL_ADC_CHANNEL_12
6132 * @arg @ref LL_ADC_CHANNEL_13
6133 * @arg @ref LL_ADC_CHANNEL_14
6134 * @arg @ref LL_ADC_CHANNEL_15
6135 * @arg @ref LL_ADC_CHANNEL_16
6136 * @arg @ref LL_ADC_CHANNEL_17
6137 * @arg @ref LL_ADC_CHANNEL_18
6138 * @arg @ref LL_ADC_CHANNEL_19
6139 * @arg @ref LL_ADC_CHANNEL_VREFINT
6140 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6141 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6142 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6143 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6144 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
6145 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
6146 *
6147 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6148 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6149 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6150 * Other channels are slow channels (conversion rate: refer to reference manual).
6151 * @param Rank3_Channel This parameter can be one of the following values:
6152 * @arg @ref LL_ADC_CHANNEL_0 (3)
6153 * @arg @ref LL_ADC_CHANNEL_1 (3)
6154 * @arg @ref LL_ADC_CHANNEL_2 (3)
6155 * @arg @ref LL_ADC_CHANNEL_3 (3)
6156 * @arg @ref LL_ADC_CHANNEL_4 (3)
6157 * @arg @ref LL_ADC_CHANNEL_5 (3)
6158 * @arg @ref LL_ADC_CHANNEL_6
6159 * @arg @ref LL_ADC_CHANNEL_7
6160 * @arg @ref LL_ADC_CHANNEL_8
6161 * @arg @ref LL_ADC_CHANNEL_9
6162 * @arg @ref LL_ADC_CHANNEL_10
6163 * @arg @ref LL_ADC_CHANNEL_11
6164 * @arg @ref LL_ADC_CHANNEL_12
6165 * @arg @ref LL_ADC_CHANNEL_13
6166 * @arg @ref LL_ADC_CHANNEL_14
6167 * @arg @ref LL_ADC_CHANNEL_15
6168 * @arg @ref LL_ADC_CHANNEL_16
6169 * @arg @ref LL_ADC_CHANNEL_17
6170 * @arg @ref LL_ADC_CHANNEL_18
6171 * @arg @ref LL_ADC_CHANNEL_19
6172 * @arg @ref LL_ADC_CHANNEL_VREFINT
6173 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6174 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6175 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6176 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6177 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
6178 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
6179 *
6180 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6181 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6182 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6183 * Other channels are slow channels (conversion rate: refer to reference manual).
6184 * @param Rank4_Channel This parameter can be one of the following values:
6185 * @arg @ref LL_ADC_CHANNEL_0 (3)
6186 * @arg @ref LL_ADC_CHANNEL_1 (3)
6187 * @arg @ref LL_ADC_CHANNEL_2 (3)
6188 * @arg @ref LL_ADC_CHANNEL_3 (3)
6189 * @arg @ref LL_ADC_CHANNEL_4 (3)
6190 * @arg @ref LL_ADC_CHANNEL_5 (3)
6191 * @arg @ref LL_ADC_CHANNEL_6
6192 * @arg @ref LL_ADC_CHANNEL_7
6193 * @arg @ref LL_ADC_CHANNEL_8
6194 * @arg @ref LL_ADC_CHANNEL_9
6195 * @arg @ref LL_ADC_CHANNEL_10
6196 * @arg @ref LL_ADC_CHANNEL_11
6197 * @arg @ref LL_ADC_CHANNEL_12
6198 * @arg @ref LL_ADC_CHANNEL_13
6199 * @arg @ref LL_ADC_CHANNEL_14
6200 * @arg @ref LL_ADC_CHANNEL_15
6201 * @arg @ref LL_ADC_CHANNEL_16
6202 * @arg @ref LL_ADC_CHANNEL_17
6203 * @arg @ref LL_ADC_CHANNEL_18
6204 * @arg @ref LL_ADC_CHANNEL_19
6205 * @arg @ref LL_ADC_CHANNEL_VREFINT
6206 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6207 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6208 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6209 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6210 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
6211 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
6212 *
6213 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6214 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6215 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6216 * Other channels are slow channels (conversion rate: refer to reference manual).
6217 * @retval None
6218 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)6219 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
6220 uint32_t TriggerSource,
6221 uint32_t ExternalTriggerEdge,
6222 uint32_t SequencerNbRanks,
6223 uint32_t Rank1_Channel,
6224 uint32_t Rank2_Channel,
6225 uint32_t Rank3_Channel,
6226 uint32_t Rank4_Channel)
6227 {
6228 /* Set bits with content of parameter "Rankx_Channel" with bits position */
6229 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
6230 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
6231 /* because containing other bits reserved for other purpose. */
6232 /* If parameter "TriggerSource" is set to SW start, then parameter */
6233 /* "ExternalTriggerEdge" is discarded. */
6234 /* "TriggerSource" is define dwith default edge (rising): */
6235 /* So we need to discard the default edge else the edge will not as expected*/
6236 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
6237 MODIFY_REG(ADCx->JSQR,
6238 ADC_JSQR_JEXTSEL |
6239 ADC_JSQR_JEXTEN |
6240 ADC_JSQR_JSQ4 |
6241 ADC_JSQR_JSQ3 |
6242 ADC_JSQR_JSQ2 |
6243 ADC_JSQR_JSQ1 |
6244 ADC_JSQR_JL,
6245 (TriggerSource & ADC_JSQR_JEXTSEL) |
6246 (ExternalTriggerEdge * (is_trigger_not_sw)) |
6247 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
6248 << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6249 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
6250 << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6251 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
6252 << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6253 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
6254 << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
6255 SequencerNbRanks
6256 );
6257 }
6258
6259 /**
6260 * @}
6261 */
6262
6263 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
6264 * @{
6265 */
6266
6267 /**
6268 * @brief Set sampling time of the selected ADC channel
6269 * Unit: ADC clock cycles.
6270 * @note On this device, sampling time is on channel scope: independently
6271 * of channel mapped on ADC group regular or injected.
6272 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
6273 * converted:
6274 * sampling time constraints must be respected (sampling time can be
6275 * adjusted in function of ADC clock frequency and sampling time
6276 * setting).
6277 * Refer to device datasheet for timings values (parameters TS_vrefint,
6278 * TS_temp, ...).
6279 * @note Conversion time is the addition of sampling time and processing time.
6280 * On this STM32 series, ADC processing time is:
6281 * - 12.5 ADC clock cycles at ADC resolution 12 bits
6282 * - 10.5 ADC clock cycles at ADC resolution 10 bits
6283 * - 8.5 ADC clock cycles at ADC resolution 8 bits
6284 * - 6.5 ADC clock cycles at ADC resolution 6 bits
6285 * @note In case of ADC conversion of internal channel (VrefInt,
6286 * temperature sensor, ...), a sampling time minimum value
6287 * is required.
6288 * Refer to device datasheet.
6289 * @note On this STM32 series, setting of this feature is conditioned to
6290 * ADC state:
6291 * ADC must be disabled or enabled without conversion on going
6292 * on either groups regular or injected.
6293 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime
6294 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime
6295 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime
6296 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime
6297 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime
6298 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime
6299 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime
6300 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime
6301 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime
6302 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime
6303 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime
6304 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime
6305 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime
6306 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime
6307 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime
6308 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime
6309 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime
6310 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime
6311 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
6312 * @param ADCx ADC instance
6313 * @param Channel This parameter can be one of the following values:
6314 * @arg @ref LL_ADC_CHANNEL_0 (3)
6315 * @arg @ref LL_ADC_CHANNEL_1 (3)
6316 * @arg @ref LL_ADC_CHANNEL_2 (3)
6317 * @arg @ref LL_ADC_CHANNEL_3 (3)
6318 * @arg @ref LL_ADC_CHANNEL_4 (3)
6319 * @arg @ref LL_ADC_CHANNEL_5 (3)
6320 * @arg @ref LL_ADC_CHANNEL_6
6321 * @arg @ref LL_ADC_CHANNEL_7
6322 * @arg @ref LL_ADC_CHANNEL_8
6323 * @arg @ref LL_ADC_CHANNEL_9
6324 * @arg @ref LL_ADC_CHANNEL_10
6325 * @arg @ref LL_ADC_CHANNEL_11
6326 * @arg @ref LL_ADC_CHANNEL_12
6327 * @arg @ref LL_ADC_CHANNEL_13
6328 * @arg @ref LL_ADC_CHANNEL_14
6329 * @arg @ref LL_ADC_CHANNEL_15
6330 * @arg @ref LL_ADC_CHANNEL_16
6331 * @arg @ref LL_ADC_CHANNEL_17
6332 * @arg @ref LL_ADC_CHANNEL_18
6333 * @arg @ref LL_ADC_CHANNEL_19
6334 * @arg @ref LL_ADC_CHANNEL_VREFINT
6335 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6336 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6337 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6338 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6339 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
6340 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
6341 *
6342 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6343 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6344 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6345 * Other channels are slow channels (conversion rate: refer to reference manual).
6346 * @param SamplingTime This parameter can be one of the following values, In case of ADC1 instance:
6347 * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES (1)
6348 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES (1)
6349 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES (1)
6350 * @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES (1)
6351 * @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES (1)
6352 * @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES (1)
6353 * @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES (1)
6354 * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES (1)
6355 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 (2)
6356 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 (2)
6357 *
6358 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6359 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6360 * @retval None
6361 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)6362 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
6363 {
6364 if (ADCx != ADC4) /* ADC1 or ADC2 */
6365 {
6366 /* Set bits with content of parameter "SamplingTime" with bits position */
6367 /* in register and register position depending on parameter "Channel". */
6368 /* Parameter "Channel" is used with masks because containing */
6369 /* other bits reserved for other purpose. */
6370 uint32_t shift_value = ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) - (10UL * ((Channel \
6371 & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
6372 >> ADC_SMPRX_REGOFFSET_POS))) * 3UL);
6373 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
6374 >> ADC_SMPRX_REGOFFSET_POS));
6375
6376 MODIFY_REG(*preg, ADC_SMPR1_SMP0 << shift_value, SamplingTime << shift_value);
6377
6378 }
6379 else
6380 {
6381 /* Parameter "Channel" is used with masks because containing */
6382 /* other bits reserved for other purpose. It needs to be converted to decimal */
6383 /* to select the bit position */
6384 MODIFY_REG(ADCx->SMPR1,
6385 ((Channel & ADC_CHANNEL_ID_BITFIELD_MASK) << ADC4_SMPR_SMPSEL0_BITOFFSET_POS),
6386 ((Channel & ADC_CHANNEL_ID_BITFIELD_MASK) << ADC4_SMPR_SMPSEL0_BITOFFSET_POS)
6387 & (SamplingTime & ADC4_SAMPLING_TIME_CH_MASK)
6388 );
6389 }
6390 }
6391
6392 /**
6393 * @brief Get sampling time of the selected ADC channel
6394 * Unit: ADC clock cycles.
6395 * @note On this device, sampling time is on channel scope: independently
6396 * of channel mapped on ADC group regular or injected.
6397 * @note Conversion time is the addition of sampling time and processing time.
6398 * On this STM32 series, ADC processing time is:
6399 * - 12.5 ADC clock cycles at ADC resolution 12 bits
6400 * - 10.5 ADC clock cycles at ADC resolution 10 bits
6401 * - 8.5 ADC clock cycles at ADC resolution 8 bits
6402 * - 6.5 ADC clock cycles at ADC resolution 6 bits
6403 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime
6404 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime
6405 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime
6406 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime
6407 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime
6408 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime
6409 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime
6410 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime
6411 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime
6412 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime
6413 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime
6414 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime
6415 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime
6416 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime
6417 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime
6418 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime
6419 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime
6420 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime
6421 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
6422 * @param ADCx ADC instance
6423 * @param Channel This parameter can be one of the following values:
6424 * @arg @ref LL_ADC_CHANNEL_0 (3)
6425 * @arg @ref LL_ADC_CHANNEL_1 (3)
6426 * @arg @ref LL_ADC_CHANNEL_2 (3)
6427 * @arg @ref LL_ADC_CHANNEL_3 (3)
6428 * @arg @ref LL_ADC_CHANNEL_4 (3)
6429 * @arg @ref LL_ADC_CHANNEL_5 (3)
6430 * @arg @ref LL_ADC_CHANNEL_6
6431 * @arg @ref LL_ADC_CHANNEL_7
6432 * @arg @ref LL_ADC_CHANNEL_8
6433 * @arg @ref LL_ADC_CHANNEL_9
6434 * @arg @ref LL_ADC_CHANNEL_10
6435 * @arg @ref LL_ADC_CHANNEL_11
6436 * @arg @ref LL_ADC_CHANNEL_12
6437 * @arg @ref LL_ADC_CHANNEL_13
6438 * @arg @ref LL_ADC_CHANNEL_14
6439 * @arg @ref LL_ADC_CHANNEL_15
6440 * @arg @ref LL_ADC_CHANNEL_16
6441 * @arg @ref LL_ADC_CHANNEL_17
6442 * @arg @ref LL_ADC_CHANNEL_18
6443 * @arg @ref LL_ADC_CHANNEL_19
6444 * @arg @ref LL_ADC_CHANNEL_VREFINT
6445 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
6446 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
6447 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
6448 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
6449 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
6450 * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
6451 *
6452 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6453 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6454 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
6455 * Other channels are slow channels (conversion rate: refer to reference manual).
6456 * @retval In case of ADC1 insatnace, Returned value can be one of the following values:
6457 * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES (1)
6458 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES (1)
6459 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES (1)
6460 * @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES (1)
6461 * @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES (1)
6462 * @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES (1)
6463 * @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES (1)
6464 * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES (1)
6465 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 (2)
6466 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 (2)
6467 *
6468 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6469 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6470 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)6471 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
6472 {
6473 if (ADCx != ADC4) /* (ADCx == ADC1) || (ADCx == ADC2) */
6474 {
6475 uint32_t shift_value = ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) - (10UL * ((Channel \
6476 & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
6477 >> ADC_SMPRX_REGOFFSET_POS))) * 3UL);
6478 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
6479 >> ADC_SMPRX_REGOFFSET_POS));
6480
6481 return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << shift_value) >> shift_value);
6482 }
6483 else /* ADCx == ADC4 */
6484 {
6485 uint32_t smpr = READ_REG(ADCx->SMPR1);
6486
6487 /* Retrieve sampling time bit corresponding to the selected channel */
6488 /* and shift it to position 0. */
6489 uint32_t smp_channel_posbit0 = ((smpr & ADC4_SAMPLING_TIME_CH_MASK)
6490 >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) \
6491 >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
6492 + ADC4_SMPR_SMPSEL0_BITOFFSET_POS)
6493 & 0x1FUL));
6494
6495 /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
6496 return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
6497 | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
6498 }
6499 }
6500
6501 /**
6502 * @brief Set mode single-ended or differential input of the selected
6503 * ADC channel.
6504 * @note Channel ending is on channel scope: independently of channel mapped
6505 * on ADC group regular or injected.
6506 * In differential mode: Differential measurement is carried out
6507 * between the selected channel 'i' (positive input) and
6508 * channel 'i+1' (negative input). Only channel 'i' has to be
6509 * configured, channel 'i+1' is configured automatically.
6510 * @note Refer to Reference Manual to ensure the selected channel is
6511 * available in differential mode.
6512 * For example, internal channels (VrefInt, TempSensor, ...) are
6513 * not available in differential mode.
6514 * @note When configuring a channel 'i' in differential mode,
6515 * the channel 'i+1' is not usable separately.
6516 * @note On STM32U5, some channels are internally fixed to single-ended inputs
6517 * configuration:
6518 * - ADC1: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
6519 * - ADC2: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
6520 * - ADC4: None
6521 * @note For ADC channels configured in differential mode, both inputs
6522 * should be biased at (Vref+)/2 +/-200mV.
6523 * (Vref+ is the analog voltage reference)
6524 * @note On this STM32 series, setting of this feature is conditioned to
6525 * ADC state:
6526 * ADC must be ADC disabled.
6527 * @note One or several values can be selected.
6528 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
6529 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
6530 * @param ADCx ADC instance
6531 * @param Channel This parameter can be one of the following values:
6532 * @arg @ref LL_ADC_CHANNEL_1
6533 * @arg @ref LL_ADC_CHANNEL_2
6534 * @arg @ref LL_ADC_CHANNEL_3
6535 * @arg @ref LL_ADC_CHANNEL_4
6536 * @arg @ref LL_ADC_CHANNEL_5
6537 * @arg @ref LL_ADC_CHANNEL_10
6538 * @arg @ref LL_ADC_CHANNEL_11
6539 * @arg @ref LL_ADC_CHANNEL_12
6540 * @arg @ref LL_ADC_CHANNEL_13
6541 * @arg @ref LL_ADC_CHANNEL_14
6542 * @arg @ref LL_ADC_CHANNEL_15
6543 * @arg @ref LL_ADC_CHANNEL_16
6544 * @arg @ref LL_ADC_CHANNEL_17
6545 * @arg @ref LL_ADC_CHANNEL_18
6546 * @arg @ref LL_ADC_CHANNEL_19
6547 * @param SingleDiff This parameter can be a combination of the following values:
6548 * @arg @ref LL_ADC_SINGLE_ENDED
6549 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6550 * @retval None
6551 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)6552 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
6553 {
6554 /* Bits of channels in single or differential mode are set only for */
6555 /* differential mode (for single mode, mask of bits allowed to be set is */
6556 /* shifted out of range of bits of channels in single or differential mode. */
6557 MODIFY_REG(ADCx->DIFSEL,
6558 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
6559 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff \
6560 & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
6561 }
6562
6563 /**
6564 * @brief Get mode single-ended or differential input of the selected
6565 * ADC channel.
6566 * @note When configuring a channel 'i' in differential mode,
6567 * the channel 'i+1' is not usable separately.
6568 * Therefore, to ensure a channel is configured in single-ended mode,
6569 * the configuration of channel itself and the channel 'i-1' must be
6570 * read back (to ensure that the selected channel channel has not been
6571 * configured in differential mode by the previous channel).
6572 * @note Refer to Reference Manual to ensure the selected channel is
6573 * available in differential mode.
6574 * For example, internal channels (VrefInt, TempSensor, ...) are
6575 * not available in differential mode.
6576 * @note When configuring a channel 'i' in differential mode,
6577 * the channel 'i+1' is not usable separately.
6578 * @note On STM32U5, some channels are internally fixed to single-ended inputs
6579 * configuration:
6580 * - ADC1: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
6581 * - ADC2: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
6582 * - ADC4: None
6583 * @note One or several values can be selected. In this case, the value
6584 * returned is null if all channels are in single ended-mode.
6585 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
6586 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
6587 * @param ADCx ADC instance
6588 * @param Channel This parameter can be a combination of the following values:
6589 * @arg @ref LL_ADC_CHANNEL_1
6590 * @arg @ref LL_ADC_CHANNEL_2
6591 * @arg @ref LL_ADC_CHANNEL_3
6592 * @arg @ref LL_ADC_CHANNEL_4
6593 * @arg @ref LL_ADC_CHANNEL_5
6594 * @arg @ref LL_ADC_CHANNEL_10
6595 * @arg @ref LL_ADC_CHANNEL_11
6596 * @arg @ref LL_ADC_CHANNEL_12
6597 * @arg @ref LL_ADC_CHANNEL_13
6598 * @arg @ref LL_ADC_CHANNEL_14
6599 * @arg @ref LL_ADC_CHANNEL_15
6600 * @arg @ref LL_ADC_CHANNEL_16
6601 * @arg @ref LL_ADC_CHANNEL_17
6602 * @arg @ref LL_ADC_CHANNEL_18
6603 * @arg @ref LL_ADC_CHANNEL_19
6604 * @retval 0: channel in single-ended mode, else: channel in differential mode
6605 */
LL_ADC_GetChannelSingleDiff(const ADC_TypeDef * ADCx,uint32_t Channel)6606 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
6607 {
6608 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
6609 }
6610
6611 /**
6612 * @}
6613 */
6614
6615 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
6616 * @{
6617 */
6618
6619 /**
6620 * @brief Set ADC analog watchdog monitored channels:
6621 * a single channel, multiple channels or all channels,
6622 * on ADC groups regular and-or injected.
6623 * @note Once monitored channels are selected, analog watchdog
6624 * is enabled.
6625 * @note In case of need to define a single channel to monitor
6626 * with analog watchdog from sequencer channel definition,
6627 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
6628 * @note On this STM32 series, there are 2 kinds of analog watchdog
6629 * instance:
6630 * - AWD standard (instance AWD1):
6631 * - channels monitored: can monitor 1 channel or all channels.
6632 * - groups monitored: ADC groups regular and-or injected.
6633 * - resolution: resolution is not limited (corresponds to
6634 * ADC resolution configured).
6635 * - AWD flexible (instances AWD2, AWD3):
6636 * - channels monitored: flexible on channels monitored, selection is
6637 * channel wise, from from 1 to all channels.
6638 * Specificity of this analog watchdog: Multiple channels can
6639 * be selected. For example:
6640 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6641 * - groups monitored: not selection possible (monitoring on both
6642 * groups regular and injected).
6643 * Channels selected are monitored on groups regular and injected:
6644 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6645 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6646 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6647 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6648 * the 2 LSB are ignored.
6649 * @note On this STM32 series, setting of this feature is conditioned to
6650 * ADC state:
6651 * ADC must be disabled or enabled without conversion on going
6652 * on either groups regular or injected.
6653 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels
6654 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels
6655 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels
6656 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels
6657 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels
6658 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
6659 * @param ADCx ADC instance
6660 * @param AWDy This parameter can be one of the following values:
6661 * @arg @ref LL_ADC_AWD1
6662 * @arg @ref LL_ADC_AWD2
6663 * @arg @ref LL_ADC_AWD3
6664 * @param AWDChannelGroup This parameter can be one of the following values:
6665 * @arg @ref LL_ADC_AWD_DISABLE
6666 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
6667 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
6668 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
6669 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
6670 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
6671 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
6672 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
6673 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
6674 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
6675 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
6676 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
6677 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
6678 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
6679 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
6680 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
6681 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
6682 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
6683 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
6684 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
6685 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
6686 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
6687 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
6688 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
6689 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
6690 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
6691 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
6692 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
6693 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
6694 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
6695 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
6696 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
6697 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
6698 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
6699 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
6700 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
6701 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
6702 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
6703 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
6704 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
6705 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
6706 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
6707 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
6708 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
6709 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
6710 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
6711 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
6712 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
6713 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
6714 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
6715 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
6716 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
6717 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
6718 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
6719 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
6720 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
6721 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
6722 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
6723 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
6724 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
6725 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
6726 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
6727 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
6728 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
6729 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
6730 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
6731 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
6732 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
6733 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
6734 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
6735 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
6736 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
6737 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
6738 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC4_REG (0)(2)
6739 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC4_REG (0)(2)
6740 *
6741 * (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
6742 * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2.
6743 * (2) On STM32U5, parameter available only on ADC instance: ADC4.
6744 * @retval None
6745 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)6746 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
6747 {
6748 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
6749 /* in register and register position depending on parameter "AWDy". */
6750 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
6751 /* containing other bits reserved for other purpose. */
6752
6753 __IO uint32_t *preg;
6754 uint32_t channel_monitored;
6755
6756 if (AWDy == LL_ADC_AWD1)
6757 {
6758 /* Set pointer to register of selected analog watchdog */
6759 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
6760
6761 /* Compute channel monitored as number */
6762 channel_monitored = (AWDChannelGroup & ADC_AWD_CR1_CHANNEL_MASK);
6763 }
6764 else
6765 {
6766 /* Set pointer to register of selected analog watchdog */
6767 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CR3_REGOFFSET)) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL));
6768
6769 /* Compute channel monitored as bitfield */
6770 channel_monitored = (1UL << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) \
6771 >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
6772 /* Case of all channels monitored */
6773 channel_monitored |= ((1UL - ((AWDChannelGroup & ADC_CFGR1_AWD1SGL) >> ADC_CFGR1_AWD1SGL_Pos)) * 0x00FFFFFFUL);
6774 /* Case of no channel monitored */
6775 channel_monitored *= ((((AWDChannelGroup & (ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)) == 0UL) ? 0UL : 1UL));
6776 }
6777
6778 MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), channel_monitored);
6779 }
6780
6781 /**
6782 * @brief Get ADC analog watchdog monitored channel.
6783 * @note Usage of the returned channel number:
6784 * - To reinject this channel into another function LL_ADC_xxx:
6785 * the returned channel number is only partly formatted on definition
6786 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
6787 * with parts of literals LL_ADC_CHANNEL_x or using
6788 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
6789 * Then the selected literal LL_ADC_CHANNEL_x can be used
6790 * as parameter for another function.
6791 * - To get the channel number in decimal format:
6792 * process the returned value with the helper macro
6793 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
6794 * Applicable only when the analog watchdog is set to monitor
6795 * one channel.
6796 * @note On this STM32 series, there are 2 kinds of analog watchdog
6797 * instance:
6798 * - AWD standard (instance AWD1):
6799 * - channels monitored: can monitor 1 channel or all channels.
6800 * - groups monitored: ADC groups regular and-or injected.
6801 * - resolution: resolution is not limited (corresponds to
6802 * ADC resolution configured).
6803 * - AWD flexible (instances AWD2, AWD3):
6804 * - channels monitored: flexible on channels monitored, selection is
6805 * channel wise, from from 1 to all channels.
6806 * Specificity of this analog watchdog: Multiple channels can
6807 * be selected. For example:
6808 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6809 * - groups monitored: not selection possible (monitoring on both
6810 * groups regular and injected).
6811 * Channels selected are monitored on groups regular and injected:
6812 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6813 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6814 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6815 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6816 * the 2 LSB are ignored.
6817 * @note On this STM32 series, setting of this feature is conditioned to
6818 * ADC state:
6819 * ADC must be disabled or enabled without conversion on going
6820 * on either groups regular or injected.
6821 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels
6822 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels
6823 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels
6824 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels
6825 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels
6826 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
6827 * @param ADCx ADC instance
6828 * @param AWDy This parameter can be one of the following values:
6829 * @arg @ref LL_ADC_AWD1
6830 * @arg @ref LL_ADC_AWD2 (1)
6831 * @arg @ref LL_ADC_AWD3 (1)
6832 *
6833 * (1) On this AWD number, monitored channel can be retrieved
6834 * if only 1 channel is programmed (or none or all channels).
6835 * This function cannot retrieve monitored channel if
6836 * multiple channels are programmed simultaneously
6837 * by bitfield.
6838 * @retval Returned value can be one of the following values:
6839 * @arg @ref LL_ADC_AWD_DISABLE
6840 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
6841 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
6842 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
6843 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
6844 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
6845 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
6846 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
6847 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
6848 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
6849 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
6850 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
6851 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
6852 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
6853 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
6854 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
6855 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
6856 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
6857 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
6858 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
6859 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
6860 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
6861 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
6862 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
6863 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
6864 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
6865 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
6866 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
6867 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
6868 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
6869 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
6870 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
6871 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
6872 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
6873 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
6874 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
6875 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
6876 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
6877 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
6878 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
6879 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
6880 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
6881 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
6882 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
6883 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
6884 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
6885 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
6886 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
6887 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
6888 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
6889 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
6890 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
6891 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
6892 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
6893 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
6894 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
6895 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
6896 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
6897 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
6898 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
6899 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
6900 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
6901 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
6902 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
6903 *
6904 * (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
6905 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)6906 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
6907 {
6908 const __IO uint32_t *preg;
6909
6910 if (AWDy == LL_ADC_AWD1)
6911 {
6912 /* Set pointer to register of selected analog watchdog */
6913 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
6914 }
6915 else
6916 {
6917 /* Set pointer to register of selected analog watchdog */
6918 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) \
6919 >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL));
6920 }
6921
6922 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
6923
6924 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
6925 /* (parameter value LL_ADC_AWD_DISABLE). */
6926 /* Else, the selected AWD is enabled and is monitoring a group of channels */
6927 /* or a single channel. */
6928 if (analog_wd_monit_channels != 0UL)
6929 {
6930 if (AWDy == LL_ADC_AWD1)
6931 {
6932 if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
6933 {
6934 /* AWD monitoring a group of channels */
6935 analog_wd_monit_channels = ((analog_wd_monit_channels | (0x000FFFFFUL)) & (~(ADC_CFGR1_AWD1CH)));
6936 }
6937 else
6938 {
6939 /* AWD monitoring a single channel */
6940 analog_wd_monit_channels = analog_wd_monit_channels;
6941 }
6942 }
6943 else
6944 {
6945 if (ADCx != ADC4)
6946 {
6947 if ((analog_wd_monit_channels & 0x000FFFFFUL) == 0x000FFFFFUL)
6948 {
6949 /* AWD monitoring a group of channels */
6950 analog_wd_monit_channels = (0x000FFFFFUL | ((ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)));
6951 }
6952 else
6953 {
6954 /* AWD monitoring a single channel */
6955 /* AWD monitoring a group of channels */
6956 analog_wd_monit_channels = ((ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
6957 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) \
6958 << ADC_CFGR1_AWD1CH_Pos));
6959 }
6960 }
6961 else
6962 {
6963 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
6964 {
6965 /* AWD monitoring a group of channels */
6966 analog_wd_monit_channels = (0x000FFFFFUL | (ADC_CFGR1_AWD1EN));
6967 }
6968 else
6969 {
6970 /* AWD monitoring a single channel */
6971 /* AWD monitoring a group of channels */
6972 analog_wd_monit_channels = ((ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
6973 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) \
6974 << ADC_CFGR1_AWD1CH_Pos));
6975 }
6976 }
6977 }
6978 }
6979
6980 return analog_wd_monit_channels;
6981 }
6982
6983 /**
6984 * @brief Set ADC analog watchdog threshold value of threshold
6985 * high or low.
6986 * @note In case of ADC resolution different of 12 bits,
6987 * analog watchdog thresholds data require a specific shift.
6988 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
6989 * @note On this STM32 series, there are 2 kinds of analog watchdog
6990 * instance:
6991 * - AWD standard (instance AWD1):
6992 * - channels monitored: can monitor 1 channel or all channels.
6993 * - groups monitored: ADC groups regular and-or injected.
6994 * - resolution: resolution is not limited (corresponds to
6995 * ADC resolution configured).
6996 * - AWD flexible (instances AWD2, AWD3):
6997 * - channels monitored: flexible on channels monitored, selection is
6998 * channel wise, from from 1 to all channels.
6999 * Specificity of this analog watchdog: Multiple channels can
7000 * be selected. For example:
7001 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
7002 * - groups monitored: not selection possible (monitoring on both
7003 * groups regular and injected).
7004 * Channels selected are monitored on groups regular and injected:
7005 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
7006 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
7007 * - resolution: resolution is limited to 8 bits: if ADC resolution is
7008 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
7009 * the 2 LSB are ignored.
7010 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
7011 * impacted: the comparison of analog watchdog thresholds is done
7012 * on oversampling intermediate computation (after ratio, before shift
7013 * application): intermediate register bitfield [32:7]
7014 * (26 most significant bits).
7015 * @note On this STM32 series, setting of this feature is conditioned to
7016 * ADC state:
7017 * ADC must be disabled or enabled without conversion on going
7018 * on either ADC groups regular or injected.
7019 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds
7020 * TR2 HT2 LL_ADC_SetAnalogWDThresholds
7021 * TR3 HT3 LL_ADC_SetAnalogWDThresholds
7022 * TR1 LT1 LL_ADC_SetAnalogWDThresholds
7023 * TR2 LT2 LL_ADC_SetAnalogWDThresholds
7024 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
7025 * @param ADCx ADC instance
7026 * @param AWDy This parameter can be one of the following values:
7027 * @arg @ref LL_ADC_AWD1
7028 * @arg @ref LL_ADC_AWD2
7029 * @arg @ref LL_ADC_AWD3
7030 * @param AWDThresholdsHighLow This parameter can be one of the following values:
7031 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
7032 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
7033 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
7034 * @retval None
7035 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)7036 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
7037 uint32_t AWDThresholdValue)
7038 {
7039 __IO uint32_t *preg;
7040 /* Set bits with content of parameter "AWDThresholdValue" with bits */
7041 /* position in register and register position depending on parameters */
7042 /* "AWDThresholdsHighLow" and "AWDy". */
7043 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
7044 /* containing other bits reserved for other purpose. */
7045 if (ADCx != ADC4) /* ADCx == ADC1 or ADCx == ADC2 */
7046 {
7047 if (AWDy == LL_ADC_AWD1)
7048 {
7049 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (AWDThresholdsHighLow));
7050 }
7051 else
7052 {
7053 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
7054 >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
7055 + (AWDThresholdsHighLow));
7056 }
7057
7058 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
7059 }
7060 else /* ADCx == ADC4 */
7061 {
7062 if (AWDy == LL_ADC_AWD1)
7063 {
7064 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
7065 }
7066 else
7067 {
7068 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS))\
7069 + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
7070 }
7071
7072 MODIFY_REG(*preg,
7073 ADC_AWD1TR_LT1 << (AWDThresholdsHighLow * ADC_AWD1TR_HT1_Pos),
7074 AWDThresholdValue << (((AWDThresholdsHighLow << ADC_AWD1TR_HT1_Pos) & ADC_AWD_TRX_BIT_HIGH_MASK) \
7075 >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
7076
7077 }
7078 }
7079
7080 /**
7081 * @brief Get ADC analog watchdog threshold value of threshold high,
7082 * threshold low or raw data with ADC thresholds high and low
7083 * concatenated.
7084 * @note In case of ADC resolution different of 12 bits,
7085 * analog watchdog thresholds data require a specific shift.
7086 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
7087 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds
7088 * TR2 HT2 LL_ADC_GetAnalogWDThresholds
7089 * TR3 HT3 LL_ADC_GetAnalogWDThresholds
7090 * TR1 LT1 LL_ADC_GetAnalogWDThresholds
7091 * TR2 LT2 LL_ADC_GetAnalogWDThresholds
7092 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
7093 * @param ADCx ADC instance
7094 * @param AWDy This parameter can be one of the following values:
7095 * @arg @ref LL_ADC_AWD1
7096 * @arg @ref LL_ADC_AWD2
7097 * @arg @ref LL_ADC_AWD3
7098 * @param AWDThresholdsHighLow This parameter can be one of the following values:
7099 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
7100 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
7101 * @retval In case of ADC1 instance, Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
7102 * @retval In case of ADC1 instance, Value between Min_Data=0x000 and Max_Data=0xFFF
7103 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)7104 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy,
7105 uint32_t AWDThresholdsHighLow)
7106 {
7107 const __IO uint32_t *preg;
7108 if (ADCx != ADC4) /* ADCx == ADC1 or ADCx == ADC2 */
7109 {
7110 if (AWDy == LL_ADC_AWD1)
7111 {
7112 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (AWDThresholdsHighLow));
7113 }
7114 else
7115 {
7116 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
7117 + (AWDThresholdsHighLow));
7118 }
7119
7120 return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
7121 }
7122 else /* ADCx == ADC4 */
7123 {
7124 if (AWDy == LL_ADC_AWD1)
7125 {
7126 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
7127
7128 }
7129 else
7130 {
7131 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS))\
7132 + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
7133 }
7134
7135 return (uint32_t)(READ_BIT(*preg,
7136 (ADC_AWD1TR_LT1 << (AWDThresholdsHighLow * ADC_AWD1TR_HT1_Pos)))
7137 >> (((AWDThresholdsHighLow << ADC_AWD1TR_HT1_Pos) & ADC_AWD_TRX_BIT_HIGH_MASK) \
7138 >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
7139 );
7140 }
7141 }
7142
7143 /**
7144 * @brief Set ADC analog watchdog thresholds value of both thresholds
7145 * high and low.
7146 * @note If value of only one threshold high or low must be set,
7147 * use function @ref LL_ADC_SetAnalogWDThresholds().
7148 * @note In case of ADC resolution different of 12 bits,
7149 * analog watchdog thresholds data require a specific shift.
7150 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
7151 * @note On this STM32 series, there are 2 kinds of analog watchdog
7152 * instance:
7153 * - AWD standard (instance AWD1):
7154 * - channels monitored: can monitor 1 channel or all channels.
7155 * - groups monitored: ADC group regular.
7156 * - resolution: resolution is not limited (corresponds to
7157 * ADC resolution configured).
7158 * - AWD flexible (instances AWD2, AWD3):
7159 * - channels monitored: flexible on channels monitored, selection is
7160 * channel wise, from from 1 to all channels.
7161 * Specificity of this analog watchdog: Multiple channels can
7162 * be selected. For example:
7163 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
7164 * - groups monitored: not selection possible (monitoring on both
7165 * groups regular and injected).
7166 * Channels selected are monitored on groups regular and injected:
7167 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
7168 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
7169 * - resolution: resolution is not limited (corresponds to
7170 * ADC resolution configured).
7171 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
7172 * impacted: the comparison of analog watchdog thresholds is done on
7173 * oversampling final computation (after ratio and shift application):
7174 * ADC data register bitfield [15:4] (12 most significant bits).
7175 * Examples:
7176 * - Oversampling ratio and shift selected to have ADC conversion data
7177 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
7178 * ADC analog watchdog thresholds must be divided by 16.
7179 * - Oversampling ratio and shift selected to have ADC conversion data
7180 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
7181 * ADC analog watchdog thresholds must be divided by 4.
7182 * - Oversampling ratio and shift selected to have ADC conversion data
7183 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
7184 * ADC analog watchdog thresholds match directly to ADC data register.
7185 * @note On this STM32 series, setting of this feature is conditioned to
7186 * ADC state:
7187 * ADC must be disabled or enabled without conversion on going
7188 * on group regular.
7189 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds
7190 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds
7191 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds
7192 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds
7193 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds
7194 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
7195 * @param ADCx ADC instance
7196 * @param AWDy This parameter can be one of the following values:
7197 * @arg @ref LL_ADC_AWD1
7198 * @arg @ref LL_ADC_AWD2
7199 * @arg @ref LL_ADC_AWD3
7200 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
7201 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
7202 * @retval None
7203 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)7204 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
7205 uint32_t AWDThresholdLowValue)
7206 {
7207 __IO uint32_t *preg;
7208 __IO uint32_t *preg2;
7209 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
7210 /* position in register and register position depending on parameter */
7211 /* "AWDy". */
7212 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
7213 /* containing other bits reserved for other purpose. */
7214 if (ADCx != ADC4) /* ADC1 or ADC2 */
7215 {
7216 if (AWDy == LL_ADC_AWD1)
7217 {
7218 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (LL_ADC_AWD_THRESHOLD_LOW));
7219 preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (LL_ADC_AWD_THRESHOLD_HIGH));
7220 }
7221 else
7222 {
7223 preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
7224 >> (ADC_AWD_TRX_REGOFFSET_POS - 1UL)))
7225 + (LL_ADC_AWD_THRESHOLD_LOW));
7226 preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
7227 >> (ADC_AWD_TRX_REGOFFSET_POS - 1UL)))
7228 + (LL_ADC_AWD_THRESHOLD_HIGH));
7229 }
7230
7231 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdLowValue);
7232 MODIFY_REG(*preg2, ADC_HTR_HT, AWDThresholdHighValue);
7233 }
7234 else
7235 {
7236 if (AWDy == LL_ADC_AWD1)
7237 {
7238 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
7239 }
7240 else
7241 {
7242 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS)) \
7243 + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
7244 }
7245
7246 MODIFY_REG(*preg,
7247 ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
7248 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
7249 }
7250 }
7251
7252 /**
7253 * @brief Set ADC analog watchdog filtering configuration
7254 * @note On this STM32 series, setting of this feature is conditioned to
7255 * ADC state:
7256 * ADC must be disabled or enabled without conversion on going
7257 * on either groups regular or injected.
7258 * @note On this STM32 series, this feature is only available on first
7259 * analog watchdog (AWD1)
7260 * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
7261 * @param ADCx ADC instance
7262 * @param AWDy This parameter can be one of the following values:
7263 * @arg @ref LL_ADC_AWD1
7264 * @param FilteringConfig This parameter can be one of the following values:
7265 * @arg @ref LL_ADC_AWD_FILTERING_NONE
7266 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
7267 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
7268 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
7269 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
7270 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
7271 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
7272 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
7273 * @retval None
7274 */
LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t FilteringConfig)7275 __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
7276 {
7277 /* Prevent unused argument(s) compilation warning */
7278 (void)(AWDy);
7279 MODIFY_REG(ADCx->HTR1, ADC_HTR_AWDFILT, FilteringConfig);
7280 }
7281
7282 /**
7283 * @brief Get ADC analog watchdog filtering configuration
7284 * @note On this STM32 series, this feature is only available on first
7285 * analog watchdog (AWD1)
7286 * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
7287 * @param ADCx ADC instance
7288 * @param AWDy This parameter can be one of the following values:
7289 * @arg @ref LL_ADC_AWD1
7290 * @retval Returned value can be:
7291 * @arg @ref LL_ADC_AWD_FILTERING_NONE
7292 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
7293 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
7294 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
7295 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
7296 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
7297 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
7298 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
7299 */
LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef * ADCx,uint32_t AWDy)7300 __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy)
7301 {
7302 /* Prevent unused argument(s) compilation warning */
7303 (void)(AWDy);
7304 return (uint32_t)(READ_BIT(ADCx->HTR1, ADC_HTR_AWDFILT));
7305 }
7306
7307 /**
7308 * @}
7309 */
7310
7311 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
7312 * @{
7313 */
7314
7315 /**
7316 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
7317 * (availability of ADC group injected depends on STM32 families).
7318 * @note If both groups regular and injected are selected,
7319 * specify behavior of ADC group injected interrupting
7320 * group regular: when ADC group injected is triggered,
7321 * the oversampling on ADC group regular is either
7322 * temporary stopped and continued, or resumed from start
7323 * (oversampler buffer reset).
7324 * @note On this STM32 series, setting of this feature is conditioned to
7325 * ADC state:
7326 * ADC must be disabled or enabled without conversion on going
7327 * on either groups regular or injected.
7328 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope
7329 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope
7330 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
7331 * @param ADCx ADC instance
7332 * @param OvsScope This parameter can be one of the following values:
7333 * @arg @ref LL_ADC_OVS_DISABLE
7334 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
7335 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
7336 * @arg @ref LL_ADC_OVS_GRP_INJECTED
7337 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
7338 * @retval None
7339 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)7340 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
7341 {
7342 if (ADCx != ADC4)
7343 {
7344 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
7345 }
7346 else
7347 {
7348 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE, OvsScope);
7349 }
7350 }
7351
7352 /**
7353 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
7354 * (availability of ADC group injected depends on STM32 families).
7355 * @note If both groups regular and injected are selected,
7356 * specify behavior of ADC group injected interrupting
7357 * group regular: when ADC group injected is triggered,
7358 * the oversampling on ADC group regular is either
7359 * temporary stopped and continued, or resumed from start
7360 * (oversampler buffer reset).
7361 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope
7362 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope
7363 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
7364 * @param ADCx ADC instance
7365 * @retval Returned value can be one of the following values:
7366 * @arg @ref LL_ADC_OVS_DISABLE
7367 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
7368 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
7369 * @arg @ref LL_ADC_OVS_GRP_INJECTED
7370 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
7371 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)7372 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
7373 {
7374 if (ADCx != ADC4)
7375 {
7376 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
7377 }
7378 else
7379 {
7380 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE));
7381 }
7382 }
7383
7384 /**
7385 * @brief Set ADC oversampling discontinuous mode (triggered mode)
7386 * on the selected ADC group.
7387 * @note Number of oversampled conversions are done either in:
7388 * - continuous mode (all conversions of oversampling ratio
7389 * are done from 1 trigger)
7390 * - discontinuous mode (each conversion of oversampling ratio
7391 * needs a trigger)
7392 * @note On this STM32 series, setting of this feature is conditioned to
7393 * ADC state:
7394 * ADC must be disabled or enabled without conversion on going
7395 * on group regular.
7396 * @note On this STM32 series, oversampling discontinuous mode
7397 * (triggered mode) can be used only when oversampling is
7398 * set on group regular only and in resumed mode.
7399 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
7400 * @param ADCx ADC instance
7401 * @param OverSamplingDiscont This parameter can be one of the following values:
7402 * @arg @ref LL_ADC_OVS_REG_CONT
7403 * @arg @ref LL_ADC_OVS_REG_DISCONT
7404 * @retval None
7405 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)7406 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
7407 {
7408 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
7409 }
7410
7411 /**
7412 * @brief Get ADC oversampling discontinuous mode (triggered mode)
7413 * on the selected ADC group.
7414 * @note Number of oversampled conversions are done either in:
7415 * - continuous mode (all conversions of oversampling ratio
7416 * are done from 1 trigger)
7417 * - discontinuous mode (each conversion of oversampling ratio
7418 * needs a trigger)
7419 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
7420 * @param ADCx ADC instance
7421 * @retval Returned value can be one of the following values:
7422 * @arg @ref LL_ADC_OVS_REG_CONT
7423 * @arg @ref LL_ADC_OVS_REG_DISCONT
7424 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)7425 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
7426 {
7427 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
7428 }
7429
7430 /**
7431 * @brief Set ADC oversampling
7432 * (impacting both ADC groups regular and injected)
7433 * @note This function set the 2 items of oversampling configuration:
7434 * - ratio
7435 * - shift
7436 * @note On this STM32 series, setting of this feature is conditioned to
7437 * ADC state:
7438 * ADC must be disabled or enabled without conversion on going
7439 * on either groups regular or injected.
7440 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift
7441 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
7442 * @param ADCx ADC instance
7443 * @param Ratio For ADC instance ADC1, ADC2: This parameter can be in the range from 1 to 1024.
7444 * For ADC instance ADC4: This parameter can be one of the following values:
7445 * @arg @ref LL_ADC_OVS_RATIO_2
7446 * @arg @ref LL_ADC_OVS_RATIO_4
7447 * @arg @ref LL_ADC_OVS_RATIO_8
7448 * @arg @ref LL_ADC_OVS_RATIO_16
7449 * @arg @ref LL_ADC_OVS_RATIO_32
7450 * @arg @ref LL_ADC_OVS_RATIO_64
7451 * @arg @ref LL_ADC_OVS_RATIO_128
7452 * @arg @ref LL_ADC_OVS_RATIO_256
7453 * @param Shift This parameter can be one of the following values:
7454 * @arg @ref LL_ADC_OVS_SHIFT_NONE
7455 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
7456 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
7457 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
7458 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
7459 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
7460 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
7461 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
7462 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
7463 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9 (1)
7464 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 (1)
7465 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 (1)
7466 *
7467 * (1): Only for ADC1 instance.
7468 * @retval None
7469 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)7470 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
7471 {
7472 if (ADCx != ADC4)
7473 {
7474 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
7475 }
7476 else /* ADCx == ADC4 */
7477 {
7478 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC4_CFGR2_OVSR),
7479 (Shift | (Ratio & ~ADC4_OVERSAMPLING_RATIO_PARAMETER_MASK)));
7480 }
7481 }
7482
7483 /**
7484 * @brief Get ADC oversampling ratio
7485 * (impacting both ADC groups regular and injected)
7486 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
7487 * @param ADCx ADC instance
7488 * @retval Ratio This parameter can be a value from 1 to 1024 in the case of ADC1/2,
7489 * In the case of ADC4 can be one of the following values:
7490 * @arg @ref LL_ADC_OVS_RATIO_2
7491 * @arg @ref LL_ADC_OVS_RATIO_4
7492 * @arg @ref LL_ADC_OVS_RATIO_8
7493 * @arg @ref LL_ADC_OVS_RATIO_16
7494 * @arg @ref LL_ADC_OVS_RATIO_32
7495 * @arg @ref LL_ADC_OVS_RATIO_64
7496 * @arg @ref LL_ADC_OVS_RATIO_128
7497 * @arg @ref LL_ADC_OVS_RATIO_256
7498 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)7499 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
7500 {
7501 if (ADCx != ADC4)
7502 {
7503 return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
7504 }
7505 else /* ADCx == ADC4 */
7506 {
7507 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_OVSR) | ADC4_OVERSAMPLING_RATIO_PARAMETER);
7508 }
7509 }
7510
7511 /**
7512 * @brief Get ADC oversampling shift
7513 * (impacting both ADC groups regular and injected)
7514 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
7515 * @param ADCx ADC instance
7516 * @retval Shift This parameter can be one of the following values:
7517 * @arg @ref LL_ADC_OVS_SHIFT_NONE
7518 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
7519 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
7520 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
7521 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
7522 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
7523 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
7524 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
7525 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
7526 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9 (1)
7527 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 (1)
7528 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 (1)
7529 *
7530 * (1): Only for ADC1 instance.
7531 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)7532 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
7533 {
7534 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
7535 }
7536
7537 #if defined(ADC_MULTIMODE_SUPPORT)
7538 /**
7539 * @brief Set ADC multimode configuration to operate in independent mode
7540 * or multimode (for devices with several ADC instances).
7541 * @note If multimode configuration: the selected ADC instance is
7542 * either master or slave depending on hardware.
7543 * Refer to reference manual.
7544 * @note On this STM32 series, setting of this feature is conditioned to
7545 * ADC state:
7546 * All ADC instances of the ADC common group must be disabled.
7547 * This check can be done with function @ref LL_ADC_IsEnabled() for each
7548 * ADC instance or by using helper macro
7549 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
7550 * @rmtoll CCR DUAL LL_ADC_SetMultimode
7551 * @param ADCxy_COMMON ADC common instance
7552 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7553 * @param Multimode This parameter can be one of the following values:
7554 * @arg @ref LL_ADC_MULTI_INDEPENDENT
7555 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
7556 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
7557 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
7558 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
7559 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
7560 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
7561 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
7562 * @retval None
7563 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)7564 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
7565 {
7566 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
7567 }
7568
7569 /**
7570 * @brief Get ADC multimode configuration to operate in independent mode
7571 * or multimode (for devices with several ADC instances).
7572 * @note If multimode configuration: the selected ADC instance is
7573 * either master or slave depending on hardware.
7574 * Refer to reference manual.
7575 * @rmtoll CCR DUAL LL_ADC_GetMultimode
7576 * @param ADCxy_COMMON ADC common instance
7577 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7578 * @retval Returned value can be one of the following values:
7579 * @arg @ref LL_ADC_MULTI_INDEPENDENT
7580 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
7581 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
7582 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
7583 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
7584 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
7585 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
7586 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
7587 */
LL_ADC_GetMultimode(const ADC_Common_TypeDef * ADCxy_COMMON)7588 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
7589 {
7590 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
7591 }
7592
7593 /**
7594 * @brief Set ADC multimode conversion data transfer: no transfer
7595 * or transfer by DMA.
7596 * @note If ADC multimode transfer by DMA is not selected:
7597 * each ADC uses its own DMA channel, with its individual
7598 * DMA transfer settings.
7599 * If ADC multimode transfer by DMA is selected:
7600 * One DMA channel is used for both ADC (DMA of ADC master)
7601 * Specifies the DMA requests mode:
7602 * - Limited mode (One shot mode): DMA transfer requests are stopped
7603 * when number of DMA data transfers (number of
7604 * ADC conversions) is reached.
7605 * This ADC mode is intended to be used with DMA mode non-circular.
7606 * - Unlimited mode: DMA transfer requests are unlimited,
7607 * whatever number of DMA data transfers (number of
7608 * ADC conversions).
7609 * This ADC mode is intended to be used with DMA mode circular.
7610 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
7611 * mode non-circular:
7612 * when DMA transfers size will be reached, DMA will stop transfers of
7613 * ADC conversions data ADC will raise an overrun error
7614 * (overrun flag and interruption if enabled).
7615 * @note How to retrieve multimode conversion data:
7616 * Whatever multimode transfer by DMA setting: using function
7617 * @ref LL_ADC_REG_ReadMultiConversionData32().
7618 * If ADC multimode transfer by DMA is selected: conversion data
7619 * is a raw data with ADC master and slave concatenated.
7620 * A macro is available to get the conversion data of
7621 * ADC master or ADC slave: see helper macro
7622 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
7623 * @note On this STM32 series, setting of this feature is conditioned to
7624 * ADC state:
7625 * All ADC instances of the ADC common group must be disabled
7626 * or enabled without conversion on going on group regular.
7627 * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
7628 * @param ADCxy_COMMON ADC common instance
7629 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7630 * @param MultiDMATransfer This parameter can be one of the following values:
7631 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
7632 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
7633 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
7634 * @retval None
7635 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)7636 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
7637 {
7638 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);
7639 }
7640
7641 /**
7642 * @brief Get ADC multimode conversion data transfer: no transfer
7643 * or transfer by DMA.
7644 * @note If ADC multimode transfer by DMA is not selected:
7645 * each ADC uses its own DMA channel, with its individual
7646 * DMA transfer settings.
7647 * If ADC multimode transfer by DMA is selected:
7648 * One DMA channel is used for both ADC (DMA of ADC master)
7649 * Specifies the DMA requests mode:
7650 * - Limited mode (One shot mode): DMA transfer requests are stopped
7651 * when number of DMA data transfers (number of
7652 * ADC conversions) is reached.
7653 * This ADC mode is intended to be used with DMA mode non-circular.
7654 * - Unlimited mode: DMA transfer requests are unlimited,
7655 * whatever number of DMA data transfers (number of
7656 * ADC conversions).
7657 * This ADC mode is intended to be used with DMA mode circular.
7658 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
7659 * mode non-circular:
7660 * when DMA transfers size will be reached, DMA will stop transfers of
7661 * ADC conversions data ADC will raise an overrun error
7662 * (overrun flag and interruption if enabled).
7663 * @note How to retrieve multimode conversion data:
7664 * Whatever multimode transfer by DMA setting: using function
7665 * @ref LL_ADC_REG_ReadMultiConversionData32().
7666 * If ADC multimode transfer by DMA is selected: conversion data
7667 * is a raw data with ADC master and slave concatenated.
7668 * A macro is available to get the conversion data of
7669 * ADC master or ADC slave: see helper macro
7670 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
7671 * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
7672 * @param ADCxy_COMMON ADC common instance
7673 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7674 * @retval Returned value can be one of the following values:
7675 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
7676 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
7677 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
7678 */
LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef * ADCxy_COMMON)7679 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
7680 {
7681 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
7682 }
7683
7684 /**
7685 * @brief Set ADC multimode delay between 2 sampling phases.
7686 * @note The sampling delay range depends on ADC resolution:
7687 * - ADC resolution 14 bits can have maximum delay of 16 cycles.
7688 * - ADC resolution 12 bits can have maximum delay of 16 cycles.
7689 * - ADC resolution 10 bits can have maximum delay of 15 cycles.
7690 * - ADC resolution 8 bits can have maximum delay of 13 cycles.
7691 * @note On this STM32 series, setting of this feature is conditioned to
7692 * ADC state:
7693 * All ADC instances of the ADC common group must be disabled.
7694 * This check can be done with function @ref LL_ADC_IsEnabled() for each
7695 * ADC instance or by using helper macro helper macro
7696 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
7697 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
7698 * @param ADCxy_COMMON ADC common instance
7699 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7700 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
7701 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
7702 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
7703 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
7704 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
7705 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
7706 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
7707 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
7708 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
7709 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
7710 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
7711 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
7712 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
7713 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
7714 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS
7715 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (1)
7716 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (1)
7717 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS
7718 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (2)
7719 *
7720 * (1) Parameter available only if ADC resolution is 14, 12 or 10 bits.
7721 * (2) Parameter available only if ADC resolution is 14 or 12 bits.
7722 * @retval None
7723 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)7724 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
7725 {
7726 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
7727 }
7728
7729 /**
7730 * @brief Get ADC multimode delay between 2 sampling phases.
7731 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
7732 * @param ADCxy_COMMON ADC common instance
7733 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7734 * @retval Returned value can be one of the following values:
7735 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
7736 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
7737 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
7738 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
7739 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
7740 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
7741 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
7742 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
7743 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
7744 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
7745 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
7746 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
7747 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
7748 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS
7749 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (1)
7750 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (1)
7751 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS
7752 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (2)
7753 *
7754 * (1) Parameter available only if ADC resolution is 14, 12 or 10 bits.
7755 * (2) Parameter available only if ADC resolution is 14 or 12 bits.
7756 */
LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef * ADCxy_COMMON)7757 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
7758 {
7759 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
7760 }
7761
7762 #endif /* ADC_MULTIMODE_SUPPORT */
7763
7764 /**
7765 * @}
7766 */
7767 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
7768 * @{
7769 */
7770
7771 /**
7772 * @brief Put ADC instance in deep power down state.
7773 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
7774 * state, the internal analog calibration is lost. After exiting from
7775 * deep power down, calibration must be relaunched or calibration factor
7776 * (preliminarily saved) must be set back into calibration register.
7777 * @note On this STM32 series, setting of this feature is conditioned to
7778 * ADC state:
7779 * ADC must be ADC disabled.
7780 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
7781 * @param ADCx ADC instance
7782 * @retval None
7783 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)7784 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
7785 {
7786 /* Note: Write register with some additional bits forced to state reset */
7787 /* instead of modifying only the selected bit for this function, */
7788 /* to not interfere with bits with HW property "rs". */
7789 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_DEEPPWD);
7790 }
7791
7792 /**
7793 * @brief Disable ADC deep power down mode.
7794 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
7795 * state, the internal analog calibration is lost. After exiting from
7796 * deep power down, calibration must be relaunched or calibration factor
7797 * (preliminarily saved) must be set back into calibration register.
7798 * @note On this STM32 series, setting of this feature is conditioned to
7799 * ADC state:
7800 * ADC must be ADC disabled.
7801 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
7802 * @param ADCx ADC instance
7803 * @retval None
7804 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)7805 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
7806 {
7807 /* Note: Write register with some additional bits forced to state reset */
7808 /* instead of modifying only the selected bit for this function, */
7809 /* to not interfere with bits with HW property "rs". */
7810 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
7811 }
7812
7813 /**
7814 * @brief Get the selected ADC instance deep power down state.
7815 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
7816 * @param ADCx ADC instance
7817 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
7818 */
LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef * ADCx)7819 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
7820 {
7821 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
7822 }
7823
7824 /**
7825 * @brief Enable ADC instance internal voltage regulator.
7826 * @note On this STM32 series, after ADC internal voltage regulator enable,
7827 * a delay for ADC internal voltage regulator stabilization
7828 * is required before performing a ADC calibration or ADC enable.
7829 * Refer to device datasheet, parameter tADCVREG_STUP.
7830 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
7831 * @note On this STM32 series, setting of this feature is conditioned to
7832 * ADC state:
7833 * ADC must be ADC disabled.
7834 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
7835 * @param ADCx ADC instance
7836 * @retval None
7837 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)7838 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
7839 {
7840 /* Note: Write register with some additional bits forced to state reset */
7841 /* instead of modifying only the selected bit for this function, */
7842 /* to not interfere with bits with HW property "rs". */
7843 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN);
7844 }
7845
7846 /**
7847 * @brief Disable ADC internal voltage regulator.
7848 * @note On this STM32 series, setting of this feature is conditioned to
7849 * ADC state:
7850 * ADC must be ADC disabled.
7851 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
7852 * @param ADCx ADC instance
7853 * @retval None
7854 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)7855 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
7856 {
7857 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
7858 }
7859
7860 /**
7861 * @brief Get the selected ADC instance internal voltage regulator state.
7862 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
7863 * @param ADCx ADC instance
7864 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
7865 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)7866 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
7867 {
7868 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
7869 }
7870
7871 /**
7872 * @brief Enable the selected ADC instance.
7873 * @note On this STM32 series, after ADC enable, a delay for
7874 * ADC internal analog stabilization is required before performing a
7875 * ADC conversion start.
7876 * Refer to device datasheet, parameter tSTAB.
7877 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7878 * is enabled and when conversion clock is active.
7879 * (not only core clock: this ADC has a dual clock domain)
7880 * @note On this STM32 series, setting of this feature is conditioned to
7881 * ADC state:
7882 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
7883 * @rmtoll CR ADEN LL_ADC_Enable
7884 * @param ADCx ADC instance
7885 * @retval None
7886 */
LL_ADC_Enable(ADC_TypeDef * ADCx)7887 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
7888 {
7889 /* Note: Write register with some additional bits forced to state reset */
7890 /* instead of modifying only the selected bit for this function, */
7891 /* to not interfere with bits with HW property "rs". */
7892 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN);
7893 }
7894
7895 /**
7896 * @brief Disable the selected ADC instance.
7897 * @note On this STM32 series, setting of this feature is conditioned to
7898 * ADC state:
7899 * ADC must be not disabled. Must be enabled without conversion on going
7900 * on either groups regular or injected.
7901 * @rmtoll CR ADDIS LL_ADC_Disable
7902 * @param ADCx ADC instance
7903 * @retval None
7904 */
LL_ADC_Disable(ADC_TypeDef * ADCx)7905 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
7906 {
7907 /* Note: Write register with some additional bits forced to state reset */
7908 /* instead of modifying only the selected bit for this function, */
7909 /* to not interfere with bits with HW property "rs". */
7910 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS);
7911 }
7912
7913 /**
7914 * @brief Get the selected ADC instance enable state.
7915 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7916 * is enabled and when conversion clock is active.
7917 * (not only core clock: this ADC has a dual clock domain)
7918 * @rmtoll CR ADEN LL_ADC_IsEnabled
7919 * @param ADCx ADC instance
7920 * @retval 0: ADC is disabled, 1: ADC is enabled.
7921 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)7922 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
7923 {
7924 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
7925 }
7926
7927 /**
7928 * @brief Get the selected ADC instance disable state.
7929 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
7930 * @param ADCx ADC instance
7931 * @retval 0: no ADC disable command on going.
7932 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)7933 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
7934 {
7935 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
7936 }
7937
7938 /**
7939 * @brief Start ADC calibration in the mode single-ended
7940 * or differential (for devices with differential mode available).
7941 * @note On this STM32 series, a minimum number of ADC clock cycles
7942 * are required between ADC end of calibration and ADC enable.
7943 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
7944 * @note Calibration duration:
7945 * - Calibration of offset: 520 ADC clock cycles
7946 * - Calibration of linearity: 131072 ADC clock cycles
7947 * @note For devices with differential mode available:
7948 * Calibration of offset is specific to each of
7949 * single-ended and differential modes
7950 * (calibration run must be performed for each of these
7951 * differential modes, if used afterwards and if the application
7952 * requires their calibration).
7953 * Calibration of linearity is common to both
7954 * single-ended and differential modes
7955 * (calibration run can be performed only once).
7956 * @note On this STM32 series, setting of this feature is conditioned to
7957 * ADC state:
7958 * ADC must be ADC disabled.
7959 * @rmtoll CR ADCAL LL_ADC_StartCalibration
7960 * CR ADCALDIF LL_ADC_StartCalibration
7961 * CR ADCALLIN LL_ADC_StartCalibration
7962 * @param ADCx ADC instance
7963 * @param CalibrationMode This parameter can be one of the following values:
7964 * @arg @ref LL_ADC_CALIB_OFFSET
7965 * @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY
7966 * @retval None
7967 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t CalibrationMode)7968 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode)
7969 {
7970 /* Note: Write register with some additional bits forced to state reset */
7971 /* instead of modifying only the selected bit for this function, */
7972 /* to not interfere with bits with HW property "rs". */
7973 if (ADCx != ADC4) /* ADC1 or ADC2 */
7974 {
7975 MODIFY_REG(ADCx->CR,
7976 ADC_CR_ADCALLIN | ADC_CR_BITS_PROPERTY_RS,
7977 ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK));
7978 }
7979 else
7980 {
7981 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCAL);
7982 }
7983 }
7984
7985 /**
7986 * @brief Get ADC calibration state.
7987 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
7988 * @param ADCx ADC instance
7989 * @retval 0: calibration complete, 1: calibration in progress.
7990 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)7991 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
7992 {
7993 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
7994 }
7995
7996 /**
7997 * @}
7998 */
7999
8000 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
8001 * @{
8002 */
8003
8004 /**
8005 * @brief Start ADC group regular conversion.
8006 * @note On this STM32 series, this function is relevant for both
8007 * internal trigger (SW start) and external trigger:
8008 * - If ADC trigger has been set to software start, ADC conversion
8009 * starts immediately.
8010 * - If ADC trigger has been set to external trigger, ADC conversion
8011 * will start at next trigger event (on the selected trigger edge)
8012 * following the ADC start conversion command.
8013 * @note On this STM32 series, setting of this feature is conditioned to
8014 * ADC state:
8015 * ADC must be enabled without conversion on going on group regular,
8016 * without conversion stop command on going on group regular,
8017 * without ADC disable command on going.
8018 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
8019 * @param ADCx ADC instance
8020 * @retval None
8021 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)8022 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
8023 {
8024 /* Note: Write register with some additional bits forced to state reset */
8025 /* instead of modifying only the selected bit for this function, */
8026 /* to not interfere with bits with HW property "rs". */
8027 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART);
8028 }
8029
8030 /**
8031 * @brief Stop ADC group regular conversion.
8032 * @note On this STM32 series, setting of this feature is conditioned to
8033 * ADC state:
8034 * ADC must be enabled with conversion on going on group regular,
8035 * without ADC disable command on going.
8036 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
8037 * @param ADCx ADC instance
8038 * @retval None
8039 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)8040 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
8041 {
8042 /* Note: Write register with some additional bits forced to state reset */
8043 /* instead of modifying only the selected bit for this function, */
8044 /* to not interfere with bits with HW property "rs". */
8045 MODIFY_REG(ADCx->CR,
8046 ADC_CR_BITS_PROPERTY_RS,
8047 ADC_CR_ADSTP);
8048 }
8049
8050 /**
8051 * @brief Get ADC group regular conversion state.
8052 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
8053 * @param ADCx ADC instance
8054 * @retval 0: no conversion is on going on ADC group regular.
8055 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)8056 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
8057 {
8058 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8059 }
8060
8061 /**
8062 * @brief Get ADC group regular command of conversion stop state
8063 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
8064 * @param ADCx ADC instance
8065 * @retval 0: no command of conversion stop is on going on ADC group regular.
8066 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)8067 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
8068 {
8069 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
8070 }
8071
8072 /**
8073 * @brief Get ADC group regular conversion data, range fit for
8074 * all ADC configurations: all ADC resolutions and
8075 * all oversampling increased data width (for devices
8076 * with feature oversampling).
8077 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
8078 * @param ADCx ADC instance
8079 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
8080 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)8081 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
8082 {
8083 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8084 }
8085
8086 /**
8087 * @brief Get ADC group regular conversion data, range fit for
8088 * ADC resolution 16 bits.
8089 * @note For devices with feature oversampling: Oversampling
8090 * can increase data width, function for extended range
8091 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
8092 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData16
8093 * @param ADCx ADC instance
8094 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
8095 */
LL_ADC_REG_ReadConversionData16(const ADC_TypeDef * ADCx)8096 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(const ADC_TypeDef *ADCx)
8097 {
8098 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8099 }
8100
8101 /**
8102 * @brief Get ADC group regular conversion data, range fit for
8103 * ADC resolution 14 bits.
8104 * @note For devices with feature oversampling: Oversampling
8105 * can increase data width, function for extended range
8106 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
8107 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData14
8108 * @param ADCx ADC instance
8109 * @retval Value between Min_Data=0x00 and Max_Data=0x3FF
8110 */
LL_ADC_REG_ReadConversionData14(const ADC_TypeDef * ADCx)8111 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(const ADC_TypeDef *ADCx)
8112 {
8113 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8114 }
8115
8116 /**
8117 * @brief Get ADC group regular conversion data, range fit for
8118 * ADC resolution 12 bits.
8119 * @note For devices with feature oversampling: Oversampling
8120 * can increase data width, function for extended range
8121 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
8122 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
8123 * @param ADCx ADC instance
8124 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
8125 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)8126 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
8127 {
8128 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8129 }
8130
8131 /**
8132 * @brief Get ADC group regular conversion data, range fit for
8133 * ADC resolution 10 bits.
8134 * @note For devices with feature oversampling: Oversampling
8135 * can increase data width, function for extended range
8136 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
8137 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
8138 * @param ADCx ADC instance
8139 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
8140 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)8141 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
8142 {
8143 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8144 }
8145
8146 /**
8147 * @brief Get ADC group regular conversion data, range fit for
8148 * ADC resolution 8 bits.
8149 * @note For devices with feature oversampling: Oversampling
8150 * can increase data width, function for extended range
8151 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
8152 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
8153 * @param ADCx ADC instance
8154 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
8155 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)8156 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
8157 {
8158 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
8159 }
8160
8161 #if defined(ADC_MULTIMODE_SUPPORT)
8162 /**
8163 * @brief Get ADC multimode conversion data of ADC master, ADC slave
8164 * or raw data with ADC master and slave concatenated.
8165 * @note If raw data with ADC master and slave concatenated is retrieved,
8166 * a macro is available to get the conversion data of
8167 * ADC master or ADC slave: see helper macro
8168 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
8169 * (however this macro is mainly intended for multimode
8170 * transfer by DMA, because this function can do the same
8171 * by getting multimode conversion data of ADC master or ADC slave
8172 * separately).
8173 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32
8174 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
8175 * @param ADCxy_COMMON ADC common instance
8176 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8177 * @param ConversionData This parameter can be one of the following values:
8178 * @arg @ref LL_ADC_MULTI_MASTER
8179 * @arg @ref LL_ADC_MULTI_SLAVE
8180 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
8181 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
8182 */
LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)8183 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON,
8184 uint32_t ConversionData)
8185 {
8186 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) >> (POSITION_VAL(ConversionData) & 0x1FUL));
8187 }
8188 #endif /* ADC_MULTIMODE_SUPPORT */
8189 /**
8190 * @}
8191 */
8192
8193 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
8194 * @{
8195 */
8196
8197 /**
8198 * @brief Start ADC group injected conversion.
8199 * @note On this STM32 series, this function is relevant for both
8200 * internal trigger (SW start) and external trigger:
8201 * - If ADC trigger has been set to software start, ADC conversion
8202 * starts immediately.
8203 * - If ADC trigger has been set to external trigger, ADC conversion
8204 * will start at next trigger event (on the selected trigger edge)
8205 * following the ADC start conversion command.
8206 * @note On this STM32 series, setting of this feature is conditioned to
8207 * ADC state:
8208 * ADC must be enabled without conversion on going on group injected,
8209 * without conversion stop command on going on group injected,
8210 * without ADC disable command on going.
8211 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
8212 * @param ADCx ADC instance
8213 * @retval None
8214 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)8215 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
8216 {
8217 /* Note: Write register with some additional bits forced to state reset */
8218 /* instead of modifying only the selected bit for this function, */
8219 /* to not interfere with bits with HW property "rs". */
8220 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTART);
8221 }
8222
8223 /**
8224 * @brief Stop ADC group injected conversion.
8225 * @note On this STM32 series, setting of this feature is conditioned to
8226 * ADC state:
8227 * ADC must be enabled with conversion on going on group injected,
8228 * without ADC disable command on going.
8229 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
8230 * @param ADCx ADC instance
8231 * @retval None
8232 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)8233 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
8234 {
8235 /* Note: Write register with some additional bits forced to state reset */
8236 /* instead of modifying only the selected bit for this function, */
8237 /* to not interfere with bits with HW property "rs". */
8238 MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTP);
8239 }
8240
8241 /**
8242 * @brief Get ADC group injected conversion state.
8243 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
8244 * @param ADCx ADC instance
8245 * @retval 0: no conversion is on going on ADC group injected.
8246 */
LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef * ADCx)8247 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
8248 {
8249 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
8250 }
8251
8252 /**
8253 * @brief Get ADC group injected command of conversion stop state
8254 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
8255 * @param ADCx ADC instance
8256 * @retval 0: no command of conversion stop is on going on ADC group injected.
8257 */
LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef * ADCx)8258 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
8259 {
8260 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
8261 }
8262
8263 /**
8264 * @brief Get ADC group regular conversion data, range fit for
8265 * all ADC configurations: all ADC resolutions and
8266 * all oversampling increased data width (for devices
8267 * with feature oversampling).
8268 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32
8269 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32
8270 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32
8271 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
8272 * @param ADCx ADC instance
8273 * @param Rank This parameter can be one of the following values:
8274 * @arg @ref LL_ADC_INJ_RANK_1
8275 * @arg @ref LL_ADC_INJ_RANK_2
8276 * @arg @ref LL_ADC_INJ_RANK_3
8277 * @arg @ref LL_ADC_INJ_RANK_4
8278 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
8279 */
LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef * ADCx,uint32_t Rank)8280 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
8281 {
8282 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8283 >> ADC_JDRX_REGOFFSET_POS));
8284
8285 return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8286 }
8287
8288 /**
8289 * @brief Get ADC group injected conversion data, range fit for
8290 * ADC resolution 16 bits.
8291 * @note For devices with feature oversampling: Oversampling
8292 * can increase data width, function for extended range
8293 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8294 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16
8295 * JDR2 JDATA LL_ADC_INJ_ReadConversionData16
8296 * JDR3 JDATA LL_ADC_INJ_ReadConversionData16
8297 * JDR4 JDATA LL_ADC_INJ_ReadConversionData16
8298 * @param ADCx ADC instance
8299 * @param Rank This parameter can be one of the following values:
8300 * @arg @ref LL_ADC_INJ_RANK_1
8301 * @arg @ref LL_ADC_INJ_RANK_2
8302 * @arg @ref LL_ADC_INJ_RANK_3
8303 * @arg @ref LL_ADC_INJ_RANK_4
8304 * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF
8305 */
LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef * ADCx,uint32_t Rank)8306 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef *ADCx, uint32_t Rank)
8307 {
8308 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8309 >> ADC_JDRX_REGOFFSET_POS));
8310
8311 return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8312 }
8313
8314 /**
8315 * @brief Get ADC group injected conversion data, range fit for
8316 * ADC resolution 14 bits.
8317 * @note For devices with feature oversampling: Oversampling
8318 * can increase data width, function for extended range
8319 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8320 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14
8321 * JDR2 JDATA LL_ADC_INJ_ReadConversionData14
8322 * JDR3 JDATA LL_ADC_INJ_ReadConversionData14
8323 * JDR4 JDATA LL_ADC_INJ_ReadConversionData14
8324 * @param ADCx ADC instance
8325 * @param Rank This parameter can be one of the following values:
8326 * @arg @ref LL_ADC_INJ_RANK_1
8327 * @arg @ref LL_ADC_INJ_RANK_2
8328 * @arg @ref LL_ADC_INJ_RANK_3
8329 * @arg @ref LL_ADC_INJ_RANK_4
8330 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF
8331 */
LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef * ADCx,uint32_t Rank)8332 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef *ADCx, uint32_t Rank)
8333 {
8334 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8335 >> ADC_JDRX_REGOFFSET_POS));
8336
8337 return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8338 }
8339
8340 /**
8341 * @brief Get ADC group injected conversion data, range fit for
8342 * ADC resolution 12 bits.
8343 * @note For devices with feature oversampling: Oversampling
8344 * can increase data width, function for extended range
8345 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8346 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12
8347 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12
8348 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12
8349 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
8350 * @param ADCx ADC instance
8351 * @param Rank This parameter can be one of the following values:
8352 * @arg @ref LL_ADC_INJ_RANK_1
8353 * @arg @ref LL_ADC_INJ_RANK_2
8354 * @arg @ref LL_ADC_INJ_RANK_3
8355 * @arg @ref LL_ADC_INJ_RANK_4
8356 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
8357 */
LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef * ADCx,uint32_t Rank)8358 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
8359 {
8360 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8361 >> ADC_JDRX_REGOFFSET_POS));
8362
8363 return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8364 }
8365
8366 /**
8367 * @brief Get ADC group injected conversion data, range fit for
8368 * ADC resolution 10 bits.
8369 * @note For devices with feature oversampling: Oversampling
8370 * can increase data width, function for extended range
8371 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8372 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10
8373 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10
8374 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10
8375 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
8376 * @param ADCx ADC instance
8377 * @param Rank This parameter can be one of the following values:
8378 * @arg @ref LL_ADC_INJ_RANK_1
8379 * @arg @ref LL_ADC_INJ_RANK_2
8380 * @arg @ref LL_ADC_INJ_RANK_3
8381 * @arg @ref LL_ADC_INJ_RANK_4
8382 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
8383 */
LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef * ADCx,uint32_t Rank)8384 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
8385 {
8386 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8387 >> ADC_JDRX_REGOFFSET_POS));
8388
8389 return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8390 }
8391
8392 /**
8393 * @brief Get ADC group injected conversion data, range fit for
8394 * ADC resolution 8 bits.
8395 * @note For devices with feature oversampling: Oversampling
8396 * can increase data width, function for extended range
8397 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
8398 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8
8399 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8
8400 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8
8401 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
8402 * @param ADCx ADC instance
8403 * @param Rank This parameter can be one of the following values:
8404 * @arg @ref LL_ADC_INJ_RANK_1
8405 * @arg @ref LL_ADC_INJ_RANK_2
8406 * @arg @ref LL_ADC_INJ_RANK_3
8407 * @arg @ref LL_ADC_INJ_RANK_4
8408 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
8409 */
LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef * ADCx,uint32_t Rank)8410 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
8411 {
8412 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
8413 >> ADC_JDRX_REGOFFSET_POS));
8414
8415 return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
8416 }
8417
8418 /**
8419 * @}
8420 */
8421
8422 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
8423 * @{
8424 */
8425
8426 /**
8427 * @brief Get flag ADC ready.
8428 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
8429 * is enabled and when conversion clock is active.
8430 * (not only core clock: this ADC has a dual clock domain)
8431 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
8432 * @param ADCx ADC instance
8433 * @retval State of bit (1 or 0).
8434 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)8435 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
8436 {
8437 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
8438 }
8439
8440 /**
8441 * @brief Get flag ADC group regular end of unitary conversion.
8442 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
8443 * @param ADCx ADC instance
8444 * @retval State of bit (1 or 0).
8445 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)8446 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
8447 {
8448 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
8449 }
8450
8451 /**
8452 * @brief Get flag ADC group regular end of sequence conversions.
8453 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
8454 * @param ADCx ADC instance
8455 * @retval State of bit (1 or 0).
8456 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)8457 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
8458 {
8459 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
8460 }
8461
8462 /**
8463 * @brief Get flag ADC group regular overrun.
8464 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
8465 * @param ADCx ADC instance
8466 * @retval State of bit (1 or 0).
8467 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)8468 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
8469 {
8470 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
8471 }
8472
8473 /**
8474 * @brief Get flag ADC group regular end of sampling phase.
8475 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
8476 * @param ADCx ADC instance
8477 * @retval State of bit (1 or 0).
8478 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)8479 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
8480 {
8481 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
8482 }
8483
8484 /**
8485 * @brief Get flag ADC group injected end of unitary conversion.
8486 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
8487 * @param ADCx ADC instance
8488 * @retval State of bit (1 or 0).
8489 */
LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef * ADCx)8490 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
8491 {
8492 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
8493 }
8494
8495 /**
8496 * @brief Get flag ADC group injected end of sequence conversions.
8497 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
8498 * @param ADCx ADC instance
8499 * @retval State of bit (1 or 0).
8500 */
LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef * ADCx)8501 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
8502 {
8503 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
8504 }
8505
8506 /**
8507 * @brief Get flag ADC analog watchdog 1 flag
8508 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
8509 * @param ADCx ADC instance
8510 * @retval State of bit (1 or 0).
8511 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)8512 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
8513 {
8514 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
8515 }
8516
8517 /**
8518 * @brief Get flag ADC analog watchdog 2.
8519 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
8520 * @param ADCx ADC instance
8521 * @retval State of bit (1 or 0).
8522 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)8523 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
8524 {
8525 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
8526 }
8527
8528 /**
8529 * @brief Get flag ADC analog watchdog 3.
8530 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
8531 * @param ADCx ADC instance
8532 * @retval State of bit (1 or 0).
8533 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)8534 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
8535 {
8536 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
8537 }
8538
8539 /**
8540 * @brief Clear flag ADC ready.
8541 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
8542 * is enabled and when conversion clock is active.
8543 * (not only core clock: this ADC has a dual clock domain)
8544 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
8545 * @param ADCx ADC instance
8546 * @retval None
8547 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)8548 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
8549 {
8550 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
8551 }
8552
8553 /**
8554 * @brief Clear flag ADC group regular end of unitary conversion.
8555 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
8556 * @param ADCx ADC instance
8557 * @retval None
8558 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)8559 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
8560 {
8561 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
8562 }
8563
8564 /**
8565 * @brief Clear flag ADC group regular end of sequence conversions.
8566 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
8567 * @param ADCx ADC instance
8568 * @retval None
8569 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)8570 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
8571 {
8572 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
8573 }
8574
8575 /**
8576 * @brief Clear flag ADC group regular overrun.
8577 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
8578 * @param ADCx ADC instance
8579 * @retval None
8580 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)8581 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
8582 {
8583 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
8584 }
8585
8586 /**
8587 * @brief Clear flag ADC group regular end of sampling phase.
8588 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
8589 * @param ADCx ADC instance
8590 * @retval None
8591 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)8592 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
8593 {
8594 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
8595 }
8596
8597 /**
8598 * @brief Clear flag ADC group injected end of unitary conversion.
8599 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
8600 * @param ADCx ADC instance
8601 * @retval None
8602 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)8603 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
8604 {
8605 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
8606 }
8607
8608 /**
8609 * @brief Clear flag ADC group injected end of sequence conversions.
8610 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
8611 * @param ADCx ADC instance
8612 * @retval None
8613 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)8614 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
8615 {
8616 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
8617 }
8618
8619 /**
8620 * @brief Clear flag ADC analog watchdog 1.
8621 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
8622 * @param ADCx ADC instance
8623 * @retval None
8624 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)8625 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
8626 {
8627 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
8628 }
8629
8630 /**
8631 * @brief Clear flag ADC analog watchdog 2.
8632 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
8633 * @param ADCx ADC instance
8634 * @retval None
8635 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)8636 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
8637 {
8638 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
8639 }
8640
8641 /**
8642 * @brief Clear flag ADC analog watchdog 3.
8643 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
8644 * @param ADCx ADC instance
8645 * @retval None
8646 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)8647 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
8648 {
8649 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
8650 }
8651
8652
8653 /**
8654 * @}
8655 */
8656
8657 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
8658 * @{
8659 */
8660
8661 /**
8662 * @brief Enable ADC ready.
8663 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
8664 * @param ADCx ADC instance
8665 * @retval None
8666 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)8667 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
8668 {
8669 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8670 }
8671
8672 /**
8673 * @brief Enable interruption ADC group regular end of unitary conversion.
8674 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
8675 * @param ADCx ADC instance
8676 * @retval None
8677 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)8678 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
8679 {
8680 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
8681 }
8682
8683 /**
8684 * @brief Enable interruption ADC group regular end of sequence conversions.
8685 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
8686 * @param ADCx ADC instance
8687 * @retval None
8688 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)8689 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
8690 {
8691 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
8692 }
8693
8694 /**
8695 * @brief Enable ADC group regular interruption overrun.
8696 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
8697 * @param ADCx ADC instance
8698 * @retval None
8699 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)8700 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
8701 {
8702 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
8703 }
8704
8705 /**
8706 * @brief Enable interruption ADC group regular end of sampling.
8707 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
8708 * @param ADCx ADC instance
8709 * @retval None
8710 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)8711 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
8712 {
8713 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8714 }
8715
8716 /**
8717 * @brief Enable interruption ADC group injected end of unitary conversion.
8718 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
8719 * @param ADCx ADC instance
8720 * @retval None
8721 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)8722 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
8723 {
8724 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8725 }
8726
8727 /**
8728 * @brief Enable interruption ADC group injected end of sequence conversions.
8729 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
8730 * @param ADCx ADC instance
8731 * @retval None
8732 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)8733 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
8734 {
8735 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8736 }
8737
8738 /**
8739 * @brief Enable interruption ADC analog watchdog 1.
8740 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
8741 * @param ADCx ADC instance
8742 * @retval None
8743 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)8744 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
8745 {
8746 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8747 }
8748
8749 /**
8750 * @brief Enable interruption ADC analog watchdog 2.
8751 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
8752 * @param ADCx ADC instance
8753 * @retval None
8754 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)8755 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
8756 {
8757 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8758 }
8759
8760 /**
8761 * @brief Enable interruption ADC analog watchdog 3.
8762 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
8763 * @param ADCx ADC instance
8764 * @retval None
8765 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)8766 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
8767 {
8768 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8769 }
8770
8771 /**
8772 * @brief Enable interruption ADC end of calibration.
8773 * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
8774 * @param ADCx ADC instance
8775 * @retval None
8776 */
LL_ADC_EnableIT_EOCAL(ADC_TypeDef * ADCx)8777 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
8778 {
8779 SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
8780 }
8781
8782 /**
8783 * @brief Disable interruption ADC ready.
8784 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
8785 * @param ADCx ADC instance
8786 * @retval None
8787 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)8788 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
8789 {
8790 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
8791 }
8792
8793 /**
8794 * @brief Disable interruption ADC group regular end of unitary conversion.
8795 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
8796 * @param ADCx ADC instance
8797 * @retval None
8798 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)8799 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
8800 {
8801 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
8802 }
8803
8804 /**
8805 * @brief Disable interruption ADC group regular end of sequence conversions.
8806 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
8807 * @param ADCx ADC instance
8808 * @retval None
8809 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)8810 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
8811 {
8812 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
8813 }
8814
8815 /**
8816 * @brief Disable interruption ADC group regular overrun.
8817 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
8818 * @param ADCx ADC instance
8819 * @retval None
8820 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)8821 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
8822 {
8823 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
8824 }
8825
8826 /**
8827 * @brief Disable interruption ADC group regular end of sampling.
8828 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
8829 * @param ADCx ADC instance
8830 * @retval None
8831 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)8832 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
8833 {
8834 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
8835 }
8836
8837 /**
8838 * @brief Disable interruption ADC group regular end of unitary conversion.
8839 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
8840 * @param ADCx ADC instance
8841 * @retval None
8842 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)8843 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
8844 {
8845 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8846 }
8847
8848 /**
8849 * @brief Disable interruption ADC group injected end of sequence conversions.
8850 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
8851 * @param ADCx ADC instance
8852 * @retval None
8853 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)8854 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
8855 {
8856 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8857 }
8858
8859 /**
8860 * @brief Disable interruption ADC analog watchdog 1.
8861 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
8862 * @param ADCx ADC instance
8863 * @retval None
8864 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)8865 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
8866 {
8867 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8868 }
8869
8870 /**
8871 * @brief Disable interruption ADC analog watchdog 2.
8872 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
8873 * @param ADCx ADC instance
8874 * @retval None
8875 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)8876 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
8877 {
8878 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8879 }
8880
8881 /**
8882 * @brief Disable interruption ADC analog watchdog 3.
8883 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
8884 * @param ADCx ADC instance
8885 * @retval None
8886 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)8887 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
8888 {
8889 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8890 }
8891
8892 /**
8893 * @brief Disable interruption ADC end of calibration.
8894 * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
8895 * @param ADCx ADC instance
8896 * @retval None
8897 */
LL_ADC_DisableIT_EOCAL(ADC_TypeDef * ADCx)8898 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
8899 {
8900 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
8901 }
8902
8903 /**
8904 * @brief Get state of interruption ADC ready
8905 * (0: interrupt disabled, 1: interrupt enabled).
8906 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
8907 * @param ADCx ADC instance
8908 * @retval State of bit (1 or 0).
8909 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)8910 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
8911 {
8912 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
8913 }
8914
8915 /**
8916 * @brief Get state of interruption ADC group regular end of unitary conversion
8917 * (0: interrupt disabled, 1: interrupt enabled).
8918 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
8919 * @param ADCx ADC instance
8920 * @retval State of bit (1 or 0).
8921 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)8922 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
8923 {
8924 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
8925 }
8926
8927 /**
8928 * @brief Get state of interruption ADC group regular end of sequence conversions
8929 * (0: interrupt disabled, 1: interrupt enabled).
8930 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
8931 * @param ADCx ADC instance
8932 * @retval State of bit (1 or 0).
8933 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)8934 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
8935 {
8936 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
8937 }
8938
8939 /**
8940 * @brief Get state of interruption ADC group regular overrun
8941 * (0: interrupt disabled, 1: interrupt enabled).
8942 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
8943 * @param ADCx ADC instance
8944 * @retval State of bit (1 or 0).
8945 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)8946 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
8947 {
8948 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
8949 }
8950
8951 /**
8952 * @brief Get state of interruption ADC group regular end of sampling
8953 * (0: interrupt disabled, 1: interrupt enabled).
8954 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
8955 * @param ADCx ADC instance
8956 * @retval State of bit (1 or 0).
8957 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)8958 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
8959 {
8960 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
8961 }
8962
8963 /**
8964 * @brief Get state of interruption ADC group injected end of unitary conversion
8965 * (0: interrupt disabled, 1: interrupt enabled).
8966 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
8967 * @param ADCx ADC instance
8968 * @retval State of bit (1 or 0).
8969 */
LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef * ADCx)8970 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
8971 {
8972 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
8973 }
8974
8975 /**
8976 * @brief Get state of interruption ADC group injected end of sequence conversions
8977 * (0: interrupt disabled, 1: interrupt enabled).
8978 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
8979 * @param ADCx ADC instance
8980 * @retval State of bit (1 or 0).
8981 */
LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef * ADCx)8982 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
8983 {
8984 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
8985 }
8986
8987 /**
8988 * @brief Get state of interruption ADC analog watchdog 1
8989 * (0: interrupt disabled, 1: interrupt enabled).
8990 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
8991 * @param ADCx ADC instance
8992 * @retval State of bit (1 or 0).
8993 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)8994 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
8995 {
8996 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
8997 }
8998
8999 /**
9000 * @brief Get state of interruption Get ADC analog watchdog 2
9001 * (0: interrupt disabled, 1: interrupt enabled).
9002 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
9003 * @param ADCx ADC instance
9004 * @retval State of bit (1 or 0).
9005 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)9006 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
9007 {
9008 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
9009 }
9010
9011 /**
9012 * @brief Get state of interruption Get ADC analog watchdog 3
9013 * (0: interrupt disabled, 1: interrupt enabled).
9014 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
9015 * @param ADCx ADC instance
9016 * @retval State of bit (1 or 0).
9017 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)9018 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
9019 {
9020 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
9021 }
9022
9023 /**
9024 * @brief Get state of interruption ADC end of calibration
9025 * (0: interrupt disabled, 1: interrupt enabled).
9026 * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
9027 * @param ADCx ADC instance
9028 * @retval State of bit (1 or 0).
9029 */
LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef * ADCx)9030 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx)
9031 {
9032 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
9033 }
9034
9035 /**
9036 * @}
9037 */
9038
9039 #if defined(USE_FULL_LL_DRIVER)
9040 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
9041 * @{
9042 */
9043
9044 /* Initialization of some features of ADC common parameters and multimode */
9045 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *pADCxy_COMMON);
9046 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *pADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
9047 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
9048
9049 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
9050 /* (availability of ADC group injected depends on STM32 families) */
9051 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *pADCx);
9052
9053 /* Initialization of some features of ADC instance */
9054 ErrorStatus LL_ADC_Init(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct);
9055 void LL_ADC_StructInit(const ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct);
9056
9057 /* Initialization of some features of ADC instance and ADC group regular */
9058 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
9059 void LL_ADC_REG_StructInit(const ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
9060
9061 /* Initialization of some features of ADC instance and ADC group injected */
9062 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *pADCx, LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
9063 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
9064
9065 /**
9066 * @}
9067 */
9068 #endif /* USE_FULL_LL_DRIVER */
9069
9070 /**
9071 * @}
9072 */
9073
9074 /**
9075 * @}
9076 */
9077
9078 #endif /* ADC1 || ADC2 || ADC3 */
9079
9080 /**
9081 * @}
9082 */
9083
9084 #ifdef __cplusplus
9085 }
9086 #endif
9087
9088 #endif /* STM32U5xx_LL_ADC_H */
9089
