1 /* 2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef LLF_RND_HW_DEFS_H 8 #define LLF_RND_HW_DEFS_H 9 10 11 /************************ Defines ******************************/ 12 13 /* SRAM base address */ 14 extern uint32_t g_MemOffsetAddr; 15 16 /* The number of words generated in the entropy holding register (EHR) 17 6 words (192 bit) according to HW implementation */ 18 #define LLF_RND_HW_TRNG_EHR_WIDTH_IN_WORDS 6 19 #define LLF_RND_HW_TRNG_EHR_WIDTH_IN_BYTES (LLF_RND_HW_TRNG_EHR_WIDTH_IN_WORDS * sizeof(uint32_t)) 20 #define LLF_RND_HW_TRNG_EHR_WIDTH_IN_BITS (8*LLF_RND_HW_TRNG_EHR_WIDTH_IN_BYTES) 21 22 /* ring oscillator length maximal level */ 23 #define LLF_RND_HW_TRNG_ROSC_LENGTH_MASK 0x0f 24 25 /* ring oscillator offsets and numbers */ 26 #define LLF_RND_HW_TRNG_ROSC0_BIT 0x1 27 #define LLF_RND_HW_TRNG_ROSC1_BIT 0x2 28 #define LLF_RND_HW_TRNG_ROSC2_BIT 0x4 29 #define LLF_RND_HW_TRNG_ROSC3_BIT 0x8 30 #define LLF_RND_HW_TRNG_ROSC0_NUM 0x0 31 #define LLF_RND_HW_TRNG_ROSC1_NUM 0x1 32 #define LLF_RND_HW_TRNG_ROSC2_NUM 0x2 33 #define LLF_RND_HW_TRNG_ROSC3_NUM 0x3 34 35 /* TRNG_CONFIG value for SRC_SEL = 0, SOP_SEL = 1 (SOP = TRNG EHR output)*/ 36 #define LLF_RND_HW_TRNG_WITH_DMA_CONFIG_VAL 0x4 37 38 /* HW_TRNG registers values on FE mode */ 39 /*---------------------------------------*/ 40 #define LLF_RND_HW_DEBUG_CONTROL_VALUE_ON_FE_MODE 0x00000000 41 #define LLF_RND_HW_DMA_EHR_SAMPLES_NUM_ON_FE_MODE 2UL /*for both AES128 and AES256*/ 42 43 /* HW_TRNG registers values on 800-90b mode */ 44 /*---------------------------------------*/ 45 #define LLF_RND_HW_DEBUG_CONTROL_VALUE_ON_TRNG90B_MODE 0x0000000A /* bypass Von-Neumann balancer and autocorrelation test */ 46 #define LLF_RND_HW_DMA_EHR_SAMPLES_NUM_ON_TRNG90B_MODE 22UL 47 48 /* HW RND DMA SRAM address offset, bytes */ 49 50 #define LLF_RND_HW_RND_DMA_ENABLE_VAL 1UL 51 #define LLF_RND_HW_RND_DMA_DISABLE_VAL 0UL 52 #define LLF_RND_HW_RND_SRC_ENABLE_VAL 1UL 53 #define LLF_RND_HW_RND_SRC_DISABLE_VAL 0UL 54 #define LLF_RND_HW_RND_CLK_ENABLE_VAL 1UL 55 #define LLF_RND_HW_RND_CLK_DISABLE_VAL 0UL 56 57 /* currently DX_RNG_ISR_RNG_WATCHDOG_BIT (bit 4 in RNG_ISR) is not defined in dx_rng.h */ 58 #define DX_RNG_ISR_RNG_WATCHDOG_BIT_SHIFT 0x4UL 59 #define DX_RNG_ISR_RNG_WATCHDOG_BIT_SIZE 0x1UL 60 61 /* 62 LLF_RND_TRNG_MAX_TIME_COEFF - scaled coefficient, defining relation of 63 maximal allowed time for TRNG generation (per one ROSC) expected minimal 64 time: MaxAllowedTime = (ExpectTime*LLF_RND_TRNG_MAX_TIME_COEFF) / 64, where 65 64 = (1<<6) is a scaling coefficient. 66 Example: if LLF_RND_TRNG_MAX_TIME_COEFF = 128, then MaxAllowedTime = 67 2*ExpectTime. 68 */ 69 #define LLF_RND_TRNG_MAX_TIME_SCALE 6 /* scaling down by 64 */ 70 #define LLF_RND_TRNG_MAX_TIME_COEFF 128 /* preferable set value as power of 2 */ 71 #define LLF_RND_TRNG_VON_NEUMAN_COEFF 4 /* increases time because part of bits are rejected */ 72 73 74 /* RNG interrupt masks */ 75 /* on trng90b DMA mode masked bits: DMA_DONE, CTRNGT; 76 unmasked: AutoCorrT, VNT EHR, other bits masked: 0xFFFFFFE4*/ 77 #define LLF_RNG_INT_MASK_ON_TRNG90B_MODE 0xFFFFFFE 78 79 /* on FE mode: masked all bits besides - EHR_VALID, AUTOCORR_ERR, and WATCHDOG: 0xFFFFFFEC */ 80 #define LLF_RNG_INT_MASK_ON_FETRNG_MODE 0xFFFFFFEC 81 82 /* TRNG errors mask - masking all bits besides TRNG errors: AutoCorr + VN + * 83 * Watchdog */ 84 #define LLF_RNG_ERRORS_MASK \ 85 ((1UL<<DX_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT) | \ 86 (1UL<<DX_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT) | \ 87 (1UL<<DX_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT)) 88 89 /* auxilary defines */ 90 #define DX_SEP_HW_RESET_SEED_OVERRIDE_FLAG 0x2Ul 91 92 93 94 /*********************** Macros ********************************/ 95 96 #ifdef __cplusplus 97 } 98 #endif 99 100 #endif 101 102 103
