1 /** 2 ****************************************************************************** 3 * @file lis3dsh_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis3dsh_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS3DSH_REGS_H 23 #define LIS3DSH_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS3DSH 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 /** 102 * @} 103 * 104 */ 105 106 #define PROPERTY_DISABLE (0U) 107 #define PROPERTY_ENABLE (1U) 108 109 /** @addtogroup Interfaces_Functions 110 * @brief This section provide a set of functions used to read and 111 * write a generic register of the device. 112 * MANDATORY: return 0 -> no Error. 113 * @{ 114 * 115 */ 116 117 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 118 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 119 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 120 121 typedef struct 122 { 123 /** Component mandatory fields **/ 124 stmdev_write_ptr write_reg; 125 stmdev_read_ptr read_reg; 126 /** Component optional fields **/ 127 stmdev_mdelay_ptr mdelay; 128 /** Customizable optional pointer **/ 129 void *handle; 130 } stmdev_ctx_t; 131 132 /** 133 * @} 134 * 135 */ 136 137 #endif /* MEMS_SHARED_TYPES */ 138 139 #ifndef MEMS_UCF_SHARED_TYPES 140 #define MEMS_UCF_SHARED_TYPES 141 142 /** @defgroup Generic address-data structure definition 143 * @brief This structure is useful to load a predefined configuration 144 * of a sensor. 145 * You can create a sensor configuration by your own or using 146 * Unico / Unicleo tools available on STMicroelectronics 147 * web site. 148 * 149 * @{ 150 * 151 */ 152 153 typedef struct 154 { 155 uint8_t address; 156 uint8_t data; 157 } ucf_line_t; 158 159 /** 160 * @} 161 * 162 */ 163 164 #endif /* MEMS_UCF_SHARED_TYPES */ 165 166 /** 167 * @} 168 * 169 */ 170 171 /** @defgroup LIS3DSH_Infos 172 * @{ 173 * 174 */ 175 176 /** I2C Device Address 8 bit format if SA0=0 -> 3D if SA0=1 -> 3B **/ 177 #define LIS3DSH_I2C_ADD_L 0x3D 178 #define LIS3DSH_I2C_ADD_H 0x3B 179 180 /** Device Identification (Who am I) **/ 181 #define LIS3DSH_ID 0x3F 182 183 /** 184 * @} 185 * 186 */ 187 188 #define LIS3DSH_OUT_T 0x0CU 189 #define LIS3DSH_INFO1 0x0DU 190 #define LIS3DSH_INFO2 0x0EU 191 #define LIS3DSH_WHO_AM_I 0x0FU 192 193 #define LIS3DSH_OFF_X 0x10U 194 #define LIS3DSH_OFF_Y 0x11U 195 #define LIS3DSH_OFF_Z 0x12U 196 197 #define LIS3DSH_CS_X 0x13U 198 #define LIS3DSH_CS_Y 0x14U 199 #define LIS3DSH_CS_Z 0x15U 200 201 #define LIS3DSH_LC_L 0x16U 202 #define LIS3DSH_LC_H 0x17U 203 204 #define LIS3DSH_STAT 0x18U 205 typedef struct 206 { 207 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 208 uint8_t drdy : 1; 209 uint8_t dor : 1; 210 uint8_t int_sm2 : 1; 211 uint8_t int_sm1 : 1; 212 uint8_t sync1 : 1; 213 uint8_t sync2 : 1; 214 uint8_t syncw : 1; 215 uint8_t l_count : 1; //alias LONG 216 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 217 uint8_t l_count : 1; //alias LONG 218 uint8_t syncw : 1; 219 uint8_t sync2 : 1; 220 uint8_t sync1 : 1; 221 uint8_t int_sm1 : 1; 222 uint8_t int_sm2 : 1; 223 uint8_t dor : 1; 224 uint8_t drdy : 1; 225 #endif /* DRV_BYTE_ORDER */ 226 } lis3dsh_stat_t; 227 228 #define LIS3DSH_PEAK1 0x19U 229 #define LIS3DSH_PEAK2 0x1AU 230 231 #define LIS3DSH_VFC_1 0x1BU 232 #define LIS3DSH_VFC_2 0x1CU 233 #define LIS3DSH_VFC_3 0x1DU 234 #define LIS3DSH_VFC_4 0x1EU 235 236 #define LIS3DSH_THRS3 0x1FU 237 #define LIS3DSH_CTRL_REG4 0x20U 238 typedef struct 239 { 240 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 241 uint8_t xen : 1; 242 uint8_t yen : 1; 243 uint8_t zen : 1; 244 uint8_t bdu : 1; 245 uint8_t odr : 4; 246 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 247 uint8_t odr : 4; 248 uint8_t bdu : 1; 249 uint8_t zen : 1; 250 uint8_t yen : 1; 251 uint8_t xen : 1; 252 #endif /* DRV_BYTE_ORDER */ 253 } lis3dsh_ctrl_reg4_t; 254 255 #define LIS3DSH_CTRL_REG1 0x21U 256 typedef struct 257 { 258 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 259 uint8_t sm1_en : 1; 260 uint8_t not_used_01 : 2; 261 uint8_t sm1_pin : 1; 262 uint8_t not_used_02 : 1; 263 uint8_t hyst_1 : 3; 264 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 265 uint8_t hyst_1 : 3; 266 uint8_t not_used_02 : 1; 267 uint8_t sm1_pin : 1; 268 uint8_t not_used_01 : 2; 269 uint8_t sm1_en : 1; 270 #endif /* DRV_BYTE_ORDER */ 271 } lis3dsh_ctrl_reg1_t; 272 273 #define LIS3DSH_CTRL_REG2 0x22U 274 typedef struct 275 { 276 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 277 uint8_t sm2_en : 1; 278 uint8_t not_used_01 : 2; 279 uint8_t sm2_pin : 1; 280 uint8_t not_used_02 : 1; 281 uint8_t hyst_2 : 3; 282 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 283 uint8_t hyst_2 : 3; 284 uint8_t not_used_02 : 1; 285 uint8_t sm2_pin : 1; 286 uint8_t not_used_01 : 2; 287 uint8_t sm2_en : 1; 288 #endif /* DRV_BYTE_ORDER */ 289 } lis3dsh_ctrl_reg2_t; 290 291 #define LIS3DSH_CTRL_REG3 0x23U 292 typedef struct 293 { 294 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 295 uint8_t strt : 1; 296 uint8_t not_used_01 : 1; 297 uint8_t vfilt : 1; 298 uint8_t int1_en : 1; 299 uint8_t int2_en : 1; 300 uint8_t iel : 1; 301 uint8_t iea : 1; 302 uint8_t dr_en : 1; 303 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 304 uint8_t dr_en : 1; 305 uint8_t iea : 1; 306 uint8_t iel : 1; 307 uint8_t int2_en : 1; 308 uint8_t int1_en : 1; 309 uint8_t vfilt : 1; 310 uint8_t not_used_01 : 1; 311 uint8_t strt : 1; 312 #endif /* DRV_BYTE_ORDER */ 313 } lis3dsh_ctrl_reg3_t; 314 315 #define LIS3DSH_CTRL_REG5 0x24U 316 typedef struct 317 { 318 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 319 uint8_t sim : 1; 320 uint8_t st : 2; 321 uint8_t fscale : 3; 322 uint8_t bw : 2; 323 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 324 uint8_t bw : 2; 325 uint8_t fscale : 3; 326 uint8_t st : 2; 327 uint8_t sim : 1; 328 #endif /* DRV_BYTE_ORDER */ 329 } lis3dsh_ctrl_reg5_t; 330 331 #define LIS3DSH_CTRL_REG6 0x25U 332 typedef struct 333 { 334 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 335 uint8_t p2_boot : 1; 336 uint8_t p1_overrun : 1; 337 uint8_t p1_wtm : 1; 338 uint8_t p1_empty : 1; 339 uint8_t add_inc : 1; 340 uint8_t wtm_en : 1; 341 uint8_t fifo_en : 1; 342 uint8_t boot : 1; 343 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 344 uint8_t boot : 1; 345 uint8_t fifo_en : 1; 346 uint8_t wtm_en : 1; 347 uint8_t add_inc : 1; 348 uint8_t p1_empty : 1; 349 uint8_t p1_wtm : 1; 350 uint8_t p1_overrun : 1; 351 uint8_t p2_boot : 1; 352 #endif /* DRV_BYTE_ORDER */ 353 } lis3dsh_ctrl_reg6_t; 354 355 #define LIS3DSH_STATUS 0x27U 356 typedef struct 357 { 358 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 359 uint8_t xda : 1; 360 uint8_t yda : 1; 361 uint8_t zda : 1; 362 uint8_t zyxda : 1; 363 uint8_t _xor : 1; 364 uint8_t yor : 1; 365 uint8_t zor : 1; 366 uint8_t zyxor : 1; 367 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 368 uint8_t zyxor : 1; 369 uint8_t zor : 1; 370 uint8_t yor : 1; 371 uint8_t _xor : 1; 372 uint8_t zyxda : 1; 373 uint8_t zda : 1; 374 uint8_t yda : 1; 375 uint8_t xda : 1; 376 #endif /* DRV_BYTE_ORDER */ 377 } lis3dsh_status_t; 378 379 #define LIS3DSH_OUT_X_L 0x28U 380 #define LIS3DSH_OUT_X_H 0x29U 381 #define LIS3DSH_OUT_Y_L 0x2AU 382 #define LIS3DSH_OUT_Y_H 0x2BU 383 #define LIS3DSH_OUT_Z_L 0x2CU 384 #define LIS3DSH_OUT_Z_H 0x2DU 385 #define LIS3DSH_FIFO_CTRL 0X2EU 386 typedef struct 387 { 388 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 389 uint8_t wtmp : 5; 390 uint8_t fmode : 3; 391 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 392 uint8_t fmode : 3; 393 uint8_t wtmp : 5; 394 #endif /* DRV_BYTE_ORDER */ 395 } lis3dsh_fifo_ctrl_t; 396 397 #define LIS3DSH_FIFO_SRC 0x2FU 398 typedef struct 399 { 400 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 401 uint8_t fss : 5; 402 uint8_t empty : 1; 403 uint8_t ovrn_fifo : 1; 404 uint8_t wtm : 1; 405 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 406 uint8_t wtm : 1; 407 uint8_t ovrn_fifo : 1; 408 uint8_t empty : 1; 409 uint8_t fss : 5; 410 #endif /* DRV_BYTE_ORDER */ 411 } lis3dsh_fifo_src_t; 412 413 /* State Machine 1 */ 414 415 #define LIS3DSH_ST0_1 0x40U 416 #define LIS3DSH_ST1_1 0x41U 417 #define LIS3DSH_ST2_1 0x42U 418 #define LIS3DSH_ST3_1 0x43U 419 #define LIS3DSH_ST4_1 0x44U 420 #define LIS3DSH_ST5_1 0x45U 421 #define LIS3DSH_ST6_1 0x46U 422 #define LIS3DSH_ST7_1 0x47U 423 #define LIS3DSH_ST8_1 0x48U 424 #define LIS3DSH_ST9_1 0x49U 425 #define LIS3DSH_ST10_1 0x4AU 426 #define LIS3DSH_ST11_1 0x4BU 427 #define LIS3DSH_ST12_1 0x4CU 428 #define LIS3DSH_ST13_1 0x4DU 429 #define LIS3DSH_ST14_1 0x4EU 430 #define LIS3DSH_ST15_1 0x4FU 431 #define LIS3DSH_TIM4_1 0x50U 432 #define LIS3DSH_TIM3_1 0x51U 433 #define LIS3DSH_TIM2_1_L 0x52U 434 #define LIS3DSH_TIM2_1_H 0x53U 435 #define LIS3DSH_TIM1_1_L 0x54U 436 #define LIS3DSH_TIM1_1_H 0x55U 437 #define LIS3DSH_THRS2_1 0x56U 438 #define LIS3DSH_THRS1_1 0x57U 439 #define LIS3DSH_MASK1_B 0x59U 440 typedef struct 441 { 442 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 443 uint8_t n_v : 1; 444 uint8_t p_v : 1; 445 uint8_t n_z : 1; 446 uint8_t p_z : 1; 447 uint8_t n_y : 1; 448 uint8_t p_y : 1; 449 uint8_t n_x : 1; 450 uint8_t p_x : 1; 451 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 452 uint8_t p_x : 1; 453 uint8_t n_x : 1; 454 uint8_t p_y : 1; 455 uint8_t n_y : 1; 456 uint8_t p_z : 1; 457 uint8_t n_z : 1; 458 uint8_t p_v : 1; 459 uint8_t n_v : 1; 460 #endif /* DRV_BYTE_ORDER */ 461 } lis3dsh_mask1_b_t; 462 463 #define LIS3DSH_MASK1_A 0x5AU 464 typedef struct 465 { 466 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 467 uint8_t n_v : 1; 468 uint8_t p_v : 1; 469 uint8_t n_z : 1; 470 uint8_t p_z : 1; 471 uint8_t n_y : 1; 472 uint8_t p_y : 1; 473 uint8_t n_x : 1; 474 uint8_t p_x : 1; 475 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 476 uint8_t p_x : 1; 477 uint8_t n_x : 1; 478 uint8_t p_y : 1; 479 uint8_t n_y : 1; 480 uint8_t p_z : 1; 481 uint8_t n_z : 1; 482 uint8_t p_v : 1; 483 uint8_t n_v : 1; 484 #endif /* DRV_BYTE_ORDER */ 485 } lis3dsh_mask1_a_t; 486 487 #define LIS3DSH_SETT1 0x5BU 488 typedef struct 489 { 490 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 491 uint8_t sitr : 1; 492 uint8_t r_tam : 1; 493 uint8_t thr3_ma : 1; 494 uint8_t not_used_01 : 2; 495 uint8_t abs : 1; 496 uint8_t thr3_sa : 1; 497 uint8_t p_det : 1; 498 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 499 uint8_t p_det : 1; 500 uint8_t thr3_sa : 1; 501 uint8_t abs : 1; 502 uint8_t not_used_01 : 2; 503 uint8_t thr3_ma : 1; 504 uint8_t r_tam : 1; 505 uint8_t sitr : 1; 506 #endif /* DRV_BYTE_ORDER */ 507 } lis3dsh_sett1_t; 508 509 #define LIS3DSH_PR1 0x5CU 510 typedef struct 511 { 512 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 513 uint8_t pp : 4; 514 uint8_t rp : 4; 515 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 516 uint8_t rp : 4; 517 uint8_t pp : 4; 518 #endif /* DRV_BYTE_ORDER */ 519 } lis3dsh_pr1_t; 520 521 #define LIS3DSH_TC1_L 0x5DU 522 #define LIS3DSH_TC1_H 0x5EU 523 #define LIS3DSH_OUTS1 0x5FU 524 typedef struct 525 { 526 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 527 uint8_t n_v : 1; 528 uint8_t p_v : 1; 529 uint8_t n_z : 1; 530 uint8_t p_z : 1; 531 uint8_t n_y : 1; 532 uint8_t p_y : 1; 533 uint8_t n_x : 1; 534 uint8_t p_x : 1; 535 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 536 uint8_t p_x : 1; 537 uint8_t n_x : 1; 538 uint8_t p_y : 1; 539 uint8_t n_y : 1; 540 uint8_t p_z : 1; 541 uint8_t n_z : 1; 542 uint8_t p_v : 1; 543 uint8_t n_v : 1; 544 #endif /* DRV_BYTE_ORDER */ 545 } lis3dsh_outs1_t; 546 547 /* State Machine 2 */ 548 549 #define LIS3DSH_ST0_2 0x60U 550 #define LIS3DSH_ST1_2 0x61U 551 #define LIS3DSH_ST2_2 0x62U 552 #define LIS3DSH_ST3_2 0x63U 553 #define LIS3DSH_ST4_2 0x64U 554 #define LIS3DSH_ST5_2 0x65U 555 #define LIS3DSH_ST6_2 0x66U 556 #define LIS3DSH_ST7_2 0x67U 557 #define LIS3DSH_ST8_2 0x68U 558 #define LIS3DSH_ST9_2 0x69U 559 #define LIS3DSH_ST10_2 0x6AU 560 #define LIS3DSH_ST11_2 0x6BU 561 #define LIS3DSH_ST12_2 0x6CU 562 #define LIS3DSH_ST13_2 0x6DU 563 #define LIS3DSH_ST14_2 0x6EU 564 #define LIS3DSH_ST15_2 0x6FU 565 #define LIS3DSH_TIM4_2 0x70U 566 #define LIS3DSH_TIM3_2 0x71U 567 #define LIS3DSH_TIM2_2_L 0x72U 568 #define LIS3DSH_TIM2_2_H 0x73U 569 #define LIS3DSH_TIM1_2_L 0x74U 570 #define LIS3DSH_TIM1_2_H 0x75U 571 #define LIS3DSH_THRS2_2 0x76U 572 #define LIS3DSH_THRS1_2 0x77U 573 #define LIS3DSH_DES2 0x78U 574 #define LIS3DSH_MASK2_B 0x79U 575 typedef struct 576 { 577 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 578 uint8_t n_v : 1; 579 uint8_t p_v : 1; 580 uint8_t n_z : 1; 581 uint8_t p_z : 1; 582 uint8_t n_y : 1; 583 uint8_t p_y : 1; 584 uint8_t n_x : 1; 585 uint8_t p_x : 1; 586 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 587 uint8_t p_x : 1; 588 uint8_t n_x : 1; 589 uint8_t p_y : 1; 590 uint8_t n_y : 1; 591 uint8_t p_z : 1; 592 uint8_t n_z : 1; 593 uint8_t p_v : 1; 594 uint8_t n_v : 1; 595 #endif /* DRV_BYTE_ORDER */ 596 } lis3dsh_mask2_b_t; 597 598 #define LIS3DSH_MASK2_A 0x7AU 599 typedef struct 600 { 601 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 602 uint8_t n_v : 1; 603 uint8_t p_v : 1; 604 uint8_t n_z : 1; 605 uint8_t p_z : 1; 606 uint8_t n_y : 1; 607 uint8_t p_y : 1; 608 uint8_t n_x : 1; 609 uint8_t p_x : 1; 610 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 611 uint8_t p_x : 1; 612 uint8_t n_x : 1; 613 uint8_t p_y : 1; 614 uint8_t n_y : 1; 615 uint8_t p_z : 1; 616 uint8_t n_z : 1; 617 uint8_t p_v : 1; 618 uint8_t n_v : 1; 619 #endif /* DRV_BYTE_ORDER */ 620 } lis3dsh_mask2_a_t; 621 622 #define LIS3DSH_SETT2 0x7BU 623 typedef struct 624 { 625 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 626 uint8_t sitr : 1; 627 uint8_t r_tam : 1; 628 uint8_t thr3_ma : 1; 629 uint8_t d_cs : 1; 630 uint8_t radi : 1; 631 uint8_t abs : 1; 632 uint8_t thr3_sa : 1; 633 uint8_t p_det : 1; 634 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 635 uint8_t p_det : 1; 636 uint8_t thr3_sa : 1; 637 uint8_t abs : 1; 638 uint8_t radi : 1; 639 uint8_t d_cs : 1; 640 uint8_t thr3_ma : 1; 641 uint8_t r_tam : 1; 642 uint8_t sitr : 1; 643 #endif /* DRV_BYTE_ORDER */ 644 } lis3dsh_sett2_t; 645 646 #define LIS3DSH_PR2 0x7CU 647 typedef struct 648 { 649 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 650 uint8_t pp : 4; 651 uint8_t rp : 4; 652 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 653 uint8_t rp : 4; 654 uint8_t pp : 4; 655 #endif /* DRV_BYTE_ORDER */ 656 } lis3dsh_pr2_t; 657 658 #define LIS3DSH_TC2_L 0x7DU 659 #define LIS3DSH_TC2_H 0x7EU 660 #define LIS3DSH_OUTS2 0x7FU 661 typedef struct 662 { 663 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 664 uint8_t n_v : 1; 665 uint8_t p_v : 1; 666 uint8_t n_z : 1; 667 uint8_t p_z : 1; 668 uint8_t n_y : 1; 669 uint8_t p_y : 1; 670 uint8_t n_x : 1; 671 uint8_t p_x : 1; 672 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 673 uint8_t p_x : 1; 674 uint8_t n_x : 1; 675 uint8_t p_y : 1; 676 uint8_t n_y : 1; 677 uint8_t p_z : 1; 678 uint8_t n_z : 1; 679 uint8_t p_v : 1; 680 uint8_t n_v : 1; 681 #endif /* DRV_BYTE_ORDER */ 682 } lis3dsh_outs2_t; 683 684 /** 685 * @defgroup LIS3DSH_Register_Union 686 * @brief This union group all the registers having a bit-field 687 * description. 688 * This union is useful but it's not needed by the driver. 689 * 690 * REMOVING this union you are compliant with: 691 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 692 * 693 * @{ 694 * 695 */ 696 typedef union 697 { 698 lis3dsh_stat_t stat; 699 lis3dsh_ctrl_reg4_t ctrl_reg4; 700 lis3dsh_ctrl_reg1_t ctrl_reg1; 701 lis3dsh_ctrl_reg2_t ctrl_reg2; 702 lis3dsh_ctrl_reg3_t ctrl_reg3; 703 lis3dsh_ctrl_reg5_t ctrl_reg5; 704 lis3dsh_ctrl_reg6_t ctrl_reg6; 705 lis3dsh_status_t status; 706 lis3dsh_fifo_ctrl_t fifo_ctrl; 707 lis3dsh_fifo_src_t fifo_src; 708 lis3dsh_mask1_b_t mask1_b; 709 lis3dsh_mask1_a_t mask1_a; 710 lis3dsh_sett1_t sett1; 711 lis3dsh_pr1_t pr1; 712 lis3dsh_outs1_t outs1; 713 lis3dsh_mask2_b_t mask2_b; 714 lis3dsh_mask2_a_t mask2_a; 715 lis3dsh_sett2_t sett2; 716 lis3dsh_pr2_t pr2; 717 lis3dsh_outs2_t outs2; 718 bitwise_t bitwise; 719 uint8_t byte; 720 } lis3dsh_reg_t; 721 722 /** 723 * @} 724 * 725 */ 726 727 #ifndef __weak 728 #define __weak __attribute__((weak)) 729 #endif /* __weak */ 730 731 /* 732 * These are the basic platform dependent I/O routines to read 733 * and write device registers connected on a standard bus. 734 * The driver keeps offering a default implementation based on function 735 * pointers to read/write routines for backward compatibility. 736 * The __weak directive allows the final application to overwrite 737 * them with a custom implementation. 738 */ 739 740 int32_t lis3dsh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 741 uint8_t *data, 742 uint16_t len); 743 int32_t lis3dsh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 744 uint8_t *data, 745 uint16_t len); 746 747 float_t lis3dsh_from_fs2_to_mg(int16_t lsb); 748 float_t lis3dsh_from_fs4_to_mg(int16_t lsb); 749 float_t lis3dsh_from_fs6_to_mg(int16_t lsb); 750 float_t lis3dsh_from_fs8_to_mg(int16_t lsb); 751 float_t lis3dsh_from_fs16_to_mg(int16_t lsb); 752 float_t lis3dsh_from_lsb_to_celsius(int8_t lsb); 753 754 typedef struct 755 { 756 uint8_t whoami; 757 uint8_t info1; 758 uint8_t info2; 759 } lis3dsh_id_t; 760 int32_t lis3dsh_id_get(stmdev_ctx_t *ctx, lis3dsh_id_t *val); 761 762 typedef enum 763 { 764 LIS3DSH_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 765 LIS3DSH_SPI_3W = 0x01, /* SDO / SDI share the same pin */ 766 } lis3dsh_bus_mode_t; 767 int32_t lis3dsh_bus_mode_set(stmdev_ctx_t *ctx, 768 lis3dsh_bus_mode_t *val); 769 int32_t lis3dsh_bus_mode_get(stmdev_ctx_t *ctx, 770 lis3dsh_bus_mode_t *val); 771 772 typedef enum 773 { 774 LIS3DSH_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 775 LIS3DSH_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 776 LIS3DSH_RESET = 0x02, /* Reset configuration registers */ 777 } lis3dsh_init_t; 778 int32_t lis3dsh_init_set(stmdev_ctx_t *ctx, lis3dsh_init_t val); 779 780 typedef struct 781 { 782 uint8_t sw_reset : 783 1; /* Restoring configuration registers */ 784 uint8_t boot : 1; /* Restoring calibration parameters */ 785 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 786 uint8_t ovrn_xl : 1; /* Accelerometer data overrun */ 787 } lis3dsh_status_var_t; 788 int32_t lis3dsh_status_get(stmdev_ctx_t *ctx, 789 lis3dsh_status_var_t *val); 790 791 typedef struct 792 { 793 uint8_t active_low : 1; /* 1 = active low / 0 = active high */ 794 uint8_t latched : 1; /* Signals 1 = latched / 0 = pulsed */ 795 } lis3dsh_int_mode_t; 796 int32_t lis3dsh_interrupt_mode_set(stmdev_ctx_t *ctx, 797 lis3dsh_int_mode_t *val); 798 int32_t lis3dsh_interrupt_mode_get(stmdev_ctx_t *ctx, 799 lis3dsh_int_mode_t *val); 800 801 typedef struct 802 { 803 uint8_t drdy_xl : 1; /* Accelerometer data ready. */ 804 uint8_t fifo_empty : 1; /* FIFO empty indication. */ 805 uint8_t fifo_th : 1; /* FIFO threshold reached */ 806 uint8_t fifo_full : 1; /* FIFO full */ 807 uint8_t fsm1 : 1; /* State machine 1 interrupt event */ 808 uint8_t fsm2 : 1; /* State machine 2 interrupt event */ 809 } lis3dsh_pin_int1_route_t; 810 int32_t lis3dsh_pin_int1_route_set(stmdev_ctx_t *ctx, 811 lis3dsh_pin_int1_route_t *val); 812 int32_t lis3dsh_pin_int1_route_get(stmdev_ctx_t *ctx, 813 lis3dsh_pin_int1_route_t *val); 814 815 typedef struct 816 { 817 uint8_t fsm1 : 1; /* State machine 1 interrupt event */ 818 uint8_t fsm2 : 1; /* State machine 2 interrupt event */ 819 uint8_t boot : 1; /* Restoring calibration parameters */ 820 } lis3dsh_pin_int2_route_t; 821 int32_t lis3dsh_pin_int2_route_set(stmdev_ctx_t *ctx, 822 lis3dsh_pin_int2_route_t *val); 823 int32_t lis3dsh_pin_int2_route_get(stmdev_ctx_t *ctx, 824 lis3dsh_pin_int2_route_t *val); 825 826 typedef struct 827 { 828 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 829 uint8_t ovrn_xl : 1; /* Accelerometer data overrun */ 830 uint8_t fsm_lc : 1; /* long counter flag (for both SM) */ 831 uint8_t fsm_ext_sync : 832 1; /* Synchronization with ext-host requested */ 833 uint8_t fsm1_wait_fsm2 : 1; /* fsm1 wait fsm2 */ 834 uint8_t fsm2_wait_fsm1 : 1; /* fsm2 wait fsm1 */ 835 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 836 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 837 uint8_t fifo_ovr : 1; /* FIFO overrun */ 838 uint8_t fifo_empty : 1; /* FIFO empty indication. */ 839 uint8_t fifo_full : 1; /* FIFO full */ 840 uint8_t fifo_th : 1; /* FIFO threshold reached */ 841 } lis3dsh_all_sources_t; 842 int32_t lis3dsh_all_sources_get(stmdev_ctx_t *ctx, 843 lis3dsh_all_sources_t *val); 844 845 typedef struct 846 { 847 enum 848 { 849 LIS3DSH_OFF = 0x00, /* in power down */ 850 LIS3DSH_3Hz125 = 0x01, /* Data rate @3.125 Hz */ 851 LIS3DSH_6Hz25 = 0x02, /* Data rate @6.25 Hz */ 852 LIS3DSH_12Hz5 = 0x03, /* Data rate @12.5 Hz */ 853 LIS3DSH_25Hz = 0x04, /* Data rate @25 Hz */ 854 LIS3DSH_50Hz = 0x05, /* Data rate @50 Hz */ 855 LIS3DSH_100Hz = 0x06, /* Data rate @100 Hz */ 856 LIS3DSH_400Hz = 0x07, /* Data rate @400 Hz */ 857 LIS3DSH_800Hz = 0x08, /* Data rate @800 Hz */ 858 LIS3DSH_1kHz6 = 0x09, /* Data rate @1600 Hz */ 859 } odr; 860 enum 861 { 862 LIS3DSH_2g = 0, 863 LIS3DSH_4g = 1, 864 LIS3DSH_6g = 2, 865 LIS3DSH_8g = 3, 866 LIS3DSH_16g = 4, 867 } fs; 868 } lis3dsh_md_t; 869 int32_t lis3dsh_mode_set(stmdev_ctx_t *ctx, lis3dsh_md_t *val); 870 int32_t lis3dsh_mode_get(stmdev_ctx_t *ctx, lis3dsh_md_t *val); 871 872 typedef struct 873 { 874 struct 875 { 876 float_t mg[3]; 877 int16_t raw[3]; 878 } xl; 879 struct 880 { 881 float_t deg_c; 882 int8_t raw; 883 } heat; 884 } lis3dsh_data_t; 885 int32_t lis3dsh_data_get(stmdev_ctx_t *ctx, lis3dsh_md_t *md, 886 lis3dsh_data_t *data); 887 888 typedef enum 889 { 890 LIS3DSH_ST_DISABLE = 0, 891 LIS3DSH_ST_POSITIVE = 1, 892 LIS3DSH_ST_NEGATIVE = 2, 893 } lis3dsh_st_t; 894 int32_t lis3dsh_self_test_set(stmdev_ctx_t *ctx, lis3dsh_st_t val); 895 int32_t lis3dsh_self_test_get(stmdev_ctx_t *ctx, lis3dsh_st_t *val); 896 897 /** 898 * @} 899 * 900 */ 901 902 #ifdef __cplusplus 903 } 904 #endif 905 906 #endif /*LIS3DSH_DRIVER_H */ 907 908 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 909
