1 /** 2 ****************************************************************************** 3 * @file lis3dh_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis3dh_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS3DH_REGS_H 23 #define LIS3DH_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS3DH 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS3DH_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ 172 #define LIS3DH_I2C_ADD_L 0x31U 173 #define LIS3DH_I2C_ADD_H 0x33U 174 175 /** Device Identification (Who am I) **/ 176 #define LIS3DH_ID 0x33U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LIS3DH_STATUS_REG_AUX 0x07U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t _1da : 1; 188 uint8_t _2da : 1; 189 uint8_t _3da : 1; 190 uint8_t _321da : 1; 191 uint8_t _1or : 1; 192 uint8_t _2or : 1; 193 uint8_t _3or : 1; 194 uint8_t _321or : 1; 195 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 196 uint8_t _321or : 1; 197 uint8_t _3or : 1; 198 uint8_t _2or : 1; 199 uint8_t _1or : 1; 200 uint8_t _321da : 1; 201 uint8_t _3da : 1; 202 uint8_t _2da : 1; 203 uint8_t _1da : 1; 204 #endif /* DRV_BYTE_ORDER */ 205 } lis3dh_status_reg_aux_t; 206 207 #define LIS3DH_OUT_ADC1_L 0x08U 208 #define LIS3DH_OUT_ADC1_H 0x09U 209 #define LIS3DH_OUT_ADC2_L 0x0AU 210 #define LIS3DH_OUT_ADC2_H 0x0BU 211 #define LIS3DH_OUT_ADC3_L 0x0CU 212 #define LIS3DH_OUT_ADC3_H 0x0DU 213 #define LIS3DH_WHO_AM_I 0x0FU 214 215 #define LIS3DH_CTRL_REG0 0x1EU 216 typedef struct 217 { 218 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 219 uint8_t not_used_01 : 7; 220 uint8_t sdo_pu_disc : 1; 221 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 222 uint8_t sdo_pu_disc : 1; 223 uint8_t not_used_01 : 7; 224 #endif /* DRV_BYTE_ORDER */ 225 } lis3dh_ctrl_reg0_t; 226 227 #define LIS3DH_TEMP_CFG_REG 0x1FU 228 typedef struct 229 { 230 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 231 uint8_t not_used_01 : 6; 232 uint8_t adc_pd : 1; 233 uint8_t temp_en : 1; 234 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 235 uint8_t temp_en : 1; 236 uint8_t adc_pd : 1; 237 uint8_t not_used_01 : 6; 238 #endif /* DRV_BYTE_ORDER */ 239 } lis3dh_temp_cfg_reg_t; 240 241 #define LIS3DH_CTRL_REG1 0x20U 242 typedef struct 243 { 244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 245 uint8_t xen : 1; 246 uint8_t yen : 1; 247 uint8_t zen : 1; 248 uint8_t lpen : 1; 249 uint8_t odr : 4; 250 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 251 uint8_t odr : 4; 252 uint8_t lpen : 1; 253 uint8_t zen : 1; 254 uint8_t yen : 1; 255 uint8_t xen : 1; 256 #endif /* DRV_BYTE_ORDER */ 257 } lis3dh_ctrl_reg1_t; 258 259 #define LIS3DH_CTRL_REG2 0x21U 260 typedef struct 261 { 262 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 263 uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ 264 uint8_t fds : 1; 265 uint8_t hpcf : 2; 266 uint8_t hpm : 2; 267 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 268 uint8_t hpm : 2; 269 uint8_t hpcf : 2; 270 uint8_t fds : 1; 271 uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ 272 #endif /* DRV_BYTE_ORDER */ 273 } lis3dh_ctrl_reg2_t; 274 275 #define LIS3DH_CTRL_REG3 0x22U 276 typedef struct 277 { 278 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 279 uint8_t not_used_01 : 1; 280 uint8_t i1_overrun : 1; 281 uint8_t i1_wtm : 1; 282 uint8_t i1_321da : 1; 283 uint8_t i1_zyxda : 1; 284 uint8_t i1_ia2 : 1; 285 uint8_t i1_ia1 : 1; 286 uint8_t i1_click : 1; 287 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 288 uint8_t i1_click : 1; 289 uint8_t i1_ia1 : 1; 290 uint8_t i1_ia2 : 1; 291 uint8_t i1_zyxda : 1; 292 uint8_t i1_321da : 1; 293 uint8_t i1_wtm : 1; 294 uint8_t i1_overrun : 1; 295 uint8_t not_used_01 : 1; 296 #endif /* DRV_BYTE_ORDER */ 297 } lis3dh_ctrl_reg3_t; 298 299 #define LIS3DH_CTRL_REG4 0x23U 300 typedef struct 301 { 302 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 303 uint8_t sim : 1; 304 uint8_t st : 2; 305 uint8_t hr : 1; 306 uint8_t fs : 2; 307 uint8_t ble : 1; 308 uint8_t bdu : 1; 309 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 310 uint8_t bdu : 1; 311 uint8_t ble : 1; 312 uint8_t fs : 2; 313 uint8_t hr : 1; 314 uint8_t st : 2; 315 uint8_t sim : 1; 316 #endif /* DRV_BYTE_ORDER */ 317 } lis3dh_ctrl_reg4_t; 318 319 #define LIS3DH_CTRL_REG5 0x24U 320 typedef struct 321 { 322 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 323 uint8_t d4d_int2 : 1; 324 uint8_t lir_int2 : 1; 325 uint8_t d4d_int1 : 1; 326 uint8_t lir_int1 : 1; 327 uint8_t not_used_01 : 2; 328 uint8_t fifo_en : 1; 329 uint8_t boot : 1; 330 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 331 uint8_t boot : 1; 332 uint8_t fifo_en : 1; 333 uint8_t not_used_01 : 2; 334 uint8_t lir_int1 : 1; 335 uint8_t d4d_int1 : 1; 336 uint8_t lir_int2 : 1; 337 uint8_t d4d_int2 : 1; 338 #endif /* DRV_BYTE_ORDER */ 339 } lis3dh_ctrl_reg5_t; 340 341 #define LIS3DH_CTRL_REG6 0x25U 342 typedef struct 343 { 344 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 345 uint8_t not_used_01 : 1; 346 uint8_t int_polarity : 1; 347 uint8_t not_used_02 : 1; 348 uint8_t i2_act : 1; 349 uint8_t i2_boot : 1; 350 uint8_t i2_ia2 : 1; 351 uint8_t i2_ia1 : 1; 352 uint8_t i2_click : 1; 353 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 354 uint8_t i2_click : 1; 355 uint8_t i2_ia1 : 1; 356 uint8_t i2_ia2 : 1; 357 uint8_t i2_boot : 1; 358 uint8_t i2_act : 1; 359 uint8_t not_used_02 : 1; 360 uint8_t int_polarity : 1; 361 uint8_t not_used_01 : 1; 362 #endif /* DRV_BYTE_ORDER */ 363 } lis3dh_ctrl_reg6_t; 364 365 #define LIS3DH_REFERENCE 0x26U 366 #define LIS3DH_STATUS_REG 0x27U 367 typedef struct 368 { 369 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 370 uint8_t xda : 1; 371 uint8_t yda : 1; 372 uint8_t zda : 1; 373 uint8_t zyxda : 1; 374 uint8_t _xor : 1; 375 uint8_t yor : 1; 376 uint8_t zor : 1; 377 uint8_t zyxor : 1; 378 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 379 uint8_t zyxor : 1; 380 uint8_t zor : 1; 381 uint8_t yor : 1; 382 uint8_t _xor : 1; 383 uint8_t zyxda : 1; 384 uint8_t zda : 1; 385 uint8_t yda : 1; 386 uint8_t xda : 1; 387 #endif /* DRV_BYTE_ORDER */ 388 } lis3dh_status_reg_t; 389 390 #define LIS3DH_OUT_X_L 0x28U 391 #define LIS3DH_OUT_X_H 0x29U 392 #define LIS3DH_OUT_Y_L 0x2AU 393 #define LIS3DH_OUT_Y_H 0x2BU 394 #define LIS3DH_OUT_Z_L 0x2CU 395 #define LIS3DH_OUT_Z_H 0x2DU 396 #define LIS3DH_FIFO_CTRL_REG 0x2EU 397 typedef struct 398 { 399 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 400 uint8_t fth : 5; 401 uint8_t tr : 1; 402 uint8_t fm : 2; 403 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 404 uint8_t fm : 2; 405 uint8_t tr : 1; 406 uint8_t fth : 5; 407 #endif /* DRV_BYTE_ORDER */ 408 } lis3dh_fifo_ctrl_reg_t; 409 410 #define LIS3DH_FIFO_SRC_REG 0x2FU 411 typedef struct 412 { 413 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 414 uint8_t fss : 5; 415 uint8_t empty : 1; 416 uint8_t ovrn_fifo : 1; 417 uint8_t wtm : 1; 418 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 419 uint8_t wtm : 1; 420 uint8_t ovrn_fifo : 1; 421 uint8_t empty : 1; 422 uint8_t fss : 5; 423 #endif /* DRV_BYTE_ORDER */ 424 } lis3dh_fifo_src_reg_t; 425 426 #define LIS3DH_INT1_CFG 0x30U 427 typedef struct 428 { 429 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 430 uint8_t xlie : 1; 431 uint8_t xhie : 1; 432 uint8_t ylie : 1; 433 uint8_t yhie : 1; 434 uint8_t zlie : 1; 435 uint8_t zhie : 1; 436 uint8_t _6d : 1; 437 uint8_t aoi : 1; 438 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 439 uint8_t aoi : 1; 440 uint8_t _6d : 1; 441 uint8_t zhie : 1; 442 uint8_t zlie : 1; 443 uint8_t yhie : 1; 444 uint8_t ylie : 1; 445 uint8_t xhie : 1; 446 uint8_t xlie : 1; 447 #endif /* DRV_BYTE_ORDER */ 448 } lis3dh_int1_cfg_t; 449 450 #define LIS3DH_INT1_SRC 0x31U 451 typedef struct 452 { 453 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 454 uint8_t xl : 1; 455 uint8_t xh : 1; 456 uint8_t yl : 1; 457 uint8_t yh : 1; 458 uint8_t zl : 1; 459 uint8_t zh : 1; 460 uint8_t ia : 1; 461 uint8_t not_used_01 : 1; 462 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 463 uint8_t not_used_01 : 1; 464 uint8_t ia : 1; 465 uint8_t zh : 1; 466 uint8_t zl : 1; 467 uint8_t yh : 1; 468 uint8_t yl : 1; 469 uint8_t xh : 1; 470 uint8_t xl : 1; 471 #endif /* DRV_BYTE_ORDER */ 472 } lis3dh_int1_src_t; 473 474 #define LIS3DH_INT1_THS 0x32U 475 typedef struct 476 { 477 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 478 uint8_t ths : 7; 479 uint8_t not_used_01 : 1; 480 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 481 uint8_t not_used_01 : 1; 482 uint8_t ths : 7; 483 #endif /* DRV_BYTE_ORDER */ 484 } lis3dh_int1_ths_t; 485 486 #define LIS3DH_INT1_DURATION 0x33U 487 typedef struct 488 { 489 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 490 uint8_t d : 7; 491 uint8_t not_used_01 : 1; 492 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 493 uint8_t not_used_01 : 1; 494 uint8_t d : 7; 495 #endif /* DRV_BYTE_ORDER */ 496 } lis3dh_int1_duration_t; 497 498 #define LIS3DH_INT2_CFG 0x34U 499 typedef struct 500 { 501 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 502 uint8_t xlie : 1; 503 uint8_t xhie : 1; 504 uint8_t ylie : 1; 505 uint8_t yhie : 1; 506 uint8_t zlie : 1; 507 uint8_t zhie : 1; 508 uint8_t _6d : 1; 509 uint8_t aoi : 1; 510 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 511 uint8_t aoi : 1; 512 uint8_t _6d : 1; 513 uint8_t zhie : 1; 514 uint8_t zlie : 1; 515 uint8_t yhie : 1; 516 uint8_t ylie : 1; 517 uint8_t xhie : 1; 518 uint8_t xlie : 1; 519 #endif /* DRV_BYTE_ORDER */ 520 } lis3dh_int2_cfg_t; 521 522 #define LIS3DH_INT2_SRC 0x35U 523 typedef struct 524 { 525 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 526 uint8_t xl : 1; 527 uint8_t xh : 1; 528 uint8_t yl : 1; 529 uint8_t yh : 1; 530 uint8_t zl : 1; 531 uint8_t zh : 1; 532 uint8_t ia : 1; 533 uint8_t not_used_01 : 1; 534 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 535 uint8_t not_used_01 : 1; 536 uint8_t ia : 1; 537 uint8_t zh : 1; 538 uint8_t zl : 1; 539 uint8_t yh : 1; 540 uint8_t yl : 1; 541 uint8_t xh : 1; 542 uint8_t xl : 1; 543 #endif /* DRV_BYTE_ORDER */ 544 } lis3dh_int2_src_t; 545 546 #define LIS3DH_INT2_THS 0x36U 547 typedef struct 548 { 549 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 550 uint8_t ths : 7; 551 uint8_t not_used_01 : 1; 552 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 553 uint8_t not_used_01 : 1; 554 uint8_t ths : 7; 555 #endif /* DRV_BYTE_ORDER */ 556 } lis3dh_int2_ths_t; 557 558 #define LIS3DH_INT2_DURATION 0x37U 559 typedef struct 560 { 561 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 562 uint8_t d : 7; 563 uint8_t not_used_01 : 1; 564 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 565 uint8_t not_used_01 : 1; 566 uint8_t d : 7; 567 #endif /* DRV_BYTE_ORDER */ 568 } lis3dh_int2_duration_t; 569 570 #define LIS3DH_CLICK_CFG 0x38U 571 typedef struct 572 { 573 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 574 uint8_t xs : 1; 575 uint8_t xd : 1; 576 uint8_t ys : 1; 577 uint8_t yd : 1; 578 uint8_t zs : 1; 579 uint8_t zd : 1; 580 uint8_t not_used_01 : 2; 581 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 582 uint8_t not_used_01 : 2; 583 uint8_t zd : 1; 584 uint8_t zs : 1; 585 uint8_t yd : 1; 586 uint8_t ys : 1; 587 uint8_t xd : 1; 588 uint8_t xs : 1; 589 #endif /* DRV_BYTE_ORDER */ 590 } lis3dh_click_cfg_t; 591 592 #define LIS3DH_CLICK_SRC 0x39U 593 typedef struct 594 { 595 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 596 uint8_t x : 1; 597 uint8_t y : 1; 598 uint8_t z : 1; 599 uint8_t sign : 1; 600 uint8_t sclick : 1; 601 uint8_t dclick : 1; 602 uint8_t ia : 1; 603 uint8_t not_used_01 : 1; 604 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 605 uint8_t not_used_01 : 1; 606 uint8_t ia : 1; 607 uint8_t dclick : 1; 608 uint8_t sclick : 1; 609 uint8_t sign : 1; 610 uint8_t z : 1; 611 uint8_t y : 1; 612 uint8_t x : 1; 613 #endif /* DRV_BYTE_ORDER */ 614 } lis3dh_click_src_t; 615 616 #define LIS3DH_CLICK_THS 0x3AU 617 typedef struct 618 { 619 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 620 uint8_t ths : 7; 621 uint8_t lir_click : 1; 622 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 623 uint8_t lir_click : 1; 624 uint8_t ths : 7; 625 #endif /* DRV_BYTE_ORDER */ 626 } lis3dh_click_ths_t; 627 628 #define LIS3DH_TIME_LIMIT 0x3BU 629 typedef struct 630 { 631 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 632 uint8_t tli : 7; 633 uint8_t not_used_01 : 1; 634 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 635 uint8_t not_used_01 : 1; 636 uint8_t tli : 7; 637 #endif /* DRV_BYTE_ORDER */ 638 } lis3dh_time_limit_t; 639 640 #define LIS3DH_TIME_LATENCY 0x3CU 641 typedef struct 642 { 643 uint8_t tla : 8; 644 } lis3dh_time_latency_t; 645 646 #define LIS3DH_TIME_WINDOW 0x3DU 647 typedef struct 648 { 649 uint8_t tw : 8; 650 } lis3dh_time_window_t; 651 652 #define LIS3DH_ACT_THS 0x3EU 653 typedef struct 654 { 655 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 656 uint8_t acth : 7; 657 uint8_t not_used_01 : 1; 658 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 659 uint8_t not_used_01 : 1; 660 uint8_t acth : 7; 661 #endif /* DRV_BYTE_ORDER */ 662 } lis3dh_act_ths_t; 663 664 #define LIS3DH_ACT_DUR 0x3FU 665 typedef struct 666 { 667 uint8_t actd : 8; 668 } lis3dh_act_dur_t; 669 670 /** 671 * @defgroup LIS3DH_Register_Union 672 * @brief This union group all the registers having a bit-field 673 * description. 674 * This union is useful but it's not needed by the driver. 675 * 676 * REMOVING this union you are compliant with: 677 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 678 * 679 * @{ 680 * 681 */ 682 typedef union 683 { 684 lis3dh_status_reg_aux_t status_reg_aux; 685 lis3dh_ctrl_reg0_t ctrl_reg0; 686 lis3dh_temp_cfg_reg_t temp_cfg_reg; 687 lis3dh_ctrl_reg1_t ctrl_reg1; 688 lis3dh_ctrl_reg2_t ctrl_reg2; 689 lis3dh_ctrl_reg3_t ctrl_reg3; 690 lis3dh_ctrl_reg4_t ctrl_reg4; 691 lis3dh_ctrl_reg5_t ctrl_reg5; 692 lis3dh_ctrl_reg6_t ctrl_reg6; 693 lis3dh_status_reg_t status_reg; 694 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg; 695 lis3dh_fifo_src_reg_t fifo_src_reg; 696 lis3dh_int1_cfg_t int1_cfg; 697 lis3dh_int1_src_t int1_src; 698 lis3dh_int1_ths_t int1_ths; 699 lis3dh_int1_duration_t int1_duration; 700 lis3dh_int2_cfg_t int2_cfg; 701 lis3dh_int2_src_t int2_src; 702 lis3dh_int2_ths_t int2_ths; 703 lis3dh_int2_duration_t int2_duration; 704 lis3dh_click_cfg_t click_cfg; 705 lis3dh_click_src_t click_src; 706 lis3dh_click_ths_t click_ths; 707 lis3dh_time_limit_t time_limit; 708 lis3dh_time_latency_t time_latency; 709 lis3dh_time_window_t time_window; 710 lis3dh_act_ths_t act_ths; 711 lis3dh_act_dur_t act_dur; 712 bitwise_t bitwise; 713 uint8_t byte; 714 } lis3dh_reg_t; 715 716 /** 717 * @} 718 * 719 */ 720 721 #ifndef __weak 722 #define __weak __attribute__((weak)) 723 #endif /* __weak */ 724 725 /* 726 * These are the basic platform dependent I/O routines to read 727 * and write device registers connected on a standard bus. 728 * The driver keeps offering a default implementation based on function 729 * pointers to read/write routines for backward compatibility. 730 * The __weak directive allows the final application to overwrite 731 * them with a custom implementation. 732 */ 733 734 int32_t lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 735 uint16_t len); 736 int32_t lis3dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 737 uint8_t *data, 738 uint16_t len); 739 740 float_t lis3dh_from_fs2_hr_to_mg(int16_t lsb); 741 float_t lis3dh_from_fs4_hr_to_mg(int16_t lsb); 742 float_t lis3dh_from_fs8_hr_to_mg(int16_t lsb); 743 float_t lis3dh_from_fs16_hr_to_mg(int16_t lsb); 744 float_t lis3dh_from_lsb_hr_to_celsius(int16_t lsb); 745 746 float_t lis3dh_from_fs2_nm_to_mg(int16_t lsb); 747 float_t lis3dh_from_fs4_nm_to_mg(int16_t lsb); 748 float_t lis3dh_from_fs8_nm_to_mg(int16_t lsb); 749 float_t lis3dh_from_fs16_nm_to_mg(int16_t lsb); 750 float_t lis3dh_from_lsb_nm_to_celsius(int16_t lsb); 751 752 float_t lis3dh_from_fs2_lp_to_mg(int16_t lsb); 753 float_t lis3dh_from_fs4_lp_to_mg(int16_t lsb); 754 float_t lis3dh_from_fs8_lp_to_mg(int16_t lsb); 755 float_t lis3dh_from_fs16_lp_to_mg(int16_t lsb); 756 float_t lis3dh_from_lsb_lp_to_celsius(int16_t lsb); 757 758 int32_t lis3dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff); 759 int32_t lis3dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 760 761 int32_t lis3dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); 762 763 int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 764 765 int32_t lis3dh_adc_raw_get(stmdev_ctx_t *ctx, int16_t *buff); 766 767 typedef enum 768 { 769 LIS3DH_AUX_DISABLE = 0, 770 LIS3DH_AUX_ON_TEMPERATURE = 3, 771 LIS3DH_AUX_ON_PADS = 1, 772 } lis3dh_temp_en_t; 773 int32_t lis3dh_aux_adc_set(stmdev_ctx_t *ctx, lis3dh_temp_en_t val); 774 int32_t lis3dh_aux_adc_get(stmdev_ctx_t *ctx, lis3dh_temp_en_t *val); 775 776 typedef enum 777 { 778 LIS3DH_HR_12bit = 0, 779 LIS3DH_NM_10bit = 1, 780 LIS3DH_LP_8bit = 2, 781 } lis3dh_op_md_t; 782 int32_t lis3dh_operating_mode_set(stmdev_ctx_t *ctx, 783 lis3dh_op_md_t val); 784 int32_t lis3dh_operating_mode_get(stmdev_ctx_t *ctx, 785 lis3dh_op_md_t *val); 786 787 typedef enum 788 { 789 LIS3DH_POWER_DOWN = 0x00, 790 LIS3DH_ODR_1Hz = 0x01, 791 LIS3DH_ODR_10Hz = 0x02, 792 LIS3DH_ODR_25Hz = 0x03, 793 LIS3DH_ODR_50Hz = 0x04, 794 LIS3DH_ODR_100Hz = 0x05, 795 LIS3DH_ODR_200Hz = 0x06, 796 LIS3DH_ODR_400Hz = 0x07, 797 LIS3DH_ODR_1kHz620_LP = 0x08, 798 LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, 799 } lis3dh_odr_t; 800 int32_t lis3dh_data_rate_set(stmdev_ctx_t *ctx, lis3dh_odr_t val); 801 int32_t lis3dh_data_rate_get(stmdev_ctx_t *ctx, lis3dh_odr_t *val); 802 803 int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, 804 uint8_t val); 805 int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, 806 uint8_t *val); 807 808 typedef enum 809 { 810 LIS3DH_AGGRESSIVE = 0, 811 LIS3DH_STRONG = 1, 812 LIS3DH_MEDIUM = 2, 813 LIS3DH_LIGHT = 3, 814 } lis3dh_hpcf_t; 815 int32_t lis3dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, 816 lis3dh_hpcf_t val); 817 int32_t lis3dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, 818 lis3dh_hpcf_t *val); 819 820 typedef enum 821 { 822 LIS3DH_NORMAL_WITH_RST = 0, 823 LIS3DH_REFERENCE_MODE = 1, 824 LIS3DH_NORMAL = 2, 825 LIS3DH_AUTORST_ON_INT = 3, 826 } lis3dh_hpm_t; 827 int32_t lis3dh_high_pass_mode_set(stmdev_ctx_t *ctx, 828 lis3dh_hpm_t val); 829 int32_t lis3dh_high_pass_mode_get(stmdev_ctx_t *ctx, 830 lis3dh_hpm_t *val); 831 832 typedef enum 833 { 834 LIS3DH_2g = 0, 835 LIS3DH_4g = 1, 836 LIS3DH_8g = 2, 837 LIS3DH_16g = 3, 838 } lis3dh_fs_t; 839 int32_t lis3dh_full_scale_set(stmdev_ctx_t *ctx, lis3dh_fs_t val); 840 int32_t lis3dh_full_scale_get(stmdev_ctx_t *ctx, lis3dh_fs_t *val); 841 842 int32_t lis3dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 843 int32_t lis3dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); 844 845 int32_t lis3dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff); 846 int32_t lis3dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff); 847 848 int32_t lis3dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 849 850 int32_t lis3dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); 851 852 int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); 853 854 int32_t lis3dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 855 856 typedef enum 857 { 858 LIS3DH_ST_DISABLE = 0, 859 LIS3DH_ST_POSITIVE = 1, 860 LIS3DH_ST_NEGATIVE = 2, 861 } lis3dh_st_t; 862 int32_t lis3dh_self_test_set(stmdev_ctx_t *ctx, lis3dh_st_t val); 863 int32_t lis3dh_self_test_get(stmdev_ctx_t *ctx, lis3dh_st_t *val); 864 865 typedef enum 866 { 867 LIS3DH_LSB_AT_LOW_ADD = 0, 868 LIS3DH_MSB_AT_LOW_ADD = 1, 869 } lis3dh_ble_t; 870 int32_t lis3dh_data_format_set(stmdev_ctx_t *ctx, lis3dh_ble_t val); 871 int32_t lis3dh_data_format_get(stmdev_ctx_t *ctx, lis3dh_ble_t *val); 872 873 int32_t lis3dh_boot_set(stmdev_ctx_t *ctx, uint8_t val); 874 int32_t lis3dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 875 876 int32_t lis3dh_status_get(stmdev_ctx_t *ctx, 877 lis3dh_status_reg_t *val); 878 879 int32_t lis3dh_int1_gen_conf_set(stmdev_ctx_t *ctx, 880 lis3dh_int1_cfg_t *val); 881 int32_t lis3dh_int1_gen_conf_get(stmdev_ctx_t *ctx, 882 lis3dh_int1_cfg_t *val); 883 884 int32_t lis3dh_int1_gen_source_get(stmdev_ctx_t *ctx, 885 lis3dh_int1_src_t *val); 886 887 int32_t lis3dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 888 int32_t lis3dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, 889 uint8_t *val); 890 891 int32_t lis3dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val); 892 int32_t lis3dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val); 893 894 int32_t lis3dh_int2_gen_conf_set(stmdev_ctx_t *ctx, 895 lis3dh_int2_cfg_t *val); 896 int32_t lis3dh_int2_gen_conf_get(stmdev_ctx_t *ctx, 897 lis3dh_int2_cfg_t *val); 898 899 int32_t lis3dh_int2_gen_source_get(stmdev_ctx_t *ctx, 900 lis3dh_int2_src_t *val); 901 902 int32_t lis3dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 903 int32_t lis3dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, 904 uint8_t *val); 905 906 int32_t lis3dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val); 907 int32_t lis3dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val); 908 909 typedef enum 910 { 911 LIS3DH_DISC_FROM_INT_GENERATOR = 0, 912 LIS3DH_ON_INT1_GEN = 1, 913 LIS3DH_ON_INT2_GEN = 2, 914 LIS3DH_ON_TAP_GEN = 4, 915 LIS3DH_ON_INT1_INT2_GEN = 3, 916 LIS3DH_ON_INT1_TAP_GEN = 5, 917 LIS3DH_ON_INT2_TAP_GEN = 6, 918 LIS3DH_ON_INT1_INT2_TAP_GEN = 7, 919 } lis3dh_hp_t; 920 int32_t lis3dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, 921 lis3dh_hp_t val); 922 int32_t lis3dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, 923 lis3dh_hp_t *val); 924 925 int32_t lis3dh_pin_int1_config_set(stmdev_ctx_t *ctx, 926 lis3dh_ctrl_reg3_t *val); 927 int32_t lis3dh_pin_int1_config_get(stmdev_ctx_t *ctx, 928 lis3dh_ctrl_reg3_t *val); 929 930 int32_t lis3dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val); 931 int32_t lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, 932 uint8_t *val); 933 934 typedef enum 935 { 936 LIS3DH_INT2_PULSED = 0, 937 LIS3DH_INT2_LATCHED = 1, 938 } lis3dh_lir_int2_t; 939 int32_t lis3dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, 940 lis3dh_lir_int2_t val); 941 int32_t lis3dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, 942 lis3dh_lir_int2_t *val); 943 944 int32_t lis3dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val); 945 int32_t lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, 946 uint8_t *val); 947 948 typedef enum 949 { 950 LIS3DH_INT1_PULSED = 0, 951 LIS3DH_INT1_LATCHED = 1, 952 } lis3dh_lir_int1_t; 953 int32_t lis3dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, 954 lis3dh_lir_int1_t val); 955 int32_t lis3dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, 956 lis3dh_lir_int1_t *val); 957 958 int32_t lis3dh_pin_int2_config_set(stmdev_ctx_t *ctx, 959 lis3dh_ctrl_reg6_t *val); 960 int32_t lis3dh_pin_int2_config_get(stmdev_ctx_t *ctx, 961 lis3dh_ctrl_reg6_t *val); 962 963 int32_t lis3dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val); 964 int32_t lis3dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); 965 966 int32_t lis3dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); 967 int32_t lis3dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); 968 969 typedef enum 970 { 971 LIS3DH_INT1_GEN = 0, 972 LIS3DH_INT2_GEN = 1, 973 } lis3dh_tr_t; 974 int32_t lis3dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, 975 lis3dh_tr_t val); 976 int32_t lis3dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, 977 lis3dh_tr_t *val); 978 979 typedef enum 980 { 981 LIS3DH_BYPASS_MODE = 0, 982 LIS3DH_FIFO_MODE = 1, 983 LIS3DH_DYNAMIC_STREAM_MODE = 2, 984 LIS3DH_STREAM_TO_FIFO_MODE = 3, 985 } lis3dh_fm_t; 986 int32_t lis3dh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dh_fm_t val); 987 int32_t lis3dh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dh_fm_t *val); 988 989 int32_t lis3dh_fifo_status_get(stmdev_ctx_t *ctx, 990 lis3dh_fifo_src_reg_t *val); 991 992 int32_t lis3dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); 993 994 int32_t lis3dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 995 996 int32_t lis3dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 997 998 int32_t lis3dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 999 1000 int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx, 1001 lis3dh_click_cfg_t *val); 1002 int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx, 1003 lis3dh_click_cfg_t *val); 1004 1005 int32_t lis3dh_tap_source_get(stmdev_ctx_t *ctx, 1006 lis3dh_click_src_t *val); 1007 1008 int32_t lis3dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 1009 int32_t lis3dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 1010 1011 typedef enum 1012 { 1013 LIS3DH_TAP_PULSED = 0, 1014 LIS3DH_TAP_LATCHED = 1, 1015 } lis3dh_lir_click_t; 1016 int32_t lis3dh_tap_notification_mode_set(stmdev_ctx_t *ctx, 1017 lis3dh_lir_click_t val); 1018 int32_t lis3dh_tap_notification_mode_get(stmdev_ctx_t *ctx, 1019 lis3dh_lir_click_t *val); 1020 1021 int32_t lis3dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val); 1022 int32_t lis3dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 1023 1024 int32_t lis3dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val); 1025 int32_t lis3dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 1026 1027 int32_t lis3dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val); 1028 int32_t lis3dh_double_tap_timeout_get(stmdev_ctx_t *ctx, 1029 uint8_t *val); 1030 1031 int32_t lis3dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 1032 int32_t lis3dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 1033 1034 int32_t lis3dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val); 1035 int32_t lis3dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); 1036 1037 typedef enum 1038 { 1039 LIS3DH_PULL_UP_DISCONNECT = 0, 1040 LIS3DH_PULL_UP_CONNECT = 1, 1041 } lis3dh_sdo_pu_disc_t; 1042 int32_t lis3dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, 1043 lis3dh_sdo_pu_disc_t val); 1044 int32_t lis3dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, 1045 lis3dh_sdo_pu_disc_t *val); 1046 1047 typedef enum 1048 { 1049 LIS3DH_SPI_4_WIRE = 0, 1050 LIS3DH_SPI_3_WIRE = 1, 1051 } lis3dh_sim_t; 1052 int32_t lis3dh_spi_mode_set(stmdev_ctx_t *ctx, lis3dh_sim_t val); 1053 int32_t lis3dh_spi_mode_get(stmdev_ctx_t *ctx, lis3dh_sim_t *val); 1054 1055 /** 1056 * @} 1057 * 1058 */ 1059 1060 #ifdef __cplusplus 1061 } 1062 #endif 1063 1064 #endif /* LIS3DH_REGS_H */ 1065 1066 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1067
