1 /** 2 ****************************************************************************** 3 * @file lis3dhh_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis3dhh_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS3DHH_REGS_H 23 #define LIS3DHH_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS3DHH 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS3DHH_Infos 167 * @{ 168 * 169 */ 170 171 /** Device Identification (Who am I) **/ 172 #define LIS3DHH_ID 0x11U 173 174 /** 175 * @} 176 * 177 */ 178 179 #define LIS3DHH_WHO_AM_I 0x0FU 180 #define LIS3DHH_CTRL_REG1 0x20U 181 typedef struct 182 { 183 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 184 uint8_t bdu : 1; 185 uint8_t drdy_pulse : 1; 186 uint8_t sw_reset : 1; 187 uint8_t boot : 1; 188 uint8_t not_used_01 : 2; 189 uint8_t if_add_inc : 1; 190 uint8_t norm_mod_en : 1; 191 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 192 uint8_t norm_mod_en : 1; 193 uint8_t if_add_inc : 1; 194 uint8_t not_used_01 : 2; 195 uint8_t boot : 1; 196 uint8_t sw_reset : 1; 197 uint8_t drdy_pulse : 1; 198 uint8_t bdu : 1; 199 #endif /* DRV_BYTE_ORDER */ 200 } lis3dhh_ctrl_reg1_t; 201 202 #define LIS3DHH_INT1_CTRL 0x21U 203 typedef struct 204 { 205 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 206 uint8_t not_used_01 : 2; 207 uint8_t int1_ext : 1; 208 uint8_t int1_fth : 1; 209 uint8_t int1_fss5 : 1; 210 uint8_t int1_ovr : 1; 211 uint8_t int1_boot : 1; 212 uint8_t int1_drdy : 1; 213 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 214 uint8_t int1_drdy : 1; 215 uint8_t int1_boot : 1; 216 uint8_t int1_ovr : 1; 217 uint8_t int1_fss5 : 1; 218 uint8_t int1_fth : 1; 219 uint8_t int1_ext : 1; 220 uint8_t not_used_01 : 2; 221 #endif /* DRV_BYTE_ORDER */ 222 } lis3dhh_int1_ctrl_t; 223 224 #define LIS3DHH_INT2_CTRL 0x22U 225 typedef struct 226 { 227 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 228 uint8_t not_used_01 : 3; 229 uint8_t int2_fth : 1; 230 uint8_t int2_fss5 : 1; 231 uint8_t int2_ovr : 1; 232 uint8_t int2_boot : 1; 233 uint8_t int2_drdy : 1; 234 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 235 uint8_t int2_drdy : 1; 236 uint8_t int2_boot : 1; 237 uint8_t int2_ovr : 1; 238 uint8_t int2_fss5 : 1; 239 uint8_t int2_fth : 1; 240 uint8_t not_used_01 : 3; 241 #endif /* DRV_BYTE_ORDER */ 242 } lis3dhh_int2_ctrl_t; 243 244 #define LIS3DHH_CTRL_REG4 0x23U 245 typedef struct 246 { 247 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 248 uint8_t not_used_01 : 1; 249 uint8_t fifo_en : 1; 250 uint8_t pp_od : 2; 251 uint8_t st : 2; 252 uint8_t dsp : 2; 253 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 254 uint8_t dsp : 2; 255 uint8_t st : 2; 256 uint8_t pp_od : 2; 257 uint8_t fifo_en : 1; 258 uint8_t not_used_01 : 1; 259 #endif /* DRV_BYTE_ORDER */ 260 } lis3dhh_ctrl_reg4_t; 261 262 #define LIS3DHH_CTRL_REG5 0x24U 263 typedef struct 264 { 265 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 266 uint8_t fifo_spi_hs_on : 1; 267 uint8_t not_used_01 : 7; 268 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 269 uint8_t not_used_01 : 7; 270 uint8_t fifo_spi_hs_on : 1; 271 #endif /* DRV_BYTE_ORDER */ 272 } lis3dhh_ctrl_reg5_t; 273 274 #define LIS3DHH_OUT_TEMP_L 0x25U 275 #define LIS3DHH_OUT_TEMP_H 0x26U 276 #define LIS3DHH_STATUS 0x27U 277 typedef struct 278 { 279 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 280 uint8_t xda : 1; 281 uint8_t yda : 1; 282 uint8_t zda : 1; 283 uint8_t zyxda : 1; 284 uint8_t _xor : 1; 285 uint8_t yor : 1; 286 uint8_t zor : 1; 287 uint8_t zyxor : 1; 288 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 289 uint8_t zyxor : 1; 290 uint8_t zor : 1; 291 uint8_t yor : 1; 292 uint8_t _xor : 1; 293 uint8_t zyxda : 1; 294 uint8_t zda : 1; 295 uint8_t yda : 1; 296 uint8_t xda : 1; 297 #endif /* DRV_BYTE_ORDER */ 298 } lis3dhh_status_t; 299 300 #define LIS3DHH_OUT_X_L_XL 0x28U 301 #define LIS3DHH_OUT_X_H_XL 0x29U 302 #define LIS3DHH_OUT_Y_L_XL 0x2AU 303 #define LIS3DHH_OUT_Y_H_XL 0x2BU 304 #define LIS3DHH_OUT_Z_L_XL 0x2CU 305 #define LIS3DHH_OUT_Z_H_XL 0x2DU 306 #define LIS3DHH_FIFO_CTRL 0x2EU 307 typedef struct 308 { 309 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 310 uint8_t fth : 5; 311 uint8_t fmode : 3; 312 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 313 uint8_t fmode : 3; 314 uint8_t fth : 5; 315 #endif /* DRV_BYTE_ORDER */ 316 } lis3dhh_fifo_ctrl_t; 317 318 #define LIS3DHH_FIFO_SRC 0x2FU 319 typedef struct 320 { 321 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 322 uint8_t fss : 6; 323 uint8_t ovrn : 1; 324 uint8_t fth : 1; 325 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 326 uint8_t fth : 1; 327 uint8_t ovrn : 1; 328 uint8_t fss : 6; 329 #endif /* DRV_BYTE_ORDER */ 330 } lis3dhh_fifo_src_t; 331 332 /** 333 * @defgroup LIS3DHH_Register_Union 334 * @brief This union group all the registers having a bit-field 335 * description. 336 * This union is useful but it's not needed by the driver. 337 * 338 * REMOVING this union you are compliant with: 339 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 340 * 341 * @{ 342 * 343 */ 344 typedef union 345 { 346 lis3dhh_ctrl_reg1_t ctrl_reg1; 347 lis3dhh_int1_ctrl_t int1_ctrl; 348 lis3dhh_int2_ctrl_t int2_ctrl; 349 lis3dhh_ctrl_reg4_t ctrl_reg4; 350 lis3dhh_ctrl_reg5_t ctrl_reg5; 351 lis3dhh_status_t status; 352 lis3dhh_fifo_ctrl_t fifo_ctrl; 353 lis3dhh_fifo_src_t fifo_src; 354 bitwise_t bitwise; 355 uint8_t byte; 356 } lis3dhh_reg_t; 357 358 /** 359 * @} 360 * 361 */ 362 363 #ifndef __weak 364 #define __weak __attribute__((weak)) 365 #endif /* __weak */ 366 367 /* 368 * These are the basic platform dependent I/O routines to read 369 * and write device registers connected on a standard bus. 370 * The driver keeps offering a default implementation based on function 371 * pointers to read/write routines for backward compatibility. 372 * The __weak directive allows the final application to overwrite 373 * them with a custom implementation. 374 */ 375 376 int32_t lis3dhh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 377 uint8_t *data, 378 uint16_t len); 379 int32_t lis3dhh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 380 uint8_t *data, 381 uint16_t len); 382 383 float_t lis3dhh_from_lsb_to_mg(int16_t lsb); 384 float_t lis3dhh_from_lsb_to_celsius(int16_t lsb); 385 386 int32_t lis3dhh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 387 int32_t lis3dhh_block_data_update_get(const stmdev_ctx_t *ctx, 388 uint8_t *val); 389 390 typedef enum 391 { 392 LIS3DHH_POWER_DOWN = 0, 393 LIS3DHH_1kHz1 = 1, 394 } lis3dhh_norm_mod_en_t; 395 int32_t lis3dhh_data_rate_set(const stmdev_ctx_t *ctx, 396 lis3dhh_norm_mod_en_t val); 397 int32_t lis3dhh_data_rate_get(const stmdev_ctx_t *ctx, 398 lis3dhh_norm_mod_en_t *val); 399 400 int32_t lis3dhh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 401 int32_t lis3dhh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 402 403 int32_t lis3dhh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 404 405 int32_t lis3dhh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 406 407 int32_t lis3dhh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 408 409 int32_t lis3dhh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 410 int32_t lis3dhh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 411 412 int32_t lis3dhh_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 413 int32_t lis3dhh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 414 415 typedef enum 416 { 417 LIS3DHH_ST_DISABLE = 0, 418 LIS3DHH_ST_POSITIVE = 1, 419 LIS3DHH_ST_NEGATIVE = 2, 420 } lis3dhh_st_t; 421 int32_t lis3dhh_self_test_set(const stmdev_ctx_t *ctx, lis3dhh_st_t val); 422 int32_t lis3dhh_self_test_get(const stmdev_ctx_t *ctx, lis3dhh_st_t *val); 423 424 typedef enum 425 { 426 LIS3DHH_LINEAR_PHASE_440Hz = 0, 427 LIS3DHH_LINEAR_PHASE_235Hz = 1, 428 LIS3DHH_NO_LINEAR_PHASE_440Hz = 2, 429 LIS3DHH_NO_LINEAR_PHASE_235Hz = 3, 430 } lis3dhh_dsp_t; 431 int32_t lis3dhh_filter_config_set(const stmdev_ctx_t *ctx, 432 lis3dhh_dsp_t val); 433 int32_t lis3dhh_filter_config_get(const stmdev_ctx_t *ctx, 434 lis3dhh_dsp_t *val); 435 436 int32_t lis3dhh_status_get(const stmdev_ctx_t *ctx, lis3dhh_status_t *val); 437 438 typedef enum 439 { 440 LIS3DHH_LATCHED = 0, 441 LIS3DHH_PULSED = 1, 442 } lis3dhh_drdy_pulse_t; 443 int32_t lis3dhh_drdy_notification_mode_set(const stmdev_ctx_t *ctx, 444 lis3dhh_drdy_pulse_t val); 445 int32_t lis3dhh_drdy_notification_mode_get(const stmdev_ctx_t *ctx, 446 lis3dhh_drdy_pulse_t *val); 447 448 449 typedef enum 450 { 451 LIS3DHH_PIN_AS_INTERRUPT = 0, 452 LIS3DHH_PIN_AS_TRIGGER = 1, 453 } lis3dhh_int1_ext_t; 454 int32_t lis3dhh_int1_mode_set(const stmdev_ctx_t *ctx, 455 lis3dhh_int1_ext_t val); 456 int32_t lis3dhh_int1_mode_get(const stmdev_ctx_t *ctx, 457 lis3dhh_int1_ext_t *val); 458 459 460 int32_t lis3dhh_fifo_threshold_on_int1_set(const stmdev_ctx_t *ctx, 461 uint8_t val); 462 int32_t lis3dhh_fifo_threshold_on_int1_get(const stmdev_ctx_t *ctx, 463 uint8_t *val); 464 465 int32_t lis3dhh_fifo_full_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 466 int32_t lis3dhh_fifo_full_on_int1_get(const stmdev_ctx_t *ctx, 467 uint8_t *val); 468 469 int32_t lis3dhh_fifo_ovr_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 470 int32_t lis3dhh_fifo_ovr_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 471 472 int32_t lis3dhh_boot_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 473 int32_t lis3dhh_boot_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 474 475 int32_t lis3dhh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 476 int32_t lis3dhh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 477 478 int32_t lis3dhh_fifo_threshold_on_int2_set(const stmdev_ctx_t *ctx, 479 uint8_t val); 480 int32_t lis3dhh_fifo_threshold_on_int2_get(const stmdev_ctx_t *ctx, 481 uint8_t *val); 482 483 int32_t lis3dhh_fifo_full_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 484 int32_t lis3dhh_fifo_full_on_int2_get(const stmdev_ctx_t *ctx, 485 uint8_t *val); 486 487 int32_t lis3dhh_fifo_ovr_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 488 int32_t lis3dhh_fifo_ovr_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); 489 490 int32_t lis3dhh_boot_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 491 int32_t lis3dhh_boot_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); 492 493 int32_t lis3dhh_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 494 int32_t lis3dhh_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); 495 496 typedef enum 497 { 498 LIS3DHH_ALL_PUSH_PULL = 0, 499 LIS3DHH_INT1_OD_INT2_PP = 1, 500 LIS3DHH_INT1_PP_INT2_OD = 2, 501 LIS3DHH_ALL_OPEN_DRAIN = 3, 502 } lis3dhh_pp_od_t; 503 int32_t lis3dhh_pin_mode_set(const stmdev_ctx_t *ctx, lis3dhh_pp_od_t val); 504 int32_t lis3dhh_pin_mode_get(const stmdev_ctx_t *ctx, lis3dhh_pp_od_t *val); 505 506 int32_t lis3dhh_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); 507 int32_t lis3dhh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); 508 509 int32_t lis3dhh_fifo_block_spi_hs_set(const stmdev_ctx_t *ctx, uint8_t val); 510 int32_t lis3dhh_fifo_block_spi_hs_get(const stmdev_ctx_t *ctx, 511 uint8_t *val); 512 513 int32_t lis3dhh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 514 int32_t lis3dhh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 515 516 typedef enum 517 { 518 LIS3DHH_BYPASS_MODE = 0, 519 LIS3DHH_FIFO_MODE = 1, 520 LIS3DHH_STREAM_TO_FIFO_MODE = 3, 521 LIS3DHH_BYPASS_TO_STREAM_MODE = 4, 522 LIS3DHH_DYNAMIC_STREAM_MODE = 6, 523 } lis3dhh_fmode_t; 524 int32_t lis3dhh_fifo_mode_set(const stmdev_ctx_t *ctx, lis3dhh_fmode_t val); 525 int32_t lis3dhh_fifo_mode_get(const stmdev_ctx_t *ctx, 526 lis3dhh_fmode_t *val); 527 528 int32_t lis3dhh_fifo_status_get(const stmdev_ctx_t *ctx, 529 lis3dhh_fifo_src_t *val); 530 531 int32_t lis3dhh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 532 533 int32_t lis3dhh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 534 535 int32_t lis3dhh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 536 537 int32_t lis3dhh_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val); 538 int32_t lis3dhh_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val); 539 540 /** 541 *@} 542 * 543 */ 544 545 #ifdef __cplusplus 546 } 547 #endif 548 549 #endif /* LIS3DHH_REGS_H */ 550 551 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 552
