1 /* 2 ****************************************************************************** 3 * @file lis2dux12_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis2dux12_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS2DUX12_REGS_H 23 #define LIS2DUX12_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS2DUX12 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *ctx, uint8_t reg, const uint8_t *data, uint16_t len); 113 typedef int32_t (*stmdev_read_ptr)(void *ctx, uint8_t reg, uint8_t *data, uint16_t len); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS2DUX12_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0x if SA0=1 -> 0x **/ 172 #define LIS2DUX12_I2C_ADD_L 0x31U 173 #define LIS2DUX12_I2C_ADD_H 0x33U 174 175 /** Device Identification (Who am I) **/ 176 #define LIS2DUX12_ID 0x47U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LIS2DUX12_EXT_CLK_CFG 0x08U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used0 : 7; 188 uint8_t ext_clk_en : 1; 189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 190 uint8_t ext_clk_en : 1; 191 uint8_t not_used0 : 7; 192 #endif /* DRV_BYTE_ORDER */ 193 } lis2dux12_ext_clk_cfg_t; 194 195 #define LIS2DUX12_PIN_CTRL 0x0CU 196 typedef struct 197 { 198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 199 uint8_t sim : 1; 200 uint8_t pp_od : 1; 201 uint8_t cs_pu_dis : 1; 202 uint8_t h_lactive : 1; 203 uint8_t pd_dis_int1 : 1; 204 uint8_t pd_dis_int2 : 1; 205 uint8_t sda_pu_en : 1; 206 uint8_t sdo_pu_en : 1; 207 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 208 uint8_t sdo_pu_en : 1; 209 uint8_t sda_pu_en : 1; 210 uint8_t pd_dis_int2 : 1; 211 uint8_t pd_dis_int1 : 1; 212 uint8_t h_lactive : 1; 213 uint8_t cs_pu_dis : 1; 214 uint8_t pp_od : 1; 215 uint8_t sim : 1; 216 #endif /* DRV_BYTE_ORDER */ 217 } lis2dux12_pin_ctrl_t; 218 219 #define LIS2DUX12_WAKE_UP_DUR_EXT 0x0EU 220 typedef struct 221 { 222 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 223 uint8_t not_used0 : 4; 224 uint8_t wu_dur_extended : 1; 225 uint8_t not_used1 : 3; 226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 227 uint8_t not_used1 : 3; 228 uint8_t wu_dur_extended : 1; 229 uint8_t not_used0 : 4; 230 #endif /* DRV_BYTE_ORDER */ 231 } lis2dux12_wake_up_dur_ext_t; 232 233 #define LIS2DUX12_WHO_AM_I 0x0FU 234 typedef struct 235 { 236 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 237 uint8_t id : 8; 238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 239 uint8_t id : 8; 240 #endif /* DRV_BYTE_ORDER */ 241 } lis2dux12_who_am_i_t; 242 243 #define LIS2DUX12_CTRL1 0x10U 244 typedef struct 245 { 246 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 247 uint8_t wu_z_en : 1; 248 uint8_t wu_y_en : 1; 249 uint8_t wu_x_en : 1; 250 uint8_t drdy_pulsed : 1; 251 uint8_t if_add_inc : 1; 252 uint8_t sw_reset : 1; 253 uint8_t int1_on_res : 1; 254 uint8_t smart_power_en : 1; 255 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 256 uint8_t smart_power_en : 1; 257 uint8_t int1_on_res : 1; 258 uint8_t sw_reset : 1; 259 uint8_t if_add_inc : 1; 260 uint8_t drdy_pulsed : 1; 261 uint8_t wu_x_en : 1; 262 uint8_t wu_y_en : 1; 263 uint8_t wu_z_en : 1; 264 #endif /* DRV_BYTE_ORDER */ 265 } lis2dux12_ctrl1_t; 266 267 #define LIS2DUX12_CTRL2 0x11U 268 typedef struct 269 { 270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 271 uint8_t not_used0 : 3; 272 uint8_t int1_drdy : 1; 273 uint8_t int1_fifo_ovr : 1; 274 uint8_t int1_fifo_th : 1; 275 uint8_t int1_fifo_full : 1; 276 uint8_t int1_boot : 1; 277 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 278 uint8_t int1_boot : 1; 279 uint8_t int1_fifo_full : 1; 280 uint8_t int1_fifo_th : 1; 281 uint8_t int1_fifo_ovr : 1; 282 uint8_t int1_drdy : 1; 283 uint8_t not_used0 : 3; 284 #endif /* DRV_BYTE_ORDER */ 285 } lis2dux12_ctrl2_t; 286 287 #define LIS2DUX12_CTRL3 0x12U 288 typedef struct 289 { 290 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 291 uint8_t st_sign_x : 1; 292 uint8_t st_sign_y : 1; 293 uint8_t hp_en : 1; 294 uint8_t int2_drdy : 1; 295 uint8_t int2_fifo_ovr : 1; 296 uint8_t int2_fifo_th : 1; 297 uint8_t int2_fifo_full : 1; 298 uint8_t int2_boot : 1; 299 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 300 uint8_t int2_boot : 1; 301 uint8_t int2_fifo_full : 1; 302 uint8_t int2_fifo_th : 1; 303 uint8_t int2_fifo_ovr : 1; 304 uint8_t int2_drdy : 1; 305 uint8_t hp_en : 1; 306 uint8_t st_sign_y : 1; 307 uint8_t st_sign_x : 1; 308 #endif /* DRV_BYTE_ORDER */ 309 } lis2dux12_ctrl3_t; 310 311 #define LIS2DUX12_CTRL4 0x13U 312 typedef struct 313 { 314 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 315 uint8_t boot : 1; 316 uint8_t soc : 1; 317 uint8_t not_used0 : 1; 318 uint8_t fifo_en : 1; 319 uint8_t emb_func_en : 1; 320 uint8_t bdu : 1; 321 uint8_t inact_odr : 2; 322 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 323 uint8_t inact_odr : 2; 324 uint8_t bdu : 1; 325 uint8_t emb_func_en : 1; 326 uint8_t fifo_en : 1; 327 uint8_t not_used0 : 1; 328 uint8_t soc : 1; 329 uint8_t boot : 1; 330 #endif /* DRV_BYTE_ORDER */ 331 } lis2dux12_ctrl4_t; 332 333 #define LIS2DUX12_CTRL5 0x14U 334 typedef struct 335 { 336 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 337 uint8_t fs : 2; 338 uint8_t bw : 2; 339 uint8_t odr : 4; 340 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 341 uint8_t odr : 4; 342 uint8_t bw : 2; 343 uint8_t fs : 2; 344 #endif /* DRV_BYTE_ORDER */ 345 } lis2dux12_ctrl5_t; 346 347 #define LIS2DUX12_FIFO_CTRL 0x15U 348 typedef struct 349 { 350 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 351 uint8_t fifo_mode : 3; 352 uint8_t stop_on_fth : 1; 353 uint8_t not_used0 : 2; 354 uint8_t fifo_depth : 1; 355 uint8_t cfg_chg_en : 1; 356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 357 uint8_t cfg_chg_en : 1; 358 uint8_t fifo_depth : 1; 359 uint8_t not_used0 : 2; 360 uint8_t stop_on_fth : 1; 361 uint8_t fifo_mode : 3; 362 #endif /* DRV_BYTE_ORDER */ 363 } lis2dux12_fifo_ctrl_t; 364 365 #define LIS2DUX12_FIFO_WTM 0x16U 366 typedef struct 367 { 368 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 369 uint8_t fth : 7; 370 uint8_t xl_only_fifo : 1; 371 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 372 uint8_t xl_only_fifo : 1; 373 uint8_t fth : 7; 374 #endif /* DRV_BYTE_ORDER */ 375 } lis2dux12_fifo_wtm_t; 376 377 #define LIS2DUX12_INTERRUPT_CFG 0x17U 378 typedef struct 379 { 380 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 381 uint8_t interrupts_enable : 1; 382 uint8_t lir : 1; 383 uint8_t dis_rst_lir_all_int : 1; 384 uint8_t sleep_status_on_int : 1; 385 uint8_t not_used0 : 1; 386 uint8_t wake_ths_w : 1; 387 uint8_t not_used1 : 1; 388 uint8_t timestamp_en : 1; 389 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 390 uint8_t timestamp_en : 1; 391 uint8_t not_used1 : 1; 392 uint8_t wake_ths_w : 1; 393 uint8_t not_used0 : 1; 394 uint8_t sleep_status_on_int : 1; 395 uint8_t dis_rst_lir_all_int : 1; 396 uint8_t lir : 1; 397 uint8_t interrupts_enable : 1; 398 #endif /* DRV_BYTE_ORDER */ 399 } lis2dux12_interrupt_cfg_t; 400 401 #define LIS2DUX12_SIXD 0x18U 402 typedef struct 403 { 404 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 405 uint8_t not_used0 : 5; 406 uint8_t d6d_ths : 2; 407 uint8_t d4d_en : 1; 408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 409 uint8_t d4d_en : 1; 410 uint8_t d6d_ths : 2; 411 uint8_t not_used0 : 5; 412 #endif /* DRV_BYTE_ORDER */ 413 } lis2dux12_sixd_t; 414 415 #define LIS2DUX12_WAKE_UP_THS 0x1CU 416 typedef struct 417 { 418 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 419 uint8_t wk_ths : 6; 420 uint8_t sleep_on : 1; 421 uint8_t not_used0 : 1; 422 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 423 uint8_t not_used0 : 1; 424 uint8_t sleep_on : 1; 425 uint8_t wk_ths : 6; 426 #endif /* DRV_BYTE_ORDER */ 427 } lis2dux12_wake_up_ths_t; 428 429 #define LIS2DUX12_WAKE_UP_DUR 0x1DU 430 typedef struct 431 { 432 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 433 uint8_t sleep_dur : 4; 434 uint8_t st_sign_z : 1; 435 uint8_t wake_dur : 2; 436 uint8_t ff_dur : 1; 437 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 438 uint8_t ff_dur : 1; 439 uint8_t wake_dur : 2; 440 uint8_t st_sign_z : 1; 441 uint8_t sleep_dur : 4; 442 #endif /* DRV_BYTE_ORDER */ 443 } lis2dux12_wake_up_dur_t; 444 445 #define LIS2DUX12_FREE_FALL 0x1EU 446 typedef struct 447 { 448 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 449 uint8_t ff_ths : 3; 450 uint8_t ff_dur : 5; 451 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 452 uint8_t ff_dur : 5; 453 uint8_t ff_ths : 3; 454 #endif /* DRV_BYTE_ORDER */ 455 } lis2dux12_free_fall_t; 456 457 #define LIS2DUX12_MD1_CFG 0x1FU 458 typedef struct 459 { 460 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 461 uint8_t int1_emb_func : 1; 462 uint8_t int1_timestamp : 1; 463 uint8_t int1_6d : 1; 464 uint8_t int1_tap : 1; 465 uint8_t int1_ff : 1; 466 uint8_t int1_wu : 1; 467 uint8_t not_used0 : 1; 468 uint8_t int1_sleep_change : 1; 469 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 470 uint8_t int1_sleep_change : 1; 471 uint8_t not_used0 : 1; 472 uint8_t int1_wu : 1; 473 uint8_t int1_ff : 1; 474 uint8_t int1_tap : 1; 475 uint8_t int1_6d : 1; 476 uint8_t int1_timestamp : 1; 477 uint8_t int1_emb_func : 1; 478 #endif /* DRV_BYTE_ORDER */ 479 } lis2dux12_md1_cfg_t; 480 481 #define LIS2DUX12_MD2_CFG 0x20U 482 typedef struct 483 { 484 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 485 uint8_t int2_emb_func : 1; 486 uint8_t int2_timestamp : 1; 487 uint8_t int2_6d : 1; 488 uint8_t int2_tap : 1; 489 uint8_t int2_ff : 1; 490 uint8_t int2_wu : 1; 491 uint8_t not_used0 : 1; 492 uint8_t int2_sleep_change : 1; 493 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 494 uint8_t int2_sleep_change : 1; 495 uint8_t not_used0 : 1; 496 uint8_t int2_wu : 1; 497 uint8_t int2_ff : 1; 498 uint8_t int2_tap : 1; 499 uint8_t int2_6d : 1; 500 uint8_t int2_timestamp : 1; 501 uint8_t int2_emb_func : 1; 502 #endif /* DRV_BYTE_ORDER */ 503 } lis2dux12_md2_cfg_t; 504 505 #define LIS2DUX12_WAKE_UP_SRC 0x21U 506 typedef struct 507 { 508 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 509 uint8_t z_wu : 1; 510 uint8_t y_wu : 1; 511 uint8_t x_wu : 1; 512 uint8_t wu_ia : 1; 513 uint8_t sleep_state : 1; 514 uint8_t ff_ia : 1; 515 uint8_t sleep_change_ia : 1; 516 uint8_t not_used0 : 1; 517 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 518 uint8_t not_used0 : 1; 519 uint8_t sleep_change_ia : 1; 520 uint8_t ff_ia : 1; 521 uint8_t sleep_state : 1; 522 uint8_t wu_ia : 1; 523 uint8_t x_wu : 1; 524 uint8_t y_wu : 1; 525 uint8_t z_wu : 1; 526 #endif /* DRV_BYTE_ORDER */ 527 } lis2dux12_wake_up_src_t; 528 529 #define LIS2DUX12_TAP_SRC 0x22U 530 typedef struct 531 { 532 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 533 uint8_t not_used0 : 4; 534 uint8_t triple_tap_ia : 1; 535 uint8_t double_tap_ia : 1; 536 uint8_t single_tap_ia : 1; 537 uint8_t tap_ia : 1; 538 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 539 uint8_t tap_ia : 1; 540 uint8_t single_tap_ia : 1; 541 uint8_t double_tap_ia : 1; 542 uint8_t triple_tap_ia : 1; 543 uint8_t not_used0 : 4; 544 #endif /* DRV_BYTE_ORDER */ 545 } lis2dux12_tap_src_t; 546 547 #define LIS2DUX12_SIXD_SRC 0x23U 548 typedef struct 549 { 550 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 551 uint8_t xl : 1; 552 uint8_t xh : 1; 553 uint8_t yl : 1; 554 uint8_t yh : 1; 555 uint8_t zl : 1; 556 uint8_t zh : 1; 557 uint8_t d6d_ia : 1; 558 uint8_t not_used0 : 1; 559 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 560 uint8_t not_used0 : 1; 561 uint8_t d6d_ia : 1; 562 uint8_t zh : 1; 563 uint8_t zl : 1; 564 uint8_t yh : 1; 565 uint8_t yl : 1; 566 uint8_t xh : 1; 567 uint8_t xl : 1; 568 #endif /* DRV_BYTE_ORDER */ 569 } lis2dux12_sixd_src_t; 570 571 #define LIS2DUX12_ALL_INT_SRC 0x24U 572 typedef struct 573 { 574 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 575 uint8_t ff_ia_all : 1; 576 uint8_t wu_ia_all : 1; 577 uint8_t single_tap_all : 1; 578 uint8_t double_tap_all : 1; 579 uint8_t triple_tap_all : 1; 580 uint8_t d6d_ia_all : 1; 581 uint8_t sleep_change_ia_all : 1; 582 uint8_t not_used0 : 1; 583 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 584 uint8_t not_used0 : 1; 585 uint8_t sleep_change_ia_all : 1; 586 uint8_t d6d_ia_all : 1; 587 uint8_t triple_tap_all : 1; 588 uint8_t double_tap_all : 1; 589 uint8_t single_tap_all : 1; 590 uint8_t wu_ia_all : 1; 591 uint8_t ff_ia_all : 1; 592 #endif /* DRV_BYTE_ORDER */ 593 } lis2dux12_all_int_src_t; 594 595 #define LIS2DUX12_STATUS 0x25U 596 typedef struct 597 { 598 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 599 uint8_t drdy : 1; 600 uint8_t not_used0 : 4; 601 uint8_t int_global : 1; 602 uint8_t not_used1 : 2; 603 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 604 uint8_t not_used1 : 2; 605 uint8_t int_global : 1; 606 uint8_t not_used0 : 4; 607 uint8_t drdy : 1; 608 #endif /* DRV_BYTE_ORDER */ 609 } lis2dux12_status_register_t; 610 611 #define LIS2DUX12_FIFO_STATUS1 0x26U 612 typedef struct 613 { 614 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 615 uint8_t not_used0 : 6; 616 uint8_t fifo_ovr_ia : 1; 617 uint8_t fifo_wtm_ia : 1; 618 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 619 uint8_t fifo_wtm_ia : 1; 620 uint8_t fifo_ovr_ia : 1; 621 uint8_t not_used0 : 6; 622 #endif /* DRV_BYTE_ORDER */ 623 } lis2dux12_fifo_status1_t; 624 625 #define LIS2DUX12_FIFO_STATUS2 0x27U 626 typedef struct 627 { 628 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 629 uint8_t fss : 8; 630 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 631 uint8_t fss : 8; 632 #endif /* DRV_BYTE_ORDER */ 633 } lis2dux12_fifo_status2_t; 634 635 #define LIS2DUX12_OUT_X_L 0x28U 636 typedef struct 637 { 638 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 639 uint8_t outx : 8; 640 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 641 uint8_t outx : 8; 642 #endif /* DRV_BYTE_ORDER */ 643 } lis2dux12_out_x_l_t; 644 645 #define LIS2DUX12_OUT_X_H 0x29U 646 typedef struct 647 { 648 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 649 uint8_t outx : 8; 650 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 651 uint8_t outx : 8; 652 #endif /* DRV_BYTE_ORDER */ 653 } lis2dux12_out_x_h_t; 654 655 #define LIS2DUX12_OUT_Y_L 0x2AU 656 typedef struct 657 { 658 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 659 uint8_t outy : 8; 660 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 661 uint8_t outy : 8; 662 #endif /* DRV_BYTE_ORDER */ 663 } lis2dux12_out_y_l_t; 664 665 #define LIS2DUX12_OUT_Y_H 0x2BU 666 typedef struct 667 { 668 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 669 uint8_t outy : 8; 670 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 671 uint8_t outy : 8; 672 #endif /* DRV_BYTE_ORDER */ 673 } lis2dux12_out_y_h_t; 674 675 #define LIS2DUX12_OUT_Z_L 0x2CU 676 typedef struct 677 { 678 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 679 uint8_t outz : 8; 680 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 681 uint8_t outz : 8; 682 #endif /* DRV_BYTE_ORDER */ 683 } lis2dux12_out_z_l_t; 684 685 #define LIS2DUX12_OUT_Z_H 0x2DU 686 typedef struct 687 { 688 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 689 uint8_t outz : 8; 690 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 691 uint8_t outz : 8; 692 #endif /* DRV_BYTE_ORDER */ 693 } lis2dux12_out_z_h_t; 694 695 #define LIS2DUX12_OUT_T_L 0x2EU 696 typedef struct 697 { 698 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 699 uint8_t outt : 8; 700 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 701 uint8_t outt : 8; 702 #endif /* DRV_BYTE_ORDER */ 703 } lis2dux12_out_t_l_t; 704 705 #define LIS2DUX12_OUT_T_H 0x2FU 706 typedef struct 707 { 708 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 709 uint8_t outt : 8; 710 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 711 uint8_t outt : 8; 712 #endif /* DRV_BYTE_ORDER */ 713 } lis2dux12_out_t_h_t; 714 715 #define LIS2DUX12_SELF_TEST 0x32U 716 typedef struct 717 { 718 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 719 uint8_t t_dis : 1; 720 uint8_t not_used0 : 3; 721 uint8_t st : 2; 722 uint8_t not_used1 : 2; 723 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 724 uint8_t not_used1 : 2; 725 uint8_t st : 2; 726 uint8_t not_used0 : 3; 727 uint8_t t_dis : 1; 728 #endif /* DRV_BYTE_ORDER */ 729 } lis2dux12_self_test_t; 730 731 #define LIS2DUX12_I3C_IF_CTRL 0x33U 732 typedef struct 733 { 734 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 735 uint8_t bus_act_sel : 2; 736 uint8_t not_used0 : 3; 737 uint8_t asf_on : 1; 738 uint8_t dis_drstdaa : 1; 739 uint8_t not_used1 : 1; 740 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 741 uint8_t not_used1 : 1; 742 uint8_t dis_drstdaa : 1; 743 uint8_t asf_on : 1; 744 uint8_t not_used0 : 3; 745 uint8_t bus_act_sel : 2; 746 #endif /* DRV_BYTE_ORDER */ 747 } lis2dux12_i3c_if_ctrl_t; 748 749 #define LIS2DUX12_EMB_FUNC_STATUS_MAINPAGE 0x34U 750 typedef struct 751 { 752 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 753 uint8_t not_used0 : 3; 754 uint8_t is_step_det : 1; 755 uint8_t is_tilt : 1; 756 uint8_t is_sigmot : 1; 757 uint8_t not_used1 : 1; 758 uint8_t is_fsm_lc : 1; 759 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 760 uint8_t is_fsm_lc : 1; 761 uint8_t not_used1 : 1; 762 uint8_t is_sigmot : 1; 763 uint8_t is_tilt : 1; 764 uint8_t is_step_det : 1; 765 uint8_t not_used0 : 3; 766 #endif /* DRV_BYTE_ORDER */ 767 } lis2dux12_emb_func_status_mainpage_t; 768 769 #define LIS2DUX12_FSM_STATUS_MAINPAGE 0x35U 770 typedef struct 771 { 772 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 773 uint8_t is_fsm1 : 1; 774 uint8_t is_fsm2 : 1; 775 uint8_t is_fsm3 : 1; 776 uint8_t is_fsm4 : 1; 777 uint8_t is_fsm5 : 1; 778 uint8_t is_fsm6 : 1; 779 uint8_t is_fsm7 : 1; 780 uint8_t is_fsm8 : 1; 781 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 782 uint8_t is_fsm8 : 1; 783 uint8_t is_fsm7 : 1; 784 uint8_t is_fsm6 : 1; 785 uint8_t is_fsm5 : 1; 786 uint8_t is_fsm4 : 1; 787 uint8_t is_fsm3 : 1; 788 uint8_t is_fsm2 : 1; 789 uint8_t is_fsm1 : 1; 790 #endif /* DRV_BYTE_ORDER */ 791 } lis2dux12_fsm_status_mainpage_t; 792 793 #define LIS2DUX12_MLC_STATUS_MAINPAGE 0x36U 794 typedef struct 795 { 796 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 797 uint8_t is_mlc1 : 1; 798 uint8_t is_mlc2 : 1; 799 uint8_t is_mlc3 : 1; 800 uint8_t is_mlc4 : 1; 801 uint8_t not_used0 : 4; 802 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 803 uint8_t not_used0 : 4; 804 uint8_t is_mlc4 : 1; 805 uint8_t is_mlc3 : 1; 806 uint8_t is_mlc2 : 1; 807 uint8_t is_mlc1 : 1; 808 #endif /* DRV_BYTE_ORDER */ 809 } lis2dux12_mlc_status_mainpage_t; 810 811 #define LIS2DUX12_SLEEP 0x3DU 812 typedef struct 813 { 814 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 815 uint8_t deep_pd : 1; 816 uint8_t not_used0 : 7; 817 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 818 uint8_t not_used0 : 7; 819 uint8_t deep_pd : 1; 820 #endif /* DRV_BYTE_ORDER */ 821 } lis2dux12_sleep_t; 822 823 #define LIS2DUX12_EN_DEVICE_CONFIG 0x3EU 824 typedef struct 825 { 826 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 827 uint8_t soft_pd : 1; 828 uint8_t not_used0 : 7; 829 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 830 uint8_t not_used0 : 7; 831 uint8_t soft_pd : 1; 832 #endif /* DRV_BYTE_ORDER */ 833 } lis2dux12_en_device_config_t; 834 835 #define LIS2DUX12_FUNC_CFG_ACCESS 0x3FU 836 typedef struct 837 { 838 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 839 uint8_t fsm_wr_ctrl_en : 1; 840 uint8_t not_used0 : 6; 841 uint8_t emb_func_reg_access : 1; 842 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 843 uint8_t emb_func_reg_access : 1; 844 uint8_t not_used0 : 6; 845 uint8_t fsm_wr_ctrl_en : 1; 846 #endif /* DRV_BYTE_ORDER */ 847 } lis2dux12_func_cfg_access_t; 848 849 #define LIS2DUX12_FIFO_DATA_OUT_TAG 0x40U 850 typedef struct 851 { 852 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 853 uint8_t not_used0 : 3; 854 uint8_t tag_sensor : 5; 855 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 856 uint8_t tag_sensor : 5; 857 uint8_t not_used0 : 3; 858 #endif /* DRV_BYTE_ORDER */ 859 } lis2dux12_fifo_data_out_tag_t; 860 861 #define LIS2DUX12_FIFO_DATA_OUT_X_L 0x41U 862 typedef struct 863 { 864 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 865 uint8_t fifo_data_out : 8; 866 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 867 uint8_t fifo_data_out : 8; 868 #endif /* DRV_BYTE_ORDER */ 869 } lis2dux12_fifo_data_out_x_l_t; 870 871 #define LIS2DUX12_FIFO_DATA_OUT_X_H 0x42U 872 typedef struct 873 { 874 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 875 uint8_t fifo_data_out : 8; 876 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 877 uint8_t fifo_data_out : 8; 878 #endif /* DRV_BYTE_ORDER */ 879 } lis2dux12_fifo_data_out_x_h_t; 880 881 #define LIS2DUX12_FIFO_DATA_OUT_Y_L 0x43U 882 typedef struct 883 { 884 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 885 uint8_t fifo_data_out : 8; 886 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 887 uint8_t fifo_data_out : 8; 888 #endif /* DRV_BYTE_ORDER */ 889 } lis2dux12_fifo_data_out_y_l_t; 890 891 #define LIS2DUX12_FIFO_DATA_OUT_Y_H 0x44U 892 typedef struct 893 { 894 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 895 uint8_t fifo_data_out : 8; 896 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 897 uint8_t fifo_data_out : 8; 898 #endif /* DRV_BYTE_ORDER */ 899 } lis2dux12_fifo_data_out_y_h_t; 900 901 #define LIS2DUX12_FIFO_DATA_OUT_Z_L 0x45U 902 typedef struct 903 { 904 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 905 uint8_t fifo_data_out : 8; 906 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 907 uint8_t fifo_data_out : 8; 908 #endif /* DRV_BYTE_ORDER */ 909 } lis2dux12_fifo_data_out_z_l_t; 910 911 #define LIS2DUX12_FIFO_DATA_OUT_Z_H 0x46U 912 typedef struct 913 { 914 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 915 uint8_t fifo_data_out : 8; 916 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 917 uint8_t fifo_data_out : 8; 918 #endif /* DRV_BYTE_ORDER */ 919 } lis2dux12_fifo_data_out_z_h_t; 920 921 #define LIS2DUX12_FIFO_BATCH_DEC 0x47U 922 typedef struct 923 { 924 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 925 uint8_t bdr_xl : 3; 926 uint8_t dec_ts_batch : 2; 927 uint8_t not_used0 : 3; 928 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 929 uint8_t not_used0 : 3; 930 uint8_t dec_ts_batch : 2; 931 uint8_t bdr_xl : 3; 932 #endif /* DRV_BYTE_ORDER */ 933 } lis2dux12_fifo_batch_dec_t; 934 935 #define LIS2DUX12_TAP_CFG0 0x6FU 936 typedef struct 937 { 938 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 939 uint8_t not_used0 : 1; 940 uint8_t invert_t : 5; 941 uint8_t axis : 2; 942 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 943 uint8_t axis : 2; 944 uint8_t invert_t : 5; 945 uint8_t not_used0 : 1; 946 #endif /* DRV_BYTE_ORDER */ 947 } lis2dux12_tap_cfg0_t; 948 949 #define LIS2DUX12_TAP_CFG1 0x70U 950 typedef struct 951 { 952 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 953 uint8_t post_still_t : 4; 954 uint8_t pre_still_ths : 4; 955 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 956 uint8_t pre_still_ths : 4; 957 uint8_t post_still_t : 4; 958 #endif /* DRV_BYTE_ORDER */ 959 } lis2dux12_tap_cfg1_t; 960 961 #define LIS2DUX12_TAP_CFG2 0x71U 962 typedef struct 963 { 964 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 965 uint8_t wait_t : 6; 966 uint8_t post_still_t : 2; 967 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 968 uint8_t post_still_t : 2; 969 uint8_t wait_t : 6; 970 #endif /* DRV_BYTE_ORDER */ 971 } lis2dux12_tap_cfg2_t; 972 973 #define LIS2DUX12_TAP_CFG3 0x72U 974 typedef struct 975 { 976 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 977 uint8_t latency_t : 4; 978 uint8_t post_still_ths : 4; 979 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 980 uint8_t post_still_ths : 4; 981 uint8_t latency_t : 4; 982 #endif /* DRV_BYTE_ORDER */ 983 } lis2dux12_tap_cfg3_t; 984 985 #define LIS2DUX12_TAP_CFG4 0x73U 986 typedef struct 987 { 988 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 989 uint8_t peak_ths : 6; 990 uint8_t not_used0 : 1; 991 uint8_t wait_end_latency : 1; 992 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 993 uint8_t wait_end_latency : 1; 994 uint8_t not_used0 : 1; 995 uint8_t peak_ths : 6; 996 #endif /* DRV_BYTE_ORDER */ 997 } lis2dux12_tap_cfg4_t; 998 999 #define LIS2DUX12_TAP_CFG5 0x74U 1000 typedef struct 1001 { 1002 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1003 uint8_t rebound_t : 5; 1004 uint8_t single_tap_en : 1; 1005 uint8_t double_tap_en : 1; 1006 uint8_t triple_tap_en : 1; 1007 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1008 uint8_t triple_tap_en : 1; 1009 uint8_t double_tap_en : 1; 1010 uint8_t single_tap_en : 1; 1011 uint8_t rebound_t : 5; 1012 #endif /* DRV_BYTE_ORDER */ 1013 } lis2dux12_tap_cfg5_t; 1014 1015 #define LIS2DUX12_TAP_CFG6 0x75U 1016 typedef struct 1017 { 1018 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1019 uint8_t pre_still_n : 4; 1020 uint8_t pre_still_st : 4; 1021 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1022 uint8_t pre_still_st : 4; 1023 uint8_t pre_still_n : 4; 1024 #endif /* DRV_BYTE_ORDER */ 1025 } lis2dux12_tap_cfg6_t; 1026 1027 #define LIS2DUX12_TIMESTAMP0 0x7AU 1028 typedef struct 1029 { 1030 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1031 uint8_t timestamp : 8; 1032 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1033 uint8_t timestamp : 8; 1034 #endif /* DRV_BYTE_ORDER */ 1035 } lis2dux12_timestamp0_t; 1036 1037 #define LIS2DUX12_TIMESTAMP1 0x7BU 1038 typedef struct 1039 { 1040 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1041 uint8_t timestamp : 8; 1042 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1043 uint8_t timestamp : 8; 1044 #endif /* DRV_BYTE_ORDER */ 1045 } lis2dux12_timestamp1_t; 1046 1047 #define LIS2DUX12_TIMESTAMP2 0x7CU 1048 typedef struct 1049 { 1050 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1051 uint8_t timestamp : 8; 1052 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1053 uint8_t timestamp : 8; 1054 #endif /* DRV_BYTE_ORDER */ 1055 } lis2dux12_timestamp2_t; 1056 1057 #define LIS2DUX12_TIMESTAMP3 0x7DU 1058 typedef struct 1059 { 1060 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1061 uint8_t timestamp : 8; 1062 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1063 uint8_t timestamp : 8; 1064 #endif /* DRV_BYTE_ORDER */ 1065 } lis2dux12_timestamp3_t; 1066 1067 /** 1068 * @} 1069 * 1070 */ 1071 1072 /** @defgroup bitfields page embedded 1073 * @{ 1074 * 1075 */ 1076 1077 #define LIS2DUX12_PAGE_SEL 0x2U 1078 typedef struct 1079 { 1080 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1081 uint8_t not_used0 : 4; 1082 uint8_t page_sel : 4; 1083 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1084 uint8_t page_sel : 4; 1085 uint8_t not_used0 : 4; 1086 #endif /* DRV_BYTE_ORDER */ 1087 } lis2dux12_page_sel_t; 1088 1089 #define LIS2DUX12_EMB_FUNC_EN_A 0x4U 1090 typedef struct 1091 { 1092 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1093 uint8_t not_used0 : 3; 1094 uint8_t pedo_en : 1; 1095 uint8_t tilt_en : 1; 1096 uint8_t sign_motion_en : 1; 1097 uint8_t not_used1 : 1; 1098 uint8_t mlc_before_fsm_en : 1; 1099 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1100 uint8_t mlc_before_fsm_en : 1; 1101 uint8_t not_used1 : 1; 1102 uint8_t sign_motion_en : 1; 1103 uint8_t tilt_en : 1; 1104 uint8_t pedo_en : 1; 1105 uint8_t not_used0 : 3; 1106 #endif /* DRV_BYTE_ORDER */ 1107 } lis2dux12_emb_func_en_a_t; 1108 1109 #define LIS2DUX12_EMB_FUNC_EN_B 0x5U 1110 typedef struct 1111 { 1112 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1113 uint8_t fsm_en : 1; 1114 uint8_t not_used0 : 3; 1115 uint8_t mlc_en : 1; 1116 uint8_t not_used1 : 3; 1117 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1118 uint8_t not_used1 : 3; 1119 uint8_t mlc_en : 1; 1120 uint8_t not_used0 : 3; 1121 uint8_t fsm_en : 1; 1122 #endif /* DRV_BYTE_ORDER */ 1123 } lis2dux12_emb_func_en_b_t; 1124 1125 #define LIS2DUX12_EMB_FUNC_EXEC_STATUS 0x7U 1126 typedef struct 1127 { 1128 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1129 uint8_t emb_func_endop : 1; 1130 uint8_t emb_func_exec_ovr : 1; 1131 uint8_t not_used0 : 6; 1132 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1133 uint8_t not_used0 : 6; 1134 uint8_t emb_func_exec_ovr : 1; 1135 uint8_t emb_func_endop : 1; 1136 #endif /* DRV_BYTE_ORDER */ 1137 } lis2dux12_emb_func_exec_status_t; 1138 1139 #define LIS2DUX12_PAGE_ADDRESS 0x8U 1140 typedef struct 1141 { 1142 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1143 uint8_t page_addr : 8; 1144 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1145 uint8_t page_addr : 8; 1146 #endif /* DRV_BYTE_ORDER */ 1147 } lis2dux12_page_address_t; 1148 1149 #define LIS2DUX12_PAGE_VALUE 0x9U 1150 typedef struct 1151 { 1152 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1153 uint8_t page_value : 8; 1154 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1155 uint8_t page_value : 8; 1156 #endif /* DRV_BYTE_ORDER */ 1157 } lis2dux12_page_value_t; 1158 1159 #define LIS2DUX12_EMB_FUNC_INT1 0x0AU 1160 typedef struct 1161 { 1162 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1163 uint8_t not_used0 : 3; 1164 uint8_t int1_step_det : 1; 1165 uint8_t int1_tilt : 1; 1166 uint8_t int1_sig_mot : 1; 1167 uint8_t not_used1 : 1; 1168 uint8_t int1_fsm_lc : 1; 1169 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1170 uint8_t int1_fsm_lc : 1; 1171 uint8_t not_used1 : 1; 1172 uint8_t int1_sig_mot : 1; 1173 uint8_t int1_tilt : 1; 1174 uint8_t int1_step_det : 1; 1175 uint8_t not_used0 : 3; 1176 #endif /* DRV_BYTE_ORDER */ 1177 } lis2dux12_emb_func_int1_t; 1178 1179 #define LIS2DUX12_FSM_INT1 0x0BU 1180 typedef struct 1181 { 1182 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1183 uint8_t int1_fsm1 : 1; 1184 uint8_t int1_fsm2 : 1; 1185 uint8_t int1_fsm3 : 1; 1186 uint8_t int1_fsm4 : 1; 1187 uint8_t int1_fsm5 : 1; 1188 uint8_t int1_fsm6 : 1; 1189 uint8_t int1_fsm7 : 1; 1190 uint8_t int1_fsm8 : 1; 1191 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1192 uint8_t int1_fsm8 : 1; 1193 uint8_t int1_fsm7 : 1; 1194 uint8_t int1_fsm6 : 1; 1195 uint8_t int1_fsm5 : 1; 1196 uint8_t int1_fsm4 : 1; 1197 uint8_t int1_fsm3 : 1; 1198 uint8_t int1_fsm2 : 1; 1199 uint8_t int1_fsm1 : 1; 1200 #endif /* DRV_BYTE_ORDER */ 1201 } lis2dux12_fsm_int1_t; 1202 1203 #define LIS2DUX12_MLC_INT1 0x0DU 1204 typedef struct 1205 { 1206 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1207 uint8_t int1_mlc1 : 1; 1208 uint8_t int1_mlc2 : 1; 1209 uint8_t int1_mlc3 : 1; 1210 uint8_t int1_mlc4 : 1; 1211 uint8_t not_used0 : 4; 1212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1213 uint8_t not_used0 : 4; 1214 uint8_t int1_mlc4 : 1; 1215 uint8_t int1_mlc3 : 1; 1216 uint8_t int1_mlc2 : 1; 1217 uint8_t int1_mlc1 : 1; 1218 #endif /* DRV_BYTE_ORDER */ 1219 } lis2dux12_mlc_int1_t; 1220 1221 #define LIS2DUX12_EMB_FUNC_INT2 0x0EU 1222 typedef struct 1223 { 1224 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1225 uint8_t not_used0 : 3; 1226 uint8_t int2_step_det : 1; 1227 uint8_t int2_tilt : 1; 1228 uint8_t int2_sig_mot : 1; 1229 uint8_t not_used1 : 1; 1230 uint8_t int2_fsm_lc : 1; 1231 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1232 uint8_t int2_fsm_lc : 1; 1233 uint8_t not_used1 : 1; 1234 uint8_t int2_sig_mot : 1; 1235 uint8_t int2_tilt : 1; 1236 uint8_t int2_step_det : 1; 1237 uint8_t not_used0 : 3; 1238 #endif /* DRV_BYTE_ORDER */ 1239 } lis2dux12_emb_func_int2_t; 1240 1241 #define LIS2DUX12_FSM_INT2 0x0FU 1242 typedef struct 1243 { 1244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1245 uint8_t int2_fsm1 : 1; 1246 uint8_t int2_fsm2 : 1; 1247 uint8_t int2_fsm3 : 1; 1248 uint8_t int2_fsm4 : 1; 1249 uint8_t int2_fsm5 : 1; 1250 uint8_t int2_fsm6 : 1; 1251 uint8_t int2_fsm7 : 1; 1252 uint8_t int2_fsm8 : 1; 1253 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1254 uint8_t int2_fsm8 : 1; 1255 uint8_t int2_fsm7 : 1; 1256 uint8_t int2_fsm6 : 1; 1257 uint8_t int2_fsm5 : 1; 1258 uint8_t int2_fsm4 : 1; 1259 uint8_t int2_fsm3 : 1; 1260 uint8_t int2_fsm2 : 1; 1261 uint8_t int2_fsm1 : 1; 1262 #endif /* DRV_BYTE_ORDER */ 1263 } lis2dux12_fsm_int2_t; 1264 1265 #define LIS2DUX12_MLC_INT2 0x11U 1266 typedef struct 1267 { 1268 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1269 uint8_t int2_mlc1 : 1; 1270 uint8_t int2_mlc2 : 1; 1271 uint8_t int2_mlc3 : 1; 1272 uint8_t int2_mlc4 : 1; 1273 uint8_t not_used0 : 4; 1274 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1275 uint8_t not_used0 : 4; 1276 uint8_t int2_mlc4 : 1; 1277 uint8_t int2_mlc3 : 1; 1278 uint8_t int2_mlc2 : 1; 1279 uint8_t int2_mlc1 : 1; 1280 #endif /* DRV_BYTE_ORDER */ 1281 } lis2dux12_mlc_int2_t; 1282 1283 #define LIS2DUX12_EMB_FUNC_STATUS 0x12U 1284 typedef struct 1285 { 1286 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1287 uint8_t not_used0 : 3; 1288 uint8_t is_step_det : 1; 1289 uint8_t is_tilt : 1; 1290 uint8_t is_sigmot : 1; 1291 uint8_t not_used1 : 1; 1292 uint8_t is_fsm_lc : 1; 1293 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1294 uint8_t is_fsm_lc : 1; 1295 uint8_t not_used1 : 1; 1296 uint8_t is_sigmot : 1; 1297 uint8_t is_tilt : 1; 1298 uint8_t is_step_det : 1; 1299 uint8_t not_used0 : 3; 1300 #endif /* DRV_BYTE_ORDER */ 1301 } lis2dux12_emb_func_status_t; 1302 1303 #define LIS2DUX12_FSM_STATUS 0x13U 1304 typedef struct 1305 { 1306 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1307 uint8_t is_fsm1 : 1; 1308 uint8_t is_fsm2 : 1; 1309 uint8_t is_fsm3 : 1; 1310 uint8_t is_fsm4 : 1; 1311 uint8_t is_fsm5 : 1; 1312 uint8_t is_fsm6 : 1; 1313 uint8_t is_fsm7 : 1; 1314 uint8_t is_fsm8 : 1; 1315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1316 uint8_t is_fsm8 : 1; 1317 uint8_t is_fsm7 : 1; 1318 uint8_t is_fsm6 : 1; 1319 uint8_t is_fsm5 : 1; 1320 uint8_t is_fsm4 : 1; 1321 uint8_t is_fsm3 : 1; 1322 uint8_t is_fsm2 : 1; 1323 uint8_t is_fsm1 : 1; 1324 #endif /* DRV_BYTE_ORDER */ 1325 } lis2dux12_fsm_status_t; 1326 1327 #define LIS2DUX12_MLC_STATUS 0x15U 1328 typedef struct 1329 { 1330 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1331 uint8_t is_mlc1 : 1; 1332 uint8_t is_mlc2 : 1; 1333 uint8_t is_mlc3 : 1; 1334 uint8_t is_mlc4 : 1; 1335 uint8_t not_used0 : 4; 1336 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1337 uint8_t not_used0 : 4; 1338 uint8_t is_mlc4 : 1; 1339 uint8_t is_mlc3 : 1; 1340 uint8_t is_mlc2 : 1; 1341 uint8_t is_mlc1 : 1; 1342 #endif /* DRV_BYTE_ORDER */ 1343 } lis2dux12_mlc_status_t; 1344 1345 #define LIS2DUX12_PAGE_RW 0x17U 1346 typedef struct 1347 { 1348 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1349 uint8_t not_used0 : 5; 1350 uint8_t page_read : 1; 1351 uint8_t page_write : 1; 1352 uint8_t emb_func_lir : 1; 1353 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1354 uint8_t emb_func_lir : 1; 1355 uint8_t page_write : 1; 1356 uint8_t page_read : 1; 1357 uint8_t not_used0 : 5; 1358 #endif /* DRV_BYTE_ORDER */ 1359 } lis2dux12_page_rw_t; 1360 1361 #define LIS2DUX12_EMB_FUNC_FIFO_EN 0x18U 1362 typedef struct 1363 { 1364 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1365 uint8_t step_counter_fifo_en : 1; 1366 uint8_t mlc_fifo_en : 1; 1367 uint8_t mlc_filter_feature_fifo_en : 1; 1368 uint8_t fsm_fifo_en : 1; 1369 uint8_t not_used0 : 4; 1370 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1371 uint8_t not_used0 : 4; 1372 uint8_t fsm_fifo_en : 1; 1373 uint8_t mlc_filter_feature_fifo_en : 1; 1374 uint8_t mlc_fifo_en : 1; 1375 uint8_t step_counter_fifo_en : 1; 1376 #endif /* DRV_BYTE_ORDER */ 1377 } lis2dux12_emb_func_fifo_en_t; 1378 1379 #define LIS2DUX12_FSM_ENABLE 0x1AU 1380 typedef struct 1381 { 1382 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1383 uint8_t fsm1_en : 1; 1384 uint8_t fsm2_en : 1; 1385 uint8_t fsm3_en : 1; 1386 uint8_t fsm4_en : 1; 1387 uint8_t fsm5_en : 1; 1388 uint8_t fsm6_en : 1; 1389 uint8_t fsm7_en : 1; 1390 uint8_t fsm8_en : 1; 1391 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1392 uint8_t fsm8_en : 1; 1393 uint8_t fsm7_en : 1; 1394 uint8_t fsm6_en : 1; 1395 uint8_t fsm5_en : 1; 1396 uint8_t fsm4_en : 1; 1397 uint8_t fsm3_en : 1; 1398 uint8_t fsm2_en : 1; 1399 uint8_t fsm1_en : 1; 1400 #endif /* DRV_BYTE_ORDER */ 1401 } lis2dux12_fsm_enable_t; 1402 1403 #define LIS2DUX12_FSM_LONG_COUNTER_L 0x1CU 1404 typedef struct 1405 { 1406 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1407 uint8_t fsm_lc : 8; 1408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1409 uint8_t fsm_lc : 8; 1410 #endif /* DRV_BYTE_ORDER */ 1411 } lis2dux12_fsm_long_counter_l_t; 1412 1413 #define LIS2DUX12_FSM_LONG_COUNTER_H 0x1DU 1414 typedef struct 1415 { 1416 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1417 uint8_t fsm_lc : 8; 1418 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1419 uint8_t fsm_lc : 8; 1420 #endif /* DRV_BYTE_ORDER */ 1421 } lis2dux12_fsm_long_counter_h_t; 1422 1423 #define LIS2DUX12_INT_ACK_MASK 0x1FU 1424 typedef struct 1425 { 1426 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1427 uint8_t iack_mask0 : 1; 1428 uint8_t iack_mask1 : 1; 1429 uint8_t iack_mask2 : 1; 1430 uint8_t iack_mask3 : 1; 1431 uint8_t iack_mask4 : 1; 1432 uint8_t iack_mask5 : 1; 1433 uint8_t iack_mask6 : 1; 1434 uint8_t iack_mask7 : 1; 1435 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1436 uint8_t iack_mask7 : 1; 1437 uint8_t iack_mask6 : 1; 1438 uint8_t iack_mask5 : 1; 1439 uint8_t iack_mask4 : 1; 1440 uint8_t iack_mask3 : 1; 1441 uint8_t iack_mask2 : 1; 1442 uint8_t iack_mask1 : 1; 1443 uint8_t iack_mask0 : 1; 1444 #endif /* DRV_BYTE_ORDER */ 1445 } lis2dux12_int_ack_mask_t; 1446 1447 #define LIS2DUX12_FSM_OUTS1 0x20U 1448 typedef struct 1449 { 1450 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1451 uint8_t n_v : 1; 1452 uint8_t p_v : 1; 1453 uint8_t n_z : 1; 1454 uint8_t p_z : 1; 1455 uint8_t n_y : 1; 1456 uint8_t p_y : 1; 1457 uint8_t n_x : 1; 1458 uint8_t p_x : 1; 1459 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1460 uint8_t p_x : 1; 1461 uint8_t n_x : 1; 1462 uint8_t p_y : 1; 1463 uint8_t n_y : 1; 1464 uint8_t p_z : 1; 1465 uint8_t n_z : 1; 1466 uint8_t p_v : 1; 1467 uint8_t n_v : 1; 1468 #endif /* DRV_BYTE_ORDER */ 1469 } lis2dux12_fsm_outs1_t; 1470 1471 #define LIS2DUX12_FSM_OUTS2 0x21U 1472 typedef struct 1473 { 1474 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1475 uint8_t n_v : 1; 1476 uint8_t p_v : 1; 1477 uint8_t n_z : 1; 1478 uint8_t p_z : 1; 1479 uint8_t n_y : 1; 1480 uint8_t p_y : 1; 1481 uint8_t n_x : 1; 1482 uint8_t p_x : 1; 1483 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1484 uint8_t p_x : 1; 1485 uint8_t n_x : 1; 1486 uint8_t p_y : 1; 1487 uint8_t n_y : 1; 1488 uint8_t p_z : 1; 1489 uint8_t n_z : 1; 1490 uint8_t p_v : 1; 1491 uint8_t n_v : 1; 1492 #endif /* DRV_BYTE_ORDER */ 1493 } lis2dux12_fsm_outs2_t; 1494 1495 #define LIS2DUX12_FSM_OUTS3 0x22U 1496 typedef struct 1497 { 1498 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1499 uint8_t n_v : 1; 1500 uint8_t p_v : 1; 1501 uint8_t n_z : 1; 1502 uint8_t p_z : 1; 1503 uint8_t n_y : 1; 1504 uint8_t p_y : 1; 1505 uint8_t n_x : 1; 1506 uint8_t p_x : 1; 1507 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1508 uint8_t p_x : 1; 1509 uint8_t n_x : 1; 1510 uint8_t p_y : 1; 1511 uint8_t n_y : 1; 1512 uint8_t p_z : 1; 1513 uint8_t n_z : 1; 1514 uint8_t p_v : 1; 1515 uint8_t n_v : 1; 1516 #endif /* DRV_BYTE_ORDER */ 1517 } lis2dux12_fsm_outs3_t; 1518 1519 #define LIS2DUX12_FSM_OUTS4 0x23U 1520 typedef struct 1521 { 1522 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1523 uint8_t n_v : 1; 1524 uint8_t p_v : 1; 1525 uint8_t n_z : 1; 1526 uint8_t p_z : 1; 1527 uint8_t n_y : 1; 1528 uint8_t p_y : 1; 1529 uint8_t n_x : 1; 1530 uint8_t p_x : 1; 1531 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1532 uint8_t p_x : 1; 1533 uint8_t n_x : 1; 1534 uint8_t p_y : 1; 1535 uint8_t n_y : 1; 1536 uint8_t p_z : 1; 1537 uint8_t n_z : 1; 1538 uint8_t p_v : 1; 1539 uint8_t n_v : 1; 1540 #endif /* DRV_BYTE_ORDER */ 1541 } lis2dux12_fsm_outs4_t; 1542 1543 #define LIS2DUX12_FSM_OUTS5 0x24U 1544 typedef struct 1545 { 1546 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1547 uint8_t n_v : 1; 1548 uint8_t p_v : 1; 1549 uint8_t n_z : 1; 1550 uint8_t p_z : 1; 1551 uint8_t n_y : 1; 1552 uint8_t p_y : 1; 1553 uint8_t n_x : 1; 1554 uint8_t p_x : 1; 1555 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1556 uint8_t p_x : 1; 1557 uint8_t n_x : 1; 1558 uint8_t p_y : 1; 1559 uint8_t n_y : 1; 1560 uint8_t p_z : 1; 1561 uint8_t n_z : 1; 1562 uint8_t p_v : 1; 1563 uint8_t n_v : 1; 1564 #endif /* DRV_BYTE_ORDER */ 1565 } lis2dux12_fsm_outs5_t; 1566 1567 #define LIS2DUX12_FSM_OUTS6 0x25U 1568 typedef struct 1569 { 1570 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1571 uint8_t n_v : 1; 1572 uint8_t p_v : 1; 1573 uint8_t n_z : 1; 1574 uint8_t p_z : 1; 1575 uint8_t n_y : 1; 1576 uint8_t p_y : 1; 1577 uint8_t n_x : 1; 1578 uint8_t p_x : 1; 1579 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1580 uint8_t p_x : 1; 1581 uint8_t n_x : 1; 1582 uint8_t p_y : 1; 1583 uint8_t n_y : 1; 1584 uint8_t p_z : 1; 1585 uint8_t n_z : 1; 1586 uint8_t p_v : 1; 1587 uint8_t n_v : 1; 1588 #endif /* DRV_BYTE_ORDER */ 1589 } lis2dux12_fsm_outs6_t; 1590 1591 #define LIS2DUX12_FSM_OUTS7 0x26U 1592 typedef struct 1593 { 1594 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1595 uint8_t n_v : 1; 1596 uint8_t p_v : 1; 1597 uint8_t n_z : 1; 1598 uint8_t p_z : 1; 1599 uint8_t n_y : 1; 1600 uint8_t p_y : 1; 1601 uint8_t n_x : 1; 1602 uint8_t p_x : 1; 1603 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1604 uint8_t p_x : 1; 1605 uint8_t n_x : 1; 1606 uint8_t p_y : 1; 1607 uint8_t n_y : 1; 1608 uint8_t p_z : 1; 1609 uint8_t n_z : 1; 1610 uint8_t p_v : 1; 1611 uint8_t n_v : 1; 1612 #endif /* DRV_BYTE_ORDER */ 1613 } lis2dux12_fsm_outs7_t; 1614 1615 #define LIS2DUX12_FSM_OUTS8 0x27U 1616 typedef struct 1617 { 1618 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1619 uint8_t n_v : 1; 1620 uint8_t p_v : 1; 1621 uint8_t n_z : 1; 1622 uint8_t p_z : 1; 1623 uint8_t n_y : 1; 1624 uint8_t p_y : 1; 1625 uint8_t n_x : 1; 1626 uint8_t p_x : 1; 1627 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1628 uint8_t p_x : 1; 1629 uint8_t n_x : 1; 1630 uint8_t p_y : 1; 1631 uint8_t n_y : 1; 1632 uint8_t p_z : 1; 1633 uint8_t n_z : 1; 1634 uint8_t p_v : 1; 1635 uint8_t n_v : 1; 1636 #endif /* DRV_BYTE_ORDER */ 1637 } lis2dux12_fsm_outs8_t; 1638 1639 #define LIS2DUX12_STEP_COUNTER_L 0x28U 1640 typedef struct 1641 { 1642 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1643 uint8_t step : 8; 1644 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1645 uint8_t step : 8; 1646 #endif /* DRV_BYTE_ORDER */ 1647 } lis2dux12_step_counter_l_t; 1648 1649 #define LIS2DUX12_STEP_COUNTER_H 0x29U 1650 typedef struct 1651 { 1652 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1653 uint8_t step : 8; 1654 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1655 uint8_t step : 8; 1656 #endif /* DRV_BYTE_ORDER */ 1657 } lis2dux12_step_counter_h_t; 1658 1659 #define LIS2DUX12_EMB_FUNC_SRC 0x2AU 1660 typedef struct 1661 { 1662 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1663 uint8_t not_used0 : 2; 1664 uint8_t stepcounter_bit_set : 1; 1665 uint8_t step_overflow : 1; 1666 uint8_t step_count_delta_ia : 1; 1667 uint8_t step_detected : 1; 1668 uint8_t not_used1 : 1; 1669 uint8_t pedo_rst_step : 1; 1670 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1671 uint8_t pedo_rst_step : 1; 1672 uint8_t not_used1 : 1; 1673 uint8_t step_detected : 1; 1674 uint8_t step_count_delta_ia : 1; 1675 uint8_t step_overflow : 1; 1676 uint8_t stepcounter_bit_set : 1; 1677 uint8_t not_used0 : 2; 1678 #endif /* DRV_BYTE_ORDER */ 1679 } lis2dux12_emb_func_src_t; 1680 1681 #define LIS2DUX12_EMB_FUNC_INIT_A 0x2CU 1682 typedef struct 1683 { 1684 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1685 uint8_t not_used0 : 3; 1686 uint8_t step_det_init : 1; 1687 uint8_t tilt_init : 1; 1688 uint8_t sig_mot_init : 1; 1689 uint8_t not_used1 : 1; 1690 uint8_t mlc_before_fsm_init : 1; 1691 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1692 uint8_t mlc_before_fsm_init : 1; 1693 uint8_t not_used1 : 1; 1694 uint8_t sig_mot_init : 1; 1695 uint8_t tilt_init : 1; 1696 uint8_t step_det_init : 1; 1697 uint8_t not_used0 : 3; 1698 #endif /* DRV_BYTE_ORDER */ 1699 } lis2dux12_emb_func_init_a_t; 1700 1701 #define LIS2DUX12_EMB_FUNC_INIT_B 0x2DU 1702 typedef struct 1703 { 1704 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1705 uint8_t fsm_init : 1; 1706 uint8_t not_used0 : 3; 1707 uint8_t mlc_init : 1; 1708 uint8_t not_used1 : 3; 1709 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1710 uint8_t not_used1 : 3; 1711 uint8_t mlc_init : 1; 1712 uint8_t not_used0 : 3; 1713 uint8_t fsm_init : 1; 1714 #endif /* DRV_BYTE_ORDER */ 1715 } lis2dux12_emb_func_init_b_t; 1716 1717 #define LIS2DUX12_MLC1_SRC 0x34U 1718 typedef struct 1719 { 1720 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1721 uint8_t mlc1_src : 8; 1722 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1723 uint8_t mlc1_src : 8; 1724 #endif /* DRV_BYTE_ORDER */ 1725 } lis2dux12_mlc1_src_t; 1726 1727 #define LIS2DUX12_MLC2_SRC 0x35U 1728 typedef struct 1729 { 1730 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1731 uint8_t mlc2_src : 8; 1732 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1733 uint8_t mlc2_src : 8; 1734 #endif /* DRV_BYTE_ORDER */ 1735 } lis2dux12_mlc2_src_t; 1736 1737 #define LIS2DUX12_MLC3_SRC 0x36U 1738 typedef struct 1739 { 1740 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1741 uint8_t mlc3_src : 8; 1742 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1743 uint8_t mlc3_src : 8; 1744 #endif /* DRV_BYTE_ORDER */ 1745 } lis2dux12_mlc3_src_t; 1746 1747 #define LIS2DUX12_MLC4_SRC 0x37U 1748 typedef struct 1749 { 1750 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1751 uint8_t mlc4_src : 8; 1752 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1753 uint8_t mlc4_src : 8; 1754 #endif /* DRV_BYTE_ORDER */ 1755 } lis2dux12_mlc4_src_t; 1756 1757 #define LIS2DUX12_FSM_ODR 0x39U 1758 typedef struct 1759 { 1760 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1761 uint8_t not_used0 : 3; 1762 uint8_t fsm_odr : 3; 1763 uint8_t not_used1 : 2; 1764 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1765 uint8_t not_used1 : 2; 1766 uint8_t fsm_odr : 3; 1767 uint8_t not_used0 : 3; 1768 #endif /* DRV_BYTE_ORDER */ 1769 } lis2dux12_fsm_odr_t; 1770 1771 #define LIS2DUX12_MLC_ODR 0x3AU 1772 typedef struct 1773 { 1774 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1775 uint8_t not_used0 : 4; 1776 uint8_t mlc_odr : 3; 1777 uint8_t not_used1 : 1; 1778 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1779 uint8_t not_used1 : 1; 1780 uint8_t mlc_odr : 3; 1781 uint8_t not_used0 : 4; 1782 #endif /* DRV_BYTE_ORDER */ 1783 } lis2dux12_mlc_odr_t; 1784 1785 /** 1786 * @} 1787 * 1788 */ 1789 1790 /** @defgroup bitfields page pg0_emb_adv 1791 * @{ 1792 * 1793 */ 1794 #define LIS2DUX12_EMB_ADV_PG_0 0x000U 1795 1796 #define LIS2DUX12_FSM_LC_TIMEOUT_L 0x54U 1797 typedef struct 1798 { 1799 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1800 uint8_t fsm_lc_timeout : 8; 1801 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1802 uint8_t fsm_lc_timeout : 8; 1803 #endif /* DRV_BYTE_ORDER */ 1804 } lis2dux12_fsm_lc_timeout_l_t; 1805 1806 #define LIS2DUX12_FSM_LC_TIMEOUT_H 0x55U 1807 typedef struct 1808 { 1809 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1810 uint8_t fsm_lc_timeout : 8; 1811 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1812 uint8_t fsm_lc_timeout : 8; 1813 #endif /* DRV_BYTE_ORDER */ 1814 } lis2dux12_fsm_lc_timeout_h_t; 1815 1816 #define LIS2DUX12_FSM_PROGRAMS 0x56U 1817 typedef struct 1818 { 1819 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1820 uint8_t fsm_n_prog : 8; 1821 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1822 uint8_t fsm_n_prog : 8; 1823 #endif /* DRV_BYTE_ORDER */ 1824 } lis2dux12_fsm_programs_t; 1825 1826 #define LIS2DUX12_FSM_START_ADD_L 0x58U 1827 typedef struct 1828 { 1829 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1830 uint8_t fsm_start : 8; 1831 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1832 uint8_t fsm_start : 8; 1833 #endif /* DRV_BYTE_ORDER */ 1834 } lis2dux12_fsm_start_add_l_t; 1835 1836 #define LIS2DUX12_FSM_START_ADD_H 0x59U 1837 typedef struct 1838 { 1839 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1840 uint8_t fsm_start : 8; 1841 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1842 uint8_t fsm_start : 8; 1843 #endif /* DRV_BYTE_ORDER */ 1844 } lis2dux12_fsm_start_add_h_t; 1845 1846 #define LIS2DUX12_PEDO_CMD_REG 0x5DU 1847 typedef struct 1848 { 1849 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1850 uint8_t not_used0 : 2; 1851 uint8_t fp_rejection_en : 1; 1852 uint8_t carry_count_en : 1; 1853 uint8_t not_used1 : 4; 1854 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1855 uint8_t not_used1 : 4; 1856 uint8_t carry_count_en : 1; 1857 uint8_t fp_rejection_en : 1; 1858 uint8_t not_used0 : 2; 1859 #endif /* DRV_BYTE_ORDER */ 1860 } lis2dux12_pedo_cmd_reg_t; 1861 1862 #define LIS2DUX12_PEDO_DEB_STEPS_CONF 0x5EU 1863 typedef struct 1864 { 1865 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1866 uint8_t deb_step : 8; 1867 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1868 uint8_t deb_step : 8; 1869 #endif /* DRV_BYTE_ORDER */ 1870 } lis2dux12_pedo_deb_steps_conf_t; 1871 1872 #define LIS2DUX12_PEDO_SC_DELTAT_L 0xAAU 1873 typedef struct 1874 { 1875 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1876 uint8_t pd_sc : 8; 1877 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1878 uint8_t pd_sc : 8; 1879 #endif /* DRV_BYTE_ORDER */ 1880 } lis2dux12_pedo_sc_deltat_l_t; 1881 1882 #define LIS2DUX12_PEDO_SC_DELTAT_H 0xABU 1883 typedef struct 1884 { 1885 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1886 uint8_t pd_sc : 8; 1887 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1888 uint8_t pd_sc : 8; 1889 #endif /* DRV_BYTE_ORDER */ 1890 } lis2dux12_pedo_sc_deltat_h_t; 1891 1892 #define LIS2DUX12_T_SENSITIVITY_L 0xB6U 1893 typedef struct 1894 { 1895 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1896 uint8_t t_s : 8; 1897 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1898 uint8_t t_s : 8; 1899 #endif /* DRV_BYTE_ORDER */ 1900 } lis2dux12_t_sensitivity_l_t; 1901 1902 #define LIS2DUX12_T_SENSITIVITY_H 0xB7U 1903 typedef struct 1904 { 1905 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1906 uint8_t t_s : 8; 1907 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1908 uint8_t t_s : 8; 1909 #endif /* DRV_BYTE_ORDER */ 1910 } lis2dux12_t_sensitivity_h_t; 1911 1912 #define LIS2DUX12_SMART_POWER_CTRL 0xD2U 1913 typedef struct 1914 { 1915 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1916 uint8_t smart_power_ctrl_win : 4; 1917 uint8_t smart_power_ctrl_dur : 4; 1918 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1919 uint8_t smart_power_ctrl_dur : 4; 1920 uint8_t smart_power_ctrl_win : 4; 1921 #endif /* DRV_BYTE_ORDER */ 1922 } lis2dux12_smart_power_ctrl_t; 1923 1924 /** 1925 * @} 1926 * 1927 */ 1928 1929 typedef union 1930 { 1931 lis2dux12_pin_ctrl_t pin_ctrl; 1932 lis2dux12_wake_up_dur_ext_t wake_up_dur_ext; 1933 lis2dux12_who_am_i_t who_am_i; 1934 lis2dux12_ctrl1_t ctrl1; 1935 lis2dux12_ctrl2_t ctrl2; 1936 lis2dux12_ctrl3_t ctrl3; 1937 lis2dux12_ctrl4_t ctrl4; 1938 lis2dux12_ctrl5_t ctrl5; 1939 lis2dux12_fifo_ctrl_t fifo_ctrl; 1940 lis2dux12_fifo_wtm_t fifo_wtm; 1941 lis2dux12_interrupt_cfg_t interrupt_cfg; 1942 lis2dux12_sixd_t sixd; 1943 lis2dux12_wake_up_ths_t wake_up_ths; 1944 lis2dux12_wake_up_dur_t wake_up_dur; 1945 lis2dux12_free_fall_t free_fall; 1946 lis2dux12_md1_cfg_t md1_cfg; 1947 lis2dux12_md2_cfg_t md2_cfg; 1948 lis2dux12_wake_up_src_t wake_up_src; 1949 lis2dux12_tap_src_t tap_src; 1950 lis2dux12_sixd_src_t sixd_src; 1951 lis2dux12_all_int_src_t all_int_src; 1952 lis2dux12_status_register_t status; 1953 lis2dux12_fifo_status1_t fifo_status1; 1954 lis2dux12_fifo_status2_t fifo_status2; 1955 lis2dux12_out_x_l_t out_x_l; 1956 lis2dux12_out_x_h_t out_x_h; 1957 lis2dux12_out_y_l_t out_y_l; 1958 lis2dux12_out_y_h_t out_y_h; 1959 lis2dux12_out_z_l_t out_z_l; 1960 lis2dux12_out_z_h_t out_z_h; 1961 lis2dux12_out_t_l_t out_t_l; 1962 lis2dux12_out_t_h_t out_t_h; 1963 lis2dux12_self_test_t self_test; 1964 lis2dux12_i3c_if_ctrl_t i3c_if_ctrl; 1965 lis2dux12_emb_func_status_mainpage_t emb_func_status_mainpage; 1966 lis2dux12_fsm_status_mainpage_t fsm_status_mainpage; 1967 lis2dux12_mlc_status_mainpage_t mlc_status_mainpage; 1968 lis2dux12_sleep_t sleep; 1969 lis2dux12_en_device_config_t en_device_config; 1970 lis2dux12_func_cfg_access_t func_cfg_access; 1971 lis2dux12_fifo_data_out_tag_t fifo_data_out_tag; 1972 lis2dux12_fifo_data_out_x_l_t fifo_data_out_x_l; 1973 lis2dux12_fifo_data_out_x_h_t fifo_data_out_x_h; 1974 lis2dux12_fifo_data_out_y_l_t fifo_data_out_y_l; 1975 lis2dux12_fifo_data_out_y_h_t fifo_data_out_y_h; 1976 lis2dux12_fifo_data_out_z_l_t fifo_data_out_z_l; 1977 lis2dux12_fifo_data_out_z_h_t fifo_data_out_z_h; 1978 lis2dux12_fifo_batch_dec_t fifo_batch_dec; 1979 lis2dux12_tap_cfg0_t tap_cfg0; 1980 lis2dux12_tap_cfg1_t tap_cfg1; 1981 lis2dux12_tap_cfg2_t tap_cfg2; 1982 lis2dux12_tap_cfg3_t tap_cfg3; 1983 lis2dux12_tap_cfg4_t tap_cfg4; 1984 lis2dux12_tap_cfg5_t tap_cfg5; 1985 lis2dux12_tap_cfg6_t tap_cfg6; 1986 lis2dux12_timestamp0_t timestamp0; 1987 lis2dux12_timestamp1_t timestamp1; 1988 lis2dux12_timestamp2_t timestamp2; 1989 lis2dux12_timestamp3_t timestamp3; 1990 lis2dux12_page_sel_t page_sel; 1991 lis2dux12_emb_func_en_a_t emb_func_en_a; 1992 lis2dux12_emb_func_en_b_t emb_func_en_b; 1993 lis2dux12_emb_func_exec_status_t emb_func_exec_status; 1994 lis2dux12_page_address_t page_address; 1995 lis2dux12_page_value_t page_value; 1996 lis2dux12_emb_func_int1_t emb_func_int1; 1997 lis2dux12_fsm_int1_t fsm_int1; 1998 lis2dux12_mlc_int1_t mlc_int1; 1999 lis2dux12_emb_func_int2_t emb_func_int2; 2000 lis2dux12_fsm_int2_t fsm_int2; 2001 lis2dux12_mlc_int2_t mlc_int2; 2002 lis2dux12_emb_func_status_t emb_func_status; 2003 lis2dux12_fsm_status_t fsm_status; 2004 lis2dux12_mlc_status_t mlc_status; 2005 lis2dux12_page_rw_t page_rw; 2006 lis2dux12_emb_func_fifo_en_t emb_func_fifo_en; 2007 lis2dux12_fsm_enable_t fsm_enable; 2008 lis2dux12_fsm_long_counter_l_t fsm_long_counter_l; 2009 lis2dux12_fsm_long_counter_h_t fsm_long_counter_h; 2010 lis2dux12_int_ack_mask_t int_ack_mask; 2011 lis2dux12_fsm_outs1_t fsm_outs1; 2012 lis2dux12_fsm_outs2_t fsm_outs2; 2013 lis2dux12_fsm_outs3_t fsm_outs3; 2014 lis2dux12_fsm_outs4_t fsm_outs4; 2015 lis2dux12_fsm_outs5_t fsm_outs5; 2016 lis2dux12_fsm_outs6_t fsm_outs6; 2017 lis2dux12_fsm_outs7_t fsm_outs7; 2018 lis2dux12_fsm_outs8_t fsm_outs8; 2019 lis2dux12_step_counter_l_t step_counter_l; 2020 lis2dux12_step_counter_h_t step_counter_h; 2021 lis2dux12_emb_func_src_t emb_func_src; 2022 lis2dux12_emb_func_init_a_t emb_func_init_a; 2023 lis2dux12_emb_func_init_b_t emb_func_init_b; 2024 lis2dux12_mlc1_src_t mlc1_src; 2025 lis2dux12_mlc2_src_t mlc2_src; 2026 lis2dux12_mlc3_src_t mlc3_src; 2027 lis2dux12_mlc4_src_t mlc4_src; 2028 lis2dux12_fsm_odr_t fsm_odr; 2029 lis2dux12_mlc_odr_t mlc_odr; 2030 lis2dux12_fsm_lc_timeout_l_t fsm_lc_timeout_l; 2031 lis2dux12_fsm_lc_timeout_h_t fsm_lc_timeout_h; 2032 lis2dux12_fsm_programs_t fsm_programs; 2033 lis2dux12_fsm_start_add_l_t fsm_start_add_l; 2034 lis2dux12_fsm_start_add_h_t fsm_start_add_h; 2035 lis2dux12_pedo_cmd_reg_t pedo_cmd_reg; 2036 lis2dux12_pedo_deb_steps_conf_t pedo_deb_steps_conf; 2037 lis2dux12_pedo_sc_deltat_l_t pedo_sc_deltat_l; 2038 lis2dux12_pedo_sc_deltat_h_t pedo_sc_deltat_h; 2039 lis2dux12_t_sensitivity_l_t t_sensitivity_l; 2040 lis2dux12_t_sensitivity_h_t t_sensitivity_h; 2041 lis2dux12_smart_power_ctrl_t smart_power_ctrl; 2042 bitwise_t bitwise; 2043 uint8_t byte; 2044 } lis2dux12_reg_t; 2045 2046 /** 2047 * @} 2048 * 2049 */ 2050 2051 #ifndef __weak 2052 #define __weak __attribute__((weak)) 2053 #endif /* __weak */ 2054 2055 /* 2056 * These are the basic platform dependent I/O routines to read 2057 * and write device registers connected on a standard bus. 2058 * The driver keeps offering a default implementation based on function 2059 * pointers to read/write routines for backward compatibility. 2060 * The __weak directive allows the final application to overwrite 2061 * them with a custom implementation. 2062 */ 2063 2064 int32_t lis2dux12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2065 uint8_t *data, 2066 uint16_t len); 2067 int32_t lis2dux12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2068 uint8_t *data, 2069 uint16_t len); 2070 2071 float_t lis2dux12_from_fs2g_to_mg(int16_t lsb); 2072 float_t lis2dux12_from_fs4g_to_mg(int16_t lsb); 2073 float_t lis2dux12_from_fs8g_to_mg(int16_t lsb); 2074 float_t lis2dux12_from_fs16g_to_mg(int16_t lsb); 2075 float_t lis2dux12_from_lsb_to_celsius(int16_t lsb); 2076 2077 int32_t lis2dux12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); 2078 2079 typedef enum 2080 { 2081 LIS2DUX12_SENSOR_ONLY_ON = 0x00, /* Initialize the driver for sensor usage */ 2082 LIS2DUX12_BOOT = 0x01, /* Restore calib. param. (it takes 10ms) */ 2083 LIS2DUX12_RESET = 0x02, /* Reset configuration registers */ 2084 LIS2DUX12_SENSOR_EMB_FUNC_ON = 0x03, /* Initialize the driver for sensor and/or 2085 embedded functions usage (it takes 10ms) */ 2086 } lis2dux12_init_t; 2087 int32_t lis2dux12_init_set(const stmdev_ctx_t *ctx, lis2dux12_init_t val); 2088 2089 typedef struct 2090 { 2091 uint8_t sw_reset : 1; /* Restoring configuration registers */ 2092 uint8_t boot : 1; /* Restoring calibration parameters */ 2093 uint8_t drdy : 1; /* Accelerometer data ready */ 2094 uint8_t power_down : 1; /* Monitors power-down. */ 2095 } lis2dux12_status_t; 2096 int32_t lis2dux12_status_get(const stmdev_ctx_t *ctx, lis2dux12_status_t *val); 2097 2098 typedef struct 2099 { 2100 uint8_t is_step_det : 1; /* Step detected */ 2101 uint8_t is_tilt : 1; /* Tilt detected */ 2102 uint8_t is_sigmot : 1; /* Significant motion detected */ 2103 } lis2dux12_embedded_status_t; 2104 int32_t lis2dux12_embedded_status_get(const stmdev_ctx_t *ctx, lis2dux12_embedded_status_t *val); 2105 2106 typedef enum 2107 { 2108 LIS2DUX12_DRDY_LATCHED = 0x0, 2109 LIS2DUX12_DRDY_PULSED = 0x1, 2110 } lis2dux12_data_ready_mode_t; 2111 int32_t lis2dux12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t val); 2112 int32_t lis2dux12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t *val); 2113 2114 typedef enum 2115 { 2116 LIS2DUX12_OFF = 0x00, /* in power down */ 2117 LIS2DUX12_1Hz6_ULP = 0x01, /* @1Hz6 (ultra low power) */ 2118 LIS2DUX12_3Hz_ULP = 0x02, /* @3Hz (ultra low power) */ 2119 LIS2DUX12_25Hz_ULP = 0x03, /* @25Hz (ultra low power) */ 2120 LIS2DUX12_6Hz_LP = 0x04, /* @6Hz (low power) */ 2121 LIS2DUX12_12Hz5_LP = 0x05, /* @12Hz5 (low power) */ 2122 LIS2DUX12_25Hz_LP = 0x06, /* @25Hz (low power ) */ 2123 LIS2DUX12_50Hz_LP = 0x07, /* @50Hz (low power) */ 2124 LIS2DUX12_100Hz_LP = 0x08, /* @100Hz (low power) */ 2125 LIS2DUX12_200Hz_LP = 0x09, /* @200Hz (low power) */ 2126 LIS2DUX12_400Hz_LP = 0x0A, /* @400Hz (low power) */ 2127 LIS2DUX12_800Hz_LP = 0x0B, /* @800Hz (low power) */ 2128 LIS2DUX12_6Hz_HP = 0x14, /* @6Hz (high performance) */ 2129 LIS2DUX12_12Hz5_HP = 0x15, /* @12Hz5 (high performance) */ 2130 LIS2DUX12_25Hz_HP = 0x16, /* @25Hz (high performance ) */ 2131 LIS2DUX12_50Hz_HP = 0x17, /* @50Hz (high performance) */ 2132 LIS2DUX12_100Hz_HP = 0x18, /* @100Hz (high performance) */ 2133 LIS2DUX12_200Hz_HP = 0x19, /* @200Hz (high performance) */ 2134 LIS2DUX12_400Hz_HP = 0x1A, /* @400Hz (high performance) */ 2135 LIS2DUX12_800Hz_HP = 0x1B, /* @800Hz (high performance) */ 2136 LIS2DUX12_TRIG_PIN = 0x2E, /* Single-shot high latency by INT2 */ 2137 LIS2DUX12_TRIG_SW = 0x2F, /* Single-shot high latency by IF */ 2138 } lis2dux12_odr_t; 2139 2140 typedef enum 2141 { 2142 LIS2DUX12_2g = 0, 2143 LIS2DUX12_4g = 1, 2144 LIS2DUX12_8g = 2, 2145 LIS2DUX12_16g = 3, 2146 } lis2dux12_fs_t; 2147 2148 typedef enum 2149 { 2150 LIS2DUX12_ODR_div_2 = 0, 2151 LIS2DUX12_ODR_div_4 = 1, 2152 LIS2DUX12_ODR_div_8 = 2, 2153 LIS2DUX12_ODR_div_16 = 3, 2154 } lis2dux12_bw_t; 2155 2156 typedef struct 2157 { 2158 lis2dux12_odr_t odr; 2159 lis2dux12_fs_t fs; 2160 lis2dux12_bw_t bw; 2161 } lis2dux12_md_t; 2162 int32_t lis2dux12_mode_set(const stmdev_ctx_t *ctx, const lis2dux12_md_t *val); 2163 int32_t lis2dux12_mode_get(const stmdev_ctx_t *ctx, lis2dux12_md_t *val); 2164 2165 int32_t lis2dux12_temp_disable_set(const stmdev_ctx_t *ctx, uint8_t val); 2166 int32_t lis2dux12_temp_disable_get(const stmdev_ctx_t *ctx, uint8_t *val); 2167 2168 int32_t lis2dux12_trigger_sw(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md); 2169 2170 typedef struct 2171 { 2172 uint8_t drdy : 1; 2173 uint8_t timestamp : 1; 2174 uint8_t free_fall : 1; 2175 uint8_t wake_up : 1; 2176 uint8_t wake_up_z : 1; 2177 uint8_t wake_up_y : 1; 2178 uint8_t wake_up_x : 1; 2179 uint8_t single_tap : 1; 2180 uint8_t double_tap : 1; 2181 uint8_t triple_tap : 1; 2182 uint8_t six_d : 1; 2183 uint8_t six_d_xl : 1; 2184 uint8_t six_d_xh : 1; 2185 uint8_t six_d_yl : 1; 2186 uint8_t six_d_yh : 1; 2187 uint8_t six_d_zl : 1; 2188 uint8_t six_d_zh : 1; 2189 uint8_t sleep_change : 1; 2190 uint8_t sleep_state : 1; 2191 uint8_t tilt : 1; 2192 uint8_t fifo_bdr : 1; 2193 uint8_t fifo_full : 1; 2194 uint8_t fifo_ovr : 1; 2195 uint8_t fifo_th : 1; 2196 } lis2dux12_all_sources_t; 2197 int32_t lis2dux12_all_sources_get(const stmdev_ctx_t *ctx, lis2dux12_all_sources_t *val); 2198 2199 typedef struct 2200 { 2201 float_t mg[3]; 2202 int16_t raw[3]; 2203 } lis2dux12_xl_data_t; 2204 int32_t lis2dux12_xl_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md, 2205 lis2dux12_xl_data_t *data); 2206 2207 typedef struct 2208 { 2209 struct 2210 { 2211 float_t deg_c; 2212 int16_t raw; 2213 } heat; 2214 } lis2dux12_outt_data_t; 2215 int32_t lis2dux12_outt_data_get(const stmdev_ctx_t *ctx, 2216 lis2dux12_outt_data_t *data); 2217 2218 typedef enum 2219 { 2220 LIS2DUX12_XL_ST_DISABLE = 0x0, 2221 LIS2DUX12_XL_ST_POSITIVE = 0x1, 2222 LIS2DUX12_XL_ST_NEGATIVE = 0x2, 2223 } lis2dux12_xl_self_test_t; 2224 int32_t lis2dux12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2dux12_xl_self_test_t val); 2225 int32_t lis2dux12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val); 2226 int32_t lis2dux12_self_test_stop(const stmdev_ctx_t *ctx); 2227 2228 int32_t lis2dux12_enter_deep_power_down(const stmdev_ctx_t *ctx, uint8_t val); 2229 int32_t lis2dux12_exit_deep_power_down(const stmdev_ctx_t *ctx); 2230 2231 typedef enum 2232 { 2233 LIS2DUX12_I3C_BUS_AVAIL_TIME_20US = 0x0, 2234 LIS2DUX12_I3C_BUS_AVAIL_TIME_50US = 0x1, 2235 LIS2DUX12_I3C_BUS_AVAIL_TIME_1MS = 0x2, 2236 LIS2DUX12_I3C_BUS_AVAIL_TIME_25MS = 0x3, 2237 } lis2dux12_bus_act_sel_t; 2238 2239 typedef struct 2240 { 2241 lis2dux12_bus_act_sel_t bus_act_sel; 2242 uint8_t asf_on : 1; 2243 uint8_t drstdaa_en : 1; 2244 } lis2dux12_i3c_cfg_t; 2245 int32_t lis2dux12_i3c_configure_set(const stmdev_ctx_t *ctx, const lis2dux12_i3c_cfg_t *val); 2246 int32_t lis2dux12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val); 2247 2248 typedef enum 2249 { 2250 LIS2DUX12_MAIN_MEM_BANK = 0x0, 2251 LIS2DUX12_EMBED_FUNC_MEM_BANK = 0x1, 2252 } lis2dux12_mem_bank_t; 2253 int32_t lis2dux12_mem_bank_set(const stmdev_ctx_t *ctx, lis2dux12_mem_bank_t val); 2254 int32_t lis2dux12_mem_bank_get(const stmdev_ctx_t *ctx, lis2dux12_mem_bank_t *val); 2255 2256 int32_t lis2dux12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); 2257 int32_t lis2dux12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); 2258 2259 int32_t lis2dux12_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2260 int32_t lis2dux12_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2261 2262 typedef struct 2263 { 2264 uint8_t sdo_pull_up : 1; /* 1 = pull up enable */ 2265 uint8_t sda_pull_up : 1; /* 1 = pull up enable */ 2266 uint8_t cs_pull_up : 1; /* 1 = pull up enable */ 2267 uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 2268 uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ 2269 uint8_t int2_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ 2270 } lis2dux12_pin_conf_t; 2271 int32_t lis2dux12_pin_conf_set(const stmdev_ctx_t *ctx, const lis2dux12_pin_conf_t *val); 2272 int32_t lis2dux12_pin_conf_get(const stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val); 2273 2274 typedef enum 2275 { 2276 LIS2DUX12_ACTIVE_HIGH = 0x0, 2277 LIS2DUX12_ACTIVE_LOW = 0x1, 2278 } lis2dux12_int_pin_polarity_t; 2279 int32_t lis2dux12_int_pin_polarity_set(const stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t val); 2280 int32_t lis2dux12_int_pin_polarity_get(const stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t *val); 2281 2282 typedef enum 2283 { 2284 LIS2DUX12_SPI_4_WIRE = 0x0, /* SPI 4 wires */ 2285 LIS2DUX12_SPI_3_WIRE = 0x1, /* SPI 3 wires */ 2286 } lis2dux12_spi_mode; 2287 int32_t lis2dux12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dux12_spi_mode val); 2288 int32_t lis2dux12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dux12_spi_mode *val); 2289 2290 typedef struct 2291 { 2292 uint8_t int_on_res : 1; /* Interrupt on RES pin */ 2293 uint8_t drdy : 1; /* Accelerometer data ready */ 2294 uint8_t boot : 1; /* Restoring calibration parameters */ 2295 uint8_t fifo_th : 1; /* FIFO threshold reached */ 2296 uint8_t fifo_ovr : 1; /* FIFO overrun */ 2297 uint8_t fifo_full : 1; /* FIFO full */ 2298 uint8_t free_fall : 1; /* free fall event */ 2299 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 2300 uint8_t tap : 1; /* all tap event */ 2301 uint8_t wake_up : 1; /* wake up event */ 2302 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 2303 uint8_t emb_function : 1; /* Embedded Function */ 2304 uint8_t timestamp : 1; /* Timestamp */ 2305 } lis2dux12_pin_int_route_t; 2306 int32_t lis2dux12_pin_int1_route_set(const stmdev_ctx_t *ctx, 2307 const lis2dux12_pin_int_route_t *val); 2308 int32_t lis2dux12_pin_int1_route_get(const stmdev_ctx_t *ctx, 2309 lis2dux12_pin_int_route_t *val); 2310 int32_t lis2dux12_pin_int2_route_set(const stmdev_ctx_t *ctx, 2311 const lis2dux12_pin_int_route_t *val); 2312 int32_t lis2dux12_pin_int2_route_get(const stmdev_ctx_t *ctx, 2313 lis2dux12_pin_int_route_t *val); 2314 2315 typedef struct 2316 { 2317 uint8_t step_det : 1; /* route step detection event on INT pad */ 2318 uint8_t tilt : 1; /* route tilt event on INT pad */ 2319 uint8_t sig_mot : 1; /* route significant motion event on INT pad */ 2320 uint8_t fsm_lc : 1; /* route FSM long counter event on INT pad */ 2321 } lis2dux12_emb_pin_int_route_t; 2322 int32_t lis2dux12_emb_pin_int1_route_set(const stmdev_ctx_t *ctx, 2323 const lis2dux12_emb_pin_int_route_t *val); 2324 int32_t lis2dux12_emb_pin_int1_route_get(const stmdev_ctx_t *ctx, 2325 lis2dux12_emb_pin_int_route_t *val); 2326 int32_t lis2dux12_emb_pin_int2_route_set(const stmdev_ctx_t *ctx, 2327 const lis2dux12_emb_pin_int_route_t *val); 2328 int32_t lis2dux12_emb_pin_int2_route_get(const stmdev_ctx_t *ctx, 2329 lis2dux12_emb_pin_int_route_t *val); 2330 2331 typedef enum 2332 { 2333 LIS2DUX12_INT_DISABLED = 0x0, 2334 LIS2DUX12_INT_LEVEL = 0x1, 2335 LIS2DUX12_INT_LATCHED = 0x2, 2336 } lis2dux12_int_cfg_t; 2337 2338 typedef struct 2339 { 2340 lis2dux12_int_cfg_t int_cfg; 2341 uint8_t sleep_status_on_int : 1; /* route sleep_status on interrupt */ 2342 uint8_t dis_rst_lir_all_int : 1; /* disable LIR reset when reading ALL_INT_SRC */ 2343 } lis2dux12_int_config_t; 2344 int32_t lis2dux12_int_config_set(const stmdev_ctx_t *ctx, const lis2dux12_int_config_t *val); 2345 int32_t lis2dux12_int_config_get(const stmdev_ctx_t *ctx, lis2dux12_int_config_t *val); 2346 2347 typedef enum 2348 { 2349 LIS2DUX12_EMBEDDED_INT_LEVEL = 0x0, 2350 LIS2DUX12_EMBEDDED_INT_LATCHED = 0x1, 2351 } lis2dux12_embedded_int_config_t; 2352 int32_t lis2dux12_embedded_int_cfg_set(const stmdev_ctx_t *ctx, 2353 lis2dux12_embedded_int_config_t val); 2354 int32_t lis2dux12_embedded_int_cfg_get(const stmdev_ctx_t *ctx, 2355 lis2dux12_embedded_int_config_t *val); 2356 2357 typedef enum 2358 { 2359 LIS2DUX12_BYPASS_MODE = 0x0, 2360 LIS2DUX12_FIFO_MODE = 0x1, 2361 LIS2DUX12_STREAM_TO_FIFO_MODE = 0x3, 2362 LIS2DUX12_BYPASS_TO_STREAM_MODE = 0x4, 2363 LIS2DUX12_STREAM_MODE = 0x6, 2364 LIS2DUX12_BYPASS_TO_FIFO_MODE = 0x7, 2365 LIS2DUX12_FIFO_OFF = 0x8, 2366 } lis2dux12_operation_t; 2367 2368 typedef enum 2369 { 2370 LIS2DUX12_FIFO_1X = 0, 2371 LIS2DUX12_FIFO_2X = 1, 2372 } lis2dux12_store_t; 2373 2374 typedef enum 2375 { 2376 LIS2DUX12_DEC_TS_OFF = 0x0, 2377 LIS2DUX12_DEC_TS_1 = 0x1, 2378 LIS2DUX12_DEC_TS_8 = 0x2, 2379 LIS2DUX12_DEC_TS_32 = 0x3, 2380 } lis2dux12_dec_ts_t; 2381 2382 typedef enum 2383 { 2384 LIS2DUX12_BDR_XL_ODR = 0x0, 2385 LIS2DUX12_BDR_XL_ODR_DIV_2 = 0x1, 2386 LIS2DUX12_BDR_XL_ODR_DIV_4 = 0x2, 2387 LIS2DUX12_BDR_XL_ODR_DIV_8 = 0x3, 2388 LIS2DUX12_BDR_XL_ODR_DIV_16 = 0x4, 2389 LIS2DUX12_BDR_XL_ODR_DIV_32 = 0x5, 2390 LIS2DUX12_BDR_XL_ODR_DIV_64 = 0x6, 2391 LIS2DUX12_BDR_XL_ODR_OFF = 0x7, 2392 } lis2dux12_bdr_xl_t; 2393 2394 typedef struct 2395 { 2396 lis2dux12_operation_t operation; 2397 lis2dux12_store_t store; 2398 uint8_t xl_only : 1; /* only XL samples (16-bit) are stored in FIFO */ 2399 uint8_t watermark : 7; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ 2400 uint8_t cfg_change_in_fifo : 1; 2401 struct 2402 { 2403 lis2dux12_dec_ts_t dec_ts; /* decimation for timestamp batching*/ 2404 lis2dux12_bdr_xl_t bdr_xl; /* accelerometer batch data rate*/ 2405 } batch; 2406 } lis2dux12_fifo_mode_t; 2407 int32_t lis2dux12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val); 2408 int32_t lis2dux12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t *val); 2409 2410 int32_t lis2dux12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); 2411 int32_t lis2dux12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 2412 2413 typedef enum 2414 { 2415 LIS2DUX12_FIFO_EMPTY = 0x0, 2416 LIS2DUX12_XL_TEMP_TAG = 0x2, 2417 LIS2DUX12_XL_ONLY_2X_TAG = 0x3, 2418 LIS2DUX12_TIMESTAMP_TAG = 0x4, 2419 LIS2DUX12_STEP_COUNTER_TAG = 0x12, 2420 LIS2DUX12_MLC_RESULT_TAG = 0x1A, 2421 LIS2DUX12_MLC_FILTER_TAG = 0x1B, 2422 LIS2DUX12_MLC_FEATURE = 0x1C, 2423 LIS2DUX12_FSM_RESULT_TAG = 0x1D, 2424 } lis2dux12_fifo_sensor_tag_t; 2425 int32_t lis2dux12_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 2426 lis2dux12_fifo_sensor_tag_t *val); 2427 2428 int32_t lis2dux12_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2429 2430 typedef struct 2431 { 2432 uint8_t tag; 2433 struct 2434 { 2435 float_t mg[3]; 2436 int16_t raw[3]; 2437 } xl[2]; 2438 struct 2439 { 2440 float_t deg_c; 2441 int16_t raw; 2442 } heat; 2443 struct 2444 { 2445 uint32_t steps; 2446 uint32_t timestamp; 2447 } pedo; 2448 struct 2449 { 2450 uint8_t cfg_change : 1; /* 1 if ODR/BDR configuration is changed */ 2451 uint8_t odr : 4; /* ODR */ 2452 uint8_t bw : 2; /* BW */ 2453 uint8_t lp_hp : 1; /* Power: 0 for LP, 1 for HP */ 2454 uint8_t fs : 2; /* FS */ 2455 uint8_t dec_ts : 2; /* Timestamp decimator value */ 2456 uint8_t odr_xl_batch : 1; /* Accelerometer ODR is batched */ 2457 uint32_t timestamp; 2458 } cfg_chg; 2459 } lis2dux12_fifo_data_t; 2460 int32_t lis2dux12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md, 2461 const lis2dux12_fifo_mode_t *fmd, 2462 lis2dux12_fifo_data_t *data); 2463 2464 typedef struct 2465 { 2466 uint8_t false_step_rej : 1; 2467 uint8_t step_counter_enable : 1; 2468 uint8_t step_counter_in_fifo : 1; 2469 } lis2dux12_stpcnt_mode_t; 2470 int32_t lis2dux12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t val); 2471 int32_t lis2dux12_stpcnt_mode_get(const stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t *val); 2472 2473 int32_t lis2dux12_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); 2474 2475 int32_t lis2dux12_stpcnt_rst_step_set(const stmdev_ctx_t *ctx); 2476 2477 int32_t lis2dux12_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); 2478 int32_t lis2dux12_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); 2479 2480 int32_t lis2dux12_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); 2481 int32_t lis2dux12_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); 2482 2483 typedef struct 2484 { 2485 uint8_t enable : 1; 2486 uint8_t window : 1; 2487 uint8_t duration : 1; 2488 } lis2dux12_smart_power_cfg_t; 2489 int32_t lis2dux12_smart_power_set(const stmdev_ctx_t *ctx, lis2dux12_smart_power_cfg_t val); 2490 int32_t lis2dux12_smart_power_get(const stmdev_ctx_t *ctx, lis2dux12_smart_power_cfg_t *val); 2491 2492 int32_t lis2dux12_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2493 int32_t lis2dux12_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2494 int32_t lis2dux12_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2495 int32_t lis2dux12_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2496 2497 2498 int32_t lis2dux12_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val); 2499 int32_t lis2dux12_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); 2500 2501 typedef enum 2502 { 2503 LIS2DUX12_156_mg = 0x0, 2504 LIS2DUX12_219_mg = 0x1, 2505 LIS2DUX12_250_mg = 0x2, 2506 LIS2DUX12_312_mg = 0x3, 2507 LIS2DUX12_344_mg = 0x4, 2508 LIS2DUX12_406_mg = 0x5, 2509 LIS2DUX12_469_mg = 0x6, 2510 LIS2DUX12_500_mg = 0x7, 2511 } lis2dux12_ff_thresholds_t; 2512 int32_t lis2dux12_ff_thresholds_set(const stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t val); 2513 int32_t lis2dux12_ff_thresholds_get(const stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t *val); 2514 2515 typedef enum 2516 { 2517 LIS2DUX12_DEG_80 = 0x0, 2518 LIS2DUX12_DEG_70 = 0x1, 2519 LIS2DUX12_DEG_60 = 0x2, 2520 LIS2DUX12_DEG_50 = 0x3, 2521 } lis2dux12_threshold_t; 2522 2523 typedef enum 2524 { 2525 LIS2DUX12_6D = 0x0, 2526 LIS2DUX12_4D = 0x1, 2527 } lis2dux12_mode_t; 2528 2529 typedef struct 2530 { 2531 lis2dux12_threshold_t threshold; 2532 lis2dux12_mode_t mode; 2533 } lis2dux12_sixd_config_t; 2534 2535 int32_t lis2dux12_sixd_config_set(const stmdev_ctx_t *ctx, lis2dux12_sixd_config_t val); 2536 int32_t lis2dux12_sixd_config_get(const stmdev_ctx_t *ctx, lis2dux12_sixd_config_t *val); 2537 2538 typedef enum 2539 { 2540 LIS2DUX12_0_ODR = 0x000, /* 0 ODR time */ 2541 LIS2DUX12_1_ODR = 0x001, /* 1 ODR time */ 2542 LIS2DUX12_2_ODR = 0x002, /* 2 ODR time */ 2543 LIS2DUX12_3_ODR = 0x100, /* 3 ODR time */ 2544 LIS2DUX12_7_ODR = 0x101, /* 7 ODR time */ 2545 LIS2DUX12_11_ODR = 0x102, /* 11 ODR time */ 2546 LIS2DUX12_15_ODR = 0x103, /* 15 ODR time */ 2547 } lis2dux12_wake_dur_t; 2548 2549 typedef enum 2550 { 2551 LIS2DUX12_SLEEP_OFF = 0, 2552 LIS2DUX12_SLEEP_ON = 1, 2553 } lis2dux12_wake_enable_t; 2554 2555 typedef enum 2556 { 2557 LIS2DUX12_ODR_NO_CHANGE = 0, /* no odr change during inactivity state */ 2558 LIS2DUX12_ODR_1_6_HZ = 1, /* set odr to 1.6Hz during inactivity state */ 2559 LIS2DUX12_ODR_3_HZ = 1, /* set odr to 3Hz during inactivity state */ 2560 LIS2DUX12_ODR_25_HZ = 1, /* set odr to 25Hz during inactivity state */ 2561 } lis2dux12_inact_odr_t; 2562 2563 typedef struct 2564 { 2565 lis2dux12_wake_dur_t wake_dur; 2566 uint8_t sleep_dur : 4; /* 1 LSB == 512 ODR time */ 2567 uint8_t wake_ths : 7; /* wakeup threshold */ 2568 uint8_t wake_ths_weight : 1; /* 0: 1LSB = FS_XL/2^6, 1: 1LSB = FS_XL/2^8 */ 2569 lis2dux12_wake_enable_t wake_enable; 2570 lis2dux12_inact_odr_t inact_odr; 2571 } lis2dux12_wakeup_config_t; 2572 2573 int32_t lis2dux12_wakeup_config_set(const stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t val); 2574 int32_t lis2dux12_wakeup_config_get(const stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t *val); 2575 2576 typedef enum 2577 { 2578 LIS2DUX12_TAP_NONE = 0x0, /* No axis */ 2579 LIS2DUX12_TAP_ON_X = 0x1, /* Detect tap on X axis */ 2580 LIS2DUX12_TAP_ON_Y = 0x2, /* Detect tap on Y axis */ 2581 LIS2DUX12_TAP_ON_Z = 0x3, /* Detect tap on Z axis */ 2582 } lis2dux12_axis_t; 2583 2584 typedef struct 2585 { 2586 lis2dux12_axis_t axis; 2587 uint8_t inverted_peak_time : 5; /* 1 LSB == 1 sample */ 2588 uint8_t pre_still_ths : 4; /* 1 LSB == 62.5 mg */ 2589 uint8_t post_still_ths : 4; /* 1 LSB == 62.5 mg */ 2590 uint8_t post_still_time : 6; /* samples num during stationary condition */ 2591 uint8_t shock_wait_time : 6; /* samples num during shock condition */ 2592 uint8_t latency : 4; /* samples max num between taps */ 2593 uint8_t wait_end_latency : 1; /* wait end of latency time to generate tap events */ 2594 uint8_t peak_ths : 6; /* 1 LSB == 62.5 mg */ 2595 uint8_t rebound : 5; /* samples num during rebound condition */ 2596 uint8_t pre_still_start : 4; /* pre still start */ 2597 uint8_t pre_still_n : 4; /* pre still n */ 2598 uint8_t single_tap_on : 1; /* enable single tap */ 2599 uint8_t double_tap_on : 1; /* enable double tap */ 2600 uint8_t triple_tap_on : 1; /* enable triple tap */ 2601 } lis2dux12_tap_config_t; 2602 2603 int32_t lis2dux12_tap_config_set(const stmdev_ctx_t *ctx, lis2dux12_tap_config_t val); 2604 int32_t lis2dux12_tap_config_get(const stmdev_ctx_t *ctx, lis2dux12_tap_config_t *val); 2605 2606 int32_t lis2dux12_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 2607 int32_t lis2dux12_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 2608 2609 int32_t lis2dux12_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 2610 2611 int32_t lis2dux12_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, 2612 uint8_t *val); 2613 2614 int32_t lis2dux12_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2615 int32_t lis2dux12_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2616 2617 typedef struct 2618 { 2619 lis2dux12_fsm_enable_t fsm_enable; 2620 } lis2dux12_emb_fsm_enable_t; 2621 int32_t lis2dux12_fsm_enable_set(const stmdev_ctx_t *ctx, 2622 lis2dux12_emb_fsm_enable_t *val); 2623 int32_t lis2dux12_fsm_enable_get(const stmdev_ctx_t *ctx, 2624 lis2dux12_emb_fsm_enable_t *val); 2625 2626 int32_t lis2dux12_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 2627 int32_t lis2dux12_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 2628 2629 int32_t lis2dux12_fsm_status_get(const stmdev_ctx_t *ctx, 2630 lis2dux12_fsm_status_mainpage_t *val); 2631 int32_t lis2dux12_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val); 2632 2633 typedef enum 2634 { 2635 LIS2DUX12_ODR_FSM_12Hz5 = 0, 2636 LIS2DUX12_ODR_FSM_25Hz = 1, 2637 LIS2DUX12_ODR_FSM_50Hz = 2, 2638 LIS2DUX12_ODR_FSM_100Hz = 3, 2639 LIS2DUX12_ODR_FSM_200Hz = 4, 2640 LIS2DUX12_ODR_FSM_400Hz = 5, 2641 LIS2DUX12_ODR_FSM_800Hz = 6, 2642 } lis2dux12_fsm_val_odr_t; 2643 int32_t lis2dux12_fsm_data_rate_set(const stmdev_ctx_t *ctx, 2644 lis2dux12_fsm_val_odr_t val); 2645 int32_t lis2dux12_fsm_data_rate_get(const stmdev_ctx_t *ctx, 2646 lis2dux12_fsm_val_odr_t *val); 2647 2648 int32_t lis2dux12_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); 2649 int32_t lis2dux12_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 2650 2651 int32_t lis2dux12_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2652 int32_t lis2dux12_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2653 2654 int32_t lis2dux12_long_cnt_int_value_set(const stmdev_ctx_t *ctx, 2655 uint16_t val); 2656 int32_t lis2dux12_long_cnt_int_value_get(const stmdev_ctx_t *ctx, 2657 uint16_t *val); 2658 2659 int32_t lis2dux12_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val); 2660 int32_t lis2dux12_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val); 2661 2662 int32_t lis2dux12_fsm_start_address_set(const stmdev_ctx_t *ctx, 2663 uint16_t val); 2664 int32_t lis2dux12_fsm_start_address_get(const stmdev_ctx_t *ctx, 2665 uint16_t *val); 2666 2667 typedef enum 2668 { 2669 LIS2DUX12_MLC_OFF = 0, 2670 LIS2DUX12_MLC_ON = 1, 2671 LIS2DUX12_MLC_ON_BEFORE_FSM = 2, 2672 } lis2dux12_mlc_mode_t; 2673 int32_t lis2dux12_mlc_set(const stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val); 2674 int32_t lis2dux12_mlc_get(const stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t *val); 2675 2676 int32_t lis2dux12_mlc_status_get(const stmdev_ctx_t *ctx, 2677 lis2dux12_mlc_status_mainpage_t *val); 2678 2679 int32_t lis2dux12_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2680 2681 typedef enum 2682 { 2683 LIS2DUX12_ODR_PRGS_12Hz5 = 0, 2684 LIS2DUX12_ODR_PRGS_25Hz = 1, 2685 LIS2DUX12_ODR_PRGS_50Hz = 2, 2686 LIS2DUX12_ODR_PRGS_100Hz = 3, 2687 LIS2DUX12_ODR_PRGS_200Hz = 4, 2688 } lis2dux12_mlc_odr_val_t; 2689 int32_t lis2dux12_mlc_data_rate_set(const stmdev_ctx_t *ctx, 2690 lis2dux12_mlc_odr_val_t val); 2691 int32_t lis2dux12_mlc_data_rate_get(const stmdev_ctx_t *ctx, 2692 lis2dux12_mlc_odr_val_t *val); 2693 2694 int32_t lis2dux12_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2695 int32_t lis2dux12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2696 2697 #ifdef __cplusplus 2698 } 2699 #endif 2700 2701 #endif /* LIS2DUX12_REGS_H */ 2702 2703 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2704
