1 /** 2 ****************************************************************************** 3 * @file lis2dtw12_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis2dtw12_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS2DTW12_REGS_H 23 #define LIS2DTW12_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS2DTW12 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS2DTW12_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ 172 #define LIS2DTW12_I2C_ADD_L 0x31U 173 #define LIS2DTW12_I2C_ADD_H 0x33U 174 175 /** Device Identification (Who am I) **/ 176 #define LIS2DTW12_ID 0x44U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LIS2DTW12_OUT_T_L 0x0DU 184 #define LIS2DTW12_OUT_T_H 0x0EU 185 #define LIS2DTW12_WHO_AM_I 0x0FU 186 #define LIS2DTW12_CTRL1 0x20U 187 typedef struct 188 { 189 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 190 uint8_t lp_mode : 2; 191 uint8_t mode : 2; 192 uint8_t odr : 4; 193 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 194 uint8_t odr : 4; 195 uint8_t mode : 2; 196 uint8_t lp_mode : 2; 197 #endif /* DRV_BYTE_ORDER */ 198 } lis2dtw12_ctrl1_t; 199 200 #define LIS2DTW12_CTRL2 0x21U 201 typedef struct 202 { 203 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 204 uint8_t sim : 1; 205 uint8_t i2c_disable : 1; 206 uint8_t if_add_inc : 1; 207 uint8_t bdu : 1; 208 uint8_t cs_pu_disc : 1; 209 uint8_t not_used_01 : 1; 210 uint8_t soft_reset : 1; 211 uint8_t boot : 1; 212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 213 uint8_t boot : 1; 214 uint8_t soft_reset : 1; 215 uint8_t not_used_01 : 1; 216 uint8_t cs_pu_disc : 1; 217 uint8_t bdu : 1; 218 uint8_t if_add_inc : 1; 219 uint8_t i2c_disable : 1; 220 uint8_t sim : 1; 221 #endif /* DRV_BYTE_ORDER */ 222 } lis2dtw12_ctrl2_t; 223 224 #define LIS2DTW12_CTRL3 0x22U 225 typedef struct 226 { 227 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 228 uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */ 229 uint8_t not_used_01 : 1; 230 uint8_t h_lactive : 1; 231 uint8_t lir : 1; 232 uint8_t pp_od : 1; 233 uint8_t st : 2; 234 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 235 uint8_t st : 2; 236 uint8_t pp_od : 1; 237 uint8_t lir : 1; 238 uint8_t h_lactive : 1; 239 uint8_t not_used_01 : 1; 240 uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */ 241 #endif /* DRV_BYTE_ORDER */ 242 } lis2dtw12_ctrl3_t; 243 244 #define LIS2DTW12_CTRL4_INT1_PAD_CTRL 0x23U 245 typedef struct 246 { 247 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 248 uint8_t int1_drdy : 1; 249 uint8_t int1_fth : 1; 250 uint8_t int1_diff5 : 1; 251 uint8_t int1_tap : 1; 252 uint8_t int1_ff : 1; 253 uint8_t int1_wu : 1; 254 uint8_t int1_single_tap : 1; 255 uint8_t int1_6d : 1; 256 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 257 uint8_t int1_6d : 1; 258 uint8_t int1_single_tap : 1; 259 uint8_t int1_wu : 1; 260 uint8_t int1_ff : 1; 261 uint8_t int1_tap : 1; 262 uint8_t int1_diff5 : 1; 263 uint8_t int1_fth : 1; 264 uint8_t int1_drdy : 1; 265 #endif /* DRV_BYTE_ORDER */ 266 267 } lis2dtw12_ctrl4_int1_pad_ctrl_t; 268 269 #define LIS2DTW12_CTRL5_INT2_PAD_CTRL 0x24U 270 typedef struct 271 { 272 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 273 uint8_t int2_drdy : 1; 274 uint8_t int2_fth : 1; 275 uint8_t int2_diff5 : 1; 276 uint8_t int2_ovr : 1; 277 uint8_t int2_drdy_t : 1; 278 uint8_t int2_boot : 1; 279 uint8_t int2_sleep_chg : 1; 280 uint8_t int2_sleep_state : 1; 281 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 282 uint8_t int2_sleep_state : 1; 283 uint8_t int2_sleep_chg : 1; 284 uint8_t int2_boot : 1; 285 uint8_t int2_drdy_t : 1; 286 uint8_t int2_ovr : 1; 287 uint8_t int2_diff5 : 1; 288 uint8_t int2_fth : 1; 289 uint8_t int2_drdy : 1; 290 #endif /* DRV_BYTE_ORDER */ 291 292 } lis2dtw12_ctrl5_int2_pad_ctrl_t; 293 294 #define LIS2DTW12_CTRL6 0x25U 295 typedef struct 296 { 297 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 298 uint8_t not_used_01 : 2; 299 uint8_t low_noise : 1; 300 uint8_t fds : 1; 301 uint8_t fs : 2; 302 uint8_t bw_filt : 2; 303 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 304 uint8_t bw_filt : 2; 305 uint8_t fs : 2; 306 uint8_t fds : 1; 307 uint8_t low_noise : 1; 308 uint8_t not_used_01 : 2; 309 #endif /* DRV_BYTE_ORDER */ 310 311 } lis2dtw12_ctrl6_t; 312 313 #define LIS2DTW12_STATUS 0x27U 314 typedef struct 315 { 316 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 317 uint8_t drdy : 1; 318 uint8_t ff_ia : 1; 319 uint8_t _6d_ia : 1; 320 uint8_t single_tap : 1; 321 uint8_t double_tap : 1; 322 uint8_t sleep_state : 1; 323 uint8_t wu_ia : 1; 324 uint8_t fifo_ths : 1; 325 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 326 uint8_t fifo_ths : 1; 327 uint8_t wu_ia : 1; 328 uint8_t sleep_state : 1; 329 uint8_t double_tap : 1; 330 uint8_t single_tap : 1; 331 uint8_t _6d_ia : 1; 332 uint8_t ff_ia : 1; 333 uint8_t drdy : 1; 334 #endif /* DRV_BYTE_ORDER */ 335 } lis2dtw12_status_t; 336 337 #define LIS2DTW12_OUT_X_L 0x28U 338 #define LIS2DTW12_OUT_X_H 0x29U 339 #define LIS2DTW12_OUT_Y_L 0x2AU 340 #define LIS2DTW12_OUT_Y_H 0x2BU 341 #define LIS2DTW12_OUT_Z_L 0x2CU 342 #define LIS2DTW12_OUT_Z_H 0x2DU 343 #define LIS2DTW12_FIFO_CTRL 0x2EU 344 typedef struct 345 { 346 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 347 uint8_t fth : 5; 348 uint8_t fmode : 3; 349 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 350 uint8_t fmode : 3; 351 uint8_t fth : 5; 352 #endif /* DRV_BYTE_ORDER */ 353 } lis2dtw12_fifo_ctrl_t; 354 355 #define LIS2DTW12_FIFO_SAMPLES 0x2FU 356 typedef struct 357 { 358 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 359 uint8_t diff : 6; 360 uint8_t fifo_ovr : 1; 361 uint8_t fifo_fth : 1; 362 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 363 uint8_t fifo_fth : 1; 364 uint8_t fifo_ovr : 1; 365 uint8_t diff : 6; 366 #endif /* DRV_BYTE_ORDER */ 367 } lis2dtw12_fifo_samples_t; 368 369 #define LIS2DTW12_TAP_THS_X 0x30U 370 typedef struct 371 { 372 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 373 uint8_t tap_thsx : 5; 374 uint8_t _6d_ths : 2; 375 uint8_t _4d_en : 1; 376 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 377 uint8_t _4d_en : 1; 378 uint8_t _6d_ths : 2; 379 uint8_t tap_thsx : 5; 380 #endif /* DRV_BYTE_ORDER */ 381 } lis2dtw12_tap_ths_x_t; 382 383 #define LIS2DTW12_TAP_THS_Y 0x31U 384 typedef struct 385 { 386 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 387 uint8_t tap_thsy : 5; 388 uint8_t tap_prior : 3; 389 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 390 uint8_t tap_prior : 3; 391 uint8_t tap_thsy : 5; 392 #endif /* DRV_BYTE_ORDER */ 393 } lis2dtw12_tap_ths_y_t; 394 395 #define LIS2DTW12_TAP_THS_Z 0x32U 396 typedef struct 397 { 398 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 399 uint8_t tap_thsz : 5; 400 uint8_t tap_z_en : 1; 401 uint8_t tap_y_en : 1; 402 uint8_t tap_x_en : 1; 403 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 404 uint8_t tap_x_en : 1; 405 uint8_t tap_y_en : 1; 406 uint8_t tap_z_en : 1; 407 uint8_t tap_thsz : 5; 408 #endif /* DRV_BYTE_ORDER */ 409 } lis2dtw12_tap_ths_z_t; 410 411 #define LIS2DTW12_INT_DUR 0x33U 412 typedef struct 413 { 414 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 415 uint8_t shock : 2; 416 uint8_t quiet : 2; 417 uint8_t latency : 4; 418 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 419 uint8_t latency : 4; 420 uint8_t quiet : 2; 421 uint8_t shock : 2; 422 #endif /* DRV_BYTE_ORDER */ 423 } lis2dtw12_int_dur_t; 424 425 #define LIS2DTW12_WAKE_UP_THS 0x34U 426 typedef struct 427 { 428 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 429 uint8_t wk_ths : 6; 430 uint8_t sleep_on : 1; 431 uint8_t single_double_tap : 1; 432 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 433 uint8_t single_double_tap : 1; 434 uint8_t sleep_on : 1; 435 uint8_t wk_ths : 6; 436 #endif /* DRV_BYTE_ORDER */ 437 } lis2dtw12_wake_up_ths_t; 438 439 #define LIS2DTW12_WAKE_UP_DUR 0x35U 440 typedef struct 441 { 442 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 443 uint8_t sleep_dur : 4; 444 uint8_t stationary : 1; 445 uint8_t wake_dur : 2; 446 uint8_t ff_dur : 1; 447 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 448 uint8_t ff_dur : 1; 449 uint8_t wake_dur : 2; 450 uint8_t stationary : 1; 451 uint8_t sleep_dur : 4; 452 #endif /* DRV_BYTE_ORDER */ 453 } lis2dtw12_wake_up_dur_t; 454 455 #define LIS2DTW12_FREE_FALL 0x36U 456 typedef struct 457 { 458 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 459 uint8_t ff_ths : 3; 460 uint8_t ff_dur : 5; 461 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 462 uint8_t ff_dur : 5; 463 uint8_t ff_ths : 3; 464 #endif /* DRV_BYTE_ORDER */ 465 } lis2dtw12_free_fall_t; 466 467 #define LIS2DTW12_STATUS_DUP 0x37U 468 typedef struct 469 { 470 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 471 uint8_t drdy : 1; 472 uint8_t ff_ia : 1; 473 uint8_t _6d_ia : 1; 474 uint8_t single_tap : 1; 475 uint8_t double_tap : 1; 476 uint8_t sleep_state_ia : 1; 477 uint8_t drdy_t : 1; 478 uint8_t ovr : 1; 479 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 480 uint8_t ovr : 1; 481 uint8_t drdy_t : 1; 482 uint8_t sleep_state_ia : 1; 483 uint8_t double_tap : 1; 484 uint8_t single_tap : 1; 485 uint8_t _6d_ia : 1; 486 uint8_t ff_ia : 1; 487 uint8_t drdy : 1; 488 #endif /* DRV_BYTE_ORDER */ 489 } lis2dtw12_status_dup_t; 490 491 #define LIS2DTW12_WAKE_UP_SRC 0x38U 492 typedef struct 493 { 494 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 495 uint8_t z_wu : 1; 496 uint8_t y_wu : 1; 497 uint8_t x_wu : 1; 498 uint8_t wu_ia : 1; 499 uint8_t sleep_state_ia : 1; 500 uint8_t ff_ia : 1; 501 uint8_t not_used_01 : 2; 502 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 503 uint8_t not_used_01 : 2; 504 uint8_t ff_ia : 1; 505 uint8_t sleep_state_ia : 1; 506 uint8_t wu_ia : 1; 507 uint8_t x_wu : 1; 508 uint8_t y_wu : 1; 509 uint8_t z_wu : 1; 510 #endif /* DRV_BYTE_ORDER */ 511 } lis2dtw12_wake_up_src_t; 512 513 #define LIS2DTW12_TAP_SRC 0x39U 514 typedef struct 515 { 516 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 517 uint8_t z_tap : 1; 518 uint8_t y_tap : 1; 519 uint8_t x_tap : 1; 520 uint8_t tap_sign : 1; 521 uint8_t double_tap : 1; 522 uint8_t single_tap : 1; 523 uint8_t tap_ia : 1; 524 uint8_t not_used_01 : 1; 525 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 526 uint8_t not_used_01 : 1; 527 uint8_t tap_ia : 1; 528 uint8_t single_tap : 1; 529 uint8_t double_tap : 1; 530 uint8_t tap_sign : 1; 531 uint8_t x_tap : 1; 532 uint8_t y_tap : 1; 533 uint8_t z_tap : 1; 534 #endif /* DRV_BYTE_ORDER */ 535 } lis2dtw12_tap_src_t; 536 537 #define LIS2DTW12_SIXD_SRC 0x3AU 538 typedef struct 539 { 540 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 541 uint8_t xl : 1; 542 uint8_t xh : 1; 543 uint8_t yl : 1; 544 uint8_t yh : 1; 545 uint8_t zl : 1; 546 uint8_t zh : 1; 547 uint8_t _6d_ia : 1; 548 uint8_t not_used_01 : 1; 549 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 550 uint8_t not_used_01 : 1; 551 uint8_t _6d_ia : 1; 552 uint8_t zh : 1; 553 uint8_t zl : 1; 554 uint8_t yh : 1; 555 uint8_t yl : 1; 556 uint8_t xh : 1; 557 uint8_t xl : 1; 558 #endif /* DRV_BYTE_ORDER */ 559 } lis2dtw12_sixd_src_t; 560 561 #define LIS2DTW12_ALL_INT_SRC 0x3BU 562 typedef struct 563 { 564 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 565 uint8_t ff_ia : 1; 566 uint8_t wu_ia : 1; 567 uint8_t single_tap : 1; 568 uint8_t double_tap : 1; 569 uint8_t _6d_ia : 1; 570 uint8_t sleep_change_ia : 1; 571 uint8_t not_used_01 : 2; 572 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 573 uint8_t not_used_01 : 2; 574 uint8_t sleep_change_ia : 1; 575 uint8_t _6d_ia : 1; 576 uint8_t double_tap : 1; 577 uint8_t single_tap : 1; 578 uint8_t wu_ia : 1; 579 uint8_t ff_ia : 1; 580 #endif /* DRV_BYTE_ORDER */ 581 } lis2dtw12_all_int_src_t; 582 583 #define LIS2DTW12_X_OFS_USR 0x3CU 584 #define LIS2DTW12_Y_OFS_USR 0x3DU 585 #define LIS2DTW12_Z_OFS_USR 0x3EU 586 #define LIS2DTW12_CTRL_REG7 0x3FU 587 typedef struct 588 { 589 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 590 uint8_t lpass_on6d : 1; 591 uint8_t hp_ref_mode : 1; 592 uint8_t usr_off_w : 1; 593 uint8_t usr_off_on_wu : 1; 594 uint8_t usr_off_on_out : 1; 595 uint8_t interrupts_enable : 1; 596 uint8_t int2_on_int1 : 1; 597 uint8_t drdy_pulsed : 1; 598 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 599 uint8_t drdy_pulsed : 1; 600 uint8_t int2_on_int1 : 1; 601 uint8_t interrupts_enable : 1; 602 uint8_t usr_off_on_out : 1; 603 uint8_t usr_off_on_wu : 1; 604 uint8_t usr_off_w : 1; 605 uint8_t hp_ref_mode : 1; 606 uint8_t lpass_on6d : 1; 607 #endif /* DRV_BYTE_ORDER */ 608 } lis2dtw12_ctrl_reg7_t; 609 610 /** 611 * @defgroup LIS2DTW12_Register_Union 612 * @brief This union group all the registers having a bit-field 613 * description. 614 * This union is useful but it's not needed by the driver. 615 * 616 * REMOVING this union you are compliant with: 617 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 618 * 619 * @{ 620 * 621 */ 622 typedef union 623 { 624 lis2dtw12_ctrl1_t ctrl1; 625 lis2dtw12_ctrl2_t ctrl2; 626 lis2dtw12_ctrl3_t ctrl3; 627 lis2dtw12_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad_ctrl; 628 lis2dtw12_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl; 629 lis2dtw12_ctrl6_t ctrl6; 630 lis2dtw12_status_t status; 631 lis2dtw12_fifo_ctrl_t fifo_ctrl; 632 lis2dtw12_fifo_samples_t fifo_samples; 633 lis2dtw12_tap_ths_x_t tap_ths_x; 634 lis2dtw12_tap_ths_y_t tap_ths_y; 635 lis2dtw12_tap_ths_z_t tap_ths_z; 636 lis2dtw12_int_dur_t int_dur; 637 lis2dtw12_wake_up_ths_t wake_up_ths; 638 lis2dtw12_wake_up_dur_t wake_up_dur; 639 lis2dtw12_free_fall_t free_fall; 640 lis2dtw12_status_dup_t status_dup; 641 lis2dtw12_wake_up_src_t wake_up_src; 642 lis2dtw12_tap_src_t tap_src; 643 lis2dtw12_sixd_src_t sixd_src; 644 lis2dtw12_all_int_src_t all_int_src; 645 lis2dtw12_ctrl_reg7_t ctrl_reg7; 646 bitwise_t bitwise; 647 uint8_t byte; 648 } lis2dtw12_reg_t; 649 650 /** 651 * @} 652 * 653 */ 654 655 #ifndef __weak 656 #define __weak __attribute__((weak)) 657 #endif /* __weak */ 658 659 /* 660 * These are the basic platform dependent I/O routines to read 661 * and write device registers connected on a standard bus. 662 * The driver keeps offering a default implementation based on function 663 * pointers to read/write routines for backward compatibility. 664 * The __weak directive allows the final application to overwrite 665 * them with a custom implementation. 666 */ 667 668 int32_t lis2dtw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 669 uint8_t *data, 670 uint16_t len); 671 int32_t lis2dtw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 672 uint8_t *data, 673 uint16_t len); 674 675 float_t lis2dtw12_from_fs2_to_mg(int16_t lsb); 676 float_t lis2dtw12_from_fs4_to_mg(int16_t lsb); 677 float_t lis2dtw12_from_fs8_to_mg(int16_t lsb); 678 float_t lis2dtw12_from_fs16_to_mg(int16_t lsb); 679 680 float_t lis2dtw12_from_fs2_lp1_to_mg(int16_t lsb); 681 float_t lis2dtw12_from_fs4_lp1_to_mg(int16_t lsb); 682 float_t lis2dtw12_from_fs8_lp1_to_mg(int16_t lsb); 683 float_t lis2dtw12_from_fs16_lp1_to_mg(int16_t lsb); 684 685 float_t lis2dtw12_from_lsb_to_celsius(int16_t lsb); 686 687 typedef enum 688 { 689 LIS2DTW12_HIGH_PERFORMANCE = 0x04, 690 LIS2DTW12_CONT_LOW_PWR_4 = 0x03, 691 LIS2DTW12_CONT_LOW_PWR_3 = 0x02, 692 LIS2DTW12_CONT_LOW_PWR_2 = 0x01, 693 LIS2DTW12_CONT_LOW_PWR_12bit = 0x00, 694 LIS2DTW12_SINGLE_LOW_PWR_4 = 0x0B, 695 LIS2DTW12_SINGLE_LOW_PWR_3 = 0x0A, 696 LIS2DTW12_SINGLE_LOW_PWR_2 = 0x09, 697 LIS2DTW12_SINGLE_LOW_PWR_12bit = 0x08, 698 LIS2DTW12_HIGH_PERFORMANCE_LOW_NOISE = 0x14, 699 LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_4 = 0x13, 700 LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_3 = 0x12, 701 LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_2 = 0x11, 702 LIS2DTW12_CONT_LOW_PWR_LOW_NOISE_12bit = 0x10, 703 LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_4 = 0x1B, 704 LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_3 = 0x1A, 705 LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19, 706 LIS2DTW12_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18, 707 } lis2dtw12_mode_t; 708 int32_t lis2dtw12_power_mode_set(const stmdev_ctx_t *ctx, 709 lis2dtw12_mode_t val); 710 int32_t lis2dtw12_power_mode_get(const stmdev_ctx_t *ctx, 711 lis2dtw12_mode_t *val); 712 713 typedef enum 714 { 715 LIS2DTW12_XL_ODR_OFF = 0x00, 716 LIS2DTW12_XL_ODR_1Hz6_LP_ONLY = 0x01, 717 LIS2DTW12_XL_ODR_12Hz5 = 0x02, 718 LIS2DTW12_XL_ODR_25Hz = 0x03, 719 LIS2DTW12_XL_ODR_50Hz = 0x04, 720 LIS2DTW12_XL_ODR_100Hz = 0x05, 721 LIS2DTW12_XL_ODR_200Hz = 0x06, 722 LIS2DTW12_XL_ODR_400Hz = 0x07, 723 LIS2DTW12_XL_ODR_800Hz = 0x08, 724 LIS2DTW12_XL_ODR_1k6Hz = 0x09, 725 LIS2DTW12_XL_SET_SW_TRIG = 0x12, /* Use this only in SINGLE mode */ 726 LIS2DTW12_XL_SET_PIN_TRIG = 0x22, /* Use this only in SINGLE mode */ 727 } lis2dtw12_odr_t; 728 int32_t lis2dtw12_data_rate_set(const stmdev_ctx_t *ctx, 729 lis2dtw12_odr_t val); 730 int32_t lis2dtw12_data_rate_get(const stmdev_ctx_t *ctx, 731 lis2dtw12_odr_t *val); 732 733 int32_t lis2dtw12_block_data_update_set(const stmdev_ctx_t *ctx, 734 uint8_t val); 735 int32_t lis2dtw12_block_data_update_get(const stmdev_ctx_t *ctx, 736 uint8_t *val); 737 738 typedef enum 739 { 740 LIS2DTW12_2g = 0, 741 LIS2DTW12_4g = 1, 742 LIS2DTW12_8g = 2, 743 LIS2DTW12_16g = 3, 744 } lis2dtw12_fs_t; 745 int32_t lis2dtw12_full_scale_set(const stmdev_ctx_t *ctx, 746 lis2dtw12_fs_t val); 747 int32_t lis2dtw12_full_scale_get(const stmdev_ctx_t *ctx, 748 lis2dtw12_fs_t *val); 749 750 int32_t lis2dtw12_status_reg_get(const stmdev_ctx_t *ctx, 751 lis2dtw12_status_t *val); 752 753 int32_t lis2dtw12_flag_data_ready_get(const stmdev_ctx_t *ctx, 754 uint8_t *val); 755 756 typedef struct 757 { 758 lis2dtw12_status_dup_t status_dup; 759 lis2dtw12_wake_up_src_t wake_up_src; 760 lis2dtw12_tap_src_t tap_src; 761 lis2dtw12_sixd_src_t sixd_src; 762 lis2dtw12_all_int_src_t all_int_src; 763 } lis2dtw12_all_sources_t; 764 int32_t lis2dtw12_all_sources_get(const stmdev_ctx_t *ctx, 765 lis2dtw12_all_sources_t *val); 766 767 int32_t lis2dtw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); 768 int32_t lis2dtw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); 769 770 int32_t lis2dtw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); 771 int32_t lis2dtw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); 772 773 int32_t lis2dtw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); 774 int32_t lis2dtw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); 775 776 typedef enum 777 { 778 LIS2DTW12_LSb_977ug = 0, 779 LIS2DTW12_LSb_15mg6 = 1, 780 } lis2dtw12_usr_off_w_t; 781 int32_t lis2dtw12_offset_weight_set(const stmdev_ctx_t *ctx, 782 lis2dtw12_usr_off_w_t val); 783 int32_t lis2dtw12_offset_weight_get(const stmdev_ctx_t *ctx, 784 lis2dtw12_usr_off_w_t *val); 785 786 int32_t lis2dtw12_temperature_raw_get(const stmdev_ctx_t *ctx, 787 int16_t *val); 788 789 int32_t lis2dtw12_acceleration_raw_get(const stmdev_ctx_t *ctx, 790 int16_t *val); 791 792 int32_t lis2dtw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 793 794 int32_t lis2dtw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 795 int32_t lis2dtw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 796 797 int32_t lis2dtw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 798 int32_t lis2dtw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 799 800 int32_t lis2dtw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 801 int32_t lis2dtw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 802 803 typedef enum 804 { 805 LIS2DTW12_XL_ST_DISABLE = 0, 806 LIS2DTW12_XL_ST_POSITIVE = 1, 807 LIS2DTW12_XL_ST_NEGATIVE = 2, 808 } lis2dtw12_st_t; 809 int32_t lis2dtw12_self_test_set(const stmdev_ctx_t *ctx, 810 lis2dtw12_st_t val); 811 int32_t lis2dtw12_self_test_get(const stmdev_ctx_t *ctx, 812 lis2dtw12_st_t *val); 813 814 typedef enum 815 { 816 LIS2DTW12_DRDY_LATCHED = 0, 817 LIS2DTW12_DRDY_PULSED = 1, 818 } lis2dtw12_drdy_pulsed_t; 819 int32_t lis2dtw12_data_ready_mode_set(const stmdev_ctx_t *ctx, 820 lis2dtw12_drdy_pulsed_t val); 821 int32_t lis2dtw12_data_ready_mode_get(const stmdev_ctx_t *ctx, 822 lis2dtw12_drdy_pulsed_t *val); 823 824 typedef enum 825 { 826 LIS2DTW12_LPF_ON_OUT = 0x00, 827 LIS2DTW12_USER_OFFSET_ON_OUT = 0x01, 828 LIS2DTW12_HIGH_PASS_ON_OUT = 0x10, 829 } lis2dtw12_fds_t; 830 int32_t lis2dtw12_filter_path_set(const stmdev_ctx_t *ctx, 831 lis2dtw12_fds_t val); 832 int32_t lis2dtw12_filter_path_get(const stmdev_ctx_t *ctx, 833 lis2dtw12_fds_t *val); 834 835 typedef enum 836 { 837 LIS2DTW12_ODR_DIV_2 = 0, 838 LIS2DTW12_ODR_DIV_4 = 1, 839 LIS2DTW12_ODR_DIV_10 = 2, 840 LIS2DTW12_ODR_DIV_20 = 3, 841 } lis2dtw12_bw_filt_t; 842 int32_t lis2dtw12_filter_bandwidth_set(const stmdev_ctx_t *ctx, 843 lis2dtw12_bw_filt_t val); 844 int32_t lis2dtw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, 845 lis2dtw12_bw_filt_t *val); 846 847 int32_t lis2dtw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 848 int32_t lis2dtw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 849 850 typedef enum 851 { 852 LIS2DTW12_SPI_4_WIRE = 0, 853 LIS2DTW12_SPI_3_WIRE = 1, 854 } lis2dtw12_sim_t; 855 int32_t lis2dtw12_spi_mode_set(const stmdev_ctx_t *ctx, 856 lis2dtw12_sim_t val); 857 int32_t lis2dtw12_spi_mode_get(const stmdev_ctx_t *ctx, 858 lis2dtw12_sim_t *val); 859 860 typedef enum 861 { 862 LIS2DTW12_I2C_ENABLE = 0, 863 LIS2DTW12_I2C_DISABLE = 1, 864 } lis2dtw12_i2c_disable_t; 865 int32_t lis2dtw12_i2c_interface_set(const stmdev_ctx_t *ctx, 866 lis2dtw12_i2c_disable_t val); 867 int32_t lis2dtw12_i2c_interface_get(const stmdev_ctx_t *ctx, 868 lis2dtw12_i2c_disable_t *val); 869 870 typedef enum 871 { 872 LIS2DTW12_PULL_UP_CONNECT = 0, 873 LIS2DTW12_PULL_UP_DISCONNECT = 1, 874 } lis2dtw12_cs_pu_disc_t; 875 int32_t lis2dtw12_cs_mode_set(const stmdev_ctx_t *ctx, 876 lis2dtw12_cs_pu_disc_t val); 877 int32_t lis2dtw12_cs_mode_get(const stmdev_ctx_t *ctx, 878 lis2dtw12_cs_pu_disc_t *val); 879 880 typedef enum 881 { 882 LIS2DTW12_ACTIVE_HIGH = 0, 883 LIS2DTW12_ACTIVE_LOW = 1, 884 } lis2dtw12_h_lactive_t; 885 int32_t lis2dtw12_pin_polarity_set(const stmdev_ctx_t *ctx, 886 lis2dtw12_h_lactive_t val); 887 int32_t lis2dtw12_pin_polarity_get(const stmdev_ctx_t *ctx, 888 lis2dtw12_h_lactive_t *val); 889 890 typedef enum 891 { 892 LIS2DTW12_INT_PULSED = 0, 893 LIS2DTW12_INT_LATCHED = 1, 894 } lis2dtw12_lir_t; 895 int32_t lis2dtw12_int_notification_set(const stmdev_ctx_t *ctx, 896 lis2dtw12_lir_t val); 897 int32_t lis2dtw12_int_notification_get(const stmdev_ctx_t *ctx, 898 lis2dtw12_lir_t *val); 899 900 typedef enum 901 { 902 LIS2DTW12_PUSH_PULL = 0, 903 LIS2DTW12_OPEN_DRAIN = 1, 904 } lis2dtw12_pp_od_t; 905 int32_t lis2dtw12_pin_mode_set(const stmdev_ctx_t *ctx, 906 lis2dtw12_pp_od_t val); 907 int32_t lis2dtw12_pin_mode_get(const stmdev_ctx_t *ctx, 908 lis2dtw12_pp_od_t *val); 909 910 int32_t lis2dtw12_pin_int1_route_set(const stmdev_ctx_t *ctx, 911 lis2dtw12_ctrl4_int1_pad_ctrl_t *val); 912 int32_t lis2dtw12_pin_int1_route_get(const stmdev_ctx_t *ctx, 913 lis2dtw12_ctrl4_int1_pad_ctrl_t *val); 914 915 int32_t lis2dtw12_pin_int2_route_set(const stmdev_ctx_t *ctx, 916 lis2dtw12_ctrl5_int2_pad_ctrl_t *val); 917 int32_t lis2dtw12_pin_int2_route_get(const stmdev_ctx_t *ctx, 918 lis2dtw12_ctrl5_int2_pad_ctrl_t *val); 919 920 int32_t lis2dtw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 921 int32_t lis2dtw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 922 923 int32_t lis2dtw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 924 int32_t lis2dtw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 925 926 int32_t lis2dtw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 927 int32_t lis2dtw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 928 929 typedef enum 930 { 931 LIS2DTW12_HP_FEED = 0, 932 LIS2DTW12_USER_OFFSET_FEED = 1, 933 } lis2dtw12_usr_off_on_wu_t; 934 int32_t lis2dtw12_wkup_feed_data_set(const stmdev_ctx_t *ctx, 935 lis2dtw12_usr_off_on_wu_t val); 936 int32_t lis2dtw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, 937 lis2dtw12_usr_off_on_wu_t *val); 938 939 typedef enum 940 { 941 LIS2DTW12_NO_DETECTION = 0, 942 LIS2DTW12_DETECT_ACT_INACT = 1, 943 LIS2DTW12_DETECT_STAT_MOTION = 3, 944 } lis2dtw12_sleep_on_t; 945 int32_t lis2dtw12_act_mode_set(const stmdev_ctx_t *ctx, 946 lis2dtw12_sleep_on_t val); 947 int32_t lis2dtw12_act_mode_get(const stmdev_ctx_t *ctx, 948 lis2dtw12_sleep_on_t *val); 949 950 int32_t lis2dtw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 951 int32_t lis2dtw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 952 953 int32_t lis2dtw12_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); 954 int32_t lis2dtw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, 955 uint8_t *val); 956 957 int32_t lis2dtw12_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); 958 int32_t lis2dtw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, 959 uint8_t *val); 960 961 typedef enum 962 { 963 LIS2DTW12_XYZ = 0, 964 LIS2DTW12_YXZ = 1, 965 LIS2DTW12_XZY = 2, 966 LIS2DTW12_ZYX = 3, 967 LIS2DTW12_YZX = 5, 968 LIS2DTW12_ZXY = 6, 969 } lis2dtw12_tap_prior_t; 970 int32_t lis2dtw12_tap_axis_priority_set(const stmdev_ctx_t *ctx, 971 lis2dtw12_tap_prior_t val); 972 int32_t lis2dtw12_tap_axis_priority_get(const stmdev_ctx_t *ctx, 973 lis2dtw12_tap_prior_t *val); 974 975 int32_t lis2dtw12_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); 976 int32_t lis2dtw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, 977 uint8_t *val); 978 979 int32_t lis2dtw12_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 980 uint8_t val); 981 int32_t lis2dtw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 982 uint8_t *val); 983 984 int32_t lis2dtw12_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 985 uint8_t val); 986 int32_t lis2dtw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 987 uint8_t *val); 988 989 int32_t lis2dtw12_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 990 uint8_t val); 991 int32_t lis2dtw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 992 uint8_t *val); 993 994 int32_t lis2dtw12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 995 int32_t lis2dtw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 996 997 int32_t lis2dtw12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 998 int32_t lis2dtw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 999 1000 int32_t lis2dtw12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1001 int32_t lis2dtw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1002 1003 typedef enum 1004 { 1005 LIS2DTW12_ONLY_SINGLE = 0, 1006 LIS2DTW12_BOTH_SINGLE_DOUBLE = 1, 1007 } lis2dtw12_single_double_tap_t; 1008 int32_t lis2dtw12_tap_mode_set(const stmdev_ctx_t *ctx, 1009 lis2dtw12_single_double_tap_t val); 1010 int32_t lis2dtw12_tap_mode_get(const stmdev_ctx_t *ctx, 1011 lis2dtw12_single_double_tap_t *val); 1012 1013 int32_t lis2dtw12_tap_src_get(const stmdev_ctx_t *ctx, 1014 lis2dtw12_tap_src_t *val); 1015 1016 int32_t lis2dtw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1017 int32_t lis2dtw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1018 1019 int32_t lis2dtw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 1020 int32_t lis2dtw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 1021 1022 int32_t lis2dtw12_6d_src_get(const stmdev_ctx_t *ctx, 1023 lis2dtw12_sixd_src_t *val); 1024 1025 typedef enum 1026 { 1027 LIS2DTW12_ODR_DIV_2_FEED = 0, 1028 LIS2DTW12_LPF2_FEED = 1, 1029 } lis2dtw12_lpass_on6d_t; 1030 int32_t lis2dtw12_6d_feed_data_set(const stmdev_ctx_t *ctx, 1031 lis2dtw12_lpass_on6d_t val); 1032 int32_t lis2dtw12_6d_feed_data_get(const stmdev_ctx_t *ctx, 1033 lis2dtw12_lpass_on6d_t *val); 1034 1035 int32_t lis2dtw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1036 int32_t lis2dtw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1037 1038 typedef enum 1039 { 1040 LIS2DTW12_FF_TSH_5LSb_FS2g = 0, 1041 LIS2DTW12_FF_TSH_7LSb_FS2g = 1, 1042 LIS2DTW12_FF_TSH_8LSb_FS2g = 2, 1043 LIS2DTW12_FF_TSH_10LSb_FS2g = 3, 1044 LIS2DTW12_FF_TSH_11LSb_FS2g = 4, 1045 LIS2DTW12_FF_TSH_13LSb_FS2g = 5, 1046 LIS2DTW12_FF_TSH_15LSb_FS2g = 6, 1047 LIS2DTW12_FF_TSH_16LSb_FS2g = 7, 1048 } lis2dtw12_ff_ths_t; 1049 int32_t lis2dtw12_ff_threshold_set(const stmdev_ctx_t *ctx, 1050 lis2dtw12_ff_ths_t val); 1051 int32_t lis2dtw12_ff_threshold_get(const stmdev_ctx_t *ctx, 1052 lis2dtw12_ff_ths_t *val); 1053 1054 int32_t lis2dtw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 1055 int32_t lis2dtw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 1056 1057 typedef enum 1058 { 1059 LIS2DTW12_BYPASS_MODE = 0, 1060 LIS2DTW12_FIFO_MODE = 1, 1061 LIS2DTW12_STREAM_TO_FIFO_MODE = 3, 1062 LIS2DTW12_BYPASS_TO_STREAM_MODE = 4, 1063 LIS2DTW12_STREAM_MODE = 6, 1064 } lis2dtw12_fmode_t; 1065 int32_t lis2dtw12_fifo_mode_set(const stmdev_ctx_t *ctx, 1066 lis2dtw12_fmode_t val); 1067 int32_t lis2dtw12_fifo_mode_get(const stmdev_ctx_t *ctx, 1068 lis2dtw12_fmode_t *val); 1069 1070 int32_t lis2dtw12_fifo_data_level_get(const stmdev_ctx_t *ctx, 1071 uint8_t *val); 1072 1073 int32_t lis2dtw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1074 1075 int32_t lis2dtw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1076 1077 /** 1078 * @} 1079 * 1080 */ 1081 1082 #ifdef __cplusplus 1083 } 1084 #endif 1085 1086 #endif /*LIS2DTW12_REGS_H */ 1087 1088 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1089
