1 /** 2 ****************************************************************************** 3 * @file lis2ds12_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis2ds12_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS2DS12_REGS_H 23 #define LIS2DS12_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS2DS12 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS2DS12_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0x3D if SA0=1 -> 0x3B **/ 172 #define LIS2DS12_I2C_ADD_L 0x3DU 173 #define LIS2DS12_I2C_ADD_H 0x3BU 174 175 /** Device Identification (Who am I) **/ 176 #define LIS2DS12_ID 0x43U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LIS2DS12_SENSORHUB1_REG 0x06U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t bit0 : 1; 188 uint8_t bit1 : 1; 189 uint8_t bit2 : 1; 190 uint8_t bit3 : 1; 191 uint8_t bit4 : 1; 192 uint8_t bit5 : 1; 193 uint8_t bit6 : 1; 194 uint8_t bit7 : 1; 195 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 196 uint8_t bit7 : 1; 197 uint8_t bit6 : 1; 198 uint8_t bit5 : 1; 199 uint8_t bit4 : 1; 200 uint8_t bit3 : 1; 201 uint8_t bit2 : 1; 202 uint8_t bit1 : 1; 203 uint8_t bit0 : 1; 204 #endif /* DRV_BYTE_ORDER */ 205 } lis2ds12_sensorhub1_reg_t; 206 207 #define LIS2DS12_SENSORHUB2_REG 0x07U 208 typedef struct 209 { 210 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 211 uint8_t bit0 : 1; 212 uint8_t bit1 : 1; 213 uint8_t bit2 : 1; 214 uint8_t bit3 : 1; 215 uint8_t bit4 : 1; 216 uint8_t bit5 : 1; 217 uint8_t bit6 : 1; 218 uint8_t bit7 : 1; 219 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 220 uint8_t bit7 : 1; 221 uint8_t bit6 : 1; 222 uint8_t bit5 : 1; 223 uint8_t bit4 : 1; 224 uint8_t bit3 : 1; 225 uint8_t bit2 : 1; 226 uint8_t bit1 : 1; 227 uint8_t bit0 : 1; 228 #endif /* DRV_BYTE_ORDER */ 229 } lis2ds12_sensorhub2_reg_t; 230 231 #define LIS2DS12_SENSORHUB3_REG 0x08U 232 typedef struct 233 { 234 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 235 uint8_t bit0 : 1; 236 uint8_t bit1 : 1; 237 uint8_t bit2 : 1; 238 uint8_t bit3 : 1; 239 uint8_t bit4 : 1; 240 uint8_t bit5 : 1; 241 uint8_t bit6 : 1; 242 uint8_t bit7 : 1; 243 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 244 uint8_t bit7 : 1; 245 uint8_t bit6 : 1; 246 uint8_t bit5 : 1; 247 uint8_t bit4 : 1; 248 uint8_t bit3 : 1; 249 uint8_t bit2 : 1; 250 uint8_t bit1 : 1; 251 uint8_t bit0 : 1; 252 #endif /* DRV_BYTE_ORDER */ 253 } lis2ds12_sensorhub3_reg_t; 254 255 #define LIS2DS12_SENSORHUB4_REG 0x09U 256 typedef struct 257 { 258 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 259 uint8_t bit0 : 1; 260 uint8_t bit1 : 1; 261 uint8_t bit2 : 1; 262 uint8_t bit3 : 1; 263 uint8_t bit4 : 1; 264 uint8_t bit5 : 1; 265 uint8_t bit6 : 1; 266 uint8_t bit7 : 1; 267 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 268 uint8_t bit7 : 1; 269 uint8_t bit6 : 1; 270 uint8_t bit5 : 1; 271 uint8_t bit4 : 1; 272 uint8_t bit3 : 1; 273 uint8_t bit2 : 1; 274 uint8_t bit1 : 1; 275 uint8_t bit0 : 1; 276 #endif /* DRV_BYTE_ORDER */ 277 } lis2ds12_sensorhub4_reg_t; 278 279 #define LIS2DS12_SENSORHUB5_REG 0x0AU 280 typedef struct 281 { 282 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 283 uint8_t bit0 : 1; 284 uint8_t bit1 : 1; 285 uint8_t bit2 : 1; 286 uint8_t bit3 : 1; 287 uint8_t bit4 : 1; 288 uint8_t bit5 : 1; 289 uint8_t bit6 : 1; 290 uint8_t bit7 : 1; 291 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 292 uint8_t bit7 : 1; 293 uint8_t bit6 : 1; 294 uint8_t bit5 : 1; 295 uint8_t bit4 : 1; 296 uint8_t bit3 : 1; 297 uint8_t bit2 : 1; 298 uint8_t bit1 : 1; 299 uint8_t bit0 : 1; 300 #endif /* DRV_BYTE_ORDER */ 301 } lis2ds12_sensorhub5_reg_t; 302 303 #define LIS2DS12_SENSORHUB6_REG 0x0BU 304 typedef struct 305 { 306 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 307 uint8_t bit0 : 1; 308 uint8_t bit1 : 1; 309 uint8_t bit2 : 1; 310 uint8_t bit3 : 1; 311 uint8_t bit4 : 1; 312 uint8_t bit5 : 1; 313 uint8_t bit6 : 1; 314 uint8_t bit7 : 1; 315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 316 uint8_t bit7 : 1; 317 uint8_t bit6 : 1; 318 uint8_t bit5 : 1; 319 uint8_t bit4 : 1; 320 uint8_t bit3 : 1; 321 uint8_t bit2 : 1; 322 uint8_t bit1 : 1; 323 uint8_t bit0 : 1; 324 #endif /* DRV_BYTE_ORDER */ 325 } lis2ds12_sensorhub6_reg_t; 326 327 #define LIS2DS12_MODULE_8BIT 0x0CU 328 #define LIS2DS12_WHO_AM_I 0x0FU 329 #define LIS2DS12_CTRL1 0x20U 330 typedef struct 331 { 332 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 333 uint8_t bdu : 1; 334 uint8_t hf_odr : 1; 335 uint8_t fs : 2; 336 uint8_t odr : 4; 337 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 338 uint8_t odr : 4; 339 uint8_t fs : 2; 340 uint8_t hf_odr : 1; 341 uint8_t bdu : 1; 342 #endif /* DRV_BYTE_ORDER */ 343 344 } lis2ds12_ctrl1_t; 345 346 #define LIS2DS12_CTRL2 0x21U 347 typedef struct 348 { 349 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 350 uint8_t sim : 1; 351 uint8_t i2c_disable : 1; 352 uint8_t if_add_inc : 1; 353 uint8_t fds_slope : 1; 354 uint8_t func_cfg_en : 1; 355 uint8_t not_used_01 : 1; 356 uint8_t soft_reset : 1; 357 uint8_t boot : 1; 358 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 359 uint8_t boot : 1; 360 uint8_t soft_reset : 1; 361 uint8_t not_used_01 : 1; 362 uint8_t func_cfg_en : 1; 363 uint8_t fds_slope : 1; 364 uint8_t if_add_inc : 1; 365 uint8_t i2c_disable : 1; 366 uint8_t sim : 1; 367 #endif /* DRV_BYTE_ORDER */ 368 369 } lis2ds12_ctrl2_t; 370 371 #define LIS2DS12_CTRL3 0x22U 372 typedef struct 373 { 374 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 375 uint8_t pp_od : 1; 376 uint8_t h_lactive : 1; 377 uint8_t lir : 1; 378 uint8_t tap_z_en : 1; 379 uint8_t tap_y_en : 1; 380 uint8_t tap_x_en : 1; 381 uint8_t st : 2; 382 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 383 uint8_t st : 2; 384 uint8_t tap_x_en : 1; 385 uint8_t tap_y_en : 1; 386 uint8_t tap_z_en : 1; 387 uint8_t lir : 1; 388 uint8_t h_lactive : 1; 389 uint8_t pp_od : 1; 390 #endif /* DRV_BYTE_ORDER */ 391 392 } lis2ds12_ctrl3_t; 393 394 #define LIS2DS12_CTRL4 0x23U 395 typedef struct 396 { 397 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 398 uint8_t int1_drdy : 1; 399 uint8_t int1_fth : 1; 400 uint8_t int1_6d : 1; 401 uint8_t int1_tap : 1; 402 uint8_t int1_ff : 1; 403 uint8_t int1_wu : 1; 404 uint8_t int1_s_tap : 1; 405 uint8_t int1_master_drdy : 1; 406 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 407 uint8_t int1_master_drdy : 1; 408 uint8_t int1_s_tap : 1; 409 uint8_t int1_wu : 1; 410 uint8_t int1_ff : 1; 411 uint8_t int1_tap : 1; 412 uint8_t int1_6d : 1; 413 uint8_t int1_fth : 1; 414 uint8_t int1_drdy : 1; 415 #endif /* DRV_BYTE_ORDER */ 416 } lis2ds12_ctrl4_t; 417 418 #define LIS2DS12_CTRL5 0x24U 419 typedef struct 420 { 421 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 422 uint8_t int2_drdy : 1; 423 uint8_t int2_fth : 1; 424 uint8_t int2_step_det : 1; 425 uint8_t int2_sig_mot : 1; 426 uint8_t int2_tilt : 1; 427 uint8_t int2_on_int1 : 1; 428 uint8_t int2_boot : 1; 429 uint8_t drdy_pulsed : 1; 430 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 431 uint8_t drdy_pulsed : 1; 432 uint8_t int2_boot : 1; 433 uint8_t int2_on_int1 : 1; 434 uint8_t int2_tilt : 1; 435 uint8_t int2_sig_mot : 1; 436 uint8_t int2_step_det : 1; 437 uint8_t int2_fth : 1; 438 uint8_t int2_drdy : 1; 439 #endif /* DRV_BYTE_ORDER */ 440 } lis2ds12_ctrl5_t; 441 442 #define LIS2DS12_FIFO_CTRL 0x25U 443 typedef struct 444 { 445 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 446 uint8_t if_cs_pu_dis : 1; 447 uint8_t not_used_01 : 2; 448 uint8_t module_to_fifo : 1; 449 uint8_t int2_step_count_ov : 1; 450 uint8_t fmode : 3; 451 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 452 uint8_t fmode : 3; 453 uint8_t int2_step_count_ov : 1; 454 uint8_t module_to_fifo : 1; 455 uint8_t not_used_01 : 2; 456 uint8_t if_cs_pu_dis : 1; 457 #endif /* DRV_BYTE_ORDER */ 458 } lis2ds12_fifo_ctrl_t; 459 460 #define LIS2DS12_OUT_T 0x26U 461 #define LIS2DS12_STATUS 0x27U 462 typedef struct 463 { 464 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 465 uint8_t drdy : 1; 466 uint8_t ff_ia : 1; 467 uint8_t _6d_ia : 1; 468 uint8_t single_tap : 1; 469 uint8_t double_tap : 1; 470 uint8_t sleep_state : 1; 471 uint8_t wu_ia : 1; 472 uint8_t fifo_ths : 1; 473 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 474 uint8_t fifo_ths : 1; 475 uint8_t wu_ia : 1; 476 uint8_t sleep_state : 1; 477 uint8_t double_tap : 1; 478 uint8_t single_tap : 1; 479 uint8_t _6d_ia : 1; 480 uint8_t ff_ia : 1; 481 uint8_t drdy : 1; 482 #endif /* DRV_BYTE_ORDER */ 483 } lis2ds12_status_t; 484 485 #define LIS2DS12_OUT_X_L 0x28U 486 #define LIS2DS12_OUT_X_H 0x29U 487 #define LIS2DS12_OUT_Y_L 0x2AU 488 #define LIS2DS12_OUT_Y_H 0x2BU 489 #define LIS2DS12_OUT_Z_L 0x2CU 490 #define LIS2DS12_OUT_Z_H 0x2DU 491 #define LIS2DS12_FIFO_THS 0x2EU 492 typedef struct 493 { 494 uint8_t fth : 8; 495 } lis2ds12_fifo_ths_t; 496 497 #define LIS2DS12_FIFO_SRC 0x2FU 498 typedef struct 499 { 500 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 501 uint8_t not_used_01 : 5; 502 uint8_t diff : 1; 503 uint8_t fifo_ovr : 1; 504 uint8_t fth : 1; 505 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 506 uint8_t fth : 1; 507 uint8_t fifo_ovr : 1; 508 uint8_t diff : 1; 509 uint8_t not_used_01 : 5; 510 #endif /* DRV_BYTE_ORDER */ 511 } lis2ds12_fifo_src_t; 512 513 #define LIS2DS12_FIFO_SAMPLES 0x30U 514 #define LIS2DS12_TAP_6D_THS 0x31U 515 typedef struct 516 { 517 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 518 uint8_t tap_ths : 5; 519 uint8_t _6d_ths : 2; 520 uint8_t _4d_en : 1; 521 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 522 uint8_t _4d_en : 1; 523 uint8_t _6d_ths : 2; 524 uint8_t tap_ths : 5; 525 #endif /* DRV_BYTE_ORDER */ 526 } lis2ds12_tap_6d_ths_t; 527 528 #define LIS2DS12_INT_DUR 0x32U 529 typedef struct 530 { 531 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 532 uint8_t shock : 2; 533 uint8_t quiet : 2; 534 uint8_t lat : 4; 535 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 536 uint8_t lat : 4; 537 uint8_t quiet : 2; 538 uint8_t shock : 2; 539 #endif /* DRV_BYTE_ORDER */ 540 } lis2ds12_int_dur_t; 541 542 #define LIS2DS12_WAKE_UP_THS 0x33U 543 typedef struct 544 { 545 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 546 uint8_t wu_ths : 6; 547 uint8_t sleep_on : 1; 548 uint8_t single_double_tap : 1; 549 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 550 uint8_t single_double_tap : 1; 551 uint8_t sleep_on : 1; 552 uint8_t wu_ths : 6; 553 #endif /* DRV_BYTE_ORDER */ 554 } lis2ds12_wake_up_ths_t; 555 556 #define LIS2DS12_WAKE_UP_DUR 0x34U 557 typedef struct 558 { 559 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 560 uint8_t sleep_dur : 4; 561 uint8_t int1_fss7 : 1; 562 uint8_t wu_dur : 2; 563 uint8_t ff_dur : 1; 564 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 565 uint8_t ff_dur : 1; 566 uint8_t wu_dur : 2; 567 uint8_t int1_fss7 : 1; 568 uint8_t sleep_dur : 4; 569 #endif /* DRV_BYTE_ORDER */ 570 } lis2ds12_wake_up_dur_t; 571 572 #define LIS2DS12_FREE_FALL 0x35U 573 typedef struct 574 { 575 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 576 uint8_t ff_ths : 3; 577 uint8_t ff_dur : 5; 578 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 579 uint8_t ff_dur : 5; 580 uint8_t ff_ths : 3; 581 #endif /* DRV_BYTE_ORDER */ 582 } lis2ds12_free_fall_t; 583 584 #define LIS2DS12_STATUS_DUP 0x36U 585 typedef struct 586 { 587 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 588 uint8_t drdy : 1; 589 uint8_t ff_ia : 1; 590 uint8_t _6d_ia : 1; 591 uint8_t single_tap : 1; 592 uint8_t double_tap : 1; 593 uint8_t sleep_state : 1; 594 uint8_t wu_ia : 1; 595 uint8_t ovr : 1; 596 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 597 uint8_t ovr : 1; 598 uint8_t ovr : 1; 599 uint8_t sleep_state : 1; 600 uint8_t double_tap : 1; 601 uint8_t single_tap : 1; 602 uint8_t _6d_ia : 1; 603 uint8_t ff_ia : 1; 604 uint8_t drdy : 1; 605 #endif /* DRV_BYTE_ORDER */ 606 } lis2ds12_status_dup_t; 607 608 #define LIS2DS12_WAKE_UP_SRC 0x37U 609 typedef struct 610 { 611 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 612 uint8_t z_wu : 1; 613 uint8_t y_wu : 1; 614 uint8_t x_wu : 1; 615 uint8_t wu_ia : 1; 616 uint8_t sleep_state_ia : 1; 617 uint8_t ff_ia : 1; 618 uint8_t not_used_01 : 2; 619 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 620 uint8_t not_used_01 : 2; 621 uint8_t ff_ia : 1; 622 uint8_t sleep_state_ia : 1; 623 uint8_t wu_ia : 1; 624 uint8_t x_wu : 1; 625 uint8_t y_wu : 1; 626 uint8_t z_wu : 1; 627 #endif /* DRV_BYTE_ORDER */ 628 } lis2ds12_wake_up_src_t; 629 630 #define LIS2DS12_TAP_SRC 0x38U 631 typedef struct 632 { 633 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 634 uint8_t z_tap : 1; 635 uint8_t y_tap : 1; 636 uint8_t x_tap : 1; 637 uint8_t tap_sign : 1; 638 uint8_t double_tap : 1; 639 uint8_t single_tap : 1; 640 uint8_t tap_ia : 1; 641 uint8_t not_used_01 : 1; 642 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 643 uint8_t not_used_01 : 1; 644 uint8_t tap_ia : 1; 645 uint8_t single_tap : 1; 646 uint8_t double_tap : 1; 647 uint8_t tap_sign : 1; 648 uint8_t x_tap : 1; 649 uint8_t y_tap : 1; 650 uint8_t z_tap : 1; 651 #endif /* DRV_BYTE_ORDER */ 652 } lis2ds12_tap_src_t; 653 654 #define LIS2DS12_6D_SRC 0x39U 655 typedef struct 656 { 657 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 658 uint8_t xl : 1; 659 uint8_t xh : 1; 660 uint8_t yl : 1; 661 uint8_t yh : 1; 662 uint8_t zl : 1; 663 uint8_t zh : 1; 664 uint8_t _6d_ia : 1; 665 uint8_t not_used_01 : 1; 666 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 667 uint8_t not_used_01 : 1; 668 uint8_t _6d_ia : 1; 669 uint8_t zh : 1; 670 uint8_t zl : 1; 671 uint8_t yh : 1; 672 uint8_t yl : 1; 673 uint8_t xh : 1; 674 uint8_t xl : 1; 675 #endif /* DRV_BYTE_ORDER */ 676 } lis2ds12_6d_src_t; 677 678 #define LIS2DS12_STEP_COUNTER_MINTHS 0x3AU 679 typedef struct 680 { 681 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 682 uint8_t sc_mths : 6; 683 uint8_t pedo4g : 1; 684 uint8_t rst_nstep : 1; 685 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 686 uint8_t rst_nstep : 1; 687 uint8_t pedo4g : 1; 688 uint8_t sc_mths : 6; 689 #endif /* DRV_BYTE_ORDER */ 690 } lis2ds12_step_counter_minths_t; 691 692 #define LIS2DS12_STEP_COUNTER_L 0x3BU 693 #define LIS2DS12_STEP_COUNTER_H 0x3CU 694 #define LIS2DS12_FUNC_CK_GATE 0x3DU 695 typedef struct 696 { 697 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 698 uint8_t ck_gate_func : 1; 699 uint8_t step_detect : 1; 700 uint8_t rst_pedo : 1; 701 uint8_t rst_sign_mot : 1; 702 uint8_t sig_mot_detect : 1; 703 uint8_t fs_src : 2; 704 uint8_t tilt_int : 1; 705 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 706 uint8_t tilt_int : 1; 707 uint8_t fs_src : 2; 708 uint8_t sig_mot_detect : 1; 709 uint8_t rst_sign_mot : 1; 710 uint8_t rst_pedo : 1; 711 uint8_t step_detect : 1; 712 uint8_t ck_gate_func : 1; 713 #endif /* DRV_BYTE_ORDER */ 714 } lis2ds12_func_ck_gate_t; 715 716 #define LIS2DS12_FUNC_SRC 0x3EU 717 typedef struct 718 { 719 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 720 uint8_t sensorhub_end_op : 1; 721 uint8_t module_ready : 1; 722 uint8_t rst_tilt : 1; 723 uint8_t not_used_01 : 5; 724 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 725 uint8_t not_used_01 : 5; 726 uint8_t rst_tilt : 1; 727 uint8_t module_ready : 1; 728 uint8_t sensorhub_end_op : 1; 729 #endif /* DRV_BYTE_ORDER */ 730 } lis2ds12_func_src_t; 731 732 #define LIS2DS12_FUNC_CTRL 0x3FU 733 typedef struct 734 { 735 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 736 uint8_t step_cnt_on : 1; 737 uint8_t sign_mot_on : 1; 738 uint8_t master_on : 1; 739 uint8_t tud_en : 1; 740 uint8_t tilt_on : 1; 741 uint8_t module_on : 1; 742 uint8_t not_used_01 : 2; 743 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 744 uint8_t not_used_01 : 2; 745 uint8_t module_on : 1; 746 uint8_t tilt_on : 1; 747 uint8_t tud_en : 1; 748 uint8_t master_on : 1; 749 uint8_t sign_mot_on : 1; 750 uint8_t step_cnt_on : 1; 751 #endif /* DRV_BYTE_ORDER */ 752 } lis2ds12_func_ctrl_t; 753 754 #define LIS2DS12_PEDO_DEB_REG 0x2BU 755 typedef struct 756 { 757 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 758 uint8_t deb_step : 3; 759 uint8_t deb_time : 5; 760 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 761 uint8_t deb_time : 5; 762 uint8_t deb_step : 3; 763 #endif /* DRV_BYTE_ORDER */ 764 } lis2ds12_pedo_deb_reg_t; 765 766 #define LIS2DS12_SLV0_ADD 0x30U 767 typedef struct 768 { 769 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 770 uint8_t rw_0 : 1; 771 uint8_t slave0_add : 7; 772 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 773 uint8_t slave0_add : 7; 774 uint8_t rw_0 : 1; 775 #endif /* DRV_BYTE_ORDER */ 776 } lis2ds12_slv0_add_t; 777 778 #define LIS2DS12_SLV0_SUBADD 0x31U 779 typedef struct 780 { 781 uint8_t slave0_reg : 8; 782 } lis2ds12_slv0_subadd_t; 783 784 #define LIS2DS12_SLV0_CONFIG 0x32U 785 typedef struct 786 { 787 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 788 uint8_t slave0_numop : 3; 789 uint8_t not_used_01 : 5; 790 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 791 uint8_t not_used_01 : 5; 792 uint8_t slave0_numop : 3; 793 #endif /* DRV_BYTE_ORDER */ 794 } lis2ds12_slv0_config_t; 795 796 #define LIS2DS12_DATAWRITE_SLV0 0x33U 797 typedef struct 798 { 799 uint8_t slave_dataw : 8; 800 } lis2ds12_datawrite_slv0_t; 801 802 #define LIS2DS12_SM_THS 0x34U 803 typedef struct 804 { 805 uint8_t sm_ths : 8; 806 } lis2ds12_sm_ths_t; 807 808 #define LIS2DS12_STEP_COUNT_DELTA 0x3AU 809 typedef struct 810 { 811 uint8_t step_count_d : 8; 812 } lis2ds12_step_count_delta_t; 813 814 #define LIS2DS12_CTRL2_ADV 0x3FU 815 typedef struct 816 { 817 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 818 uint8_t sim : 1; 819 uint8_t i2c_disable : 1; 820 uint8_t if_add_inc : 1; 821 uint8_t fds_slope : 1; 822 uint8_t func_cfg_en : 1; 823 uint8_t not_used_01 : 1; 824 uint8_t soft_reset : 1; 825 uint8_t boot : 1; 826 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 827 uint8_t boot : 1; 828 uint8_t soft_reset : 1; 829 uint8_t not_used_01 : 1; 830 uint8_t func_cfg_en : 1; 831 uint8_t fds_slope : 1; 832 uint8_t if_add_inc : 1; 833 uint8_t i2c_disable : 1; 834 uint8_t sim : 1; 835 #endif /* DRV_BYTE_ORDER */ 836 } lis2ds12_ctrl2_adv_t; 837 838 /** 839 * @defgroup LIS2DS12_Register_Union 840 * @brief This union group all the registers having a bit-field 841 * description. 842 * This union is useful but it's not needed by the driver. 843 * 844 * REMOVING this union you are compliant with: 845 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 846 * 847 * @{ 848 * 849 */ 850 typedef union 851 { 852 lis2ds12_sensorhub1_reg_t sensorhub1_reg; 853 lis2ds12_sensorhub2_reg_t sensorhub2_reg; 854 lis2ds12_sensorhub3_reg_t sensorhub3_reg; 855 lis2ds12_sensorhub4_reg_t sensorhub4_reg; 856 lis2ds12_sensorhub5_reg_t sensorhub5_reg; 857 lis2ds12_sensorhub6_reg_t sensorhub6_reg; 858 lis2ds12_ctrl1_t ctrl1; 859 lis2ds12_ctrl2_t ctrl2; 860 lis2ds12_ctrl3_t ctrl3; 861 lis2ds12_ctrl4_t ctrl4; 862 lis2ds12_ctrl5_t ctrl5; 863 lis2ds12_fifo_ctrl_t fifo_ctrl; 864 lis2ds12_status_t status; 865 lis2ds12_fifo_src_t fifo_src; 866 lis2ds12_tap_6d_ths_t tap_6d_ths; 867 lis2ds12_int_dur_t int_dur; 868 lis2ds12_wake_up_ths_t wake_up_ths; 869 lis2ds12_wake_up_dur_t wake_up_dur; 870 lis2ds12_free_fall_t free_fall; 871 lis2ds12_status_dup_t status_dup; 872 lis2ds12_wake_up_src_t wake_up_src; 873 lis2ds12_tap_src_t tap_src; 874 lis2ds12_6d_src_t _6d_src; 875 lis2ds12_step_counter_minths_t step_counter_minths; 876 lis2ds12_func_ck_gate_t func_ck_gate; 877 lis2ds12_func_src_t func_src; 878 lis2ds12_func_ctrl_t func_ctrl; 879 lis2ds12_pedo_deb_reg_t pedo_deb_reg; 880 lis2ds12_slv0_add_t slv0_add; 881 lis2ds12_slv0_subadd_t slv0_subadd; 882 lis2ds12_slv0_config_t slv0_config; 883 lis2ds12_datawrite_slv0_t datawrite_slv0; 884 lis2ds12_sm_ths_t sm_ths; 885 lis2ds12_step_count_delta_t step_count_delta; 886 lis2ds12_ctrl2_adv_t ctrl2_adv; 887 bitwise_t bitwise; 888 uint8_t byte; 889 } lis2ds12_reg_t; 890 891 /** 892 * @} 893 * 894 */ 895 896 #ifndef __weak 897 #define __weak __attribute__((weak)) 898 #endif /* __weak */ 899 900 /* 901 * These are the basic platform dependent I/O routines to read 902 * and write device registers connected on a standard bus. 903 * The driver keeps offering a default implementation based on function 904 * pointers to read/write routines for backward compatibility. 905 * The __weak directive allows the final application to overwrite 906 * them with a custom implementation. 907 */ 908 909 int32_t lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 910 uint8_t *data, 911 uint16_t len); 912 int32_t lis2ds12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 913 uint8_t *data, 914 uint16_t len); 915 916 float_t lis2ds12_from_fs2g_to_mg(int16_t lsb); 917 float_t lis2ds12_from_fs4g_to_mg(int16_t lsb); 918 float_t lis2ds12_from_fs8g_to_mg(int16_t lsb); 919 float_t lis2ds12_from_fs16g_to_mg(int16_t lsb); 920 921 float_t lis2ds12_from_lsb_to_celsius(int16_t lsb); 922 923 typedef struct 924 { 925 lis2ds12_fifo_src_t fifo_src; 926 lis2ds12_status_dup_t status_dup; 927 lis2ds12_wake_up_src_t wake_up_src; 928 lis2ds12_tap_src_t tap_src; 929 lis2ds12_6d_src_t _6d_src; 930 lis2ds12_func_ck_gate_t func_ck_gate; 931 lis2ds12_func_src_t func_src; 932 } lis2ds12_all_sources_t; 933 int32_t lis2ds12_all_sources_get(stmdev_ctx_t *ctx, 934 lis2ds12_all_sources_t *val); 935 936 int32_t lis2ds12_block_data_update_set(stmdev_ctx_t *ctx, 937 uint8_t val); 938 int32_t lis2ds12_block_data_update_get(stmdev_ctx_t *ctx, 939 uint8_t *val); 940 941 typedef enum 942 { 943 LIS2DS12_2g = 0, 944 LIS2DS12_16g = 1, 945 LIS2DS12_4g = 2, 946 LIS2DS12_8g = 3, 947 } lis2ds12_fs_t; 948 int32_t lis2ds12_xl_full_scale_set(stmdev_ctx_t *ctx, 949 lis2ds12_fs_t val); 950 int32_t lis2ds12_xl_full_scale_get(stmdev_ctx_t *ctx, 951 lis2ds12_fs_t *val); 952 953 typedef enum 954 { 955 LIS2DS12_XL_ODR_OFF = 0x00, 956 LIS2DS12_XL_ODR_1Hz_LP = 0x08, 957 LIS2DS12_XL_ODR_12Hz5_LP = 0x09, 958 LIS2DS12_XL_ODR_25Hz_LP = 0x0A, 959 LIS2DS12_XL_ODR_50Hz_LP = 0x0B, 960 LIS2DS12_XL_ODR_100Hz_LP = 0x0C, 961 LIS2DS12_XL_ODR_200Hz_LP = 0x0D, 962 LIS2DS12_XL_ODR_400Hz_LP = 0x0E, 963 LIS2DS12_XL_ODR_800Hz_LP = 0x0F, 964 LIS2DS12_XL_ODR_12Hz5_HR = 0x01, 965 LIS2DS12_XL_ODR_25Hz_HR = 0x02, 966 LIS2DS12_XL_ODR_50Hz_HR = 0x03, 967 LIS2DS12_XL_ODR_100Hz_HR = 0x04, 968 LIS2DS12_XL_ODR_200Hz_HR = 0x05, 969 LIS2DS12_XL_ODR_400Hz_HR = 0x06, 970 LIS2DS12_XL_ODR_800Hz_HR = 0x07, 971 LIS2DS12_XL_ODR_1k6Hz_HF = 0x15, 972 LIS2DS12_XL_ODR_3k2Hz_HF = 0x16, 973 LIS2DS12_XL_ODR_6k4Hz_HF = 0x17, 974 } lis2ds12_odr_t; 975 int32_t lis2ds12_xl_data_rate_set(stmdev_ctx_t *ctx, 976 lis2ds12_odr_t val); 977 int32_t lis2ds12_xl_data_rate_get(stmdev_ctx_t *ctx, 978 lis2ds12_odr_t *val); 979 980 int32_t lis2ds12_status_reg_get(stmdev_ctx_t *ctx, 981 lis2ds12_status_t *val); 982 983 int32_t lis2ds12_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 984 uint8_t *val); 985 986 int32_t lis2ds12_acceleration_module_raw_get(stmdev_ctx_t *ctx, 987 uint8_t *buff); 988 989 int32_t lis2ds12_temperature_raw_get(stmdev_ctx_t *ctx, 990 uint8_t *buff); 991 992 int32_t lis2ds12_acceleration_raw_get(stmdev_ctx_t *ctx, 993 int16_t *val); 994 995 int32_t lis2ds12_number_of_steps_get(stmdev_ctx_t *ctx, int16_t *val); 996 997 int32_t lis2ds12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 998 999 int32_t lis2ds12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 1000 int32_t lis2ds12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 1001 1002 typedef enum 1003 { 1004 LIS2DS12_USER_BANK = 0, 1005 LIS2DS12_ADV_BANK = 1, 1006 } lis2ds12_func_cfg_en_t; 1007 int32_t lis2ds12_mem_bank_set(stmdev_ctx_t *ctx, 1008 lis2ds12_func_cfg_en_t val); 1009 1010 int32_t lis2ds12_reset_set(stmdev_ctx_t *ctx, uint8_t val); 1011 int32_t lis2ds12_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 1012 1013 int32_t lis2ds12_boot_set(stmdev_ctx_t *ctx, uint8_t val); 1014 int32_t lis2ds12_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 1015 1016 typedef enum 1017 { 1018 LIS2DS12_XL_ST_DISABLE = 0, 1019 LIS2DS12_XL_ST_POSITIVE = 1, 1020 LIS2DS12_XL_ST_NEGATIVE = 2, 1021 } lis2ds12_st_t; 1022 int32_t lis2ds12_xl_self_test_set(stmdev_ctx_t *ctx, 1023 lis2ds12_st_t val); 1024 int32_t lis2ds12_xl_self_test_get(stmdev_ctx_t *ctx, 1025 lis2ds12_st_t *val); 1026 1027 typedef enum 1028 { 1029 LIS2DS12_DRDY_LATCHED = 0, 1030 LIS2DS12_DRDY_PULSED = 1, 1031 } lis2ds12_drdy_pulsed_t; 1032 int32_t lis2ds12_data_ready_mode_set(stmdev_ctx_t *ctx, 1033 lis2ds12_drdy_pulsed_t val); 1034 int32_t lis2ds12_data_ready_mode_get(stmdev_ctx_t *ctx, 1035 lis2ds12_drdy_pulsed_t *val); 1036 1037 typedef enum 1038 { 1039 LIS2DS12_HP_INTERNAL_ONLY = 0, 1040 LIS2DS12_HP_ON_OUTPUTS = 1, 1041 } lis2ds12_fds_slope_t; 1042 int32_t lis2ds12_xl_hp_path_set(stmdev_ctx_t *ctx, 1043 lis2ds12_fds_slope_t val); 1044 int32_t lis2ds12_xl_hp_path_get(stmdev_ctx_t *ctx, 1045 lis2ds12_fds_slope_t *val); 1046 1047 typedef enum 1048 { 1049 LIS2DS12_SPI_4_WIRE = 0, 1050 LIS2DS12_SPI_3_WIRE = 1, 1051 } lis2ds12_sim_t; 1052 int32_t lis2ds12_spi_mode_set(stmdev_ctx_t *ctx, lis2ds12_sim_t val); 1053 int32_t lis2ds12_spi_mode_get(stmdev_ctx_t *ctx, lis2ds12_sim_t *val); 1054 1055 typedef enum 1056 { 1057 LIS2DS12_I2C_ENABLE = 0, 1058 LIS2DS12_I2C_DISABLE = 1, 1059 } lis2ds12_i2c_disable_t; 1060 int32_t lis2ds12_i2c_interface_set(stmdev_ctx_t *ctx, 1061 lis2ds12_i2c_disable_t val); 1062 int32_t lis2ds12_i2c_interface_get(stmdev_ctx_t *ctx, 1063 lis2ds12_i2c_disable_t *val); 1064 1065 typedef enum 1066 { 1067 LIS2DS12_PULL_UP_CONNECTED = 0, 1068 LIS2DS12_PULL_UP_DISCONNECTED = 1, 1069 } lis2ds12_if_cs_pu_dis_t; 1070 int32_t lis2ds12_cs_mode_set(stmdev_ctx_t *ctx, 1071 lis2ds12_if_cs_pu_dis_t val); 1072 int32_t lis2ds12_cs_mode_get(stmdev_ctx_t *ctx, 1073 lis2ds12_if_cs_pu_dis_t *val); 1074 1075 typedef enum 1076 { 1077 LIS2DS12_PUSH_PULL = 0, 1078 LIS2DS12_OPEN_DRAIN = 1, 1079 } lis2ds12_pp_od_t; 1080 int32_t lis2ds12_pin_mode_set(stmdev_ctx_t *ctx, 1081 lis2ds12_pp_od_t val); 1082 int32_t lis2ds12_pin_mode_get(stmdev_ctx_t *ctx, 1083 lis2ds12_pp_od_t *val); 1084 1085 typedef enum 1086 { 1087 LIS2DS12_ACTIVE_HIGH = 0, 1088 LIS2DS12_ACTIVE_LOW = 1, 1089 } lis2ds12_h_lactive_t; 1090 int32_t lis2ds12_pin_polarity_set(stmdev_ctx_t *ctx, 1091 lis2ds12_h_lactive_t val); 1092 int32_t lis2ds12_pin_polarity_get(stmdev_ctx_t *ctx, 1093 lis2ds12_h_lactive_t *val); 1094 1095 typedef enum 1096 { 1097 LIS2DS12_INT_PULSED = 0, 1098 LIS2DS12_INT_LATCHED = 1, 1099 } lis2ds12_lir_t; 1100 int32_t lis2ds12_int_notification_set(stmdev_ctx_t *ctx, 1101 lis2ds12_lir_t val); 1102 int32_t lis2ds12_int_notification_get(stmdev_ctx_t *ctx, 1103 lis2ds12_lir_t *val); 1104 1105 typedef struct 1106 { 1107 uint8_t int1_drdy : 1; 1108 uint8_t int1_fth : 1; 1109 uint8_t int1_6d : 1; 1110 uint8_t int1_tap : 1; 1111 uint8_t int1_ff : 1; 1112 uint8_t int1_wu : 1; 1113 uint8_t int1_s_tap : 1; 1114 uint8_t int1_master_drdy : 1; 1115 uint8_t int1_fss7 : 1; 1116 } lis2ds12_pin_int1_route_t; 1117 int32_t lis2ds12_pin_int1_route_set(stmdev_ctx_t *ctx, 1118 lis2ds12_pin_int1_route_t val); 1119 int32_t lis2ds12_pin_int1_route_get(stmdev_ctx_t *ctx, 1120 lis2ds12_pin_int1_route_t *val); 1121 1122 typedef struct 1123 { 1124 uint8_t int2_boot : 1; 1125 uint8_t int2_tilt : 1; 1126 uint8_t int2_sig_mot : 1; 1127 uint8_t int2_step_det : 1; 1128 uint8_t int2_fth : 1; 1129 uint8_t int2_drdy : 1; 1130 } lis2ds12_pin_int2_route_t; 1131 int32_t lis2ds12_pin_int2_route_set(stmdev_ctx_t *ctx, 1132 lis2ds12_pin_int2_route_t val); 1133 int32_t lis2ds12_pin_int2_route_get(stmdev_ctx_t *ctx, 1134 lis2ds12_pin_int2_route_t *val); 1135 1136 int32_t lis2ds12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 1137 int32_t lis2ds12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 1138 1139 int32_t lis2ds12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 1140 int32_t lis2ds12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 1141 1142 int32_t lis2ds12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); 1143 int32_t lis2ds12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 1144 1145 int32_t lis2ds12_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); 1146 int32_t lis2ds12_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 1147 1148 int32_t lis2ds12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); 1149 int32_t lis2ds12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 1150 1151 int32_t lis2ds12_tap_detection_on_z_set(stmdev_ctx_t *ctx, 1152 uint8_t val); 1153 int32_t lis2ds12_tap_detection_on_z_get(stmdev_ctx_t *ctx, 1154 uint8_t *val); 1155 1156 int32_t lis2ds12_tap_detection_on_y_set(stmdev_ctx_t *ctx, 1157 uint8_t val); 1158 int32_t lis2ds12_tap_detection_on_y_get(stmdev_ctx_t *ctx, 1159 uint8_t *val); 1160 1161 int32_t lis2ds12_tap_detection_on_x_set(stmdev_ctx_t *ctx, 1162 uint8_t val); 1163 int32_t lis2ds12_tap_detection_on_x_get(stmdev_ctx_t *ctx, 1164 uint8_t *val); 1165 1166 int32_t lis2ds12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 1167 int32_t lis2ds12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 1168 1169 int32_t lis2ds12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); 1170 int32_t lis2ds12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); 1171 1172 int32_t lis2ds12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); 1173 int32_t lis2ds12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); 1174 1175 int32_t lis2ds12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); 1176 int32_t lis2ds12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 1177 1178 typedef enum 1179 { 1180 LIS2DS12_ONLY_SINGLE = 0, 1181 LIS2DS12_ONLY_DOUBLE = 1, 1182 } lis2ds12_single_double_tap_t; 1183 int32_t lis2ds12_tap_mode_set(stmdev_ctx_t *ctx, 1184 lis2ds12_single_double_tap_t val); 1185 int32_t lis2ds12_tap_mode_get(stmdev_ctx_t *ctx, 1186 lis2ds12_single_double_tap_t *val); 1187 1188 int32_t lis2ds12_tap_src_get(stmdev_ctx_t *ctx, 1189 lis2ds12_tap_src_t *val); 1190 1191 typedef enum 1192 { 1193 LIS2DS12_DEG_80 = 0, 1194 LIS2DS12_DEG_70 = 1, 1195 LIS2DS12_DEG_60 = 2, 1196 LIS2DS12_DEG_50 = 3, 1197 } lis2ds12_6d_ths_t; 1198 int32_t lis2ds12_6d_threshold_set(stmdev_ctx_t *ctx, 1199 lis2ds12_6d_ths_t val); 1200 int32_t lis2ds12_6d_threshold_get(stmdev_ctx_t *ctx, 1201 lis2ds12_6d_ths_t *val); 1202 1203 int32_t lis2ds12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); 1204 int32_t lis2ds12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 1205 1206 int32_t lis2ds12_6d_src_get(stmdev_ctx_t *ctx, 1207 lis2ds12_6d_src_t *val); 1208 1209 int32_t lis2ds12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); 1210 int32_t lis2ds12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 1211 1212 int32_t lis2ds12_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 1213 int32_t lis2ds12_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 1214 1215 int32_t lis2ds12_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, 1216 uint8_t val); 1217 int32_t lis2ds12_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, 1218 uint8_t *val); 1219 1220 typedef enum 1221 { 1222 LIS2DS12_BYPASS_MODE = 0, 1223 LIS2DS12_FIFO_MODE = 1, 1224 LIS2DS12_STREAM_TO_FIFO_MODE = 3, 1225 LIS2DS12_BYPASS_TO_STREAM_MODE = 4, 1226 LIS2DS12_STREAM_MODE = 6, 1227 } lis2ds12_fmode_t; 1228 int32_t lis2ds12_fifo_mode_set(stmdev_ctx_t *ctx, 1229 lis2ds12_fmode_t val); 1230 int32_t lis2ds12_fifo_mode_get(stmdev_ctx_t *ctx, 1231 lis2ds12_fmode_t *val); 1232 1233 int32_t lis2ds12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); 1234 int32_t lis2ds12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); 1235 1236 int32_t lis2ds12_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 1237 1238 int32_t lis2ds12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 1239 1240 int32_t lis2ds12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 1241 1242 int32_t lis2ds12_fifo_data_level_get(stmdev_ctx_t *ctx, 1243 uint16_t *val); 1244 1245 int32_t lis2ds12_fifo_src_get(stmdev_ctx_t *ctx, 1246 lis2ds12_fifo_src_t *val); 1247 1248 int32_t lis2ds12_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 1249 int32_t lis2ds12_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 1250 1251 typedef enum 1252 { 1253 LIS2DS12_PEDO_AT_2g = 0, 1254 LIS2DS12_PEDO_AT_4g = 1, 1255 } lis2ds12_pedo4g_t; 1256 int32_t lis2ds12_pedo_full_scale_set(stmdev_ctx_t *ctx, 1257 lis2ds12_pedo4g_t val); 1258 int32_t lis2ds12_pedo_full_scale_get(stmdev_ctx_t *ctx, 1259 lis2ds12_pedo4g_t *val); 1260 1261 int32_t lis2ds12_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val); 1262 int32_t lis2ds12_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 1263 1264 int32_t lis2ds12_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, 1265 uint8_t *val); 1266 1267 int32_t lis2ds12_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); 1268 int32_t lis2ds12_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 1269 1270 int32_t lis2ds12_pedo_debounce_steps_set(stmdev_ctx_t *ctx, 1271 uint8_t val); 1272 int32_t lis2ds12_pedo_debounce_steps_get(stmdev_ctx_t *ctx, 1273 uint8_t *val); 1274 1275 int32_t lis2ds12_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val); 1276 int32_t lis2ds12_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); 1277 1278 int32_t lis2ds12_pedo_steps_period_set(stmdev_ctx_t *ctx, 1279 uint8_t *buff); 1280 int32_t lis2ds12_pedo_steps_period_get(stmdev_ctx_t *ctx, 1281 uint8_t *buff); 1282 int32_t lis2ds12_motion_data_ready_flag_get(stmdev_ctx_t *ctx, 1283 uint8_t *val); 1284 1285 int32_t lis2ds12_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); 1286 int32_t lis2ds12_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 1287 1288 int32_t lis2ds12_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 1289 int32_t lis2ds12_motion_threshold_get(stmdev_ctx_t *ctx, 1290 uint8_t *val); 1291 1292 int32_t lis2ds12_tilt_data_ready_flag_get(stmdev_ctx_t *ctx, 1293 uint8_t *val); 1294 1295 int32_t lis2ds12_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); 1296 int32_t lis2ds12_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 1297 1298 int32_t lis2ds12_module_sens_set(stmdev_ctx_t *ctx, uint8_t val); 1299 int32_t lis2ds12_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 1300 1301 typedef struct 1302 { 1303 lis2ds12_sensorhub1_reg_t sensorhub1_reg; 1304 lis2ds12_sensorhub2_reg_t sensorhub2_reg; 1305 lis2ds12_sensorhub3_reg_t sensorhub3_reg; 1306 lis2ds12_sensorhub4_reg_t sensorhub4_reg; 1307 lis2ds12_sensorhub5_reg_t sensorhub5_reg; 1308 lis2ds12_sensorhub6_reg_t sensorhub6_reg; 1309 } lis2ds12_sh_read_data_raw_t; 1310 int32_t lis2ds12_sh_read_data_raw_get(stmdev_ctx_t *ctx, 1311 lis2ds12_sh_read_data_raw_t *val); 1312 1313 int32_t lis2ds12_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); 1314 int32_t lis2ds12_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); 1315 1316 typedef enum 1317 { 1318 LIS2DS12_EXT_PULL_UP = 0, 1319 LIS2DS12_INTERNAL_PULL_UP = 1, 1320 } lis2ds12_tud_en_t; 1321 int32_t lis2ds12_sh_pin_mode_set(stmdev_ctx_t *ctx, 1322 lis2ds12_tud_en_t val); 1323 int32_t lis2ds12_sh_pin_mode_get(stmdev_ctx_t *ctx, 1324 lis2ds12_tud_en_t *val); 1325 1326 typedef struct 1327 { 1328 uint8_t slv_add; 1329 uint8_t slv_subadd; 1330 uint8_t slv_data; 1331 } lis2ds12_sh_cfg_write_t; 1332 int32_t lis2ds12_sh_cfg_write(stmdev_ctx_t *ctx, 1333 lis2ds12_sh_cfg_write_t *val); 1334 1335 typedef struct 1336 { 1337 uint8_t slv_add; 1338 uint8_t slv_subadd; 1339 uint8_t slv_len; 1340 } lis2ds12_sh_cfg_read_t; 1341 int32_t lis2ds12_sh_slv_cfg_read(stmdev_ctx_t *ctx, 1342 lis2ds12_sh_cfg_read_t *val); 1343 1344 int32_t lis2ds12_sh_slv0_cfg_read_set(stmdev_ctx_t *ctx, uint8_t val); 1345 int32_t lis2ds12_sh_slv0_cfg_read_get(stmdev_ctx_t *ctx, 1346 uint8_t *val); 1347 1348 int32_t lis2ds12_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 1349 1350 /** 1351 * @} 1352 * 1353 */ 1354 1355 #ifdef __cplusplus 1356 } 1357 #endif 1358 1359 #endif /*__LIS2DS12_DRIVER__H */ 1360 1361 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1362
