1 /** 2 ****************************************************************************** 3 * @file lis2dh_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis2dh_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS2DH_REGS_H 23 #define LIS2DH_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS2DH 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS2DH_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ 172 #define LIS2DH_I2C_ADD_L 0x31U 173 #define LIS2DH_I2C_ADD_H 0x33U 174 175 /** Device Identification (Who am I) **/ 176 #define LIS2DH_ID 0x33U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LIS2DH_STATUS_REG_AUX 0x07U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 2; 188 uint8_t tda : 1; 189 uint8_t not_used_02 : 3; 190 uint8_t tor : 1; 191 uint8_t not_used_03 : 1; 192 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 193 uint8_t not_used_03 : 1; 194 uint8_t tor : 1; 195 uint8_t not_used_02 : 3; 196 uint8_t tda : 1; 197 uint8_t not_used_01 : 2; 198 #endif /* DRV_BYTE_ORDER */ 199 } lis2dh_status_reg_aux_t; 200 201 #define LIS2DH_OUT_TEMP_L 0x0CU 202 #define LIS2DH_OUT_TEMP_H 0x0DU 203 #define LIS2DH_INT_COUNTER 0x0EU 204 #define LIS2DH_WHO_AM_I 0x0FU 205 #define LIS2DH_TEMP_CFG_REG 0x1FU 206 typedef struct 207 { 208 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 209 uint8_t not_used_01 : 6; 210 uint8_t temp_en : 2; 211 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 212 uint8_t temp_en : 2; 213 uint8_t not_used_01 : 6; 214 #endif /* DRV_BYTE_ORDER */ 215 } lis2dh_temp_cfg_reg_t; 216 217 #define LIS2DH_CTRL_REG1 0x20U 218 typedef struct 219 { 220 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 221 uint8_t xen : 1; 222 uint8_t yen : 1; 223 uint8_t zen : 1; 224 uint8_t lpen : 1; 225 uint8_t odr : 4; 226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 227 uint8_t odr : 4; 228 uint8_t lpen : 1; 229 uint8_t zen : 1; 230 uint8_t yen : 1; 231 uint8_t xen : 1; 232 #endif /* DRV_BYTE_ORDER */ 233 } lis2dh_ctrl_reg1_t; 234 235 #define LIS2DH_CTRL_REG2 0x21U 236 typedef struct 237 { 238 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 239 uint8_t hp : 3; /* HPCLICK + HPIS[1:2] -> HP */ 240 uint8_t fds : 1; 241 uint8_t hpcf : 2; 242 uint8_t hpm : 2; 243 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 244 uint8_t hpm : 2; 245 uint8_t hpcf : 2; 246 uint8_t fds : 1; 247 uint8_t hp : 3; /* HPCLICK + HPIS[1:2] -> HP */ 248 #endif /* DRV_BYTE_ORDER */ 249 } lis2dh_ctrl_reg2_t; 250 251 #define LIS2DH_CTRL_REG3 0x22U 252 typedef struct 253 { 254 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 255 uint8_t not_used_01 : 1; 256 uint8_t i1_overrun : 1; 257 uint8_t i1_wtm : 1; 258 uint8_t i1_drdy2 : 1; 259 uint8_t i1_drdy1 : 1; 260 uint8_t i1_aoi2 : 1; 261 uint8_t i1_aoi1 : 1; 262 uint8_t i1_click : 1; 263 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 264 uint8_t i1_click : 1; 265 uint8_t i1_aoi1 : 1; 266 uint8_t i1_aoi2 : 1; 267 uint8_t i1_drdy1 : 1; 268 uint8_t i1_drdy2 : 1; 269 uint8_t i1_wtm : 1; 270 uint8_t i1_overrun : 1; 271 uint8_t not_used_01 : 1; 272 #endif /* DRV_BYTE_ORDER */ 273 } lis2dh_ctrl_reg3_t; 274 275 #define LIS2DH_CTRL_REG4 0x23U 276 typedef struct 277 { 278 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 279 uint8_t sim : 1; 280 uint8_t st : 2; 281 uint8_t hr : 1; 282 uint8_t fs : 2; 283 uint8_t ble : 1; 284 uint8_t bdu : 1; 285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 286 uint8_t bdu : 1; 287 uint8_t ble : 1; 288 uint8_t fs : 2; 289 uint8_t hr : 1; 290 uint8_t st : 2; 291 uint8_t sim : 1; 292 #endif /* DRV_BYTE_ORDER */ 293 } lis2dh_ctrl_reg4_t; 294 295 #define LIS2DH_CTRL_REG5 0x24U 296 typedef struct 297 { 298 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 299 uint8_t d4d_int2 : 1; 300 uint8_t lir_int2 : 1; 301 uint8_t d4d_int1 : 1; 302 uint8_t lir_int1 : 1; 303 uint8_t not_used_01 : 2; 304 uint8_t fifo_en : 1; 305 uint8_t boot : 1; 306 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 307 uint8_t boot : 1; 308 uint8_t fifo_en : 1; 309 uint8_t not_used_01 : 2; 310 uint8_t lir_int1 : 1; 311 uint8_t d4d_int1 : 1; 312 uint8_t lir_int2 : 1; 313 uint8_t d4d_int2 : 1; 314 #endif /* DRV_BYTE_ORDER */ 315 } lis2dh_ctrl_reg5_t; 316 317 #define LIS2DH_CTRL_REG6 0x25U 318 typedef struct 319 { 320 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 321 uint8_t not_used_01 : 1; 322 uint8_t h_lactive : 1; 323 uint8_t not_used_02 : 1; 324 uint8_t p2_act : 1; 325 uint8_t boot_i2 : 1; 326 uint8_t i2_int2 : 1; 327 uint8_t i2_int1 : 1; 328 uint8_t i2_clicken : 1; 329 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 330 uint8_t i2_clicken : 1; 331 uint8_t i2_int1 : 1; 332 uint8_t i2_int2 : 1; 333 uint8_t boot_i2 : 1; 334 uint8_t p2_act : 1; 335 uint8_t not_used_02 : 1; 336 uint8_t h_lactive : 1; 337 uint8_t not_used_01 : 1; 338 #endif /* DRV_BYTE_ORDER */ 339 } lis2dh_ctrl_reg6_t; 340 341 #define LIS2DH_REFERENCE 0x26U 342 #define LIS2DH_STATUS_REG 0x27U 343 typedef struct 344 { 345 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 346 uint8_t xda : 1; 347 uint8_t yda : 1; 348 uint8_t zda : 1; 349 uint8_t zyxda : 1; 350 uint8_t _xor : 1; 351 uint8_t yor : 1; 352 uint8_t zor : 1; 353 uint8_t zyxor : 1; 354 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 355 uint8_t zyxor : 1; 356 uint8_t zor : 1; 357 uint8_t yor : 1; 358 uint8_t _xor : 1; 359 uint8_t zyxda : 1; 360 uint8_t zda : 1; 361 uint8_t yda : 1; 362 uint8_t xda : 1; 363 #endif /* DRV_BYTE_ORDER */ 364 } lis2dh_status_reg_t; 365 366 #define LIS2DH_OUT_X_L 0x28U 367 #define LIS2DH_OUT_X_H 0x29U 368 #define LIS2DH_OUT_Y_L 0x2AU 369 #define LIS2DH_OUT_Y_H 0x2BU 370 #define LIS2DH_OUT_Z_L 0x2CU 371 #define LIS2DH_OUT_Z_H 0x2DU 372 #define LIS2DH_FIFO_CTRL_REG 0x2EU 373 typedef struct 374 { 375 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 376 uint8_t fth : 5; 377 uint8_t tr : 1; 378 uint8_t fm : 2; 379 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 380 uint8_t fm : 2; 381 uint8_t tr : 1; 382 uint8_t fth : 5; 383 #endif /* DRV_BYTE_ORDER */ 384 } lis2dh_fifo_ctrl_reg_t; 385 386 #define LIS2DH_FIFO_SRC_REG 0x2FU 387 typedef struct 388 { 389 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 390 uint8_t fss : 5; 391 uint8_t empty : 1; 392 uint8_t ovrn_fifo : 1; 393 uint8_t wtm : 1; 394 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 395 uint8_t wtm : 1; 396 uint8_t ovrn_fifo : 1; 397 uint8_t empty : 1; 398 uint8_t fss : 5; 399 #endif /* DRV_BYTE_ORDER */ 400 } lis2dh_fifo_src_reg_t; 401 402 #define LIS2DH_INT1_CFG 0x30U 403 typedef struct 404 { 405 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 406 uint8_t xlie : 1; 407 uint8_t xhie : 1; 408 uint8_t ylie : 1; 409 uint8_t yhie : 1; 410 uint8_t zlie : 1; 411 uint8_t zhie : 1; 412 uint8_t _6d : 1; 413 uint8_t aoi : 1; 414 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 415 uint8_t aoi : 1; 416 uint8_t _6d : 1; 417 uint8_t zhie : 1; 418 uint8_t zlie : 1; 419 uint8_t yhie : 1; 420 uint8_t ylie : 1; 421 uint8_t xhie : 1; 422 uint8_t xlie : 1; 423 #endif /* DRV_BYTE_ORDER */ 424 } lis2dh_int1_cfg_t; 425 426 #define LIS2DH_INT1_SRC 0x31U 427 typedef struct 428 { 429 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 430 uint8_t xl : 1; 431 uint8_t xh : 1; 432 uint8_t yl : 1; 433 uint8_t yh : 1; 434 uint8_t zl : 1; 435 uint8_t zh : 1; 436 uint8_t ia : 1; 437 uint8_t not_used_01 : 1; 438 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 439 uint8_t not_used_01 : 1; 440 uint8_t ia : 1; 441 uint8_t zh : 1; 442 uint8_t zl : 1; 443 uint8_t yh : 1; 444 uint8_t yl : 1; 445 uint8_t xh : 1; 446 uint8_t xl : 1; 447 #endif /* DRV_BYTE_ORDER */ 448 } lis2dh_int1_src_t; 449 450 #define LIS2DH_INT1_THS 0x32U 451 typedef struct 452 { 453 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 454 uint8_t ths : 7; 455 uint8_t not_used_01 : 1; 456 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 457 uint8_t not_used_01 : 1; 458 uint8_t ths : 7; 459 #endif /* DRV_BYTE_ORDER */ 460 } lis2dh_int1_ths_t; 461 462 #define LIS2DH_INT1_DURATION 0x33U 463 typedef struct 464 { 465 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 466 uint8_t d : 7; 467 uint8_t not_used_01 : 1; 468 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 469 uint8_t not_used_01 : 1; 470 uint8_t d : 7; 471 #endif /* DRV_BYTE_ORDER */ 472 } lis2dh_int1_duration_t; 473 474 #define LIS2DH_INT2_CFG 0x34U 475 typedef struct 476 { 477 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 478 uint8_t xlie : 1; 479 uint8_t xhie : 1; 480 uint8_t ylie : 1; 481 uint8_t yhie : 1; 482 uint8_t zlie : 1; 483 uint8_t zhie : 1; 484 uint8_t _6d : 1; 485 uint8_t aoi : 1; 486 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 487 uint8_t aoi : 1; 488 uint8_t _6d : 1; 489 uint8_t zhie : 1; 490 uint8_t zlie : 1; 491 uint8_t yhie : 1; 492 uint8_t ylie : 1; 493 uint8_t xhie : 1; 494 uint8_t xlie : 1; 495 #endif /* DRV_BYTE_ORDER */ 496 } lis2dh_int2_cfg_t; 497 498 #define LIS2DH_INT2_SRC 0x35U 499 typedef struct 500 { 501 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 502 uint8_t xl : 1; 503 uint8_t xh : 1; 504 uint8_t yl : 1; 505 uint8_t yh : 1; 506 uint8_t zl : 1; 507 uint8_t zh : 1; 508 uint8_t ia : 1; 509 uint8_t not_used_01 : 1; 510 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 511 uint8_t not_used_01 : 1; 512 uint8_t ia : 1; 513 uint8_t zh : 1; 514 uint8_t zl : 1; 515 uint8_t yh : 1; 516 uint8_t yl : 1; 517 uint8_t xh : 1; 518 uint8_t xl : 1; 519 #endif /* DRV_BYTE_ORDER */ 520 } lis2dh_int2_src_t; 521 522 #define LIS2DH_INT2_THS 0x36U 523 typedef struct 524 { 525 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 526 uint8_t ths : 7; 527 uint8_t not_used_01 : 1; 528 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 529 uint8_t not_used_01 : 1; 530 uint8_t ths : 7; 531 #endif /* DRV_BYTE_ORDER */ 532 } lis2dh_int2_ths_t; 533 534 #define LIS2DH_INT2_DURATION 0x37U 535 typedef struct 536 { 537 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 538 uint8_t d : 7; 539 uint8_t not_used_01 : 1; 540 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 541 uint8_t not_used_01 : 1; 542 uint8_t d : 7; 543 #endif /* DRV_BYTE_ORDER */ 544 } lis2dh_int2_duration_t; 545 546 #define LIS2DH_CLICK_CFG 0x38U 547 typedef struct 548 { 549 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 550 uint8_t xs : 1; 551 uint8_t xd : 1; 552 uint8_t ys : 1; 553 uint8_t yd : 1; 554 uint8_t zs : 1; 555 uint8_t zd : 1; 556 uint8_t not_used_01 : 2; 557 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 558 uint8_t not_used_01 : 2; 559 uint8_t zd : 1; 560 uint8_t zs : 1; 561 uint8_t yd : 1; 562 uint8_t ys : 1; 563 uint8_t xd : 1; 564 uint8_t xs : 1; 565 #endif /* DRV_BYTE_ORDER */ 566 } lis2dh_click_cfg_t; 567 568 #define LIS2DH_CLICK_SRC 0x39U 569 typedef struct 570 { 571 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 572 uint8_t x : 1; 573 uint8_t y : 1; 574 uint8_t z : 1; 575 uint8_t sign : 1; 576 uint8_t sclick : 1; 577 uint8_t dclick : 1; 578 uint8_t ia : 1; 579 uint8_t not_used_01 : 1; 580 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 581 uint8_t not_used_01 : 1; 582 uint8_t ia : 1; 583 uint8_t dclick : 1; 584 uint8_t sclick : 1; 585 uint8_t sign : 1; 586 uint8_t z : 1; 587 uint8_t y : 1; 588 uint8_t x : 1; 589 #endif /* DRV_BYTE_ORDER */ 590 } lis2dh_click_src_t; 591 592 #define LIS2DH_CLICK_THS 0x3AU 593 typedef struct 594 { 595 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 596 uint8_t ths : 7; 597 uint8_t not_used_01 : 1; 598 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 599 uint8_t not_used_01 : 1; 600 uint8_t ths : 7; 601 #endif /* DRV_BYTE_ORDER */ 602 } lis2dh_click_ths_t; 603 604 #define LIS2DH_TIME_LIMIT 0x3BU 605 typedef struct 606 { 607 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 608 uint8_t tli : 7; 609 uint8_t not_used_01 : 1; 610 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 611 uint8_t not_used_01 : 1; 612 uint8_t tli : 7; 613 #endif /* DRV_BYTE_ORDER */ 614 } lis2dh_time_limit_t; 615 616 #define LIS2DH_TIME_LATENCY 0x3CU 617 typedef struct 618 { 619 uint8_t tla : 8; 620 } lis2dh_time_latency_t; 621 622 #define LIS2DH_TIME_WINDOW 0x3DU 623 typedef struct 624 { 625 uint8_t tw : 8; 626 } lis2dh_time_window_t; 627 628 #define LIS2DH_ACT_THS 0x3EU 629 typedef struct 630 { 631 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 632 uint8_t acth : 7; 633 uint8_t not_used_01 : 1; 634 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 635 uint8_t not_used_01 : 1; 636 uint8_t acth : 7; 637 #endif /* DRV_BYTE_ORDER */ 638 } lis2dh_act_ths_t; 639 640 #define LIS2DH_ACT_DUR 0x3FU 641 typedef struct 642 { 643 uint8_t actd : 8; 644 } lis2dh_act_dur_t; 645 646 /** 647 * @defgroup LIS2DH_Register_Union 648 * @brief This union group all the registers having a bit-field 649 * description. 650 * This union is useful but it's not needed by the driver. 651 * 652 * REMOVING this union you are compliant with: 653 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 654 * 655 * @{ 656 * 657 */ 658 typedef union 659 { 660 lis2dh_status_reg_aux_t status_reg_aux; 661 lis2dh_temp_cfg_reg_t temp_cfg_reg; 662 lis2dh_ctrl_reg1_t ctrl_reg1; 663 lis2dh_ctrl_reg2_t ctrl_reg2; 664 lis2dh_ctrl_reg3_t ctrl_reg3; 665 lis2dh_ctrl_reg4_t ctrl_reg4; 666 lis2dh_ctrl_reg5_t ctrl_reg5; 667 lis2dh_ctrl_reg6_t ctrl_reg6; 668 lis2dh_status_reg_t status_reg; 669 lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; 670 lis2dh_fifo_src_reg_t fifo_src_reg; 671 lis2dh_int1_cfg_t int1_cfg; 672 lis2dh_int1_src_t int1_src; 673 lis2dh_int1_ths_t int1_ths; 674 lis2dh_int1_duration_t int1_duration; 675 lis2dh_int2_cfg_t int2_cfg; 676 lis2dh_int2_src_t int2_src; 677 lis2dh_int2_ths_t int2_ths; 678 lis2dh_int2_duration_t int2_duration; 679 lis2dh_click_cfg_t click_cfg; 680 lis2dh_click_src_t click_src; 681 lis2dh_click_ths_t click_ths; 682 lis2dh_time_limit_t time_limit; 683 lis2dh_time_latency_t time_latency; 684 lis2dh_time_window_t time_window; 685 lis2dh_act_ths_t act_ths; 686 lis2dh_act_dur_t act_dur; 687 bitwise_t bitwise; 688 uint8_t byte; 689 } lis2dh_reg_t; 690 691 /** 692 * @} 693 * 694 */ 695 696 #ifndef __weak 697 #define __weak __attribute__((weak)) 698 #endif /* __weak */ 699 700 /* 701 * These are the basic platform dependent I/O routines to read 702 * and write device registers connected on a standard bus. 703 * The driver keeps offering a default implementation based on function 704 * pointers to read/write routines for backward compatibility. 705 * The __weak directive allows the final application to overwrite 706 * them with a custom implementation. 707 */ 708 709 int32_t lis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 710 uint8_t *data, 711 uint16_t len); 712 int32_t lis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 713 uint8_t *data, 714 uint16_t len); 715 716 float_t lis2dh_from_fs2_hr_to_mg(int16_t lsb); 717 float_t lis2dh_from_fs4_hr_to_mg(int16_t lsb); 718 float_t lis2dh_from_fs8_hr_to_mg(int16_t lsb); 719 float_t lis2dh_from_fs16_hr_to_mg(int16_t lsb); 720 float_t lis2dh_from_lsb_hr_to_celsius(int16_t lsb); 721 722 float_t lis2dh_from_fs2_nm_to_mg(int16_t lsb); 723 float_t lis2dh_from_fs4_nm_to_mg(int16_t lsb); 724 float_t lis2dh_from_fs8_nm_to_mg(int16_t lsb); 725 float_t lis2dh_from_fs16_nm_to_mg(int16_t lsb); 726 float_t lis2dh_from_lsb_nm_to_celsius(int16_t lsb); 727 728 float_t lis2dh_from_fs2_lp_to_mg(int16_t lsb); 729 float_t lis2dh_from_fs4_lp_to_mg(int16_t lsb); 730 float_t lis2dh_from_fs8_lp_to_mg(int16_t lsb); 731 float_t lis2dh_from_fs16_lp_to_mg(int16_t lsb); 732 float_t lis2dh_from_lsb_lp_to_celsius(int16_t lsb); 733 734 int32_t lis2dh_int_count_get(stmdev_ctx_t *ctx, uint8_t *val); 735 736 int32_t lis2dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff); 737 738 int32_t lis2dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 739 740 int32_t lis2dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); 741 742 int32_t lis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 743 744 typedef enum 745 { 746 LIS2DH_TEMP_DISABLE = 0, 747 LIS2DH_TEMP_ENABLE = 3, 748 } lis2dh_temp_en_t; 749 int32_t lis2dh_temperature_meas_set(stmdev_ctx_t *ctx, 750 lis2dh_temp_en_t val); 751 int32_t lis2dh_temperature_meas_get(stmdev_ctx_t *ctx, 752 lis2dh_temp_en_t *val); 753 754 typedef enum 755 { 756 LIS2DH_HR_12bit = 0, 757 LIS2DH_NM_10bit = 1, 758 LIS2DH_LP_8bit = 2, 759 } lis2dh_op_md_t; 760 int32_t lis2dh_operating_mode_set(stmdev_ctx_t *ctx, 761 lis2dh_op_md_t val); 762 int32_t lis2dh_operating_mode_get(stmdev_ctx_t *ctx, 763 lis2dh_op_md_t *val); 764 765 typedef enum 766 { 767 LIS2DH_POWER_DOWN = 0x00, 768 LIS2DH_ODR_1Hz = 0x01, 769 LIS2DH_ODR_10Hz = 0x02, 770 LIS2DH_ODR_25Hz = 0x03, 771 LIS2DH_ODR_50Hz = 0x04, 772 LIS2DH_ODR_100Hz = 0x05, 773 LIS2DH_ODR_200Hz = 0x06, 774 LIS2DH_ODR_400Hz = 0x07, 775 LIS2DH_ODR_1kHz620_LP = 0x08, 776 LIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, 777 } lis2dh_odr_t; 778 int32_t lis2dh_data_rate_set(stmdev_ctx_t *ctx, lis2dh_odr_t val); 779 int32_t lis2dh_data_rate_get(stmdev_ctx_t *ctx, 780 lis2dh_odr_t *val); 781 782 int32_t lis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, 783 uint8_t val); 784 int32_t lis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, 785 uint8_t *val); 786 787 typedef enum 788 { 789 LIS2DH_AGGRESSIVE = 0, 790 LIS2DH_STRONG = 1, 791 LIS2DH_MEDIUM = 2, 792 LIS2DH_LIGHT = 3, 793 } lis2dh_hpcf_t; 794 int32_t lis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, 795 lis2dh_hpcf_t val); 796 int32_t lis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, 797 lis2dh_hpcf_t *val); 798 799 typedef enum 800 { 801 LIS2DH_NORMAL_WITH_RST = 0, 802 LIS2DH_REFERENCE_MODE = 1, 803 LIS2DH_NORMAL = 2, 804 LIS2DH_AUTORST_ON_INT = 3, 805 } lis2dh_hpm_t; 806 int32_t lis2dh_high_pass_mode_set(stmdev_ctx_t *ctx, 807 lis2dh_hpm_t val); 808 int32_t lis2dh_high_pass_mode_get(stmdev_ctx_t *ctx, 809 lis2dh_hpm_t *val); 810 811 typedef enum 812 { 813 LIS2DH_2g = 0, 814 LIS2DH_4g = 1, 815 LIS2DH_8g = 2, 816 LIS2DH_16g = 3, 817 } lis2dh_fs_t; 818 int32_t lis2dh_full_scale_set(stmdev_ctx_t *ctx, lis2dh_fs_t val); 819 int32_t lis2dh_full_scale_get(stmdev_ctx_t *ctx, 820 lis2dh_fs_t *val); 821 822 int32_t lis2dh_block_data_update_set(stmdev_ctx_t *ctx, 823 uint8_t val); 824 int32_t lis2dh_block_data_update_get(stmdev_ctx_t *ctx, 825 uint8_t *val); 826 827 int32_t lis2dh_filter_reference_set(stmdev_ctx_t *ctx, 828 uint8_t *buff); 829 int32_t lis2dh_filter_reference_get(stmdev_ctx_t *ctx, 830 uint8_t *buff); 831 832 int32_t lis2dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 833 834 int32_t lis2dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); 835 836 int32_t lis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, 837 int16_t *val); 838 839 int32_t lis2dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 840 841 typedef enum 842 { 843 LIS2DH_ST_DISABLE = 0, 844 LIS2DH_ST_POSITIVE = 1, 845 LIS2DH_ST_NEGATIVE = 2, 846 } lis2dh_st_t; 847 int32_t lis2dh_self_test_set(stmdev_ctx_t *ctx, lis2dh_st_t val); 848 int32_t lis2dh_self_test_get(stmdev_ctx_t *ctx, lis2dh_st_t *val); 849 850 typedef enum 851 { 852 LIS2DH_LSB_AT_LOW_ADD = 0, 853 LIS2DH_MSB_AT_LOW_ADD = 1, 854 } lis2dh_ble_t; 855 int32_t lis2dh_data_format_set(stmdev_ctx_t *ctx, 856 lis2dh_ble_t val); 857 int32_t lis2dh_data_format_get(stmdev_ctx_t *ctx, 858 lis2dh_ble_t *val); 859 860 int32_t lis2dh_boot_set(stmdev_ctx_t *ctx, uint8_t val); 861 int32_t lis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 862 863 int32_t lis2dh_status_get(stmdev_ctx_t *ctx, 864 lis2dh_status_reg_t *val); 865 866 int32_t lis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx, 867 lis2dh_int1_cfg_t *val); 868 int32_t lis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx, 869 lis2dh_int1_cfg_t *val); 870 871 int32_t lis2dh_int1_gen_source_get(stmdev_ctx_t *ctx, 872 lis2dh_int1_src_t *val); 873 874 int32_t lis2dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, 875 uint8_t val); 876 int32_t lis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, 877 uint8_t *val); 878 879 int32_t lis2dh_int1_gen_duration_set(stmdev_ctx_t *ctx, 880 uint8_t val); 881 int32_t lis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx, 882 uint8_t *val); 883 884 int32_t lis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx, 885 lis2dh_int2_cfg_t *val); 886 int32_t lis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx, 887 lis2dh_int2_cfg_t *val); 888 889 int32_t lis2dh_int2_gen_source_get(stmdev_ctx_t *ctx, 890 lis2dh_int2_src_t *val); 891 892 int32_t lis2dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, 893 uint8_t val); 894 int32_t lis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, 895 uint8_t *val); 896 897 int32_t lis2dh_int2_gen_duration_set(stmdev_ctx_t *ctx, 898 uint8_t val); 899 int32_t lis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, 900 uint8_t *val); 901 902 typedef enum 903 { 904 LIS2DH_DISC_FROM_INT_GENERATOR = 0, 905 LIS2DH_ON_INT1_GEN = 1, 906 LIS2DH_ON_INT2_GEN = 2, 907 LIS2DH_ON_TAP_GEN = 4, 908 LIS2DH_ON_INT1_INT2_GEN = 3, 909 LIS2DH_ON_INT1_TAP_GEN = 5, 910 LIS2DH_ON_INT2_TAP_GEN = 6, 911 LIS2DH_ON_INT1_INT2_TAP_GEN = 7, 912 } lis2dh_hp_t; 913 int32_t lis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, 914 lis2dh_hp_t val); 915 int32_t lis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, 916 lis2dh_hp_t *val); 917 918 int32_t lis2dh_pin_int1_config_set(stmdev_ctx_t *ctx, 919 lis2dh_ctrl_reg3_t *val); 920 int32_t lis2dh_pin_int1_config_get(stmdev_ctx_t *ctx, 921 lis2dh_ctrl_reg3_t *val); 922 923 int32_t lis2dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, 924 uint8_t val); 925 int32_t lis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, 926 uint8_t *val); 927 928 typedef enum 929 { 930 LIS2DH_INT2_PULSED = 0, 931 LIS2DH_INT2_LATCHED = 1, 932 } lis2dh_lir_int2_t; 933 int32_t lis2dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, 934 lis2dh_lir_int2_t val); 935 int32_t lis2dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, 936 lis2dh_lir_int2_t *val); 937 938 int32_t lis2dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, 939 uint8_t val); 940 int32_t lis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, 941 uint8_t *val); 942 943 typedef enum 944 { 945 LIS2DH_INT1_PULSED = 0, 946 LIS2DH_INT1_LATCHED = 1, 947 } lis2dh_lir_int1_t; 948 int32_t lis2dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, 949 lis2dh_lir_int1_t val); 950 int32_t lis2dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, 951 lis2dh_lir_int1_t *val); 952 953 int32_t lis2dh_pin_int2_config_set(stmdev_ctx_t *ctx, 954 lis2dh_ctrl_reg6_t *val); 955 int32_t lis2dh_pin_int2_config_get(stmdev_ctx_t *ctx, 956 lis2dh_ctrl_reg6_t *val); 957 958 int32_t lis2dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val); 959 int32_t lis2dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); 960 961 int32_t lis2dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); 962 int32_t lis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); 963 964 typedef enum 965 { 966 LIS2DH_INT1_GEN = 0, 967 LIS2DH_INT2_GEN = 1, 968 } lis2dh_tr_t; 969 int32_t lis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, 970 lis2dh_tr_t val); 971 int32_t lis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, 972 lis2dh_tr_t *val); 973 974 typedef enum 975 { 976 LIS2DH_BYPASS_MODE = 0, 977 LIS2DH_FIFO_MODE = 1, 978 LIS2DH_DYNAMIC_STREAM_MODE = 2, 979 LIS2DH_STREAM_TO_FIFO_MODE = 3, 980 } lis2dh_fm_t; 981 int32_t lis2dh_fifo_mode_set(stmdev_ctx_t *ctx, lis2dh_fm_t val); 982 int32_t lis2dh_fifo_mode_get(stmdev_ctx_t *ctx, lis2dh_fm_t *val); 983 984 int32_t lis2dh_fifo_status_get(stmdev_ctx_t *ctx, 985 lis2dh_fifo_src_reg_t *val); 986 987 int32_t lis2dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); 988 989 int32_t lis2dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 990 991 int32_t lis2dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 992 993 int32_t lis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 994 995 int32_t lis2dh_tap_conf_set(stmdev_ctx_t *ctx, 996 lis2dh_click_cfg_t *val); 997 int32_t lis2dh_tap_conf_get(stmdev_ctx_t *ctx, 998 lis2dh_click_cfg_t *val); 999 1000 int32_t lis2dh_tap_source_get(stmdev_ctx_t *ctx, 1001 lis2dh_click_src_t *val); 1002 1003 int32_t lis2dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 1004 int32_t lis2dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 1005 1006 int32_t lis2dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val); 1007 int32_t lis2dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 1008 1009 int32_t lis2dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val); 1010 int32_t lis2dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 1011 1012 int32_t lis2dh_double_tap_timeout_set(stmdev_ctx_t *ctx, 1013 uint8_t val); 1014 int32_t lis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx, 1015 uint8_t *val); 1016 1017 int32_t lis2dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 1018 int32_t lis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 1019 1020 int32_t lis2dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val); 1021 int32_t lis2dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); 1022 1023 typedef enum 1024 { 1025 LIS2DH_SPI_4_WIRE = 0, 1026 LIS2DH_SPI_3_WIRE = 1, 1027 } lis2dh_sim_t; 1028 int32_t lis2dh_spi_mode_set(stmdev_ctx_t *ctx, lis2dh_sim_t val); 1029 int32_t lis2dh_spi_mode_get(stmdev_ctx_t *ctx, lis2dh_sim_t *val); 1030 1031 /** 1032 * @} 1033 * 1034 */ 1035 1036 #ifdef __cplusplus 1037 } 1038 #endif 1039 1040 #endif /* LIS2DH_REGS_H */ 1041 1042 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1043
