1 /** 2 ****************************************************************************** 3 * @file lis2de12_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis2de12_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS2DE12_REGS_H 23 #define LIS2DE12_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS2DE12 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS2DE12_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ 172 #define LIS2DE12_I2C_ADD_L 0x31U 173 #define LIS2DE12_I2C_ADD_H 0x33U 174 175 /** Device Identification (Who am I) **/ 176 #define LIS2DE12_ID 0x33U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LIS2DE12_STATUS_REG_AUX 0x07U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 2; 188 uint8_t tda : 1; 189 uint8_t not_used_02 : 3; 190 uint8_t tor : 1; 191 uint8_t not_used_03 : 1; 192 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 193 uint8_t not_used_03 : 1; 194 uint8_t tor : 1; 195 uint8_t not_used_02 : 3; 196 uint8_t tda : 1; 197 uint8_t not_used_01 : 2; 198 #endif /* DRV_BYTE_ORDER */ 199 } lis2de12_status_reg_aux_t; 200 201 #define LIS2DE12_OUT_TEMP_L 0x0CU 202 #define LIS2DE12_OUT_TEMP_H 0x0DU 203 #define LIS2DE12_WHO_AM_I 0x0FU 204 205 #define LIS2DE12_CTRL_REG0 0x1EU 206 typedef struct 207 { 208 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 209 uint8_t not_used_01 : 7; 210 uint8_t sdo_pu_disc : 1; 211 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 212 uint8_t sdo_pu_disc : 1; 213 uint8_t not_used_01 : 7; 214 #endif /* DRV_BYTE_ORDER */ 215 } lis2de12_ctrl_reg0_t; 216 217 #define LIS2DE12_TEMP_CFG_REG 0x1FU 218 typedef struct 219 { 220 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 221 uint8_t not_used_01 : 6; 222 uint8_t temp_en : 2; 223 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 224 uint8_t temp_en : 2; 225 uint8_t not_used_01 : 6; 226 #endif /* DRV_BYTE_ORDER */ 227 } lis2de12_temp_cfg_reg_t; 228 229 #define LIS2DE12_CTRL_REG1 0x20U 230 typedef struct 231 { 232 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 233 uint8_t xen : 1; 234 uint8_t yen : 1; 235 uint8_t zen : 1; 236 uint8_t lpen : 1; 237 uint8_t odr : 4; 238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 239 uint8_t odr : 4; 240 uint8_t lpen : 1; 241 uint8_t zen : 1; 242 uint8_t yen : 1; 243 uint8_t xen : 1; 244 #endif /* DRV_BYTE_ORDER */ 245 } lis2de12_ctrl_reg1_t; 246 247 #define LIS2DE12_CTRL_REG2 0x21U 248 typedef struct 249 { 250 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 251 uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ 252 uint8_t fds : 1; 253 uint8_t hpcf : 2; 254 uint8_t hpm : 2; 255 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 256 uint8_t hpm : 2; 257 uint8_t hpcf : 2; 258 uint8_t fds : 1; 259 uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ 260 #endif /* DRV_BYTE_ORDER */ 261 } lis2de12_ctrl_reg2_t; 262 263 #define LIS2DE12_CTRL_REG3 0x22U 264 typedef struct 265 { 266 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 267 uint8_t not_used_01 : 1; 268 uint8_t i1_overrun : 1; 269 uint8_t i1_wtm : 1; 270 uint8_t not_used_02 : 1; 271 uint8_t i1_zyxda : 1; 272 uint8_t i1_ia2 : 1; 273 uint8_t i1_ia1 : 1; 274 uint8_t i1_click : 1; 275 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 276 uint8_t i1_click : 1; 277 uint8_t i1_ia1 : 1; 278 uint8_t i1_ia2 : 1; 279 uint8_t i1_zyxda : 1; 280 uint8_t not_used_02 : 1; 281 uint8_t i1_wtm : 1; 282 uint8_t i1_overrun : 1; 283 uint8_t not_used_01 : 1; 284 #endif /* DRV_BYTE_ORDER */ 285 } lis2de12_ctrl_reg3_t; 286 287 #define LIS2DE12_CTRL_REG4 0x23U 288 typedef struct 289 { 290 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 291 uint8_t sim : 1; 292 uint8_t st : 2; 293 uint8_t not_used_01 : 1; 294 uint8_t fs : 2; 295 uint8_t not_used_02 : 1; 296 uint8_t bdu : 1; 297 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 298 uint8_t bdu : 1; 299 uint8_t not_used_02 : 1; 300 uint8_t fs : 2; 301 uint8_t not_used_01 : 1; 302 uint8_t st : 2; 303 uint8_t sim : 1; 304 #endif /* DRV_BYTE_ORDER */ 305 } lis2de12_ctrl_reg4_t; 306 307 #define LIS2DE12_CTRL_REG5 0x24U 308 typedef struct 309 { 310 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 311 uint8_t d4d_int2 : 1; 312 uint8_t lir_int2 : 1; 313 uint8_t d4d_int1 : 1; 314 uint8_t lir_int1 : 1; 315 uint8_t not_used_01 : 2; 316 uint8_t fifo_en : 1; 317 uint8_t boot : 1; 318 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 319 uint8_t boot : 1; 320 uint8_t fifo_en : 1; 321 uint8_t not_used_01 : 2; 322 uint8_t lir_int1 : 1; 323 uint8_t d4d_int1 : 1; 324 uint8_t lir_int2 : 1; 325 uint8_t d4d_int2 : 1; 326 #endif /* DRV_BYTE_ORDER */ 327 } lis2de12_ctrl_reg5_t; 328 329 #define LIS2DE12_CTRL_REG6 0x25U 330 typedef struct 331 { 332 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 333 uint8_t not_used_01 : 1; 334 uint8_t int_polarity : 1; 335 uint8_t not_used_02 : 1; 336 uint8_t i2_act : 1; 337 uint8_t i2_boot : 1; 338 uint8_t i2_ia2 : 1; 339 uint8_t i2_ia1 : 1; 340 uint8_t i2_click : 1; 341 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 342 uint8_t i2_click : 1; 343 uint8_t i2_ia1 : 1; 344 uint8_t i2_ia2 : 1; 345 uint8_t i2_boot : 1; 346 uint8_t i2_act : 1; 347 uint8_t not_used_02 : 1; 348 uint8_t int_polarity : 1; 349 uint8_t not_used_01 : 1; 350 #endif /* DRV_BYTE_ORDER */ 351 } lis2de12_ctrl_reg6_t; 352 353 #define LIS2DE12_REFERENCE 0x26U 354 #define LIS2DE12_STATUS_REG 0x27U 355 typedef struct 356 { 357 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 358 uint8_t xda : 1; 359 uint8_t yda : 1; 360 uint8_t zda : 1; 361 uint8_t zyxda : 1; 362 uint8_t _xor : 1; 363 uint8_t yor : 1; 364 uint8_t zor : 1; 365 uint8_t zyxor : 1; 366 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 367 uint8_t zyxor : 1; 368 uint8_t zor : 1; 369 uint8_t yor : 1; 370 uint8_t _xor : 1; 371 uint8_t zyxda : 1; 372 uint8_t zda : 1; 373 uint8_t yda : 1; 374 uint8_t xda : 1; 375 #endif /* DRV_BYTE_ORDER */ 376 } lis2de12_status_reg_t; 377 378 #define LIS2DE12_FIFO_READ_START 0x28U 379 #define LIS2DE12_OUT_X_H 0x29U 380 #define LIS2DE12_OUT_Y_H 0x2BU 381 #define LIS2DE12_OUT_Z_H 0x2DU 382 #define LIS2DE12_FIFO_CTRL_REG 0x2EU 383 typedef struct 384 { 385 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 386 uint8_t fth : 5; 387 uint8_t tr : 1; 388 uint8_t fm : 2; 389 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 390 uint8_t fm : 2; 391 uint8_t tr : 1; 392 uint8_t fth : 5; 393 #endif /* DRV_BYTE_ORDER */ 394 } lis2de12_fifo_ctrl_reg_t; 395 396 #define LIS2DE12_FIFO_SRC_REG 0x2FU 397 typedef struct 398 { 399 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 400 uint8_t fss : 5; 401 uint8_t empty : 1; 402 uint8_t ovrn_fifo : 1; 403 uint8_t wtm : 1; 404 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 405 uint8_t wtm : 1; 406 uint8_t ovrn_fifo : 1; 407 uint8_t empty : 1; 408 uint8_t fss : 5; 409 #endif /* DRV_BYTE_ORDER */ 410 } lis2de12_fifo_src_reg_t; 411 412 #define LIS2DE12_INT1_CFG 0x30U 413 typedef struct 414 { 415 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 416 uint8_t xlie : 1; 417 uint8_t xhie : 1; 418 uint8_t ylie : 1; 419 uint8_t yhie : 1; 420 uint8_t zlie : 1; 421 uint8_t zhie : 1; 422 uint8_t _6d : 1; 423 uint8_t aoi : 1; 424 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 425 uint8_t aoi : 1; 426 uint8_t _6d : 1; 427 uint8_t zhie : 1; 428 uint8_t zlie : 1; 429 uint8_t yhie : 1; 430 uint8_t ylie : 1; 431 uint8_t xhie : 1; 432 uint8_t xlie : 1; 433 #endif /* DRV_BYTE_ORDER */ 434 } lis2de12_int1_cfg_t; 435 436 #define LIS2DE12_INT1_SRC 0x31U 437 typedef struct 438 { 439 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 440 uint8_t xl : 1; 441 uint8_t xh : 1; 442 uint8_t yl : 1; 443 uint8_t yh : 1; 444 uint8_t zl : 1; 445 uint8_t zh : 1; 446 uint8_t ia : 1; 447 uint8_t not_used_01 : 1; 448 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 449 uint8_t not_used_01 : 1; 450 uint8_t ia : 1; 451 uint8_t zh : 1; 452 uint8_t zl : 1; 453 uint8_t yh : 1; 454 uint8_t yl : 1; 455 uint8_t xh : 1; 456 uint8_t xl : 1; 457 #endif /* DRV_BYTE_ORDER */ 458 } lis2de12_int1_src_t; 459 460 #define LIS2DE12_INT1_THS 0x32U 461 typedef struct 462 { 463 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 464 uint8_t ths : 7; 465 uint8_t not_used_01 : 1; 466 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 467 uint8_t not_used_01 : 1; 468 uint8_t ths : 7; 469 #endif /* DRV_BYTE_ORDER */ 470 } lis2de12_int1_ths_t; 471 472 #define LIS2DE12_INT1_DURATION 0x33U 473 typedef struct 474 { 475 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 476 uint8_t d : 7; 477 uint8_t not_used_01 : 1; 478 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 479 uint8_t not_used_01 : 1; 480 uint8_t d : 7; 481 #endif /* DRV_BYTE_ORDER */ 482 } lis2de12_int1_duration_t; 483 484 #define LIS2DE12_INT2_CFG 0x34U 485 typedef struct 486 { 487 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 488 uint8_t xlie : 1; 489 uint8_t xhie : 1; 490 uint8_t ylie : 1; 491 uint8_t yhie : 1; 492 uint8_t zlie : 1; 493 uint8_t zhie : 1; 494 uint8_t _6d : 1; 495 uint8_t aoi : 1; 496 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 497 uint8_t aoi : 1; 498 uint8_t _6d : 1; 499 uint8_t zhie : 1; 500 uint8_t zlie : 1; 501 uint8_t yhie : 1; 502 uint8_t ylie : 1; 503 uint8_t xhie : 1; 504 uint8_t xlie : 1; 505 #endif /* DRV_BYTE_ORDER */ 506 } lis2de12_int2_cfg_t; 507 508 #define LIS2DE12_INT2_SRC 0x35U 509 typedef struct 510 { 511 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 512 uint8_t xl : 1; 513 uint8_t xh : 1; 514 uint8_t yl : 1; 515 uint8_t yh : 1; 516 uint8_t zl : 1; 517 uint8_t zh : 1; 518 uint8_t ia : 1; 519 uint8_t not_used_01 : 1; 520 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 521 uint8_t not_used_01 : 1; 522 uint8_t ia : 1; 523 uint8_t zh : 1; 524 uint8_t zl : 1; 525 uint8_t yh : 1; 526 uint8_t yl : 1; 527 uint8_t xh : 1; 528 uint8_t xl : 1; 529 #endif /* DRV_BYTE_ORDER */ 530 } lis2de12_int2_src_t; 531 532 #define LIS2DE12_INT2_THS 0x36U 533 typedef struct 534 { 535 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 536 uint8_t ths : 7; 537 uint8_t not_used_01 : 1; 538 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 539 uint8_t not_used_01 : 1; 540 uint8_t ths : 7; 541 #endif /* DRV_BYTE_ORDER */ 542 } lis2de12_int2_ths_t; 543 544 #define LIS2DE12_INT2_DURATION 0x37U 545 typedef struct 546 { 547 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 548 uint8_t d : 7; 549 uint8_t not_used_01 : 1; 550 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 551 uint8_t not_used_01 : 1; 552 uint8_t d : 7; 553 #endif /* DRV_BYTE_ORDER */ 554 } lis2de12_int2_duration_t; 555 556 #define LIS2DE12_CLICK_CFG 0x38U 557 typedef struct 558 { 559 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 560 uint8_t xs : 1; 561 uint8_t xd : 1; 562 uint8_t ys : 1; 563 uint8_t yd : 1; 564 uint8_t zs : 1; 565 uint8_t zd : 1; 566 uint8_t not_used_01 : 2; 567 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 568 uint8_t not_used_01 : 2; 569 uint8_t zd : 1; 570 uint8_t zs : 1; 571 uint8_t yd : 1; 572 uint8_t ys : 1; 573 uint8_t xd : 1; 574 uint8_t xs : 1; 575 #endif /* DRV_BYTE_ORDER */ 576 } lis2de12_click_cfg_t; 577 578 #define LIS2DE12_CLICK_SRC 0x39U 579 typedef struct 580 { 581 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 582 uint8_t x : 1; 583 uint8_t y : 1; 584 uint8_t z : 1; 585 uint8_t sign : 1; 586 uint8_t sclick : 1; 587 uint8_t dclick : 1; 588 uint8_t ia : 1; 589 uint8_t not_used_01 : 1; 590 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 591 uint8_t not_used_01 : 1; 592 uint8_t ia : 1; 593 uint8_t dclick : 1; 594 uint8_t sclick : 1; 595 uint8_t sign : 1; 596 uint8_t z : 1; 597 uint8_t y : 1; 598 uint8_t x : 1; 599 #endif /* DRV_BYTE_ORDER */ 600 } lis2de12_click_src_t; 601 602 #define LIS2DE12_CLICK_THS 0x3AU 603 typedef struct 604 { 605 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 606 uint8_t ths : 7; 607 uint8_t lir_click : 1; 608 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 609 uint8_t lir_click : 1; 610 uint8_t ths : 7; 611 #endif /* DRV_BYTE_ORDER */ 612 } lis2de12_click_ths_t; 613 614 #define LIS2DE12_TIME_LIMIT 0x3BU 615 typedef struct 616 { 617 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 618 uint8_t tli : 7; 619 uint8_t not_used_01 : 1; 620 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 621 uint8_t not_used_01 : 1; 622 uint8_t tli : 7; 623 #endif /* DRV_BYTE_ORDER */ 624 } lis2de12_time_limit_t; 625 626 #define LIS2DE12_TIME_LATENCY 0x3CU 627 typedef struct 628 { 629 uint8_t tla : 8; 630 } lis2de12_time_latency_t; 631 632 #define LIS2DE12_TIME_WINDOW 0x3DU 633 typedef struct 634 { 635 uint8_t tw : 8; 636 } lis2de12_time_window_t; 637 638 #define LIS2DE12_ACT_THS 0x3EU 639 typedef struct 640 { 641 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 642 uint8_t acth : 7; 643 uint8_t not_used_01 : 1; 644 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 645 uint8_t not_used_01 : 1; 646 uint8_t acth : 7; 647 #endif /* DRV_BYTE_ORDER */ 648 } lis2de12_act_ths_t; 649 650 #define LIS2DE12_ACT_DUR 0x3FU 651 typedef struct 652 { 653 uint8_t actd : 8; 654 } lis2de12_act_dur_t; 655 656 /** 657 * @defgroup LIS2DE12_Register_Union 658 * @brief This union group all the registers having a bit-field 659 * description. 660 * This union is useful but it's not needed by the driver. 661 * 662 * REMOVING this union you are compliant with: 663 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 664 * 665 * @{ 666 * 667 */ 668 typedef union 669 { 670 lis2de12_status_reg_aux_t status_reg_aux; 671 lis2de12_ctrl_reg0_t ctrl_reg0; 672 lis2de12_temp_cfg_reg_t temp_cfg_reg; 673 lis2de12_ctrl_reg1_t ctrl_reg1; 674 lis2de12_ctrl_reg2_t ctrl_reg2; 675 lis2de12_ctrl_reg3_t ctrl_reg3; 676 lis2de12_ctrl_reg4_t ctrl_reg4; 677 lis2de12_ctrl_reg5_t ctrl_reg5; 678 lis2de12_ctrl_reg6_t ctrl_reg6; 679 lis2de12_status_reg_t status_reg; 680 lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg; 681 lis2de12_fifo_src_reg_t fifo_src_reg; 682 lis2de12_int1_cfg_t int1_cfg; 683 lis2de12_int1_src_t int1_src; 684 lis2de12_int1_ths_t int1_ths; 685 lis2de12_int1_duration_t int1_duration; 686 lis2de12_int2_cfg_t int2_cfg; 687 lis2de12_int2_src_t int2_src; 688 lis2de12_int2_ths_t int2_ths; 689 lis2de12_int2_duration_t int2_duration; 690 lis2de12_click_cfg_t click_cfg; 691 lis2de12_click_src_t click_src; 692 lis2de12_click_ths_t click_ths; 693 lis2de12_time_limit_t time_limit; 694 lis2de12_time_latency_t time_latency; 695 lis2de12_time_window_t time_window; 696 lis2de12_act_ths_t act_ths; 697 lis2de12_act_dur_t act_dur; 698 bitwise_t bitwise; 699 uint8_t byte; 700 } lis2de12_reg_t; 701 702 /** 703 * @} 704 * 705 */ 706 707 #ifndef __weak 708 #define __weak __attribute__((weak)) 709 #endif /* __weak */ 710 711 /* 712 * These are the basic platform dependent I/O routines to read 713 * and write device registers connected on a standard bus. 714 * The driver keeps offering a default implementation based on function 715 * pointers to read/write routines for backward compatibility. 716 * The __weak directive allows the final application to overwrite 717 * them with a custom implementation. 718 */ 719 720 int32_t lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 721 uint8_t *data, 722 uint16_t len); 723 int32_t lis2de12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 724 uint8_t *data, 725 uint16_t len); 726 727 float_t lis2de12_from_fs2_to_mg(int16_t lsb); 728 float_t lis2de12_from_fs4_to_mg(int16_t lsb); 729 float_t lis2de12_from_fs8_to_mg(int16_t lsb); 730 float_t lis2de12_from_fs16_to_mg(int16_t lsb); 731 732 float_t lis2de12_from_lsb_to_celsius(int16_t lsb); 733 734 int32_t lis2de12_temp_status_reg_get(stmdev_ctx_t *ctx, 735 uint8_t *buff); 736 int32_t lis2de12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 737 738 int32_t lis2de12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); 739 740 int32_t lis2de12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 741 742 typedef enum 743 { 744 LIS2DE12_TEMP_DISABLE = 0, 745 LIS2DE12_TEMP_ENABLE = 3, 746 } lis2de12_temp_en_t; 747 int32_t lis2de12_temperature_meas_set(stmdev_ctx_t *ctx, 748 lis2de12_temp_en_t val); 749 int32_t lis2de12_temperature_meas_get(stmdev_ctx_t *ctx, 750 lis2de12_temp_en_t *val); 751 752 typedef enum 753 { 754 LIS2DE12_POWER_DOWN = 0x00, 755 LIS2DE12_ODR_1Hz = 0x01, 756 LIS2DE12_ODR_10Hz = 0x02, 757 LIS2DE12_ODR_25Hz = 0x03, 758 LIS2DE12_ODR_50Hz = 0x04, 759 LIS2DE12_ODR_100Hz = 0x05, 760 LIS2DE12_ODR_200Hz = 0x06, 761 LIS2DE12_ODR_400Hz = 0x07, 762 LIS2DE12_ODR_1kHz620_LP = 0x08, 763 LIS2DE12_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, 764 } lis2de12_odr_t; 765 int32_t lis2de12_data_rate_set(stmdev_ctx_t *ctx, lis2de12_odr_t val); 766 int32_t lis2de12_data_rate_get(stmdev_ctx_t *ctx, 767 lis2de12_odr_t *val); 768 769 int32_t lis2de12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, 770 uint8_t val); 771 int32_t lis2de12_high_pass_on_outputs_get(stmdev_ctx_t *ctx, 772 uint8_t *val); 773 774 typedef enum 775 { 776 LIS2DE12_AGGRESSIVE = 0, 777 LIS2DE12_STRONG = 1, 778 LIS2DE12_MEDIUM = 2, 779 LIS2DE12_LIGHT = 3, 780 } lis2de12_hpcf_t; 781 int32_t lis2de12_high_pass_bandwidth_set(stmdev_ctx_t *ctx, 782 lis2de12_hpcf_t val); 783 int32_t lis2de12_high_pass_bandwidth_get(stmdev_ctx_t *ctx, 784 lis2de12_hpcf_t *val); 785 786 typedef enum 787 { 788 LIS2DE12_NORMAL_WITH_RST = 0, 789 LIS2DE12_REFERENCE_MODE = 1, 790 LIS2DE12_NORMAL = 2, 791 LIS2DE12_AUTORST_ON_INT = 3, 792 } lis2de12_hpm_t; 793 int32_t lis2de12_high_pass_mode_set(stmdev_ctx_t *ctx, 794 lis2de12_hpm_t val); 795 int32_t lis2de12_high_pass_mode_get(stmdev_ctx_t *ctx, 796 lis2de12_hpm_t *val); 797 798 typedef enum 799 { 800 LIS2DE12_2g = 0, 801 LIS2DE12_4g = 1, 802 LIS2DE12_8g = 2, 803 LIS2DE12_16g = 3, 804 } lis2de12_fs_t; 805 int32_t lis2de12_full_scale_set(stmdev_ctx_t *ctx, lis2de12_fs_t val); 806 int32_t lis2de12_full_scale_get(stmdev_ctx_t *ctx, 807 lis2de12_fs_t *val); 808 809 int32_t lis2de12_block_data_update_set(stmdev_ctx_t *ctx, 810 uint8_t val); 811 int32_t lis2de12_block_data_update_get(stmdev_ctx_t *ctx, 812 uint8_t *val); 813 814 int32_t lis2de12_filter_reference_set(stmdev_ctx_t *ctx, 815 uint8_t *buff); 816 int32_t lis2de12_filter_reference_get(stmdev_ctx_t *ctx, 817 uint8_t *buff); 818 819 int32_t lis2de12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 820 821 int32_t lis2de12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); 822 823 int32_t lis2de12_acceleration_raw_get(stmdev_ctx_t *ctx, 824 int16_t *val); 825 826 int32_t lis2de12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 827 828 typedef enum 829 { 830 LIS2DE12_ST_DISABLE = 0, 831 LIS2DE12_ST_POSITIVE = 1, 832 LIS2DE12_ST_NEGATIVE = 2, 833 } lis2de12_st_t; 834 int32_t lis2de12_self_test_set(stmdev_ctx_t *ctx, lis2de12_st_t val); 835 int32_t lis2de12_self_test_get(stmdev_ctx_t *ctx, lis2de12_st_t *val); 836 837 int32_t lis2de12_boot_set(stmdev_ctx_t *ctx, uint8_t val); 838 int32_t lis2de12_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 839 840 int32_t lis2de12_status_get(stmdev_ctx_t *ctx, 841 lis2de12_status_reg_t *val); 842 843 int32_t lis2de12_int1_gen_conf_set(stmdev_ctx_t *ctx, 844 lis2de12_int1_cfg_t *val); 845 int32_t lis2de12_int1_gen_conf_get(stmdev_ctx_t *ctx, 846 lis2de12_int1_cfg_t *val); 847 848 int32_t lis2de12_int1_gen_source_get(stmdev_ctx_t *ctx, 849 lis2de12_int1_src_t *val); 850 851 int32_t lis2de12_int1_gen_threshold_set(stmdev_ctx_t *ctx, 852 uint8_t val); 853 int32_t lis2de12_int1_gen_threshold_get(stmdev_ctx_t *ctx, 854 uint8_t *val); 855 856 int32_t lis2de12_int1_gen_duration_set(stmdev_ctx_t *ctx, 857 uint8_t val); 858 int32_t lis2de12_int1_gen_duration_get(stmdev_ctx_t *ctx, 859 uint8_t *val); 860 861 int32_t lis2de12_int2_gen_conf_set(stmdev_ctx_t *ctx, 862 lis2de12_int2_cfg_t *val); 863 int32_t lis2de12_int2_gen_conf_get(stmdev_ctx_t *ctx, 864 lis2de12_int2_cfg_t *val); 865 866 int32_t lis2de12_int2_gen_source_get(stmdev_ctx_t *ctx, 867 lis2de12_int2_src_t *val); 868 869 int32_t lis2de12_int2_gen_threshold_set(stmdev_ctx_t *ctx, 870 uint8_t val); 871 int32_t lis2de12_int2_gen_threshold_get(stmdev_ctx_t *ctx, 872 uint8_t *val); 873 874 int32_t lis2de12_int2_gen_duration_set(stmdev_ctx_t *ctx, 875 uint8_t val); 876 int32_t lis2de12_int2_gen_duration_get(stmdev_ctx_t *ctx, 877 uint8_t *val); 878 879 typedef enum 880 { 881 LIS2DE12_DISC_FROM_INT_GENERATOR = 0, 882 LIS2DE12_ON_INT1_GEN = 1, 883 LIS2DE12_ON_INT2_GEN = 2, 884 LIS2DE12_ON_TAP_GEN = 4, 885 LIS2DE12_ON_INT1_INT2_GEN = 3, 886 LIS2DE12_ON_INT1_TAP_GEN = 5, 887 LIS2DE12_ON_INT2_TAP_GEN = 6, 888 LIS2DE12_ON_INT1_INT2_TAP_GEN = 7, 889 } lis2de12_hp_t; 890 int32_t lis2de12_high_pass_int_conf_set(stmdev_ctx_t *ctx, 891 lis2de12_hp_t val); 892 int32_t lis2de12_high_pass_int_conf_get(stmdev_ctx_t *ctx, 893 lis2de12_hp_t *val); 894 895 int32_t lis2de12_pin_int1_config_set(stmdev_ctx_t *ctx, 896 lis2de12_ctrl_reg3_t *val); 897 int32_t lis2de12_pin_int1_config_get(stmdev_ctx_t *ctx, 898 lis2de12_ctrl_reg3_t *val); 899 900 int32_t lis2de12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, 901 uint8_t val); 902 int32_t lis2de12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, 903 uint8_t *val); 904 905 typedef enum 906 { 907 LIS2DE12_INT2_PULSED = 0, 908 LIS2DE12_INT2_LATCHED = 1, 909 } lis2de12_lir_int2_t; 910 int32_t lis2de12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, 911 lis2de12_lir_int2_t val); 912 int32_t lis2de12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, 913 lis2de12_lir_int2_t *val); 914 915 int32_t lis2de12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, 916 uint8_t val); 917 int32_t lis2de12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, 918 uint8_t *val); 919 920 typedef enum 921 { 922 LIS2DE12_INT1_PULSED = 0, 923 LIS2DE12_INT1_LATCHED = 1, 924 } lis2de12_lir_int1_t; 925 int32_t lis2de12_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, 926 lis2de12_lir_int1_t val); 927 int32_t lis2de12_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, 928 lis2de12_lir_int1_t *val); 929 930 int32_t lis2de12_pin_int2_config_set(stmdev_ctx_t *ctx, 931 lis2de12_ctrl_reg6_t *val); 932 int32_t lis2de12_pin_int2_config_get(stmdev_ctx_t *ctx, 933 lis2de12_ctrl_reg6_t *val); 934 935 int32_t lis2de12_fifo_set(stmdev_ctx_t *ctx, uint8_t val); 936 int32_t lis2de12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); 937 938 int32_t lis2de12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); 939 int32_t lis2de12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); 940 941 typedef enum 942 { 943 LIS2DE12_INT1_GEN = 0, 944 LIS2DE12_INT2_GEN = 1, 945 } lis2de12_tr_t; 946 int32_t lis2de12_fifo_trigger_event_set(stmdev_ctx_t *ctx, 947 lis2de12_tr_t val); 948 int32_t lis2de12_fifo_trigger_event_get(stmdev_ctx_t *ctx, 949 lis2de12_tr_t *val); 950 951 typedef enum 952 { 953 LIS2DE12_BYPASS_MODE = 0, 954 LIS2DE12_FIFO_MODE = 1, 955 LIS2DE12_DYNAMIC_STREAM_MODE = 2, 956 LIS2DE12_STREAM_TO_FIFO_MODE = 3, 957 } lis2de12_fm_t; 958 int32_t lis2de12_fifo_mode_set(stmdev_ctx_t *ctx, lis2de12_fm_t val); 959 int32_t lis2de12_fifo_mode_get(stmdev_ctx_t *ctx, lis2de12_fm_t *val); 960 961 int32_t lis2de12_fifo_status_get(stmdev_ctx_t *ctx, 962 lis2de12_fifo_src_reg_t *val); 963 964 int32_t lis2de12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); 965 966 int32_t lis2de12_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 967 968 int32_t lis2de12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 969 970 int32_t lis2de12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 971 972 int32_t lis2de12_tap_conf_set(stmdev_ctx_t *ctx, 973 lis2de12_click_cfg_t *val); 974 int32_t lis2de12_tap_conf_get(stmdev_ctx_t *ctx, 975 lis2de12_click_cfg_t *val); 976 977 int32_t lis2de12_tap_source_get(stmdev_ctx_t *ctx, 978 lis2de12_click_src_t *val); 979 980 int32_t lis2de12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 981 int32_t lis2de12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 982 983 typedef enum 984 { 985 LIS2DE12_TAP_PULSED = 0, 986 LIS2DE12_TAP_LATCHED = 1, 987 } lis2de12_lir_click_t; 988 int32_t lis2de12_tap_notification_mode_set(stmdev_ctx_t *ctx, 989 lis2de12_lir_click_t val); 990 int32_t lis2de12_tap_notification_mode_get(stmdev_ctx_t *ctx, 991 lis2de12_lir_click_t *val); 992 993 int32_t lis2de12_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val); 994 int32_t lis2de12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 995 996 int32_t lis2de12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val); 997 int32_t lis2de12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 998 999 int32_t lis2de12_double_tap_timeout_set(stmdev_ctx_t *ctx, 1000 uint8_t val); 1001 int32_t lis2de12_double_tap_timeout_get(stmdev_ctx_t *ctx, 1002 uint8_t *val); 1003 1004 int32_t lis2de12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 1005 int32_t lis2de12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 1006 1007 int32_t lis2de12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val); 1008 int32_t lis2de12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); 1009 1010 typedef enum 1011 { 1012 LIS2DE12_PULL_UP_DISCONNECT = 1, 1013 LIS2DE12_PULL_UP_CONNECT = 0, 1014 } lis2de12_sdo_pu_disc_t; 1015 int32_t lis2de12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, 1016 lis2de12_sdo_pu_disc_t val); 1017 int32_t lis2de12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, 1018 lis2de12_sdo_pu_disc_t *val); 1019 1020 typedef enum 1021 { 1022 LIS2DE12_SPI_4_WIRE = 0, 1023 LIS2DE12_SPI_3_WIRE = 1, 1024 } lis2de12_sim_t; 1025 int32_t lis2de12_spi_mode_set(stmdev_ctx_t *ctx, lis2de12_sim_t val); 1026 int32_t lis2de12_spi_mode_get(stmdev_ctx_t *ctx, lis2de12_sim_t *val); 1027 1028 /** 1029 * @} 1030 * 1031 */ 1032 1033 #ifdef __cplusplus 1034 } 1035 #endif 1036 1037 #endif /* LIS2DE12_REGS_H */ 1038 1039 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1040
