1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * @file hw_sgmii_tip.h 7 * @author Microchip-FPGA Embedded Systems Solutions 8 * 9 * 10 * Note 1: This file should not be edited. If you need to modify a parameter 11 * without going through regenerating using the MSS Configurator Libero flow 12 * or editing the associated xml file 13 * the following method is recommended: 14 15 * 1. edit the following file 16 * boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h 17 18 * 2. define the value you want to override there. 19 * (Note: There is a commented example in the platform directory) 20 21 * Note 2: The definition in mss_sw_config.h takes precedence, as 22 * mss_sw_config.h is included prior to the generated header files located in 23 * boards/your_board/fpga_design_config 24 * 25 */ 26 27 #ifndef HW_SGMII_TIP_H_ 28 #define HW_SGMII_TIP_H_ 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined (LIBERO_SETTING_SGMII_MODE) 36 /*SGMII mode control (SEU) */ 37 #define LIBERO_SETTING_SGMII_MODE 0x08C0E6FFUL 38 /* REG_PLL_EN [0:1] RW value= 0x1 */ 39 /* REG_DLL_EN [1:1] RW value= 0x1 */ 40 /* REG_PVT_EN [2:1] RW value= 0x1 */ 41 /* REG_BC_VRGEN_EN [3:1] RW value= 0x1 */ 42 /* REG_TX0_EN [4:1] RW value= 0x1 */ 43 /* REG_RX0_EN [5:1] RW value= 0x1 */ 44 /* REG_TX1_EN [6:1] RW value= 0x1 */ 45 /* REG_RX1_EN [7:1] RW value= 0x1 */ 46 /* REG_DLL_LOCK_FLT [8:2] RW value= 0x2 */ 47 /* REG_DLL_ADJ_CODE [10:4] RW value= 0x9 */ 48 /* REG_CH0_CDR_RESET_B [14:1] RW value= 0x1 */ 49 /* REG_CH1_CDR_RESET_B [15:1] RW value= 0x1 */ 50 /* REG_BC_VRGEN [16:6] RW value= 0x00 */ 51 /* REG_CDR_MOVE_STEP [22:1] RW value= 0x1 */ 52 /* REG_REFCLK_EN_RDIFF [23:1] RW value= 0x1 */ 53 /* REG_BC_VS [24:4] RW value= 0x8 */ 54 /* REG_REFCLK_EN_UDRIVE_P [28:1] RW value= 0x0 */ 55 /* REG_REFCLK_EN_INS_HYST_P [29:1] RW value= 0x0 */ 56 /* REG_REFCLK_EN_UDRIVE_N [30:1] RW value= 0x0 */ 57 /* REG_REFCLK_EN_INS_HYST_N [31:1] RW value= 0x0 */ 58 #endif 59 #if !defined (LIBERO_SETTING_PLL_CNTL) 60 /*PLL control register (SEU) */ 61 #define LIBERO_SETTING_PLL_CNTL 0x80140101UL 62 /* REG_PLL_POSTDIV [0:7] RW value= 0x1 */ 63 /* ARO_PLL0_LOCK [7:1] RO */ 64 /* REG_PLL_RFDIV [8:6] RW value= 0x1 */ 65 /* REG_PLL_REG_RFCLK_SEL [14:1] RW value= 0x0 */ 66 /* REG_PLL_LP_REQUIRES_LOCK [15:1] RW value= 0x0 */ 67 /* REG_PLL_INTIN [16:12] RW value= 0x14 */ 68 /* REG_PLL_BWI [28:2] RW value= 0x0 */ 69 /* REG_PLL_BWP [30:2] RW value= 0x2 */ 70 #endif 71 #if !defined (LIBERO_SETTING_CH0_CNTL) 72 /*Channel0 control register */ 73 #define LIBERO_SETTING_CH0_CNTL 0x37F07770UL 74 /* REG_TX0_WPU_P [0:1] RW value= 0x0 */ 75 /* REG_TX0_WPD_P [1:1] RW value= 0x0 */ 76 /* REG_TX0_SLEW_P [2:2] RW value= 0x0 */ 77 /* REG_TX0_DRV_P [4:4] RW value= 0x7 */ 78 /* REG_TX0_ODT_P [8:4] RW value= 0x7 */ 79 /* REG_TX0_ODT_STATIC_P [12:3] RW value= 0x7 */ 80 /* REG_RX0_TIM_LONG [15:1] RW value= 0x0 */ 81 /* REG_RX0_WPU_P [16:1] RW value= 0x0 */ 82 /* REG_RX0_WPD_P [17:1] RW value= 0x0 */ 83 /* REG_RX0_IBUFMD_P [18:3] RW value= 0x4 */ 84 /* REG_RX0_EYEWIDTH_P [21:3] RW value= 0x7 */ 85 /* REG_RX0_ODT_P [24:4] RW value= 0x7 */ 86 /* REG_RX0_ODT_STATIC_P [28:3] RW value= 0x3 */ 87 /* REG_RX0_EN_FLAG_N [31:1] RW value= 0x0 */ 88 #endif 89 #if !defined (LIBERO_SETTING_CH1_CNTL) 90 /*Channel1 control register */ 91 #define LIBERO_SETTING_CH1_CNTL 0x37F07770UL 92 /* REG_TX1_WPU_P [0:1] RW value= 0x0 */ 93 /* REG_TX1_WPD_P [1:1] RW value= 0x0 */ 94 /* REG_TX1_SLEW_P [2:2] RW value= 0x0 */ 95 /* REG_TX1_DRV_P [4:4] RW value= 0x7 */ 96 /* REG_TX1_ODT_P [8:4] RW value= 0x7 */ 97 /* REG_TX1_ODT_STATIC_P [12:3] RW value= 0x7 */ 98 /* REG_RX1_TIM_LONG [15:1] RW value= 0x0 */ 99 /* REG_RX1_WPU_P [16:1] RW value= 0x0 */ 100 /* REG_RX1_WPD_P [17:1] RW value= 0x0 */ 101 /* REG_RX1_IBUFMD_P [18:3] RW value= 0x4 */ 102 /* REG_RX1_EYEWIDTH_P [21:3] RW value= 0x7 */ 103 /* REG_RX1_ODT_P [24:4] RW value= 0x7 */ 104 /* REG_RX1_ODT_STATIC_P [28:3] RW value= 0x3 */ 105 /* REG_RX1_EN_FLAG_N [31:1] RW value= 0x0 */ 106 #endif 107 #if !defined (LIBERO_SETTING_RECAL_CNTL) 108 /*Recalibration control register */ 109 #define LIBERO_SETTING_RECAL_CNTL 0x000020C8UL 110 /* REG_RECAL_DIFF_RANGE [0:5] RW value= 0x8 */ 111 /* REG_RECAL_START_EN [5:1] RW value= 0x0 */ 112 /* REG_PVT_CALIB_START [6:1] RW value= 0x1 */ 113 /* REG_PVT_CALIB_LOCK [7:1] RW value= 0x1 */ 114 /* REG_RECAL_UPD [8:1] RW value= 0x0 */ 115 /* BC_VRGEN_DIRECTION [9:1] RW value= 0x0 */ 116 /* BC_VRGEN_LOAD [10:1] RW value= 0x0 */ 117 /* BC_VRGEN_MOVE [11:1] RW value= 0x0 */ 118 /* REG_PVT_REG_CALIB_CLKDIV [12:2] RW value= 0x2 */ 119 /* REG_PVT_REG_CALIB_DIFFR_VSEL [14:2] RW value= 0x0 */ 120 /* SRO_DLL_90_CODE [16:7] RO */ 121 /* SRO_DLL_LOCK [23:1] RO */ 122 /* SRO_DLL_ST_CODE [24:7] RO */ 123 /* SRO_RECAL_START [31:1] RO */ 124 #endif 125 #if !defined (LIBERO_SETTING_CLK_CNTL) 126 /*Clock input and routing control registers */ 127 #define LIBERO_SETTING_CLK_CNTL 0xF00050CCUL 128 /* REG_REFCLK_EN_TERM_P [0:2] RW value= 0x0 */ 129 /* REG_REFCLK_EN_RXMODE_P [2:2] RW value= 0x3 */ 130 /* REG_REFCLK_EN_TERM_N [4:2] RW value= 0x0 */ 131 /* REG_REFCLK_EN_RXMODE_N [6:2] RW value= 0x3 */ 132 /* REG_REFCLK_CLKBUF_EN_PULLUP [8:1] RW value= 0x0 */ 133 /* REG_CLKMUX_FCLK_SEL [9:3] RW value= 0x0 */ 134 /* REG_CLKMUX_PLL0_RFCLK0_SEL [12:2] RW value= 0x1 */ 135 /* REG_CLKMUX_PLL0_RFCLK1_SEL [14:2] RW value= 0x1 */ 136 /* REG_CLKMUX_SPARE0 [16:16] RW value= 0xf000 */ 137 #endif 138 #if !defined (LIBERO_SETTING_DYN_CNTL) 139 /*Dynamic control registers */ 140 #define LIBERO_SETTING_DYN_CNTL 0x00000000UL 141 /* REG_PLL_DYNEN [0:1] RW value= 0x0 */ 142 /* REG_DLL_DYNEN [1:1] RW value= 0x0 */ 143 /* REG_PVT_DYNEN [2:1] RW value= 0x0 */ 144 /* REG_BC_DYNEN [3:1] RW value= 0x0 */ 145 /* REG_CLKMUX_DYNEN [4:1] RW value= 0x0 */ 146 /* REG_LANE0_DYNEN [5:1] RW value= 0x0 */ 147 /* REG_LANE1_DYNEN [6:1] RW value= 0x0 */ 148 /* BC_VRGEN_OOR [7:1] RO */ 149 /* REG_PLL_SOFT_RESET_PERIPH [8:1] RW value= 0x0 */ 150 /* REG_DLL_SOFT_RESET_PERIPH [9:1] RW value= 0x0 */ 151 /* REG_PVT_SOFT_RESET_PERIPH [10:1] RW value= 0x0 */ 152 /* REG_BC_SOFT_RESET_PERIPH [11:1] RW value= 0x0 */ 153 /* REG_CLKMUX_SOFT_RESET_PERIPH [12:1] RW value= 0x0 */ 154 /* REG_LANE0_SOFT_RESET_PERIPH [13:1] RW value= 0x0 */ 155 /* REG_LANE1_SOFT_RESET_PERIPH [14:1] RW value= 0x0 */ 156 /* PVT_CALIB_STATUS [15:1] RO */ 157 /* ARO_PLL0_VCO0PH_SEL [16:3] RO */ 158 /* ARO_PLL0_VCO1PH_SEL [19:3] RO */ 159 /* ARO_PLL0_VCO2PH_SEL [22:3] RO */ 160 /* ARO_PLL0_VCO3PH_SEL [25:3] RO */ 161 /* ARO_REF_DIFFR [28:4] RO */ 162 #endif 163 #if !defined (LIBERO_SETTING_PVT_STAT) 164 /*PVT calibrator status registers */ 165 #define LIBERO_SETTING_PVT_STAT 0x00000000UL 166 /* ARO_REF_PCODE [0:6] RO */ 167 /* ARO_IOEN_BNK [6:1] RO */ 168 /* ARO_IOEN_BNK_B [7:1] RO */ 169 /* ARO_REF_NCODE [8:6] RO */ 170 /* ARO_CALIB_STATUS [14:1] RO */ 171 /* ARO_CALIB_STATUS_B [15:1] RO */ 172 /* ARO_PCODE [16:6] RO */ 173 /* ARO_CALIB_INTRPT [22:1] RO */ 174 /* PVT_CALIB_INTRPT [23:1] RO */ 175 /* ARO_NCODE [24:6] RO */ 176 /* PVT_CALIB_LOCK [30:1] RW value= 0x0 */ 177 /* PVT_CALIB_START [31:1] RW value= 0x0 */ 178 #endif 179 #if !defined (LIBERO_SETTING_SPARE_CNTL) 180 /*Spare control register */ 181 #define LIBERO_SETTING_SPARE_CNTL 0xFF000000UL 182 /* REG_SPARE [0:32] RW value= 0xFF000000 */ 183 #endif 184 #if !defined (LIBERO_SETTING_SPARE_STAT) 185 /*Spare status register */ 186 #define LIBERO_SETTING_SPARE_STAT 0x00000000UL 187 /* SRO_SPARE [0:32] RO */ 188 #endif 189 190 #ifdef __cplusplus 191 } 192 #endif 193 194 195 #endif /* #ifdef HW_SGMII_TIP_H_ */ 196 197