1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * @file hw_ddr_io_bank.h 7 * @author Microchip-FPGA Embedded Systems Solutions 8 * 9 * 10 * Note 1: This file should not be edited. If you need to modify a parameter 11 * without going through regenerating using the MSS Configurator Libero flow 12 * or editing the associated xml file 13 * the following method is recommended: 14 15 * 1. edit the following file 16 * boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h 17 18 * 2. define the value you want to override there. 19 * (Note: There is a commented example in the platform directory) 20 21 * Note 2: The definition in mss_sw_config.h takes precedence, as 22 * mss_sw_config.h is included prior to the generated header files located in 23 * boards/your_board/fpga_design_config 24 * 25 */ 26 27 #ifndef HW_DDR_IO_BANK_H_ 28 #define HW_DDR_IO_BANK_H_ 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined (LIBERO_SETTING_DPC_BITS) 36 /*DPC Bits Register */ 37 #define LIBERO_SETTING_DPC_BITS 0x0004C422UL 38 /* DPC_VS [0:4] RW value= 0x2 */ 39 /* DPC_VRGEN_H [4:6] RW value= 0x2 */ 40 /* DPC_VRGEN_EN_H [10:1] RW value= 0x1 */ 41 /* DPC_MOVE_EN_H [11:1] RW value= 0x0 */ 42 /* DPC_VRGEN_V [12:6] RW value= 0xC */ 43 /* DPC_VRGEN_EN_V [18:1] RW value= 0x1 */ 44 /* DPC_MOVE_EN_V [19:1] RW value= 0x0 */ 45 /* RESERVE01 [20:12] RSVD */ 46 #endif 47 #if !defined (LIBERO_SETTING_RPC_ODT_DQ) 48 /*Need to be set by software in all modes but OFF mode. Decoding options should 49 follow ODT_STR table, depends on drive STR setting */ 50 #define LIBERO_SETTING_RPC_ODT_DQ 0x00000006UL 51 /* RPC_ODT_DQ [0:32] RW value= 0x6 */ 52 #endif 53 #if !defined (LIBERO_SETTING_RPC_ODT_DQS) 54 /*Need to be set by software in all modes but OFF mode. Decoding options should 55 follow ODT_STR table, depends on drive STR setting */ 56 #define LIBERO_SETTING_RPC_ODT_DQS 0x00000006UL 57 /* RPC_ODT_DQS [0:32] RW value= 0x6 */ 58 #endif 59 #if !defined (LIBERO_SETTING_RPC_ODT_ADDCMD) 60 /*Need to be set by software in all modes but OFF mode. Decoding options should 61 follow ODT_STR table, depends on drive STR setting */ 62 #define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000002UL 63 /* RPC_ODT_ADDCMD [0:32] RW value= 0x2 */ 64 #endif 65 #if !defined (LIBERO_SETTING_RPC_ODT_CLK) 66 /*Need to be set by software in all modes but OFF mode. Decoding options should 67 follow ODT_STR table, depends on drive STR setting */ 68 #define LIBERO_SETTING_RPC_ODT_CLK 0x00000002UL 69 /* RPC_ODT_CLK [0:32] RW value= 0x2 */ 70 #endif 71 #if !defined (LIBERO_SETTING_RPC_ODT_STATIC_DQ) 72 /*0x2000 73A8 (rpc10_ODT) */ 73 #define LIBERO_SETTING_RPC_ODT_STATIC_DQ 0x00000005UL 74 /* RPC_ODT_STATIC_DQ [0:32] RW value= 0x5 */ 75 #endif 76 #if !defined (LIBERO_SETTING_RPC_ODT_STATIC_DQS) 77 /*0x2000 73AC (rpc11_ODT) */ 78 #define LIBERO_SETTING_RPC_ODT_STATIC_DQS 0x00000005UL 79 /* RPC_ODT_STATIC_DQS [0:32] RW value= 0x5 */ 80 #endif 81 #if !defined (LIBERO_SETTING_RPC_ODT_STATIC_ADDCMD) 82 /*0x2000 739C (rpc7_ODT) */ 83 #define LIBERO_SETTING_RPC_ODT_STATIC_ADDCMD 0x00000007UL 84 /* RPC_ODT_STATIC_ADDCMD [0:32] RW value= 0x7 */ 85 #endif 86 #if !defined (LIBERO_SETTING_RPC_ODT_STATIC_CLKP) 87 /*0x2000 73A4 (rpc9_ODT) */ 88 #define LIBERO_SETTING_RPC_ODT_STATIC_CLKP 0x00000007UL 89 /* RPC_ODT_STATIC_CLKP [0:32] RW value= 0x7 */ 90 #endif 91 #if !defined (LIBERO_SETTING_RPC_ODT_STATIC_CLKN) 92 /*0x2000 73A0 (rpc8_ODT) */ 93 #define LIBERO_SETTING_RPC_ODT_STATIC_CLKN 0x00000007UL 94 /* RPC_ODT_STATIC_CLKN [0:32] RW value= 0x7 */ 95 #endif 96 #if !defined (LIBERO_SETTING_RPC_IBUFMD_ADDCMD) 97 /*0x2000 757C (rpc95) */ 98 #define LIBERO_SETTING_RPC_IBUFMD_ADDCMD 0x00000003UL 99 /* RPC_IBUFMD_ADDCMD [0:32] RW value= 0x3 */ 100 #endif 101 #if !defined (LIBERO_SETTING_RPC_IBUFMD_CLK) 102 /*0x2000 7580 (rpc96) */ 103 #define LIBERO_SETTING_RPC_IBUFMD_CLK 0x00000004UL 104 /* RPC_IBUFMD_CLK [0:32] RW value= 0x4 */ 105 #endif 106 #if !defined (LIBERO_SETTING_RPC_IBUFMD_DQ) 107 /*0x2000 7584 (rpc97) */ 108 #define LIBERO_SETTING_RPC_IBUFMD_DQ 0x00000003UL 109 /* RPC_IBUFMD_DQ [0:32] RW value= 0x3 */ 110 #endif 111 #if !defined (LIBERO_SETTING_RPC_IBUFMD_DQS) 112 /*0x2000 7588 (rpc98) */ 113 #define LIBERO_SETTING_RPC_IBUFMD_DQS 0x00000004UL 114 /* RPC_IBUFMD_DQS [0:32] RW value= 0x4 */ 115 #endif 116 #if !defined (LIBERO_SETTING_RPC_SPARE0_DQ) 117 /*bits 15:14 connect to pc_ibufmx DQ/DQS/DM bits 13:12 connect to pc_ibufmx 118 CA/CK Check at ioa pc bit */ 119 #define LIBERO_SETTING_RPC_SPARE0_DQ 0x00008000UL 120 /* RPC_SPARE0_DQ [0:32] RW value= 0x8000 */ 121 #endif 122 #if !defined (LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9) 123 /*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding 124 to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ 125 #define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000F00UL 126 /* MSS_DDR_CK0 [0:1] RW value= 0x0 */ 127 /* MSS_DDR_CK_N0 [1:1] RW value= 0x0 */ 128 /* MSS_DDR_A0 [2:1] RW value= 0x0 */ 129 /* MSS_DDR_A1 [3:1] RW value= 0x0 */ 130 /* MSS_DDR_A2 [4:1] RW value= 0x0 */ 131 /* MSS_DDR_A3 [5:1] RW value= 0x0 */ 132 /* MSS_DDR_A4 [6:1] RW value= 0x0 */ 133 /* MSS_DDR_A5 [7:1] RW value= 0x0 */ 134 /* MSS_DDR_A6 [8:1] RW value= 0x1 */ 135 /* MSS_DDR_A7 [9:1] RW value= 0x1 */ 136 /* MSS_DDR_A8 [10:1] RW value= 0x1 */ 137 /* MSS_DDR_A9 [11:1] RW value= 0x1 */ 138 #endif 139 #if !defined (LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10) 140 /*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding 141 to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ 142 #define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000FFFUL 143 /* MSS_DDR_CK1 [0:1] RW value= 0x1 */ 144 /* MSS_DDR_CK_N1 [1:1] RW value= 0x1 */ 145 /* MSS_DDR_A10 [2:1] RW value= 0x1 */ 146 /* MSS_DDR_A11 [3:1] RW value= 0x1 */ 147 /* MSS_DDR_A12 [4:1] RW value= 0x1 */ 148 /* MSS_DDR_A13 [5:1] RW value= 0x1 */ 149 /* MSS_DDR_A14 [6:1] RW value= 0x1 */ 150 /* MSS_DDR_A15 [7:1] RW value= 0x1 */ 151 /* MSS_DDR_A16 [8:1] RW value= 0x1 */ 152 /* MSS_DDR3_WE_N [9:1] RW value= 0x1 */ 153 /* MSS_DDR_BA0 [10:1] RW value= 0x1 */ 154 /* MSS_DDR_BA1 [11:1] RW value= 0x1 */ 155 #endif 156 #if !defined (LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11) 157 /*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding 158 to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ 159 #define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000FE6UL 160 /* MSS_DDR_RAM_RST_N [0:1] RW value= 0x0 */ 161 /* MSS_DDR_BG0 [1:1] RW value= 0x1 */ 162 /* MSS_DDR_BG1 [2:1] RW value= 0x1 */ 163 /* MSS_DDR_CS0 [3:1] RW value= 0x0 */ 164 /* MSS_DDR_CKE0 [4:1] RW value= 0x0 */ 165 /* MSS_DDR_ODT0 [5:1] RW value= 0x1 */ 166 /* MSS_DDR_CS1 [6:1] RW value= 0x1 */ 167 /* MSS_DDR_CKE1 [7:1] RW value= 0x1 */ 168 /* MSS_DDR_ODT1 [8:1] RW value= 0x1 */ 169 /* MSS_DDR_ACT_N [9:1] RW value= 0x1 */ 170 /* MSS_DDR_PARITY [10:1] RW value= 0x1 */ 171 /* MSS_DDR_ALERT_N [11:1] RW value= 0x1 */ 172 #endif 173 #if !defined (LIBERO_SETTING_RPC_EN_DATA0_OVRT12) 174 /*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding 175 to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ 176 #define LIBERO_SETTING_RPC_EN_DATA0_OVRT12 0x00000000UL 177 /* MSS_DDR_DQ0 [0:1] RW value= 0x0 */ 178 /* MSS_DDR_DQ1 [1:1] RW value= 0x0 */ 179 /* MSS_DDR_DQ2 [2:1] RW value= 0x0 */ 180 /* MSS_DDR_DQ3 [3:1] RW value= 0x0 */ 181 /* MSS_DDR_DQS_P0 [4:1] RW value= 0x0 */ 182 /* MSS_DDR_DQS_N0 [5:1] RW value= 0x0 */ 183 /* MSS_DDR_DQ4 [6:1] RW value= 0x0 */ 184 /* MSS_DDR_DQ5 [7:1] RW value= 0x0 */ 185 /* MSS_DDR_DQ6 [8:1] RW value= 0x0 */ 186 /* MSS_DDR_DQ7 [9:1] RW value= 0x0 */ 187 /* MSS_DDR_DM0 [10:1] RW value= 0x0 */ 188 #endif 189 #if !defined (LIBERO_SETTING_RPC_EN_DATA1_OVRT13) 190 /*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding 191 to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ 192 #define LIBERO_SETTING_RPC_EN_DATA1_OVRT13 0x00000000UL 193 /* MSS_DDR_DQ8 [0:1] RW value= 0x0 */ 194 /* MSS_DDR_DQ9 [1:1] RW value= 0x0 */ 195 /* MSS_DDR_DQ10 [2:1] RW value= 0x0 */ 196 /* MSS_DDR_DQ11 [3:1] RW value= 0x0 */ 197 /* MSS_DDR_DQS_P1 [4:1] RW value= 0x0 */ 198 /* MSS_DDR_DQS_N1 [5:1] RW value= 0x0 */ 199 /* MSS_DDR_DQ12 [6:1] RW value= 0x0 */ 200 /* MSS_DDR_DQ13 [7:1] RW value= 0x0 */ 201 /* MSS_DDR_DQ14 [8:1] RW value= 0x0 */ 202 /* MSS_DDR_DQ15 [9:1] RW value= 0x0 */ 203 /* MSS_DDR_DM1 [10:1] RW value= 0x0 */ 204 #endif 205 #if !defined (LIBERO_SETTING_RPC_EN_DATA2_OVRT14) 206 /*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding 207 to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ 208 #define LIBERO_SETTING_RPC_EN_DATA2_OVRT14 0x00000000UL 209 /* MSS_DDR_DQ16 [0:1] RW value= 0x0 */ 210 /* MSS_DDR_DQ17 [1:1] RW value= 0x0 */ 211 /* MSS_DDR_DQ18 [2:1] RW value= 0x0 */ 212 /* MSS_DDR_DQ19 [3:1] RW value= 0x0 */ 213 /* MSS_DDR_DQS_P2 [4:1] RW value= 0x0 */ 214 /* MSS_DDR_DQS_N2 [5:1] RW value= 0x0 */ 215 /* MSS_DDR_DQ20 [6:1] RW value= 0x0 */ 216 /* MSS_DDR_DQ21 [7:1] RW value= 0x0 */ 217 /* MSS_DDR_DQ22 [8:1] RW value= 0x0 */ 218 /* MSS_DDR_DQ23 [9:1] RW value= 0x0 */ 219 /* MSS_DDR_DM2 [10:1] RW value= 0x0 */ 220 #endif 221 #if !defined (LIBERO_SETTING_RPC_EN_DATA3_OVRT15) 222 /*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding 223 to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ 224 #define LIBERO_SETTING_RPC_EN_DATA3_OVRT15 0x00000000UL 225 /* MSS_DDR_DQ24 [0:1] RW value= 0x0 */ 226 /* MSS_DDR_DQ25 [1:1] RW value= 0x0 */ 227 /* MSS_DDR_DQ26 [2:1] RW value= 0x0 */ 228 /* MSS_DDR_DQ27 [3:1] RW value= 0x0 */ 229 /* MSS_DDR_DQS_P3 [4:1] RW value= 0x0 */ 230 /* MSS_DDR_DQS_N3 [5:1] RW value= 0x0 */ 231 /* MSS_DDR_DQ28 [6:1] RW value= 0x0 */ 232 /* MSS_DDR_DQ29 [7:1] RW value= 0x0 */ 233 /* MSS_DDR_DQ30 [8:1] RW value= 0x0 */ 234 /* MSS_DDR_DQ31 [9:1] RW value= 0x0 */ 235 /* MSS_DDR_DM3 [10:1] RW value= 0x0 */ 236 #endif 237 #if !defined (LIBERO_SETTING_RPC_EN_ECC_OVRT16) 238 /*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding 239 to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ 240 #define LIBERO_SETTING_RPC_EN_ECC_OVRT16 0x0000007FUL 241 /* MSS_DDR_DQ32 [0:1] RW value= 0x1 */ 242 /* MSS_DDR_DQ33 [1:1] RW value= 0x1 */ 243 /* MSS_DDR_DQ34 [2:1] RW value= 0x1 */ 244 /* MSS_DDR_DQ35 [3:1] RW value= 0x1 */ 245 /* MSS_DDR_DQS_P4 [4:1] RW value= 0x1 */ 246 /* MSS_DDR_DQS_N4 [5:1] RW value= 0x1 */ 247 /* MSS_DDR_DM4 [6:1] RW value= 0x1 */ 248 #endif 249 #if !defined (LIBERO_SETTING_RPC235_WPD_ADD_CMD0) 250 /*Sets pull-downs when override enabled. Each bit corresponding to an IO in 251 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 252 #define LIBERO_SETTING_RPC235_WPD_ADD_CMD0 0x00000000UL 253 /* MSS_DDR_CK0 [0:1] RW value= 0x0 */ 254 /* MSS_DDR_CK_N0 [1:1] RW value= 0x0 */ 255 /* MSS_DDR_A0 [2:1] RW value= 0x0 */ 256 /* MSS_DDR_A1 [3:1] RW value= 0x0 */ 257 /* MSS_DDR_A2 [4:1] RW value= 0x0 */ 258 /* MSS_DDR_A3 [5:1] RW value= 0x0 */ 259 /* MSS_DDR_A4 [6:1] RW value= 0x0 */ 260 /* MSS_DDR_A5 [7:1] RW value= 0x0 */ 261 /* MSS_DDR_A6 [8:1] RW value= 0x0 */ 262 /* MSS_DDR_A7 [9:1] RW value= 0x0 */ 263 /* MSS_DDR_A8 [10:1] RW value= 0x0 */ 264 /* MSS_DDR_A9 [11:1] RW value= 0x0 */ 265 #endif 266 #if !defined (LIBERO_SETTING_RPC236_WPD_ADD_CMD1) 267 /*Sets pull-downs when override enabled. Each bit corresponding to an IO in 268 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 269 #define LIBERO_SETTING_RPC236_WPD_ADD_CMD1 0x00000000UL 270 /* MSS_DDR_CK1 [0:1] RW value= 0x0 */ 271 /* MSS_DDR_CK_N1 [1:1] RW value= 0x0 */ 272 /* MSS_DDR_A10 [2:1] RW value= 0x0 */ 273 /* MSS_DDR_A11 [3:1] RW value= 0x0 */ 274 /* MSS_DDR_A12 [4:1] RW value= 0x0 */ 275 /* MSS_DDR_A13 [5:1] RW value= 0x0 */ 276 /* MSS_DDR_A14 [6:1] RW value= 0x0 */ 277 /* MSS_DDR_A15 [7:1] RW value= 0x0 */ 278 /* MSS_DDR_A16 [8:1] RW value= 0x0 */ 279 /* MSS_DDR3_WE_N [9:1] RW value= 0x0 */ 280 /* MSS_DDR_BA0 [10:1] RW value= 0x0 */ 281 /* MSS_DDR_BA1 [11:1] RW value= 0x0 */ 282 #endif 283 #if !defined (LIBERO_SETTING_RPC237_WPD_ADD_CMD2) 284 /*Sets pull-downs when override enabled. Each bit corresponding to an IO in 285 corresponding IOG lane, starting from p_pair0 to n_pair5. Note: For LPDDR4 need 286 to over-ride MSS_DDR_ODT0 and MSS_DDR_ODT1 and eanble PU i.e. (set OVR_EN ==1 , 287 wpu == 0 , wpd == 1 ) */ 288 #define LIBERO_SETTING_RPC237_WPD_ADD_CMD2 0x00000120UL 289 /* MSS_DDR_RAM_RST_N [0:1] RW value= 0x0 */ 290 /* MSS_DDR_BG0 [1:1] RW value= 0x0 */ 291 /* MSS_DDR_BG1 [2:1] RW value= 0x0 */ 292 /* MSS_DDR_CS0 [3:1] RW value= 0x0 */ 293 /* MSS_DDR_CKE0 [4:1] RW value= 0x0 */ 294 /* MSS_DDR_ODT0 [5:1] RW value= 0x1 */ 295 /* MSS_DDR_CS1 [6:1] RW value= 0x0 */ 296 /* MSS_DDR_CKE1 [7:1] RW value= 0x0 */ 297 /* MSS_DDR_ODT1 [8:1] RW value= 0x1 */ 298 /* MSS_DDR_ACT_N [9:1] RW value= 0x0 */ 299 /* MSS_DDR_PARITY [10:1] RW value= 0x0 */ 300 /* MSS_DDR_ALERT_N [11:1] RW value= 0x0 */ 301 #endif 302 #if !defined (LIBERO_SETTING_RPC238_WPD_DATA0) 303 /*Sets pull-downs when override enabled. Each bit corresponding to an IO in 304 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 305 #define LIBERO_SETTING_RPC238_WPD_DATA0 0x00000000UL 306 /* MSS_DDR_DQ0 [0:1] RW value= 0x0 */ 307 /* MSS_DDR_DQ1 [1:1] RW value= 0x0 */ 308 /* MSS_DDR_DQ2 [2:1] RW value= 0x0 */ 309 /* MSS_DDR_DQ3 [3:1] RW value= 0x0 */ 310 /* MSS_DDR_DQS_P0 [4:1] RW value= 0x0 */ 311 /* MSS_DDR_DQS_N0 [5:1] RW value= 0x0 */ 312 /* MSS_DDR_DQ4 [6:1] RW value= 0x0 */ 313 /* MSS_DDR_DQ5 [7:1] RW value= 0x0 */ 314 /* MSS_DDR_DQ6 [8:1] RW value= 0x0 */ 315 /* MSS_DDR_DQ7 [9:1] RW value= 0x0 */ 316 /* MSS_DDR_DM0 [10:1] RW value= 0x0 */ 317 #endif 318 #if !defined (LIBERO_SETTING_RPC239_WPD_DATA1) 319 /*Sets pull-downs when override enabled. Each bit corresponding to an IO in 320 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 321 #define LIBERO_SETTING_RPC239_WPD_DATA1 0x00000000UL 322 /* MSS_DDR_DQ8 [0:1] RW value= 0x0 */ 323 /* MSS_DDR_DQ9 [1:1] RW value= 0x0 */ 324 /* MSS_DDR_DQ10 [2:1] RW value= 0x0 */ 325 /* MSS_DDR_DQ11 [3:1] RW value= 0x0 */ 326 /* MSS_DDR_DQS_P1 [4:1] RW value= 0x0 */ 327 /* MSS_DDR_DQS_N1 [5:1] RW value= 0x0 */ 328 /* MSS_DDR_DQ12 [6:1] RW value= 0x0 */ 329 /* MSS_DDR_DQ13 [7:1] RW value= 0x0 */ 330 /* MSS_DDR_DQ14 [8:1] RW value= 0x0 */ 331 /* MSS_DDR_DQ15 [9:1] RW value= 0x0 */ 332 /* MSS_DDR_DM1 [10:1] RW value= 0x0 */ 333 #endif 334 #if !defined (LIBERO_SETTING_RPC240_WPD_DATA2) 335 /*Sets pull-downs when override enabled. Each bit corresponding to an IO in 336 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 337 #define LIBERO_SETTING_RPC240_WPD_DATA2 0x00000000UL 338 /* MSS_DDR_DQ16 [0:1] RW value= 0x0 */ 339 /* MSS_DDR_DQ17 [1:1] RW value= 0x0 */ 340 /* MSS_DDR_DQ18 [2:1] RW value= 0x0 */ 341 /* MSS_DDR_DQ19 [3:1] RW value= 0x0 */ 342 /* MSS_DDR_DQS_P2 [4:1] RW value= 0x0 */ 343 /* MSS_DDR_DQS_N2 [5:1] RW value= 0x0 */ 344 /* MSS_DDR_DQ20 [6:1] RW value= 0x0 */ 345 /* MSS_DDR_DQ21 [7:1] RW value= 0x0 */ 346 /* MSS_DDR_DQ22 [8:1] RW value= 0x0 */ 347 /* MSS_DDR_DQ23 [9:1] RW value= 0x0 */ 348 /* MSS_DDR_DM2 [10:1] RW value= 0x0 */ 349 #endif 350 #if !defined (LIBERO_SETTING_RPC241_WPD_DATA3) 351 /*Sets pull-downs when override enabled. Each bit corresponding to an IO in 352 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 353 #define LIBERO_SETTING_RPC241_WPD_DATA3 0x00000000UL 354 /* MSS_DDR_DQ24 [0:1] RW value= 0x0 */ 355 /* MSS_DDR_DQ25 [1:1] RW value= 0x0 */ 356 /* MSS_DDR_DQ26 [2:1] RW value= 0x0 */ 357 /* MSS_DDR_DQ27 [3:1] RW value= 0x0 */ 358 /* MSS_DDR_DQS_P3 [4:1] RW value= 0x0 */ 359 /* MSS_DDR_DQS_N3 [5:1] RW value= 0x0 */ 360 /* MSS_DDR_DQ28 [6:1] RW value= 0x0 */ 361 /* MSS_DDR_DQ29 [7:1] RW value= 0x0 */ 362 /* MSS_DDR_DQ30 [8:1] RW value= 0x0 */ 363 /* MSS_DDR_DQ31 [9:1] RW value= 0x0 */ 364 /* MSS_DDR_DM3 [10:1] RW value= 0x0 */ 365 #endif 366 #if !defined (LIBERO_SETTING_RPC242_WPD_ECC) 367 /*Sets pull-downs when override enabled. Each bit corresponding to an IO in 368 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 369 #define LIBERO_SETTING_RPC242_WPD_ECC 0x00000000UL 370 /* MSS_DDR_DQ32 [0:1] RW value= 0x0 */ 371 /* MSS_DDR_DQ33 [1:1] RW value= 0x0 */ 372 /* MSS_DDR_DQ34 [2:1] RW value= 0x0 */ 373 /* MSS_DDR_DQ35 [3:1] RW value= 0x0 */ 374 /* MSS_DDR_DQS_P4 [4:1] RW value= 0x0 */ 375 /* MSS_DDR_DQS_N4 [5:1] RW value= 0x0 */ 376 /* MSS_DDR_DM4 [6:1] RW value= 0x0 */ 377 #endif 378 #if !defined (LIBERO_SETTING_RPC243_WPU_ADD_CMD0) 379 /*Sets pull-ups when override enabled. Each bit corresponding to an IO in 380 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 381 #define LIBERO_SETTING_RPC243_WPU_ADD_CMD0 0x00000FFFUL 382 /* MSS_DDR_CK0 [0:1] RW value= 0x1 */ 383 /* MSS_DDR_CK_N0 [1:1] RW value= 0x1 */ 384 /* MSS_DDR_A0 [2:1] RW value= 0x1 */ 385 /* MSS_DDR_A1 [3:1] RW value= 0x1 */ 386 /* MSS_DDR_A2 [4:1] RW value= 0x1 */ 387 /* MSS_DDR_A3 [5:1] RW value= 0x1 */ 388 /* MSS_DDR_A4 [6:1] RW value= 0x1 */ 389 /* MSS_DDR_A5 [7:1] RW value= 0x1 */ 390 /* MSS_DDR_A6 [8:1] RW value= 0x1 */ 391 /* MSS_DDR_A7 [9:1] RW value= 0x1 */ 392 /* MSS_DDR_A8 [10:1] RW value= 0x1 */ 393 /* MSS_DDR_A9 [11:1] RW value= 0x1 */ 394 #endif 395 #if !defined (LIBERO_SETTING_RPC244_WPU_ADD_CMD1) 396 /*Sets pull-ups when override enabled. Each bit corresponding to an IO in 397 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 398 #define LIBERO_SETTING_RPC244_WPU_ADD_CMD1 0x00000FFFUL 399 /* MSS_DDR_CK1 [0:1] RW value= 0x1 */ 400 /* MSS_DDR_CK_N1 [1:1] RW value= 0x1 */ 401 /* MSS_DDR_A10 [2:1] RW value= 0x1 */ 402 /* MSS_DDR_A11 [3:1] RW value= 0x1 */ 403 /* MSS_DDR_A12 [4:1] RW value= 0x1 */ 404 /* MSS_DDR_A13 [5:1] RW value= 0x1 */ 405 /* MSS_DDR_A14 [6:1] RW value= 0x1 */ 406 /* MSS_DDR_A15 [7:1] RW value= 0x1 */ 407 /* MSS_DDR_A16 [8:1] RW value= 0x1 */ 408 /* MSS_DDR3_WE_N [9:1] RW value= 0x1 */ 409 /* MSS_DDR_BA0 [10:1] RW value= 0x1 */ 410 /* MSS_DDR_BA1 [11:1] RW value= 0x1 */ 411 #endif 412 #if !defined (LIBERO_SETTING_RPC245_WPU_ADD_CMD2) 413 /*Sets pull-ups when override enabled. Each bit corresponding to an IO in 414 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 415 #define LIBERO_SETTING_RPC245_WPU_ADD_CMD2 0x00000EDFUL 416 /* MSS_DDR_RAM_RST_N [0:1] RW value= 0x1 */ 417 /* MSS_DDR_BG0 [1:1] RW value= 0x1 */ 418 /* MSS_DDR_BG1 [2:1] RW value= 0x1 */ 419 /* MSS_DDR_CS0 [3:1] RW value= 0x1 */ 420 /* MSS_DDR_CKE0 [4:1] RW value= 0x1 */ 421 /* MSS_DDR_ODT0 [5:1] RW value= 0x0 */ 422 /* MSS_DDR_CS1 [6:1] RW value= 0x1 */ 423 /* MSS_DDR_CKE1 [7:1] RW value= 0x1 */ 424 /* MSS_DDR_ODT1 [8:1] RW value= 0x0 */ 425 /* MSS_DDR_ACT_N [9:1] RW value= 0x1 */ 426 /* MSS_DDR_PARITY [10:1] RW value= 0x1 */ 427 /* MSS_DDR_ALERT_N [11:1] RW value= 0x1 */ 428 #endif 429 #if !defined (LIBERO_SETTING_RPC246_WPU_DATA0) 430 /*Sets pull-ups when override enabled. Each bit corresponding to an IO in 431 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 432 #define LIBERO_SETTING_RPC246_WPU_DATA0 0x000007FFUL 433 /* MSS_DDR_DQ0 [0:1] RW value= 0x1 */ 434 /* MSS_DDR_DQ1 [1:1] RW value= 0x1 */ 435 /* MSS_DDR_DQ2 [2:1] RW value= 0x1 */ 436 /* MSS_DDR_DQ3 [3:1] RW value= 0x1 */ 437 /* MSS_DDR_DQS_P0 [4:1] RW value= 0x1 */ 438 /* MSS_DDR_DQS_N0 [5:1] RW value= 0x1 */ 439 /* MSS_DDR_DQ4 [6:1] RW value= 0x1 */ 440 /* MSS_DDR_DQ5 [7:1] RW value= 0x1 */ 441 /* MSS_DDR_DQ6 [8:1] RW value= 0x1 */ 442 /* MSS_DDR_DQ7 [9:1] RW value= 0x1 */ 443 /* MSS_DDR_DM0 [10:1] RW value= 0x1 */ 444 #endif 445 #if !defined (LIBERO_SETTING_RPC247_WPU_DATA1) 446 /*Sets pull-ups when override enabled. Each bit corresponding to an IO in 447 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 448 #define LIBERO_SETTING_RPC247_WPU_DATA1 0x000007FFUL 449 /* MSS_DDR_DQ8 [0:1] RW value= 0x1 */ 450 /* MSS_DDR_DQ9 [1:1] RW value= 0x1 */ 451 /* MSS_DDR_DQ10 [2:1] RW value= 0x1 */ 452 /* MSS_DDR_DQ11 [3:1] RW value= 0x1 */ 453 /* MSS_DDR_DQS_P1 [4:1] RW value= 0x1 */ 454 /* MSS_DDR_DQS_N1 [5:1] RW value= 0x1 */ 455 /* MSS_DDR_DQ12 [6:1] RW value= 0x1 */ 456 /* MSS_DDR_DQ13 [7:1] RW value= 0x1 */ 457 /* MSS_DDR_DQ14 [8:1] RW value= 0x1 */ 458 /* MSS_DDR_DQ15 [9:1] RW value= 0x1 */ 459 /* MSS_DDR_DM1 [10:1] RW value= 0x1 */ 460 #endif 461 #if !defined (LIBERO_SETTING_RPC248_WPU_DATA2) 462 /*Sets pull-ups when override enabled. Each bit corresponding to an IO in 463 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 464 #define LIBERO_SETTING_RPC248_WPU_DATA2 0x000007FFUL 465 /* MSS_DDR_DQ16 [0:1] RW value= 0x1 */ 466 /* MSS_DDR_DQ17 [1:1] RW value= 0x1 */ 467 /* MSS_DDR_DQ18 [2:1] RW value= 0x1 */ 468 /* MSS_DDR_DQ19 [3:1] RW value= 0x1 */ 469 /* MSS_DDR_DQS_P2 [4:1] RW value= 0x1 */ 470 /* MSS_DDR_DQS_N2 [5:1] RW value= 0x1 */ 471 /* MSS_DDR_DQ20 [6:1] RW value= 0x1 */ 472 /* MSS_DDR_DQ21 [7:1] RW value= 0x1 */ 473 /* MSS_DDR_DQ22 [8:1] RW value= 0x1 */ 474 /* MSS_DDR_DQ23 [9:1] RW value= 0x1 */ 475 /* MSS_DDR_DM2 [10:1] RW value= 0x1 */ 476 #endif 477 #if !defined (LIBERO_SETTING_RPC249_WPU_DATA3) 478 /*Sets pull-ups when override enabled. Each bit corresponding to an IO in 479 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 480 #define LIBERO_SETTING_RPC249_WPU_DATA3 0x000007FFUL 481 /* MSS_DDR_DQ24 [0:1] RW value= 0x1 */ 482 /* MSS_DDR_DQ25 [1:1] RW value= 0x1 */ 483 /* MSS_DDR_DQ26 [2:1] RW value= 0x1 */ 484 /* MSS_DDR_DQ27 [3:1] RW value= 0x1 */ 485 /* MSS_DDR_DQS_P3 [4:1] RW value= 0x1 */ 486 /* MSS_DDR_DQS_N3 [5:1] RW value= 0x1 */ 487 /* MSS_DDR_DQ28 [6:1] RW value= 0x1 */ 488 /* MSS_DDR_DQ29 [7:1] RW value= 0x1 */ 489 /* MSS_DDR_DQ30 [8:1] RW value= 0x1 */ 490 /* MSS_DDR_DQ31 [9:1] RW value= 0x1 */ 491 /* MSS_DDR_DM3 [10:1] RW value= 0x1 */ 492 #endif 493 #if !defined (LIBERO_SETTING_RPC250_WPU_ECC) 494 /*Sets pull-ups when override enabled. Each bit corresponding to an IO in 495 corresponding IOG lane, starting from p_pair0 to n_pair5. */ 496 #define LIBERO_SETTING_RPC250_WPU_ECC 0x0000007FUL 497 /* MSS_DDR_DQ32 [0:1] RW value= 0x1 */ 498 /* MSS_DDR_DQ33 [1:1] RW value= 0x1 */ 499 /* MSS_DDR_DQ34 [2:1] RW value= 0x1 */ 500 /* MSS_DDR_DQ35 [3:1] RW value= 0x1 */ 501 /* MSS_DDR_DQS_P4 [4:1] RW value= 0x1 */ 502 /* MSS_DDR_DQS_N4 [5:1] RW value= 0x1 */ 503 /* MSS_DDR_DM4 [6:1] RW value= 0x1 */ 504 #endif 505 506 #ifdef __cplusplus 507 } 508 #endif 509 510 511 #endif /* #ifdef HW_DDR_IO_BANK_H_ */ 512 513
