1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * @file hw_clk_mss_pll.h 7 * @author Microchip-FPGA Embedded Systems Solutions 8 * 9 * 10 * Note 1: This file should not be edited. If you need to modify a parameter 11 * without going through regenerating using the MSS Configurator Libero flow 12 * or editing the associated xml file 13 * the following method is recommended: 14 15 * 1. edit the following file 16 * boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h 17 18 * 2. define the value you want to override there. 19 * (Note: There is a commented example in the platform directory) 20 21 * Note 2: The definition in mss_sw_config.h takes precedence, as 22 * mss_sw_config.h is included prior to the generated header files located in 23 * boards/your_board/fpga_design_config 24 * 25 */ 26 27 #ifndef HW_CLK_MSS_PLL_H_ 28 #define HW_CLK_MSS_PLL_H_ 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if !defined (LIBERO_SETTING_MSS_PLL_CTRL) 36 /*PLL control register */ 37 #define LIBERO_SETTING_MSS_PLL_CTRL 0x01000037UL 38 /* REG_POWERDOWN_B [0:1] RW value= 0x1 */ 39 /* REG_RFDIV_EN [1:1] RW value= 0x1 */ 40 /* REG_DIVQ0_EN [2:1] RW value= 0x1 */ 41 /* REG_DIVQ1_EN [3:1] RW value= 0x0 */ 42 /* REG_DIVQ2_EN [4:1] RW value= 0x1 */ 43 /* REG_DIVQ3_EN [5:1] RW value= 0x1 */ 44 /* REG_RFCLK_SEL [6:1] RW value= 0x0 */ 45 /* RESETONLOCK [7:1] RW value= 0x0 */ 46 /* BYPCK_SEL [8:4] RW value= 0x0 */ 47 /* REG_BYPASS_GO_B [12:1] RW value= 0x0 */ 48 /* RESERVE10 [13:3] RSVD */ 49 /* REG_BYPASSPRE [16:4] RW value= 0x0 */ 50 /* REG_BYPASSPOST [20:4] RW value= 0x0 */ 51 /* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */ 52 /* LOCK [25:1] RO */ 53 /* LOCK_INT_EN [26:1] RW value= 0x0 */ 54 /* UNLOCK_INT_EN [27:1] RW value= 0x0 */ 55 /* LOCK_INT [28:1] SW1C */ 56 /* UNLOCK_INT [29:1] SW1C */ 57 /* RESERVE11 [30:1] RSVD */ 58 /* LOCK_B [31:1] RO */ 59 #endif 60 #if !defined (LIBERO_SETTING_MSS_PLL_REF_FB) 61 /*PLL reference and feedback registers */ 62 #define LIBERO_SETTING_MSS_PLL_REF_FB 0x00000500UL 63 /* FSE_B [0:1] RW value= 0x0 */ 64 /* FBCK_SEL [1:2] RW value= 0x0 */ 65 /* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */ 66 /* RESERVE12 [4:4] RSVD */ 67 /* RFDIV [8:6] RW value= 0x5 */ 68 /* RESERVE13 [14:2] RSVD */ 69 /* RESERVE14 [16:12] RSVD */ 70 /* RESERVE15 [28:4] RSVD */ 71 #endif 72 #if !defined (LIBERO_SETTING_MSS_PLL_FRACN) 73 /*PLL fractional register */ 74 #define LIBERO_SETTING_MSS_PLL_FRACN 0x00000000UL 75 /* FRACN_EN [0:1] RW value= 0x0 */ 76 /* FRACN_DAC_EN [1:1] RW value= 0x0 */ 77 /* RESERVE16 [2:6] RSVD */ 78 /* RESERVE17 [8:24] RSVD */ 79 #endif 80 #if !defined (LIBERO_SETTING_MSS_PLL_DIV_0_1) 81 /*PLL 0/1 division registers */ 82 #define LIBERO_SETTING_MSS_PLL_DIV_0_1 0x01000200UL 83 /* VCO0PH_SEL [0:3] RO */ 84 /* DIV0_START [3:3] RW value= 0x0 */ 85 /* RESERVE18 [6:2] RSVD */ 86 /* POST0DIV [8:7] RW value= 0x2 */ 87 /* RESERVE19 [15:1] RSVD */ 88 /* VCO1PH_SEL [16:3] RO */ 89 /* DIV1_START [19:3] RW value= 0x0 */ 90 /* RESERVE20 [22:2] RSVD */ 91 /* POST1DIV [24:7] RW value= 0x1 */ 92 /* RESERVE21 [31:1] RSVD */ 93 #endif 94 #if !defined (LIBERO_SETTING_MSS_PLL_DIV_2_3) 95 /*PLL 2/3 division registers */ 96 #define LIBERO_SETTING_MSS_PLL_DIV_2_3 0x0F000600UL 97 /* VCO2PH_SEL [0:3] RO */ 98 /* DIV2_START [3:3] RW value= 0x0 */ 99 /* RESERVE22 [6:2] RSVD */ 100 /* POST2DIV [8:7] RW value= 0x6 */ 101 /* RESERVE23 [15:1] RSVD */ 102 /* VCO3PH_SEL [16:3] RO */ 103 /* DIV3_START [19:3] RW value= 0x0 */ 104 /* RESERVE24 [22:2] RSVD */ 105 /* POST3DIV [24:7] RW value= 0xF */ 106 /* CKPOST3_SEL [31:1] RW value= 0x0 */ 107 #endif 108 #if !defined (LIBERO_SETTING_MSS_PLL_CTRL2) 109 /*PLL control register */ 110 #define LIBERO_SETTING_MSS_PLL_CTRL2 0x00001020UL 111 /* BWI [0:2] RW value= 0x0 */ 112 /* BWP [2:2] RW value= 0x0 */ 113 /* IREF_EN [4:1] RW value= 0x0 */ 114 /* IREF_TOGGLE [5:1] RW value= 0x1 */ 115 /* RESERVE25 [6:3] RSVD */ 116 /* LOCKCNT [9:4] RW value= 0x8 */ 117 /* RESERVE26 [13:4] RSVD */ 118 /* ATEST_EN [17:1] RW value= 0x0 */ 119 /* ATEST_SEL [18:3] RW value= 0x0 */ 120 /* RESERVE27 [21:11] RSVD */ 121 #endif 122 #if !defined (LIBERO_SETTING_MSS_PLL_CAL) 123 /*PLL calibration register */ 124 #define LIBERO_SETTING_MSS_PLL_CAL 0x00000D06UL 125 /* DSKEWCALCNT [0:3] RW value= 0x6 */ 126 /* DSKEWCAL_EN [3:1] RW value= 0x0 */ 127 /* DSKEWCALBYP [4:1] RW value= 0x0 */ 128 /* RESERVE28 [5:3] RSVD */ 129 /* DSKEWCALIN [8:7] RW value= 0xd */ 130 /* RESERVE29 [15:1] RSVD */ 131 /* DSKEWCALOUT [16:7] RO */ 132 /* RESERVE30 [23:9] RSVD */ 133 #endif 134 #if !defined (LIBERO_SETTING_MSS_PLL_PHADJ) 135 /*PLL phase registers */ 136 #define LIBERO_SETTING_MSS_PLL_PHADJ 0x00004003UL 137 /* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */ 138 /* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */ 139 /* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */ 140 /* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */ 141 /* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */ 142 /* REG_OUT3_PHSINIT [11:3] RW value= 0x8 */ 143 /* REG_LOADPHS_B [14:1] RW value= 0x0 */ 144 /* RESERVE31 [15:17] RSVD */ 145 #endif 146 #if !defined (LIBERO_SETTING_MSS_SSCG_REG_0) 147 /*SSCG registers 0 */ 148 #define LIBERO_SETTING_MSS_SSCG_REG_0 0x00000000UL 149 /* DIVVAL [0:6] RW value= 0x0 */ 150 /* FRACIN [6:24] RW value= 0x0 */ 151 /* RESERVE00 [30:2] RSVD */ 152 #endif 153 #if !defined (LIBERO_SETTING_MSS_SSCG_REG_1) 154 /*SSCG registers 1 */ 155 #define LIBERO_SETTING_MSS_SSCG_REG_1 0x00000000UL 156 /* DOWNSPREAD [0:1] RW value= 0x0 */ 157 /* SSMD [1:5] RW value= 0x0 */ 158 /* FRACMOD [6:24] RO */ 159 /* RESERVE01 [30:2] RSVD */ 160 #endif 161 #if !defined (LIBERO_SETTING_MSS_SSCG_REG_2) 162 /*SSCG registers 2 */ 163 #define LIBERO_SETTING_MSS_SSCG_REG_2 0x000000C0UL 164 /* INTIN [0:12] RW value= 0xC0 */ 165 /* INTMOD [12:12] RO */ 166 /* RESERVE02 [24:8] RSVD */ 167 #endif 168 #if !defined (LIBERO_SETTING_MSS_SSCG_REG_3) 169 /*SSCG registers 3 */ 170 #define LIBERO_SETTING_MSS_SSCG_REG_3 0x00000001UL 171 /* SSE_B [0:1] RW value= 0x1 */ 172 /* SEL_EXTWAVE [1:2] RW value= 0x0 */ 173 /* EXT_MAXADDR [3:8] RW value= 0x0 */ 174 /* TBLADDR [11:8] RO */ 175 /* RANDOM_FILTER [19:1] RW value= 0x0 */ 176 /* RANDOM_SEL [20:2] RW value= 0x0 */ 177 /* RESERVE03 [22:1] RSVD */ 178 /* RESERVE04 [23:9] RSVD */ 179 #endif 180 181 #ifdef __cplusplus 182 } 183 #endif 184 185 186 #endif /* #ifdef HW_CLK_MSS_PLL_H_ */ 187 188
